reg 244 arch/i386/i386/freebsd_machdep.c netbsd_to_freebsd_ptrace_regs(struct reg *nregs, struct fpreg *nfpregs,
reg 303 arch/i386/i386/freebsd_machdep.c struct reg *nregs, struct fpreg *nfpregs)
reg 53 arch/i386/i386/k6_mem.c #define k6_reg_get(reg, addr, mask, wc, uc) do { \
reg 54 arch/i386/i386/k6_mem.c addr = (reg) & 0xfffe0000; \
reg 55 arch/i386/i386/k6_mem.c mask = ((reg) & 0x1fffc) >> 2; \
reg 56 arch/i386/i386/k6_mem.c wc = ((reg) & 0x2) >> 1; \
reg 57 arch/i386/i386/k6_mem.c uc = (reg) & 0x1; \
reg 98 arch/i386/i386/k6_mem.c u_int64_t reg;
reg 111 arch/i386/i386/k6_mem.c reg = rdmsr(UWCCR);
reg 113 arch/i386/i386/k6_mem.c u_int32_t one = (reg & (0xffffffff << (32 * d))) >> (32 * d);
reg 130 arch/i386/i386/k6_mem.c u_int64_t reg;
reg 168 arch/i386/i386/k6_mem.c reg = rdmsr(UWCCR);
reg 169 arch/i386/i386/k6_mem.c reg &= ~(0xffffffff << (32 * d));
reg 170 arch/i386/i386/k6_mem.c reg |= mtrr << (32 * d);
reg 171 arch/i386/i386/k6_mem.c wrmsr(UWCCR, reg);
reg 346 arch/i386/i386/machdep.c cyrix_read_reg(u_char reg)
reg 348 arch/i386/i386/machdep.c outb(0x22, reg);
reg 353 arch/i386/i386/machdep.c cyrix_write_reg(u_char reg, u_char data)
reg 355 arch/i386/i386/machdep.c outb(0x22, reg);
reg 85 arch/i386/i386/mpbios_intr_fixup.c pcireg_t reg;
reg 90 arch/i386/i386/mpbios_intr_fixup.c reg = pci_conf_read(pc, tag, NFORCE4_PNPIRQ2);
reg 91 arch/i386/i386/mpbios_intr_fixup.c pin = (reg & NFORCE4_USB2_MASK) >> NFORCE4_USB2_SHIFT;
reg 94 arch/i386/i386/mpbios_intr_fixup.c pin = (reg & NFORCE4_SATA1_MASK) >> NFORCE4_SATA1_SHIFT;
reg 97 arch/i386/i386/mpbios_intr_fixup.c pin = (reg & NFORCE4_SATA2_MASK) >> NFORCE4_SATA2_SHIFT;
reg 101 arch/i386/i386/mpbios_intr_fixup.c reg = pci_conf_read(pc, tag, NFORCE4_PNPIRQ3);
reg 102 arch/i386/i386/mpbios_intr_fixup.c pin = (reg & NFORCE4_USB1_MASK) >> NFORCE4_USB1_SHIFT;
reg 105 arch/i386/i386/mpbios_intr_fixup.c pin = (reg & NFORCE4_LAN_MASK) >> NFORCE4_LAN_SHIFT;
reg 117 arch/i386/i386/mpbios_intr_fixup.c pcireg_t reg;
reg 122 arch/i386/i386/mpbios_intr_fixup.c reg = pci_conf_read(pc, tag, NFORCE4_PNPIRQ2);
reg 123 arch/i386/i386/mpbios_intr_fixup.c pin = (reg & NFORCE4_SATA1_MASK) >> NFORCE4_SATA1_SHIFT;
reg 126 arch/i386/i386/mpbios_intr_fixup.c pin = (reg & NFORCE4_SATA2_MASK) >> NFORCE4_SATA2_SHIFT;
reg 48 arch/i386/i386/p4tcc.c u_short reg;
reg 82 arch/i386/i386/p4tcc.c tcc[TCC_LEVELS - 1].reg = 2;
reg 89 arch/i386/i386/p4tcc.c tcc[TCC_LEVELS - 1].reg = 3;
reg 90 arch/i386/i386/p4tcc.c tcc[TCC_LEVELS - 2].reg = 3;
reg 123 arch/i386/i386/p4tcc.c if (tcc[i].reg != 0) /* enable it */
reg 124 arch/i386/i386/p4tcc.c msreg |= tcc[i].reg << 1 | 1 << 4;
reg 153 arch/i386/i386/process_machdep.c process_read_regs(struct proc *p, struct reg *regs)
reg 265 arch/i386/i386/process_machdep.c process_write_regs(struct proc *p, struct reg *regs)
reg 414 arch/i386/i386/vm86.c #define DOVREG(reg) tf->tf_vm86_##reg = (u_short) vm86s.regs.vmsc.sc_##reg
reg 415 arch/i386/i386/vm86.c #define DOREG(reg) tf->tf_##reg = (u_short) vm86s.regs.vmsc.sc_##reg
reg 167 arch/i386/i386/vm_machdep.c struct reg intreg;
reg 51 arch/i386/include/i82489var.h i82489_readreg(reg)
reg 52 arch/i386/include/i82489var.h int reg;
reg 55 arch/i386/include/i82489var.h + reg));
reg 59 arch/i386/include/i82489var.h i82489_writereg(reg, val)
reg 60 arch/i386/include/i82489var.h int reg;
reg 63 arch/i386/include/i82489var.h *((volatile u_int32_t *)(((volatile u_int8_t *)local_apic) + reg)) =
reg 72 arch/i386/include/reg.h struct reg {
reg 146 arch/i386/isa/clock.c mc146818_read(void *sc, u_int reg)
reg 152 arch/i386/isa/clock.c outb(IO_RTC, reg);
reg 161 arch/i386/isa/clock.c mc146818_write(void *sc, u_int reg, u_int datum)
reg 166 arch/i386/isa/clock.c outb(IO_RTC, reg);
reg 157 arch/i386/pci/ali1543.c #define ALI1543_INTR_PIRQ_IRQ(reg, clink) \
reg 158 arch/i386/pci/ali1543.c (((reg) >> ((clink)*4)) & 0x0f)
reg 159 arch/i386/pci/ali1543.c #define ALI1543_PIRQ(reg, clink) \
reg 160 arch/i386/pci/ali1543.c ali1543_intr_shuffle_get[ALI1543_INTR_PIRQ_IRQ((reg), (clink))]
reg 193 arch/i386/pci/ali1543.c pcireg_t reg;
reg 199 arch/i386/pci/ali1543.c reg = pci_conf_read(ph->ph_pc, ph->ph_tag, ALI1543_INTR_CFG_REG);
reg 201 arch/i386/pci/ali1543.c printf("ali1543: PIRQ reg 0x%08x\n", reg); /* XXX debug */
reg 203 arch/i386/pci/ali1543.c val = ALI1543_PIRQ(reg, clink);
reg 215 arch/i386/pci/ali1543.c pcireg_t reg;
reg 220 arch/i386/pci/ali1543.c reg = pci_conf_read(ph->ph_pc, ph->ph_tag, ALI1543_INTR_CFG_REG);
reg 223 arch/i386/pci/ali1543.c reg &= ~(0x0f << shift);
reg 224 arch/i386/pci/ali1543.c reg |= (ali1543_intr_shuffle_set[irq] << shift);
reg 225 arch/i386/pci/ali1543.c pci_conf_write(ph->ph_pc, ph->ph_tag, ALI1543_INTR_CFG_REG, reg);
reg 148 arch/i386/pci/amd756.c pcireg_t reg;
reg 154 arch/i386/pci/amd756.c reg = AMD756_GET_PIIRQSEL(ph);
reg 155 arch/i386/pci/amd756.c val = (reg >> (4*clink)) & 0x0f;
reg 167 arch/i386/pci/amd756.c pcireg_t reg;
reg 172 arch/i386/pci/amd756.c reg = AMD756_GET_PIIRQSEL(ph);
reg 174 arch/i386/pci/amd756.c reg &= ~(0x000f << (4*clink));
reg 175 arch/i386/pci/amd756.c reg |= irq << (4*clink);
reg 176 arch/i386/pci/amd756.c AMD756_SET_PIIRQSEL(ph, reg);
reg 186 arch/i386/pci/amd756.c pcireg_t reg;
reg 194 arch/i386/pci/amd756.c reg = AMD756_GET_EDGESEL(ph);
reg 195 arch/i386/pci/amd756.c if (reg & (1 << i))
reg 211 arch/i386/pci/amd756.c pcireg_t reg;
reg 219 arch/i386/pci/amd756.c reg = AMD756_GET_PIIRQSEL(ph);
reg 221 arch/i386/pci/amd756.c reg &= ~(1 << (4*i));
reg 223 arch/i386/pci/amd756.c reg |= 1 << (4*i);
reg 224 arch/i386/pci/amd756.c AMD756_SET_PIIRQSEL(ph, reg);
reg 133 arch/i386/pci/elan520.c int pin, reg, shift;
reg 181 arch/i386/pci/elan520.c reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16);
reg 183 arch/i386/pci/elan520.c data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg);
reg 377 arch/i386/pci/elan520.c int reg, shift;
reg 380 arch/i386/pci/elan520.c reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16);
reg 382 arch/i386/pci/elan520.c data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg);
reg 391 arch/i386/pci/elan520.c int reg, shift;
reg 394 arch/i386/pci/elan520.c reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16);
reg 396 arch/i386/pci/elan520.c data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg);
reg 402 arch/i386/pci/elan520.c bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data);
reg 409 arch/i386/pci/elan520.c int reg, shift;
reg 412 arch/i386/pci/elan520.c reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16);
reg 414 arch/i386/pci/elan520.c data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg);
reg 420 arch/i386/pci/elan520.c bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data);
reg 95 arch/i386/pci/geodesc.c pcireg_t reg;
reg 98 arch/i386/pci/geodesc.c reg = pci_conf_read(pa->pa_pc, pa->pa_tag, SC1100_F5_SCRATCHPAD);
reg 100 arch/i386/pci/geodesc.c if (reg == 0 ||
reg 101 arch/i386/pci/geodesc.c bus_space_map(sc->sc_iot, reg, 64, 0, &sc->sc_ioh)) {
reg 102 arch/i386/pci/geodesc.c printf(": unable to map registers at 0x%x\n", reg);
reg 106 arch/i386/pci/geodesc.c if (cba != reg) {
reg 107 arch/i386/pci/geodesc.c printf(": cba mismatch: cba 0x%x != reg 0x%x\n", cba, reg);
reg 156 arch/i386/pci/gscpcib.c int reg, shift;
reg 159 arch/i386/pci/gscpcib.c reg = (pin < 32 ? GSCGPIO_GPDI0 : GSCGPIO_GPDI1);
reg 161 arch/i386/pci/gscpcib.c data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg);
reg 170 arch/i386/pci/gscpcib.c int reg, shift;
reg 173 arch/i386/pci/gscpcib.c reg = (pin < 32 ? GSCGPIO_GPDO0 : GSCGPIO_GPDO1);
reg 175 arch/i386/pci/gscpcib.c data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg);
reg 181 arch/i386/pci/gscpcib.c bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data);
reg 161 arch/i386/pci/opti82c558.c pcireg_t reg;
reg 167 arch/i386/pci/opti82c558.c reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ);
reg 168 arch/i386/pci/opti82c558.c val = VIPER_PIRQ(reg, clink);
reg 179 arch/i386/pci/opti82c558.c pcireg_t reg;
reg 184 arch/i386/pci/opti82c558.c reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ);
reg 186 arch/i386/pci/opti82c558.c reg &= ~(VIPER_PIRQ_SELECT_MASK << shift);
reg 187 arch/i386/pci/opti82c558.c reg |= (viper_pirq_encode[irq] << shift);
reg 188 arch/i386/pci/opti82c558.c pci_conf_write(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ, reg);
reg 197 arch/i386/pci/opti82c558.c pcireg_t reg;
reg 205 arch/i386/pci/opti82c558.c reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ);
reg 206 arch/i386/pci/opti82c558.c if ((reg >> (VIPER_CFG_TRIGGER_SHIFT + viper_pirq_encode[irq])) & 1)
reg 219 arch/i386/pci/opti82c558.c pcireg_t reg;
reg 226 arch/i386/pci/opti82c558.c reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ);
reg 229 arch/i386/pci/opti82c558.c reg |= (1 << shift);
reg 231 arch/i386/pci/opti82c558.c reg &= ~(1 << shift);
reg 232 arch/i386/pci/opti82c558.c pci_conf_write(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ, reg);
reg 65 arch/i386/pci/opti82c558reg.h #define VIPER_PIRQ(reg, x) (((reg) >> ((x) * VIPER_PIRQ_SELECT_SHIFT)) \
reg 203 arch/i386/pci/opti82c700.c pcireg_t reg;
reg 209 arch/i386/pci/opti82c700.c reg = pci_conf_read(ph->ph_pc, ph->ph_tag, addrofs);
reg 210 arch/i386/pci/opti82c700.c val = (reg >> ofs) & FIRESTAR_CFG_PIRQ_MASK;
reg 223 arch/i386/pci/opti82c700.c pcireg_t reg;
reg 231 arch/i386/pci/opti82c700.c reg = pci_conf_read(ph->ph_pc, ph->ph_tag, addrofs);
reg 232 arch/i386/pci/opti82c700.c reg &= ~(FIRESTAR_CFG_PIRQ_MASK << ofs);
reg 233 arch/i386/pci/opti82c700.c reg |= (irq << ofs);
reg 234 arch/i386/pci/opti82c700.c pci_conf_write(ph->ph_pc, ph->ph_tag, addrofs, reg);
reg 244 arch/i386/pci/opti82c700.c pcireg_t reg;
reg 258 arch/i386/pci/opti82c700.c reg = pci_conf_read(ph->ph_pc, ph->ph_tag, addrofs);
reg 259 arch/i386/pci/opti82c700.c val = (reg >> ofs) & FIRESTAR_CFG_PIRQ_MASK;
reg 262 arch/i386/pci/opti82c700.c val = ((reg >> ofs) >> FIRESTAR_TRIGGER_SHIFT) &
reg 274 arch/i386/pci/opti82c700.c reg = pci_conf_read(ph->ph_pc, ph->ph_tag, addrofs);
reg 275 arch/i386/pci/opti82c700.c val = (reg >> ofs) & FIRESTAR_CFG_PIRQ_MASK;
reg 290 arch/i386/pci/opti82c700.c pcireg_t reg;
reg 303 arch/i386/pci/opti82c700.c reg = pci_conf_read(ph->ph_pc, ph->ph_tag, addrofs);
reg 304 arch/i386/pci/opti82c700.c val = (reg >> ofs) & FIRESTAR_CFG_PIRQ_MASK;
reg 308 arch/i386/pci/opti82c700.c reg |= (FIRESTAR_TRIGGER_MASK <<
reg 311 arch/i386/pci/opti82c700.c reg &= ~(FIRESTAR_TRIGGER_MASK <<
reg 313 arch/i386/pci/opti82c700.c pci_conf_write(ph->ph_pc, ph->ph_tag, addrofs, reg);
reg 323 arch/i386/pci/opti82c700.c reg = pci_conf_read(ph->ph_pc, ph->ph_tag, addrofs);
reg 324 arch/i386/pci/opti82c700.c val = (reg >> ofs) & FIRESTAR_CFG_PIRQ_MASK;
reg 86 arch/i386/pci/pchb.c #define PCISET_INTEL_BRIDGE_NUMBER(reg) (((reg) >> 8) & 0xff)
reg 87 arch/i386/pci/pchb.c #define PCISET_INTEL_PCI_BUS_NUMBER(reg) (((reg) >> 16) & 0xff)
reg 115 arch/i386/pci/pchb.c #define AMD64HT_LDT_SEC_BUS_NUM(reg) (((reg) >> 8) & 0xff)
reg 459 arch/i386/pci/pchb.c int reg;
reg 461 arch/i386/pci/pchb.c reg = AMD64HT_LDT0_TYPE + i * 0x20;
reg 462 arch/i386/pci/pchb.c type = pci_conf_read(pa->pa_pc, pa->pa_tag, reg);
reg 467 arch/i386/pci/pchb.c reg = AMD64HT_LDT0_BUS + i * 0x20;
reg 468 arch/i386/pci/pchb.c bus = pci_conf_read(pa->pa_pc, pa->pa_tag, reg);
reg 56 arch/i386/pci/pci_bus_fixup.c pcireg_t reg;
reg 64 arch/i386/pci/pci_bus_fixup.c reg = pci_conf_read(pc, tag, PCI_ID_REG);
reg 71 arch/i386/pci/pci_bus_fixup.c if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID)
reg 74 arch/i386/pci/pci_bus_fixup.c if (PCI_VENDOR(reg) == 0)
reg 77 arch/i386/pci/pci_bus_fixup.c qd = pci_lookup_quirkdata(PCI_VENDOR(reg), PCI_PRODUCT(reg));
reg 79 arch/i386/pci/pci_bus_fixup.c reg = pci_conf_read(pc, tag, PCI_BHLC_REG);
reg 80 arch/i386/pci/pci_bus_fixup.c if (PCI_HDRTYPE_MULTIFN(reg) ||
reg 89 arch/i386/pci/pci_bus_fixup.c reg = pci_conf_read(pc, tag, PCI_ID_REG);
reg 92 arch/i386/pci/pci_bus_fixup.c if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID)
reg 95 arch/i386/pci/pci_bus_fixup.c if (PCI_VENDOR(reg) == 0)
reg 98 arch/i386/pci/pci_bus_fixup.c reg = pci_conf_read(pc, tag, PCI_CLASS_REG);
reg 99 arch/i386/pci/pci_bus_fixup.c if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE &&
reg 100 arch/i386/pci/pci_bus_fixup.c (PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI ||
reg 101 arch/i386/pci/pci_bus_fixup.c PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) {
reg 103 arch/i386/pci/pci_bus_fixup.c reg = pci_conf_read(pc, tag, PPB_REG_BUSINFO);
reg 104 arch/i386/pci/pci_bus_fixup.c if (PPB_BUSINFO_PRIMARY(reg) != bus) {
reg 110 arch/i386/pci/pci_bus_fixup.c PPB_BUSINFO_PRIMARY(reg),
reg 111 arch/i386/pci/pci_bus_fixup.c PPB_BUSINFO_SECONDARY(reg),
reg 112 arch/i386/pci/pci_bus_fixup.c PPB_BUSINFO_SUBORDINATE(reg));
reg 116 arch/i386/pci/pci_bus_fixup.c if (PPB_BUSINFO_SECONDARY(reg) <= bus) {
reg 122 arch/i386/pci/pci_bus_fixup.c PPB_BUSINFO_PRIMARY(reg),
reg 123 arch/i386/pci/pci_bus_fixup.c PPB_BUSINFO_SECONDARY(reg),
reg 124 arch/i386/pci/pci_bus_fixup.c PPB_BUSINFO_SUBORDINATE(reg));
reg 131 arch/i386/pci/pci_bus_fixup.c PPB_BUSINFO_SECONDARY(reg));
reg 135 arch/i386/pci/pci_bus_fixup.c if (PPB_BUSINFO_SUBORDINATE(reg) < bus_sub) {
reg 141 arch/i386/pci/pci_bus_fixup.c PPB_BUSINFO_PRIMARY(reg),
reg 142 arch/i386/pci/pci_bus_fixup.c PPB_BUSINFO_SECONDARY(reg),
reg 143 arch/i386/pci/pci_bus_fixup.c PPB_BUSINFO_SUBORDINATE(reg));
reg 163 arch/i386/pci/pci_bus_fixup.c pcireg_t reg;
reg 171 arch/i386/pci/pci_bus_fixup.c reg = pci_conf_read(pc, tag, PCI_ID_REG);
reg 178 arch/i386/pci/pci_bus_fixup.c if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID)
reg 181 arch/i386/pci/pci_bus_fixup.c if (PCI_VENDOR(reg) == 0)
reg 184 arch/i386/pci/pci_bus_fixup.c qd = pci_lookup_quirkdata(PCI_VENDOR(reg), PCI_PRODUCT(reg));
reg 186 arch/i386/pci/pci_bus_fixup.c reg = pci_conf_read(pc, tag, PCI_BHLC_REG);
reg 187 arch/i386/pci/pci_bus_fixup.c if (PCI_HDRTYPE_MULTIFN(reg) ||
reg 196 arch/i386/pci/pci_bus_fixup.c reg = pci_conf_read(pc, tag, PCI_ID_REG);
reg 199 arch/i386/pci/pci_bus_fixup.c if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID)
reg 202 arch/i386/pci/pci_bus_fixup.c if (PCI_VENDOR(reg) == 0)
reg 205 arch/i386/pci/pci_bus_fixup.c reg = pci_conf_read(pc, tag, PCI_CLASS_REG);
reg 206 arch/i386/pci/pci_bus_fixup.c if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE &&
reg 207 arch/i386/pci/pci_bus_fixup.c (PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI ||
reg 208 arch/i386/pci/pci_bus_fixup.c PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) {
reg 212 arch/i386/pci/pci_bus_fixup.c reg = pci_conf_read(pc, tag, PPB_REG_BUSINFO);
reg 213 arch/i386/pci/pci_bus_fixup.c reg &= 0xff000000;
reg 214 arch/i386/pci/pci_bus_fixup.c reg |= bus | (bus_max << 8) | (0xff << 16);
reg 215 arch/i386/pci/pci_bus_fixup.c pci_conf_write(pc, tag, PPB_REG_BUSINFO, reg);
reg 221 arch/i386/pci/pci_bus_fixup.c reg &= 0xff000000;
reg 222 arch/i386/pci/pci_bus_fixup.c reg |= bus | (bus_max << 8) | (bus_sub << 16);
reg 223 arch/i386/pci/pci_bus_fixup.c pci_conf_write(pc, tag, PPB_REG_BUSINFO, reg);
reg 258 arch/i386/pci/pci_machdep.c pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
reg 264 arch/i386/pci/pci_machdep.c outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg);
reg 271 arch/i386/pci/pci_machdep.c data = inl(tag.mode2.port | reg);
reg 282 arch/i386/pci/pci_machdep.c pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
reg 287 arch/i386/pci/pci_machdep.c outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg);
reg 294 arch/i386/pci/pci_machdep.c outl(tag.mode2.port | reg, data);
reg 170 arch/i386/pci/piix.c pcireg_t reg;
reg 181 arch/i386/pci/piix.c reg = pci_conf_read(ph->ph_pc, ph->ph_tag, off);
reg 183 arch/i386/pci/piix.c if ((reg >> shift) & PIIX_CFG_PIRQ_NONE)
reg 186 arch/i386/pci/piix.c *irqp = PIIX_PIRQ(reg, clink);
reg 196 arch/i386/pci/piix.c pcireg_t reg;
reg 207 arch/i386/pci/piix.c reg = pci_conf_read(ph->ph_pc, ph->ph_tag, off);
reg 209 arch/i386/pci/piix.c reg &= ~((PIIX_CFG_PIRQ_NONE | PIIX_CFG_PIRQ_MASK) << shift);
reg 210 arch/i386/pci/piix.c reg |= irq << shift;
reg 211 arch/i386/pci/piix.c pci_conf_write(ph->ph_pc, ph->ph_tag, off, reg);
reg 49 arch/i386/pci/piixreg.h #define PIIX_PIRQ(reg, x) (((reg) >> ((x) << 3)) & 0xff)
reg 134 arch/i386/pci/sis85c503.c pcireg_t reg;
reg 139 arch/i386/pci/sis85c503.c reg = pci_conf_read(ph->ph_pc, ph->ph_tag,
reg 141 arch/i386/pci/sis85c503.c reg = SIS85C503_CFG_PIRQ_REG(reg, clink);
reg 143 arch/i386/pci/sis85c503.c if (reg & SIS85C503_CFG_PIRQ_ROUTE_DISABLE)
reg 146 arch/i386/pci/sis85c503.c *irqp = reg & SIS85C503_CFG_PIRQ_INTR_MASK;
reg 156 arch/i386/pci/sis85c503.c pcireg_t reg;
reg 161 arch/i386/pci/sis85c503.c reg = pci_conf_read(ph->ph_pc, ph->ph_tag,
reg 164 arch/i386/pci/sis85c503.c reg &= ~((SIS85C503_CFG_PIRQ_ROUTE_DISABLE |
reg 166 arch/i386/pci/sis85c503.c reg |= (irq << shift);
reg 168 arch/i386/pci/sis85c503.c reg);
reg 46 arch/i386/pci/sis85c503reg.h #define SIS85C503_CFG_PIRQ_REG(reg, regofs) \
reg 47 arch/i386/pci/sis85c503reg.h (((reg) >> SIS85C503_CFG_PIRQ_SHIFT(regofs)) & SIS85C503_CFG_PIRQ_MASK)
reg 127 arch/i386/pci/via8231.c #define VIA8231_GET_TRIGGER_CNFG(reg, pirq) \
reg 128 arch/i386/pci/via8231.c ((reg) & (1 << (3 - (clink & 3))))
reg 129 arch/i386/pci/via8231.c #define VIA8231_SET_TRIGGER_CNFG(reg, clink, cfg) \
reg 130 arch/i386/pci/via8231.c (((reg) & ~(1 << (3 - (clink & 3)))) | ((cfg) << (3 - (clink & 3))))
reg 132 arch/i386/pci/via8231.c #define VIA8231_GET_ROUTING_CNFG(reg, pirq) \
reg 133 arch/i386/pci/via8231.c (((reg) >> via8231_routing_cnfg[(pirq)].shft) & \
reg 136 arch/i386/pci/via8231.c #define VIA8231_SET_ROUTING_CNFG(reg, pirq, cfg) \
reg 137 arch/i386/pci/via8231.c (((reg) & ~(via8231_routing_cnfg[(pirq)].mask << \
reg 189 arch/i386/pci/via8231.c int reg, val;
reg 195 arch/i386/pci/via8231.c reg = VIA8231_GET_ROUTING(ph);
reg 196 arch/i386/pci/via8231.c val = VIA8231_GET_ROUTING_CNFG(reg, clink);
reg 198 arch/i386/pci/via8231.c reg = VIA8237_GET_ROUTING(ph);
reg 199 arch/i386/pci/via8231.c val = (reg >> ((clink & 3) * 4)) & 0xf;
reg 212 arch/i386/pci/via8231.c int reg;
reg 223 arch/i386/pci/via8231.c reg = VIA8231_GET_ROUTING(ph);
reg 225 arch/i386/pci/via8231.c VIA8231_SET_ROUTING_CNFG(reg, clink, irq));
reg 227 arch/i386/pci/via8231.c reg = VIA8237_GET_ROUTING(ph);
reg 228 arch/i386/pci/via8231.c VIA8237_SET_ROUTING(ph, (reg & ~(0xf << (clink & 3))) |
reg 239 arch/i386/pci/via8231.c int reg, clink, max, pciirq;
reg 248 arch/i386/pci/via8231.c reg = VIA8231_LINK_LEGAL(clink)?
reg 251 arch/i386/pci/via8231.c *triggerp = VIA8231_GET_TRIGGER_CNFG(reg, clink)?
reg 264 arch/i386/pci/via8231.c int reg, clink, max, pciirq;
reg 278 arch/i386/pci/via8231.c reg = VIA8231_LINK_LEGAL(clink)?
reg 283 arch/i386/pci/via8231.c reg = VIA8231_SET_TRIGGER_CNFG(reg, clink,
reg 287 arch/i386/pci/via8231.c reg = VIA8231_SET_TRIGGER_CNFG(reg, clink,
reg 294 arch/i386/pci/via8231.c VIA8231_SET_TRIGGER(ph, reg);
reg 296 arch/i386/pci/via8231.c VIA8237_SET_TRIGGER(ph, reg);
reg 106 arch/i386/pci/via82c586.c #define VP3_TRIGGER(reg, pirq) (((reg) >> vp3_cfg_trigger_shift[(pirq)]) & \
reg 119 arch/i386/pci/via82c586.c #define VP3_PIRQ(reg, pirq) (((reg) >> vp3_cfg_intr_shift[(pirq)]) & \
reg 126 arch/i386/pci/via82c586.c pcireg_t reg;
reg 134 arch/i386/pci/via82c586.c reg = pci_conf_read(pc, tag, VP3_CFG_KBDMISCCTRL12_REG);
reg 135 arch/i386/pci/via82c586.c reg |= VP3_CFG_MISCCTRL2_EISA4D04D1PORT_ENABLE <<
reg 137 arch/i386/pci/via82c586.c pci_conf_write(pc, tag, VP3_CFG_KBDMISCCTRL12_REG, reg);
reg 161 arch/i386/pci/via82c586.c pcireg_t reg;
reg 167 arch/i386/pci/via82c586.c reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VP3_CFG_PIRQ_REG);
reg 168 arch/i386/pci/via82c586.c val = VP3_PIRQ(reg, clink);
reg 180 arch/i386/pci/via82c586.c pcireg_t reg;
reg 185 arch/i386/pci/via82c586.c reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VP3_CFG_PIRQ_REG);
reg 188 arch/i386/pci/via82c586.c reg &= ~(VP3_CFG_INTR_MASK << shift);
reg 189 arch/i386/pci/via82c586.c reg |= (irq << shift);
reg 190 arch/i386/pci/via82c586.c pci_conf_write(ph->ph_pc, ph->ph_tag, VP3_CFG_PIRQ_REG, reg);
reg 203 arch/i386/pci/via82c586.c pcireg_t reg;
reg 212 arch/i386/pci/via82c586.c reg = pci_conf_read(ph->ph_pc, ph->ph_tag,
reg 214 arch/i386/pci/via82c586.c if (VP3_TRIGGER(reg, i) == VP3_CFG_TRIGGER_EDGE)
reg 234 arch/i386/pci/via82c586.c pcireg_t reg;
reg 242 arch/i386/pci/via82c586.c reg = pci_conf_read(ph->ph_pc, ph->ph_tag,
reg 247 arch/i386/pci/via82c586.c reg &= ~(VP3_CFG_TRIGGER_MASK << shift);
reg 249 arch/i386/pci/via82c586.c VP3_CFG_PIRQ_REG, reg);
reg 40 arch/i386/pci/via82c586reg.h #define VP3_CFG_MISCCTRL2_REG(reg) \
reg 41 arch/i386/pci/via82c586reg.h (((reg) >> VP3_CFG_MISCCTRL2_SHIFT) & VP3_CFG_MISCCTRL2_MASK)
reg 38 arch/i386/stand/libsa/debug.c struct reg reg;
reg 39 arch/i386/stand/libsa/debug.c u_int32_t *const reg_values[] = { REG_VALUES(reg) };
reg 51 arch/i386/stand/libsa/debug_md.h .globl _C_LABEL(reg)
reg 55 arch/i386/stand/libsa/debug_md.h extern struct reg reg;
reg 77 compat/freebsd/freebsd_ptrace.c struct reg regs;
reg 54 compat/freebsd/freebsd_ptrace.h void netbsd_to_freebsd_ptrace_regs(struct reg *, struct fpreg *,
reg 57 compat/freebsd/freebsd_ptrace.h struct reg *, struct fpreg *);
reg 136 dev/acpi/acpi.c int reg, idx, ival, sval;
reg 160 dev/acpi/acpi.c for (reg = 0; reg < len; reg += access_size) {
reg 164 dev/acpi/acpi.c *(uint8_t *)(pb+reg) = bus_space_read_1(
reg 165 dev/acpi/acpi.c sc->sc_iot, ioh, reg);
reg 167 dev/acpi/acpi.c reg+address, *(uint8_t *)(pb+reg));
reg 170 dev/acpi/acpi.c *(uint16_t *)(pb+reg) = bus_space_read_2(
reg 171 dev/acpi/acpi.c sc->sc_iot, ioh, reg);
reg 173 dev/acpi/acpi.c reg+address, *(uint16_t *)(pb+reg));
reg 176 dev/acpi/acpi.c *(uint32_t *)(pb+reg) = bus_space_read_4(
reg 177 dev/acpi/acpi.c sc->sc_iot, ioh, reg);
reg 183 dev/acpi/acpi.c bus_space_write_1(sc->sc_iot, ioh, reg,
reg 184 dev/acpi/acpi.c *(uint8_t *)(pb+reg));
reg 186 dev/acpi/acpi.c reg+address, *(uint8_t *)(pb+reg));
reg 189 dev/acpi/acpi.c bus_space_write_2(sc->sc_iot, ioh, reg,
reg 190 dev/acpi/acpi.c *(uint16_t *)(pb+reg));
reg 192 dev/acpi/acpi.c reg+address, *(uint16_t *)(pb+reg));
reg 195 dev/acpi/acpi.c bus_space_write_4(sc->sc_iot, ioh, reg,
reg 196 dev/acpi/acpi.c *(uint32_t *)(pb+reg));
reg 225 dev/acpi/acpi.c reg = ACPI_PCI_REG(address);
reg 226 dev/acpi/acpi.c for (idx = reg; idx < reg+len; idx++) {
reg 1384 dev/acpi/acpi.c int reg;
reg 1386 dev/acpi/acpi.c for (reg = 0; reg < ACPIREG_MAXREG; reg++) {
reg 1388 dev/acpi/acpi.c switch (reg) {
reg 1399 dev/acpi/acpi.c if (reg == ACPIREG_PM1A_EN && addr) {
reg 1414 dev/acpi/acpi.c if (reg == ACPIREG_PM1B_EN && addr) {
reg 1447 dev/acpi/acpi.c if (reg == ACPIREG_GPE0_EN && addr) {
reg 1462 dev/acpi/acpi.c if (reg == ACPIREG_GPE1_EN && addr) {
reg 1474 dev/acpi/acpi.c &sc->sc_pmregs[reg].ioh);
reg 1476 dev/acpi/acpi.c sc->sc_pmregs[reg].name = name;
reg 1477 dev/acpi/acpi.c sc->sc_pmregs[reg].size = size;
reg 1478 dev/acpi/acpi.c sc->sc_pmregs[reg].addr = addr;
reg 1485 dev/acpi/acpi.c acpi_read_pmreg(struct acpi_softc *sc, int reg, int offset)
reg 1493 dev/acpi/acpi.c switch (reg) {
reg 1508 dev/acpi/acpi.c reg = ACPIREG_GPE0_STS;
reg 1517 dev/acpi/acpi.c reg = ACPIREG_GPE0_EN;
reg 1522 dev/acpi/acpi.c if (reg >= ACPIREG_MAXREG || sc->sc_pmregs[reg].size == 0)
reg 1526 dev/acpi/acpi.c ioh = sc->sc_pmregs[reg].ioh;
reg 1527 dev/acpi/acpi.c size = sc->sc_pmregs[reg].size;
reg 1546 dev/acpi/acpi.c sc->sc_pmregs[reg].name,
reg 1547 dev/acpi/acpi.c sc->sc_pmregs[reg].addr, offset, regval);
reg 1553 dev/acpi/acpi.c acpi_write_pmreg(struct acpi_softc *sc, int reg, int offset, int regval)
reg 1560 dev/acpi/acpi.c switch (reg) {
reg 1579 dev/acpi/acpi.c reg = ACPIREG_GPE0_STS;
reg 1588 dev/acpi/acpi.c reg = ACPIREG_GPE0_EN;
reg 1594 dev/acpi/acpi.c if (reg >= ACPIREG_MAXREG)
reg 1597 dev/acpi/acpi.c ioh = sc->sc_pmregs[reg].ioh;
reg 1598 dev/acpi/acpi.c size = sc->sc_pmregs[reg].size;
reg 1616 dev/acpi/acpi.c sc->sc_pmregs[reg].name, sc->sc_pmregs[reg].addr, offset, regval);
reg 230 dev/acpi/acpiec.c int reg;
reg 240 dev/acpi/acpiec.c for (reg = 0; reg < len; reg++)
reg 241 dev/acpi/acpiec.c buffer[reg] = acpiec_read_1(sc, addr + reg);
reg 247 dev/acpi/acpiec.c int reg;
reg 256 dev/acpi/acpiec.c for (reg = 0; reg < len; reg++)
reg 257 dev/acpi/acpiec.c acpiec_write_1(sc, addr + reg, buffer[reg]);
reg 153 dev/acpi/acpiprt.c pcireg_t reg;
reg 245 dev/acpi/acpiprt.c reg = pci_conf_read(pc, tag, PCI_BHLC_REG);
reg 246 dev/acpi/acpiprt.c if (PCI_HDRTYPE_MULTIFN(reg))
reg 253 dev/acpi/acpiprt.c reg = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
reg 254 dev/acpi/acpiprt.c if (PCI_INTERRUPT_PIN(reg) == pin + 1) {
reg 255 dev/acpi/acpiprt.c reg &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT);
reg 256 dev/acpi/acpiprt.c reg |= irq << PCI_INTERRUPT_LINE_SHIFT;
reg 257 dev/acpi/acpiprt.c pci_conf_write(pc, tag, PCI_INTERRUPT_REG, reg);
reg 281 dev/acpi/acpiprt.c pcireg_t reg;
reg 301 dev/acpi/acpiprt.c reg = pci_conf_read(pc, tag, PCI_CLASS_REG);
reg 302 dev/acpi/acpiprt.c if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE &&
reg 303 dev/acpi/acpiprt.c PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI) {
reg 304 dev/acpi/acpiprt.c reg = pci_conf_read(pc, tag, PPB_REG_BUSINFO);
reg 305 dev/acpi/acpiprt.c return (PPB_BUSINFO_SECONDARY(reg));
reg 53 dev/adb/adb.h #define ADBLISTEN(dev, reg) ((((u_int8_t)dev & 0x0f) << 4) | 0x08 | reg)
reg 54 dev/adb/adb.h #define ADBTALK(dev, reg) ((((u_int8_t)dev & 0x0f) << 4) | 0x0c | reg)
reg 517 dev/atapiscsi/atapiscsi.c u_int8_t reg = CHP_READ_REG(chp, wdr_sdh);
reg 519 dev/atapiscsi/atapiscsi.c WDC_LOG_REG(chp, wdr_sdh, reg);
reg 521 dev/atapiscsi/atapiscsi.c return ((reg & 0x10) == (drive << 4));
reg 156 dev/cardbus/cardbus.c int reg;
reg 188 dev/cardbus/cardbus.c reg = CARDBUS_ROM_REG;
reg 192 dev/cardbus/cardbus.c reg = CARDBUS_BASE0_REG + (cardbus_space - 1) * 4;
reg 199 dev/cardbus/cardbus.c cardbus_conf_write(cc, cf, tag, reg, 0);
reg 200 dev/cardbus/cardbus.c if (Cardbus_mapreg_map(ca->ca_ct, reg,
reg 216 dev/cardbus/cardbus.c exrom = cardbus_conf_read(cc, cf, tag, reg);
reg 217 dev/cardbus/cardbus.c cardbus_conf_write(cc, cf, tag, reg, exrom | 1);
reg 246 dev/cardbus/cardbus.c exrom = cardbus_conf_read(cc, cf, tag, reg);
reg 247 dev/cardbus/cardbus.c cardbus_conf_write(cc, cf, tag, reg, exrom & ~1);
reg 264 dev/cardbus/cardbus.c cardbus_conf_write(cc, cf, tag, reg, 0);
reg 266 dev/cardbus/cardbus.c Cardbus_mapreg_unmap(ca->ca_ct, reg, bar_tag, bar_memh,
reg 778 dev/cardbus/cardbus.c cardbusreg_t reg;
reg 781 dev/cardbus/cardbus.c reg = cardbus_conf_read(cc, cf, tag, PCI_COMMAND_STATUS_REG);
reg 782 dev/cardbus/cardbus.c if (!(reg & PCI_STATUS_CAPLIST_SUPPORT))
reg 792 dev/cardbus/cardbus.c reg = cardbus_conf_read(cc, cf, tag, ofs);
reg 793 dev/cardbus/cardbus.c if (PCI_CAPLIST_CAP(reg) == capid) {
reg 797 dev/cardbus/cardbus.c *value = reg;
reg 800 dev/cardbus/cardbus.c ofs = PCI_CAPLIST_NEXT(reg);
reg 69 dev/cardbus/cardbus_map.c cardbustag_t tag, int reg, pcireg_t *typep)
reg 75 dev/cardbus/cardbus_map.c address = cardbus_conf_read(cc, cf, tag, reg);
reg 76 dev/cardbus/cardbus_map.c cardbus_conf_write(cc, cf, tag, reg, 0xffffffff);
reg 77 dev/cardbus/cardbus_map.c mask = cardbus_conf_read(cc, cf, tag, reg);
reg 78 dev/cardbus/cardbus_map.c cardbus_conf_write(cc, cf, tag, reg, address);
reg 98 dev/cardbus/cardbus_map.c cardbustag_t tag, int reg, cardbusreg_t type, bus_addr_t *basep,
reg 105 dev/cardbus/cardbus_map.c if (reg == CARDBUS_ROM_REG)
reg 108 dev/cardbus/cardbus_map.c if (reg < PCI_MAPREG_START || reg >= PCI_MAPREG_END || (reg & 3)) {
reg 123 dev/cardbus/cardbus_map.c address = cardbus_conf_read(cc, cf, tag, reg);
reg 124 dev/cardbus/cardbus_map.c cardbus_conf_write(cc, cf, tag, reg, 0xffffffff);
reg 125 dev/cardbus/cardbus_map.c mask = cardbus_conf_read(cc, cf, tag, reg);
reg 126 dev/cardbus/cardbus_map.c cardbus_conf_write(cc, cf, tag, reg, address);
reg 158 dev/cardbus/cardbus_map.c cardbustag_t tag, int reg, cardbusreg_t type, bus_addr_t *basep,
reg 164 dev/cardbus/cardbus_map.c if (reg != CARDBUS_ROM_REG &&
reg 165 dev/cardbus/cardbus_map.c (reg < PCI_MAPREG_START || reg >= PCI_MAPREG_END || (reg & 3))) {
reg 180 dev/cardbus/cardbus_map.c address = cardbus_conf_read(cc, cf, tag, reg);
reg 181 dev/cardbus/cardbus_map.c cardbus_conf_write(cc, cf, tag, reg, 0xffffffff);
reg 182 dev/cardbus/cardbus_map.c mask = cardbus_conf_read(cc, cf, tag, reg);
reg 183 dev/cardbus/cardbus_map.c cardbus_conf_write(cc, cf, tag, reg, address);
reg 186 dev/cardbus/cardbus_map.c if (reg != CARDBUS_ROM_REG) {
reg 246 dev/cardbus/cardbus_map.c cardbus_mapreg_map(struct cardbus_softc *sc, int func, int reg,
reg 267 dev/cardbus/cardbus_map.c if (cardbus_io_find(cc, cf, tag, reg, type, &base, &size,
reg 273 dev/cardbus/cardbus_map.c if (cardbus_mem_find(cc, cf, tag, reg, type, &base, &size,
reg 288 dev/cardbus/cardbus_map.c cardbus_conf_write(cc, cf, tag, reg, base);
reg 319 dev/cardbus/cardbus_map.c cardbus_mapreg_unmap(struct cardbus_softc *sc, int func, int reg,
reg 341 dev/cardbus/cardbus_map.c cardbus_conf_write(cc, cf, cardbustag, reg, 0);
reg 421 dev/cardbus/cardbusvar.h #define Cardbus_mapreg_map(ct, reg, type, busflags, tagp, handlep, basep, sizep) \
reg 423 dev/cardbus/cardbusvar.h (reg), (type), (busflags), (tagp), (handlep), (basep), (sizep))
reg 424 dev/cardbus/cardbusvar.h #define Cardbus_mapreg_unmap(ct, reg, tag, handle, size)\
reg 426 dev/cardbus/cardbusvar.h (reg), (tag), (handle), (size))
reg 120 dev/cardbus/com_cardbus.c cardbusreg_t reg;
reg 189 dev/cardbus/com_cardbus.c csc->cc_reg = cp->reg;
reg 309 dev/cardbus/com_cardbus.c cardbusreg_t reg;
reg 318 dev/cardbus/com_cardbus.c reg = cardbus_conf_read(cc, cf, csc->cc_tag, CARDBUS_COMMAND_STATUS_REG);
reg 319 dev/cardbus/com_cardbus.c reg &= ~(CARDBUS_COMMAND_IO_ENABLE | CARDBUS_COMMAND_MEM_ENABLE);
reg 320 dev/cardbus/com_cardbus.c reg |= csc->cc_csr;
reg 321 dev/cardbus/com_cardbus.c cardbus_conf_write(cc, cf, csc->cc_tag, CARDBUS_COMMAND_STATUS_REG, reg);
reg 327 dev/cardbus/com_cardbus.c reg = cardbus_conf_read(cc, cf, csc->cc_tag, CARDBUS_BHLC_REG);
reg 328 dev/cardbus/com_cardbus.c if (CARDBUS_LATTIMER(reg) < 0x20) {
reg 329 dev/cardbus/com_cardbus.c reg &= ~(CARDBUS_LATTIMER_MASK << CARDBUS_LATTIMER_SHIFT);
reg 330 dev/cardbus/com_cardbus.c reg |= (0x20 << CARDBUS_LATTIMER_SHIFT);
reg 331 dev/cardbus/com_cardbus.c cardbus_conf_write(cc, cf, csc->cc_tag, CARDBUS_BHLC_REG, reg);
reg 275 dev/cardbus/if_acx_cardbus.c pcireg_t reg;
reg 295 dev/cardbus/if_acx_cardbus.c reg = cardbus_conf_read(cc, cf, csc->sc_tag,
reg 297 dev/cardbus/if_acx_cardbus.c reg |= CARDBUS_COMMAND_MASTER_ENABLE | CARDBUS_COMMAND_MEM_ENABLE;
reg 300 dev/cardbus/if_acx_cardbus.c reg |= CARDBUS_COMMAND_IO_ENABLE;
reg 303 dev/cardbus/if_acx_cardbus.c reg);
reg 286 dev/cardbus/if_ath_cardbus.c pcireg_t reg;
reg 302 dev/cardbus/if_ath_cardbus.c reg = cardbus_conf_read(cc, cf, csc->sc_tag,
reg 304 dev/cardbus/if_ath_cardbus.c reg |= CARDBUS_COMMAND_MASTER_ENABLE | CARDBUS_COMMAND_MEM_ENABLE;
reg 306 dev/cardbus/if_ath_cardbus.c reg);
reg 312 dev/cardbus/if_ath_cardbus.c reg = cardbus_conf_read(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG);
reg 313 dev/cardbus/if_ath_cardbus.c if (CARDBUS_LATTIMER(reg) < 0x20) {
reg 314 dev/cardbus/if_ath_cardbus.c reg &= ~(CARDBUS_LATTIMER_MASK << CARDBUS_LATTIMER_SHIFT);
reg 315 dev/cardbus/if_ath_cardbus.c reg |= (0x20 << CARDBUS_LATTIMER_SHIFT);
reg 316 dev/cardbus/if_ath_cardbus.c cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG, reg);
reg 333 dev/cardbus/if_atw_cardbus.c pcireg_t reg;
reg 349 dev/cardbus/if_atw_cardbus.c reg = cardbus_conf_read(cc, cf, csc->sc_tag,
reg 351 dev/cardbus/if_atw_cardbus.c reg &= ~(CARDBUS_COMMAND_IO_ENABLE|CARDBUS_COMMAND_MEM_ENABLE);
reg 352 dev/cardbus/if_atw_cardbus.c reg |= csc->sc_csr;
reg 354 dev/cardbus/if_atw_cardbus.c reg);
reg 360 dev/cardbus/if_atw_cardbus.c reg = cardbus_conf_read(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG);
reg 361 dev/cardbus/if_atw_cardbus.c if (CARDBUS_LATTIMER(reg) < 0x20) {
reg 362 dev/cardbus/if_atw_cardbus.c reg &= ~(CARDBUS_LATTIMER_MASK << CARDBUS_LATTIMER_SHIFT);
reg 363 dev/cardbus/if_atw_cardbus.c reg |= (0x20 << CARDBUS_LATTIMER_SHIFT);
reg 364 dev/cardbus/if_atw_cardbus.c cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG, reg);
reg 100 dev/cardbus/if_dc_cardbus.c cardbusreg_t reg;
reg 190 dev/cardbus/if_dc_cardbus.c reg = cardbus_conf_read(cc, cf, ca->ca_tag, PCI_BHLC_REG);
reg 191 dev/cardbus/if_dc_cardbus.c if (PCI_LATTIMER(reg) < 0x20) {
reg 192 dev/cardbus/if_dc_cardbus.c reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
reg 193 dev/cardbus/if_dc_cardbus.c reg |= (0x20 << PCI_LATTIMER_SHIFT);
reg 194 dev/cardbus/if_dc_cardbus.c cardbus_conf_write(cc, cf, ca->ca_tag, PCI_BHLC_REG, reg);
reg 268 dev/cardbus/if_dc_cardbus.c cardbusreg_t reg;
reg 272 dev/cardbus/if_dc_cardbus.c reg = cardbus_conf_read(cc, cf, csc->sc_tag, PCI_CFDA);
reg 273 dev/cardbus/if_dc_cardbus.c if (reg | (DC_CFDA_SUSPEND|DC_CFDA_STANDBY)) {
reg 275 dev/cardbus/if_dc_cardbus.c reg & ~(DC_CFDA_SUSPEND|DC_CFDA_STANDBY));
reg 291 dev/cardbus/if_dc_cardbus.c reg = cardbus_conf_read(cc, cf, csc->sc_tag, PCI_COMMAND_STATUS_REG);
reg 292 dev/cardbus/if_dc_cardbus.c reg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
reg 294 dev/cardbus/if_dc_cardbus.c cardbus_conf_write(cc, cf, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg);
reg 295 dev/cardbus/if_dc_cardbus.c reg = cardbus_conf_read(cc, cf, csc->sc_tag, PCI_COMMAND_STATUS_REG);
reg 263 dev/cardbus/if_fxp_cardbus.c int rv, reg;
reg 281 dev/cardbus/if_fxp_cardbus.c reg = CARDBUS_BASE0_REG;
reg 283 dev/cardbus/if_fxp_cardbus.c reg = CARDBUS_BASE1_REG;
reg 284 dev/cardbus/if_fxp_cardbus.c Cardbus_mapreg_unmap(ct, reg, sc->sc_st, sc->sc_sh, csc->size);
reg 176 dev/cardbus/if_malo_cardbus.c pcireg_t reg;
reg 189 dev/cardbus/if_malo_cardbus.c reg = cardbus_conf_read(cc, cf, csc->sc_tag,
reg 191 dev/cardbus/if_malo_cardbus.c reg |= CARDBUS_COMMAND_MASTER_ENABLE | CARDBUS_COMMAND_MEM_ENABLE;
reg 193 dev/cardbus/if_malo_cardbus.c reg);
reg 232 dev/cardbus/if_pgt_cardbus.c pcireg_t reg;
reg 243 dev/cardbus/if_pgt_cardbus.c reg = cardbus_conf_read(cc, cf, csc->sc_tag,
reg 245 dev/cardbus/if_pgt_cardbus.c reg |= CARDBUS_COMMAND_MASTER_ENABLE | CARDBUS_COMMAND_MEM_ENABLE;
reg 247 dev/cardbus/if_pgt_cardbus.c reg);
reg 253 dev/cardbus/if_ral_cardbus.c pcireg_t reg;
reg 264 dev/cardbus/if_ral_cardbus.c reg = cardbus_conf_read(cc, cf, csc->sc_tag,
reg 266 dev/cardbus/if_ral_cardbus.c reg |= CARDBUS_COMMAND_MASTER_ENABLE | CARDBUS_COMMAND_MEM_ENABLE;
reg 268 dev/cardbus/if_ral_cardbus.c reg);
reg 182 dev/cardbus/if_re_cardbus.c pcireg_t reg, command;
reg 222 dev/cardbus/if_re_cardbus.c reg = cardbus_conf_read(cc, cf, csc->sc_tag, CARDBUS_COMMAND_STATUS_REG);
reg 223 dev/cardbus/if_re_cardbus.c reg &= ~(CARDBUS_COMMAND_IO_ENABLE|CARDBUS_COMMAND_MEM_ENABLE);
reg 224 dev/cardbus/if_re_cardbus.c reg |= csc->sc_csr;
reg 225 dev/cardbus/if_re_cardbus.c cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_COMMAND_STATUS_REG, reg);
reg 228 dev/cardbus/if_re_cardbus.c reg = cardbus_conf_read(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG);
reg 229 dev/cardbus/if_re_cardbus.c if (CARDBUS_LATTIMER(reg) < 0x20) {
reg 230 dev/cardbus/if_re_cardbus.c reg &= ~(CARDBUS_LATTIMER_MASK << CARDBUS_LATTIMER_SHIFT);
reg 231 dev/cardbus/if_re_cardbus.c reg |= (0x20 << CARDBUS_LATTIMER_SHIFT);
reg 232 dev/cardbus/if_re_cardbus.c cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG, reg);
reg 285 dev/cardbus/if_rl_cardbus.c pcireg_t reg, command;
reg 332 dev/cardbus/if_rl_cardbus.c reg = cardbus_conf_read(cc, cf, csc->sc_tag,
reg 334 dev/cardbus/if_rl_cardbus.c reg &= ~(CARDBUS_COMMAND_IO_ENABLE|CARDBUS_COMMAND_MEM_ENABLE);
reg 335 dev/cardbus/if_rl_cardbus.c reg |= csc->sc_csr;
reg 337 dev/cardbus/if_rl_cardbus.c CARDBUS_COMMAND_STATUS_REG, reg);
reg 343 dev/cardbus/if_rl_cardbus.c reg = cardbus_conf_read(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG);
reg 344 dev/cardbus/if_rl_cardbus.c if (CARDBUS_LATTIMER(reg) < 0x20) {
reg 345 dev/cardbus/if_rl_cardbus.c reg &= ~(CARDBUS_LATTIMER_MASK << CARDBUS_LATTIMER_SHIFT);
reg 346 dev/cardbus/if_rl_cardbus.c reg |= (0x20 << CARDBUS_LATTIMER_SHIFT);
reg 347 dev/cardbus/if_rl_cardbus.c cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG, reg);
reg 187 dev/cardbus/if_rtw_cardbus.c u_int32_t reg;
reg 189 dev/cardbus/if_rtw_cardbus.c reg = RTW_READ(regs, RTW_CONFIG3);
reg 191 dev/cardbus/if_rtw_cardbus.c RTW_WRITE(regs, RTW_CONFIG3, reg | RTW_CONFIG3_FUNCREGEN);
reg 193 dev/cardbus/if_rtw_cardbus.c RTW_WRITE(regs, RTW_CONFIG3, reg & ~RTW_CONFIG3_FUNCREGEN);
reg 399 dev/cardbus/if_rtw_cardbus.c pcireg_t reg;
reg 404 dev/cardbus/if_rtw_cardbus.c reg = cardbus_conf_read(cc, cf, csc->sc_tag, pmreg + 4) & 0x03;
reg 406 dev/cardbus/if_rtw_cardbus.c if (reg == 3) {
reg 416 dev/cardbus/if_rtw_cardbus.c if (reg != 0) {
reg 418 dev/cardbus/if_rtw_cardbus.c sc->sc_dev.dv_xname, reg);
reg 433 dev/cardbus/if_rtw_cardbus.c reg = cardbus_conf_read(cc, cf, csc->sc_tag,
reg 435 dev/cardbus/if_rtw_cardbus.c reg &= ~(CARDBUS_COMMAND_IO_ENABLE|CARDBUS_COMMAND_MEM_ENABLE);
reg 436 dev/cardbus/if_rtw_cardbus.c reg |= csc->sc_csr;
reg 438 dev/cardbus/if_rtw_cardbus.c reg);
reg 444 dev/cardbus/if_rtw_cardbus.c reg = cardbus_conf_read(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG);
reg 445 dev/cardbus/if_rtw_cardbus.c if (CARDBUS_LATTIMER(reg) < 0x20) {
reg 446 dev/cardbus/if_rtw_cardbus.c reg &= ~(CARDBUS_LATTIMER_MASK << CARDBUS_LATTIMER_SHIFT);
reg 447 dev/cardbus/if_rtw_cardbus.c reg |= (0x20 << CARDBUS_LATTIMER_SHIFT);
reg 448 dev/cardbus/if_rtw_cardbus.c cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG, reg);
reg 62 dev/cardbus/puc_cardbus.c cardbusreg_t bhlc, reg;
reg 73 dev/cardbus/puc_cardbus.c reg = cardbus_conf_read(cc, cf, ca->ca_tag, PCI_SUBSYS_ID_REG);
reg 75 dev/cardbus/puc_cardbus.c PCI_PRODUCT(ca->ca_id), PCI_VENDOR(reg), PCI_PRODUCT(reg)))
reg 91 dev/cardbus/puc_cardbus.c cardbusreg_t reg;
reg 98 dev/cardbus/puc_cardbus.c reg = cardbus_conf_read(cc, cf, ca->ca_tag, PCI_SUBSYS_ID_REG);
reg 100 dev/cardbus/puc_cardbus.c PCI_PRODUCT(ca->ca_id), PCI_VENDOR(reg), PCI_PRODUCT(reg));
reg 125 dev/cardbus/puc_cardbus.c if (cardbus_get_capability(cc, cf, ca->ca_tag, PCI_CAP_PWRMGMT, ®,
reg 127 dev/cardbus/puc_cardbus.c reg = cardbus_conf_read(cc, cf, ca->ca_tag, reg + 4) & 3;
reg 128 dev/cardbus/puc_cardbus.c if (reg) {
reg 130 dev/cardbus/puc_cardbus.c sc->sc_dev.dv_xname, reg);
reg 131 dev/cardbus/puc_cardbus.c cardbus_conf_write(cc, cf, ca->ca_tag, reg + 4, 0);
reg 192 dev/flash.c flash_reg8_read(struct flash_softc *sc, int reg)
reg 194 dev/flash.c return sc->sc_tag->reg8_read(sc->sc_cookie, reg);
reg 211 dev/flash.c flash_reg8_write(struct flash_softc *sc, int reg, u_int8_t value)
reg 213 dev/flash.c sc->sc_tag->reg8_write(sc->sc_cookie, reg, value);
reg 162 dev/i2c/ad741x.c u_int8_t cmd, data[2], reg;
reg 167 dev/i2c/ad741x.c reg = (sc->sc_config & AD741X_CONFMASK) | (0 << 5);
reg 169 dev/i2c/ad741x.c sc->sc_addr, &cmd, sizeof cmd, ®, sizeof reg, 0))
reg 183 dev/i2c/ad741x.c reg = (reg & AD741X_CONFMASK) | (4 << 5);
reg 185 dev/i2c/ad741x.c sc->sc_addr, &cmd, sizeof cmd, ®, sizeof reg, 0))
reg 198 dev/i2c/ad741x.c reg = (reg & AD741X_CONFMASK) | (i << 5);
reg 200 dev/i2c/ad741x.c sc->sc_addr, &cmd, sizeof cmd, ®, sizeof reg, 0))
reg 334 dev/i2c/i2c_scan.c u_int8_t reg, val;
reg 338 dev/i2c/i2c_scan.c for (reg = 0x00; reg < 0x09; reg++) {
reg 339 dev/i2c/i2c_scan.c if (iicprobe(reg) == 0xff)
reg 341 dev/i2c/i2c_scan.c if (iicprobe(reg) == 0x00)
reg 343 dev/i2c/i2c_scan.c if (val == iicprobe(reg))
reg 349 dev/i2c/i2c_scan.c for (reg = 0x0a; reg < 0xfc; reg++) {
reg 350 dev/i2c/i2c_scan.c if (iicprobe(reg) != val)
reg 110 dev/i2c/lm78_i2c.c lm_i2c_readreg(struct lm_softc *lmsc, int reg)
reg 117 dev/i2c/lm78_i2c.c cmd = reg;
reg 127 dev/i2c/lm78_i2c.c lm_i2c_writereg(struct lm_softc *lmsc, int reg, int val)
reg 134 dev/i2c/lm78_i2c.c cmd = reg;
reg 247 dev/i2c/rs5c372.c ricohrtc_reg_write(struct ricohrtc_softc *sc, int reg, uint8_t val)
reg 252 dev/i2c/rs5c372.c reg &= 0xf;
reg 253 dev/i2c/rs5c372.c cmd = (reg << 4);
reg 258 dev/i2c/rs5c372.c sc->sc_dev.dv_xname, reg);
reg 69 dev/i2c/w83l784r.c u_int8_t reg;
reg 273 dev/i2c/w83l784r.c int data, reg = sc->sc_wbenv_sensors[n].reg;
reg 275 dev/i2c/w83l784r.c data = wbenv_readreg(sc, reg);
reg 285 dev/i2c/w83l784r.c int data, reg = sc->sc_wbenv_sensors[n].reg;
reg 287 dev/i2c/w83l784r.c data = wbenv_readreg(sc, reg);
reg 299 dev/i2c/w83l784r.c sdata = wbenv_readreg(sc, sc->sc_wbenv_sensors[n].reg);
reg 313 dev/i2c/w83l784r.c sc->sc_addr[sc->sc_wbenv_sensors[n].reg],
reg 325 dev/i2c/w83l784r.c if (sc->sc_wbenv_sensors[n].reg == W83L784R_FAN1)
reg 330 dev/i2c/w83l784r.c data = wbenv_readreg(sc, sc->sc_wbenv_sensors[n].reg);
reg 347 dev/i2c/w83l784r.c if (sc->sc_wbenv_sensors[n].reg == W83L784R_FAN1)
reg 352 dev/i2c/w83l784r.c data = wbenv_readreg(sc, sc->sc_wbenv_sensors[n].reg);
reg 363 dev/i2c/w83l784r.c wbenv_readreg(struct wbenv_softc *sc, u_int8_t reg)
reg 368 dev/i2c/w83l784r.c sc->sc_addr[0], ®, sizeof reg, &data, sizeof data, 0);
reg 374 dev/i2c/w83l784r.c wbenv_writereg(struct wbenv_softc *sc, u_int8_t reg, u_int8_t data)
reg 377 dev/i2c/w83l784r.c sc->sc_addr[0], ®, sizeof reg, &data, sizeof data, 0);
reg 205 dev/ic/aacvar.h #define AAC_SETREG4(sc, reg, val) \
reg 206 dev/ic/aacvar.h bus_space_write_4((sc)->aac_memt, (sc)->aac_memh, (reg), (val))
reg 207 dev/ic/aacvar.h #define AAC_GETREG4(sc, reg) \
reg 208 dev/ic/aacvar.h bus_space_read_4((sc)->aac_memt, (sc)->aac_memh, (reg))
reg 209 dev/ic/aacvar.h #define AAC_SETREG2(sc, reg, val) \
reg 210 dev/ic/aacvar.h bus_space_write_2((sc)->aac_memt, (sc)->aac_memh, (reg), (val))
reg 211 dev/ic/aacvar.h #define AAC_GETREG2(sc, reg) \
reg 212 dev/ic/aacvar.h bus_space_read_2((sc)->aac_memt, (sc)->aac_memh, (reg))
reg 213 dev/ic/aacvar.h #define AAC_SETREG1(sc, reg, val) \
reg 214 dev/ic/aacvar.h bus_space_write_1((sc)->aac_memt, (sc)->aac_memh, (reg), (val))
reg 215 dev/ic/aacvar.h #define AAC_GETREG1(sc, reg) \
reg 216 dev/ic/aacvar.h bus_space_read_1((sc)->aac_memt, (sc)->aac_memh, (reg))
reg 129 dev/ic/ac97.c u_int8_t reg;
reg 558 dev/ic/ac97.c ac97_read(struct ac97_softc *as, u_int8_t reg, u_int16_t *val)
reg 563 dev/ic/ac97.c (reg != AC97_REG_VENDOR_ID1 && reg != AC97_REG_VENDOR_ID2 &&
reg 564 dev/ic/ac97.c reg != AC97_REG_RESET)) ||
reg 566 dev/ic/ac97.c *val = as->shadow_reg[reg >> 1];
reg 570 dev/ic/ac97.c if ((error = as->host_if->read(as->host_if->arg, reg, val)))
reg 571 dev/ic/ac97.c *val = as->shadow_reg[reg >> 1];
reg 576 dev/ic/ac97.c ac97_write(struct ac97_softc *as, u_int8_t reg, u_int16_t val)
reg 578 dev/ic/ac97.c as->shadow_reg[reg >> 1] = val;
reg 579 dev/ic/ac97.c return (as->host_if->write(as->host_if->arg, reg, val));
reg 592 dev/ic/ac97.c ac97_write(as, si->reg, si->default_value);
reg 605 dev/ic/ac97.c ac97_write(as, si->reg, as->shadow_reg[si->reg >> 1]);
reg 880 dev/ic/ac97.c ac97_read(as, si->reg, &val);
reg 882 dev/ic/ac97.c DPRINTFN(5, ("read(%x) = %x\n", si->reg, val));
reg 892 dev/ic/ac97.c if (si->reg == AC97_REG_RECORD_SELECT) {
reg 945 dev/ic/ac97.c error = ac97_write(as, si->reg, (val & ~mask) | newval);
reg 982 dev/ic/ac97.c ac97_read(as, si->reg, &val);
reg 984 dev/ic/ac97.c DPRINTFN(5, ("read(%x) = %x\n", si->reg, val));
reg 1048 dev/ic/ac97.c u_int16_t reg, val, regval, id = 0;
reg 1076 dev/ic/ac97.c reg = mode == AUMODE_PLAY ?
reg 1079 dev/ic/ac97.c if (ac97_write(as, reg, (u_int16_t) p->sample_rate) ||
reg 1080 dev/ic/ac97.c ac97_read(as, reg, ®val))
reg 1117 dev/ic/ac97.c if (as->source_info[i].reg == AC97_REG_SURROUND_VOLUME)
reg 1118 dev/ic/ac97.c as->source_info[i].reg = AC97_REG_MASTER_VOLUME;
reg 1119 dev/ic/ac97.c else if (as->source_info[i].reg == AC97_REG_MASTER_VOLUME) {
reg 1120 dev/ic/ac97.c as->source_info[i].reg = AC97_REG_SURROUND_VOLUME;
reg 46 dev/ic/ac97.h int (*read)(void *arg, u_int8_t reg, u_int16_t *val);
reg 47 dev/ic/ac97.h int (*write)(void *arg, u_int8_t reg, u_int16_t val);
reg 91 dev/ic/ac97.h #define AC97_CAPS_ENHANCEMENT(reg) (((reg) >> 10) & 0x1f)
reg 1428 dev/ic/acx.c uint16_t reg;
reg 1434 dev/ic/acx.c reg = CSR_READ_2(sc, ACXREG_SOFT_RESET);
reg 1435 dev/ic/acx.c CSR_WRITE_2(sc, ACXREG_SOFT_RESET, reg | ACXRV_SOFT_RESET);
reg 1437 dev/ic/acx.c CSR_WRITE_2(sc, ACXREG_SOFT_RESET, reg);
reg 1444 dev/ic/acx.c reg = CSR_READ_2(sc, ACXREG_ECPU_CTRL);
reg 1445 dev/ic/acx.c if (!(reg & ACXRV_ECPU_HALT)) {
reg 1482 dev/ic/acx.c acx_read_phyreg(struct acx_softc *sc, uint32_t reg, uint8_t *val)
reg 1487 dev/ic/acx.c CSR_WRITE_4(sc, ACXREG_PHY_ADDR, reg);
reg 1498 dev/ic/acx.c ifp->if_xname, reg);
reg 1509 dev/ic/acx.c acx_write_phyreg(struct acx_softc *sc, uint32_t reg, uint8_t val)
reg 1512 dev/ic/acx.c CSR_WRITE_4(sc, ACXREG_PHY_ADDR, reg);
reg 1548 dev/ic/acx.c uint16_t reg;
reg 1550 dev/ic/acx.c reg = CSR_READ_2(sc, ACXREG_INTR_STATUS);
reg 1551 dev/ic/acx.c if (reg & ACXRV_INTR_FCS_THRESH) {
reg 2641 dev/ic/acx.c uint16_t reg;
reg 2643 dev/ic/acx.c reg = CSR_READ_2(sc, ACXREG_INTR_STATUS);
reg 2644 dev/ic/acx.c if (reg & ACXRV_INTR_CMD_FINI) {
reg 88 dev/ic/acxreg.h #define ACXREG(reg, val) [ACXREG_##reg] = val
reg 76 dev/ic/acxvar.h #define CSR_READ_1(sc, reg) \
reg 78 dev/ic/acxvar.h (sc)->chip_ioreg[(reg)])
reg 79 dev/ic/acxvar.h #define CSR_READ_2(sc, reg) \
reg 81 dev/ic/acxvar.h (sc)->chip_ioreg[(reg)])
reg 82 dev/ic/acxvar.h #define CSR_READ_4(sc, reg) \
reg 84 dev/ic/acxvar.h (sc)->chip_ioreg[(reg)])
reg 86 dev/ic/acxvar.h #define CSR_WRITE_2(sc, reg, val) \
reg 88 dev/ic/acxvar.h (sc)->chip_ioreg[(reg)], val)
reg 89 dev/ic/acxvar.h #define CSR_WRITE_4(sc, reg, val) \
reg 91 dev/ic/acxvar.h (sc)->chip_ioreg[(reg)], val)
reg 93 dev/ic/acxvar.h #define CSR_SETB_2(sc, reg, b) \
reg 94 dev/ic/acxvar.h CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (b))
reg 95 dev/ic/acxvar.h #define CSR_CLRB_2(sc, reg, b) \
reg 96 dev/ic/acxvar.h CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & (~(b)))
reg 123 dev/ic/aic6915.c #define sf_funcreg_read(sc, reg) \
reg 124 dev/ic/aic6915.c bus_space_read_4((sc)->sc_st, (sc)->sc_sh_func, (reg))
reg 125 dev/ic/aic6915.c #define sf_funcreg_write(sc, reg, val) \
reg 126 dev/ic/aic6915.c bus_space_write_4((sc)->sc_st, (sc)->sc_sh_func, (reg), (val))
reg 129 dev/ic/aic6915.c sf_reg_read(struct sf_softc *sc, bus_addr_t reg)
reg 134 dev/ic/aic6915.c reg);
reg 139 dev/ic/aic6915.c return (bus_space_read_4(sc->sc_st, sc->sc_sh, reg));
reg 143 dev/ic/aic6915.c sf_reg_write(struct sf_softc *sc, bus_addr_t reg, uint32_t val)
reg 148 dev/ic/aic6915.c reg);
reg 154 dev/ic/aic6915.c bus_space_write_4(sc->sc_st, sc->sc_sh, reg, val);
reg 157 dev/ic/aic6915.c #define sf_genreg_read(sc, reg) \
reg 158 dev/ic/aic6915.c sf_reg_read((sc), (reg) + SF_GENREG_OFFSET)
reg 159 dev/ic/aic6915.c #define sf_genreg_write(sc, reg, val) \
reg 160 dev/ic/aic6915.c sf_reg_write((sc), (reg) + SF_GENREG_OFFSET, (val))
reg 1267 dev/ic/aic6915.c uint32_t reg;
reg 1269 dev/ic/aic6915.c reg = sf_genreg_read(sc, SF_EEPROM_BASE + (offset & ~3));
reg 1271 dev/ic/aic6915.c return ((reg >> (8 * (offset & 3))) & 0xff);
reg 1335 dev/ic/aic6915.c uint32_t hash, slot, reg;
reg 1340 dev/ic/aic6915.c reg = sf_genreg_read(sc, SF_HASH_BASE + (slot * 0x10));
reg 1341 dev/ic/aic6915.c reg |= 1 << (hash & 0xf);
reg 1342 dev/ic/aic6915.c sf_genreg_write(sc, SF_HASH_BASE + (slot * 0x10), reg);
reg 1441 dev/ic/aic6915.c sf_mii_read(struct device *self, int phy, int reg)
reg 1448 dev/ic/aic6915.c v = sf_genreg_read(sc, SF_MII_PHY_REG(phy, reg));
reg 1469 dev/ic/aic6915.c sf_mii_write(struct device *self, int phy, int reg, int val)
reg 1474 dev/ic/aic6915.c sf_genreg_write(sc, SF_MII_PHY_REG(phy, reg), val);
reg 1477 dev/ic/aic6915.c if ((sf_genreg_read(sc, SF_MII_PHY_REG(phy, reg)) &
reg 345 dev/ic/aic7xxx_openbsd.h ahc_pci_read_config(ahc_dev_softc_t pci, int reg, int width)
reg 347 dev/ic/aic7xxx_openbsd.h return (pci_conf_read(pci->pa_pc, pci->pa_tag, reg));
reg 351 dev/ic/aic7xxx_openbsd.h ahc_pci_write_config(ahc_dev_softc_t pci, int reg, uint32_t value, int width)
reg 353 dev/ic/aic7xxx_openbsd.h pci_conf_write(pci->pa_pc, pci->pa_tag, reg, value);
reg 49 dev/ic/anvar.h #define CSR_WRITE_2(sc, reg, val) \
reg 50 dev/ic/anvar.h bus_space_write_2(sc->sc_iot, sc->sc_ioh, reg, val)
reg 52 dev/ic/anvar.h #define CSR_READ_2(sc, reg) \
reg 53 dev/ic/anvar.h bus_space_read_2(sc->sc_iot, sc->sc_ioh, reg)
reg 60 dev/ic/anvar.h #define CSR_WRITE_MULTI_STREAM_2(sc, reg, val, count) \
reg 61 dev/ic/anvar.h bus_space_write_multi_stream_2(sc->sc_iot, sc->sc_ioh, reg, val, count)
reg 62 dev/ic/anvar.h #define CSR_READ_MULTI_STREAM_2(sc, reg, buf, count) \
reg 63 dev/ic/anvar.h bus_space_read_multi_stream_2(sc->sc_iot, sc->sc_ioh, reg, buf, count)
reg 668 dev/ic/ar5xxx.c ar5k_register_timeout(struct ath_hal *hal, u_int32_t reg, u_int32_t flag,
reg 675 dev/ic/ar5xxx.c data = AR5K_REG_READ(reg);
reg 1299 dev/ic/ar5xxx.c ar5k_rfregs_op(u_int32_t *rf, u_int32_t offset, u_int32_t reg, u_int32_t bits,
reg 1320 dev/ic/ar5xxx.c data = ar5k_bitswap(reg, bits);
reg 470 dev/ic/atw.c #define PRINTREG(sc, reg) \
reg 471 dev/ic/atw.c ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \
reg 472 dev/ic/atw.c sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg)))
reg 576 dev/ic/atw.c u_int32_t reg;
reg 694 dev/ic/atw.c reg = LSHIFT(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK);
reg 698 dev/ic/atw.c reg |= ATW_SYNCTL_CS1;
reg 701 dev/ic/atw.c reg |= ATW_SYNCTL_CS0;
reg 707 dev/ic/atw.c sc->sc_synctl_rd = reg | ATW_SYNCTL_RD;
reg 708 dev/ic/atw.c sc->sc_synctl_wr = reg | ATW_SYNCTL_WR;
reg 710 dev/ic/atw.c reg = LSHIFT(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK);
reg 714 dev/ic/atw.c reg |= ATW_BBPCTL_TWI;
reg 717 dev/ic/atw.c reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO |
reg 728 dev/ic/atw.c sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR;
reg 729 dev/ic/atw.c sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD;
reg 796 dev/ic/atw.c reg = ATW_READ(sc, ATW_PAR0);
reg 797 dev/ic/atw.c ic->ic_myaddr[0] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB0_MASK);
reg 798 dev/ic/atw.c ic->ic_myaddr[1] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB1_MASK);
reg 799 dev/ic/atw.c ic->ic_myaddr[2] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB2_MASK);
reg 800 dev/ic/atw.c ic->ic_myaddr[3] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB3_MASK);
reg 801 dev/ic/atw.c reg = ATW_READ(sc, ATW_PAR1);
reg 802 dev/ic/atw.c ic->ic_myaddr[4] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB4_MASK);
reg 803 dev/ic/atw.c ic->ic_myaddr[5] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB5_MASK);
reg 1808 dev/ic/atw.c u_int32_t reg;
reg 1861 dev/ic/atw.c reg = ATW_READ(sc, ATW_PLCPHD);
reg 1862 dev/ic/atw.c reg &= ~ATW_PLCPHD_SERVICE_MASK;
reg 1863 dev/ic/atw.c reg |= LSHIFT(LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK),
reg 1865 dev/ic/atw.c ATW_WRITE(sc, ATW_PLCPHD, reg);
reg 1879 dev/ic/atw.c u_int32_t reg;
reg 1882 dev/ic/atw.c reg = sc->sc_bbpctl_wr |
reg 1887 dev/ic/atw.c ATW_WRITE(sc, ATW_BBPCTL, reg);
reg 1917 dev/ic/atw.c u_int32_t reg;
reg 1932 dev/ic/atw.c reg = sc->sc_bbpctl_rd | LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK);
reg 1934 dev/ic/atw.c ATW_WRITE(sc, ATW_BBPCTL, reg);
reg 1946 dev/ic/atw.c sc->sc_dev.dv_xname, reg);
reg 1950 dev/ic/atw.c *val = MASK_AND_RSHIFT(reg, ATW_BBPCTL_DATA_MASK);
reg 1965 dev/ic/atw.c uint32_t bits, mask, reg;
reg 1984 dev/ic/atw.c reg = ATW_SYNRF_SELSYN;
reg 1988 dev/ic/atw.c ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF);
reg 1989 dev/ic/atw.c ATW_WRITE(sc, ATW_SYNRF, reg);
reg 1993 dev/ic/atw.c reg |= ATW_SYNRF_SYNDATA;
reg 1995 dev/ic/atw.c reg &= ~ATW_SYNRF_SYNDATA;
reg 1996 dev/ic/atw.c ATW_WRITE(sc, ATW_SYNRF, reg);
reg 1997 dev/ic/atw.c ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK);
reg 1998 dev/ic/atw.c ATW_WRITE(sc, ATW_SYNRF, reg);
reg 2000 dev/ic/atw.c ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF);
reg 2014 dev/ic/atw.c u_int32_t reg;
reg 2031 dev/ic/atw.c reg = sc->sc_synctl_rd | LSHIFT(addr, ATW_SYNCTL_DATA_MASK);
reg 2033 dev/ic/atw.c ATW_WRITE(sc, ATW_SYNCTL, reg);
reg 2045 dev/ic/atw.c sc->sc_dev.dv_xname, reg);
reg 2214 dev/ic/atw.c u_int32_t reg;
reg 2244 dev/ic/atw.c reg = ATW_READ(sc, ATW_MACTEST);
reg 2245 dev/ic/atw.c reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID;
reg 2246 dev/ic/atw.c reg &= ~ATW_MACTEST_KEYID_MASK;
reg 2247 dev/ic/atw.c reg |= LSHIFT(ic->ic_wep_txkey, ATW_MACTEST_KEYID_MASK);
reg 2248 dev/ic/atw.c ATW_WRITE(sc, ATW_MACTEST, reg);
reg 91 dev/ic/atwreg.h #define MASK_AND_REPLACE(reg, val, mask) ((reg & ~mask) | LSHIFT(val, mask))
reg 444 dev/ic/atwvar.h #define ATW_READ(sc, reg) \
reg 445 dev/ic/atwvar.h bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
reg 447 dev/ic/atwvar.h #define ATW_WRITE(sc, reg, val) \
reg 448 dev/ic/atwvar.h bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
reg 450 dev/ic/atwvar.h #define ATW_SET(sc, reg, mask) \
reg 451 dev/ic/atwvar.h ATW_WRITE((sc), (reg), ATW_READ((sc), (reg)) | (mask))
reg 453 dev/ic/atwvar.h #define ATW_CLR(sc, reg, mask) \
reg 454 dev/ic/atwvar.h ATW_WRITE((sc), (reg), ATW_READ((sc), (reg)) & ~(mask))
reg 456 dev/ic/atwvar.h #define ATW_ISSET(sc, reg, mask) \
reg 457 dev/ic/atwvar.h (ATW_READ((sc), (reg)) & (mask))
reg 171 dev/ic/ax88190.c ax88190_mii_readreg(self, phy, reg)
reg 173 dev/ic/ax88190.c int phy, reg;
reg 175 dev/ic/ax88190.c return (mii_bitbang_readreg(self, &ax88190_mii_bitbang_ops, phy, reg));
reg 179 dev/ic/ax88190.c ax88190_mii_writereg(self, phy, reg, val)
reg 181 dev/ic/ax88190.c int phy, reg, val;
reg 183 dev/ic/ax88190.c mii_bitbang_writereg(self, &ax88190_mii_bitbang_ops, phy, reg, val);
reg 105 dev/ic/cyreg.h #define cd_read_reg(cy,reg) bus_space_read_1(cy->cy_memt, cy->cy_memh, \
reg 106 dev/ic/cyreg.h cy->cy_chip_offs+(((reg<<1))<<cy->cy_bustype))
reg 108 dev/ic/cyreg.h #define cd_write_reg(cy,reg,val) bus_space_write_1(cy->cy_memt, cy->cy_memh, \
reg 109 dev/ic/cyreg.h cy->cy_chip_offs+(((reg<<1))<<cy->cy_bustype), \
reg 115 dev/ic/cyreg.h #define cd_read_reg_sc(sc,chip,reg) bus_space_read_1(sc->sc_memt, \
reg 118 dev/ic/cyreg.h (((reg<<1))<<sc->sc_bustype))
reg 120 dev/ic/cyreg.h #define cd_write_reg_sc(sc,chip,reg,val) bus_space_write_1(sc->sc_memt, \
reg 123 dev/ic/cyreg.h (((reg<<1))<<sc->sc_bustype), \
reg 197 dev/ic/dc.c #define DC_SETBIT(sc, reg, x) \
reg 198 dev/ic/dc.c CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
reg 200 dev/ic/dc.c #define DC_CLRBIT(sc, reg, x) \
reg 201 dev/ic/dc.c CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
reg 652 dev/ic/dc.c dc_miibus_readreg(self, phy, reg)
reg 654 dev/ic/dc.c int phy, reg;
reg 682 dev/ic/dc.c switch(reg) {
reg 710 dev/ic/dc.c (phy << 23) | (reg << 18));
reg 723 dev/ic/dc.c switch(reg) {
reg 747 dev/ic/dc.c sc->sc_dev.dv_xname, reg);
reg 762 dev/ic/dc.c frame.mii_regaddr = reg;
reg 775 dev/ic/dc.c dc_miibus_writereg(self, phy, reg, data)
reg 777 dev/ic/dc.c int phy, reg, data;
reg 792 dev/ic/dc.c (phy << 23) | (reg << 10) | data);
reg 801 dev/ic/dc.c switch(reg) {
reg 825 dev/ic/dc.c sc->sc_dev.dv_xname, reg);
reg 835 dev/ic/dc.c frame.mii_regaddr = reg;
reg 1447 dev/ic/dc.c u_int32_t reg;
reg 1461 dev/ic/dc.c reg = (p[0] | (p[1] << 8)) << 16;
reg 1462 dev/ic/dc.c CSR_WRITE_4(sc, DC_WATCHDOG, reg);
reg 1466 dev/ic/dc.c reg = (p[0] | (p[1] << 8)) << 16;
reg 1467 dev/ic/dc.c CSR_WRITE_4(sc, DC_WATCHDOG, reg);
reg 1656 dev/ic/dc.c u_int32_t reg;
reg 1686 dev/ic/dc.c reg = CSR_READ_4(sc, DC_AL_PAR0);
reg 1687 dev/ic/dc.c sc->sc_arpcom.ac_enaddr[0] = (reg & 0xff);
reg 1688 dev/ic/dc.c sc->sc_arpcom.ac_enaddr[1] = (reg >> 8) & 0xff;
reg 1689 dev/ic/dc.c sc->sc_arpcom.ac_enaddr[2] = (reg >> 16) & 0xff;
reg 1690 dev/ic/dc.c sc->sc_arpcom.ac_enaddr[3] = (reg >> 24) & 0xff;
reg 1691 dev/ic/dc.c reg = CSR_READ_4(sc, DC_AL_PAR1);
reg 1692 dev/ic/dc.c sc->sc_arpcom.ac_enaddr[4] = (reg & 0xff);
reg 1693 dev/ic/dc.c sc->sc_arpcom.ac_enaddr[5] = (reg >> 8) & 0xff;
reg 779 dev/ic/dcreg.h #define CSR_WRITE_4(sc, reg, val) \
reg 780 dev/ic/dcreg.h bus_space_write_4(sc->dc_btag, sc->dc_bhandle, reg, val)
reg 782 dev/ic/dcreg.h #define CSR_READ_4(sc, reg) \
reg 783 dev/ic/dcreg.h bus_space_read_4(sc->dc_btag, sc->dc_bhandle, reg)
reg 212 dev/ic/dl10019.c dl10019_mii_readreg(struct device *self, int phy, int reg)
reg 220 dev/ic/dl10019.c return (mii_bitbang_readreg(self, ops, phy, reg));
reg 224 dev/ic/dl10019.c dl10019_mii_writereg(struct device *self, int phy, int reg, int val)
reg 232 dev/ic/dl10019.c mii_bitbang_writereg(self, ops, phy, reg, val);
reg 147 dev/ic/dp8390var.h #define NIC_GET(t, h, reg) bus_space_read_1(t, h, \
reg 148 dev/ic/dp8390var.h ((sc)->sc_reg_map[reg]))
reg 149 dev/ic/dp8390var.h #define NIC_PUT(t, h, reg, val) bus_space_write_1(t, h, \
reg 150 dev/ic/dp8390var.h ((sc)->sc_reg_map[reg]), (val))
reg 89 dev/ic/dp857xreg.h u_int dp857x_read(void *sc, u_int reg);
reg 90 dev/ic/dp857xreg.h void dp857x_write(void *sc, u_int reg, u_int datum);
reg 245 dev/ic/elink3.c ep_w1_reg(sc, reg)
reg 247 dev/ic/elink3.c int reg;
reg 251 dev/ic/elink3.c switch (reg) {
reg 255 dev/ic/elink3.c return (reg);
reg 257 dev/ic/elink3.c return (reg + 0x10);
reg 259 dev/ic/elink3.c return (reg);
reg 1834 dev/ic/elink3.c ep_mii_readreg(self, phy, reg)
reg 1836 dev/ic/elink3.c int phy, reg;
reg 1853 dev/ic/elink3.c ep_mii_sendbits(sc, reg, 5);
reg 1880 dev/ic/elink3.c ep_mii_writereg(self, phy, reg, val)
reg 1882 dev/ic/elink3.c int phy, reg, val;
reg 1896 dev/ic/elink3.c ep_mii_sendbits(sc, reg, 5);
reg 210 dev/ic/fxp.c u_int16_t reg;
reg 218 dev/ic/fxp.c reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
reg 220 dev/ic/fxp.c reg = FXP_EEPROM_EECS;
reg 221 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
reg 223 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
reg 225 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
reg 582 dev/ic/fxp.c u_int16_t reg;
reg 591 dev/ic/fxp.c reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
reg 593 dev/ic/fxp.c reg = FXP_EEPROM_EECS;
reg 595 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
reg 597 dev/ic/fxp.c reg | FXP_EEPROM_EESK);
reg 599 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
reg 632 dev/ic/fxp.c u_int16_t reg;
reg 642 dev/ic/fxp.c reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
reg 644 dev/ic/fxp.c reg = FXP_EEPROM_EECS;
reg 646 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
reg 648 dev/ic/fxp.c reg | FXP_EEPROM_EESK);
reg 650 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
reg 658 dev/ic/fxp.c reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
reg 660 dev/ic/fxp.c reg = FXP_EEPROM_EECS;
reg 662 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
reg 664 dev/ic/fxp.c reg | FXP_EEPROM_EESK);
reg 666 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
reg 669 dev/ic/fxp.c reg = FXP_EEPROM_EECS;
reg 676 dev/ic/fxp.c reg | FXP_EEPROM_EESK);
reg 681 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
reg 1563 dev/ic/fxp.c fxp_mdi_read(struct device *self, int phy, int reg)
reg 1570 dev/ic/fxp.c (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
reg 1589 dev/ic/fxp.c fxp_mdi_write(struct device *self, int phy, int reg, int value)
reg 1595 dev/ic/fxp.c (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
reg 149 dev/ic/fxpvar.h #define CSR_READ_1(sc, reg) \
reg 150 dev/ic/fxpvar.h bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))
reg 151 dev/ic/fxpvar.h #define CSR_READ_2(sc, reg) \
reg 152 dev/ic/fxpvar.h bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))
reg 153 dev/ic/fxpvar.h #define CSR_READ_4(sc, reg) \
reg 154 dev/ic/fxpvar.h bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
reg 155 dev/ic/fxpvar.h #define CSR_WRITE_1(sc, reg, val) \
reg 156 dev/ic/fxpvar.h bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
reg 157 dev/ic/fxpvar.h #define CSR_WRITE_2(sc, reg, val) \
reg 158 dev/ic/fxpvar.h bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
reg 159 dev/ic/fxpvar.h #define CSR_WRITE_4(sc, reg, val) \
reg 160 dev/ic/fxpvar.h bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
reg 417 dev/ic/gem.c u_int32_t reg;
reg 420 dev/ic/gem.c reg = bus_space_read_4(sc->sc_bustag, h, r);
reg 421 dev/ic/gem.c if ((reg & clr) == 0 && (reg & set) == set)
reg 1192 dev/ic/gem.c gem_mii_readreg(struct device *self, int phy, int reg)
reg 1202 dev/ic/gem.c printf("gem_mii_readreg: phy %d reg %d\n", phy, reg);
reg 1206 dev/ic/gem.c v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) |
reg 1222 dev/ic/gem.c gem_mii_writereg(struct device *self, int phy, int reg, int val)
reg 1233 dev/ic/gem.c phy, reg, val);
reg 1239 dev/ic/gem.c (reg << GEM_MIF_REG_SHIFT) |
reg 1310 dev/ic/gem.c gem_pcs_readreg(struct device *self, int phy, int reg)
reg 1318 dev/ic/gem.c printf("gem_pcs_readreg: phy %d reg %d\n", phy, reg);
reg 1324 dev/ic/gem.c switch (reg) {
reg 1326 dev/ic/gem.c reg = GEM_MII_CONTROL;
reg 1329 dev/ic/gem.c reg = GEM_MII_STATUS;
reg 1332 dev/ic/gem.c reg = GEM_MII_ANAR;
reg 1335 dev/ic/gem.c reg = GEM_MII_ANLPAR;
reg 1343 dev/ic/gem.c return bus_space_read_4(t, pcs, reg);
reg 1347 dev/ic/gem.c gem_pcs_writereg(struct device *self, int phy, int reg, int val)
reg 1356 dev/ic/gem.c phy, reg, val);
reg 1362 dev/ic/gem.c switch (reg) {
reg 1364 dev/ic/gem.c reg = GEM_MII_CONTROL;
reg 1367 dev/ic/gem.c reg = GEM_MII_STATUS;
reg 1370 dev/ic/gem.c reg = GEM_MII_ANAR;
reg 1373 dev/ic/gem.c reg = GEM_MII_ANLPAR;
reg 1379 dev/ic/gem.c bus_space_write_4(t, pcs, reg, val);
reg 1381 dev/ic/gem.c if (reg == GEM_MII_ANAR) {
reg 1014 dev/ic/hme.c hme_mii_readreg(self, phy, reg)
reg 1016 dev/ic/hme.c int phy, reg;
reg 1048 dev/ic/hme.c (reg << HME_MIF_FO_REGAD_SHIFT);
reg 1072 dev/ic/hme.c hme_mii_writereg(self, phy, reg, val)
reg 1074 dev/ic/hme.c int phy, reg, val;
reg 1107 dev/ic/hme.c (reg << HME_MIF_FO_REGAD_SHIFT) |
reg 137 dev/ic/i82365.c int vendor, reg;
reg 145 dev/ic/i82365.c reg = pcic_read(h, -1);
reg 147 dev/ic/i82365.c if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) ==
reg 149 dev/ic/i82365.c reg = pcic_read(h, -1);
reg 150 dev/ic/i82365.c if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 0) {
reg 151 dev/ic/i82365.c if (reg & PCIC_CIRRUS_CHIP_INFO_SLOTS)
reg 158 dev/ic/i82365.c reg = pcic_read(h, PCIC_IDENT);
reg 160 dev/ic/i82365.c switch (reg) {
reg 178 dev/ic/i82365.c reg = pcic_read(h, PCIC_VG468_MISC);
reg 179 dev/ic/i82365.c reg |= PCIC_VG468_MISC_VADEMREV;
reg 180 dev/ic/i82365.c pcic_write(h, PCIC_VG468_MISC, reg);
reg 182 dev/ic/i82365.c reg = pcic_read(h, PCIC_IDENT);
reg 184 dev/ic/i82365.c if (reg & PCIC_IDENT_VADEM_MASK) {
reg 185 dev/ic/i82365.c if ((reg & 7) >= 4)
reg 190 dev/ic/i82365.c reg = pcic_read(h, PCIC_VG468_MISC);
reg 191 dev/ic/i82365.c reg &= ~PCIC_VG468_MISC_VADEMREV;
reg 192 dev/ic/i82365.c pcic_write(h, PCIC_VG468_MISC, reg);
reg 202 dev/ic/i82365.c int vendor, count, i, reg;
reg 222 dev/ic/i82365.c if (pcic_ident_ok(reg = pcic_read(&sc->handle[0], PCIC_IDENT))) {
reg 230 dev/ic/i82365.c DPRINTF((" 0x%02x", reg));
reg 239 dev/ic/i82365.c if (pcic_ident_ok(reg = pcic_read(&sc->handle[1], PCIC_IDENT))) {
reg 247 dev/ic/i82365.c DPRINTF((" 0x%02x", reg));
reg 263 dev/ic/i82365.c if (pcic_ident_ok(reg = pcic_read(&sc->handle[2],
reg 272 dev/ic/i82365.c DPRINTF((" 0x%02x", reg));
reg 281 dev/ic/i82365.c if (pcic_ident_ok(reg = pcic_read(&sc->handle[3],
reg 290 dev/ic/i82365.c DPRINTF((" 0x%02x\n", reg));
reg 518 dev/ic/i82365.c int reg;
reg 541 dev/ic/i82365.c reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_2);
reg 542 dev/ic/i82365.c if (reg & PCIC_CIRRUS_MISC_CTL_2_SUSPEND) {
reg 545 dev/ic/i82365.c reg &= ~PCIC_CIRRUS_MISC_CTL_2_SUSPEND;
reg 546 dev/ic/i82365.c pcic_write(h, PCIC_CIRRUS_MISC_CTL_2, reg);
reg 551 dev/ic/i82365.c reg = pcic_read(h, PCIC_IF_STATUS);
reg 553 dev/ic/i82365.c if ((reg & PCIC_IF_STATUS_CARDDETECT_MASK) ==
reg 977 dev/ic/i82365.c int reg;
reg 1007 dev/ic/i82365.c reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);
reg 1008 dev/ic/i82365.c reg |= (mem_map_index[win].memenable | PCIC_ADDRWIN_ENABLE_MEMCS16);
reg 1009 dev/ic/i82365.c pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
reg 1104 dev/ic/i82365.c int reg;
reg 1109 dev/ic/i82365.c reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);
reg 1110 dev/ic/i82365.c reg &= ~mem_map_index[window].memenable;
reg 1111 dev/ic/i82365.c pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
reg 1269 dev/ic/i82365.c int reg;
reg 1284 dev/ic/i82365.c reg = pcic_read(h, PCIC_IOCTL);
reg 1285 dev/ic/i82365.c reg &= ~io_map_index[win].ioctlmask;
reg 1286 dev/ic/i82365.c reg |= io_map_index[win].ioctlbits[h->io[win].width];
reg 1287 dev/ic/i82365.c pcic_write(h, PCIC_IOCTL, reg);
reg 1289 dev/ic/i82365.c reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);
reg 1290 dev/ic/i82365.c reg |= io_map_index[win].ioenable;
reg 1291 dev/ic/i82365.c pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
reg 1350 dev/ic/i82365.c int reg;
reg 1355 dev/ic/i82365.c reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);
reg 1356 dev/ic/i82365.c reg &= ~io_map_index[window].ioenable;
reg 1357 dev/ic/i82365.c pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
reg 1389 dev/ic/i82365.c int cardtype, reg, win;
reg 1404 dev/ic/i82365.c reg = pcic_read(h, PCIC_VG469_VSELECT);
reg 1405 dev/ic/i82365.c reg &= ~PCIC_VG469_VSELECT_VCC;
reg 1406 dev/ic/i82365.c pcic_write(h, PCIC_VG469_VSELECT, reg);
reg 1443 dev/ic/i82365.c reg = pcic_read(h, PCIC_IF_STATUS);
reg 1444 dev/ic/i82365.c if (!(reg & PCIC_IF_STATUS_POWERACTIVE)) {
reg 1445 dev/ic/i82365.c printf("pcic_chip_socket_enable: status %x\n", reg);
reg 1459 dev/ic/i82365.c reg = pcic_read(h, PCIC_INTR);
reg 1460 dev/ic/i82365.c reg &= ~PCIC_INTR_CARDTYPE_MASK;
reg 1461 dev/ic/i82365.c reg |= ((cardtype == PCMCIA_IFTYPE_IO) ?
reg 1464 dev/ic/i82365.c reg |= h->ih_irq;
reg 1465 dev/ic/i82365.c pcic_write(h, PCIC_INTR, reg);
reg 1469 dev/ic/i82365.c ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg));
reg 506 dev/ic/ibm561.c ibm561_regcont10bit(struct ibm561data *data, u_int16_t reg, u_int16_t val)
reg 513 dev/ic/ibm561.c ibm561_regbegin(struct ibm561data *data, u_int16_t reg)
reg 515 dev/ic/ibm561.c data->ramdac_wr(data->cookie, IBM561_ADDR_LOW, reg & 0xff);
reg 516 dev/ic/ibm561.c data->ramdac_wr(data->cookie, IBM561_ADDR_HIGH, (reg >> 8) & 0xff);
reg 520 dev/ic/ibm561.c ibm561_regcont(struct ibm561data *data, u_int16_t reg, u_int8_t val)
reg 522 dev/ic/ibm561.c data->ramdac_wr(data->cookie, reg, val);
reg 526 dev/ic/ibm561.c ibm561_regwr(struct ibm561data *data, u_int16_t reg, u_int8_t val)
reg 528 dev/ic/ibm561.c ibm561_regbegin(data, reg);
reg 90 dev/ic/if_wireg.h #define CSR_WRITE_4(sc, reg, val) \
reg 92 dev/ic/if_wireg.h (sc->sc_pci ? reg * 2: reg), \
reg 94 dev/ic/if_wireg.h #define CSR_WRITE_2(sc, reg, val) \
reg 96 dev/ic/if_wireg.h (sc->sc_pci ? reg * 2: reg), \
reg 98 dev/ic/if_wireg.h #define CSR_WRITE_1(sc, reg, val) \
reg 100 dev/ic/if_wireg.h (sc->sc_pci ? reg * 2: reg), val)
reg 102 dev/ic/if_wireg.h #define CSR_READ_4(sc, reg) \
reg 105 dev/ic/if_wireg.h (sc->sc_pci ? reg * 2: reg))) : \
reg 107 dev/ic/if_wireg.h (sc->sc_pci ? reg * 2: reg)))
reg 108 dev/ic/if_wireg.h #define CSR_READ_2(sc, reg) \
reg 111 dev/ic/if_wireg.h (sc->sc_pci ? reg * 2: reg))) : \
reg 113 dev/ic/if_wireg.h (sc->sc_pci ? reg * 2: reg)))
reg 114 dev/ic/if_wireg.h #define CSR_READ_1(sc, reg) \
reg 116 dev/ic/if_wireg.h (sc->sc_pci ? reg * 2: reg))
reg 105 dev/ic/ispvar.h #define ISP_READ(isp, reg) \
reg 106 dev/ic/ispvar.h (*(isp)->isp_mdvec->dv_rd_reg)((isp), (reg))
reg 108 dev/ic/ispvar.h #define ISP_WRITE(isp, reg, val) \
reg 109 dev/ic/ispvar.h (*(isp)->isp_mdvec->dv_wr_reg)((isp), (reg), (val))
reg 128 dev/ic/ispvar.h #define ISP_SETBITS(isp, reg, val) \
reg 129 dev/ic/ispvar.h (*(isp)->isp_mdvec->dv_wr_reg)((isp), (reg), ISP_READ((isp), (reg)) | (val))
reg 131 dev/ic/ispvar.h #define ISP_CLRBITS(isp, reg, val) \
reg 132 dev/ic/ispvar.h (*(isp)->isp_mdvec->dv_wr_reg)((isp), (reg), ISP_READ((isp), (reg)) & ~(val))
reg 620 dev/ic/lm78.c data = sc->lm_readreg(sc, sc->lm_sensors[n].reg);
reg 636 dev/ic/lm78.c sdata = sc->lm_readreg(sc, sc->lm_sensors[n].reg);
reg 661 dev/ic/lm78.c if (sc->lm_sensors[n].reg == LM_FAN1 ||
reg 662 dev/ic/lm78.c sc->lm_sensors[n].reg == LM_FAN2) {
reg 664 dev/ic/lm78.c if (sc->lm_sensors[n].reg == LM_FAN1)
reg 670 dev/ic/lm78.c data = sc->lm_readreg(sc, sc->lm_sensors[n].reg);
reg 706 dev/ic/lm78.c data = sc->lm_readreg(sc, sc->lm_sensors[n].reg);
reg 726 dev/ic/lm78.c data = sc->lm_readreg(sc, sc->lm_sensors[n].reg);
reg 739 dev/ic/lm78.c data = sc->lm_readreg(sc, sc->lm_sensors[n].reg);
reg 759 dev/ic/lm78.c sdata = sc->lm_readreg(sc, sc->lm_sensors[n].reg) << 1;
reg 760 dev/ic/lm78.c sdata += sc->lm_readreg(sc, sc->lm_sensors[n].reg + 1) >> 7;
reg 783 dev/ic/lm78.c if (sc->lm_sensors[n].reg == LM_FAN1 ||
reg 784 dev/ic/lm78.c sc->lm_sensors[n].reg == LM_FAN2 ||
reg 785 dev/ic/lm78.c sc->lm_sensors[n].reg == LM_FAN3) {
reg 787 dev/ic/lm78.c fan = (sc->lm_sensors[n].reg - LM_FAN1);
reg 792 dev/ic/lm78.c if (sc->lm_sensors[n].reg == LM_FAN1 ||
reg 793 dev/ic/lm78.c sc->lm_sensors[n].reg == LM_FAN2) {
reg 795 dev/ic/lm78.c if (sc->lm_sensors[n].reg == LM_FAN1)
reg 799 dev/ic/lm78.c } else if (sc->lm_sensors[n].reg == LM_FAN3) {
reg 802 dev/ic/lm78.c } else if (sc->lm_sensors[n].reg == WB_BANK0_FAN4 ||
reg 803 dev/ic/lm78.c sc->lm_sensors[n].reg == WB_BANK0_FAN5) {
reg 805 dev/ic/lm78.c if (sc->lm_sensors[n].reg == WB_BANK0_FAN4)
reg 811 dev/ic/lm78.c data = sc->lm_readreg(sc, sc->lm_sensors[n].reg);
reg 825 dev/ic/lm78.c int reg, shift, data, divisor = 1;
reg 827 dev/ic/lm78.c switch (sc->lm_sensors[n].reg) {
reg 829 dev/ic/lm78.c reg = 0x47; shift = 0;
reg 832 dev/ic/lm78.c reg = 0x47; shift = 4;
reg 835 dev/ic/lm78.c reg = 0x5b; shift = 0;
reg 838 dev/ic/lm78.c reg = 0x5b; shift = 4;
reg 841 dev/ic/lm78.c reg = 0x5c; shift = 0;
reg 844 dev/ic/lm78.c reg = 0x5c; shift = 4;
reg 847 dev/ic/lm78.c reg = 0x9e; shift = 0;
reg 850 dev/ic/lm78.c reg = 0;
reg 854 dev/ic/lm78.c data = sc->lm_readreg(sc, sc->lm_sensors[n].reg);
reg 859 dev/ic/lm78.c if (reg != 0)
reg 860 dev/ic/lm78.c divisor = (sc->lm_readreg(sc, reg) >> shift) & 0x7;
reg 876 dev/ic/lm78.c sdata = sc->lm_readreg(sc, sc->lm_sensors[n].reg) << 1;
reg 877 dev/ic/lm78.c sdata += sc->lm_readreg(sc, sc->lm_sensors[n].reg + 1) >> 7;
reg 134 dev/ic/lm78var.h u_int8_t reg;
reg 151 dev/ic/mc146818reg.h u_int mc146818_read(void *sc, u_int reg);
reg 152 dev/ic/mc146818reg.h void mc146818_write(void *sc, u_int reg, u_int datum);
reg 669 dev/ic/midway.c u_int32_t reg, lcv, check, ptr, sav, midvloc;
reg 685 dev/ic/midway.c reg = EN_READ(sc, check);
reg 686 dev/ic/midway.c if (reg != check) { /* found an alias! */
reg 711 dev/ic/midway.c reg = EN_READ(sc, MID_RESID);
reg 714 dev/ic/midway.c sc->sc_dev.dv_xname, MID_VER(reg), MID_MID(reg), MID_DID(reg),
reg 715 dev/ic/midway.c (MID_IS_SABRE(reg)) ? "sabre controller, " : "",
reg 716 dev/ic/midway.c (MID_IS_SUNI(reg)) ? "SUNI" : "Utopia",
reg 717 dev/ic/midway.c (!MID_IS_SUNI(reg) && MID_IS_UPIPE(reg)) ? " (pipelined)" : "",
reg 947 dev/ic/midway.c u_int32_t reg, bcode, midvloc;
reg 1016 dev/ic/midway.c reg = EN_READ(sc, MID_INTACK);
reg 1017 dev/ic/midway.c if ((reg & MID_INT_DMA_TX) != MID_INT_DMA_TX) {
reg 1019 dev/ic/midway.c sc->sc_dev.dv_xname, reg);
reg 1042 dev/ic/midway.c reg = EN_READ(sc, MID_INTACK);
reg 1043 dev/ic/midway.c if ((reg & MID_INT_DMA_RX) != MID_INT_DMA_RX) {
reg 1045 dev/ic/midway.c sc->sc_dev.dv_xname, reg);
reg 1459 dev/ic/midway.c u_int32_t reg = EN_READ(sc, MID_VC(vc));
reg 1461 dev/ic/midway.c reg = MIDV_SETMODE(reg, MIDV_TRASH);
reg 1462 dev/ic/midway.c EN_WRITE(sc, MID_VC(vc), reg);
reg 2345 dev/ic/midway.c u_int32_t reg, kick, val, mask, chip, vci, slot, dtq, drq;
reg 2348 dev/ic/midway.c reg = EN_READ(sc, MID_INTACK);
reg 2350 dev/ic/midway.c if ((reg & MID_INT_ANY) == 0)
reg 2354 dev/ic/midway.c printf("%s: interrupt=0x%b\n", sc->sc_dev.dv_xname, reg, MID_INTBITS);
reg 2361 dev/ic/midway.c if ((reg & (MID_INT_IDENT|MID_INT_LERR|MID_INT_DMA_ERR|MID_INT_SUNI)) != 0) {
reg 2363 dev/ic/midway.c sc->sc_dev.dv_xname, reg, MID_INTBITS);
reg 2381 dev/ic/midway.c if (reg & MID_INT_TX) { /* TX done! */
reg 2389 dev/ic/midway.c if (reg & MID_TXCHAN(lcv)) {
reg 2406 dev/ic/midway.c if (reg & MID_INT_DMA_TX) { /* TX DMA done! */
reg 2467 dev/ic/midway.c if (reg & MID_INT_DMA_RX) {
reg 2538 dev/ic/midway.c if (reg & MID_INT_SERVICE) {
reg 2588 dev/ic/midway.c if (reg & MID_INT_DMA_OVR) {
reg 2594 dev/ic/midway.c reg = EN_READ(sc, MID_STAT);
reg 2596 dev/ic/midway.c sc->otrash += MID_OTRASH(reg);
reg 2597 dev/ic/midway.c sc->vtrash += MID_VTRASH(reg);
reg 3041 dev/ic/midway.c u_int32_t ptr, reg;
reg 3159 dev/ic/midway.c reg = EN_READ(sc, ptr);
reg 3161 dev/ic/midway.c sc->dtq[MID_DTQ_A2REG(ptr)], MID_DMA_CNT(reg), MID_DMA_TXCHAN(reg),
reg 3162 dev/ic/midway.c (reg & MID_DMA_END) != 0, MID_DMA_TYPE(reg), EN_READ(sc, ptr+4));
reg 3172 dev/ic/midway.c reg = EN_READ(sc, ptr);
reg 3174 dev/ic/midway.c sc->drq[MID_DRQ_A2REG(ptr)], MID_DMA_CNT(reg), MID_DMA_RXVCI(reg),
reg 3175 dev/ic/midway.c (reg & MID_DMA_END) != 0, MID_DMA_TYPE(reg), EN_READ(sc, ptr+4));
reg 3202 dev/ic/midway.c u_int32_t reg;
reg 3216 dev/ic/midway.c reg = EN_READ(sc, addr);
reg 3217 dev/ic/midway.c printf("mem[0x%x] = 0x%x\n", addr, reg);
reg 662 dev/ic/mpi.c u_int32_t reg;
reg 665 dev/ic/mpi.c while ((reg = mpi_pop_reply(sc)) != 0xffffffff) {
reg 666 dev/ic/mpi.c mpi_reply(sc, reg);
reg 674 dev/ic/mpi.c mpi_reply(struct mpi_softc *sc, u_int32_t reg)
reg 683 dev/ic/mpi.c DNPRINTF(MPI_D_INTR, "%s: mpi_reply reg: 0x%08x\n", DEVNAME(sc), reg);
reg 685 dev/ic/mpi.c if (reg & MPI_REPLY_QUEUE_ADDRESS) {
reg 690 dev/ic/mpi.c reply_dva = (reg & MPI_REPLY_QUEUE_ADDRESS_MASK) << 1;
reg 703 dev/ic/mpi.c switch (reg & MPI_REPLY_QUEUE_TYPE_MASK) {
reg 705 dev/ic/mpi.c id = reg & MPI_REPLY_QUEUE_CONTEXT;
reg 945 dev/ic/mpi.c u_int32_t reg;
reg 952 dev/ic/mpi.c reg = mpi_pop_reply(sc);
reg 953 dev/ic/mpi.c if (reg == 0xffffffff) {
reg 961 dev/ic/mpi.c id = mpi_reply(sc, reg);
reg 220 dev/ic/mtd8xx.c mtd_mii_command(struct mtd_softc *sc, int opcode, int phy, int reg)
reg 235 dev/ic/mtd8xx.c data = opcode | (phy << 7) | (reg << 2);
reg 255 dev/ic/mtd8xx.c mtd_miibus_readreg(struct device *self, int phy, int reg)
reg 260 dev/ic/mtd8xx.c return (phy ? 0 : (int)CSR_READ_2(MTD_PHYCSR + (reg << 1)));
reg 264 dev/ic/mtd8xx.c miir = mtd_mii_command(sc, MII_OPCODE_RD, phy, reg);
reg 284 dev/ic/mtd8xx.c mtd_miibus_writereg(struct device *self, int phy, int reg, int val)
reg 290 dev/ic/mtd8xx.c CSR_WRITE_2(MTD_PHYCSR + (reg << 1), val);
reg 294 dev/ic/mtd8xx.c miir = mtd_mii_command(sc, MII_OPCODE_WR, phy, reg);
reg 200 dev/ic/mtd8xxreg.h #define CSR_READ_1(reg) bus_space_read_1(sc->sc_bust, sc->sc_bush, reg)
reg 201 dev/ic/mtd8xxreg.h #define CSR_WRITE_1(reg, val) \
reg 202 dev/ic/mtd8xxreg.h bus_space_write_1(sc->sc_bust, sc->sc_bush, reg, val)
reg 204 dev/ic/mtd8xxreg.h #define CSR_READ_2(reg) bus_space_read_2(sc->sc_bust, sc->sc_bush, reg)
reg 205 dev/ic/mtd8xxreg.h #define CSR_WRITE_2(reg, vat) \
reg 206 dev/ic/mtd8xxreg.h bus_space_write_2(sc->sc_bust, sc->sc_bush, reg, val)
reg 208 dev/ic/mtd8xxreg.h #define CSR_READ_4(reg) bus_space_read_4(sc->sc_bust, sc->sc_bush, reg)
reg 209 dev/ic/mtd8xxreg.h #define CSR_WRITE_4(reg, val) \
reg 210 dev/ic/mtd8xxreg.h bus_space_write_4(sc->sc_bust, sc->sc_bush, reg, val)
reg 212 dev/ic/mtd8xxreg.h #define CSR_SETBIT(reg, val) CSR_WRITE_4(reg, CSR_READ_4(reg) | (val))
reg 213 dev/ic/mtd8xxreg.h #define CSR_CLRBIT(reg, val) CSR_WRITE_4(reg, CSR_READ_4(reg) & ~(val))
reg 400 dev/ic/ncr53c9xvar.h #define NCR_READ_REG(sc, reg) \
reg 401 dev/ic/ncr53c9xvar.h (*(sc)->sc_glue->gl_read_reg)((sc), (reg))
reg 402 dev/ic/ncr53c9xvar.h #define NCR_WRITE_REG(sc, reg, val) \
reg 403 dev/ic/ncr53c9xvar.h (*(sc)->sc_glue->gl_write_reg)((sc), (reg), (val))
reg 64 dev/ic/osiopvar.h #define osiop_read_1(sc, reg) \
reg 65 dev/ic/osiopvar.h bus_space_read_1((sc)->sc_bst, (sc)->sc_reg, reg)
reg 66 dev/ic/osiopvar.h #define osiop_write_1(sc, reg, val) \
reg 67 dev/ic/osiopvar.h bus_space_write_1((sc)->sc_bst, (sc)->sc_reg, reg, val)
reg 69 dev/ic/osiopvar.h #define osiop_read_4(sc, reg) \
reg 70 dev/ic/osiopvar.h bus_space_read_4((sc)->sc_bst, (sc)->sc_reg, reg)
reg 71 dev/ic/osiopvar.h #define osiop_write_4(sc, reg, val) \
reg 72 dev/ic/osiopvar.h bus_space_write_4((sc)->sc_bst, (sc)->sc_reg, reg, val)
reg 58 dev/ic/pcdisplayvar.h static inline u_int8_t _pcdisplay_6845_read(ph, reg)
reg 60 dev/ic/pcdisplayvar.h int reg;
reg 62 dev/ic/pcdisplayvar.h bus_space_write_1(ph->ph_iot, ph->ph_ioh_6845, MC6845_INDEX, reg);
reg 66 dev/ic/pcdisplayvar.h static inline void _pcdisplay_6845_write(ph, reg, val)
reg 68 dev/ic/pcdisplayvar.h int reg;
reg 71 dev/ic/pcdisplayvar.h bus_space_write_1(ph->ph_iot, ph->ph_ioh_6845, MC6845_INDEX, reg);
reg 75 dev/ic/pcdisplayvar.h #define pcdisplay_6845_read(ph, reg) \
reg 76 dev/ic/pcdisplayvar.h _pcdisplay_6845_read(ph, offsetof(struct reg_mc6845, reg))
reg 77 dev/ic/pcdisplayvar.h #define pcdisplay_6845_write(ph, reg, val) \
reg 78 dev/ic/pcdisplayvar.h _pcdisplay_6845_write(ph, offsetof(struct reg_mc6845, reg), val)
reg 297 dev/ic/pgt.c int error, reg, dirreg, fwoff, ucodeoff, fwlen;
reg 328 dev/ic/pgt.c reg = PGT_FIRMWARE_INTERNAL_OFFSET;
reg 330 dev/ic/pgt.c pgt_write_4_flush(sc, PGT_REG_DIR_MEM_BASE, reg);
reg 342 dev/ic/pgt.c reg += 4;
reg 349 dev/ic/pgt.c reg += 4;
reg 356 dev/ic/pgt.c reg = pgt_read_4(sc, PGT_REG_CTRL_STAT);
reg 357 dev/ic/pgt.c reg &= ~(PGT_CTRL_STAT_RESET | PGT_CTRL_STAT_CLOCKRUN);
reg 358 dev/ic/pgt.c reg |= PGT_CTRL_STAT_RAMBOOT;
reg 359 dev/ic/pgt.c pgt_write_4_flush(sc, PGT_REG_CTRL_STAT, reg);
reg 363 dev/ic/pgt.c reg |= PGT_CTRL_STAT_RESET;
reg 364 dev/ic/pgt.c pgt_write_4(sc, PGT_REG_CTRL_STAT, reg);
reg 368 dev/ic/pgt.c reg &= ~PGT_CTRL_STAT_RESET;
reg 369 dev/ic/pgt.c pgt_write_4(sc, PGT_REG_CTRL_STAT, reg);
reg 660 dev/ic/pgt.c uint32_t reg;
reg 662 dev/ic/pgt.c reg = pgt_read_4(sc, PGT_REG_CTRL_STAT);
reg 663 dev/ic/pgt.c reg &= ~(PGT_CTRL_STAT_RESET | PGT_CTRL_STAT_RAMBOOT);
reg 664 dev/ic/pgt.c pgt_write_4(sc, PGT_REG_CTRL_STAT, reg);
reg 668 dev/ic/pgt.c reg |= PGT_CTRL_STAT_RESET;
reg 669 dev/ic/pgt.c pgt_write_4(sc, PGT_REG_CTRL_STAT, reg);
reg 673 dev/ic/pgt.c reg &= ~PGT_CTRL_STAT_RESET;
reg 674 dev/ic/pgt.c pgt_write_4(sc, PGT_REG_CTRL_STAT, reg);
reg 1191 dev/ic/pgt.c u_int32_t reg;
reg 1208 dev/ic/pgt.c reg = pgt_read_4(sc, PGT_REG_CTRL_STAT);
reg 1209 dev/ic/pgt.c if (reg & PGT_CTRL_STAT_SLEEPMODE)
reg 1212 dev/ic/pgt.c reg = pgt_read_4(sc, PGT_REG_INT_STAT);
reg 1213 dev/ic/pgt.c if (reg == 0)
reg 1216 dev/ic/pgt.c pgt_write_4_flush(sc, PGT_REG_INT_ACK, reg);
reg 1217 dev/ic/pgt.c if (reg & PGT_INT_STAT_INIT)
reg 1219 dev/ic/pgt.c if (reg & PGT_INT_STAT_UPDATE) {
reg 1234 dev/ic/pgt.c if (reg & PGT_INT_STAT_SLEEP && !(reg & PGT_INT_STAT_WAKEUP))
reg 1236 dev/ic/pgt.c if (reg & PGT_INT_STAT_WAKEUP)
reg 1244 dev/ic/pgt.c if (reg & ~PGT_INT_STAT_SOURCES && sc->sc_debug & SC_DEBUG_UNEXPECTED) {
reg 1247 dev/ic/pgt.c reg & ~PGT_INT_STAT_SOURCES,
reg 1775 dev/ic/pgt.c uint32_t reg;
reg 1785 dev/ic/pgt.c reg = pgt_read_4(sc, PGT_REG_CTRL_STAT);
reg 1786 dev/ic/pgt.c if (!(reg & PGT_CTRL_STAT_SLEEPMODE))
reg 1789 dev/ic/pgt.c if (!(reg & PGT_CTRL_STAT_SLEEPMODE)) {
reg 323 dev/ic/re.c re_gmii_readreg(struct device *self, int phy, int reg)
reg 334 dev/ic/re.c if (reg == RL_GMEDIASTAT) {
reg 339 dev/ic/re.c CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
reg 358 dev/ic/re.c re_gmii_writereg(struct device *dev, int phy, int reg, int data)
reg 364 dev/ic/re.c CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
reg 380 dev/ic/re.c re_miibus_readreg(struct device *dev, int phy, int reg)
reg 390 dev/ic/re.c rval = re_gmii_readreg(dev, phy, reg);
reg 400 dev/ic/re.c switch(reg) {
reg 431 dev/ic/re.c printf("%s: bad phy register %x\n", sc->sc_dev.dv_xname, reg);
reg 445 dev/ic/re.c re_miibus_writereg(struct device *dev, int phy, int reg, int data)
reg 454 dev/ic/re.c re_gmii_writereg(dev, phy, reg, data);
reg 464 dev/ic/re.c switch(reg) {
reg 490 dev/ic/re.c printf("%s: bad phy register %x\n", sc->sc_dev.dv_xname, reg);
reg 151 dev/ic/rt2560.c uint32_t reg;
reg 158 dev/ic/rt2560.c uint8_t reg;
reg 2083 dev/ic/rt2560.c rt2560_bbp_write(struct rt2560_softc *sc, uint8_t reg, uint8_t val)
reg 2098 dev/ic/rt2560.c tmp = RT2560_BBP_WRITE | RT2560_BBP_BUSY | reg << 8 | val;
reg 2101 dev/ic/rt2560.c DPRINTFN(15, ("BBP R%u <- 0x%02x\n", reg, val));
reg 2105 dev/ic/rt2560.c rt2560_bbp_read(struct rt2560_softc *sc, uint8_t reg)
reg 2110 dev/ic/rt2560.c val = RT2560_BBP_BUSY | reg << 8;
reg 2125 dev/ic/rt2560.c rt2560_rf_write(struct rt2560_softc *sc, uint8_t reg, uint32_t val)
reg 2141 dev/ic/rt2560.c (reg & 0x3);
reg 2145 dev/ic/rt2560.c sc->rf_regs[reg] = val;
reg 2147 dev/ic/rt2560.c DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff));
reg 2536 dev/ic/rt2560.c sc->bbp_prom[i].reg = val >> 8;
reg 2567 dev/ic/rt2560.c rt2560_bbp_write(sc, rt2560_def_bbp[i].reg,
reg 2573 dev/ic/rt2560.c if (sc->bbp_prom[i].reg == 0xff)
reg 2575 dev/ic/rt2560.c rt2560_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);
reg 2625 dev/ic/rt2560.c RAL_WRITE(sc, rt2560_def_mac[i].reg, rt2560_def_mac[i].val);
reg 303 dev/ic/rt2560reg.h #define RAL_READ(sc, reg) \
reg 304 dev/ic/rt2560reg.h bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
reg 306 dev/ic/rt2560reg.h #define RAL_WRITE(sc, reg, val) \
reg 307 dev/ic/rt2560reg.h bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
reg 136 dev/ic/rt2560var.h uint8_t reg;
reg 160 dev/ic/rt2661.c uint32_t reg;
reg 167 dev/ic/rt2661.c uint8_t reg;
reg 1927 dev/ic/rt2661.c rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val)
reg 1942 dev/ic/rt2661.c tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val;
reg 1945 dev/ic/rt2661.c DPRINTFN(15, ("BBP R%u <- 0x%02x\n", reg, val));
reg 1949 dev/ic/rt2661.c rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg)
reg 1964 dev/ic/rt2661.c val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8;
reg 1979 dev/ic/rt2661.c rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val)
reg 1995 dev/ic/rt2661.c (reg & 3);
reg 1999 dev/ic/rt2661.c sc->rf_regs[reg] = val;
reg 2001 dev/ic/rt2661.c DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff));
reg 2380 dev/ic/rt2661.c sc->bbp_prom[i].reg = val >> 8;
reg 2382 dev/ic/rt2661.c DPRINTF(("BBP R%d=%02x\n", sc->bbp_prom[i].reg,
reg 2407 dev/ic/rt2661.c rt2661_bbp_write(sc, rt2661_def_bbp[i].reg,
reg 2413 dev/ic/rt2661.c if (sc->bbp_prom[i].reg == 0)
reg 2415 dev/ic/rt2661.c rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);
reg 2519 dev/ic/rt2661.c RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val);
reg 317 dev/ic/rt2661reg.h #define RAL_READ(sc, reg) \
reg 318 dev/ic/rt2661reg.h bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
reg 324 dev/ic/rt2661reg.h #define RAL_WRITE(sc, reg, val) \
reg 325 dev/ic/rt2661reg.h bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
reg 327 dev/ic/rt2661reg.h #define RAL_WRITE_1(sc, reg, val) \
reg 328 dev/ic/rt2661reg.h bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
reg 330 dev/ic/rt2661reg.h #define RAL_RW_BARRIER_1(sc, reg) \
reg 331 dev/ic/rt2661reg.h bus_space_barrier((sc)->sc_st, (sc)->sc_sh, (reg), 1, \
reg 133 dev/ic/rt2661var.h uint8_t reg;
reg 122 dev/ic/rtl80x9.c u_int8_t reg;
reg 132 dev/ic/rtl80x9.c reg = NIC_GET(sc->sc_regt, sc->sc_regh, NERTL_RTL3_CONFIG2);
reg 133 dev/ic/rtl80x9.c reg &= ~(RTL3_CONFIG2_PL1|RTL3_CONFIG2_PL0);
reg 148 dev/ic/rtl80x9.c reg |= RTL3_CONFIG2_PL1|RTL3_CONFIG2_PL0;
reg 151 dev/ic/rtl80x9.c NIC_PUT(sc->sc_regt, sc->sc_regh, NERTL_RTL3_CONFIG2, reg);
reg 154 dev/ic/rtl80x9.c reg = NIC_GET(sc->sc_regt, sc->sc_regh, NERTL_RTL3_CONFIG3);
reg 156 dev/ic/rtl80x9.c reg |= RTL3_CONFIG3_FUDUP;
reg 158 dev/ic/rtl80x9.c reg &= ~RTL3_CONFIG3_FUDUP;
reg 159 dev/ic/rtl80x9.c NIC_PUT(sc->sc_regt, sc->sc_regh, NERTL_RTL3_CONFIG3, reg);
reg 1367 dev/ic/rtl81x9.c rl_miibus_readreg(self, phy, reg)
reg 1369 dev/ic/rtl81x9.c int phy, reg;
reg 1383 dev/ic/rtl81x9.c switch (reg) {
reg 1412 dev/ic/rtl81x9.c frame.mii_regaddr = reg;
reg 1419 dev/ic/rtl81x9.c rl_miibus_writereg(self, phy, reg, val)
reg 1421 dev/ic/rtl81x9.c int phy, reg, val;
reg 1431 dev/ic/rtl81x9.c switch (reg) {
reg 1457 dev/ic/rtl81x9.c frame.mii_regaddr = reg;
reg 4238 dev/ic/rtw.c #define RTW_BBP_WRITE_OR_RETURN(reg, val) \
reg 4239 dev/ic/rtw.c if ((rc = rtw_bbp_write(regs, reg, val)) != 0) \
reg 4835 dev/ic/rtw.c u_int32_t mask, reg;
reg 4843 dev/ic/rtw.c reg = RTW8180_PHYCFG_HST;
reg 4844 dev/ic/rtw.c RTW_WRITE(regs, RTW8180_PHYCFG, reg);
reg 4858 dev/ic/rtw.c reg |= RTW8180_PHYCFG_HST_DATA;
reg 4860 dev/ic/rtw.c reg &= ~RTW8180_PHYCFG_HST_DATA;
reg 4862 dev/ic/rtw.c reg |= RTW8180_PHYCFG_HST_CLK;
reg 4863 dev/ic/rtw.c RTW_WRITE(regs, RTW8180_PHYCFG, reg);
reg 4868 dev/ic/rtw.c reg &= ~RTW8180_PHYCFG_HST_CLK;
reg 4869 dev/ic/rtw.c RTW_WRITE(regs, RTW8180_PHYCFG, reg);
reg 4878 dev/ic/rtw.c reg |= RTW8180_PHYCFG_HST_EN;
reg 4879 dev/ic/rtw.c KASSERT((reg & RTW8180_PHYCFG_HST_CLK) == 0);
reg 4880 dev/ic/rtw.c RTW_WRITE(regs, RTW8180_PHYCFG, reg);
reg 4923 dev/ic/rtw.c reg |= RTW8180_PHYCFG_HST_DATA;
reg 4925 dev/ic/rtw.c reg &= ~RTW8180_PHYCFG_HST_DATA;
reg 4927 dev/ic/rtw.c reg |= RTW8180_PHYCFG_HST_CLK;
reg 4928 dev/ic/rtw.c RTW_WRITE(regs, RTW8180_PHYCFG, reg);
reg 4933 dev/ic/rtw.c reg &= ~RTW8180_PHYCFG_HST_CLK;
reg 4934 dev/ic/rtw.c RTW_WRITE(regs, RTW8180_PHYCFG, reg);
reg 4952 dev/ic/rtw.c rtw_rf_macbangbits(struct rtw_regs *regs, u_int32_t reg)
reg 4956 dev/ic/rtw.c RTW_DPRINTF(RTW_DEBUG_PHY, ("%s: %#08x\n", __func__, reg));
reg 4958 dev/ic/rtw.c RTW_WRITE(regs, RTW8180_PHYCFG, RTW8180_PHYCFG_MAC_POLL | reg);
reg 5088 dev/ic/rtw.c u_int32_t reg;
reg 5095 dev/ic/rtw.c reg = rtw_grf5101_mac_crypt(addr, val);
reg 5098 dev/ic/rtw.c reg = rtw_maxim_swizzle(addr, val);
reg 5107 dev/ic/rtw.c reg = LSHIFT(addr, RTW8180_PHYCFG_MAC_PHILIPS_ADDR_MASK) |
reg 5115 dev/ic/rtw.c reg |= RTW8180_PHYCFG_MAC_RFTYPE_RFMD;
reg 5118 dev/ic/rtw.c reg |= RTW8180_PHYCFG_MAC_RFTYPE_INTERSIL;
reg 5121 dev/ic/rtw.c reg |= RTW8180_PHYCFG_MAC_RFTYPE_PHILIPS;
reg 5128 dev/ic/rtw.c return rtw_rf_macbangbits(&sc->sc_regs, reg);
reg 76 dev/ic/rtwreg.h #define MASK_AND_REPLACE(reg, val, mask) ((reg & ~mask) | LSHIFT(val, mask))
reg 1140 dev/ic/rtwreg.h #define RTW_ISSET(regs, reg, mask) \
reg 1141 dev/ic/rtwreg.h (RTW_READ((regs), (reg)) & (mask))
reg 1143 dev/ic/rtwreg.h #define RTW_CLR(regs, reg, mask) \
reg 1144 dev/ic/rtwreg.h RTW_WRITE((regs), (reg), RTW_READ((regs), (reg)) & ~(mask))
reg 100 dev/ic/s3_617.h #define SET_FIELD(reg, field) ((reg & ~(field##_MASK)) | field)
reg 101 dev/ic/s3_617.h #define GET_FIELD(reg, field) (reg & ~(field##_MASK))
reg 1145 dev/ic/smc83c170.c u_int32_t reg;
reg 1168 dev/ic/smc83c170.c reg = bus_space_read_4(st, sh, EPIC_GENCTL);
reg 1169 dev/ic/smc83c170.c bus_space_write_4(st, sh, EPIC_GENCTL, reg & ~GENCTL_INTENA);
reg 1202 dev/ic/smc83c170.c u_int16_t reg;
reg 1222 dev/ic/smc83c170.c reg = EECTL_ENABLE|EECTL_EECS;
reg 1224 dev/ic/smc83c170.c reg |= EECTL_EEDI;
reg 1225 dev/ic/smc83c170.c bus_space_write_4(st, sh, EPIC_EECTL, reg);
reg 1227 dev/ic/smc83c170.c bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK);
reg 1229 dev/ic/smc83c170.c bus_space_write_4(st, sh, EPIC_EECTL, reg);
reg 1235 dev/ic/smc83c170.c reg = EECTL_ENABLE|EECTL_EECS;
reg 1237 dev/ic/smc83c170.c reg |= EECTL_EEDI;
reg 1238 dev/ic/smc83c170.c bus_space_write_4(st, sh, EPIC_EECTL, reg);
reg 1240 dev/ic/smc83c170.c bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK);
reg 1242 dev/ic/smc83c170.c bus_space_write_4(st, sh, EPIC_EECTL, reg);
reg 1247 dev/ic/smc83c170.c reg = EECTL_ENABLE|EECTL_EECS;
reg 1250 dev/ic/smc83c170.c bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK);
reg 1254 dev/ic/smc83c170.c bus_space_write_4(st, sh, EPIC_EECTL, reg);
reg 1400 dev/ic/smc83c170.c epic_mii_read(struct device *self, int phy, int reg)
reg 1408 dev/ic/smc83c170.c MMCTL_ARG(phy, reg, MMCTL_READ));
reg 1421 dev/ic/smc83c170.c epic_mii_write(struct device *self, int phy, int reg, int val)
reg 1430 dev/ic/smc83c170.c MMCTL_ARG(phy, reg, MMCTL_WRITE));
reg 281 dev/ic/smc83c170reg.h #define MMCTL_ARG(phy, reg, cmd) (((phy) << 9) | ((reg) << 4) | (cmd))
reg 1301 dev/ic/smc91cxx.c smc91cxx_mii_readreg(self, phy, reg)
reg 1303 dev/ic/smc91cxx.c int phy, reg;
reg 1310 dev/ic/smc91cxx.c val = mii_bitbang_readreg(self, &smc91cxx_mii_bitbang_ops, phy, reg);
reg 1318 dev/ic/smc91cxx.c smc91cxx_mii_writereg(self, phy, reg, val)
reg 1320 dev/ic/smc91cxx.c int phy, reg, val;
reg 1326 dev/ic/smc91cxx.c mii_bitbang_writereg(self, &smc91cxx_mii_bitbang_ops, phy, reg, val);
reg 83 dev/ic/tc921x.c tc921x_decode_freq(u_int32_t reg) {
reg 84 dev/ic/tc921x.c return (reg & TC921X_D0_FREQ_DIVIDER) * 10 - IF_FREQ;
reg 115 dev/ic/tc921x.c tc921x_write_addr(struct tc921x_t *c, u_int8_t addr, u_int32_t reg) {
reg 130 dev/ic/tc921x.c __tc921x_write_burst(TC921X_REGISTER_LENGTH, reg, c, 1);
reg 323 dev/ic/tcic2.c int i, reg;
reg 338 dev/ic/tcic2.c reg = TCIC_WAIT_SYNC | TCIC_WAIT_CCLK | TCIC_WAIT_RISING;
reg 339 dev/ic/tcic2.c reg |= (tcic_ns2wscnt(250) & TCIC_WAIT_COUNT_MASK);
reg 340 dev/ic/tcic2.c tcic_write_aux_1(sc->iot, sc->ioh, TCIC_AR_WCTL, TCIC_R_WCTL_WAIT, reg);
reg 341 dev/ic/tcic2.c reg = TCIC_SYSCFG_MPSEL_RI | TCIC_SYSCFG_MCSFULL;
reg 342 dev/ic/tcic2.c tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, reg);
reg 343 dev/ic/tcic2.c reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_ILOCK);
reg 344 dev/ic/tcic2.c reg |= TCIC_ILOCK_HOLD_CCLK;
reg 345 dev/ic/tcic2.c tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_ILOCK, reg);
reg 358 dev/ic/tcic2.c reg = tcic_read_1(&sc->handle[0], TCIC_R_IENA);
reg 360 dev/ic/tcic2.c (reg & ~TCIC_IENA_CFG_MASK) | TCIC_IENA_CFG_HIGH);
reg 361 dev/ic/tcic2.c reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG);
reg 363 dev/ic/tcic2.c (reg & ~TCIC_SYSCFG_IRQ_MASK) | tcic_irqmap[sc->irq]);
reg 379 dev/ic/tcic2.c reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG);
reg 380 dev/ic/tcic2.c reg &= ~TCIC_SYSCFG_AUTOBUSY;
reg 381 dev/ic/tcic2.c tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, reg);
reg 519 dev/ic/tcic2.c int reg;
reg 525 dev/ic/tcic2.c reg = tcic_read_ind_2(h, TCIC_IR_SCF2_N(h->sock));
reg 526 dev/ic/tcic2.c tcic_write_ind_2(h, TCIC_IR_SCF2_N(h->sock), reg & ~TCIC_SCF2_MCD);
reg 529 dev/ic/tcic2.c reg = tcic_read_2(h, TCIC_R_IENA);
reg 530 dev/ic/tcic2.c tcic_write_2(h, TCIC_R_IENA, reg |= TCIC_IENA_CDCHG);
reg 533 dev/ic/tcic2.c h->sstat = reg = tcic_read_1(h, TCIC_R_SSTAT) & TCIC_SSTAT_STAT_MASK;
reg 534 dev/ic/tcic2.c if (reg & TCIC_SSTAT_CD)
reg 758 dev/ic/tcic2.c int val, reg;
reg 776 dev/ic/tcic2.c reg = TCIC_IR_SCF1_N(h->sock);
reg 777 dev/ic/tcic2.c val = tcic_read_ind_2(h, reg);
reg 778 dev/ic/tcic2.c tcic_write_ind_2(h, reg, (val & ~TCIC_SCF1_IRQ_MASK)|TCIC_SCF1_IRQOFF);
reg 779 dev/ic/tcic2.c reg = TCIC_IR_SCF2_N(h->sock);
reg 780 dev/ic/tcic2.c val = tcic_read_ind_2(h, reg);
reg 781 dev/ic/tcic2.c tcic_write_ind_2(h, reg,
reg 867 dev/ic/tcic2.c int reg, hwwin, wscnt;
reg 885 dev/ic/tcic2.c reg = ((h->mem[win].addr >> TCIC_MEM_SHIFT) &
reg 888 dev/ic/tcic2.c reg = ((h->mem[win].addr >> TCIC_MEM_SHIFT) &
reg 891 dev/ic/tcic2.c tcic_write_ind_2(h, TCIC_WR_MBASE_N(hwwin), reg);
reg 894 dev/ic/tcic2.c reg = 0;
reg 895 dev/ic/tcic2.c reg = ((h->mem[win].offset >> TCIC_MEM_SHIFT) & TCIC_MMAP_ADDR_MASK);
reg 896 dev/ic/tcic2.c reg |= (kind == PCMCIA_MEM_ATTR) ? TCIC_MMAP_ATTR : 0;
reg 898 dev/ic/tcic2.c win, hwwin, reg));
reg 899 dev/ic/tcic2.c tcic_write_ind_2(h, TCIC_WR_MMAP_N(hwwin), reg);
reg 904 dev/ic/tcic2.c reg = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin)) & TCIC_MCTL_WSCNT_MASK;
reg 905 dev/ic/tcic2.c reg |= TCIC_MCTL_ENA|TCIC_MCTL_QUIET;
reg 906 dev/ic/tcic2.c reg |= mem8 ? TCIC_MCTL_B8 : 0;
reg 907 dev/ic/tcic2.c reg |= (h->sock << TCIC_MCTL_SS_SHIFT) & TCIC_MCTL_SS_MASK;
reg 924 dev/ic/tcic2.c reg |= wscnt & TCIC_MCTL_WSCNT_MASK;
reg 926 dev/ic/tcic2.c tcic_write_ind_2(h, TCIC_WR_MCTL_N(hwwin), reg);
reg 1022 dev/ic/tcic2.c int reg, hwwin;
reg 1028 dev/ic/tcic2.c reg = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin));
reg 1029 dev/ic/tcic2.c reg &= ~TCIC_MCTL_ENA;
reg 1030 dev/ic/tcic2.c tcic_write_ind_2(h, TCIC_WR_MCTL_N(hwwin), reg);
reg 1124 dev/ic/tcic2.c int reg, size2, iotiny, wbase, hwwin, wscnt;
reg 1151 dev/ic/tcic2.c reg = TCIC_ICTL_ENA | TCIC_ICTL_QUIET;
reg 1152 dev/ic/tcic2.c reg |= (h->sock << TCIC_ICTL_SS_SHIFT) & TCIC_ICTL_SS_MASK;
reg 1153 dev/ic/tcic2.c reg |= iotiny | tcic_iowidth_map[h->io[win].width];
reg 1155 dev/ic/tcic2.c reg |= TCIC_ICTL_PASS16;
reg 1161 dev/ic/tcic2.c reg |= wscnt & TCIC_ICTL_WSCNT_MASK;
reg 1162 dev/ic/tcic2.c tcic_write_ind_2(h, TCIC_WR_ICTL_N(hwwin), reg);
reg 1238 dev/ic/tcic2.c int reg, hwwin;
reg 1244 dev/ic/tcic2.c reg = tcic_read_ind_2(h, TCIC_WR_ICTL_N(hwwin));
reg 1245 dev/ic/tcic2.c reg &= ~TCIC_ICTL_ENA;
reg 1246 dev/ic/tcic2.c tcic_write_ind_2(h, TCIC_WR_ICTL_N(hwwin), reg);
reg 1256 dev/ic/tcic2.c int cardtype, reg, win;
reg 1266 dev/ic/tcic2.c reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK);
reg 1267 dev/ic/tcic2.c reg |= TCIC_ILOCK_CWAIT;
reg 1268 dev/ic/tcic2.c reg &= ~(TCIC_ILOCK_CRESET|TCIC_ILOCK_CRESENA);
reg 1269 dev/ic/tcic2.c tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg);
reg 1275 dev/ic/tcic2.c reg = TCIC_PWR_VCC_N(h->sock) | TCIC_PWR_VPP_N(h->sock) | h->sc->pwrena;
reg 1277 dev/ic/tcic2.c reg |= TCIC_PWR_VCC5V;
reg 1278 dev/ic/tcic2.c tcic_write_1(h, TCIC_R_PWR, reg);
reg 1282 dev/ic/tcic2.c reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK);
reg 1283 dev/ic/tcic2.c reg |= TCIC_ILOCK_CRESENA;
reg 1284 dev/ic/tcic2.c tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg);
reg 1286 dev/ic/tcic2.c reg |= TCIC_ILOCK_CRESET;
reg 1287 dev/ic/tcic2.c tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg);
reg 1293 dev/ic/tcic2.c reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK);
reg 1294 dev/ic/tcic2.c reg &= ~(TCIC_ILOCK_CRESET);
reg 1295 dev/ic/tcic2.c tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg);
reg 1320 dev/ic/tcic2.c reg = tcic_read_ind_2(h, TCIC_IR_SCF1_N(h->sock));
reg 1321 dev/ic/tcic2.c reg &= ~TCIC_SCF1_IRQ_MASK;
reg 1323 dev/ic/tcic2.c reg = 0;
reg 1325 dev/ic/tcic2.c reg |= ((cardtype == PCMCIA_IFTYPE_IO) ?
reg 1327 dev/ic/tcic2.c reg |= tcic_irqmap[h->ih_irq]; /* enable interrupts */
reg 1328 dev/ic/tcic2.c reg &= ~TCIC_SCF1_IRQOD;
reg 1329 dev/ic/tcic2.c tcic_write_ind_2(h, TCIC_IR_SCF1_N(h->sock), reg);
reg 1333 dev/ic/tcic2.c ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg));
reg 188 dev/ic/tcic2var.h tcic_read_1(h, reg)
reg 190 dev/ic/tcic2var.h int reg;
reg 192 dev/ic/tcic2var.h return (bus_space_read_1(h->sc->iot, h->sc->ioh, reg));
reg 197 dev/ic/tcic2var.h tcic_read_2(h, reg)
reg 199 dev/ic/tcic2var.h int reg;
reg 201 dev/ic/tcic2var.h return (bus_space_read_2(h->sc->iot, h->sc->ioh, reg));
reg 206 dev/ic/tcic2var.h tcic_read_4(h, reg)
reg 208 dev/ic/tcic2var.h int reg;
reg 211 dev/ic/tcic2var.h val = bus_space_read_2(h->sc->iot, h->sc->ioh, reg);
reg 212 dev/ic/tcic2var.h val |= bus_space_read_2(h->sc->iot, h->sc->ioh, reg+2) << 16;
reg 218 dev/ic/tcic2var.h tcic_write_1(h, reg, data)
reg 220 dev/ic/tcic2var.h int reg;
reg 223 dev/ic/tcic2var.h bus_space_write_1(h->sc->iot, h->sc->ioh, reg, (data));
reg 228 dev/ic/tcic2var.h tcic_write_2(h, reg, data)
reg 230 dev/ic/tcic2var.h int reg;
reg 233 dev/ic/tcic2var.h bus_space_write_2(h->sc->iot, h->sc->ioh, reg, (data));
reg 238 dev/ic/tcic2var.h tcic_write_4(h, reg, data)
reg 240 dev/ic/tcic2var.h int reg;
reg 243 dev/ic/tcic2var.h bus_space_write_2(h->sc->iot, h->sc->ioh, reg, (data));
reg 244 dev/ic/tcic2var.h bus_space_write_2(h->sc->iot, h->sc->ioh, reg+2, (data)>>16);
reg 249 dev/ic/tcic2var.h tcic_read_ind_2(h, reg)
reg 251 dev/ic/tcic2var.h int reg;
reg 255 dev/ic/tcic2var.h tcic_write_4(h, TCIC_R_ADDR, reg|TCIC_ADDR_INDREG);
reg 263 dev/ic/tcic2var.h tcic_write_ind_2(h, reg, data)
reg 265 dev/ic/tcic2var.h int reg;
reg 270 dev/ic/tcic2var.h tcic_write_4(h, TCIC_R_ADDR, reg|TCIC_ADDR_INDREG);
reg 307 dev/ic/tcic2var.h tcic_read_aux_1(iot, ioh, auxreg, reg)
reg 310 dev/ic/tcic2var.h int auxreg, reg;
reg 315 dev/ic/tcic2var.h val = bus_space_read_1(iot, ioh, reg);
reg 335 dev/ic/tcic2var.h tcic_write_aux_1(iot, ioh, auxreg, reg, val)
reg 338 dev/ic/tcic2var.h int auxreg, reg, val;
reg 343 dev/ic/tcic2var.h bus_space_write_1(iot, ioh, reg, val);
reg 103 dev/ic/tea5757.c u_int32_t reg;
reg 106 dev/ic/tea5757.c reg = stereo | lock | TEA5757_SEARCH_START;
reg 107 dev/ic/tea5757.c reg |= dir ? TEA5757_SEARCH_UP : TEA5757_SEARCH_DOWN;
reg 108 dev/ic/tea5757.c tea5757_hardware_write(tea, reg);
reg 114 dev/ic/tea5757.c reg = tea->read(tea->iot, tea->ioh, tea->offset);
reg 115 dev/ic/tea5757.c } while ((reg & TEA5757_FREQ) == 0 && ++co < 200);
reg 72 dev/ic/vgavar.h static inline u_int8_t _vga_attr_read(vh, reg)
reg 74 dev/ic/vgavar.h int reg;
reg 81 dev/ic/vgavar.h bus_space_write_1(vh->vh_iot, vh->vh_ioh_vga, VGA_ATC_INDEX, reg);
reg 93 dev/ic/vgavar.h static inline void _vga_attr_write(vh, reg, val)
reg 95 dev/ic/vgavar.h int reg;
reg 101 dev/ic/vgavar.h bus_space_write_1(vh->vh_iot, vh->vh_ioh_vga, VGA_ATC_INDEX, reg);
reg 111 dev/ic/vgavar.h static inline u_int8_t _vga_ts_read(vh, reg)
reg 113 dev/ic/vgavar.h int reg;
reg 115 dev/ic/vgavar.h bus_space_write_1(vh->vh_iot, vh->vh_ioh_vga, VGA_TS_INDEX, reg);
reg 119 dev/ic/vgavar.h static inline void _vga_ts_write(vh, reg, val)
reg 121 dev/ic/vgavar.h int reg;
reg 124 dev/ic/vgavar.h bus_space_write_1(vh->vh_iot, vh->vh_ioh_vga, VGA_TS_INDEX, reg);
reg 128 dev/ic/vgavar.h static inline u_int8_t _vga_gdc_read(vh, reg)
reg 130 dev/ic/vgavar.h int reg;
reg 132 dev/ic/vgavar.h bus_space_write_1(vh->vh_iot, vh->vh_ioh_vga, VGA_GDC_INDEX, reg);
reg 136 dev/ic/vgavar.h static inline void _vga_gdc_write(vh, reg, val)
reg 138 dev/ic/vgavar.h int reg;
reg 141 dev/ic/vgavar.h bus_space_write_1(vh->vh_iot, vh->vh_ioh_vga, VGA_GDC_INDEX, reg);
reg 145 dev/ic/vgavar.h #define vga_attr_read(vh, reg) \
reg 146 dev/ic/vgavar.h _vga_attr_read(vh, offsetof(struct reg_vgaattr, reg))
reg 147 dev/ic/vgavar.h #define vga_attr_write(vh, reg, val) \
reg 148 dev/ic/vgavar.h _vga_attr_write(vh, offsetof(struct reg_vgaattr, reg), val)
reg 149 dev/ic/vgavar.h #define vga_ts_read(vh, reg) \
reg 150 dev/ic/vgavar.h _vga_ts_read(vh, offsetof(struct reg_vgats, reg))
reg 151 dev/ic/vgavar.h #define vga_ts_write(vh, reg, val) \
reg 152 dev/ic/vgavar.h _vga_ts_write(vh, offsetof(struct reg_vgats, reg), val)
reg 153 dev/ic/vgavar.h #define vga_gdc_read(vh, reg) \
reg 154 dev/ic/vgavar.h _vga_gdc_read(vh, offsetof(struct reg_vgagdc, reg))
reg 155 dev/ic/vgavar.h #define vga_gdc_write(vh, reg, val) \
reg 156 dev/ic/vgavar.h _vga_gdc_write(vh, offsetof(struct reg_vgagdc, reg), val)
reg 158 dev/ic/vgavar.h #define vga_6845_read(vh, reg) \
reg 159 dev/ic/vgavar.h pcdisplay_6845_read(&(vh)->vh_ph, reg)
reg 160 dev/ic/vgavar.h #define vga_6845_write(vh, reg, val) \
reg 161 dev/ic/vgavar.h pcdisplay_6845_write(&(vh)->vh_ph, reg, val)
reg 299 dev/ic/wdc.c wdc_default_read_reg(chp, reg)
reg 301 dev/ic/wdc.c enum wdc_regs reg;
reg 304 dev/ic/wdc.c if (reg & _WDC_WRONLY) {
reg 305 dev/ic/wdc.c printf ("wdc_default_read_reg: reading from a write-only register %d\n", reg);
reg 309 dev/ic/wdc.c if (reg & _WDC_AUX)
reg 311 dev/ic/wdc.c reg & _WDC_REGMASK));
reg 314 dev/ic/wdc.c reg & _WDC_REGMASK));
reg 318 dev/ic/wdc.c wdc_default_write_reg(chp, reg, val)
reg 320 dev/ic/wdc.c enum wdc_regs reg;
reg 324 dev/ic/wdc.c if (reg & _WDC_RDONLY) {
reg 325 dev/ic/wdc.c printf ("wdc_default_write_reg: writing to a read-only register %d\n", reg);
reg 329 dev/ic/wdc.c if (reg & _WDC_AUX)
reg 331 dev/ic/wdc.c reg & _WDC_REGMASK, val);
reg 334 dev/ic/wdc.c reg & _WDC_REGMASK, val);
reg 338 dev/ic/wdc.c wdc_default_lba48_write_reg(chp, reg, val)
reg 340 dev/ic/wdc.c enum wdc_regs reg;
reg 344 dev/ic/wdc.c CHP_WRITE_REG(chp, reg, val >> 8);
reg 345 dev/ic/wdc.c CHP_WRITE_REG(chp, reg, val);
reg 101 dev/ic/wdcevent.h enum wdc_regs reg, u_int16_t val) {
reg 104 dev/ic/wdcevent.h record[0] = reg;
reg 121 dev/ic/wdcvar.h u_int8_t (*read_reg)(struct channel_softc *, enum wdc_regs reg);
reg 122 dev/ic/wdcvar.h void (*write_reg)(struct channel_softc *, enum wdc_regs reg,
reg 124 dev/ic/wdcvar.h void (*lba48_write_reg)(struct channel_softc *, enum wdc_regs reg,
reg 440 dev/ic/xl.c xl_miibus_readreg(struct device *self, int phy, int reg)
reg 451 dev/ic/xl.c frame.mii_regaddr = reg;
reg 458 dev/ic/xl.c xl_miibus_writereg(struct device *self, int phy, int reg, int data)
reg 469 dev/ic/xl.c frame.mii_regaddr = reg;
reg 634 dev/ic/xlreg.h #define CSR_WRITE_4(sc, reg, val) \
reg 635 dev/ic/xlreg.h bus_space_write_4(sc->xl_btag, sc->xl_bhandle, reg, val)
reg 636 dev/ic/xlreg.h #define CSR_WRITE_2(sc, reg, val) \
reg 637 dev/ic/xlreg.h bus_space_write_2(sc->xl_btag, sc->xl_bhandle, reg, val)
reg 638 dev/ic/xlreg.h #define CSR_WRITE_1(sc, reg, val) \
reg 639 dev/ic/xlreg.h bus_space_write_1(sc->xl_btag, sc->xl_bhandle, reg, val)
reg 641 dev/ic/xlreg.h #define CSR_READ_4(sc, reg) \
reg 642 dev/ic/xlreg.h bus_space_read_4(sc->xl_btag, sc->xl_bhandle, reg)
reg 643 dev/ic/xlreg.h #define CSR_READ_2(sc, reg) \
reg 644 dev/ic/xlreg.h bus_space_read_2(sc->xl_btag, sc->xl_bhandle, reg)
reg 645 dev/ic/xlreg.h #define CSR_READ_1(sc, reg) \
reg 646 dev/ic/xlreg.h bus_space_read_1(sc->xl_btag, sc->xl_bhandle, reg)
reg 144 dev/ic/z8530sc.c u_char *reg;
reg 148 dev/ic/z8530sc.c reg = cs->cs_creg; /* current regs */
reg 161 dev/ic/z8530sc.c zs_write_reg(cs, 4, reg[4]);
reg 164 dev/ic/z8530sc.c zs_write_reg(cs, 10, reg[10]);
reg 167 dev/ic/z8530sc.c zs_write_reg(cs, 3, reg[3] & ~ZSWR3_RX_ENABLE);
reg 168 dev/ic/z8530sc.c zs_write_reg(cs, 5, reg[5] & ~ZSWR5_TX_ENABLE);
reg 171 dev/ic/z8530sc.c zs_write_reg(cs, 1, reg[1]);
reg 182 dev/ic/z8530sc.c zs_write_reg(cs, 2, reg[2]);
reg 184 dev/ic/z8530sc.c zs_write_reg(cs, 9, reg[9]);
reg 188 dev/ic/z8530sc.c zs_write_reg(cs, 11, reg[11]);
reg 191 dev/ic/z8530sc.c zs_write_reg(cs, 12, reg[12]);
reg 192 dev/ic/z8530sc.c zs_write_reg(cs, 13, reg[13]);
reg 195 dev/ic/z8530sc.c zs_write_reg(cs, 14, reg[14]);
reg 198 dev/ic/z8530sc.c zs_write_reg(cs, 15, reg[15]);
reg 201 dev/ic/z8530sc.c zs_write_reg(cs, 3, reg[3]);
reg 202 dev/ic/z8530sc.c zs_write_reg(cs, 5, reg[5]);
reg 365 dev/ipmi.c bt_read(struct ipmi_softc *sc, int reg)
reg 367 dev/ipmi.c return bmc_read(sc, reg);
reg 371 dev/ipmi.c bt_write(struct ipmi_softc *sc, int reg, uint8_t data)
reg 376 dev/ipmi.c bmc_write(sc, reg, data);
reg 161 dev/isa/ad1848.c ad_read(sc, reg)
reg 163 dev/isa/ad1848.c int reg;
reg 168 dev/isa/ad1848.c ADWRITE(sc, AD1848_IADDR, (reg & 0xff) | sc->MCE_bit);
reg 177 dev/isa/ad1848.c ad_write(sc, reg, data)
reg 179 dev/isa/ad1848.c int reg;
reg 183 dev/isa/ad1848.c ADWRITE(sc, AD1848_IADDR, (reg & 0xff) | sc->MCE_bit);
reg 612 dev/isa/ad1848.c u_char reg;
reg 614 dev/isa/ad1848.c reg = ad_read(sc, mixer_channel_info[device].left_reg);
reg 618 dev/isa/ad1848.c ad_write(sc, mixer_channel_info[device].left_reg, reg & 0xFE);
reg 620 dev/isa/ad1848.c ad_write(sc, mixer_channel_info[device].left_reg, reg | 0x80);
reg 623 dev/isa/ad1848.c ad_write(sc, mixer_channel_info[device].left_reg, reg | 0x01);
reg 625 dev/isa/ad1848.c ad_write(sc, mixer_channel_info[device].left_reg, reg & ~0x80);
reg 632 dev/isa/ad1848.c reg = ad_read(sc, mixer_channel_info[device].right_reg);
reg 635 dev/isa/ad1848.c ad_write(sc, mixer_channel_info[device].right_reg, reg | 0x80);
reg 637 dev/isa/ad1848.c ad_write(sc, mixer_channel_info[device].right_reg, reg & ~0x80);
reg 649 dev/isa/ad1848.c u_char reg;
reg 656 dev/isa/ad1848.c reg = ad_read(sc, info->left_reg) & (info->atten_mask);
reg 658 dev/isa/ad1848.c reg |= ((atten & info->atten_bits) << 2);
reg 660 dev/isa/ad1848.c reg |= ((atten & info->atten_bits));
reg 662 dev/isa/ad1848.c ad_write(sc, info->left_reg, reg);
reg 668 dev/isa/ad1848.c reg = ad_read(sc, info->right_reg);
reg 669 dev/isa/ad1848.c reg &= (info->atten_mask);
reg 670 dev/isa/ad1848.c ad_write(sc, info->right_reg, (atten& info->atten_bits)|reg);
reg 700 dev/isa/ad1848.c u_char reg, gain;
reg 707 dev/isa/ad1848.c reg = ad_read(sc, SP_LEFT_INPUT_CONTROL);
reg 708 dev/isa/ad1848.c reg &= INPUT_GAIN_MASK;
reg 709 dev/isa/ad1848.c ad_write(sc, SP_LEFT_INPUT_CONTROL, (gain&0x0f)|reg);
reg 712 dev/isa/ad1848.c reg = ad_read(sc, SP_RIGHT_INPUT_CONTROL);
reg 713 dev/isa/ad1848.c reg &= INPUT_GAIN_MASK;
reg 714 dev/isa/ad1848.c ad_write(sc, SP_RIGHT_INPUT_CONTROL, (gain&0x0f)|reg);
reg 743 dev/isa/ad1848.c u_char reg;
reg 749 dev/isa/ad1848.c reg = ad_read(sc, SP_LEFT_INPUT_CONTROL);
reg 750 dev/isa/ad1848.c ad_write(sc, SP_LEFT_INPUT_CONTROL, reg | INPUT_MIC_GAIN_ENABLE);
reg 753 dev/isa/ad1848.c reg = ad_read(sc, SP_LEFT_INPUT_CONTROL);
reg 754 dev/isa/ad1848.c ad_write(sc, SP_LEFT_INPUT_CONTROL, reg & ~INPUT_MIC_GAIN_ENABLE);
reg 1110 dev/isa/ad1848.c u_char inp, reg;
reg 1129 dev/isa/ad1848.c reg = ad_read(sc, SP_LEFT_INPUT_CONTROL);
reg 1130 dev/isa/ad1848.c reg &= INPUT_SOURCE_MASK;
reg 1131 dev/isa/ad1848.c ad_write(sc, SP_LEFT_INPUT_CONTROL, (inp|reg));
reg 1133 dev/isa/ad1848.c reg = ad_read(sc, SP_RIGHT_INPUT_CONTROL);
reg 1134 dev/isa/ad1848.c reg &= INPUT_SOURCE_MASK;
reg 1135 dev/isa/ad1848.c ad_write(sc, SP_RIGHT_INPUT_CONTROL, (inp|reg));
reg 1414 dev/isa/ad1848.c u_char reg;
reg 1418 dev/isa/ad1848.c reg = ad_read(sc, SP_INTERFACE_CONFIG);
reg 1419 dev/isa/ad1848.c ad_write(sc, SP_INTERFACE_CONFIG, (reg & ~PLAYBACK_ENABLE));
reg 1430 dev/isa/ad1848.c u_char reg;
reg 1434 dev/isa/ad1848.c reg = ad_read(sc, SP_INTERFACE_CONFIG);
reg 1435 dev/isa/ad1848.c ad_write(sc, SP_INTERFACE_CONFIG, (reg & ~CAPTURE_ENABLE));
reg 1471 dev/isa/ad1848.c u_char reg;
reg 1512 dev/isa/ad1848.c reg = ad_read(sc, SP_INTERFACE_CONFIG);
reg 1513 dev/isa/ad1848.c ad_write(sc, SP_INTERFACE_CONFIG, (CAPTURE_ENABLE|reg));
reg 1556 dev/isa/ad1848.c u_char reg;
reg 1592 dev/isa/ad1848.c reg = ad_read(sc, SP_INTERFACE_CONFIG);
reg 1593 dev/isa/ad1848.c ad_write(sc, SP_INTERFACE_CONFIG, (PLAYBACK_ENABLE|reg));
reg 294 dev/isa/aps.c aps_mem_read_1(bus_space_tag_t iot, bus_space_handle_t ioh, int reg,
reg 301 dev/isa/aps.c cr = bus_space_read_1(iot, ioh, reg);
reg 306 dev/isa/aps.c DPRINTF(("aps: reg 0x%x not val 0x%x!\n", reg, val));
reg 207 dev/isa/aztech.c u_int32_t reg;
reg 218 dev/isa/aztech.c reg = lm700x_encode_freq(nfreq, sc->rf);
reg 219 dev/isa/aztech.c reg |= sc->stereo | sc->rf | LM700X_DIVIDER_FM;
reg 221 dev/isa/aztech.c lm700x_hardware_write(&sc->lm, reg, vol);
reg 1292 dev/isa/ess.c u_int8_t reg;
reg 1311 dev/isa/ess.c reg = ess_read_x_reg(sc, ESS_XCMD_AUDIO_CTRL);
reg 1313 dev/isa/ess.c reg &= ~ESS_AUDIO_CTRL_MONO;
reg 1314 dev/isa/ess.c reg |= ESS_AUDIO_CTRL_STEREO;
reg 1316 dev/isa/ess.c reg |= ESS_AUDIO_CTRL_MONO;
reg 1317 dev/isa/ess.c reg &= ~ESS_AUDIO_CTRL_STEREO;
reg 1319 dev/isa/ess.c ess_write_x_reg(sc, ESS_XCMD_AUDIO_CTRL, reg);
reg 1321 dev/isa/ess.c reg = ess_read_x_reg(sc, ESS_XCMD_AUDIO1_CTRL1);
reg 1323 dev/isa/ess.c reg |= ESS_AUDIO1_CTRL1_FIFO_SIZE;
reg 1325 dev/isa/ess.c reg &= ~ESS_AUDIO1_CTRL1_FIFO_SIZE;
reg 1327 dev/isa/ess.c reg |= ESS_AUDIO1_CTRL1_FIFO_STEREO;
reg 1329 dev/isa/ess.c reg &= ~ESS_AUDIO1_CTRL1_FIFO_STEREO;
reg 1332 dev/isa/ess.c reg |= ESS_AUDIO1_CTRL1_FIFO_SIGNED;
reg 1334 dev/isa/ess.c reg &= ~ESS_AUDIO1_CTRL1_FIFO_SIGNED;
reg 1335 dev/isa/ess.c reg |= ESS_AUDIO1_CTRL1_FIFO_CONNECT;
reg 1336 dev/isa/ess.c ess_write_x_reg(sc, ESS_XCMD_AUDIO1_CTRL1, reg);
reg 1352 dev/isa/ess.c reg = ess_read_x_reg(sc, ESS_XCMD_AUDIO1_CTRL2);
reg 1353 dev/isa/ess.c reg &= ~(ESS_AUDIO1_CTRL2_DMA_READ | ESS_AUDIO1_CTRL2_ADC_ENABLE);
reg 1354 dev/isa/ess.c reg |= ESS_AUDIO1_CTRL2_FIFO_ENABLE | ESS_AUDIO1_CTRL2_AUTO_INIT;
reg 1355 dev/isa/ess.c ess_write_x_reg(sc, ESS_XCMD_AUDIO1_CTRL2, reg);
reg 1370 dev/isa/ess.c u_int8_t reg;
reg 1389 dev/isa/ess.c reg = ess_read_mix_reg(sc, ESS_MREG_AUDIO2_CTRL2);
reg 1391 dev/isa/ess.c reg |= ESS_AUDIO2_CTRL2_FIFO_SIZE;
reg 1393 dev/isa/ess.c reg &= ~ESS_AUDIO2_CTRL2_FIFO_SIZE;
reg 1395 dev/isa/ess.c reg |= ESS_AUDIO2_CTRL2_CHANNELS;
reg 1397 dev/isa/ess.c reg &= ~ESS_AUDIO2_CTRL2_CHANNELS;
reg 1400 dev/isa/ess.c reg |= ESS_AUDIO2_CTRL2_FIFO_SIGNED;
reg 1402 dev/isa/ess.c reg &= ~ESS_AUDIO2_CTRL2_FIFO_SIGNED;
reg 1403 dev/isa/ess.c ess_write_mix_reg(sc, ESS_MREG_AUDIO2_CTRL2, reg);
reg 1416 dev/isa/ess.c reg = ess_read_mix_reg(sc, ESS_MREG_AUDIO2_CTRL1);
reg 1418 dev/isa/ess.c reg |= ESS_AUDIO2_CTRL1_XFER_SIZE;
reg 1420 dev/isa/ess.c reg &= ~ESS_AUDIO2_CTRL1_XFER_SIZE;
reg 1421 dev/isa/ess.c reg |= ESS_AUDIO2_CTRL1_DEMAND_8;
reg 1422 dev/isa/ess.c reg |= ESS_AUDIO2_CTRL1_DAC_ENABLE | ESS_AUDIO2_CTRL1_FIFO_ENABLE |
reg 1424 dev/isa/ess.c ess_write_mix_reg(sc, ESS_MREG_AUDIO2_CTRL1, reg);
reg 1439 dev/isa/ess.c u_int8_t reg;
reg 1458 dev/isa/ess.c reg = ess_read_x_reg(sc, ESS_XCMD_AUDIO_CTRL);
reg 1460 dev/isa/ess.c reg &= ~ESS_AUDIO_CTRL_MONO;
reg 1461 dev/isa/ess.c reg |= ESS_AUDIO_CTRL_STEREO;
reg 1463 dev/isa/ess.c reg |= ESS_AUDIO_CTRL_MONO;
reg 1464 dev/isa/ess.c reg &= ~ESS_AUDIO_CTRL_STEREO;
reg 1466 dev/isa/ess.c ess_write_x_reg(sc, ESS_XCMD_AUDIO_CTRL, reg);
reg 1468 dev/isa/ess.c reg = ess_read_x_reg(sc, ESS_XCMD_AUDIO1_CTRL1);
reg 1470 dev/isa/ess.c reg |= ESS_AUDIO1_CTRL1_FIFO_SIZE;
reg 1472 dev/isa/ess.c reg &= ~ESS_AUDIO1_CTRL1_FIFO_SIZE;
reg 1474 dev/isa/ess.c reg |= ESS_AUDIO1_CTRL1_FIFO_STEREO;
reg 1476 dev/isa/ess.c reg &= ~ESS_AUDIO1_CTRL1_FIFO_STEREO;
reg 1479 dev/isa/ess.c reg |= ESS_AUDIO1_CTRL1_FIFO_SIGNED;
reg 1481 dev/isa/ess.c reg &= ~ESS_AUDIO1_CTRL1_FIFO_SIGNED;
reg 1482 dev/isa/ess.c reg |= ESS_AUDIO1_CTRL1_FIFO_CONNECT;
reg 1483 dev/isa/ess.c ess_write_x_reg(sc, ESS_XCMD_AUDIO1_CTRL1, reg);
reg 1499 dev/isa/ess.c reg = ess_read_x_reg(sc, ESS_XCMD_AUDIO1_CTRL2);
reg 1500 dev/isa/ess.c reg |= ESS_AUDIO1_CTRL2_DMA_READ | ESS_AUDIO1_CTRL2_ADC_ENABLE;
reg 1501 dev/isa/ess.c reg |= ESS_AUDIO1_CTRL2_FIFO_ENABLE | ESS_AUDIO1_CTRL2_AUTO_INIT;
reg 1502 dev/isa/ess.c ess_write_x_reg(sc, ESS_XCMD_AUDIO1_CTRL2, reg);
reg 1553 dev/isa/ess.c u_int8_t reg;
reg 1558 dev/isa/ess.c reg = EREAD1(sc->sc_iot, sc->sc_ioh, ESS_DSP_RW_STATUS);
reg 1559 dev/isa/ess.c if ((reg & ESS_DSP_READ_OFLOW) == 0)
reg 1561 dev/isa/ess.c reg = EREAD1(sc->sc_iot, sc->sc_ioh, ESS_CLEAR_INTR);
reg 1577 dev/isa/ess.c u_int8_t reg;
reg 1582 dev/isa/ess.c reg = ess_read_mix_reg(sc, ESS_MREG_AUDIO2_CTRL2);
reg 1583 dev/isa/ess.c if ((reg & ESS_AUDIO2_CTRL2_IRQ_LATCH) == 0)
reg 1585 dev/isa/ess.c reg &= ~ESS_AUDIO2_CTRL2_IRQ_LATCH;
reg 1586 dev/isa/ess.c ess_write_mix_reg(sc, ESS_MREG_AUDIO2_CTRL2, reg);
reg 2601 dev/isa/ess.c ess_write_x_reg(sc, reg, val)
reg 2603 dev/isa/ess.c u_char reg;
reg 2608 dev/isa/ess.c DPRINTFN(2,("ess_write_x_reg: %02x=%02x\n", reg, val));
reg 2609 dev/isa/ess.c if ((error = ess_wdsp(sc, reg)) == 0)
reg 2619 dev/isa/ess.c ess_read_x_reg(sc, reg)
reg 2621 dev/isa/ess.c u_char reg;
reg 2627 dev/isa/ess.c error = ess_wdsp(sc, reg);
reg 2629 dev/isa/ess.c DPRINTF(("Error reading extended register 0x%02x\n", reg));
reg 2632 dev/isa/ess.c DPRINTFN(2,("ess_read_x_reg: %02x=%02x\n", reg, val));
reg 2637 dev/isa/ess.c ess_clear_xreg_bits(sc, reg, mask)
reg 2639 dev/isa/ess.c u_char reg;
reg 2642 dev/isa/ess.c if (ess_write_x_reg(sc, reg, ess_read_x_reg(sc, reg) & ~mask) == -1)
reg 2644 dev/isa/ess.c reg));
reg 2648 dev/isa/ess.c ess_set_xreg_bits(sc, reg, mask)
reg 2650 dev/isa/ess.c u_char reg;
reg 2653 dev/isa/ess.c if (ess_write_x_reg(sc, reg, ess_read_x_reg(sc, reg) | mask) == -1)
reg 2655 dev/isa/ess.c reg));
reg 2663 dev/isa/ess.c ess_write_mix_reg(sc, reg, val)
reg 2665 dev/isa/ess.c u_char reg;
reg 2672 dev/isa/ess.c DPRINTFN(2,("ess_write_mix_reg: %x=%x\n", reg, val));
reg 2675 dev/isa/ess.c EWRITE1(iot, ioh, ESS_MIX_REG_SELECT, reg);
reg 2684 dev/isa/ess.c ess_read_mix_reg(sc, reg)
reg 2686 dev/isa/ess.c u_char reg;
reg 2694 dev/isa/ess.c EWRITE1(iot, ioh, ESS_MIX_REG_SELECT, reg);
reg 2698 dev/isa/ess.c DPRINTFN(2,("ess_read_mix_reg: %x=%x\n", reg, val));
reg 2703 dev/isa/ess.c ess_clear_mreg_bits(sc, reg, mask)
reg 2705 dev/isa/ess.c u_char reg;
reg 2708 dev/isa/ess.c ess_write_mix_reg(sc, reg, ess_read_mix_reg(sc, reg) & ~mask);
reg 2712 dev/isa/ess.c ess_set_mreg_bits(sc, reg, mask)
reg 2714 dev/isa/ess.c u_char reg;
reg 2717 dev/isa/ess.c ess_write_mix_reg(sc, reg, ess_read_mix_reg(sc, reg) | mask);
reg 2721 dev/isa/ess.c ess_read_multi_mix_reg(sc, reg, datap, count)
reg 2723 dev/isa/ess.c u_char reg;
reg 2732 dev/isa/ess.c EWRITE1(iot, ioh, ESS_MIX_REG_SELECT, reg);
reg 95 dev/isa/gscsio.c #define ACB_READ(reg) \
reg 96 dev/isa/gscsio.c bus_space_read_1(sc->sc_iot, acb->ioh, (reg))
reg 97 dev/isa/gscsio.c #define ACB_WRITE(reg, val) \
reg 98 dev/isa/gscsio.c bus_space_write_1(sc->sc_iot, acb->ioh, (reg), (val))
reg 196 dev/isa/i82365_isasubr.c int irq, ist, reg;
reg 210 dev/isa/i82365_isasubr.c reg = pcic_read(h, PCIC_INTR);
reg 211 dev/isa/i82365_isasubr.c reg &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_ENABLE);
reg 212 dev/isa/i82365_isasubr.c pcic_write(h, PCIC_INTR, reg | irq);
reg 226 dev/isa/i82365_isasubr.c int reg;
reg 232 dev/isa/i82365_isasubr.c reg = pcic_read(h, PCIC_INTR);
reg 233 dev/isa/i82365_isasubr.c reg &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_ENABLE);
reg 234 dev/isa/i82365_isasubr.c pcic_write(h, PCIC_INTR, reg);
reg 850 dev/isa/if_ef_isapnp.c ef_miibus_readreg(dev, phy, reg)
reg 852 dev/isa/if_ef_isapnp.c int phy, reg;
reg 882 dev/isa/if_ef_isapnp.c ef_mii_writeb(sc, (reg & i) ? 1 : 0);
reg 923 dev/isa/if_ef_isapnp.c ef_miibus_writereg(dev, phy, reg, val)
reg 925 dev/isa/if_ef_isapnp.c int phy, reg, val;
reg 949 dev/isa/if_ef_isapnp.c ef_mii_writeb(sc, (reg & i) ? 1 : 0);
reg 178 dev/isa/it.c it_readreg(struct it_softc *sc, int reg)
reg 180 dev/isa/it.c bus_space_write_1(sc->it_iot, sc->it_ioh, ITC_ADDR, reg);
reg 185 dev/isa/it.c it_writereg(struct it_softc *sc, int reg, int val)
reg 187 dev/isa/it.c bus_space_write_1(sc->it_iot, sc->it_ioh, ITC_ADDR, reg);
reg 181 dev/isa/lm78_isa.c lm_isa_readreg(struct lm_softc *lmsc, int reg)
reg 185 dev/isa/lm78_isa.c bus_space_write_1(sc->sc_iot, sc->sc_ioh, LMC_ADDR, reg);
reg 190 dev/isa/lm78_isa.c lm_isa_writereg(struct lm_softc *lmsc, int reg, int val)
reg 194 dev/isa/lm78_isa.c bus_space_write_1(sc->sc_iot, sc->sc_ioh, LMC_ADDR, reg);
reg 183 dev/isa/nsclpcsio_isa.c #define GPIO_READ(sc, reg) \
reg 185 dev/isa/nsclpcsio_isa.c (sc)->sc_ld_ioh[SIO_LDN_GPIO], (reg))
reg 186 dev/isa/nsclpcsio_isa.c #define GPIO_WRITE(sc, reg, val) \
reg 188 dev/isa/nsclpcsio_isa.c (sc)->sc_ld_ioh[SIO_LDN_GPIO], (reg), (val))
reg 189 dev/isa/nsclpcsio_isa.c #define TMS_WRITE(sc, reg, val) \
reg 191 dev/isa/nsclpcsio_isa.c (sc)->sc_ld_ioh[SIO_LDN_TMS], (reg), (val))
reg 192 dev/isa/nsclpcsio_isa.c #define TMS_READ(sc, reg) \
reg 194 dev/isa/nsclpcsio_isa.c (sc)->sc_ld_ioh[SIO_LDN_TMS], (reg))
reg 195 dev/isa/nsclpcsio_isa.c #define VLM_WRITE(sc, reg, val) \
reg 197 dev/isa/nsclpcsio_isa.c (sc)->sc_ld_ioh[SIO_LDN_VLM], (reg), (val))
reg 198 dev/isa/nsclpcsio_isa.c #define VLM_READ(sc, reg) \
reg 200 dev/isa/nsclpcsio_isa.c (sc)->sc_ld_ioh[SIO_LDN_VLM], (reg))
reg 542 dev/isa/nsclpcsio_isa.c int port, shift, reg;
reg 550 dev/isa/nsclpcsio_isa.c reg = SIO_GPDI0;
reg 553 dev/isa/nsclpcsio_isa.c reg = SIO_GPDI1;
reg 556 dev/isa/nsclpcsio_isa.c reg = SIO_GPDI2;
reg 559 dev/isa/nsclpcsio_isa.c reg = SIO_GPDI3;
reg 563 dev/isa/nsclpcsio_isa.c data = GPIO_READ(sc, reg);
reg 572 dev/isa/nsclpcsio_isa.c int port, shift, reg;
reg 580 dev/isa/nsclpcsio_isa.c reg = SIO_GPDO0;
reg 583 dev/isa/nsclpcsio_isa.c reg = SIO_GPDO1;
reg 586 dev/isa/nsclpcsio_isa.c reg = SIO_GPDO2;
reg 589 dev/isa/nsclpcsio_isa.c reg = SIO_GPDO3;
reg 593 dev/isa/nsclpcsio_isa.c data = GPIO_READ(sc, reg);
reg 599 dev/isa/nsclpcsio_isa.c GPIO_WRITE(sc, reg, data);
reg 217 dev/isa/radiotrack.c u_int32_t reg;
reg 226 dev/isa/radiotrack.c reg = lm700x_encode_freq(nfreq, sc->sc_rf);
reg 227 dev/isa/radiotrack.c reg |= sc->sc_stereo | sc->sc_rf | LM700X_DIVIDER_FM;
reg 229 dev/isa/radiotrack.c lm700x_hardware_write(&sc->lm, reg, RT_VOLUME_STEADY);
reg 211 dev/isa/sf16fmr2.c u_int32_t reg, vol, i;
reg 225 dev/isa/sf16fmr2.c reg = pt2254a_compose_register(vol, vol,
reg 233 dev/isa/sf16fmr2.c reg & (1 << i));
reg 320 dev/isa/tcic2_isa.c int irq, ist, val, reg;
reg 350 dev/isa/tcic2_isa.c reg = TCIC_IR_SCF1_N(h->sock);
reg 351 dev/isa/tcic2_isa.c val = (tcic_read_ind_2(h, reg) & (~TCIC_SCF1_IRQ_MASK)) | irqmap[irq];
reg 352 dev/isa/tcic2_isa.c tcic_write_ind_2(h, reg, val);
reg 364 dev/isa/tcic2_isa.c int val, reg;
reg 370 dev/isa/tcic2_isa.c reg = TCIC_IR_SCF1_N(h->sock);
reg 371 dev/isa/tcic2_isa.c val = tcic_read_ind_2(h, reg);
reg 373 dev/isa/tcic2_isa.c tcic_write_ind_2(h, reg, val);
reg 145 dev/isa/viasio.c u_int8_t reg;
reg 152 dev/isa/viasio.c reg = viasio_conf_read(iot, ioh, VT1211_ID);
reg 153 dev/isa/viasio.c DPRINTF(("viasio_probe: id 0x%02x\n", reg));
reg 156 dev/isa/viasio.c if (reg == VT1211_ID_VT1211) {
reg 173 dev/isa/viasio.c u_int8_t reg;
reg 187 dev/isa/viasio.c reg = viasio_conf_read(sc->sc_iot, sc->sc_ioh, VT1211_REV);
reg 188 dev/isa/viasio.c printf(": VT1211 rev 0x%02x", reg);
reg 186 dev/isa/ym.c ym_read(sc, reg)
reg 188 dev/isa/ym.c int reg;
reg 191 dev/isa/ym.c (reg & 0xff));
reg 196 dev/isa/ym.c ym_write(sc, reg, data)
reg 198 dev/isa/ym.c int reg;
reg 202 dev/isa/ym.c (reg & 0xff));
reg 245 dev/isa/ym.c u_int8_t reg;
reg 247 dev/isa/ym.c reg = ym_read(sc, left_reg);
reg 249 dev/isa/ym.c ym_write(sc, left_reg, reg | 0x80);
reg 251 dev/isa/ym.c ym_write(sc, left_reg, reg & ~0x80);
reg 291 dev/isa/ym.c ym_set_3d(sc, cp, val, reg)
reg 295 dev/isa/ym.c int reg;
reg 306 dev/isa/ym.c ym_write(sc, reg, e);
reg 1055 dev/microcode/ncr53cxxx/ncr53cxxx.c int reg;
reg 1072 dev/microcode/ncr53cxxx/ncr53cxxx.c reg = CheckRegister (tokenix);
reg 1073 dev/microcode/ncr53cxxx/ncr53cxxx.c if (reg < 0) { /* Not register, must be data */
reg 1077 dev/microcode/ncr53cxxx/ncr53cxxx.c reg = CheckRegister (tokenix+2);
reg 1078 dev/microcode/ncr53cxxx/ncr53cxxx.c if (reg < 0)
reg 1080 dev/microcode/ncr53cxxx/ncr53cxxx.c inst0 = 0x78000000 | (data << 8) | reg;
reg 1082 dev/microcode/ncr53cxxx/ncr53cxxx.c fprintf (listfp, "Move data to register: %02x %d\n", data, reg);
reg 1095 dev/microcode/ncr53cxxx/ncr53cxxx.c if (reg != data && reg != 8 && data != 8)
reg 1097 dev/microcode/ncr53cxxx/ncr53cxxx.c if (reg == data) { /* A register read/modify/write */
reg 1099 dev/microcode/ncr53cxxx/ncr53cxxx.c fprintf (listfp, "Read/modify register: %02x %d %d\n", inst0 >> 8, op, reg);
reg 1101 dev/microcode/ncr53cxxx/ncr53cxxx.c inst0 |= 0x78000000 | (op << 25) | (reg << 16);
reg 1104 dev/microcode/ncr53cxxx/ncr53cxxx.c if (reg == 8) { /* MOVE SFBR <> TO reg */
reg 1112 dev/microcode/ncr53cxxx/ncr53cxxx.c fprintf (listfp, "Move register to SFBR: %02x %d %d\n", inst0 >> 8, op, reg);
reg 1114 dev/microcode/ncr53cxxx/ncr53cxxx.c inst0 |= 0x70000000 | (op << 25) | (reg << 16);
reg 1120 dev/microcode/ncr53cxxx/ncr53cxxx.c if (reg == 8) /* move SFBR to reg */
reg 1123 dev/microcode/ncr53cxxx/ncr53cxxx.c inst0 = 0x72000000 | (reg << 16);
reg 1118 dev/microcode/siop/ncr53cxxx.c int reg, size;
reg 1120 dev/microcode/siop/ncr53cxxx.c reg = CheckRegister(i);
reg 1121 dev/microcode/siop/ncr53cxxx.c if (reg < 0)
reg 1124 dev/microcode/siop/ncr53cxxx.c inst0 |= reg << 16;
reg 1125 dev/microcode/siop/ncr53cxxx.c if (reg == 8)
reg 1135 dev/microcode/siop/ncr53cxxx.c if ((reg & 0x3) + size > 4)
reg 1345 dev/microcode/siop/ncr53cxxx.c int reg;
reg 1375 dev/microcode/siop/ncr53cxxx.c reg = CheckRegister (tokenix);
reg 1376 dev/microcode/siop/ncr53cxxx.c if (reg < 0) { /* Not register, must be data */
reg 1380 dev/microcode/siop/ncr53cxxx.c reg = CheckRegister (tokenix+2);
reg 1381 dev/microcode/siop/ncr53cxxx.c if (reg < 0)
reg 1383 dev/microcode/siop/ncr53cxxx.c inst0 = 0x78000000 | (data << 8) | reg << 16;
reg 1385 dev/microcode/siop/ncr53cxxx.c fprintf (listfp, "Move data to register: %02x %d\n", data, reg);
reg 1428 dev/microcode/siop/ncr53cxxx.c if (reg != data && reg != 8 && data != 8)
reg 1430 dev/microcode/siop/ncr53cxxx.c if (reg == data) { /* A register read/modify/write */
reg 1432 dev/microcode/siop/ncr53cxxx.c fprintf (listfp, "Read/modify register: %02x %d %d\n", inst0 >> 8, op, reg);
reg 1434 dev/microcode/siop/ncr53cxxx.c inst0 |= 0x78000000 | (op << 24) | (reg << 16);
reg 1437 dev/microcode/siop/ncr53cxxx.c if (reg == 8) { /* MOVE SFBR <> TO reg */
reg 1445 dev/microcode/siop/ncr53cxxx.c fprintf (listfp, "Move register to SFBR: %02x %d %d\n", inst0 >> 8, op, reg);
reg 1447 dev/microcode/siop/ncr53cxxx.c inst0 |= 0x70000000 | (op << 24) | (reg << 16);
reg 1454 dev/microcode/siop/ncr53cxxx.c if (reg == 8) /* move SFBR to reg */
reg 1457 dev/microcode/siop/ncr53cxxx.c inst0 = 0x72000000 | (reg << 16);
reg 145 dev/mii/acphy.c int reg;
reg 162 dev/mii/acphy.c reg = PHY_READ(sc, MII_BMCR);
reg 163 dev/mii/acphy.c PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
reg 135 dev/mii/amphy.c int reg;
reg 152 dev/mii/amphy.c reg = PHY_READ(sc, MII_BMCR);
reg 153 dev/mii/amphy.c PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
reg 139 dev/mii/bmtphy.c int reg;
reg 159 dev/mii/bmtphy.c reg = PHY_READ(sc, MII_BMCR);
reg 160 dev/mii/bmtphy.c PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
reg 190 dev/mii/brgphy.c int reg, speed, gig;
reg 210 dev/mii/brgphy.c reg = PHY_READ(sc, MII_BMCR);
reg 211 dev/mii/brgphy.c PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
reg 291 dev/mii/brgphy.c reg = PHY_READ(sc, BRGPHY_MII_AUXSTS);
reg 292 dev/mii/brgphy.c if (reg & BRGPHY_AUXSTS_LINK)
reg 531 dev/mii/brgphy.c int reg;
reg 549 dev/mii/brgphy.c for (i = 0; dspcode[i].reg != 0; i++)
reg 550 dev/mii/brgphy.c PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
reg 559 dev/mii/brgphy.c int reg;
reg 569 dev/mii/brgphy.c for (i = 0; dspcode[i].reg != 0; i++)
reg 570 dev/mii/brgphy.c PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
reg 596 dev/mii/brgphy.c int reg;
reg 605 dev/mii/brgphy.c for (i = 0; dspcode[i].reg != 0; i++)
reg 606 dev/mii/brgphy.c PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
reg 613 dev/mii/brgphy.c int reg;
reg 626 dev/mii/brgphy.c for (i = 0; dspcode[i].reg != 0; i++)
reg 627 dev/mii/brgphy.c PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
reg 634 dev/mii/brgphy.c int reg;
reg 643 dev/mii/brgphy.c for (i = 0; dspcode[i].reg != 0; i++)
reg 644 dev/mii/brgphy.c PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
reg 651 dev/mii/brgphy.c int reg;
reg 666 dev/mii/brgphy.c for (i = 0; dspcode[i].reg != 0; i++)
reg 667 dev/mii/brgphy.c PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
reg 148 dev/mii/ciphy.c int reg, speed, gig;
reg 165 dev/mii/ciphy.c reg = PHY_READ(sc, MII_BMCR);
reg 166 dev/mii/ciphy.c PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
reg 71 dev/mii/dcphy.c #define DC_SETBIT(sc, reg, x) \
reg 72 dev/mii/dcphy.c CSR_WRITE_4(sc, reg, \
reg 73 dev/mii/dcphy.c CSR_READ_4(sc, reg) | x)
reg 75 dev/mii/dcphy.c #define DC_CLRBIT(sc, reg, x) \
reg 76 dev/mii/dcphy.c CSR_WRITE_4(sc, reg, \
reg 77 dev/mii/dcphy.c CSR_READ_4(sc, reg) & ~x)
reg 183 dev/mii/dcphy.c int reg;
reg 278 dev/mii/dcphy.c reg = CSR_READ_4(dc_sc, DC_10BTSTAT);
reg 279 dev/mii/dcphy.c if (!(reg & DC_TSTAT_LS10) || !(reg & DC_TSTAT_LS100))
reg 314 dev/mii/dcphy.c int reg, anlpar, tstat = 0;
reg 322 dev/mii/dcphy.c reg = CSR_READ_4(dc_sc, DC_10BTSTAT);
reg 323 dev/mii/dcphy.c if (!(reg & DC_TSTAT_LS10) || !(reg & DC_TSTAT_LS100))
reg 368 dev/mii/dcphy.c if (!(reg & DC_TSTAT_LS100))
reg 370 dev/mii/dcphy.c else if (!(reg & DC_TSTAT_LS10))
reg 136 dev/mii/eephy.c int reg, page;
reg 156 dev/mii/eephy.c reg = PHY_READ(sc, E1000_SCR);
reg 157 dev/mii/eephy.c reg &= ~E1000_SCR_MODE_MASK;
reg 158 dev/mii/eephy.c reg |= E1000_SCR_MODE_1000BX;
reg 159 dev/mii/eephy.c PHY_WRITE(sc, E1000_SCR, reg);
reg 175 dev/mii/eephy.c reg = PHY_READ(sc, E1000_SCR);
reg 178 dev/mii/eephy.c reg |= E1000_SCR_ASSERT_CRS_ON_TX;
reg 184 dev/mii/eephy.c reg |= (E1000_SCR_AUTO_X_MODE >> 1);
reg 189 dev/mii/eephy.c reg &= ~E1000_SCR_AUTO_X_MODE;
reg 191 dev/mii/eephy.c reg |= E1000_SCR_AUTO_X_MODE;
reg 200 dev/mii/eephy.c reg &= ~E1000_SCR_EN_DETECT_MASK;
reg 204 dev/mii/eephy.c PHY_WRITE(sc, E1000_SCR, reg);
reg 207 dev/mii/eephy.c reg = PHY_READ(sc, E1000_ESCR);
reg 208 dev/mii/eephy.c reg |= E1000_ESCR_TX_CLK_25;
reg 209 dev/mii/eephy.c PHY_WRITE(sc, E1000_ESCR, reg);
reg 216 dev/mii/eephy.c reg = PHY_READ(sc, E1000_CR);
reg 217 dev/mii/eephy.c reg &= ~E1000_CR_AUTO_NEG_ENABLE;
reg 218 dev/mii/eephy.c PHY_WRITE(sc, E1000_CR, reg | E1000_CR_RESET);
reg 224 dev/mii/eephy.c int reg, i;
reg 226 dev/mii/eephy.c reg = PHY_READ(sc, E1000_CR);
reg 227 dev/mii/eephy.c reg |= E1000_CR_RESET;
reg 228 dev/mii/eephy.c PHY_WRITE(sc, E1000_CR, reg);
reg 232 dev/mii/eephy.c reg = PHY_READ(sc, E1000_CR);
reg 233 dev/mii/eephy.c if (!(reg & E1000_CR_RESET))
reg 185 dev/mii/gentbi.c int reg;
reg 202 dev/mii/gentbi.c reg = PHY_READ(sc, MII_BMCR);
reg 203 dev/mii/gentbi.c PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
reg 167 dev/mii/icsphy.c int reg;
reg 187 dev/mii/icsphy.c reg = PHY_READ(sc, MII_BMCR);
reg 188 dev/mii/icsphy.c PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
reg 170 dev/mii/inphy.c int reg;
reg 190 dev/mii/inphy.c reg = PHY_READ(sc, MII_BMCR);
reg 191 dev/mii/inphy.c PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
reg 167 dev/mii/iophy.c int reg;
reg 187 dev/mii/iophy.c reg = PHY_READ(sc, MII_BMCR);
reg 188 dev/mii/iophy.c PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
reg 148 dev/mii/ipgphy.c uint32_t gig, reg, speed;
reg 165 dev/mii/ipgphy.c reg = PHY_READ(sc, IPGPHY_MII_BMCR);
reg 167 dev/mii/ipgphy.c reg | IPGPHY_BMCR_ISO);
reg 251 dev/mii/ipgphy.c reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
reg 252 dev/mii/ipgphy.c if (reg & BMSR_LINK) {
reg 336 dev/mii/ipgphy.c uint32_t reg;
reg 338 dev/mii/ipgphy.c reg = IPGPHY_ANAR_10T | IPGPHY_ANAR_10T_FDX |
reg 342 dev/mii/ipgphy.c reg |= IPGPHY_ANAR_PAUSE | IPGPHY_ANAR_APAUSE;
reg 344 dev/mii/ipgphy.c PHY_WRITE(mii, IPGPHY_MII_ANAR, reg);
reg 345 dev/mii/ipgphy.c reg = IPGPHY_1000CR_1000T | IPGPHY_1000CR_1000T_FDX;
reg 346 dev/mii/ipgphy.c reg |= IPGPHY_1000CR_MASTER;
reg 347 dev/mii/ipgphy.c PHY_WRITE(mii, IPGPHY_MII_1000CR, reg);
reg 373 dev/mii/ipgphy.c uint32_t reg;
reg 378 dev/mii/ipgphy.c reg = PHY_READ(sc, IPGPHY_MII_BMCR);
reg 379 dev/mii/ipgphy.c reg &= ~(IPGPHY_BMCR_AUTOEN | IPGPHY_BMCR_FDX);
reg 380 dev/mii/ipgphy.c PHY_WRITE(sc, MII_BMCR, reg);
reg 181 dev/mii/lxtphy.c int reg;
reg 201 dev/mii/lxtphy.c reg = PHY_READ(sc, MII_BMCR);
reg 202 dev/mii/lxtphy.c PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
reg 122 dev/mii/mii_bitbang.c int reg)
reg 131 dev/mii/mii_bitbang.c mii_bitbang_sendbits(sc, ops, reg, 5);
reg 170 dev/mii/mii_bitbang.c int phy, int reg, int val)
reg 178 dev/mii/mii_bitbang.c mii_bitbang_sendbits(sc, ops, reg, 5);
reg 242 dev/mii/mii_physubr.c int reg;
reg 258 dev/mii/mii_physubr.c reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
reg 259 dev/mii/mii_physubr.c if (reg & BMSR_LINK) {
reg 291 dev/mii/mii_physubr.c int reg, i;
reg 294 dev/mii/mii_physubr.c reg = BMCR_RESET;
reg 296 dev/mii/mii_physubr.c reg = BMCR_RESET | BMCR_ISO;
reg 297 dev/mii/mii_physubr.c PHY_WRITE(sc, MII_BMCR, reg);
reg 311 dev/mii/mii_physubr.c reg = PHY_READ(sc, MII_BMCR);
reg 312 dev/mii/mii_physubr.c if ((reg & BMCR_RESET) == 0)
reg 318 dev/mii/mii_physubr.c PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
reg 114 dev/mii/mtdphy.c int reg;
reg 133 dev/mii/mtdphy.c reg = PHY_READ(sc, MII_BMCR);
reg 134 dev/mii/mtdphy.c PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
reg 153 dev/mii/nsgphy.c int reg;
reg 173 dev/mii/nsgphy.c reg = PHY_READ(sc, MII_BMCR);
reg 174 dev/mii/nsgphy.c PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
reg 160 dev/mii/nsphy.c int reg;
reg 180 dev/mii/nsphy.c reg = PHY_READ(sc, MII_BMCR);
reg 181 dev/mii/nsphy.c PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
reg 191 dev/mii/nsphy.c reg = PHY_READ(sc, MII_NSPHY_PCR);
reg 197 dev/mii/nsphy.c reg |= PCR_LED4MODE;
reg 204 dev/mii/nsphy.c reg |= PCR_CIMDIS;
reg 210 dev/mii/nsphy.c reg |= PCR_FLINK100;
reg 217 dev/mii/nsphy.c reg |= PCR_CONGCTRL | PCR_TXREADYSEL;
reg 219 dev/mii/nsphy.c PHY_WRITE(sc, MII_NSPHY_PCR, reg);
reg 162 dev/mii/nsphyter.c int reg;
reg 182 dev/mii/nsphyter.c reg = PHY_READ(sc, MII_BMCR);
reg 183 dev/mii/nsphyter.c PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
reg 158 dev/mii/qsphy.c int reg;
reg 178 dev/mii/qsphy.c reg = PHY_READ(sc, MII_BMCR);
reg 179 dev/mii/qsphy.c PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
reg 150 dev/mii/rgephy.c int anar, reg, speed, gig = 0;
reg 167 dev/mii/rgephy.c reg = PHY_READ(sc, MII_BMCR);
reg 168 dev/mii/rgephy.c PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
reg 256 dev/mii/rgephy.c reg = PHY_READ(sc, RL_GMEDIASTAT);
reg 257 dev/mii/rgephy.c if (reg & RL_GMEDIASTAT_LINK)
reg 162 dev/mii/sqphy.c int reg;
reg 182 dev/mii/sqphy.c reg = PHY_READ(sc, MII_BMCR);
reg 183 dev/mii/sqphy.c PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
reg 197 dev/mii/tlphy.c int reg;
reg 220 dev/mii/tlphy.c reg = PHY_READ(&sc->sc_mii, MII_BMCR);
reg 221 dev/mii/tlphy.c PHY_WRITE(&sc->sc_mii, MII_BMCR, reg | BMCR_ISO);
reg 164 dev/mii/tqphy.c int reg;
reg 184 dev/mii/tqphy.c reg = PHY_READ(sc, MII_BMCR);
reg 185 dev/mii/tqphy.c PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
reg 155 dev/mii/ukphy.c int reg;
reg 175 dev/mii/ukphy.c reg = PHY_READ(sc, MII_BMCR);
reg 176 dev/mii/ukphy.c PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
reg 140 dev/mii/urlphy.c int reg;
reg 191 dev/mii/urlphy.c reg = PHY_READ(sc, URLPHY_MSR) | PHY_READ(sc, URLPHY_MSR);
reg 192 dev/mii/urlphy.c if (reg & URLPHY_MSR_LINK)
reg 140 dev/mii/xmphy.c int reg;
reg 160 dev/mii/xmphy.c reg = PHY_READ(sc, MII_BMCR);
reg 161 dev/mii/xmphy.c PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
reg 217 dev/mii/xmphy.c reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
reg 218 dev/mii/xmphy.c if (reg & BMSR_LINK)
reg 83 dev/pci/agp_ali.c pcireg_t reg;
reg 119 dev/pci/agp_ali.c reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, AGP_ALI_ATTBASE);
reg 120 dev/pci/agp_ali.c reg = (reg & 0xff) | gatt->ag_physical;
reg 121 dev/pci/agp_ali.c pci_conf_write(sc->sc_pc, sc->sc_pcitag, AGP_ALI_ATTBASE, reg);
reg 124 dev/pci/agp_ali.c reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, AGP_ALI_TLBCTRL);
reg 125 dev/pci/agp_ali.c reg = (reg & ~0xff) | 0x10;
reg 126 dev/pci/agp_ali.c pci_conf_write(sc->sc_pc, sc->sc_pcitag, AGP_ALI_TLBCTRL, reg);
reg 136 dev/pci/agp_ali.c pcireg_t reg;
reg 144 dev/pci/agp_ali.c reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, AGP_ALI_TLBCTRL);
reg 145 dev/pci/agp_ali.c reg &= ~0xff;
reg 146 dev/pci/agp_ali.c reg |= 0x90;
reg 147 dev/pci/agp_ali.c pci_conf_write(sc->sc_pc, sc->sc_pcitag, AGP_ALI_TLBCTRL, reg);
reg 151 dev/pci/agp_ali.c reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, AGP_ALI_ATTBASE);
reg 152 dev/pci/agp_ali.c reg &= 0xff;
reg 153 dev/pci/agp_ali.c pci_conf_write(sc->sc_pc, sc->sc_pcitag, AGP_ALI_ATTBASE, reg);
reg 197 dev/pci/agp_ali.c pcireg_t reg;
reg 205 dev/pci/agp_ali.c reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, AGP_ALI_ATTBASE);
reg 206 dev/pci/agp_ali.c reg &= ~0xff;
reg 207 dev/pci/agp_ali.c reg |= i;
reg 208 dev/pci/agp_ali.c pci_conf_write(sc->sc_pc, sc->sc_pcitag, AGP_ALI_ATTBASE, reg);
reg 239 dev/pci/agp_ali.c pcireg_t reg;
reg 241 dev/pci/agp_ali.c reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, AGP_ALI_TLBCTRL);
reg 242 dev/pci/agp_ali.c reg &= ~0xff;
reg 243 dev/pci/agp_ali.c reg |= 0x90;
reg 244 dev/pci/agp_ali.c pci_conf_write(sc->sc_pc, sc->sc_pcitag, AGP_ALI_TLBCTRL, reg);
reg 245 dev/pci/agp_ali.c reg &= ~0xff;
reg 246 dev/pci/agp_ali.c reg |= 0x10;
reg 247 dev/pci/agp_ali.c pci_conf_write(sc->sc_pc, sc->sc_pcitag, AGP_ALI_TLBCTRL, reg);
reg 162 dev/pci/agp_amd.c pcireg_t reg;
reg 211 dev/pci/agp_amd.c reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, AGP_AMD751_MODECTRL);
reg 212 dev/pci/agp_amd.c reg &= ~0x00ff00ff;
reg 213 dev/pci/agp_amd.c reg |= (AGP_AMD751_MODECTRL_SYNEN) | (AGP_AMD751_MODECTRL2_GPDCE << 16);
reg 214 dev/pci/agp_amd.c pci_conf_write(sc->sc_pc, sc->sc_pcitag, AGP_AMD751_MODECTRL, reg);
reg 227 dev/pci/agp_amd.c pcireg_t reg;
reg 235 dev/pci/agp_amd.c reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, AGP_AMD751_MODECTRL);
reg 236 dev/pci/agp_amd.c reg &= 0xffffff00;
reg 237 dev/pci/agp_amd.c pci_conf_write(sc->sc_pc, sc->sc_pcitag, AGP_AMD751_MODECTRL, reg);
reg 271 dev/pci/agp_amd.c pcireg_t reg;
reg 284 dev/pci/agp_amd.c reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, AGP_AMD751_APCTRL);
reg 285 dev/pci/agp_amd.c reg = (reg & ~0x06) | (vas << 1);
reg 286 dev/pci/agp_amd.c pci_conf_write(sc->sc_pc, sc->sc_pcitag, AGP_AMD751_APCTRL, reg);
reg 230 dev/pci/agp_i810.c pcireg_t reg;
reg 234 dev/pci/agp_i810.c reg = pci_conf_read(isc->bridge_pa.pa_pc,
reg 236 dev/pci/agp_i810.c gcc1 = (u_int16_t)(reg >> 16);
reg 269 dev/pci/agp_i810.c pcireg_t reg;
reg 273 dev/pci/agp_i810.c reg = pci_conf_read(isc->bridge_pa.pa_pc,
reg 275 dev/pci/agp_i810.c gcc1 = (u_int16_t)(reg >> 16);
reg 319 dev/pci/agp_i810.c pcireg_t reg;
reg 338 dev/pci/agp_i810.c reg = pci_conf_read(isc->bridge_pa.pa_pc,
reg 340 dev/pci/agp_i810.c gcc1 = (u_int16_t)(reg >> 16);
reg 372 dev/pci/agp_i810.c "disabling\n", reg);
reg 391 dev/pci/agp_i810.c pcireg_t reg;
reg 395 dev/pci/agp_i810.c reg = pci_conf_read(isc->bridge_pa.pa_pc,
reg 397 dev/pci/agp_i810.c gcc1 = (u_int16_t)(reg >> 16);
reg 448 dev/pci/agp_i810.c pcireg_t reg;
reg 453 dev/pci/agp_i810.c reg = pci_conf_read(isc->bridge_pa.pa_pc,
reg 455 dev/pci/agp_i810.c miscc = (u_int16_t)(reg >> 16);
reg 464 dev/pci/agp_i810.c reg = pci_conf_read(isc->bridge_pa.pa_pc,
reg 466 dev/pci/agp_i810.c gcc1 = (u_int16_t)(reg >> 16);
reg 472 dev/pci/agp_i810.c reg = pci_conf_read(isc->bridge_pa.pa_pc,
reg 474 dev/pci/agp_i810.c if ((reg & AGP_I915_MSAC_GMASIZE) == AGP_I915_MSAC_GMASIZE_128) {
reg 480 dev/pci/agp_i810.c reg = pci_conf_read(isc->bridge_pa.pa_pc,
reg 482 dev/pci/agp_i810.c switch (reg & AGP_I965_MSAC_GMASIZE) {
reg 500 dev/pci/agp_i810.c pcireg_t reg;
reg 514 dev/pci/agp_i810.c reg = pci_conf_read(isc->bridge_pa.pa_pc,
reg 516 dev/pci/agp_i810.c miscc = (u_int16_t)(reg >> 16);
reg 523 dev/pci/agp_i810.c reg &= 0x0000ffff;
reg 524 dev/pci/agp_i810.c reg |= ((pcireg_t)miscc) << 16;
reg 526 dev/pci/agp_i810.c isc->bridge_pa.pa_tag, AGP_I810_SMRAM, reg);
reg 535 dev/pci/agp_i810.c reg = pci_conf_read(isc->bridge_pa.pa_pc,
reg 537 dev/pci/agp_i810.c gcc1 = (u_int16_t)(reg >> 16);
reg 544 dev/pci/agp_i810.c reg &= 0x0000ffff;
reg 545 dev/pci/agp_i810.c reg |= ((pcireg_t)gcc1) << 16;
reg 547 dev/pci/agp_i810.c isc->bridge_pa.pa_tag, AGP_I830_GCC0, reg);
reg 554 dev/pci/agp_i810.c reg = pci_conf_read(isc->bridge_pa.pa_pc,
reg 556 dev/pci/agp_i810.c reg &= ~AGP_I915_MSAC_GMASIZE;
reg 558 dev/pci/agp_i810.c reg |= AGP_I915_MSAC_GMASIZE_128;
reg 560 dev/pci/agp_i810.c reg |= AGP_I915_MSAC_GMASIZE_256;
reg 562 dev/pci/agp_i810.c isc->bridge_pa.pa_tag, AGP_I915_MSAC, reg);
reg 564 dev/pci/agp_i810.c reg = pci_conf_read(isc->bridge_pa.pa_pc,
reg 566 dev/pci/agp_i810.c reg &= ~AGP_I965_MSAC_GMASIZE;
reg 569 dev/pci/agp_i810.c reg |= AGP_I965_MSAC_GMASIZE_128;
reg 572 dev/pci/agp_i810.c reg |= AGP_I965_MSAC_GMASIZE_256;
reg 575 dev/pci/agp_i810.c reg |= AGP_I965_MSAC_GMASIZE_512;
reg 582 dev/pci/agp_i810.c isc->bridge_pa.pa_tag, AGP_I965_MSAC, reg);
reg 83 dev/pci/agp_intel.c pcireg_t reg;
reg 128 dev/pci/agp_intel.c reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, AGP_INTEL_NBXCFG);
reg 129 dev/pci/agp_intel.c reg &= ~(1 << 10);
reg 130 dev/pci/agp_intel.c reg |= (1 << 9);
reg 131 dev/pci/agp_intel.c pci_conf_write(sc->sc_pc, sc->sc_pcitag, AGP_INTEL_NBXCFG, reg);
reg 133 dev/pci/agp_intel.c reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, AGP_INTEL_STS);
reg 134 dev/pci/agp_intel.c reg &= ~0x00ff0000;
reg 135 dev/pci/agp_intel.c reg |= (7 << 16);
reg 136 dev/pci/agp_intel.c pci_conf_write(sc->sc_pc, sc->sc_pcitag, AGP_INTEL_STS, reg);
reg 146 dev/pci/agp_intel.c pcireg_t reg;
reg 153 dev/pci/agp_intel.c reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, AGP_INTEL_NBXCFG);
reg 154 dev/pci/agp_intel.c reg &= ~(1 << 9);
reg 155 dev/pci/agp_intel.c printf("%s: set NBXCFG to %x\n", __FUNCTION__, reg);
reg 156 dev/pci/agp_intel.c pci_conf_write(sc->sc_pc, sc->sc_pcitag, AGP_INTEL_NBXCFG, reg);
reg 187 dev/pci/agp_intel.c pcireg_t reg;
reg 200 dev/pci/agp_intel.c reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, AGP_INTEL_APSIZE);
reg 201 dev/pci/agp_intel.c reg = (reg & 0xffffff00) | apsize;
reg 202 dev/pci/agp_intel.c pci_conf_write(sc->sc_pc, sc->sc_pcitag, AGP_INTEL_APSIZE, reg);
reg 82 dev/pci/agp_sis.c pcireg_t reg;
reg 122 dev/pci/agp_sis.c reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, AGP_SIS_WINCTRL);
reg 123 dev/pci/agp_sis.c reg |= (0x05 << 24) | 3;
reg 124 dev/pci/agp_sis.c pci_conf_write(sc->sc_pc, sc->sc_pcitag, AGP_SIS_WINCTRL, reg);
reg 134 dev/pci/agp_sis.c pcireg_t reg;
reg 141 dev/pci/agp_sis.c reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, AGP_SIS_WINCTRL);
reg 142 dev/pci/agp_sis.c reg &= ~3;
reg 143 dev/pci/agp_sis.c reg &= 0x00ffffff;
reg 144 dev/pci/agp_sis.c pci_conf_write(sc->sc_pc, sc->sc_pcitag, AGP_SIS_WINCTRL, reg);
reg 171 dev/pci/agp_sis.c pcireg_t reg;
reg 184 dev/pci/agp_sis.c reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, AGP_SIS_WINCTRL);
reg 185 dev/pci/agp_sis.c reg &= ~0x00000070;
reg 186 dev/pci/agp_sis.c reg |= gws << 4;
reg 187 dev/pci/agp_sis.c pci_conf_write(sc->sc_pc, sc->sc_pcitag, AGP_SIS_WINCTRL, reg);
reg 219 dev/pci/agp_sis.c pcireg_t reg;
reg 221 dev/pci/agp_sis.c reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, AGP_SIS_TLBFLUSH);
reg 222 dev/pci/agp_sis.c reg &= 0xffffff00;
reg 223 dev/pci/agp_sis.c reg |= 0x02;
reg 224 dev/pci/agp_sis.c pci_conf_write(sc->sc_pc, sc->sc_pcitag, AGP_SIS_TLBFLUSH, reg);
reg 169 dev/pci/agp_via.c pcireg_t reg;
reg 182 dev/pci/agp_via.c reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, AGP_VIA_APSIZE);
reg 183 dev/pci/agp_via.c reg &= ~0xff;
reg 184 dev/pci/agp_via.c reg |= apsize;
reg 185 dev/pci/agp_via.c pci_conf_write(sc->sc_pc, sc->sc_pcitag, AGP_VIA_APSIZE, reg);
reg 764 dev/pci/ahci.c u_int32_t reg, cap, pi;
reg 794 dev/pci/ahci.c reg = ahci_read(sc, AHCI_REG_VS);
reg 795 dev/pci/ahci.c switch (reg) {
reg 807 dev/pci/ahci.c printf(" unsupported AHCI revision 0x%08x\n", reg);
reg 342 dev/pci/ahd_pci.c pcireg_t devconfig, memtype, reg, subid;
reg 464 dev/pci/ahd_pci.c reg = pci_conf_read(pa->pa_pc, pa->pa_tag, offset);
reg 465 dev/pci/ahd_pci.c if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) {
reg 467 dev/pci/ahd_pci.c (reg & ~PCI_PMCSR_STATE_MASK) | PCI_PMCSR_STATE_D0);
reg 938 dev/pci/ahd_pci.c u_int reg;
reg 952 dev/pci/ahd_pci.c for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) {
reg 956 dev/pci/ahd_pci.c pci_status[i] = ahd_inb(ahd, reg);
reg 958 dev/pci/ahd_pci.c ahd_outb(ahd, reg, pci_status[i]);
reg 145 dev/pci/alipm.c pcireg_t iobase, reg;
reg 149 dev/pci/alipm.c reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
reg 150 dev/pci/alipm.c if ((reg & PCI_STATUS_CAPLIST_SUPPORT) == 0) {
reg 161 dev/pci/alipm.c reg = pci_conf_read(pa->pa_pc, pa->pa_tag, ALIPM_CONF);
reg 162 dev/pci/alipm.c if ((reg & ALIPM_CONF_SMBEN) == 0) {
reg 167 dev/pci/alipm.c reg = pci_conf_read(pa->pa_pc, pa->pa_tag, ALIPM_SMB_HOSTC);
reg 168 dev/pci/alipm.c if ((reg & ALIPM_SMB_HOSTC_HSTEN) == 0) {
reg 180 dev/pci/alipm.c reg = pci_conf_read(pa->pa_pc, pa->pa_tag, ALIPM_SMB_HOSTX);
reg 181 dev/pci/alipm.c if ((reg & ALIPM_SMB_HOSTC_HSTEN) == 0) {
reg 187 dev/pci/alipm.c switch (reg & ALIPM_SMB_HOSTC_CLOCK) {
reg 194 dev/pci/amdiic.c amdiic_read(struct amdiic_softc *sc, u_int8_t reg)
reg 202 dev/pci/amdiic.c bus_space_write_1(sc->sc_iot, sc->sc_ioh, AMD8111_SMB_SC_DATA, reg);
reg 210 dev/pci/amdiic.c amdiic_write(struct amdiic_softc *sc, u_int8_t reg, u_int8_t val)
reg 218 dev/pci/amdiic.c bus_space_write_1(sc->sc_iot, sc->sc_ioh, AMD8111_SMB_SC_DATA, reg);
reg 227 dev/pci/amdpm.c pcireg_t cfg_reg, reg;
reg 243 dev/pci/amdpm.c reg = pci_conf_read(pa->pa_pc, pa->pa_tag, AMDPM_PMPTR);
reg 244 dev/pci/amdpm.c if (AMDPM_PMBASE(reg) == 0 ||
reg 245 dev/pci/amdpm.c bus_space_map(sc->sc_iot, AMDPM_PMBASE(reg), AMDPM_PMSIZE,
reg 299 dev/pci/amdpm.c reg = pci_conf_read(pa->pa_pc, pa->pa_tag, NFPM_PMPTR);
reg 300 dev/pci/amdpm.c if (AMDPM_PMBASE(reg) == 0 ||
reg 301 dev/pci/amdpm.c bus_space_map(sc->sc_iot, AMDPM_PMBASE(reg), AMDPM_SMB_SIZE, 0,
reg 326 dev/pci/amdpm.c u_int32_t reg;
reg 330 dev/pci/amdpm.c reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, AMDPM_RNGDATA);
reg 331 dev/pci/amdpm.c add_true_randomness(reg);
reg 610 dev/pci/arc.c u_int32_t reg, intrstat;
reg 626 dev/pci/arc.c reg = arc_read(sc, ARC_REG_OUTB_DOORBELL);
reg 627 dev/pci/arc.c arc_write(sc, ARC_REG_OUTB_DOORBELL, reg);
reg 628 dev/pci/arc.c if (reg & ARC_REG_OUTB_DOORBELL_WRITE_OK)
reg 634 dev/pci/arc.c while ((reg = arc_pop(sc)) != 0xffffffff) {
reg 636 dev/pci/arc.c ((reg << ARC_REG_REPLY_QUEUE_ADDR_SHIFT) -
reg 644 dev/pci/arc.c arc_scsi_cmd_done(sc, ccb, reg);
reg 657 dev/pci/arc.c u_int32_t reg;
reg 696 dev/pci/arc.c reg = ccb->ccb_cmd_post;
reg 709 dev/pci/arc.c reg |= ARC_REG_POST_QUEUE_BIGFRAME;
reg 723 dev/pci/arc.c arc_push(sc, reg);
reg 774 dev/pci/arc.c arc_scsi_cmd_done(struct arc_softc *sc, struct arc_ccb *ccb, u_int32_t reg)
reg 789 dev/pci/arc.c if (reg & ARC_REG_REPLY_QUEUE_ERR) {
reg 832 dev/pci/arc.c u_int32_t reg;
reg 835 dev/pci/arc.c reg = arc_pop(sc);
reg 836 dev/pci/arc.c if (reg == 0xffffffff) {
reg 845 dev/pci/arc.c ((reg << ARC_REG_REPLY_QUEUE_ADDR_SHIFT) -
reg 853 dev/pci/arc.c arc_scsi_cmd_done(sc, ccb, reg);
reg 1368 dev/pci/arc.c u_int32_t reg, rwlen;
reg 1395 dev/pci/arc.c reg = ARC_REG_OUTB_DOORBELL_READ_OK;
reg 1398 dev/pci/arc.c if ((reg & ARC_REG_OUTB_DOORBELL_READ_OK) && wdone < wlen) {
reg 1424 dev/pci/arc.c while ((reg = arc_read(sc, ARC_REG_OUTB_DOORBELL)) == 0)
reg 1426 dev/pci/arc.c arc_write(sc, ARC_REG_OUTB_DOORBELL, reg);
reg 1428 dev/pci/arc.c DNPRINTF(ARC_D_DB, "%s: reg: 0x%08x\n", DEVNAME(sc), reg);
reg 1430 dev/pci/arc.c if ((reg & ARC_REG_OUTB_DOORBELL_WRITE_OK) && rdone < rlen) {
reg 544 dev/pci/auich.c auich_read_codec(v, reg, val)
reg 546 dev/pci/auich.c u_int8_t reg;
reg 562 dev/pci/auich.c *val = bus_space_read_2(sc->iot_mix, sc->mix_ioh, reg);
reg 564 dev/pci/auich.c sc->sc_dev.dv_xname, reg, *val));
reg 569 dev/pci/auich.c auich_write_codec(v, reg, val)
reg 571 dev/pci/auich.c u_int8_t reg;
reg 583 dev/pci/auich.c sc->sc_dev.dv_xname, reg, val));
reg 584 dev/pci/auich.c bus_space_write_2(sc->iot_mix, sc->mix_ioh, reg, val);
reg 1449 dev/pci/auixp.c auixp_read_codec(void *aux, u_int8_t reg, u_int16_t *result)
reg 1466 dev/pci/auixp.c data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
reg 1482 dev/pci/auixp.c reg, data >> ATI_REG_PHYS_IN_DATA_SHIFT));
reg 1490 dev/pci/auixp.c if (reg < 0x7c)
reg 1492 dev/pci/auixp.c sc->sc_dev.dv_xname, reg);
reg 1498 dev/pci/auixp.c auixp_write_codec(void *aux, u_int8_t reg, u_int16_t data)
reg 1506 dev/pci/auixp.c DPRINTF(("write ac'97 codec reg 0x%x = 0x%08x\n", reg, data));
reg 1516 dev/pci/auixp.c (((u_int32_t) reg) << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
reg 397 dev/pci/autri.c u_int32_t reg, ready;
reg 452 dev/pci/autri.c reg = TREAD4(sc, addr);
reg 453 dev/pci/autri.c if (reg & ready)
reg 642 dev/pci/autri.c pcireg_t reg;
reg 655 dev/pci/autri.c reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);
reg 656 dev/pci/autri.c pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg & 0xffff0000);
reg 659 dev/pci/autri.c reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);
reg 660 dev/pci/autri.c pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg | 0x00040000);
reg 663 dev/pci/autri.c reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);
reg 664 dev/pci/autri.c pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg & ~0x00040000);
reg 672 dev/pci/autri.c reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);
reg 673 dev/pci/autri.c pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg & 0xffff0000);
reg 676 dev/pci/autri.c reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);
reg 677 dev/pci/autri.c pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg | 0x00010000);
reg 680 dev/pci/autri.c reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);
reg 681 dev/pci/autri.c pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg & ~0x00010000);
reg 689 dev/pci/autri.c reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);
reg 690 dev/pci/autri.c pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg & 0xffff0000);
reg 693 dev/pci/autri.c reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);
reg 694 dev/pci/autri.c pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg | 0x000c0000);
reg 697 dev/pci/autri.c reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);
reg 698 dev/pci/autri.c pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg & ~0x00040000);
reg 708 dev/pci/autri.c reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);
reg 709 dev/pci/autri.c pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg & 0xffff0000);
reg 712 dev/pci/autri.c reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);
reg 713 dev/pci/autri.c pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg | 0x000c0000);
reg 716 dev/pci/autri.c reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);
reg 717 dev/pci/autri.c pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg & ~0x00040000);
reg 762 dev/pci/autri.c u_int32_t reg;
reg 765 dev/pci/autri.c reg = ENDLP_IE;
reg 768 dev/pci/autri.c reg |= BANK_B_EN;
reg 770 dev/pci/autri.c autri_reg_set_4(sc,AUTRI_LFO_GC_CIR,reg);
reg 779 dev/pci/autri.c u_int32_t reg;
reg 781 dev/pci/autri.c reg = (ENDLP_IE | MIDLP_IE);
reg 782 dev/pci/autri.c autri_reg_clear_4(sc,AUTRI_LFO_GC_CIR,reg);
reg 823 dev/pci/autri.c reg = TREAD4(sc,AUTRI_LFO_GC_CIR) & ~0x0000003f;
reg 824 dev/pci/autri.c TWRITE4(sc,AUTRI_LFO_GC_CIR, reg | ch);
reg 1263 dev/pci/autri.c u_int32_t reg, cr[5];
reg 1375 dev/pci/autri.c reg = TREAD4(sc,AUTRI_LFO_GC_CIR) & ~0x0000003f;
reg 1376 dev/pci/autri.c TWRITE4(sc,AUTRI_LFO_GC_CIR, reg | channel);
reg 1508 dev/pci/autri.c int reg;
reg 1510 dev/pci/autri.c reg = (ch & 0x20) ? AUTRI_AINTEN_B : AUTRI_AINTEN_A;
reg 1513 dev/pci/autri.c autri_reg_set_4(sc, reg, 1 << ch);
reg 1521 dev/pci/autri.c int reg;
reg 1523 dev/pci/autri.c reg = (ch & 0x20) ? AUTRI_AINTEN_B : AUTRI_AINTEN_A;
reg 1526 dev/pci/autri.c autri_reg_clear_4(sc, reg, 1 << ch);
reg 1534 dev/pci/autri.c int reg;
reg 1537 dev/pci/autri.c reg = (ch & 0x20) ? AUTRI_START_B : AUTRI_START_A;
reg 1541 dev/pci/autri.c autri_reg_set_4(sc, reg, chmask);
reg 1549 dev/pci/autri.c int reg;
reg 1552 dev/pci/autri.c reg = (ch & 0x20) ? AUTRI_STOP_B : AUTRI_STOP_A;
reg 1556 dev/pci/autri.c autri_reg_set_4(sc, reg, chmask);
reg 403 dev/pci/auvia.c auvia_write_codec(void *addr, u_int8_t reg, u_int16_t val)
reg 411 dev/pci/auvia.c AUVIA_CODEC_PRIVALID | AUVIA_CODEC_INDEX(reg) | val);
reg 418 dev/pci/auvia.c auvia_read_codec(void *addr, u_int8_t reg, u_int16_t *val)
reg 426 dev/pci/auvia.c AUVIA_CODEC_PRIVALID | AUVIA_CODEC_READ | AUVIA_CODEC_INDEX(reg));
reg 173 dev/pci/cac_pci.c pcireg_t reg;
reg 189 dev/pci/cac_pci.c reg = pci_conf_read(pa->pa_pc, pa->pa_tag, i);
reg 191 dev/pci/cac_pci.c if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO) {
reg 192 dev/pci/cac_pci.c if (ior == -1 && PCI_MAPREG_IO_SIZE(reg) != 0)
reg 195 dev/pci/cac_pci.c if (memr == -1 && PCI_MAPREG_MEM_SIZE(reg) != 0)
reg 101 dev/pci/ciss_pci.c pcireg_t reg;
reg 117 dev/pci/ciss_pci.c reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
reg 118 dev/pci/ciss_pci.c if (PCI_VENDOR(reg) == PCI_VENDOR_COMPAQ &&
reg 119 dev/pci/ciss_pci.c (PCI_PRODUCT(reg) == PCI_PRODUCT_COMPAQ_CSA5i ||
reg 120 dev/pci/ciss_pci.c PCI_PRODUCT(reg) == PCI_PRODUCT_COMPAQ_CSA532 ||
reg 121 dev/pci/ciss_pci.c PCI_PRODUCT(reg) == PCI_PRODUCT_COMPAQ_CSA5312))
reg 324 dev/pci/cs4281.c pcireg_t reg;
reg 327 dev/pci/cs4281.c reg = pci_conf_read(pa->pa_pc, pa->pa_tag, pci_pwrmgmt_csr_reg);
reg 328 dev/pci/cs4281.c if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) {
reg 330 dev/pci/cs4281.c (reg & ~PCI_PMCSR_STATE_MASK) |
reg 112 dev/pci/cy82c693.c cy82c693_read(const struct cy82c693_handle *cyhc, int reg)
reg 124 dev/pci/cy82c693.c bus_space_write_1(cyhc->cyhc_iot, cyhc->cyhc_ioh, 0, reg);
reg 133 dev/pci/cy82c693.c cy82c693_write(const struct cy82c693_handle *cyhc, int reg, u_int8_t val)
reg 144 dev/pci/cy82c693.c bus_space_write_1(cyhc->cyhc_iot, cyhc->cyhc_ioh, 0, reg);
reg 204 dev/pci/cz.c #define CZ_PLX_READ(cz, reg) \
reg 205 dev/pci/cz.c bus_space_read_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, (reg))
reg 206 dev/pci/cz.c #define CZ_PLX_WRITE(cz, reg, val) \
reg 208 dev/pci/cz.c (reg), (val))
reg 214 dev/pci/cz.c #define CZ_FPGA_READ(cz, reg) \
reg 215 dev/pci/cz.c bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg))
reg 216 dev/pci/cz.c #define CZ_FPGA_WRITE(cz, reg, val) \
reg 217 dev/pci/cz.c bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg), (val))
reg 453 dev/pci/cz.c u_int32_t reg;
reg 455 dev/pci/cz.c reg = CZ_PLX_READ(cz, PLX_CONTROL);
reg 456 dev/pci/cz.c CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_SWR);
reg 459 dev/pci/cz.c CZ_PLX_WRITE(cz, PLX_CONTROL, reg);
reg 463 dev/pci/cz.c reg = CZ_PLX_READ(cz, PLX_CONTROL);
reg 464 dev/pci/cz.c CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_RELOADCFG);
reg 466 dev/pci/cz.c CZ_PLX_WRITE(cz, PLX_CONTROL, reg);
reg 221 dev/pci/czreg.h #define ZFIRM_CHNCTL_OFF(chan, reg) \
reg 222 dev/pci/czreg.h (ZFIRM_BRDCTL_SIZE + ((chan) * ZFIRM_CHNCTL_SIZE) + (reg))
reg 223 dev/pci/czreg.h #define ZFIRM_BUFCTL_OFF(chan, reg) \
reg 225 dev/pci/czreg.h ((chan) * ZFIRM_BUFCTL_SIZE) + (reg))
reg 585 dev/pci/emuxki.c emuxki_read(struct emuxki_softc *sc, u_int16_t chano, u_int32_t reg)
reg 591 dev/pci/emuxki.c ptr = ((((u_int32_t) reg) << 16) &
reg 595 dev/pci/emuxki.c if (reg & 0xff000000) {
reg 596 dev/pci/emuxki.c size = (reg >> 24) & 0x3f;
reg 597 dev/pci/emuxki.c offset = (reg >> 16) & 0x1f;
reg 612 dev/pci/emuxki.c u_int32_t reg, u_int32_t data)
reg 618 dev/pci/emuxki.c ptr = ((((u_int32_t) reg) << 16) &
reg 627 dev/pci/emuxki.c if (reg & 0xff000000) {
reg 628 dev/pci/emuxki.c size = (reg >> 24) & 0x3f;
reg 629 dev/pci/emuxki.c offset = (reg >> 16) & 0x1f;
reg 632 dev/pci/emuxki.c (emuxki_read(sc, chano, reg & 0xffff) & ~mask);
reg 2462 dev/pci/emuxki.c emuxki_ac97_read(void *arg, u_int8_t reg, u_int16_t *val)
reg 2468 dev/pci/emuxki.c bus_space_write_1(sc->sc_iot, sc->sc_ioh, EMU_AC97ADDR, reg);
reg 2476 dev/pci/emuxki.c emuxki_ac97_write(void *arg, u_int8_t reg, u_int16_t val)
reg 2482 dev/pci/emuxki.c bus_space_write_1(sc->sc_iot, sc->sc_ioh, EMU_AC97ADDR, reg);
reg 56 dev/pci/emuxkireg.h #define EMU_MKSUBREG(sz, idx, reg) (((sz) << 24) | ((idx) << 16) | (reg))
reg 1218 dev/pci/esa.c esa_read_codec(void *aux, u_int8_t reg, u_int16_t *result)
reg 1226 dev/pci/esa.c bus_space_write_1(iot, ioh, ESA_CODEC_COMMAND, (reg & 0x7f) | 0x80);
reg 1236 dev/pci/esa.c esa_write_codec(void *aux, u_int8_t reg, u_int16_t data)
reg 1247 dev/pci/esa.c bus_space_write_1(iot, ioh, ESA_CODEC_COMMAND, reg & 0x7f);
reg 449 dev/pci/eso.c eso_write_ctlreg(sc, reg, val)
reg 451 dev/pci/eso.c uint8_t reg, val;
reg 456 dev/pci/eso.c eso_write_cmd(sc, reg);
reg 483 dev/pci/eso.c eso_read_ctlreg(sc, reg)
reg 485 dev/pci/eso.c uint8_t reg;
reg 489 dev/pci/eso.c eso_write_cmd(sc, reg);
reg 494 dev/pci/eso.c eso_write_mixreg(sc, reg, val)
reg 496 dev/pci/eso.c uint8_t reg, val;
reg 503 dev/pci/eso.c bus_space_write_1(sc->sc_sb_iot, sc->sc_sb_ioh, ESO_SB_MIXERADDR, reg);
reg 509 dev/pci/eso.c eso_read_mixreg(sc, reg)
reg 511 dev/pci/eso.c uint8_t reg;
reg 517 dev/pci/eso.c bus_space_write_1(sc->sc_sb_iot, sc->sc_sb_ioh, ESO_SB_MIXERADDR, reg);
reg 308 dev/pci/fms.c fms_read_codec(addr, reg, val)
reg 310 dev/pci/fms.c u_int8_t reg;
reg 327 dev/pci/fms.c reg | FM_CODEC_CMD_READ);
reg 344 dev/pci/fms.c fms_write_codec(addr, reg, val)
reg 346 dev/pci/fms.c u_int8_t reg;
reg 364 dev/pci/fms.c bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_CODEC_CMD, reg);
reg 485 dev/pci/hifn7751.c u_int32_t reg;
reg 521 dev/pci/hifn7751.c for (reg = 0; reg < 1000; reg++) {
reg 527 dev/pci/hifn7751.c if (reg == 1000)
reg 2793 dev/pci/hifn7751.c hifn_write_4(struct hifn_softc *sc, int reggrp, bus_size_t reg,
reg 2803 dev/pci/hifn7751.c sc->sc_waw_lastreg == reg - 4) {
reg 2807 dev/pci/hifn7751.c sc->sc_waw_lastreg = reg;
reg 2810 dev/pci/hifn7751.c bus_space_write_4(sc->sc_st0, sc->sc_sh0, reg, val);
reg 2812 dev/pci/hifn7751.c bus_space_write_4(sc->sc_st1, sc->sc_sh1, reg, val);
reg 2817 dev/pci/hifn7751.c hifn_read_4(struct hifn_softc *sc, int reggrp, bus_size_t reg)
reg 2824 dev/pci/hifn7751.c return (bus_space_read_4(sc->sc_st0, sc->sc_sh0, reg));
reg 2825 dev/pci/hifn7751.c return (bus_space_read_4(sc->sc_st1, sc->sc_sh1, reg));
reg 169 dev/pci/hifn7751var.h #define WRITE_REG_0(sc,reg,val) hifn_write_4((sc), 0, (reg), (val))
reg 170 dev/pci/hifn7751var.h #define WRITE_REG_1(sc,reg,val) hifn_write_4((sc), 1, (reg), (val))
reg 171 dev/pci/hifn7751var.h #define READ_REG_0(sc,reg) hifn_read_4((sc), 0, (reg))
reg 172 dev/pci/hifn7751var.h #define READ_REG_1(sc,reg) hifn_read_4((sc), 1, (reg))
reg 74 dev/pci/ichwdt.c ichwdt_unlock_write(struct ichwdt_softc *sc, int reg, u_int32_t val)
reg 81 dev/pci/ichwdt.c bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, val);
reg 96 dev/pci/ichwdt.c u_int32_t reg;
reg 110 dev/pci/ichwdt.c reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ICH_WDT_CONF);
reg 111 dev/pci/ichwdt.c DPRINTF((": conf 0x%x", reg));
reg 114 dev/pci/ichwdt.c sc->sc_divisor = (reg & ICH_WDT_CONF_PRE ? 32 : 32768);
reg 115 dev/pci/ichwdt.c printf(": %s clock", (reg & ICH_WDT_CONF_PRE ? "1MHz" : "1kHz"));
reg 118 dev/pci/ichwdt.c reg &= ~ICH_WDT_CONF_INT_MASK;
reg 119 dev/pci/ichwdt.c reg |= ICH_WDT_CONF_INT_DIS;
reg 120 dev/pci/ichwdt.c pci_conf_write(sc->sc_pc, sc->sc_tag, ICH_WDT_CONF, reg);
reg 123 dev/pci/ichwdt.c reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ICH_WDT_RELOAD);
reg 124 dev/pci/ichwdt.c if (reg & ICH_WDT_RELOAD_TIMEOUT) {
reg 154 dev/pci/if_atw_pci.c pcireg_t reg;
reg 182 dev/pci/if_atw_pci.c reg = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR);
reg 183 dev/pci/if_atw_pci.c switch (reg & PCI_PMCSR_STATE_MASK) {
reg 187 dev/pci/if_atw_pci.c reg & PCI_PMCSR_STATE_MASK, sc->sc_dev.dv_xname);
reg 189 dev/pci/if_atw_pci.c (reg & ~PCI_PMCSR_STATE_MASK) |
reg 200 dev/pci/if_atw_pci.c (reg & ~PCI_PMCSR_STATE_MASK) |
reg 1377 dev/pci/if_bce.c bce_mii_read(struct device *self, int phy, int reg)
reg 1389 dev/pci/if_bce.c (MII_COMMAND_ACK << 16) | BCE_MIPHY(phy) | BCE_MIREG(reg)); /* MAGIC */
reg 1400 dev/pci/if_bce.c "0x%08x\n", sc->bce_dev.dv_xname, phy, reg, val);
reg 1408 dev/pci/if_bce.c bce_mii_write(struct device *self, int phy, int reg, int val)
reg 1422 dev/pci/if_bce.c BCE_MIPHY(phy) | BCE_MIREG(reg));
reg 1435 dev/pci/if_bce.c "= 0x%08x\n", sc->bce_dev.dv_xname, phy, reg, val);
reg 1444 dev/pci/if_bce.c u_int32_t reg;
reg 1447 dev/pci/if_bce.c reg = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL);
reg 1448 dev/pci/if_bce.c if (sc->bce_mii.mii_media_active & IFM_FDX && !(reg & EXC_FD))
reg 1450 dev/pci/if_bce.c reg | EXC_FD);
reg 1451 dev/pci/if_bce.c else if (!(sc->bce_mii.mii_media_active & IFM_FDX) && reg & EXC_FD)
reg 1453 dev/pci/if_bce.c reg & ~EXC_FD);
reg 483 dev/pci/if_bge.c bge_miibus_readreg(struct device *dev, int phy, int reg)
reg 509 dev/pci/if_bge.c BGE_MIPHY(phy)|BGE_MIREG(reg));
reg 540 dev/pci/if_bge.c bge_miibus_writereg(struct device *dev, int phy, int reg, int val)
reg 555 dev/pci/if_bge.c BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
reg 3213 dev/pci/if_bge.c bge_stop_block(struct bge_softc *sc, bus_size_t reg, u_int32_t bit)
reg 3217 dev/pci/if_bge.c BGE_CLRBIT(sc, reg, bit);
reg 3220 dev/pci/if_bge.c if ((CSR_READ_4(sc, reg) & bit) == 0)
reg 3226 dev/pci/if_bge.c sc->bge_dev.dv_xname, (u_long) reg, bit));
reg 2239 dev/pci/if_bgereg.h #define CSR_WRITE_4(sc, reg, val) \
reg 2240 dev/pci/if_bgereg.h bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val)
reg 2242 dev/pci/if_bgereg.h #define CSR_READ_4(sc, reg) \
reg 2243 dev/pci/if_bgereg.h bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg)
reg 2245 dev/pci/if_bgereg.h #define BGE_SETBIT(sc, reg, x) \
reg 2246 dev/pci/if_bgereg.h CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x)))
reg 2247 dev/pci/if_bgereg.h #define BGE_CLRBIT(sc, reg, x) \
reg 2248 dev/pci/if_bgereg.h CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x)))
reg 2250 dev/pci/if_bgereg.h #define PCI_SETBIT(pc, tag, reg, x) \
reg 2251 dev/pci/if_bgereg.h pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x)))
reg 2252 dev/pci/if_bgereg.h #define PCI_CLRBIT(pc, tag, reg, x) \
reg 2253 dev/pci/if_bgereg.h pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~(x)))
reg 1084 dev/pci/if_bnx.c bnx_miibus_read_reg(struct device *dev, int phy, int reg)
reg 1107 dev/pci/if_bnx.c val = BNX_MIPHY(phy) | BNX_MIREG(reg) |
reg 1128 dev/pci/if_bnx.c "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg);
reg 1135 dev/pci/if_bnx.c (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff);
reg 1159 dev/pci/if_bnx.c bnx_miibus_write_reg(struct device *dev, int phy, int reg, int val)
reg 1174 dev/pci/if_bnx.c phy, (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff);
reg 1186 dev/pci/if_bnx.c val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val |
reg 3128 dev/pci/if_bnx.c u_int32_t reg, val;
reg 3183 dev/pci/if_bnx.c reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_SIGNATURE);
reg 3187 dev/pci/if_bnx.c __FILE__, __LINE__); reg = 0);
reg 3189 dev/pci/if_bnx.c if ((reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
reg 3193 dev/pci/if_bnx.c (reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK),
reg 3200 dev/pci/if_bnx.c reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_FEATURE);
reg 3201 dev/pci/if_bnx.c if (reg & (BNX_PORT_FEATURE_ASF_ENABLED |
reg 663 dev/pci/if_bnxreg.h #define REG_WR(sc, reg, val) bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, reg, val)
reg 664 dev/pci/if_bnxreg.h #define REG_WR16(sc, reg, val) bus_space_write_2(sc->bnx_btag, sc->bnx_bhandle, reg, val)
reg 665 dev/pci/if_bnxreg.h #define REG_RD(sc, reg) bus_space_read_4(sc->bnx_btag, sc->bnx_bhandle, reg)
reg 669 dev/pci/if_bnxreg.h #define BNX_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x)))
reg 670 dev/pci/if_bnxreg.h #define BNX_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x)))
reg 671 dev/pci/if_bnxreg.h #define PCI_SETBIT(pc, tag, reg, x) pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x)))
reg 672 dev/pci/if_bnxreg.h #define PCI_CLRBIT(pc, tag, reg, x) pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~(x)))
reg 651 dev/pci/if_cas.c u_int32_t reg;
reg 654 dev/pci/if_cas.c reg = bus_space_read_4(sc->sc_memt, h, r);
reg 655 dev/pci/if_cas.c if ((reg & clr) == 0 && (reg & set) == set)
reg 1423 dev/pci/if_cas.c cas_mii_readreg(struct device *self, int phy, int reg)
reg 1433 dev/pci/if_cas.c printf("cas_mii_readreg: phy %d reg %d\n", phy, reg);
reg 1437 dev/pci/if_cas.c v = (reg << CAS_MIF_REG_SHIFT) | (phy << CAS_MIF_PHY_SHIFT) |
reg 1453 dev/pci/if_cas.c cas_mii_writereg(struct device *self, int phy, int reg, int val)
reg 1464 dev/pci/if_cas.c phy, reg, val);
reg 1480 dev/pci/if_cas.c (reg << CAS_MIF_REG_SHIFT) |
reg 1545 dev/pci/if_cas.c cas_pcs_readreg(struct device *self, int phy, int reg)
reg 1553 dev/pci/if_cas.c printf("cas_pcs_readreg: phy %d reg %d\n", phy, reg);
reg 1559 dev/pci/if_cas.c switch (reg) {
reg 1561 dev/pci/if_cas.c reg = CAS_MII_CONTROL;
reg 1564 dev/pci/if_cas.c reg = CAS_MII_STATUS;
reg 1567 dev/pci/if_cas.c reg = CAS_MII_ANAR;
reg 1570 dev/pci/if_cas.c reg = CAS_MII_ANLPAR;
reg 1578 dev/pci/if_cas.c return bus_space_read_4(t, pcs, reg);
reg 1582 dev/pci/if_cas.c cas_pcs_writereg(struct device *self, int phy, int reg, int val)
reg 1591 dev/pci/if_cas.c phy, reg, val);
reg 1597 dev/pci/if_cas.c switch (reg) {
reg 1599 dev/pci/if_cas.c reg = CAS_MII_CONTROL;
reg 1602 dev/pci/if_cas.c reg = CAS_MII_STATUS;
reg 1605 dev/pci/if_cas.c reg = CAS_MII_ANAR;
reg 1608 dev/pci/if_cas.c reg = CAS_MII_ANLPAR;
reg 1614 dev/pci/if_cas.c bus_space_write_4(t, pcs, reg, val);
reg 1616 dev/pci/if_cas.c if (reg == CAS_MII_ANAR) {
reg 698 dev/pci/if_che.c che_miibus_readreg(struct device *dev, int phy, int reg)
reg 701 dev/pci/if_che.c u_int32_t addr = CHE_MI1_PHYADDR(phy) | reg;
reg 713 dev/pci/if_che.c che_miibus_writereg(struct device *dev, int phy, int reg, int val)
reg 716 dev/pci/if_che.c u_int32_t addr = CHE_MI1_PHYADDR(phy) | reg;
reg 725 dev/pci/if_che.c che_miibus_ind_readreg(struct device *dev, int phy, int reg)
reg 730 dev/pci/if_che.c che_write(sc->sc_cheg, CHE_REG_MI1_DATA, reg);
reg 745 dev/pci/if_che.c che_miibus_ind_writereg(struct device *dev, int phy, int reg, int val)
reg 750 dev/pci/if_che.c che_write(sc->sc_cheg, CHE_REG_MI1_DATA, reg);
reg 1400 dev/pci/if_em.c u_int32_t reg;
reg 1411 dev/pci/if_em.c reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG);
reg 1412 dev/pci/if_em.c sc->hw.revision_id = PCI_REVISION(reg);
reg 1414 dev/pci/if_em.c reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
reg 1415 dev/pci/if_em.c sc->hw.subsystem_vendor_id = PCI_VENDOR(reg);
reg 1416 dev/pci/if_em.c sc->hw.subsystem_id = PCI_PRODUCT(reg);
reg 2777 dev/pci/if_em.c em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value)
reg 2782 dev/pci/if_em.c pci_conf_write(pc, pa->pa_tag, reg, *value);
reg 2786 dev/pci/if_em.c em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value)
reg 2790 dev/pci/if_em.c *value = pci_conf_read(pc, pa->pa_tag, reg);
reg 2814 dev/pci/if_em.c em_read_pcie_cap_reg(struct em_hw *hw, uint32_t reg, uint16_t *value)
reg 2823 dev/pci/if_em.c em_read_pci_cfg(hw, reg + 0x12, value);
reg 2825 dev/pci/if_em.c em_read_pci_cfg(hw, reg + 0x8, &pectl);
reg 2827 dev/pci/if_em.c em_write_pci_cfg(hw, reg + 0x8, &pectl);
reg 3962 dev/pci/if_em_hw.c int32_t reg;
reg 3995 dev/pci/if_em_hw.c reg = E1000_READ_REG(hw, PHY_CTRL);
reg 3996 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
reg 4847 dev/pci/if_em_hw.c uint32_t i, reg = 0;
reg 4852 dev/pci/if_em_hw.c reg = E1000_READ_REG(hw, EERD);
reg 4854 dev/pci/if_em_hw.c reg = E1000_READ_REG(hw, EEWR);
reg 4856 dev/pci/if_em_hw.c if (reg & E1000_EEPROM_RW_REG_DONE) {
reg 379 dev/pci/if_em_hw.h int32_t em_read_eeprom(struct em_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
reg 382 dev/pci/if_em_hw.h int32_t em_write_eeprom(struct em_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
reg 410 dev/pci/if_em_hw.h void em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value);
reg 411 dev/pci/if_em_hw.h void em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value);
reg 412 dev/pci/if_em_hw.h int32_t em_read_pcie_cap_reg(struct em_hw *hw, uint32_t reg, uint16_t *value);
reg 418 dev/pci/if_em_hw.h #define E1000_READ_REG_IO(a, reg) \
reg 419 dev/pci/if_em_hw.h em_read_reg_io((a), E1000_##reg)
reg 420 dev/pci/if_em_hw.h #define E1000_WRITE_REG_IO(a, reg, val) \
reg 421 dev/pci/if_em_hw.h em_write_reg_io((a), E1000_##reg, val)
reg 2627 dev/pci/if_em_hw.h #define GG82563_REG(page, reg) \
reg 2628 dev/pci/if_em_hw.h (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
reg 3146 dev/pci/if_em_hw.h #define PHY_REG(page, reg) \
reg 3147 dev/pci/if_em_hw.h (((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
reg 99 dev/pci/if_em_osdep.h #define E1000_REG_OFFSET(hw, reg) \
reg 100 dev/pci/if_em_osdep.h ((hw)->mac_type >= em_82543 ? E1000_##reg : E1000_82542_##reg)
reg 104 dev/pci/if_em_osdep.h #define E1000_READ_REG(hw, reg) \
reg 107 dev/pci/if_em_osdep.h ((hw)->mac_type >= em_82543 ? E1000_##reg : E1000_82542_##reg))
reg 109 dev/pci/if_em_osdep.h #define E1000_WRITE_REG(hw, reg, value) \
reg 112 dev/pci/if_em_osdep.h ((hw)->mac_type >= em_82543 ? E1000_##reg : E1000_82542_##reg), \
reg 115 dev/pci/if_em_osdep.h #define E1000_READ_REG_ARRAY(hw, reg, index) \
reg 118 dev/pci/if_em_osdep.h ((hw)->mac_type >= em_82543 ? E1000_##reg : E1000_82542_##reg) \
reg 121 dev/pci/if_em_osdep.h #define E1000_WRITE_REG_ARRAY(hw, reg, index, value) \
reg 124 dev/pci/if_em_osdep.h ((hw)->mac_type >= em_82543 ? E1000_##reg : E1000_82542_##reg) \
reg 130 dev/pci/if_em_osdep.h #define E1000_WRITE_REG_ARRAY_BYTE(hw, reg, index, value) \
reg 133 dev/pci/if_em_osdep.h ((hw)->mac_type >= em_82543 ? E1000_##reg : E1000_82542_##reg \
reg 136 dev/pci/if_em_osdep.h #define E1000_WRITE_REG_ARRAY_WORD(hw, reg, index, value) \
reg 139 dev/pci/if_em_osdep.h ((hw)->mac_type >= em_82543 ? E1000_##reg : E1000_82542_##reg \
reg 142 dev/pci/if_em_osdep.h #define E1000_READ_ICH_FLASH_REG(hw, reg) \
reg 144 dev/pci/if_em_osdep.h ((struct em_osdep *)(hw)->back)->flash_bus_space_handle, reg)
reg 146 dev/pci/if_em_osdep.h #define E1000_READ_ICH_FLASH_REG16(hw, reg) \
reg 148 dev/pci/if_em_osdep.h ((struct em_osdep *)(hw)->back)->flash_bus_space_handle, reg)
reg 150 dev/pci/if_em_osdep.h #define E1000_WRITE_ICH_FLASH_REG(hw, reg, value) \
reg 153 dev/pci/if_em_osdep.h reg, value)
reg 155 dev/pci/if_em_osdep.h #define E1000_WRITE_ICH_FLASH_REG16(hw, reg, value) \
reg 158 dev/pci/if_em_osdep.h reg, value)
reg 130 dev/pci/if_epic_pci.c pcireg_t reg;
reg 133 dev/pci/if_epic_pci.c reg = pci_conf_read(pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
reg 136 dev/pci/if_epic_pci.c if (esp->subsysid == reg)
reg 161 dev/pci/if_epic_pci.c pcireg_t reg;
reg 165 dev/pci/if_epic_pci.c reg = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR);
reg 166 dev/pci/if_epic_pci.c switch (reg & PCI_PMCSR_STATE_MASK) {
reg 170 dev/pci/if_epic_pci.c reg & PCI_PMCSR_STATE_MASK);
reg 172 dev/pci/if_epic_pci.c (reg & ~PCI_PMCSR_STATE_MASK) |
reg 184 dev/pci/if_epic_pci.c (reg & ~PCI_PMCSR_STATE_MASK) |
reg 276 dev/pci/if_ipwreg.h #define CSR_READ_1(sc, reg) \
reg 277 dev/pci/if_ipwreg.h bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))
reg 279 dev/pci/if_ipwreg.h #define CSR_READ_2(sc, reg) \
reg 280 dev/pci/if_ipwreg.h bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))
reg 282 dev/pci/if_ipwreg.h #define CSR_READ_4(sc, reg) \
reg 283 dev/pci/if_ipwreg.h bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
reg 285 dev/pci/if_ipwreg.h #define CSR_WRITE_1(sc, reg, val) \
reg 286 dev/pci/if_ipwreg.h bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
reg 288 dev/pci/if_ipwreg.h #define CSR_WRITE_2(sc, reg, val) \
reg 289 dev/pci/if_ipwreg.h bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
reg 291 dev/pci/if_ipwreg.h #define CSR_WRITE_4(sc, reg, val) \
reg 292 dev/pci/if_ipwreg.h bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
reg 294 dev/pci/if_ipwreg.h #define CSR_WRITE_MULTI_1(sc, reg, buf, len) \
reg 295 dev/pci/if_ipwreg.h bus_space_write_multi_1((sc)->sc_st, (sc)->sc_sh, (reg), \
reg 623 dev/pci/if_iwi.c data->reg = IWI_CSR_RX_BASE + i * 4;
reg 925 dev/pci/if_iwi.c CSR_WRITE_4(sc, data->reg, data->map->dm_segs[0].ds_addr);
reg 2222 dev/pci/if_iwi.c CSR_WRITE_4(sc, data->reg, data->map->dm_segs[0].ds_addr);
reg 425 dev/pci/if_iwireg.h #define CSR_READ_1(sc, reg) \
reg 426 dev/pci/if_iwireg.h bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))
reg 428 dev/pci/if_iwireg.h #define CSR_READ_2(sc, reg) \
reg 429 dev/pci/if_iwireg.h bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))
reg 431 dev/pci/if_iwireg.h #define CSR_READ_4(sc, reg) \
reg 432 dev/pci/if_iwireg.h bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
reg 438 dev/pci/if_iwireg.h #define CSR_WRITE_1(sc, reg, val) \
reg 439 dev/pci/if_iwireg.h bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
reg 441 dev/pci/if_iwireg.h #define CSR_WRITE_2(sc, reg, val) \
reg 442 dev/pci/if_iwireg.h bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
reg 444 dev/pci/if_iwireg.h #define CSR_WRITE_4(sc, reg, val) \
reg 445 dev/pci/if_iwireg.h bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
reg 89 dev/pci/if_iwivar.h uint32_t reg;
reg 892 dev/pci/if_ixgb.c u_int32_t reg;
reg 903 dev/pci/if_ixgb.c reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG);
reg 904 dev/pci/if_ixgb.c sc->hw.revision_id = PCI_REVISION(reg);
reg 906 dev/pci/if_ixgb.c reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
reg 907 dev/pci/if_ixgb.c sc->hw.subsystem_vendor_id = PCI_VENDOR(reg);
reg 908 dev/pci/if_ixgb.c sc->hw.subsystem_id = PCI_PRODUCT(reg);
reg 1943 dev/pci/if_ixgb.c uint32_t reg,
reg 1949 dev/pci/if_ixgb.c pci_conf_write(pc, pa->pa_tag, reg, *value);
reg 80 dev/pci/if_ixgb_osdep.h #define IXGB_READ_REG(a, reg) \
reg 83 dev/pci/if_ixgb_osdep.h IXGB_##reg)
reg 85 dev/pci/if_ixgb_osdep.h #define IXGB_WRITE_REG(a, reg, value) \
reg 88 dev/pci/if_ixgb_osdep.h IXGB_##reg, value)
reg 90 dev/pci/if_ixgb_osdep.h #define IXGB_READ_REG_ARRAY(a, reg, offset) \
reg 93 dev/pci/if_ixgb_osdep.h (IXGB_##reg + ((offset) << 2)))
reg 95 dev/pci/if_ixgb_osdep.h #define IXGB_WRITE_REG_ARRAY(a, reg, offset, value) \
reg 98 dev/pci/if_ixgb_osdep.h (IXGB_##reg + ((offset) << 2)), value)
reg 174 dev/pci/if_lge.c #define LGE_SETBIT(sc, reg, x) \
reg 175 dev/pci/if_lge.c CSR_WRITE_4(sc, reg, \
reg 176 dev/pci/if_lge.c CSR_READ_4(sc, reg) | (x))
reg 178 dev/pci/if_lge.c #define LGE_CLRBIT(sc, reg, x) \
reg 179 dev/pci/if_lge.c CSR_WRITE_4(sc, reg, \
reg 180 dev/pci/if_lge.c CSR_READ_4(sc, reg) & ~(x))
reg 238 dev/pci/if_lge.c lge_miibus_readreg(struct device *dev, int phy, int reg)
reg 251 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);
reg 266 dev/pci/if_lge.c lge_miibus_writereg(struct device *dev, int phy, int reg, int data)
reg 272 dev/pci/if_lge.c (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE);
reg 537 dev/pci/if_lgereg.h #define CSR_WRITE_4(sc, reg, val) \
reg 538 dev/pci/if_lgereg.h bus_space_write_4(sc->lge_btag, sc->lge_bhandle, reg, val)
reg 540 dev/pci/if_lgereg.h #define CSR_READ_2(sc, reg) \
reg 541 dev/pci/if_lgereg.h bus_space_read_2(sc->lge_btag, sc->lge_bhandle, reg)
reg 543 dev/pci/if_lgereg.h #define CSR_WRITE_2(sc, reg, val) \
reg 544 dev/pci/if_lgereg.h bus_space_write_2(sc->lge_btag, sc->lge_bhandle, reg, val)
reg 546 dev/pci/if_lgereg.h #define CSR_READ_4(sc, reg) \
reg 547 dev/pci/if_lgereg.h bus_space_read_4(sc->lge_btag, sc->lge_bhandle, reg)
reg 549 dev/pci/if_lgereg.h #define CSR_WRITE_1(sc, reg, val) \
reg 550 dev/pci/if_lgereg.h bus_space_write_1(sc->lge_btag, sc->lge_bhandle, reg, val)
reg 552 dev/pci/if_lgereg.h #define CSR_READ_1(sc, reg) \
reg 553 dev/pci/if_lgereg.h bus_space_read_1(sc->lge_btag, sc->lge_bhandle, reg)
reg 221 dev/pci/if_msk.c sk_win_read_4(struct sk_softc *sc, u_int32_t reg)
reg 223 dev/pci/if_msk.c return CSR_READ_4(sc, reg);
reg 227 dev/pci/if_msk.c sk_win_read_2(struct sk_softc *sc, u_int32_t reg)
reg 229 dev/pci/if_msk.c return CSR_READ_2(sc, reg);
reg 233 dev/pci/if_msk.c sk_win_read_1(struct sk_softc *sc, u_int32_t reg)
reg 235 dev/pci/if_msk.c return CSR_READ_1(sc, reg);
reg 239 dev/pci/if_msk.c sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x)
reg 241 dev/pci/if_msk.c CSR_WRITE_4(sc, reg, x);
reg 245 dev/pci/if_msk.c sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x)
reg 247 dev/pci/if_msk.c CSR_WRITE_2(sc, reg, x);
reg 251 dev/pci/if_msk.c sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x)
reg 253 dev/pci/if_msk.c CSR_WRITE_1(sc, reg, x);
reg 257 dev/pci/if_msk.c msk_miibus_readreg(struct device *dev, int phy, int reg)
reg 264 dev/pci/if_msk.c YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
reg 285 dev/pci/if_msk.c phy, reg, val));
reg 291 dev/pci/if_msk.c msk_miibus_writereg(struct device *dev, int phy, int reg, int val)
reg 297 dev/pci/if_msk.c phy, reg, val));
reg 301 dev/pci/if_msk.c YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
reg 826 dev/pci/if_msk.c int reg;
reg 889 dev/pci/if_msk.c for (reg = SK_TO0;reg <= SK_TO11; reg++)
reg 890 dev/pci/if_msk.c sk_win_write_1(sc, reg, 36);
reg 892 dev/pci/if_msk.c for (reg = SK_TO0;reg <= SK_TO11; reg++)
reg 893 dev/pci/if_msk.c sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36);
reg 1678 dev/pci/if_msk.c u_int32_t idx, reg, sk_ctl;
reg 1684 dev/pci/if_msk.c reg = SK_STAT_BMU_TXA1_RIDX;
reg 1686 dev/pci/if_msk.c reg = SK_STAT_BMU_TXA2_RIDX;
reg 1693 dev/pci/if_msk.c while (idx != sk_win_read_2(sc, reg)) {
reg 1848 dev/pci/if_msk.c u_int16_t reg;
reg 1869 dev/pci/if_msk.c reg = SK_YU_READ_2(sc_if, YUKON_PAR);
reg 1870 dev/pci/if_msk.c DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg));
reg 1873 dev/pci/if_msk.c reg |= YU_PAR_MIB_CLR;
reg 1874 dev/pci/if_msk.c DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg));
reg 1876 dev/pci/if_msk.c SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
reg 1880 dev/pci/if_msk.c reg &= ~YU_PAR_MIB_CLR;
reg 1881 dev/pci/if_msk.c SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
reg 1894 dev/pci/if_msk.c reg = YU_SMR_DATA_BLIND(0x1c) |
reg 1899 dev/pci/if_msk.c reg |= YU_SMR_MFL_JUMBO;
reg 1901 dev/pci/if_msk.c SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
reg 1913 dev/pci/if_msk.c reg = sk_win_read_2(sc_if->sk_softc,
reg 1915 dev/pci/if_msk.c SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
reg 380 dev/pci/if_nfe.c nfe_miibus_readreg(struct device *dev, int phy, int reg)
reg 393 dev/pci/if_nfe.c NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg);
reg 417 dev/pci/if_nfe.c sc->sc_dev.dv_xname, phy, reg, val));
reg 423 dev/pci/if_nfe.c nfe_miibus_writereg(struct device *dev, int phy, int reg, int val)
reg 437 dev/pci/if_nfe.c ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg;
reg 188 dev/pci/if_nfereg.h #define NFE_READ(sc, reg) \
reg 189 dev/pci/if_nfereg.h bus_space_read_4((sc)->sc_memt, (sc)->sc_memh, (reg))
reg 191 dev/pci/if_nfereg.h #define NFE_WRITE(sc, reg, val) \
reg 192 dev/pci/if_nfereg.h bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, (reg), (val))
reg 200 dev/pci/if_nge.c #define NGE_SETBIT(sc, reg, x) \
reg 201 dev/pci/if_nge.c CSR_WRITE_4(sc, reg, \
reg 202 dev/pci/if_nge.c CSR_READ_4(sc, reg) | (x))
reg 204 dev/pci/if_nge.c #define NGE_CLRBIT(sc, reg, x) \
reg 205 dev/pci/if_nge.c CSR_WRITE_4(sc, reg, \
reg 206 dev/pci/if_nge.c CSR_READ_4(sc, reg) & ~(x))
reg 535 dev/pci/if_nge.c nge_miibus_readreg(dev, phy, reg)
reg 537 dev/pci/if_nge.c int phy, reg;
reg 547 dev/pci/if_nge.c frame.mii_regaddr = reg;
reg 554 dev/pci/if_nge.c nge_miibus_writereg(dev, phy, reg, data)
reg 556 dev/pci/if_nge.c int phy, reg, data;
reg 567 dev/pci/if_nge.c frame.mii_regaddr = reg;
reg 674 dev/pci/if_ngereg.h #define CSR_WRITE_4(sc, reg, val) \
reg 675 dev/pci/if_ngereg.h bus_space_write_4(sc->nge_btag, sc->nge_bhandle, reg, val)
reg 677 dev/pci/if_ngereg.h #define CSR_READ_4(sc, reg) \
reg 678 dev/pci/if_ngereg.h bus_space_read_4(sc->nge_btag, sc->nge_bhandle, reg)
reg 505 dev/pci/if_pcn.c pcn_csr_read(struct pcn_softc *sc, int reg)
reg 508 dev/pci/if_pcn.c bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg);
reg 513 dev/pci/if_pcn.c pcn_csr_write(struct pcn_softc *sc, int reg, uint32_t val)
reg 516 dev/pci/if_pcn.c bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg);
reg 521 dev/pci/if_pcn.c pcn_bcr_read(struct pcn_softc *sc, int reg)
reg 524 dev/pci/if_pcn.c bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg);
reg 529 dev/pci/if_pcn.c pcn_bcr_write(struct pcn_softc *sc, int reg, uint32_t val)
reg 532 dev/pci/if_pcn.c bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg);
reg 588 dev/pci/if_pcn.c uint32_t chipid, reg;
reg 778 dev/pci/if_pcn.c reg = pcn_bcr_read(sc, LE_BCR25) & 0x00ff;
reg 779 dev/pci/if_pcn.c if (reg != 0)
reg 1585 dev/pci/if_pcn.c uint32_t reg;
reg 1728 dev/pci/if_pcn.c reg = pcn_bcr_read(sc, LE_BCR18);
reg 1734 dev/pci/if_pcn.c reg |= LE_B18_BREADE|LE_B18_BWRITE;
reg 1738 dev/pci/if_pcn.c reg |= LE_B18_BREADE|LE_B18_BWRITE|LE_B18_NOUFLO;
reg 1741 dev/pci/if_pcn.c pcn_bcr_write(sc, LE_BCR18, reg);
reg 2024 dev/pci/if_pcn.c uint32_t reg;
reg 2030 dev/pci/if_pcn.c reg = pcn_bcr_read(sc, LE_BCR2);
reg 2031 dev/pci/if_pcn.c reg |= LE_B2_ASEL;
reg 2032 dev/pci/if_pcn.c pcn_bcr_write(sc, LE_BCR2, reg);
reg 2037 dev/pci/if_pcn.c reg = pcn_bcr_read(sc, LE_BCR2);
reg 2038 dev/pci/if_pcn.c reg &= ~LE_B2_ASEL;
reg 2039 dev/pci/if_pcn.c pcn_bcr_write(sc, LE_BCR2, reg);
reg 2041 dev/pci/if_pcn.c reg = pcn_csr_read(sc, LE_CSR15);
reg 2042 dev/pci/if_pcn.c reg = (reg & ~LE_C15_PORTSEL(PORTSEL_MASK)) |
reg 2044 dev/pci/if_pcn.c pcn_csr_write(sc, LE_CSR15, reg);
reg 2048 dev/pci/if_pcn.c reg = LE_B9_FDEN;
reg 2050 dev/pci/if_pcn.c reg |= LE_B9_AUIFD;
reg 2051 dev/pci/if_pcn.c pcn_bcr_write(sc, LE_BCR9, reg);
reg 2135 dev/pci/if_pcn.c pcn_mii_readreg(struct device *self, int phy, int reg)
reg 2140 dev/pci/if_pcn.c pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT));
reg 2154 dev/pci/if_pcn.c pcn_mii_writereg(struct device *self, int phy, int reg, int val)
reg 2158 dev/pci/if_pcn.c pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT));
reg 163 dev/pci/if_rtw_pci.c pcireg_t reg;
reg 191 dev/pci/if_rtw_pci.c reg = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR);
reg 192 dev/pci/if_rtw_pci.c switch (reg & PCI_PMCSR_STATE_MASK) {
reg 196 dev/pci/if_rtw_pci.c reg & PCI_PMCSR_STATE_MASK);
reg 198 dev/pci/if_rtw_pci.c (reg & ~PCI_PMCSR_STATE_MASK) |
reg 209 dev/pci/if_rtw_pci.c (reg & ~PCI_PMCSR_STATE_MASK) |
reg 176 dev/pci/if_san_front_end.h #define READ_REG(reg) card->read_front_end_reg(card, reg)
reg 177 dev/pci/if_san_front_end.h #define WRITE_REG(reg, value) card->write_front_end_reg(card, reg, \
reg 74 dev/pci/if_san_te1.c #define TEST_REG(reg,value) \
reg 76 dev/pci/if_san_te1.c unsigned char test_value = READ_REG(reg); \
reg 81 dev/pci/if_san_te1.c __FILE__,__LINE__,reg, value); \
reg 85 dev/pci/if_san_te1.c #define TEST_RPSC_REG(card,reg,channel,value) \
reg 87 dev/pci/if_san_te1.c unsigned char test_value = ReadRPSCReg(card,channel,reg); \
reg 92 dev/pci/if_san_te1.c __FILE__, __LINE__, reg, channel, value); \
reg 96 dev/pci/if_san_te1.c #define TEST_TPSC_REG(card,reg,channel,value) \
reg 98 dev/pci/if_san_te1.c unsigned char test_value = ReadTPSCReg(card,channel,reg); \
reg 103 dev/pci/if_san_te1.c __FILE__, __LINE__, reg, channel, value); \
reg 109 dev/pci/if_san_te1.c #define TEST_REG(reg,value)
reg 110 dev/pci/if_san_te1.c #define TEST_RPSC_REG(card,reg,channel,value)
reg 111 dev/pci/if_san_te1.c #define TEST_TPSC_REG(card,reg,channel,value)
reg 115 dev/pci/if_san_te1.c #define READ_RPSC_REG(reg,channel) ReadRPSCReg(card,reg,channel)
reg 116 dev/pci/if_san_te1.c #define READ_TPSC_REG(reg,channel) ReadTPSCReg(card,reg,channel)
reg 117 dev/pci/if_san_te1.c #define READ_SIGX_REG(reg,channel) ReadSIGXReg(card,reg,channel)
reg 118 dev/pci/if_san_te1.c #define WRITE_RPSC_REG(reg,channel,value) \
reg 120 dev/pci/if_san_te1.c WriteRPSCReg(card,reg,channel,(unsigned char)value); \
reg 121 dev/pci/if_san_te1.c TEST_RPSC_REG(card,reg,channel,(unsigned char)value); \
reg 124 dev/pci/if_san_te1.c #define WRITE_TPSC_REG(reg,channel,value) \
reg 126 dev/pci/if_san_te1.c WriteTPSCReg(card,reg,channel,(unsigned char)value); \
reg 127 dev/pci/if_san_te1.c TEST_TPSC_REG(card,reg,channe,(unsigned char)value); \
reg 131 dev/pci/if_san_te1.c #define WRITE_SIGX_REG(reg,channel,value) \
reg 133 dev/pci/if_san_te1.c WriteSIGXReg(card,reg,channel,(unsigned char)value); \
reg 134 dev/pci/if_san_te1.c TEST_SIGX_REG(card,reg,channel,(unsigned char)value); \
reg 1551 dev/pci/if_san_te1.c WriteTPSCReg(sdla_t *card, int reg, int channel, unsigned char value)
reg 1557 dev/pci/if_san_te1.c reg += channel;
reg 1571 dev/pci/if_san_te1.c card->devname, reg, value);
reg 1579 dev/pci/if_san_te1.c (unsigned char)(reg & 0x7F));
reg 1589 dev/pci/if_san_te1.c card->devname, reg, value);
reg 1605 dev/pci/if_san_te1.c ReadTPSCReg(sdla_t *card, int reg, int channel)
reg 1610 dev/pci/if_san_te1.c reg += channel;
reg 1624 dev/pci/if_san_te1.c card->devname, reg);
reg 1629 dev/pci/if_san_te1.c (unsigned char)(reg | 0x80));
reg 1639 dev/pci/if_san_te1.c card->devname, reg);
reg 1656 dev/pci/if_san_te1.c WriteRPSCReg(sdla_t* card, int reg, int channel, unsigned char value)
reg 1662 dev/pci/if_san_te1.c reg += channel;
reg 1676 dev/pci/if_san_te1.c card->devname, reg, value);
reg 1683 dev/pci/if_san_te1.c (unsigned char)(reg & 0x7F));
reg 1693 dev/pci/if_san_te1.c card->devname, reg, value);
reg 1707 dev/pci/if_san_te1.c static unsigned char ReadRPSCReg(sdla_t* card, int reg, int channel)
reg 1712 dev/pci/if_san_te1.c reg += channel;
reg 1726 dev/pci/if_san_te1.c card->devname, reg);
reg 1731 dev/pci/if_san_te1.c (unsigned char)(reg | 0x80));
reg 1741 dev/pci/if_san_te1.c card->devname, reg);
reg 3038 dev/pci/if_san_te1.c unsigned char reg;
reg 3044 dev/pci/if_san_te1.c reg=READ_REG(REG_MASTER_DIAG);
reg 3045 dev/pci/if_san_te1.c reg|=BIT_MASTER_DIAG_LINELB;
reg 3046 dev/pci/if_san_te1.c WRITE_REG(REG_MASTER_DIAG,reg);
reg 3051 dev/pci/if_san_te1.c reg=READ_REG(REG_MASTER_DIAG);
reg 3052 dev/pci/if_san_te1.c reg&=~BIT_MASTER_DIAG_LINELB;
reg 3053 dev/pci/if_san_te1.c WRITE_REG(REG_MASTER_DIAG,reg);
reg 958 dev/pci/if_san_xilinx.c u_int32_t reg, tmp;
reg 967 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, ®);
reg 972 dev/pci/if_san_xilinx.c bit_clear((u_int8_t *)®, INTERFACE_TYPE_T1_E1_BIT);
reg 973 dev/pci/if_san_xilinx.c bit_set((u_int8_t *)®, FRONT_END_FRAME_FLAG_ENABLE_BIT);
reg 976 dev/pci/if_san_xilinx.c bit_set((u_int8_t *)®, INTERFACE_TYPE_T1_E1_BIT);
reg 977 dev/pci/if_san_xilinx.c bit_set((u_int8_t *)®, FRONT_END_FRAME_FLAG_ENABLE_BIT);
reg 984 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg);
reg 989 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, ®);
reg 990 dev/pci/if_san_xilinx.c bit_clear((u_int8_t *)®, FRONT_END_RESET_BIT);
reg 991 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg);
reg 994 dev/pci/if_san_xilinx.c bit_set((u_int8_t *)®, FRONT_END_RESET_BIT);
reg 995 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg);
reg 1003 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, ®);
reg 1004 dev/pci/if_san_xilinx.c bit_set((u_int8_t *)®, CHIP_RESET_BIT);
reg 1005 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg);
reg 1010 dev/pci/if_san_xilinx.c bit_clear((u_int8_t *)®, CHIP_RESET_BIT);
reg 1013 dev/pci/if_san_xilinx.c bit_clear((u_int8_t *)®, GLOBAL_INTR_ENABLE_BIT);
reg 1014 dev/pci/if_san_xilinx.c bit_clear((u_int8_t *)®, ERROR_INTR_ENABLE_BIT);
reg 1015 dev/pci/if_san_xilinx.c bit_clear((u_int8_t *)®, FRONT_END_INTR_ENABLE_BIT);
reg 1017 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg);
reg 1055 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, ®);
reg 1056 dev/pci/if_san_xilinx.c bit_set((u_int8_t *)®, XILINX_RED_LED);
reg 1057 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg);
reg 1081 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, ®);
reg 1084 dev/pci/if_san_xilinx.c bit_set((u_int8_t *)®, CHIP_RESET_BIT);
reg 1086 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg);
reg 1092 dev/pci/if_san_xilinx.c card->devname, reg);
reg 1098 dev/pci/if_san_xilinx.c reg = 0;
reg 1099 dev/pci/if_san_xilinx.c reg|=(XILINX_DMA_SIZE << DMA_SIZE_BIT_SHIFT);
reg 1100 dev/pci/if_san_xilinx.c reg|=(XILINX_DMA_FIFO_UP << DMA_FIFO_HI_MARK_BIT_SHIFT);
reg 1101 dev/pci/if_san_xilinx.c reg|=(XILINX_DMA_FIFO_LO << DMA_FIFO_LO_MARK_BIT_SHIFT);
reg 1108 dev/pci/if_san_xilinx.c reg|=(XILINX_DEFLT_ACTIVE_CH << DMA_ACTIVE_CHANNEL_BIT_SHIFT);
reg 1109 dev/pci/if_san_xilinx.c bit_set((u_int8_t *)®, DMA_ENGINE_ENABLE_BIT);
reg 1115 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_DMA_CONTROL_REG, reg);
reg 1123 dev/pci/if_san_xilinx.c reg = 0;
reg 1124 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG, reg);
reg 1131 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, (u_int32_t *)®);
reg 1132 dev/pci/if_san_xilinx.c if (bit_test((u_int8_t *)®, DMA_INTR_FLAG)) {
reg 1136 dev/pci/if_san_xilinx.c reg = 0;
reg 1138 dev/pci/if_san_xilinx.c bit_set((u_int8_t *)®, CHIP_RESET_BIT);
reg 1139 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg);
reg 1142 dev/pci/if_san_xilinx.c if (bit_test((u_int8_t *)®, ERROR_INTR_FLAG)) {
reg 1146 dev/pci/if_san_xilinx.c reg = 0;
reg 1148 dev/pci/if_san_xilinx.c bit_set((u_int8_t *)®, CHIP_RESET_BIT);
reg 1149 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg);
reg 1155 dev/pci/if_san_xilinx.c bit_clear((u_int8_t *)®, GLOBAL_INTR_ENABLE_BIT);
reg 1156 dev/pci/if_san_xilinx.c bit_clear((u_int8_t *)®, ERROR_INTR_ENABLE_BIT);
reg 1159 dev/pci/if_san_xilinx.c bit_set((u_int8_t *)®, FRONT_END_INTR_ENABLE_BIT);
reg 1162 dev/pci/if_san_xilinx.c log(LOG_DEBUG, "--- Set Global Interrupts (0x%X)-- \n", reg);
reg 1167 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg);
reg 1175 dev/pci/if_san_xilinx.c u_int32_t reg = 0;
reg 1177 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG, reg);
reg 1178 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, ®);
reg 1180 dev/pci/if_san_xilinx.c reg = 0;
reg 1181 dev/pci/if_san_xilinx.c bit_set((u_int8_t *)®, CHIP_RESET_BIT);
reg 1183 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg);
reg 1190 dev/pci/if_san_xilinx.c u_int32_t reg;
reg 1275 dev/pci/if_san_xilinx.c XILINX_TIMESLOT_HDLC_CHAN_REG, ®);
reg 1276 dev/pci/if_san_xilinx.c reg &= ~TIMESLOT_BIT_MASK;
reg 1279 dev/pci/if_san_xilinx.c reg &= HDLC_LCH_TIMESLOT_MASK; /* mask not valid bits*/
reg 1284 dev/pci/if_san_xilinx.c (reg | (i << TIMESLOT_BIT_SHIFT)));
reg 1286 dev/pci/if_san_xilinx.c reg = sc->logic_ch_num & CONTROL_RAM_DATA_MASK;
reg 1289 dev/pci/if_san_xilinx.c reg |= (sc->fifo_size_code & HDLC_FIFO_SIZE_MASK) <<
reg 1292 dev/pci/if_san_xilinx.c reg |= (HARD_FIFO_CODE &
reg 1296 dev/pci/if_san_xilinx.c reg |= (sc->fifo_base_addr & HDLC_FIFO_BASE_ADDR_MASK)
reg 1301 dev/pci/if_san_xilinx.c "ch %ld Reg=0x%X\n", i, sc->logic_ch_num, reg);
reg 1304 dev/pci/if_san_xilinx.c XILINX_CONTROL_RAM_ACCESS_BUF, reg);
reg 1317 dev/pci/if_san_xilinx.c XILINX_TIMESLOT_HDLC_CHAN_REG, ®);
reg 1319 dev/pci/if_san_xilinx.c reg &= ~TIMESLOT_BIT_MASK;
reg 1321 dev/pci/if_san_xilinx.c reg &= HDLC_LCH_TIMESLOT_MASK;
reg 1326 dev/pci/if_san_xilinx.c (reg | (i << TIMESLOT_BIT_SHIFT)));
reg 1328 dev/pci/if_san_xilinx.c reg = free_logic_ch&CONTROL_RAM_DATA_MASK;
reg 1333 dev/pci/if_san_xilinx.c reg |= (FIFO_32B & HDLC_FIFO_SIZE_MASK)
reg 1336 dev/pci/if_san_xilinx.c reg |= (free_logic_ch &
reg 1343 dev/pci/if_san_xilinx.c i, free_logic_ch, reg);
reg 1346 dev/pci/if_san_xilinx.c XILINX_CONTROL_RAM_ACCESS_BUF, reg);
reg 1364 dev/pci/if_san_xilinx.c XILINX_TIMESLOT_HDLC_CHAN_REG, ®);
reg 1366 dev/pci/if_san_xilinx.c reg &= ~HDLC_LOGIC_CH_BIT_MASK;
reg 1369 dev/pci/if_san_xilinx.c reg &= HDLC_LCH_TIMESLOT_MASK;
reg 1373 dev/pci/if_san_xilinx.c (reg|(free_logic_ch&HDLC_LOGIC_CH_BIT_MASK)));
reg 1375 dev/pci/if_san_xilinx.c reg = 0;
reg 1376 dev/pci/if_san_xilinx.c bit_clear((u_int8_t *)®, HDLC_RX_PROT_DISABLE_BIT);
reg 1377 dev/pci/if_san_xilinx.c bit_clear((u_int8_t *)®, HDLC_TX_PROT_DISABLE_BIT);
reg 1379 dev/pci/if_san_xilinx.c bit_set((u_int8_t *)®, HDLC_RX_ADDR_RECOGN_DIS_BIT);
reg 1382 dev/pci/if_san_xilinx.c XILINX_HDLC_CONTROL_REG, reg);
reg 1387 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG, ®);
reg 1389 dev/pci/if_san_xilinx.c reg &= ~HDLC_LOGIC_CH_BIT_MASK;
reg 1390 dev/pci/if_san_xilinx.c reg &= HDLC_LCH_TIMESLOT_MASK; /* mask not valid bits */
reg 1393 dev/pci/if_san_xilinx.c (reg | (sc->logic_ch_num & HDLC_LOGIC_CH_BIT_MASK)));
reg 1395 dev/pci/if_san_xilinx.c reg = 0;
reg 1398 dev/pci/if_san_xilinx.c bit_clear((u_int8_t *)®, HDLC_RX_PROT_DISABLE_BIT);
reg 1399 dev/pci/if_san_xilinx.c bit_clear((u_int8_t *)®, HDLC_TX_PROT_DISABLE_BIT);
reg 1401 dev/pci/if_san_xilinx.c bit_set((u_int8_t *)®, HDLC_TX_CHAN_ENABLE_BIT);
reg 1402 dev/pci/if_san_xilinx.c bit_set((u_int8_t *)®, HDLC_RX_ADDR_RECOGN_DIS_BIT);
reg 1405 dev/pci/if_san_xilinx.c XILINX_HDLC_CONTROL_REG, reg);
reg 1413 dev/pci/if_san_xilinx.c u_int32_t reg;
reg 1423 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG, ®);
reg 1424 dev/pci/if_san_xilinx.c reg &= ~HDLC_LOGIC_CH_BIT_MASK;
reg 1425 dev/pci/if_san_xilinx.c reg &= HDLC_LCH_TIMESLOT_MASK; /* mask not valid bits */
reg 1428 dev/pci/if_san_xilinx.c (reg | (sc->logic_ch_num & HDLC_LOGIC_CH_BIT_MASK)));
reg 1430 dev/pci/if_san_xilinx.c reg = 0x00020000;
reg 1432 dev/pci/if_san_xilinx.c XILINX_HDLC_CONTROL_REG, reg);
reg 1437 dev/pci/if_san_xilinx.c XILINX_TIMESLOT_HDLC_CHAN_REG, ®);
reg 1438 dev/pci/if_san_xilinx.c reg &= ~TIMESLOT_BIT_MASK;
reg 1441 dev/pci/if_san_xilinx.c reg &= HDLC_LCH_TIMESLOT_MASK;
reg 1446 dev/pci/if_san_xilinx.c (reg | (i<<TIMESLOT_BIT_SHIFT)));
reg 1448 dev/pci/if_san_xilinx.c reg = 31 & CONTROL_RAM_DATA_MASK;
reg 1449 dev/pci/if_san_xilinx.c reg |= (FIFO_32B & HDLC_FIFO_SIZE_MASK) <<
reg 1451 dev/pci/if_san_xilinx.c reg |= (31 & HDLC_FIFO_BASE_ADDR_MASK) <<
reg 1456 dev/pci/if_san_xilinx.c "to logic ch %d Reg=0x%X\n", i, 31 , reg);
reg 1459 dev/pci/if_san_xilinx.c XILINX_CONTROL_RAM_ACCESS_BUF, reg);
reg 1489 dev/pci/if_san_xilinx.c u_int32_t reg;
reg 1497 dev/pci/if_san_xilinx.c reg = 0;
reg 1498 dev/pci/if_san_xilinx.c bit_set((u_int8_t *)®, INIT_DMA_FIFO_CMD_BIT);
reg 1503 dev/pci/if_san_xilinx.c sc->if_name, dma_descr, reg, __FUNCTION__);
reg 1506 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, dma_descr, reg);
reg 1510 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, dma_descr, ®);
reg 1511 dev/pci/if_san_xilinx.c if (bit_test((u_int8_t *)®, INIT_DMA_FIFO_CMD_BIT)) {
reg 1538 dev/pci/if_san_xilinx.c u_int32_t reg;
reg 1546 dev/pci/if_san_xilinx.c reg = 0;
reg 1547 dev/pci/if_san_xilinx.c bit_set((u_int8_t *)®, INIT_DMA_FIFO_CMD_BIT);
reg 1552 dev/pci/if_san_xilinx.c sc->if_name, dma_descr, reg, __FUNCTION__);
reg 1554 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, dma_descr, reg);
reg 1558 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, dma_descr, ®);
reg 1559 dev/pci/if_san_xilinx.c if (bit_test((u_int8_t *)®, INIT_DMA_FIFO_CMD_BIT)) {
reg 1587 dev/pci/if_san_xilinx.c u_int32_t reg;
reg 1593 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_GLOBAL_INTER_MASK, ®);
reg 1594 dev/pci/if_san_xilinx.c bit_set((u_int8_t *)®, sc->logic_ch_num);
reg 1596 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_GLOBAL_INTER_MASK, reg);
reg 1604 dev/pci/if_san_xilinx.c u_int32_t reg;
reg 1612 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_GLOBAL_INTER_MASK, ®);
reg 1614 dev/pci/if_san_xilinx.c bit_clear((u_int8_t *)®, sc->logic_ch_num);
reg 1623 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_GLOBAL_INTER_MASK, reg);
reg 1626 dev/pci/if_san_xilinx.c reg = 0;
reg 1629 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG, ®);
reg 1631 dev/pci/if_san_xilinx.c reg &= ~HDLC_LOGIC_CH_BIT_MASK;
reg 1632 dev/pci/if_san_xilinx.c reg &= HDLC_LCH_TIMESLOT_MASK; /* mask not valid bits */
reg 1635 dev/pci/if_san_xilinx.c (reg | (sc->logic_ch_num & HDLC_LOGIC_CH_BIT_MASK)));
reg 1638 dev/pci/if_san_xilinx.c reg = 0;
reg 1640 dev/pci/if_san_xilinx.c XILINX_HDLC_CONTROL_REG, reg);
reg 1643 dev/pci/if_san_xilinx.c reg = 0;
reg 1645 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, dma_descr, reg);
reg 1647 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, dma_descr, reg);
reg 1655 dev/pci/if_san_xilinx.c u_int32_t reg;
reg 1663 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, dma_descr, ®);
reg 1665 dev/pci/if_san_xilinx.c if (bit_test((u_int8_t *)®, RxDMA_HI_DMA_GO_READY_BIT)) {
reg 1702 dev/pci/if_san_xilinx.c reg = bus_addr;
reg 1707 dev/pci/if_san_xilinx.c reg &= ~(RxDMA_LO_ALIGNMENT_BIT_MASK);
reg 1713 dev/pci/if_san_xilinx.c "DmaDescr=0x%lX (%s)\n", card->devname, reg, bus_addr,
reg 1716 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, dma_descr, reg);
reg 1721 dev/pci/if_san_xilinx.c reg = 0;
reg 1723 dev/pci/if_san_xilinx.c reg |= (sc->dma_mtu >> 2) & RxDMA_HI_DMA_DATA_LENGTH_MASK;
reg 1726 dev/pci/if_san_xilinx.c reg |= (sc->fifo_size_code & DMA_FIFO_SIZE_MASK) <<
reg 1730 dev/pci/if_san_xilinx.c reg |= (HARD_FIFO_CODE & DMA_FIFO_SIZE_MASK) << DMA_FIFO_SIZE_SHIFT;
reg 1732 dev/pci/if_san_xilinx.c reg |= (sc->fifo_base_addr&DMA_FIFO_BASE_ADDR_MASK) <<
reg 1735 dev/pci/if_san_xilinx.c bit_set((u_int8_t *)®, RxDMA_HI_DMA_GO_READY_BIT);
reg 1739 dev/pci/if_san_xilinx.c "(%s)\n", sc->if_name, reg, bus_addr, dma_descr, __FUNCTION__);
reg 1742 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, dma_descr, reg);
reg 1753 dev/pci/if_san_xilinx.c u_int32_t reg = 0;
reg 1804 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, dma_descr, ®);
reg 1806 dev/pci/if_san_xilinx.c if (bit_test((u_int8_t *)®, TxDMA_HI_DMA_GO_READY_BIT)) {
reg 1808 dev/pci/if_san_xilinx.c "on dma Tx 0x%X\n", card->devname, reg);
reg 1871 dev/pci/if_san_xilinx.c reg = sc->tx_dma_addr;
reg 1879 dev/pci/if_san_xilinx.c reg &= ~(TxDMA_LO_ALIGNMENT_BIT_MASK);
reg 1880 dev/pci/if_san_xilinx.c reg |= (len & 0x03);
reg 1887 dev/pci/if_san_xilinx.c sc->if_name, reg, sc->tx_dma_addr, dma_descr, __FUNCTION__);
reg 1890 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, dma_descr, reg);
reg 1894 dev/pci/if_san_xilinx.c reg = 0;
reg 1895 dev/pci/if_san_xilinx.c reg |= (((len >> 2) + len_align) & TxDMA_HI_DMA_DATA_LENGTH_MASK);
reg 1898 dev/pci/if_san_xilinx.c reg |= (sc->fifo_size_code & DMA_FIFO_SIZE_MASK) <<
reg 1902 dev/pci/if_san_xilinx.c reg |= (HARD_FIFO_CODE & DMA_FIFO_SIZE_MASK) << DMA_FIFO_SIZE_SHIFT;
reg 1904 dev/pci/if_san_xilinx.c reg |= (sc->fifo_base_addr & DMA_FIFO_BASE_ADDR_MASK) <<
reg 1911 dev/pci/if_san_xilinx.c bit_set((u_int8_t *)®, TxDMA_HI_DMA_FRAME_START_BIT);
reg 1912 dev/pci/if_san_xilinx.c bit_set((u_int8_t *)®, TxDMA_HI_DMA_FRAME_END_BIT);
reg 1914 dev/pci/if_san_xilinx.c bit_set((u_int8_t *)®, TxDMA_HI_DMA_GO_READY_BIT);
reg 1918 dev/pci/if_san_xilinx.c sc->if_name, reg, dma_descr, __FUNCTION__);
reg 1921 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, dma_descr, reg);
reg 1930 dev/pci/if_san_xilinx.c u_int32_t reg = 0;
reg 1940 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, dma_descr, ®);
reg 1962 dev/pci/if_san_xilinx.c if (reg & TxDMA_HI_DMA_PCI_ERROR_RETRY_TOUT) {
reg 1965 dev/pci/if_san_xilinx.c card->devname, sc->if_name, reg);
reg 1968 dev/pci/if_san_xilinx.c bit_set((u_int8_t *)®,
reg 1973 dev/pci/if_san_xilinx.c sc->if_name, reg, dma_descr, __FUNCTION__);
reg 1975 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, dma_descr, reg);
reg 1981 dev/pci/if_san_xilinx.c sc->tx_dma_mbuf->m_pkthdr.csum_flags = reg;
reg 1994 dev/pci/if_san_xilinx.c unsigned long reg = m->m_pkthdr.csum_flags;
reg 1998 dev/pci/if_san_xilinx.c if ((bit_test((u_int8_t *)®, TxDMA_HI_DMA_GO_READY_BIT)) ||
reg 1999 dev/pci/if_san_xilinx.c (reg & TxDMA_HI_DMA_DATA_LENGTH_MASK) ||
reg 2000 dev/pci/if_san_xilinx.c (reg & TxDMA_HI_DMA_PCI_ERROR_MASK)) {
reg 2004 dev/pci/if_san_xilinx.c card->devname, sc->if_name, reg);
reg 2008 dev/pci/if_san_xilinx.c if (bit_test((u_int8_t *)®, TxDMA_HI_DMA_GO_READY_BIT))
reg 2013 dev/pci/if_san_xilinx.c if (reg & TxDMA_HI_DMA_DATA_LENGTH_MASK)
reg 2018 dev/pci/if_san_xilinx.c if (reg & TxDMA_HI_DMA_PCI_ERROR_MASK) {
reg 2020 dev/pci/if_san_xilinx.c if (reg & TxDMA_HI_DMA_PCI_ERROR_M_ABRT)
reg 2025 dev/pci/if_san_xilinx.c if (reg & TxDMA_HI_DMA_PCI_ERROR_T_ABRT)
reg 2030 dev/pci/if_san_xilinx.c if (reg & TxDMA_HI_DMA_PCI_ERROR_DS_TOUT) {
reg 2036 dev/pci/if_san_xilinx.c if (reg & TxDMA_HI_DMA_PCI_ERROR_RETRY_TOUT)
reg 2089 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, dma_descr, &rx_el->reg);
reg 2096 dev/pci/if_san_xilinx.c sc->if_name, rx_el->reg, rx_el->align, rx_el->dma_addr,
reg 2127 dev/pci/if_san_xilinx.c sc->if_name, rx_el->reg, rx_el->align, rx_el->dma_addr,
reg 2136 dev/pci/if_san_xilinx.c if (bit_test((u_int8_t *)&rx_el->reg, RxDMA_HI_DMA_GO_READY_BIT)) {
reg 2144 dev/pci/if_san_xilinx.c if (rx_el->reg & RxDMA_HI_DMA_PCI_ERROR_MASK) {
reg 2146 dev/pci/if_san_xilinx.c if (rx_el->reg & RxDMA_HI_DMA_PCI_ERROR_M_ABRT)
reg 2150 dev/pci/if_san_xilinx.c if (rx_el->reg & RxDMA_HI_DMA_PCI_ERROR_T_ABRT)
reg 2154 dev/pci/if_san_xilinx.c if (rx_el->reg & RxDMA_HI_DMA_PCI_ERROR_DS_TOUT)
reg 2158 dev/pci/if_san_xilinx.c if (rx_el->reg & RxDMA_HI_DMA_PCI_ERROR_RETRY_TOUT)
reg 2163 dev/pci/if_san_xilinx.c card->devname, rx_el->reg);
reg 2172 dev/pci/if_san_xilinx.c if (!bit_test((u_int8_t *)&rx_el->reg, RxDMA_HI_DMA_FRAME_START_BIT)) {
reg 2175 dev/pci/if_san_xilinx.c "MTU Mismatch! Reg=0x%X\n", card->devname, rx_el->reg);
reg 2183 dev/pci/if_san_xilinx.c if (!bit_test((u_int8_t *)&rx_el->reg, RxDMA_HI_DMA_FRAME_END_BIT)) {
reg 2186 dev/pci/if_san_xilinx.c "MTU Mismatch! Reg=0x%X\n", card->devname, rx_el->reg);
reg 2194 dev/pci/if_san_xilinx.c if (bit_test((u_int8_t *)&rx_el->reg,
reg 2198 dev/pci/if_san_xilinx.c card->devname, rx_el->reg);
reg 2210 dev/pci/if_san_xilinx.c if (bit_test((u_int8_t *)&rx_el->reg,
reg 2214 dev/pci/if_san_xilinx.c card->devname, rx_el->reg);
reg 2228 dev/pci/if_san_xilinx.c len = rx_el->reg & RxDMA_HI_DMA_DATA_LENGTH_MASK;
reg 2368 dev/pci/if_san_xilinx.c u_int32_t reg;
reg 2374 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_DMA_CONTROL_REG, ®);
reg 2378 dev/pci/if_san_xilinx.c reg &= DMA_ACTIVE_CHANNEL_BIT_MASK;
reg 2379 dev/pci/if_san_xilinx.c reg |= (card->u.xilinx.top_logic_ch << DMA_ACTIVE_CHANNEL_BIT_SHIFT);
reg 2381 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_DMA_CONTROL_REG, reg);
reg 2560 dev/pci/if_san_xilinx.c fifo_error_interrupt(sdla_t *card, unsigned long reg)
reg 2672 dev/pci/if_san_xilinx.c unsigned int reg;
reg 2675 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, dma_descr, ®);
reg 2677 dev/pci/if_san_xilinx.c sc->if_name, reg);
reg 2693 dev/pci/if_san_xilinx.c front_end_interrupt(sdla_t *card, unsigned long reg)
reg 2713 dev/pci/if_san_xilinx.c u_int32_t reg;
reg 2732 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, ®);
reg 2734 dev/pci/if_san_xilinx.c if (bit_test((u_int8_t *)®, SECURITY_STATUS_FLAG)) {
reg 2749 dev/pci/if_san_xilinx.c if (bit_test((u_int8_t *)®, FRONT_END_INTR_ENABLE_BIT)) {
reg 2750 dev/pci/if_san_xilinx.c if (bit_test((u_int8_t *)®, FRONT_END_INTR_FLAG)) {
reg 2751 dev/pci/if_san_xilinx.c front_end_interrupt(card, reg);
reg 2767 dev/pci/if_san_xilinx.c if (bit_test((u_int8_t *)®, ERROR_INTR_ENABLE_BIT))
reg 2768 dev/pci/if_san_xilinx.c if (bit_test((u_int8_t *)®, ERROR_INTR_FLAG))
reg 2769 dev/pci/if_san_xilinx.c fifo_error_interrupt(card, reg);
reg 2777 dev/pci/if_san_xilinx.c if (bit_test((u_int8_t *)®, GLOBAL_INTR_ENABLE_BIT) &&
reg 2778 dev/pci/if_san_xilinx.c bit_test((u_int8_t *)®, DMA_INTR_FLAG)) {
reg 3029 dev/pci/if_san_xilinx.c u_int32_t reg;
reg 3032 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_DMA_RX_INTR_PENDING_REG, ®);
reg 3033 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_DMA_TX_INTR_PENDING_REG, ®);
reg 3060 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_DMA_CONTROL_REG, ®);
reg 3061 dev/pci/if_san_xilinx.c bit_set((u_int8_t *)®, DMA_ENGINE_ENABLE_BIT);
reg 3062 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_DMA_CONTROL_REG, reg);
reg 3146 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_HDLC_RX_INTR_PENDING_REG, ®);
reg 3147 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_HDLC_TX_INTR_PENDING_REG, ®);
reg 3150 dev/pci/if_san_xilinx.c reg = 0;
reg 3151 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, ®);
reg 3152 dev/pci/if_san_xilinx.c bit_set((u_int8_t *)®, GLOBAL_INTR_ENABLE_BIT);
reg 3153 dev/pci/if_san_xilinx.c bit_set((u_int8_t *)®, ERROR_INTR_ENABLE_BIT);
reg 3154 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg);
reg 3162 dev/pci/if_san_xilinx.c u_int32_t reg;
reg 3164 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, ®);
reg 3165 dev/pci/if_san_xilinx.c bit_clear((u_int8_t *)®, GLOBAL_INTR_ENABLE_BIT);
reg 3166 dev/pci/if_san_xilinx.c bit_clear((u_int8_t *)®, ERROR_INTR_ENABLE_BIT);
reg 3168 dev/pci/if_san_xilinx.c bit_clear((u_int8_t *)®, FRONT_END_INTR_ENABLE_BIT);
reg 3170 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg);
reg 3172 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_DMA_CONTROL_REG, ®);
reg 3173 dev/pci/if_san_xilinx.c bit_clear((u_int8_t *)®, DMA_ENGINE_ENABLE_BIT);
reg 3174 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_DMA_CONTROL_REG, reg);
reg 3182 dev/pci/if_san_xilinx.c unsigned long reg = 0;
reg 3185 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, dma_descr, reg);
reg 3194 dev/pci/if_san_xilinx.c u_int32_t reg = 0;
reg 3204 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, dma_descr, reg);
reg 3248 dev/pci/if_san_xilinx.c u_int32_t reg;
reg 3263 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG, ®);
reg 3264 dev/pci/if_san_xilinx.c reg &= XILINX_CURRENT_TIMESLOT_MASK;
reg 3266 dev/pci/if_san_xilinx.c if (reg == timeslot) {
reg 3410 dev/pci/if_san_xilinx.c u_int32_t reg = 0;
reg 3414 dev/pci/if_san_xilinx.c bit_set((u_int8_t *)®, i);
reg 3418 dev/pci/if_san_xilinx.c card->devname, reg, card->u.xilinx.fifo_addr_map);
reg 3421 dev/pci/if_san_xilinx.c if (card->u.xilinx.fifo_addr_map & (reg << i))
reg 3423 dev/pci/if_san_xilinx.c card->u.xilinx.fifo_addr_map |= reg << i;
reg 3445 dev/pci/if_san_xilinx.c u_int32_t reg = 0;
reg 3449 dev/pci/if_san_xilinx.c bit_set((u_int8_t *)®, i);
reg 3453 dev/pci/if_san_xilinx.c reg << sc->fifo_base_addr, card->u.xilinx.fifo_addr_map);
reg 3455 dev/pci/if_san_xilinx.c card->u.xilinx.fifo_addr_map &= ~(reg << sc->fifo_base_addr);
reg 3547 dev/pci/if_san_xilinx.c u_int32_t reg;
reg 3551 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, ®);
reg 3552 dev/pci/if_san_xilinx.c if (!bit_test((u_int8_t *)®, HDLC_CORE_READY_FLAG_BIT)) {
reg 369 dev/pci/if_san_xilinx.h unsigned int reg;
reg 1424 dev/pci/if_sandrv.c sdla_pci_read_config_dword(void *phw, int reg, u_int32_t *value)
reg 1433 dev/pci/if_sandrv.c *value = pci_conf_read(hwcard->pa.pa_pc, hwcard->pa.pa_tag, reg);
reg 1438 dev/pci/if_sandrv.c sdla_pci_read_config_word(void *phw, int reg, u_int16_t *value)
reg 1448 dev/pci/if_sandrv.c tmp = pci_conf_read(hwcard->pa.pa_pc, hwcard->pa.pa_tag, reg);
reg 1454 dev/pci/if_sandrv.c sdla_pci_read_config_byte(void *phw, int reg, u_int8_t *value)
reg 1464 dev/pci/if_sandrv.c tmp = pci_conf_read(hwcard->pa.pa_pc, hwcard->pa.pa_tag, reg);
reg 1470 dev/pci/if_sandrv.c sdla_pci_write_config_dword(void *phw, int reg, u_int32_t value)
reg 1479 dev/pci/if_sandrv.c pci_conf_write(card->pa.pa_pc, card->pa.pa_tag, reg, value);
reg 1484 dev/pci/if_sandrv.c sdla_pci_write_config_word(void *phw, int reg, u_int16_t value)
reg 1493 dev/pci/if_sandrv.c pci_conf_write(card->pa.pa_pc, card->pa.pa_tag, reg, value);
reg 115 dev/pci/if_sf_pci.c pcireg_t reg;
reg 120 dev/pci/if_sf_pci.c reg = pci_conf_read(pa->pa_pc, pa->pa_tag, pmreg + PCI_PMCSR);
reg 121 dev/pci/if_sf_pci.c switch (reg & PCI_PMCSR_STATE_MASK) {
reg 125 dev/pci/if_sf_pci.c reg & PCI_PMCSR_STATE_MASK, sc->sc_dev.dv_xname);
reg 127 dev/pci/if_sf_pci.c (reg & ~PCI_PMCSR_STATE_MASK) |
reg 135 dev/pci/if_sf_pci.c (reg & ~PCI_PMCSR_STATE_MASK) |
reg 144 dev/pci/if_sf_pci.c reg = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SF_PCI_MEMBA);
reg 145 dev/pci/if_sf_pci.c switch (reg) {
reg 149 dev/pci/if_sf_pci.c reg, 0, &memt, &memh, NULL, NULL, 0) == 0);
reg 156 dev/pci/if_sf_pci.c (reg == (PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT)) ?
reg 160 dev/pci/if_sis.c #define SIS_SETBIT(sc, reg, x) \
reg 161 dev/pci/if_sis.c CSR_WRITE_4(sc, reg, \
reg 162 dev/pci/if_sis.c CSR_READ_4(sc, reg) | (x))
reg 164 dev/pci/if_sis.c #define SIS_CLRBIT(sc, reg, x) \
reg 165 dev/pci/if_sis.c CSR_WRITE_4(sc, reg, \
reg 166 dev/pci/if_sis.c CSR_READ_4(sc, reg) & ~(x))
reg 323 dev/pci/if_sis.c u_int32_t reg;
reg 326 dev/pci/if_sis.c reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x48);
reg 327 dev/pci/if_sis.c pci_conf_write(pa->pa_pc, pa->pa_tag, 0x48, reg | 0x40);
reg 340 dev/pci/if_sis.c pci_conf_write(pa->pa_pc, pa->pa_tag, 0x48, reg & ~0x40);
reg 560 dev/pci/if_sis.c sis_miibus_readreg(struct device *self, int phy, int reg)
reg 580 dev/pci/if_sis.c return CSR_READ_4(sc, NS_BMCR + (reg * 4));
reg 596 dev/pci/if_sis.c (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
reg 620 dev/pci/if_sis.c frame.mii_regaddr = reg;
reg 628 dev/pci/if_sis.c sis_miibus_writereg(struct device *self, int phy, int reg, int data)
reg 636 dev/pci/if_sis.c CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
reg 653 dev/pci/if_sis.c (reg << 6) | SIS_PHYOP_WRITE);
reg 668 dev/pci/if_sis.c frame.mii_regaddr = reg;
reg 1804 dev/pci/if_sis.c uint32_t reg;
reg 1810 dev/pci/if_sis.c reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff;
reg 1811 dev/pci/if_sis.c CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000);
reg 1813 dev/pci/if_sis.c reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff;
reg 1814 dev/pci/if_sis.c if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) {
reg 1817 dev/pci/if_sis.c sc->sc_dev.dv_xname, reg);
reg 1820 dev/pci/if_sis.c reg = CSR_READ_4(sc, NS_PHY_DSPCFG);
reg 1821 dev/pci/if_sis.c SIS_SETBIT(sc, NS_PHY_DSPCFG, reg | 0x20);
reg 470 dev/pci/if_sisreg.h #define CSR_WRITE_4(sc, reg, val) \
reg 471 dev/pci/if_sisreg.h bus_space_write_4(sc->sis_btag, sc->sis_bhandle, reg, val)
reg 473 dev/pci/if_sisreg.h #define CSR_READ_4(sc, reg) \
reg 474 dev/pci/if_sisreg.h bus_space_read_4(sc->sis_btag, sc->sis_bhandle, reg)
reg 212 dev/pci/if_sk.c sk_win_read_4(struct sk_softc *sc, u_int32_t reg)
reg 214 dev/pci/if_sk.c return CSR_READ_4(sc, reg);
reg 218 dev/pci/if_sk.c sk_win_read_2(struct sk_softc *sc, u_int32_t reg)
reg 220 dev/pci/if_sk.c return CSR_READ_2(sc, reg);
reg 224 dev/pci/if_sk.c sk_win_read_1(struct sk_softc *sc, u_int32_t reg)
reg 226 dev/pci/if_sk.c return CSR_READ_1(sc, reg);
reg 230 dev/pci/if_sk.c sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x)
reg 232 dev/pci/if_sk.c CSR_WRITE_4(sc, reg, x);
reg 236 dev/pci/if_sk.c sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x)
reg 238 dev/pci/if_sk.c CSR_WRITE_2(sc, reg, x);
reg 242 dev/pci/if_sk.c sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x)
reg 244 dev/pci/if_sk.c CSR_WRITE_1(sc, reg, x);
reg 248 dev/pci/if_sk.c sk_xmac_miibus_readreg(struct device *dev, int phy, int reg)
reg 258 dev/pci/if_sk.c SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
reg 279 dev/pci/if_sk.c sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val)
reg 286 dev/pci/if_sk.c SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
reg 330 dev/pci/if_sk.c sk_marv_miibus_readreg(struct device *dev, int phy, int reg)
reg 340 dev/pci/if_sk.c phy, reg));
reg 345 dev/pci/if_sk.c YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
reg 366 dev/pci/if_sk.c phy, reg, val));
reg 372 dev/pci/if_sk.c sk_marv_miibus_writereg(struct device *dev, int phy, int reg, int val)
reg 378 dev/pci/if_sk.c phy, reg, val));
reg 382 dev/pci/if_sk.c YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
reg 2257 dev/pci/if_sk.c while(bhack[i].reg) {
reg 2259 dev/pci/if_sk.c SK_PHYADDR_BCOM, bhack[i].reg,
reg 2361 dev/pci/if_sk.c u_int16_t reg;
reg 2428 dev/pci/if_sk.c reg = SK_YU_READ_2(sc_if, YUKON_PAR);
reg 2429 dev/pci/if_sk.c DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg));
reg 2432 dev/pci/if_sk.c reg |= YU_PAR_MIB_CLR;
reg 2433 dev/pci/if_sk.c DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg));
reg 2435 dev/pci/if_sk.c SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
reg 2439 dev/pci/if_sk.c reg &= ~YU_PAR_MIB_CLR;
reg 2440 dev/pci/if_sk.c SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
reg 2467 dev/pci/if_sk.c reg = sk_win_read_2(sc_if->sk_softc,
reg 2469 dev/pci/if_sk.c SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
reg 2661 dev/pci/if_sk.c u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
reg 2662 dev/pci/if_sk.c reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
reg 2663 dev/pci/if_sk.c SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
reg 76 dev/pci/if_skreg.h #define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN)
reg 79 dev/pci/if_skreg.h #define SK_REG(reg) ((reg) & SK_REG_MASK)
reg 106 dev/pci/if_skreg.h #define SK_IF_READ_4(sc_if, skip, reg) \
reg 107 dev/pci/if_skreg.h sk_win_read_4(sc_if->sk_softc, reg + \
reg 109 dev/pci/if_skreg.h #define SK_IF_READ_2(sc_if, skip, reg) \
reg 110 dev/pci/if_skreg.h sk_win_read_2(sc_if->sk_softc, reg + \
reg 112 dev/pci/if_skreg.h #define SK_IF_READ_1(sc_if, skip, reg) \
reg 113 dev/pci/if_skreg.h sk_win_read_1(sc_if->sk_softc, reg + \
reg 116 dev/pci/if_skreg.h #define SK_IF_WRITE_4(sc_if, skip, reg, val) \
reg 118 dev/pci/if_skreg.h reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
reg 119 dev/pci/if_skreg.h #define SK_IF_WRITE_2(sc_if, skip, reg, val) \
reg 121 dev/pci/if_skreg.h reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
reg 122 dev/pci/if_skreg.h #define SK_IF_WRITE_1(sc_if, skip, reg, val) \
reg 124 dev/pci/if_skreg.h reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
reg 608 dev/pci/if_skreg.h #define SK_PCI_REG(reg) ((reg) + SK_PCI_BASE)
reg 1339 dev/pci/if_skreg.h #define SK_Y2_PCI_REG(reg) ((reg) + SK_Y2_PCI_BASE)
reg 1356 dev/pci/if_skreg.h #define SK_XMAC_REG(sc, reg) (((reg) * 2) + SK_XMAC1_BASE + \
reg 1360 dev/pci/if_skreg.h #define SK_XM_READ_4(sc, reg) \
reg 1362 dev/pci/if_skreg.h SK_XMAC_REG(sc, reg)) & 0xFFFF) | \
reg 1364 dev/pci/if_skreg.h SK_XMAC_REG(sc, reg + 2)) & 0xFFFF) << 16))
reg 1366 dev/pci/if_skreg.h #define SK_XM_WRITE_4(sc, reg, val) \
reg 1367 dev/pci/if_skreg.h sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), \
reg 1369 dev/pci/if_skreg.h sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg + 2), \
reg 1372 dev/pci/if_skreg.h #define SK_XM_READ_4(sc, reg) \
reg 1373 dev/pci/if_skreg.h sk_win_read_4(sc->sk_softc, SK_XMAC_REG(sc, reg))
reg 1375 dev/pci/if_skreg.h #define SK_XM_WRITE_4(sc, reg, val) \
reg 1376 dev/pci/if_skreg.h sk_win_write_4(sc->sk_softc, SK_XMAC_REG(sc, reg), (val))
reg 1379 dev/pci/if_skreg.h #define SK_XM_READ_2(sc, reg) \
reg 1380 dev/pci/if_skreg.h sk_win_read_2(sc->sk_softc, SK_XMAC_REG(sc, reg))
reg 1382 dev/pci/if_skreg.h #define SK_XM_WRITE_2(sc, reg, val) \
reg 1383 dev/pci/if_skreg.h sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), val)
reg 1385 dev/pci/if_skreg.h #define SK_XM_SETBIT_4(sc, reg, x) \
reg 1386 dev/pci/if_skreg.h SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x))
reg 1388 dev/pci/if_skreg.h #define SK_XM_CLRBIT_4(sc, reg, x) \
reg 1389 dev/pci/if_skreg.h SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x))
reg 1391 dev/pci/if_skreg.h #define SK_XM_SETBIT_2(sc, reg, x) \
reg 1392 dev/pci/if_skreg.h SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x))
reg 1394 dev/pci/if_skreg.h #define SK_XM_CLRBIT_2(sc, reg, x) \
reg 1395 dev/pci/if_skreg.h SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x))
reg 1398 dev/pci/if_skreg.h #define SK_YU_REG(sc, reg) \
reg 1399 dev/pci/if_skreg.h ((reg) + SK_MARV1_BASE + \
reg 1402 dev/pci/if_skreg.h #define SK_YU_READ_4(sc, reg) \
reg 1403 dev/pci/if_skreg.h sk_win_read_4((sc)->sk_softc, SK_YU_REG((sc), (reg)))
reg 1405 dev/pci/if_skreg.h #define SK_YU_READ_2(sc, reg) \
reg 1406 dev/pci/if_skreg.h sk_win_read_2((sc)->sk_softc, SK_YU_REG((sc), (reg)))
reg 1408 dev/pci/if_skreg.h #define SK_YU_WRITE_4(sc, reg, val) \
reg 1409 dev/pci/if_skreg.h sk_win_write_4((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val))
reg 1411 dev/pci/if_skreg.h #define SK_YU_WRITE_2(sc, reg, val) \
reg 1412 dev/pci/if_skreg.h sk_win_write_2((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val))
reg 1414 dev/pci/if_skreg.h #define SK_YU_SETBIT_4(sc, reg, x) \
reg 1415 dev/pci/if_skreg.h SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) | (x))
reg 1417 dev/pci/if_skreg.h #define SK_YU_CLRBIT_4(sc, reg, x) \
reg 1418 dev/pci/if_skreg.h SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) & ~(x))
reg 1420 dev/pci/if_skreg.h #define SK_YU_SETBIT_2(sc, reg, x) \
reg 1421 dev/pci/if_skreg.h SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) | (x))
reg 1423 dev/pci/if_skreg.h #define SK_YU_CLRBIT_2(sc, reg, x) \
reg 1424 dev/pci/if_skreg.h SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) & ~(x))
reg 1472 dev/pci/if_skreg.h #define CSR_WRITE_4(sc, reg, val) \
reg 1473 dev/pci/if_skreg.h bus_space_write_4((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val))
reg 1474 dev/pci/if_skreg.h #define CSR_WRITE_2(sc, reg, val) \
reg 1475 dev/pci/if_skreg.h bus_space_write_2((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val))
reg 1476 dev/pci/if_skreg.h #define CSR_WRITE_1(sc, reg, val) \
reg 1477 dev/pci/if_skreg.h bus_space_write_1((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val))
reg 1479 dev/pci/if_skreg.h #define CSR_READ_4(sc, reg) \
reg 1480 dev/pci/if_skreg.h bus_space_read_4((sc)->sk_btag, (sc)->sk_bhandle, (reg))
reg 1481 dev/pci/if_skreg.h #define CSR_READ_2(sc, reg) \
reg 1482 dev/pci/if_skreg.h bus_space_read_2((sc)->sk_btag, (sc)->sk_bhandle, (reg))
reg 1483 dev/pci/if_skreg.h #define CSR_READ_1(sc, reg) \
reg 1484 dev/pci/if_skreg.h bus_space_read_1((sc)->sk_btag, (sc)->sk_bhandle, (reg))
reg 180 dev/pci/if_skvar.h int reg;
reg 123 dev/pci/if_ste.c #define STE_SETBIT4(sc, reg, x) \
reg 124 dev/pci/if_ste.c CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
reg 126 dev/pci/if_ste.c #define STE_CLRBIT4(sc, reg, x) \
reg 127 dev/pci/if_ste.c CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
reg 129 dev/pci/if_ste.c #define STE_SETBIT2(sc, reg, x) \
reg 130 dev/pci/if_ste.c CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x)
reg 132 dev/pci/if_ste.c #define STE_CLRBIT2(sc, reg, x) \
reg 133 dev/pci/if_ste.c CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x)
reg 135 dev/pci/if_ste.c #define STE_SETBIT1(sc, reg, x) \
reg 136 dev/pci/if_ste.c CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x)
reg 138 dev/pci/if_ste.c #define STE_CLRBIT1(sc, reg, x) \
reg 139 dev/pci/if_ste.c CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x)
reg 334 dev/pci/if_ste.c ste_miibus_readreg(struct device *self, int phy, int reg)
reg 345 dev/pci/if_ste.c frame.mii_regaddr = reg;
reg 352 dev/pci/if_ste.c ste_miibus_writereg(struct device *self, int phy, int reg, int data)
reg 360 dev/pci/if_ste.c frame.mii_regaddr = reg;
reg 451 dev/pci/if_stereg.h #define CSR_WRITE_4(sc, reg, val) \
reg 452 dev/pci/if_stereg.h bus_space_write_4(sc->ste_btag, sc->ste_bhandle, reg, val)
reg 453 dev/pci/if_stereg.h #define CSR_WRITE_2(sc, reg, val) \
reg 454 dev/pci/if_stereg.h bus_space_write_2(sc->ste_btag, sc->ste_bhandle, reg, val)
reg 455 dev/pci/if_stereg.h #define CSR_WRITE_1(sc, reg, val) \
reg 456 dev/pci/if_stereg.h bus_space_write_1(sc->ste_btag, sc->ste_bhandle, reg, val)
reg 458 dev/pci/if_stereg.h #define CSR_READ_4(sc, reg) \
reg 459 dev/pci/if_stereg.h bus_space_read_4(sc->ste_btag, sc->ste_bhandle, reg)
reg 460 dev/pci/if_stereg.h #define CSR_READ_2(sc, reg) \
reg 461 dev/pci/if_stereg.h bus_space_read_2(sc->ste_btag, sc->ste_bhandle, reg)
reg 462 dev/pci/if_stereg.h #define CSR_READ_1(sc, reg) \
reg 463 dev/pci/if_stereg.h bus_space_read_1(sc->ste_btag, sc->ste_bhandle, reg)
reg 1638 dev/pci/if_stge.c stge_mii_readreg(struct device *self, int phy, int reg)
reg 1641 dev/pci/if_stge.c return (mii_bitbang_readreg(self, &stge_mii_bitbang_ops, phy, reg));
reg 1650 dev/pci/if_stge.c stge_mii_writereg(struct device *self, int phy, int reg, int val)
reg 1653 dev/pci/if_stge.c mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg, val);
reg 54 dev/pci/if_stgereg.h #define CSR_WRITE_4(_sc, reg, val) \
reg 55 dev/pci/if_stgereg.h bus_space_write_4((_sc)->sc_st, (_sc)->sc_sh, (reg), (val))
reg 56 dev/pci/if_stgereg.h #define CSR_WRITE_2(_sc, reg, val) \
reg 57 dev/pci/if_stgereg.h bus_space_write_2((_sc)->sc_st, (_sc)->sc_sh, (reg), (val))
reg 58 dev/pci/if_stgereg.h #define CSR_WRITE_1(_sc, reg, val) \
reg 59 dev/pci/if_stgereg.h bus_space_write_1((_sc)->sc_st, (_sc)->sc_sh, (reg), (val))
reg 61 dev/pci/if_stgereg.h #define CSR_READ_4(_sc, reg) \
reg 62 dev/pci/if_stgereg.h bus_space_read_4((_sc)->sc_st, (_sc)->sc_sh, (reg))
reg 63 dev/pci/if_stgereg.h #define CSR_READ_2(_sc, reg) \
reg 64 dev/pci/if_stgereg.h bus_space_read_2((_sc)->sc_st, (_sc)->sc_sh, (reg))
reg 65 dev/pci/if_stgereg.h #define CSR_READ_1(_sc, reg) \
reg 66 dev/pci/if_stgereg.h bus_space_read_1((_sc)->sc_st, (_sc)->sc_sh, (reg))
reg 975 dev/pci/if_tireg.h #define CSR_WRITE_4(sc, reg, val) \
reg 976 dev/pci/if_tireg.h bus_space_write_4(sc->ti_btag, sc->ti_bhandle, (reg), (val))
reg 978 dev/pci/if_tireg.h #define CSR_READ_4(sc, reg) \
reg 979 dev/pci/if_tireg.h bus_space_read_4(sc->ti_btag, sc->ti_bhandle, (reg))
reg 981 dev/pci/if_tireg.h #define TI_SETBIT(sc, reg, x) \
reg 982 dev/pci/if_tireg.h CSR_WRITE_4(sc, (reg), (CSR_READ_4(sc, (reg)) | (x)))
reg 983 dev/pci/if_tireg.h #define TI_CLRBIT(sc, reg, x) \
reg 984 dev/pci/if_tireg.h CSR_WRITE_4(sc, (reg), (CSR_READ_4(sc, (reg)) & ~(x)))
reg 306 dev/pci/if_tl.c u_int8_t tl_dio_read8(sc, reg)
reg 308 dev/pci/if_tl.c int reg;
reg 310 dev/pci/if_tl.c CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
reg 311 dev/pci/if_tl.c return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)));
reg 314 dev/pci/if_tl.c u_int16_t tl_dio_read16(sc, reg)
reg 316 dev/pci/if_tl.c int reg;
reg 318 dev/pci/if_tl.c CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
reg 319 dev/pci/if_tl.c return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)));
reg 322 dev/pci/if_tl.c u_int32_t tl_dio_read32(sc, reg)
reg 324 dev/pci/if_tl.c int reg;
reg 326 dev/pci/if_tl.c CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
reg 327 dev/pci/if_tl.c return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3)));
reg 330 dev/pci/if_tl.c void tl_dio_write8(sc, reg, val)
reg 332 dev/pci/if_tl.c int reg;
reg 335 dev/pci/if_tl.c CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
reg 336 dev/pci/if_tl.c CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val);
reg 340 dev/pci/if_tl.c void tl_dio_write16(sc, reg, val)
reg 342 dev/pci/if_tl.c int reg;
reg 345 dev/pci/if_tl.c CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
reg 346 dev/pci/if_tl.c CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val);
reg 350 dev/pci/if_tl.c void tl_dio_write32(sc, reg, val)
reg 352 dev/pci/if_tl.c int reg;
reg 355 dev/pci/if_tl.c CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
reg 356 dev/pci/if_tl.c CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val);
reg 360 dev/pci/if_tl.c void tl_dio_setbit(sc, reg, bit)
reg 362 dev/pci/if_tl.c int reg;
reg 367 dev/pci/if_tl.c CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
reg 368 dev/pci/if_tl.c f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
reg 370 dev/pci/if_tl.c CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
reg 375 dev/pci/if_tl.c void tl_dio_clrbit(sc, reg, bit)
reg 377 dev/pci/if_tl.c int reg;
reg 382 dev/pci/if_tl.c CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
reg 383 dev/pci/if_tl.c f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
reg 385 dev/pci/if_tl.c CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
reg 390 dev/pci/if_tl.c void tl_dio_setbit16(sc, reg, bit)
reg 392 dev/pci/if_tl.c int reg;
reg 397 dev/pci/if_tl.c CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
reg 398 dev/pci/if_tl.c f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
reg 400 dev/pci/if_tl.c CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
reg 405 dev/pci/if_tl.c void tl_dio_clrbit16(sc, reg, bit)
reg 407 dev/pci/if_tl.c int reg;
reg 412 dev/pci/if_tl.c CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
reg 413 dev/pci/if_tl.c f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
reg 415 dev/pci/if_tl.c CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
reg 738 dev/pci/if_tl.c int tl_miibus_readreg(dev, phy, reg)
reg 740 dev/pci/if_tl.c int phy, reg;
reg 748 dev/pci/if_tl.c frame.mii_regaddr = reg;
reg 754 dev/pci/if_tl.c void tl_miibus_writereg(dev, phy, reg, data)
reg 756 dev/pci/if_tl.c int phy, reg, data;
reg 764 dev/pci/if_tl.c frame.mii_regaddr = reg;
reg 501 dev/pci/if_tlreg.h #define CSR_WRITE_4(sc, reg, val) \
reg 502 dev/pci/if_tlreg.h bus_space_write_4(sc->tl_btag, sc->tl_bhandle, reg, val)
reg 503 dev/pci/if_tlreg.h #define CSR_WRITE_2(sc, reg, val) \
reg 504 dev/pci/if_tlreg.h bus_space_write_2(sc->tl_btag, sc->tl_bhandle, reg, val)
reg 505 dev/pci/if_tlreg.h #define CSR_WRITE_1(sc, reg, val) \
reg 506 dev/pci/if_tlreg.h bus_space_write_1(sc->tl_btag, sc->tl_bhandle, reg, val)
reg 508 dev/pci/if_tlreg.h #define CSR_READ_4(sc, reg) \
reg 509 dev/pci/if_tlreg.h bus_space_read_4(sc->tl_btag, sc->tl_bhandle, reg)
reg 510 dev/pci/if_tlreg.h #define CSR_READ_2(sc, reg) \
reg 511 dev/pci/if_tlreg.h bus_space_read_2(sc->tl_btag, sc->tl_bhandle, reg)
reg 512 dev/pci/if_tlreg.h #define CSR_READ_1(sc, reg) \
reg 513 dev/pci/if_tlreg.h bus_space_read_1(sc->tl_btag, sc->tl_bhandle, reg)
reg 611 dev/pci/if_txpreg.h #define WRITE_REG(sc,reg,val) \
reg 612 dev/pci/if_txpreg.h bus_space_write_4((sc)->sc_bt, (sc)->sc_bh, reg, val)
reg 613 dev/pci/if_txpreg.h #define READ_REG(sc,reg) \
reg 614 dev/pci/if_txpreg.h bus_space_read_4((sc)->sc_bt, (sc)->sc_bh, reg)
reg 312 dev/pci/if_vge.c vge_miibus_readreg(struct device *dev, int phy, int reg)
reg 326 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_MIIADDR, reg);
reg 350 dev/pci/if_vge.c vge_miibus_writereg(struct device *dev, int phy, int reg, int data)
reg 362 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_MIIADDR, reg);
reg 98 dev/pci/if_vgevar.h #define CSR_WRITE_4(sc, reg, val) \
reg 99 dev/pci/if_vgevar.h bus_space_write_4(sc->vge_btag, sc->vge_bhandle, reg, val)
reg 100 dev/pci/if_vgevar.h #define CSR_WRITE_2(sc, reg, val) \
reg 101 dev/pci/if_vgevar.h bus_space_write_2(sc->vge_btag, sc->vge_bhandle, reg, val)
reg 102 dev/pci/if_vgevar.h #define CSR_WRITE_1(sc, reg, val) \
reg 103 dev/pci/if_vgevar.h bus_space_write_1(sc->vge_btag, sc->vge_bhandle, reg, val)
reg 105 dev/pci/if_vgevar.h #define CSR_READ_4(sc, reg) \
reg 106 dev/pci/if_vgevar.h bus_space_read_4(sc->vge_btag, sc->vge_bhandle, reg)
reg 107 dev/pci/if_vgevar.h #define CSR_READ_2(sc, reg) \
reg 108 dev/pci/if_vgevar.h bus_space_read_2(sc->vge_btag, sc->vge_bhandle, reg)
reg 109 dev/pci/if_vgevar.h #define CSR_READ_1(sc, reg) \
reg 110 dev/pci/if_vgevar.h bus_space_read_1(sc->vge_btag, sc->vge_bhandle, reg)
reg 112 dev/pci/if_vgevar.h #define CSR_SETBIT_1(sc, reg, x) \
reg 113 dev/pci/if_vgevar.h CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
reg 114 dev/pci/if_vgevar.h #define CSR_SETBIT_2(sc, reg, x) \
reg 115 dev/pci/if_vgevar.h CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
reg 116 dev/pci/if_vgevar.h #define CSR_SETBIT_4(sc, reg, x) \
reg 117 dev/pci/if_vgevar.h CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
reg 119 dev/pci/if_vgevar.h #define CSR_CLRBIT_1(sc, reg, x) \
reg 120 dev/pci/if_vgevar.h CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
reg 121 dev/pci/if_vgevar.h #define CSR_CLRBIT_2(sc, reg, x) \
reg 122 dev/pci/if_vgevar.h CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
reg 123 dev/pci/if_vgevar.h #define CSR_CLRBIT_4(sc, reg, x) \
reg 124 dev/pci/if_vgevar.h CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
reg 900 dev/pci/if_vic.c u_int32_t reg;
reg 903 dev/pci/if_vic.c reg = (sc->sc_cap & VIC_CMD_HWCAP_VPROM) ? VIC_VPROM : VIC_LLADDR;
reg 905 dev/pci/if_vic.c bus_space_barrier(sc->sc_iot, sc->sc_ioh, reg, ETHER_ADDR_LEN,
reg 907 dev/pci/if_vic.c bus_space_read_region_1(sc->sc_iot, sc->sc_ioh, reg, sc->sc_lladdr,
reg 911 dev/pci/if_vic.c if (reg == VIC_VPROM)
reg 154 dev/pci/if_vr.c #define VR_SETBIT(sc, reg, x) \
reg 155 dev/pci/if_vr.c CSR_WRITE_1(sc, reg, \
reg 156 dev/pci/if_vr.c CSR_READ_1(sc, reg) | (x))
reg 158 dev/pci/if_vr.c #define VR_CLRBIT(sc, reg, x) \
reg 159 dev/pci/if_vr.c CSR_WRITE_1(sc, reg, \
reg 160 dev/pci/if_vr.c CSR_READ_1(sc, reg) & ~(x))
reg 162 dev/pci/if_vr.c #define VR_SETBIT16(sc, reg, x) \
reg 163 dev/pci/if_vr.c CSR_WRITE_2(sc, reg, \
reg 164 dev/pci/if_vr.c CSR_READ_2(sc, reg) | (x))
reg 166 dev/pci/if_vr.c #define VR_CLRBIT16(sc, reg, x) \
reg 167 dev/pci/if_vr.c CSR_WRITE_2(sc, reg, \
reg 168 dev/pci/if_vr.c CSR_READ_2(sc, reg) & ~(x))
reg 170 dev/pci/if_vr.c #define VR_SETBIT32(sc, reg, x) \
reg 171 dev/pci/if_vr.c CSR_WRITE_4(sc, reg, \
reg 172 dev/pci/if_vr.c CSR_READ_4(sc, reg) | (x))
reg 174 dev/pci/if_vr.c #define VR_CLRBIT32(sc, reg, x) \
reg 175 dev/pci/if_vr.c CSR_WRITE_4(sc, reg, \
reg 176 dev/pci/if_vr.c CSR_READ_4(sc, reg) & ~(x))
reg 430 dev/pci/if_vr.c vr_miibus_readreg(struct device *dev, int phy, int reg)
reg 447 dev/pci/if_vr.c frame.mii_regaddr = reg;
reg 454 dev/pci/if_vr.c vr_miibus_writereg(struct device *dev, int phy, int reg, int data)
reg 471 dev/pci/if_vr.c frame.mii_regaddr = reg;
reg 482 dev/pci/if_vrreg.h #define CSR_WRITE_4(sc, reg, val) \
reg 483 dev/pci/if_vrreg.h bus_space_write_4(sc->vr_btag, sc->vr_bhandle, reg, val)
reg 484 dev/pci/if_vrreg.h #define CSR_WRITE_2(sc, reg, val) \
reg 485 dev/pci/if_vrreg.h bus_space_write_2(sc->vr_btag, sc->vr_bhandle, reg, val)
reg 486 dev/pci/if_vrreg.h #define CSR_WRITE_1(sc, reg, val) \
reg 487 dev/pci/if_vrreg.h bus_space_write_1(sc->vr_btag, sc->vr_bhandle, reg, val)
reg 489 dev/pci/if_vrreg.h #define CSR_READ_4(sc, reg) \
reg 490 dev/pci/if_vrreg.h bus_space_read_4(sc->vr_btag, sc->vr_bhandle, reg)
reg 491 dev/pci/if_vrreg.h #define CSR_READ_2(sc, reg) \
reg 492 dev/pci/if_vrreg.h bus_space_read_2(sc->vr_btag, sc->vr_bhandle, reg)
reg 493 dev/pci/if_vrreg.h #define CSR_READ_1(sc, reg) \
reg 494 dev/pci/if_vrreg.h bus_space_read_1(sc->vr_btag, sc->vr_bhandle, reg)
reg 178 dev/pci/if_wb.c #define WB_SETBIT(sc, reg, x) \
reg 179 dev/pci/if_wb.c CSR_WRITE_4(sc, reg, \
reg 180 dev/pci/if_wb.c CSR_READ_4(sc, reg) | x)
reg 182 dev/pci/if_wb.c #define WB_CLRBIT(sc, reg, x) \
reg 183 dev/pci/if_wb.c CSR_WRITE_4(sc, reg, \
reg 184 dev/pci/if_wb.c CSR_READ_4(sc, reg) & ~x)
reg 481 dev/pci/if_wb.c wb_miibus_readreg(dev, phy, reg)
reg 483 dev/pci/if_wb.c int phy, reg;
reg 491 dev/pci/if_wb.c frame.mii_regaddr = reg;
reg 498 dev/pci/if_wb.c wb_miibus_writereg(dev, phy, reg, data)
reg 500 dev/pci/if_wb.c int phy, reg, data;
reg 508 dev/pci/if_wb.c frame.mii_regaddr = reg;
reg 385 dev/pci/if_wbreg.h #define CSR_WRITE_4(sc, reg, val) \
reg 386 dev/pci/if_wbreg.h bus_space_write_4(sc->wb_btag, sc->wb_bhandle, reg, val)
reg 387 dev/pci/if_wbreg.h #define CSR_WRITE_2(sc, reg, val) \
reg 388 dev/pci/if_wbreg.h bus_space_write_2(sc->wb_btag, sc->wb_bhandle, reg, val)
reg 389 dev/pci/if_wbreg.h #define CSR_WRITE_1(sc, reg, val) \
reg 390 dev/pci/if_wbreg.h bus_space_write_1(sc->wb_btag, sc->wb_bhandle, reg, val)
reg 392 dev/pci/if_wbreg.h #define CSR_READ_4(sc, reg) \
reg 393 dev/pci/if_wbreg.h bus_space_read_4(sc->wb_btag, sc->wb_bhandle, reg)
reg 394 dev/pci/if_wbreg.h #define CSR_READ_2(sc, reg) \
reg 395 dev/pci/if_wbreg.h bus_space_read_2(sc->wb_btag, sc->wb_bhandle, reg)
reg 396 dev/pci/if_wbreg.h #define CSR_READ_1(sc, reg) \
reg 397 dev/pci/if_wbreg.h bus_space_read_1(sc->wb_btag, sc->wb_bhandle, reg)
reg 719 dev/pci/if_wpireg.h #define WPI_READ(sc, reg) \
reg 720 dev/pci/if_wpireg.h bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
reg 722 dev/pci/if_wpireg.h #define WPI_WRITE(sc, reg, val) \
reg 723 dev/pci/if_wpireg.h bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
reg 681 dev/pci/if_xge.c uint64_t reg;
reg 686 dev/pci/if_xge.c reg = PIF_RCSR(ADAPTER_STATUS);
reg 687 dev/pci/if_xge.c if ((reg & (RMAC_REMOTE_FAULT|RMAC_LOCAL_FAULT)) == 0)
reg 103 dev/pci/iop_pci.c pcireg_t reg;
reg 116 dev/pci/iop_pci.c reg = pci_conf_read(pc, pa->pa_tag, i);
reg 117 dev/pci/iop_pci.c if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_MEM)
reg 840 dev/pci/ips.c u_int32_t reg;
reg 844 dev/pci/ips.c reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, IPS_REG_CCC);
reg 845 dev/pci/ips.c if ((reg & IPS_REG_CCC_SEM) == 0)
reg 873 dev/pci/ips.c u_int8_t reg;
reg 875 dev/pci/ips.c reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, IPS_REG_HIS);
reg 876 dev/pci/ips.c bus_space_write_1(sc->sc_iot, sc->sc_ioh, IPS_REG_HIS, reg);
reg 877 dev/pci/ips.c if (reg != 0xff && (reg & IPS_REG_HIS_SCE))
reg 912 dev/pci/ips.c u_int32_t reg;
reg 914 dev/pci/ips.c reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, IPS_REG_OIM);
reg 915 dev/pci/ips.c reg &= ~IPS_REG_OIM_DS;
reg 916 dev/pci/ips.c bus_space_write_4(sc->sc_iot, sc->sc_ioh, IPS_REG_OIM, reg);
reg 922 dev/pci/ips.c u_int32_t reg;
reg 924 dev/pci/ips.c reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, IPS_REG_OIS);
reg 925 dev/pci/ips.c DPRINTF(IPS_D_XFER, ("%s: isintr 0x%08x\n", sc->sc_dev.dv_xname, reg));
reg 927 dev/pci/ips.c return (reg & IPS_REG_OIS_PEND);
reg 940 dev/pci/ips.c u_int32_t reg;
reg 942 dev/pci/ips.c reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, IPS_REG_OQP);
reg 943 dev/pci/ips.c DPRINTF(IPS_D_XFER, ("%s: status 0x%08x\n", sc->sc_dev.dv_xname, reg));
reg 945 dev/pci/ips.c return (reg);
reg 89 dev/pci/ises.c #define WRITE_REG(sc,reg,val) \
reg 90 dev/pci/ises.c bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, reg, val)
reg 105 dev/pci/ixgb_ee.h uint16_t ixgb_read_eeprom(struct ixgb_hw *hw, uint16_t reg);
reg 111 dev/pci/ixgb_ee.h void ixgb_write_eeprom(struct ixgb_hw *hw, uint16_t reg, uint16_t data);
reg 862 dev/pci/ixgb_hw.h void ixgb_write_pci_cfg(struct ixgb_hw *hw, uint32_t reg, uint16_t *value);
reg 792 dev/pci/maestro.c int reg;
reg 827 dev/pci/maestro.c for (reg = WAVCACHE_PCMBAR; reg < WAVCACHE_PCMBAR + 4; reg++)
reg 828 dev/pci/maestro.c wc_reg_write(sc, reg,
reg 1691 dev/pci/maestro.c wp_reg_read(struct maestro_softc *sc, int reg)
reg 1693 dev/pci/maestro.c bus_space_write_2(sc->iot, sc->ioh, PORT_DSP_INDEX, reg);
reg 1698 dev/pci/maestro.c wp_reg_write(struct maestro_softc *sc, int reg, wpreg_t data)
reg 1700 dev/pci/maestro.c bus_space_write_2(sc->iot, sc->ioh, PORT_DSP_INDEX, reg);
reg 1705 dev/pci/maestro.c apu_setindex(struct maestro_softc *sc, int reg)
reg 1709 dev/pci/maestro.c wp_reg_write(sc, WPREG_CRAM_PTR, reg);
reg 1713 dev/pci/maestro.c PORT_DSP_DATA) == reg)
reg 1715 dev/pci/maestro.c bus_space_write_2(sc->iot, sc->ioh, PORT_DSP_DATA, reg);
reg 1722 dev/pci/maestro.c wp_apu_read(struct maestro_softc *sc, int ch, int reg)
reg 1726 dev/pci/maestro.c apu_setindex(sc, ((unsigned)ch << 4) + reg);
reg 1732 dev/pci/maestro.c wp_apu_write(struct maestro_softc *sc, int ch, int reg, wpreg_t data)
reg 1736 dev/pci/maestro.c apu_setindex(sc, ((unsigned)ch << 4) + reg);
reg 1787 dev/pci/maestro.c wc_reg_read(struct maestro_softc *sc, int reg)
reg 1789 dev/pci/maestro.c bus_space_write_2(sc->iot, sc->ioh, PORT_WAVCACHE_INDEX, reg);
reg 1794 dev/pci/maestro.c wc_reg_write(struct maestro_softc *sc, int reg, wcreg_t data)
reg 1796 dev/pci/maestro.c bus_space_write_2(sc->iot, sc->ioh, PORT_WAVCACHE_INDEX, reg);
reg 201 dev/pci/noct.c u_int32_t reg;
reg 204 dev/pci/noct.c reg = NOCT_READ_4(sc, NOCT_BRDG_STAT);
reg 206 dev/pci/noct.c if (reg & BRDGSTS_RNG_INT) {
reg 211 dev/pci/noct.c if (reg & BRDGSTS_PKP_INT) {
reg 216 dev/pci/noct.c if (reg & BRDGSTS_CCH_INT) {
reg 252 dev/pci/noct.c u_int32_t reg;
reg 256 dev/pci/noct.c reg = NOCT_READ_4(sc, NOCT_EA_CTX_ADDR);
reg 257 dev/pci/noct.c if ((reg & EACTXADDR_WRITEPEND) == 0)
reg 266 dev/pci/noct.c reg = NOCT_READ_4(sc, NOCT_EA_CTX_ADDR);
reg 267 dev/pci/noct.c if ((reg & EACTXADDR_WRITEPEND) == 0)
reg 278 dev/pci/noct.c u_int32_t reg;
reg 282 dev/pci/noct.c reg = NOCT_READ_4(sc, NOCT_EA_CTX_ADDR);
reg 283 dev/pci/noct.c if ((reg & EACTXADDR_READPEND) == 0)
reg 290 dev/pci/noct.c reg = NOCT_READ_4(sc, NOCT_EA_CTX_ADDR);
reg 291 dev/pci/noct.c if ((reg & EACTXADDR_READPEND) == 0)
reg 702 dev/pci/noct.c u_int32_t reg, rd, wr;
reg 705 dev/pci/noct.c reg = NOCT_READ_4(sc, NOCT_RNG_Q_PTR);
reg 706 dev/pci/noct.c rd = (reg & RNGQPTR_READ_M) >> RNGQPTR_READ_S;
reg 707 dev/pci/noct.c wr = (reg & RNGQPTR_WRITE_M) >> RNGQPTR_WRITE_S;
reg 1329 dev/pci/noct.c noct_write_8(sc, reg, val)
reg 1331 dev/pci/noct.c u_int32_t reg;
reg 1334 dev/pci/noct.c NOCT_WRITE_4(sc, reg, (val >> 32) & 0xffffffff);
reg 1335 dev/pci/noct.c NOCT_WRITE_4(sc, reg + 4, (val >> 0) & 0xffffffff);
reg 1339 dev/pci/noct.c noct_read_8(sc, reg)
reg 1341 dev/pci/noct.c u_int32_t reg;
reg 1345 dev/pci/noct.c ret = NOCT_READ_4(sc, reg);
reg 1347 dev/pci/noct.c ret |= NOCT_READ_4(sc, reg + 4);
reg 216 dev/pci/nofn.c u_int32_t buf[8], reg;
reg 220 dev/pci/nofn.c reg = PK_READ_4(sc, NOFN_PK_SR);
reg 221 dev/pci/nofn.c if (reg & PK_SR_UFLOW) {
reg 229 dev/pci/nofn.c if ((reg & PK_SR_RRDY) == 0)
reg 144 dev/pci/nviic.c pcireg_t reg;
reg 169 dev/pci/nviic.c reg = pci_conf_read(pa->pa_pc, pa->pa_tag, baseregs[i]);
reg 170 dev/pci/nviic.c if (NVI_SMBASE(reg) == 0 ||
reg 171 dev/pci/nviic.c bus_space_map(sc->sc_iot, NVI_SMBASE(reg), NVI_SMBASE_SIZE,
reg 100 dev/pci/pccbb.c #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg)))
reg 101 dev/pci/pccbb.c #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val)))
reg 372 dev/pci/pccbb.c pcireg_t busreg, reg, sock_base;
reg 512 dev/pci/pccbb.c reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR);
reg 513 dev/pci/pccbb.c reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA);
reg 514 dev/pci/pccbb.c pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg);
reg 666 dev/pci/pccbb.c pcireg_t reg;
reg 672 dev/pci/pccbb.c reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
reg 674 dev/pci/pccbb.c reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
reg 676 dev/pci/pccbb.c pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg);
reg 681 dev/pci/pccbb.c reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG);
reg 682 dev/pci/pccbb.c if (PCI_CB_LATENCY(reg) < 0x20) {
reg 683 dev/pci/pccbb.c reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT);
reg 684 dev/pci/pccbb.c reg |= (0x20 << PCI_CB_LATENCY_SHIFT);
reg 685 dev/pci/pccbb.c pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg);
reg 688 dev/pci/pccbb.c PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG)));
reg 693 dev/pci/pccbb.c reg = pci_conf_read(pc, tag, PCI_BHLC_REG);
reg 694 dev/pci/pccbb.c if (PCI_LATTIMER(reg) < 0x10) {
reg 695 dev/pci/pccbb.c reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
reg 696 dev/pci/pccbb.c reg |= (0x10 << PCI_LATTIMER_SHIFT);
reg 697 dev/pci/pccbb.c pci_conf_write(pc, tag, PCI_BHLC_REG, reg);
reg 700 dev/pci/pccbb.c PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG)));
reg 703 dev/pci/pccbb.c reg = pci_conf_read(pc, tag, PCI_BCR_INTR);
reg 704 dev/pci/pccbb.c reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */
reg 705 dev/pci/pccbb.c reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */
reg 706 dev/pci/pccbb.c reg |= CB_BCR_RESET_ENABLE; /* assert reset */
reg 707 dev/pci/pccbb.c pci_conf_write(pc, tag, PCI_BCR_INTR, reg);
reg 711 dev/pci/pccbb.c reg = pci_conf_read(pc, tag, PCI_CBCTRL);
reg 714 dev/pci/pccbb.c reg |= PCI113X_CBCTRL_PCI_IRQ_ENA;
reg 716 dev/pci/pccbb.c reg |= PCI113X_CBCTRL_PCI_CSC;
reg 718 dev/pci/pccbb.c reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK);
reg 719 dev/pci/pccbb.c pci_conf_write(pc, tag, PCI_CBCTRL, reg);
reg 732 dev/pci/pccbb.c reg = pci_conf_read(pc, tag, PCI12XX_MFUNC);
reg 733 dev/pci/pccbb.c if (reg == 0) {
reg 734 dev/pci/pccbb.c reg &= ~PCI12XX_MFUNC_PIN0;
reg 735 dev/pci/pccbb.c reg |= PCI12XX_MFUNC_PIN0_INTA;
reg 738 dev/pci/pccbb.c reg &= ~PCI12XX_MFUNC_PIN1;
reg 739 dev/pci/pccbb.c reg |= PCI12XX_MFUNC_PIN1_INTB;
reg 741 dev/pci/pccbb.c pci_conf_write(pc, tag, PCI12XX_MFUNC, reg);
reg 753 dev/pci/pccbb.c reg = pci_conf_read(pc, tag, PCI_SYSCTRL);
reg 754 dev/pci/pccbb.c reg |= PCI12XX_SYSCTRL_VCCPROT;
reg 755 dev/pci/pccbb.c pci_conf_write(pc, tag, PCI_SYSCTRL, reg);
reg 756 dev/pci/pccbb.c reg = pci_conf_read(pc, tag, PCI_CBCTRL);
reg 757 dev/pci/pccbb.c reg |= PCI12XX_CBCTRL_CSC;
reg 758 dev/pci/pccbb.c pci_conf_write(pc, tag, PCI_CBCTRL, reg);
reg 762 dev/pci/pccbb.c reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL);
reg 763 dev/pci/pccbb.c reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL;
reg 764 dev/pci/pccbb.c pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg);
reg 766 dev/pci/pccbb.c reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL);
reg 768 dev/pci/pccbb.c sc->sc_dev.dv_xname, reg));
reg 769 dev/pci/pccbb.c reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN |
reg 771 dev/pci/pccbb.c reg &= ~TOPIC_SLOT_CTRL_SWDETECT;
reg 772 dev/pci/pccbb.c DPRINTF(("0x%x\n", reg));
reg 773 dev/pci/pccbb.c pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg);
reg 777 dev/pci/pccbb.c reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL);
reg 779 dev/pci/pccbb.c sc->sc_dev.dv_xname, reg));
reg 780 dev/pci/pccbb.c reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN |
reg 782 dev/pci/pccbb.c reg &= ~TOPIC_SLOT_CTRL_SWDETECT;
reg 783 dev/pci/pccbb.c reg |= TOPIC97_SLOT_CTRL_PCIINT;
reg 784 dev/pci/pccbb.c reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP);
reg 785 dev/pci/pccbb.c DPRINTF(("0x%x\n", reg));
reg 786 dev/pci/pccbb.c pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg);
reg 794 dev/pci/pccbb.c reg = pci_conf_read(pc, tag, TOPIC100_PMCSR);
reg 795 dev/pci/pccbb.c if ((reg & TOPIC100_PMCSR_MASK) != TOPIC100_PMCSR_D0)
reg 797 dev/pci/pccbb.c (reg & ~TOPIC100_PMCSR_MASK) | TOPIC100_PMCSR_D0);
reg 809 dev/pci/pccbb.c sc->sc_dev.dv_xname, reg));
reg 810 dev/pci/pccbb.c reg = pci_conf_read(pc, tag, O2MICRO_RESERVED1);
reg 811 dev/pci/pccbb.c pci_conf_write(pc, tag, O2MICRO_RESERVED1, reg &
reg 813 dev/pci/pccbb.c reg = pci_conf_read(pc, tag, O2MICRO_RESERVED2);
reg 814 dev/pci/pccbb.c pci_conf_write(pc, tag, O2MICRO_RESERVED2, reg &
reg 1111 dev/pci/pccbb.c pccbb_pcmcia_read(ph, reg)
reg 1113 dev/pci/pccbb.c int reg;
reg 1116 dev/pci/pccbb.c PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ);
reg 1119 dev/pci/pccbb.c PCCBB_PCMCIA_OFFSET + reg);
reg 1123 dev/pci/pccbb.c pccbb_pcmcia_write(ph, reg, val)
reg 1125 dev/pci/pccbb.c int reg;
reg 1129 dev/pci/pccbb.c PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE);
reg 1131 dev/pci/pccbb.c bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg,
reg 1600 dev/pci/pccbb.c pcireg_t reg;
reg 1606 dev/pci/pccbb.c reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR);
reg 1607 dev/pci/pccbb.c reg &= ~CB_BCR_INTR_IREQ_ENABLE;
reg 1608 dev/pci/pccbb.c pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg);
reg 1612 dev/pci/pccbb.c reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL);
reg 1614 dev/pci/pccbb.c reg |= PCI113X_CBCTRL_PCI_INTR;
reg 1615 dev/pci/pccbb.c pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg);
reg 1660 dev/pci/pccbb.c pcireg_t reg;
reg 1683 dev/pci/pccbb.c reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR);
reg 1684 dev/pci/pccbb.c reg |= CB_BCR_INTR_IREQ_ENABLE;
reg 1685 dev/pci/pccbb.c pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg);
reg 1689 dev/pci/pccbb.c reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL);
reg 1691 dev/pci/pccbb.c reg &= ~PCI113X_CBCTRL_PCI_INTR;
reg 1692 dev/pci/pccbb.c pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg);
reg 1788 dev/pci/pccbb.c pccbb_conf_write(cc, tag, reg, val)
reg 1791 dev/pci/pccbb.c int reg; /* register offset */
reg 1796 dev/pci/pccbb.c pci_conf_write(sc->sc_pc, tag, reg, val);
reg 2073 dev/pci/pccbb.c int reg;
reg 2079 dev/pci/pccbb.c reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE);
reg 2082 dev/pci/pccbb.c reg &= ~PCIC_ADDRWIN_ENABLE_IO0;
reg 2085 dev/pci/pccbb.c reg &= ~PCIC_ADDRWIN_ENABLE_IO1;
reg 2088 dev/pci/pccbb.c Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg);
reg 2406 dev/pci/pccbb.c int reg;
reg 2453 dev/pci/pccbb.c reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE);
reg 2454 dev/pci/pccbb.c reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16);
reg 2455 dev/pci/pccbb.c Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg);
reg 2573 dev/pci/pccbb.c int reg;
reg 2579 dev/pci/pccbb.c reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE);
reg 2580 dev/pci/pccbb.c reg &= ~(1 << window);
reg 2581 dev/pci/pccbb.c Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg);
reg 3059 dev/pci/pccbb.c u_int32_t reg;
reg 3087 dev/pci/pccbb.c reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK);
reg 3089 dev/pci/pccbb.c reg |= CB_SOCKET_MASK_CD;
reg 3090 dev/pci/pccbb.c bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg);
reg 3092 dev/pci/pccbb.c reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT);
reg 3093 dev/pci/pccbb.c bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg);
reg 171 dev/pci/pci.c pcireg_t reg;
reg 190 dev/pci/pci.c reg = pci_conf_read(sc->sc_pc, pd->pd_tag,
reg 194 dev/pci/pci.c (reg & 0xffff0000) | (pd->pd_csr & 0x0000ffff));
reg 330 dev/pci/pci.c pcireg_t reg;
reg 333 dev/pci/pci.c reg = pci_conf_read(pc, tag, PCI_BHLC_REG);
reg 334 dev/pci/pci.c if (PCI_HDRTYPE_TYPE(reg) != 0)
reg 355 dev/pci/pci.c pcireg_t reg;
reg 358 dev/pci/pci.c reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
reg 359 dev/pci/pci.c if (!(reg & PCI_STATUS_CAPLIST_SUPPORT))
reg 363 dev/pci/pci.c reg = pci_conf_read(pc, tag, PCI_BHLC_REG);
reg 364 dev/pci/pci.c switch (PCI_HDRTYPE_TYPE(reg)) {
reg 381 dev/pci/pci.c reg = pci_conf_read(pc, tag, ofs);
reg 382 dev/pci/pci.c if (PCI_CAPLIST_CAP(reg) == capid) {
reg 386 dev/pci/pci.c *value = reg;
reg 389 dev/pci/pci.c ofs = PCI_CAPLIST_NEXT(reg);
reg 58 dev/pci/pci_map.c obsd_pci_io_find(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type,
reg 64 dev/pci/pci_map.c if (reg < PCI_MAPREG_START ||
reg 70 dev/pci/pci_map.c reg >= PCI_MAPREG_END ||
reg 72 dev/pci/pci_map.c (reg & 3))
reg 90 dev/pci/pci_map.c address = pci_conf_read(pc, tag, reg);
reg 91 dev/pci/pci_map.c pci_conf_write(pc, tag, reg, 0xffffffff);
reg 92 dev/pci/pci_map.c mask = pci_conf_read(pc, tag, reg);
reg 93 dev/pci/pci_map.c pci_conf_write(pc, tag, reg, address);
reg 123 dev/pci/pci_map.c obsd_pci_mem_find(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type,
reg 132 dev/pci/pci_map.c if (reg < PCI_MAPREG_START ||
reg 138 dev/pci/pci_map.c reg >= PCI_MAPREG_END ||
reg 140 dev/pci/pci_map.c (reg & 3))
reg 143 dev/pci/pci_map.c if (is64bit && (reg + 4) >= PCI_MAPREG_END)
reg 161 dev/pci/pci_map.c address = pci_conf_read(pc, tag, reg);
reg 162 dev/pci/pci_map.c pci_conf_write(pc, tag, reg, 0xffffffff);
reg 163 dev/pci/pci_map.c mask = pci_conf_read(pc, tag, reg);
reg 164 dev/pci/pci_map.c pci_conf_write(pc, tag, reg, address);
reg 166 dev/pci/pci_map.c address1 = pci_conf_read(pc, tag, reg + 4);
reg 167 dev/pci/pci_map.c pci_conf_write(pc, tag, reg + 4, 0xffffffff);
reg 168 dev/pci/pci_map.c mask1 = pci_conf_read(pc, tag, reg + 4);
reg 169 dev/pci/pci_map.c pci_conf_write(pc, tag, reg + 4, address1);
reg 253 dev/pci/pci_map.c pci_io_find(pci_chipset_tag_t pc, pcitag_t pcitag, int reg,
reg 256 dev/pci/pci_map.c return (obsd_pci_io_find(pc, pcitag, reg, 0, iobasep, iosizep, 0));
reg 260 dev/pci/pci_map.c pci_mem_find(pci_chipset_tag_t pc, pcitag_t pcitag, int reg,
reg 263 dev/pci/pci_map.c return (obsd_pci_mem_find(pc, pcitag, reg, -1, membasep, memsizep,
reg 268 dev/pci/pci_map.c pci_mapreg_type(pci_chipset_tag_t pc, pcitag_t tag, int reg)
reg 270 dev/pci/pci_map.c return (_PCI_MAPREG_TYPEBITS(pci_conf_read(pc, tag, reg)));
reg 274 dev/pci/pci_map.c pci_mapreg_probe(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t *typep)
reg 284 dev/pci/pci_map.c address = pci_conf_read(pc, tag, reg);
reg 285 dev/pci/pci_map.c pci_conf_write(pc, tag, reg, 0xffffffff);
reg 286 dev/pci/pci_map.c mask = pci_conf_read(pc, tag, reg);
reg 287 dev/pci/pci_map.c pci_conf_write(pc, tag, reg, address);
reg 301 dev/pci/pci_map.c pci_mapreg_info(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type,
reg 306 dev/pci/pci_map.c return (obsd_pci_io_find(pc, tag, reg, type, basep, sizep,
reg 309 dev/pci/pci_map.c return (obsd_pci_mem_find(pc, tag, reg, type, basep, sizep,
reg 314 dev/pci/pci_map.c pci_mapreg_map(struct pci_attach_args *pa, int reg, pcireg_t type, int busflags,
reg 326 dev/pci/pci_map.c if ((rv = pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg, type,
reg 148 dev/pci/pciide.c pciide_pci_read(pci_chipset_tag_t pc, pcitag_t pa, int reg)
reg 150 dev/pci/pciide.c return (pci_conf_read(pc, pa, (reg & ~0x03)) >>
reg 151 dev/pci/pciide.c ((reg & 0x03) * 8) & 0xff);
reg 155 dev/pci/pciide.c pciide_pci_write(pci_chipset_tag_t pc, pcitag_t pa, int reg, u_int8_t val)
reg 159 dev/pci/pciide.c pcival = pci_conf_read(pc, pa, (reg & ~0x03));
reg 160 dev/pci/pciide.c pcival &= ~(0xff << ((reg & 0x03) * 8));
reg 161 dev/pci/pciide.c pcival |= (val << ((reg & 0x03) * 8));
reg 162 dev/pci/pciide.c pci_conf_write(pc, pa, (reg & ~0x03), pcival);
reg 2345 dev/pci/pciide.c u_int8_t reg, ich = 0;
reg 2388 dev/pci/pciide.c reg = pciide_pci_read(sc->sc_pc, sc->sc_tag, ICH5_SATA_MAP);
reg 2389 dev/pci/pciide.c if ((reg & ICH5_SATA_MAP_COMBINED) == 0) {
reg 2390 dev/pci/pciide.c reg = pciide_pci_read(pa->pa_pc, pa->pa_tag,
reg 2392 dev/pci/pciide.c reg |= ICH5_SATA_PI_PRI_NATIVE |
reg 2395 dev/pci/pciide.c ICH5_SATA_PI, reg);
reg 2400 dev/pci/pciide.c reg = pciide_pci_read(sc->sc_pc, sc->sc_tag, ICH5_SATA_MAP) &
reg 2402 dev/pci/pciide.c if (reg != ICH6_SATA_MAP_CMB_PRI &&
reg 2403 dev/pci/pciide.c reg != ICH6_SATA_MAP_CMB_SEC) {
reg 2404 dev/pci/pciide.c reg = pciide_pci_read(pa->pa_pc, pa->pa_tag,
reg 2406 dev/pci/pciide.c reg |= ICH5_SATA_PI_PRI_NATIVE |
reg 2410 dev/pci/pciide.c ICH5_SATA_PI, reg);
reg 2420 dev/pci/pciide.c reg = pciide_pci_read(sc->sc_pc, sc->sc_tag,
reg 2423 dev/pci/pciide.c ICH5_SATA_MAP, reg);
reg 3628 dev/pci/pciide.c int interface, i, reg;
reg 3657 dev/pci/pciide.c reg = 0xa2 + channel * 16;
reg 3659 dev/pci/pciide.c pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]);
reg 4190 dev/pci/pciide.c int chan, reg;
reg 4207 dev/pci/pciide.c for (reg = 0; reg < IDEDMA_NREGS; reg++) {
reg 4209 dev/pci/pciide.c if (size > (IDEDMA_SCH_OFFSET - reg))
reg 4210 dev/pci/pciide.c size = IDEDMA_SCH_OFFSET - reg;
reg 4213 dev/pci/pciide.c satalink_ba5_regmap[chan].ba5_IDEDMA_CMD + reg,
reg 4214 dev/pci/pciide.c size, &sl->regs[chan].dma_iohs[reg]) != 0) {
reg 4219 dev/pci/pciide.c chan].ba5_IDEDMA_CMD + reg,
reg 4326 dev/pci/pciide.c sii3114_read_reg(struct channel_softc *chp, enum wdc_regs reg)
reg 4332 dev/pci/pciide.c if (reg & _WDC_AUX)
reg 4334 dev/pci/pciide.c sl->regs[chp->channel].ctl_ioh, reg & _WDC_REGMASK));
reg 4337 dev/pci/pciide.c sl->regs[chp->channel].cmd_iohs[reg & _WDC_REGMASK], 0));
reg 4341 dev/pci/pciide.c sii3114_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int8_t val)
reg 4347 dev/pci/pciide.c if (reg & _WDC_AUX)
reg 4349 dev/pci/pciide.c sl->regs[chp->channel].ctl_ioh, reg & _WDC_REGMASK, val);
reg 4352 dev/pci/pciide.c sl->regs[chp->channel].cmd_iohs[reg & _WDC_REGMASK],
reg 6713 dev/pci/pciide.c pdc203xx_read_reg(struct channel_softc *chp, enum wdc_regs reg)
reg 6720 dev/pci/pciide.c if (reg & _WDC_AUX) {
reg 6722 dev/pci/pciide.c ps->regs[chp->channel].ctl_ioh, reg & _WDC_REGMASK));
reg 6725 dev/pci/pciide.c ps->regs[chp->channel].cmd_iohs[reg & _WDC_REGMASK], 0);
reg 6731 dev/pci/pciide.c pdc203xx_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int8_t val)
reg 6737 dev/pci/pciide.c if (reg & _WDC_AUX)
reg 6739 dev/pci/pciide.c ps->regs[chp->channel].ctl_ioh, reg & _WDC_REGMASK, val);
reg 6742 dev/pci/pciide.c ps->regs[chp->channel].cmd_iohs[reg & _WDC_REGMASK],
reg 6868 dev/pci/pciide.c opti_read_config(struct channel_softc *chp, int reg)
reg 6881 dev/pci/pciide.c rv = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, reg);
reg 6892 dev/pci/pciide.c opti_write_config(struct channel_softc *chp, int reg, u_int8_t val)
reg 6904 dev/pci/pciide.c bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, reg, val);
reg 7554 dev/pci/pciide.c svwsata_read_reg(struct channel_softc *chp, enum wdc_regs reg)
reg 7556 dev/pci/pciide.c if (reg & _WDC_AUX) {
reg 7558 dev/pci/pciide.c (reg & _WDC_REGMASK) << 2));
reg 7561 dev/pci/pciide.c (reg & _WDC_REGMASK) << 2));
reg 7566 dev/pci/pciide.c svwsata_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int8_t val)
reg 7568 dev/pci/pciide.c if (reg & _WDC_AUX) {
reg 7570 dev/pci/pciide.c (reg & _WDC_REGMASK) << 2, val);
reg 7573 dev/pci/pciide.c (reg & _WDC_REGMASK) << 2, val);
reg 7578 dev/pci/pciide.c svwsata_lba48_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int16_t val)
reg 7580 dev/pci/pciide.c if (reg & _WDC_AUX) {
reg 7582 dev/pci/pciide.c (reg & _WDC_REGMASK) << 2, val);
reg 7585 dev/pci/pciide.c (reg & _WDC_REGMASK) << 2, val);
reg 7661 dev/pci/pciide.c u_int32_t reg;
reg 7662 dev/pci/pciide.c reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL);
reg 7663 dev/pci/pciide.c reg &= ~ATP860_CTRL_INT;
reg 7664 dev/pci/pciide.c pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg);
reg 341 dev/pci/pciide_sii3112_reg.h ba5_read_4_ind(struct pciide_softc *sc, pcireg_t reg)
reg 347 dev/pci/pciide_sii3112_reg.h pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg);
reg 355 dev/pci/pciide_sii3112_reg.h ba5_read_4(struct pciide_softc *sc, bus_size_t reg)
reg 360 dev/pci/pciide_sii3112_reg.h return (bus_space_read_4(sl->ba5_st, sl->ba5_sh, reg));
reg 362 dev/pci/pciide_sii3112_reg.h return (ba5_read_4_ind(sc, reg));
reg 365 dev/pci/pciide_sii3112_reg.h #define BA5_READ_4(sc, chan, reg) \
reg 366 dev/pci/pciide_sii3112_reg.h ba5_read_4((sc), satalink_ba5_regmap[(chan)].reg)
reg 369 dev/pci/pciide_sii3112_reg.h ba5_write_4_ind(struct pciide_softc *sc, pcireg_t reg, uint32_t val)
reg 374 dev/pci/pciide_sii3112_reg.h pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg);
reg 380 dev/pci/pciide_sii3112_reg.h ba5_write_4(struct pciide_softc *sc, bus_size_t reg, uint32_t val)
reg 385 dev/pci/pciide_sii3112_reg.h bus_space_write_4(sl->ba5_st, sl->ba5_sh, reg, val);
reg 387 dev/pci/pciide_sii3112_reg.h ba5_write_4_ind(sc, reg, val);
reg 390 dev/pci/pciide_sii3112_reg.h #define BA5_WRITE_4(sc, chan, reg, val) \
reg 391 dev/pci/pciide_sii3112_reg.h ba5_write_4((sc), satalink_ba5_regmap[(chan)].reg, (val))
reg 409 dev/pci/pcireg.h #define _PCI_MAPREG_TYPEBITS(reg) \
reg 410 dev/pci/pcireg.h (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO ? \
reg 411 dev/pci/pcireg.h reg & PCI_MAPREG_TYPE_MASK : \
reg 412 dev/pci/pcireg.h reg & (PCI_MAPREG_TYPE_MASK|PCI_MAPREG_MEM_TYPE_MASK))
reg 93 dev/pci/pcscp.c #define READ_DMAREG(sc, reg) \
reg 94 dev/pci/pcscp.c bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
reg 95 dev/pci/pcscp.c #define WRITE_DMAREG(sc, reg, var) \
reg 96 dev/pci/pcscp.c bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (var))
reg 98 dev/pci/pcscp.c #define PCSCP_READ_REG(sc, reg) \
reg 99 dev/pci/pcscp.c bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg) << 2)
reg 100 dev/pci/pcscp.c #define PCSCP_WRITE_REG(sc, reg, val) \
reg 101 dev/pci/pcscp.c bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg) << 2, (val))
reg 333 dev/pci/pcscp.c pcscp_read_reg(struct ncr53c9x_softc *sc, int reg)
reg 337 dev/pci/pcscp.c return PCSCP_READ_REG(esc, reg);
reg 341 dev/pci/pcscp.c pcscp_write_reg(struct ncr53c9x_softc *sc, int reg, u_char v)
reg 345 dev/pci/pcscp.c PCSCP_WRITE_REG(esc, reg, v);
reg 133 dev/pci/safe.c #define WRITE_REG(sc,reg,val) \
reg 134 dev/pci/safe.c bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val)
reg 77 dev/pci/sdhc_pci.c int reg;
reg 117 dev/pci/sdhc_pci.c for (reg = SDHC_PCI_BAR_START + SDHC_PCI_FIRST_BAR(slotinfo) *
reg 119 dev/pci/sdhc_pci.c reg < SDHC_PCI_BAR_END && nslots > 0;
reg 120 dev/pci/sdhc_pci.c reg += sizeof(u_int32_t), nslots--) {
reg 122 dev/pci/sdhc_pci.c if (pci_mem_find(pa->pa_pc, pa->pa_tag, reg,
reg 126 dev/pci/sdhc_pci.c if (pci_mapreg_map(pa, reg, PCI_MAPREG_TYPE_MEM, 0,
reg 129 dev/pci/sdhc_pci.c sc->sc.sc_dev.dv_xname, reg);
reg 136 dev/pci/sdhc_pci.c sc->sc.sc_dev.dv_xname, reg);
reg 150 dev/pci/sdhc_pci.c pcireg_t id, reg;
reg 162 dev/pci/sdhc_pci.c reg = pci_conf_read(pa->pa_pc, tag, SDHC_PCI_GENERAL_CTL);
reg 163 dev/pci/sdhc_pci.c reg |= MMC_SD_DIS;
reg 164 dev/pci/sdhc_pci.c pci_conf_write(pa->pa_pc, tag, SDHC_PCI_GENERAL_CTL, reg);
reg 199 dev/pci/sv.c sv_write (sc, reg, val)
reg 201 dev/pci/sv.c u_int8_t reg, val;
reg 204 dev/pci/sv.c bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val);
reg 208 dev/pci/sv.c sv_read (sc, reg)
reg 210 dev/pci/sv.c u_int8_t reg;
reg 213 dev/pci/sv.c return (bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg));
reg 217 dev/pci/sv.c sv_read_indirect (sc, reg)
reg 219 dev/pci/sv.c u_int8_t reg;
reg 226 dev/pci/sv.c iaddr |= (reg & SV_IADDR_MASK);
reg 233 dev/pci/sv.c sv_write_indirect (sc, reg, val)
reg 235 dev/pci/sv.c u_int8_t reg, val;
reg 239 dev/pci/sv.c if (reg > 0x3f) {
reg 245 dev/pci/sv.c if (reg == SV_DMA_DATA_FORMAT)
reg 251 dev/pci/sv.c iaddr |= (reg & SV_IADDR_MASK);
reg 283 dev/pci/sv.c u_int8_t reg;
reg 344 dev/pci/sv.c reg = sv_read(sc, SV_CODEC_CONTROL);
reg 345 dev/pci/sv.c reg |= SV_CTL_RESET;
reg 346 dev/pci/sv.c sv_write(sc, SV_CODEC_CONTROL, reg);
reg 349 dev/pci/sv.c reg = sv_read(sc, SV_CODEC_CONTROL);
reg 350 dev/pci/sv.c reg &= ~SV_CTL_RESET;
reg 351 dev/pci/sv.c reg |= SV_CTL_INTA | SV_CTL_ENHANCED;
reg 354 dev/pci/sv.c sv_write(sc, SV_CODEC_CONTROL, reg);
reg 358 dev/pci/sv.c sv_write(sc, SV_CODEC_CONTROL, reg);
reg 363 dev/pci/sv.c reg = sv_read(sc, SV_CODEC_INTMASK);
reg 364 dev/pci/sv.c reg &= ~(SV_INTMASK_DMAA | SV_INTMASK_DMAC);
reg 365 dev/pci/sv.c reg |= SV_INTMASK_UD | SV_INTMASK_SINT | SV_INTMASK_MIDI;
reg 366 dev/pci/sv.c sv_write(sc, SV_CODEC_INTMASK, reg);
reg 512 dev/pci/sv.c u_int8_t reg;
reg 574 dev/pci/sv.c reg = sv_read(sc, SV_CODEC_INTMASK);
reg 575 dev/pci/sv.c reg &= ~(SV_INTMASK_DMAA | SV_INTMASK_DMAC);
reg 576 dev/pci/sv.c reg |= SV_INTMASK_UD | SV_INTMASK_SINT | SV_INTMASK_MIDI;
reg 577 dev/pci/sv.c sv_write(sc, SV_CODEC_INTMASK, reg);
reg 671 dev/pci/sv.c u_int8_t reg;
reg 722 dev/pci/sv.c reg = sv_read_indirect(sc, SV_DMA_DATA_FORMAT);
reg 723 dev/pci/sv.c reg &= ~(SV_DMAA_FORMAT16 | SV_DMAC_FORMAT16 | SV_DMAA_STEREO |
reg 725 dev/pci/sv.c reg |= (mode);
reg 726 dev/pci/sv.c sv_write_indirect(sc, SV_DMA_DATA_FORMAT, reg);
reg 1143 dev/pci/sv.c u_int8_t reg;
reg 1156 dev/pci/sv.c reg = sv_read_indirect(sc, ports[idx].l_port);
reg 1158 dev/pci/sv.c reg |= SV_MUTE_BIT;
reg 1160 dev/pci/sv.c reg &= ~SV_MUTE_BIT;
reg 1161 dev/pci/sv.c sv_write_indirect(sc, ports[idx].l_port, reg);
reg 1164 dev/pci/sv.c reg = sv_read_indirect(sc, ports[idx].r_port);
reg 1166 dev/pci/sv.c reg |= SV_MUTE_BIT;
reg 1168 dev/pci/sv.c reg &= ~SV_MUTE_BIT;
reg 1169 dev/pci/sv.c sv_write_indirect(sc, ports[idx].r_port, reg);
reg 1195 dev/pci/sv.c reg = sv_read_indirect(sc, ports[idx].l_port);
reg 1196 dev/pci/sv.c reg &= ~(ports[idx].mask);
reg 1198 dev/pci/sv.c reg |= lval;
reg 1199 dev/pci/sv.c sv_write_indirect(sc, ports[idx].l_port, reg);
reg 1202 dev/pci/sv.c reg = sv_read_indirect(sc, ports[idx].r_port);
reg 1203 dev/pci/sv.c reg &= ~(ports[idx].mask);
reg 1206 dev/pci/sv.c reg |= rval;
reg 1208 dev/pci/sv.c sv_write_indirect(sc, ports[idx].r_port, reg);
reg 1232 dev/pci/sv.c reg = sv_read_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL);
reg 1233 dev/pci/sv.c reg &= ~SV_REC_SOURCE_MASK;
reg 1234 dev/pci/sv.c reg |= (((cp->un.ord) << SV_REC_SOURCE_SHIFT) & SV_REC_SOURCE_MASK);
reg 1235 dev/pci/sv.c sv_write_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL, reg);
reg 1237 dev/pci/sv.c reg = sv_read_indirect(sc, SV_RIGHT_ADC_INPUT_CONTROL);
reg 1238 dev/pci/sv.c reg &= ~SV_REC_SOURCE_MASK;
reg 1239 dev/pci/sv.c reg |= (((cp->un.ord) << SV_REC_SOURCE_SHIFT) & SV_REC_SOURCE_MASK);
reg 1240 dev/pci/sv.c sv_write_indirect(sc, SV_RIGHT_ADC_INPUT_CONTROL, reg);
reg 1256 dev/pci/sv.c reg = sv_read_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL);
reg 1257 dev/pci/sv.c reg &= ~SV_REC_GAIN_MASK;
reg 1258 dev/pci/sv.c reg |= val;
reg 1259 dev/pci/sv.c sv_write_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL, reg);
reg 1261 dev/pci/sv.c reg = sv_read_indirect(sc, SV_RIGHT_ADC_INPUT_CONTROL);
reg 1262 dev/pci/sv.c reg &= ~SV_REC_GAIN_MASK;
reg 1263 dev/pci/sv.c reg |= val;
reg 1264 dev/pci/sv.c sv_write_indirect(sc, SV_RIGHT_ADC_INPUT_CONTROL, reg);
reg 1274 dev/pci/sv.c reg = sv_read_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL);
reg 1276 dev/pci/sv.c reg |= SV_MIC_BOOST_BIT;
reg 1278 dev/pci/sv.c reg &= ~SV_MIC_BOOST_BIT;
reg 1281 dev/pci/sv.c sv_write_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL, reg);
reg 1288 dev/pci/sv.c reg = sv_read_indirect(sc, SV_SRS_SPACE_CONTROL);
reg 1290 dev/pci/sv.c reg &= ~SV_SRS_SPACE_ONOFF;
reg 1292 dev/pci/sv.c reg |= SV_SRS_SPACE_ONOFF;
reg 1295 dev/pci/sv.c sv_write_indirect(sc, SV_SRS_SPACE_CONTROL, reg);
reg 1309 dev/pci/sv.c u_int8_t reg;
reg 1321 dev/pci/sv.c reg = sv_read_indirect(sc, ports[idx].l_port);
reg 1322 dev/pci/sv.c cp->un.ord = ((reg & SV_MUTE_BIT) ? 1 : 0);
reg 1337 dev/pci/sv.c reg = sv_read_indirect(sc, ports[idx].l_port);
reg 1338 dev/pci/sv.c reg &= ports[idx].mask;
reg 1340 dev/pci/sv.c val = AUDIO_MAX_GAIN - ((reg * AUDIO_MAX_GAIN) / ports[idx].mask);
reg 1345 dev/pci/sv.c reg = sv_read_indirect(sc, ports[idx].r_port);
reg 1346 dev/pci/sv.c reg &= ports[idx].mask;
reg 1348 dev/pci/sv.c val = AUDIO_MAX_GAIN - ((reg * AUDIO_MAX_GAIN) / ports[idx].mask);
reg 1362 dev/pci/sv.c reg = sv_read_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL);
reg 1363 dev/pci/sv.c cp->un.ord = ((reg & SV_REC_SOURCE_MASK) >> SV_REC_SOURCE_SHIFT);
reg 1374 dev/pci/sv.c reg = sv_read_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL) & SV_REC_GAIN_MASK;
reg 1376 dev/pci/sv.c (((unsigned int)reg) * AUDIO_MAX_GAIN) / SV_REC_GAIN_MASK;
reg 1384 dev/pci/sv.c reg = sv_read_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL);
reg 1385 dev/pci/sv.c cp->un.ord = ((reg & SV_MIC_BOOST_BIT) ? 1 : 0);
reg 1394 dev/pci/sv.c reg = sv_read_indirect(sc, SV_SRS_SPACE_CONTROL);
reg 1396 dev/pci/sv.c cp->un.ord = ((reg & SV_SRS_SPACE_ONOFF) ? 0 : 1);
reg 678 dev/pci/tga.c u_int32_t reg;
reg 680 dev/pci/tga.c reg = TGARREG(dc, TGA_REG_SISR);
reg 681 dev/pci/tga.c if (( reg & 0x00010001) != 0x00010001) {
reg 683 dev/pci/tga.c if ((reg & 0x1f) != 0) {
reg 685 dev/pci/tga.c TGAWREG(dc, TGA_REG_SISR, (reg & 0x1f));
reg 140 dev/pci/tgavar.h #define TGARREG(dc,reg) (bus_space_read_4((dc)->dc_memt, (dc)->dc_regs, \
reg 141 dev/pci/tgavar.h (reg) << 2))
reg 144 dev/pci/tgavar.h #define TGAWREG(dc,reg,val) bus_space_write_4((dc)->dc_memt, (dc)->dc_regs, \
reg 145 dev/pci/tgavar.h (reg) << 2, (val))
reg 148 dev/pci/tgavar.h #define TGAWALREG(dc,reg,alias,val) bus_space_write_4( \
reg 150 dev/pci/tgavar.h ((alias) * TGA_CREGS_ALIAS) + ((reg) << 2), \
reg 154 dev/pci/tgavar.h #define TGAREGWB(dc,reg, nregs) bus_space_barrier( \
reg 156 dev/pci/tgavar.h ((reg) << 2), 4 * (nregs), BUS_SPACE_BARRIER_WRITE)
reg 159 dev/pci/tgavar.h #define TGAREGRB(dc,reg, nregs) bus_space_barrier( \
reg 161 dev/pci/tgavar.h ((reg) << 2), 4 * (nregs), BUS_SPACE_BARRIER_READ)
reg 164 dev/pci/tgavar.h #define TGAREGRWB(dc,reg, nregs) bus_space_barrier( \
reg 166 dev/pci/tgavar.h ((reg) << 2), 4 * (nregs), \
reg 117 dev/pci/ubsec.c #define WRITE_REG(sc,reg,val) \
reg 118 dev/pci/ubsec.c bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val)
reg 154 dev/pci/vga_pci.c pcireg_t reg;
reg 162 dev/pci/vga_pci.c reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
reg 163 dev/pci/vga_pci.c reg |= PCI_COMMAND_MASTER_ENABLE;
reg 164 dev/pci/vga_pci.c pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg);
reg 579 dev/pci/yds.c pcireg_t reg;
reg 588 dev/pci/yds.c reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, YDS_PCI_LEGACY);
reg 589 dev/pci/yds.c reg &= ~0x8133c03f; /* these bits are out of interest */
reg 590 dev/pci/yds.c reg |= (YDS_PCI_EX_LEGACY_IMOD | YDS_PCI_LEGACY_FMEN |
reg 593 dev/pci/yds.c reg |= YDS_PCI_EX_LEGACY_SMOD_DISABLE;
reg 595 dev/pci/yds.c pci_conf_write(sc->sc_pc, sc->sc_pcitag, YDS_PCI_LEGACY, reg);
reg 604 dev/pci/yds.c YDS_PCI_LEGACY, reg | (i << (0+16)));
reg 621 dev/pci/yds.c reg |= (i << (0+16));
reg 627 dev/pci/yds.c reg &= ~YDS_PCI_LEGACY_FMEN;
reg 629 dev/pci/yds.c YDS_PCI_LEGACY, reg);
reg 641 dev/pci/yds.c YDS_PCI_LEGACY, reg | (i << (4+16)));
reg 657 dev/pci/yds.c reg |= (i << (4+16));
reg 663 dev/pci/yds.c reg &= ~(YDS_PCI_LEGACY_MEN | YDS_PCI_LEGACY_MIEN);
reg 665 dev/pci/yds.c YDS_PCI_LEGACY, reg);
reg 684 dev/pci/yds.c pcireg_t reg;
reg 729 dev/pci/yds.c reg = pci_conf_read(pc, pa->pa_tag, YDS_PCI_LEGACY);
reg 731 dev/pci/yds.c reg & YDS_PCI_LEGACY_LAD);
reg 855 dev/pci/yds.c yds_read_codec(sc_, reg, data)
reg 857 dev/pci/yds.c u_int8_t reg;
reg 862 dev/pci/yds.c YWRITE2(sc->sc, AC97_CMD_ADDR, AC97_CMD_READ | AC97_ID(sc->id) | reg);
reg 883 dev/pci/yds.c yds_write_codec(sc_, reg, data)
reg 885 dev/pci/yds.c u_int8_t reg;
reg 890 dev/pci/yds.c YWRITE2(sc->sc, AC97_CMD_ADDR, AC97_CMD_WRITE | AC97_ID(sc->id) | reg);
reg 911 dev/pci/yds.c pcireg_t reg;
reg 914 dev/pci/yds.c reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, YDS_PCI_DSCTRL);
reg 915 dev/pci/yds.c if (reg & 0x03) {
reg 917 dev/pci/yds.c YDS_PCI_DSCTRL, reg & ~0x03);
reg 919 dev/pci/yds.c YDS_PCI_DSCTRL, reg | 0x03);
reg 921 dev/pci/yds.c YDS_PCI_DSCTRL, reg & ~0x03);
reg 1820 dev/pci/yds.c u_int32_t reg;
reg 1840 dev/pci/yds.c reg = pci_conf_read(pc, sc->sc_pcitag, YDS_PCI_DSCTRL);
reg 1841 dev/pci/yds.c pci_conf_write(pc, sc->sc_pcitag, YDS_PCI_DSCTRL, reg | YDS_DSCTRL_WRST);
reg 1848 dev/pci/yds.c reg = pci_conf_read(pc, sc->sc_pcitag, YDS_PCI_DSCTRL);
reg 1850 dev/pci/yds.c reg & ~YDS_DSCTRL_CRST);
reg 1900 dev/pci/yds.c reg | YDS_DSCTRL_CRST);
reg 1903 dev/pci/yds.c reg & ~YDS_DSCTRL_CRST);
reg 402 dev/pcmcia/com_pcmcia.c int reg;
reg 406 dev/pcmcia/com_pcmcia.c reg = pcmcia_ccr_read(pf, PCMCIA_CCR_OPTION);
reg 407 dev/pcmcia/com_pcmcia.c if (reg & 0x08) {
reg 408 dev/pcmcia/com_pcmcia.c reg &= ~0x08;
reg 409 dev/pcmcia/com_pcmcia.c pcmcia_ccr_write(pf, PCMCIA_CCR_OPTION, reg);
reg 369 dev/pcmcia/esp_pcmcia.c esp_pcmcia_read_reg(sc, reg)
reg 371 dev/pcmcia/esp_pcmcia.c int reg;
reg 376 dev/pcmcia/esp_pcmcia.c v = bus_space_read_1(esc->sc_pcioh.iot, esc->sc_pcioh.ioh, reg);
reg 381 dev/pcmcia/esp_pcmcia.c esp_pcmcia_write_reg(sc, reg, val)
reg 383 dev/pcmcia/esp_pcmcia.c int reg;
reg 389 dev/pcmcia/esp_pcmcia.c if (reg == NCR_CMD && v == (NCRCMD_TRANS|NCRCMD_DMA))
reg 391 dev/pcmcia/esp_pcmcia.c bus_space_write_1(esc->sc_pcioh.iot, esc->sc_pcioh.ioh, reg, v);
reg 237 dev/pcmcia/if_ep_pcmcia.c int reg;
reg 241 dev/pcmcia/if_ep_pcmcia.c reg = pcmcia_ccr_read(pf, PCMCIA_CCR_OPTION);
reg 242 dev/pcmcia/if_ep_pcmcia.c if (reg & 0x08) {
reg 243 dev/pcmcia/if_ep_pcmcia.c reg &= ~0x08;
reg 244 dev/pcmcia/if_ep_pcmcia.c pcmcia_ccr_write(pf, PCMCIA_CCR_OPTION, reg);
reg 20 dev/pcmcia/if_malovar.h #define MALO_READ_1(sc, reg) \
reg 21 dev/pcmcia/if_malovar.h bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg))
reg 22 dev/pcmcia/if_malovar.h #define MALO_READ_2(sc, reg) \
reg 23 dev/pcmcia/if_malovar.h bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, (reg))
reg 24 dev/pcmcia/if_malovar.h #define MALO_READ_MULTI_2(sc, reg, off, size) \
reg 25 dev/pcmcia/if_malovar.h bus_space_read_raw_multi_2((sc)->sc_iot, (sc)->sc_ioh, (reg), (off), \
reg 27 dev/pcmcia/if_malovar.h #define MALO_WRITE_1(sc, reg, val) \
reg 28 dev/pcmcia/if_malovar.h bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
reg 29 dev/pcmcia/if_malovar.h #define MALO_WRITE_2(sc, reg, val) \
reg 30 dev/pcmcia/if_malovar.h bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
reg 31 dev/pcmcia/if_malovar.h #define MALO_WRITE_MULTI_2(sc, reg, off, size) \
reg 32 dev/pcmcia/if_malovar.h bus_space_write_raw_multi_2((sc)->sc_iot, (sc)->sc_ioh, (reg), (off), \
reg 929 dev/pcmcia/if_xe.c xe_mdi_read(self, phy, reg)
reg 932 dev/pcmcia/if_xe.c int reg;
reg 944 dev/pcmcia/if_xe.c xe_mdi_pulse_bits(sc, reg, 5); /* PHY register */
reg 954 dev/pcmcia/if_xe.c ("xe_mdi_read: phy %d reg %d -> %x\n", phy, reg, data));
reg 960 dev/pcmcia/if_xe.c xe_mdi_write(self, phy, reg, value)
reg 963 dev/pcmcia/if_xe.c int reg;
reg 974 dev/pcmcia/if_xe.c xe_mdi_pulse_bits(sc, reg, 5); /* PHY register */
reg 980 dev/pcmcia/if_xe.c ("xe_mdi_write: phy %d reg %d val %x\n", phy, reg, value));
reg 430 dev/pcmcia/pcmcia.c int reg;
reg 494 dev/pcmcia/pcmcia.c reg = (pf->cfe->number & PCMCIA_CCR_OPTION_CFINDEX);
reg 495 dev/pcmcia/pcmcia.c reg |= PCMCIA_CCR_OPTION_LEVIREQ;
reg 497 dev/pcmcia/pcmcia.c reg |= PCMCIA_CCR_OPTION_FUNC_ENABLE;
reg 499 dev/pcmcia/pcmcia.c reg |= PCMCIA_CCR_OPTION_ADDR_DECODE;
reg 501 dev/pcmcia/pcmcia.c reg |= PCMCIA_CCR_OPTION_IREQ_ENABLE;
reg 505 dev/pcmcia/pcmcia.c pcmcia_ccr_write(pf, PCMCIA_CCR_OPTION, reg);
reg 507 dev/pcmcia/pcmcia.c reg = 0;
reg 510 dev/pcmcia/pcmcia.c reg |= PCMCIA_CCR_STATUS_IOIS8;
reg 512 dev/pcmcia/pcmcia.c reg |= PCMCIA_CCR_STATUS_AUDIO;
reg 513 dev/pcmcia/pcmcia.c pcmcia_ccr_write(pf, PCMCIA_CCR_STATUS, reg);
reg 631 dev/pcmcia/pcmcia.c int reg;
reg 669 dev/pcmcia/pcmcia.c reg = pcmcia_ccr_read(pf, PCMCIA_CCR_OPTION);
reg 670 dev/pcmcia/pcmcia.c reg |= PCMCIA_CCR_OPTION_ADDR_DECODE;
reg 671 dev/pcmcia/pcmcia.c pcmcia_ccr_write(pf, PCMCIA_CCR_OPTION, reg);
reg 685 dev/pcmcia/pcmcia.c int s, ihcnt, hiipl, reg;
reg 767 dev/pcmcia/pcmcia.c reg = pcmcia_ccr_read(pf, PCMCIA_CCR_OPTION);
reg 768 dev/pcmcia/pcmcia.c reg |= PCMCIA_CCR_OPTION_IREQ_ENABLE;
reg 769 dev/pcmcia/pcmcia.c pcmcia_ccr_write(pf, PCMCIA_CCR_OPTION, reg);
reg 771 dev/pcmcia/pcmcia.c reg = pcmcia_ccr_read(pf, PCMCIA_CCR_STATUS);
reg 772 dev/pcmcia/pcmcia.c reg |= PCMCIA_CCR_STATUS_INTRACK;
reg 773 dev/pcmcia/pcmcia.c pcmcia_ccr_write(pf, PCMCIA_CCR_STATUS, reg);
reg 787 dev/pcmcia/pcmcia.c int s, reg, ihcnt, hiipl;
reg 828 dev/pcmcia/pcmcia.c reg = pcmcia_ccr_read(pf, PCMCIA_CCR_OPTION);
reg 829 dev/pcmcia/pcmcia.c reg &= ~PCMCIA_CCR_OPTION_IREQ_ENABLE;
reg 830 dev/pcmcia/pcmcia.c pcmcia_ccr_write(pf, PCMCIA_CCR_OPTION, reg);
reg 880 dev/pcmcia/pcmcia.c int reg, ret, ret2;
reg 895 dev/pcmcia/pcmcia.c reg = pcmcia_ccr_read(pf, PCMCIA_CCR_STATUS);
reg 896 dev/pcmcia/pcmcia.c if (reg & PCMCIA_CCR_STATUS_INTR) {
reg 900 dev/pcmcia/pcmcia.c reg = pcmcia_ccr_read(pf, PCMCIA_CCR_STATUS);
reg 903 dev/pcmcia/pcmcia.c reg, reg & ~PCMCIA_CCR_STATUS_INTR);
reg 906 dev/pcmcia/pcmcia.c reg & ~PCMCIA_CCR_STATUS_INTR);
reg 705 dev/pcmcia/pcmcia_cis.c u_int reg, dtype, dspeed;
reg 707 dev/pcmcia/pcmcia_cis.c reg = pcmcia_tuple_read_1(tuple, 0);
reg 708 dev/pcmcia/pcmcia_cis.c dtype = reg & PCMCIA_DTYPE_MASK;
reg 709 dev/pcmcia/pcmcia_cis.c dspeed = reg & PCMCIA_DSPEED_MASK;
reg 870 dev/pcmcia/pcmcia_cis.c u_int reg, rasz, rmsz, rfsz;
reg 873 dev/pcmcia/pcmcia_cis.c reg = pcmcia_tuple_read_1(tuple, 0);
reg 874 dev/pcmcia/pcmcia_cis.c rasz = 1 + ((reg & PCMCIA_TPCC_RASZ_MASK) >>
reg 876 dev/pcmcia/pcmcia_cis.c rmsz = 1 + ((reg & PCMCIA_TPCC_RMSZ_MASK) >>
reg 878 dev/pcmcia/pcmcia_cis.c rfsz = ((reg & PCMCIA_TPCC_RFSZ_MASK) >>
reg 933 dev/pcmcia/pcmcia_cis.c u_int reg, reg2;
reg 940 dev/pcmcia/pcmcia_cis.c reg = pcmcia_tuple_read_1(tuple, idx);
reg 942 dev/pcmcia/pcmcia_cis.c intface = reg & PCMCIA_TPCE_INDX_INTFACE;
reg 943 dev/pcmcia/pcmcia_cis.c def = reg & PCMCIA_TPCE_INDX_DEFAULT;
reg 944 dev/pcmcia/pcmcia_cis.c num = reg & PCMCIA_TPCE_INDX_NUM_MASK;
reg 1021 dev/pcmcia/pcmcia_cis.c reg = pcmcia_tuple_read_1(tuple, idx);
reg 1027 dev/pcmcia/pcmcia_cis.c if (reg & PCMCIA_TPCE_IF_MWAIT)
reg 1029 dev/pcmcia/pcmcia_cis.c if (reg & PCMCIA_TPCE_IF_RDYBSY)
reg 1031 dev/pcmcia/pcmcia_cis.c if (reg & PCMCIA_TPCE_IF_WP)
reg 1033 dev/pcmcia/pcmcia_cis.c if (reg & PCMCIA_TPCE_IF_BVD)
reg 1035 dev/pcmcia/pcmcia_cis.c cfe->iftype = reg & PCMCIA_TPCE_IF_IFTYPE;
reg 1037 dev/pcmcia/pcmcia_cis.c reg = pcmcia_tuple_read_1(tuple, idx);
reg 1040 dev/pcmcia/pcmcia_cis.c power = reg & PCMCIA_TPCE_FS_POWER_MASK;
reg 1041 dev/pcmcia/pcmcia_cis.c timing = reg & PCMCIA_TPCE_FS_TIMING;
reg 1042 dev/pcmcia/pcmcia_cis.c iospace = reg & PCMCIA_TPCE_FS_IOSPACE;
reg 1043 dev/pcmcia/pcmcia_cis.c irq = reg & PCMCIA_TPCE_FS_IRQ;
reg 1044 dev/pcmcia/pcmcia_cis.c memspace = reg & PCMCIA_TPCE_FS_MEMSPACE_MASK;
reg 1045 dev/pcmcia/pcmcia_cis.c misc = reg & PCMCIA_TPCE_FS_MISC;
reg 1051 dev/pcmcia/pcmcia_cis.c reg = pcmcia_tuple_read_1(tuple, idx);
reg 1056 dev/pcmcia/pcmcia_cis.c if ((reg >> j) & 0x01) {
reg 1074 dev/pcmcia/pcmcia_cis.c reg = pcmcia_tuple_read_1(tuple, idx);
reg 1077 dev/pcmcia/pcmcia_cis.c if ((reg & PCMCIA_TPCE_TD_RESERVED_MASK) !=
reg 1080 dev/pcmcia/pcmcia_cis.c if ((reg & PCMCIA_TPCE_TD_RDYBSY_MASK) !=
reg 1083 dev/pcmcia/pcmcia_cis.c if ((reg & PCMCIA_TPCE_TD_WAIT_MASK) !=
reg 1094 dev/pcmcia/pcmcia_cis.c reg = pcmcia_tuple_read_1(tuple, idx);
reg 1099 dev/pcmcia/pcmcia_cis.c if (reg & PCMCIA_TPCE_IO_BUSWIDTH_8BIT)
reg 1101 dev/pcmcia/pcmcia_cis.c if (reg & PCMCIA_TPCE_IO_BUSWIDTH_16BIT)
reg 1104 dev/pcmcia/pcmcia_cis.c reg & PCMCIA_TPCE_IO_IOADDRLINES_MASK;
reg 1106 dev/pcmcia/pcmcia_cis.c if (reg & PCMCIA_TPCE_IO_HASRANGE) {
reg 1107 dev/pcmcia/pcmcia_cis.c reg = pcmcia_tuple_read_1(tuple, idx);
reg 1110 dev/pcmcia/pcmcia_cis.c cfe->num_iospace = 1 + (reg &
reg 1123 dev/pcmcia/pcmcia_cis.c switch (reg & PCMCIA_TPCE_IO_RANGE_ADDRSIZE_MASK) {
reg 1140 dev/pcmcia/pcmcia_cis.c switch (reg &
reg 1175 dev/pcmcia/pcmcia_cis.c reg = pcmcia_tuple_read_1(tuple, idx);
reg 1181 dev/pcmcia/pcmcia_cis.c if (reg & PCMCIA_TPCE_IR_SHARE)
reg 1183 dev/pcmcia/pcmcia_cis.c if (reg & PCMCIA_TPCE_IR_PULSE)
reg 1185 dev/pcmcia/pcmcia_cis.c if (reg & PCMCIA_TPCE_IR_LEVEL)
reg 1188 dev/pcmcia/pcmcia_cis.c if (reg & PCMCIA_TPCE_IR_HASMASK) {
reg 1199 dev/pcmcia/pcmcia_cis.c (1 << (reg & PCMCIA_TPCE_IR_IRQ));
reg 1232 dev/pcmcia/pcmcia_cis.c reg = pcmcia_tuple_read_1(tuple, idx);
reg 1235 dev/pcmcia/pcmcia_cis.c cfe->num_memspace = (reg &
reg 1248 dev/pcmcia/pcmcia_cis.c ((reg & PCMCIA_TPCE_MS_LENGTH_SIZE_MASK) >>
reg 1251 dev/pcmcia/pcmcia_cis.c ((reg & PCMCIA_TPCE_MS_CARDADDR_SIZE_MASK) >>
reg 1254 dev/pcmcia/pcmcia_cis.c (reg & PCMCIA_TPCE_MS_HOSTADDR) ? cardaddrsize : 0;
reg 1301 dev/pcmcia/pcmcia_cis.c reg = pcmcia_tuple_read_1(tuple, idx);
reg 1307 dev/pcmcia/pcmcia_cis.c if (reg & PCMCIA_TPCE_MI_PWRDOWN)
reg 1309 dev/pcmcia/pcmcia_cis.c if (reg & PCMCIA_TPCE_MI_READONLY)
reg 1311 dev/pcmcia/pcmcia_cis.c if (reg & PCMCIA_TPCE_MI_AUDIO)
reg 1313 dev/pcmcia/pcmcia_cis.c cfe->maxtwins = reg & PCMCIA_TPCE_MI_MAXTWINS;
reg 1315 dev/pcmcia/pcmcia_cis.c while (reg & PCMCIA_TPCE_MI_EXT) {
reg 1316 dev/pcmcia/pcmcia_cis.c reg = pcmcia_tuple_read_1(tuple, idx);
reg 419 dev/sbus/agten.c ibm561_write(struct agten_softc *sc, u_int32_t reg, u_int32_t value)
reg 425 dev/sbus/agten.c *(volatile u_int32_t *)(sc->sc_p9100 + P9100_RAMDAC_REGISTER(reg)) =
reg 1298 dev/sbus/be.c be_mii_readreg(struct device *self, int phy, int reg)
reg 1310 dev/sbus/be.c be_mii_sendbits(sc, phy, reg, 5);
reg 1326 dev/sbus/be.c be_mii_writereg(struct device *self, int phy, int reg, int val)
reg 1338 dev/sbus/be.c be_mii_sendbits(sc, phy, reg, 5);
reg 92 dev/sbus/bwtwo.c #define FBC_READ(sc, reg) \
reg 93 dev/sbus/bwtwo.c bus_space_read_1((sc)->sc_bustag, (sc)->sc_ctrl_regs, (reg))
reg 94 dev/sbus/bwtwo.c #define FBC_WRITE(sc, reg, val) \
reg 95 dev/sbus/bwtwo.c bus_space_write_1((sc)->sc_bustag, (sc)->sc_ctrl_regs, (reg), (val))
reg 314 dev/sbus/cgsixreg.h #define BT_WRITE(sc, reg, val) \
reg 315 dev/sbus/cgsixreg.h bus_space_write_4((sc)->sc_bustag, (sc)->sc_bt_regs, (reg), (val))
reg 316 dev/sbus/cgsixreg.h #define BT_READ(sc, reg) \
reg 317 dev/sbus/cgsixreg.h bus_space_read_4((sc)->sc_bustag, (sc)->sc_bt_regs, (reg))
reg 318 dev/sbus/cgsixreg.h #define BT_BARRIER(sc,reg,flags) \
reg 319 dev/sbus/cgsixreg.h bus_space_barrier((sc)->sc_bustag, (sc)->sc_bt_regs, (reg), \
reg 75 dev/sbus/cgthree.c #define BT_WRITE(sc, reg, val) \
reg 76 dev/sbus/cgthree.c bus_space_write_4((sc)->sc_bustag, (sc)->sc_ctrl_regs, (reg), (val))
reg 77 dev/sbus/cgthree.c #define BT_READ(sc, reg) \
reg 78 dev/sbus/cgthree.c bus_space_read_4((sc)->sc_bustag, (sc)->sc_ctrl_regs, (reg))
reg 79 dev/sbus/cgthree.c #define BT_BARRIER(sc,reg,flags) \
reg 80 dev/sbus/cgthree.c bus_space_barrier((sc)->sc_bustag, (sc)->sc_ctrl_regs, (reg), \
reg 114 dev/sbus/cgthree.c #define FBC_READ(sc, reg) \
reg 115 dev/sbus/cgthree.c bus_space_read_1((sc)->sc_bustag, (sc)->sc_ctrl_regs, (reg))
reg 116 dev/sbus/cgthree.c #define FBC_WRITE(sc, reg, val) \
reg 117 dev/sbus/cgthree.c bus_space_write_1((sc)->sc_bustag, (sc)->sc_ctrl_regs, (reg), (val))
reg 1318 dev/sbus/cs4231.c u_int8_t reg, status;
reg 1339 dev/sbus/cs4231.c reg = cs4231_read(sc, CS_IRQ_STATUS);
reg 1340 dev/sbus/cs4231.c if (reg & CS_AFS_PI) {
reg 1344 dev/sbus/cs4231.c if (reg & CS_AFS_CI) {
reg 580 dev/sbus/esp_sbus.c esp_read_reg(struct ncr53c9x_softc *sc, int reg)
reg 585 dev/sbus/esp_sbus.c v = bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg * 4);
reg 587 dev/sbus/esp_sbus.c if (esp_sbus_debug && (reg < 0x10) && esp__read_regnames[reg].r_flag)
reg 588 dev/sbus/esp_sbus.c printf("RD:%x <%s> %x\n", reg * 4,
reg 589 dev/sbus/esp_sbus.c ((unsigned)reg < 0x10) ? esp__read_regnames[reg].r_name : "<***>", v);
reg 595 dev/sbus/esp_sbus.c esp_write_reg(struct ncr53c9x_softc *sc, int reg, u_char v)
reg 600 dev/sbus/esp_sbus.c if (esp_sbus_debug && (reg < 0x10) && esp__write_regnames[reg].r_flag)
reg 601 dev/sbus/esp_sbus.c printf("WR:%x <%s> %x\n", reg * 4,
reg 602 dev/sbus/esp_sbus.c ((unsigned)reg < 0x10) ? esp__write_regnames[reg].r_name : "<***>", v);
reg 604 dev/sbus/esp_sbus.c bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg * 4, v);
reg 608 dev/sbus/esp_sbus.c esp_rdreg1(struct ncr53c9x_softc *sc, int reg)
reg 612 dev/sbus/esp_sbus.c return (bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg));
reg 616 dev/sbus/esp_sbus.c esp_wrreg1(struct ncr53c9x_softc *sc, int reg, u_char v)
reg 620 dev/sbus/esp_sbus.c bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg, v);
reg 225 dev/sbus/magma.c #define CD1400_READ_REG(cd,reg) \
reg 226 dev/sbus/magma.c bus_space_read_1((cd)->cd_regt, (cd)->cd_regh, (reg))
reg 227 dev/sbus/magma.c #define CD1400_WRITE_REG(cd,reg,value) \
reg 228 dev/sbus/magma.c bus_space_write_1((cd)->cd_regt, (cd)->cd_regh, (reg), (value))
reg 35 dev/sdmmc/sbt.c #define CSR_READ_1(sc, reg) sdmmc_io_read_1((sc)->sc_sf, (reg))
reg 36 dev/sdmmc/sbt.c #define CSR_WRITE_1(sc, reg, val) sdmmc_io_write_1((sc)->sc_sf, (reg), (val))
reg 60 dev/sdmmc/sdhc.c #define HREAD1(hp, reg) \
reg 61 dev/sdmmc/sdhc.c (bus_space_read_1((hp)->iot, (hp)->ioh, (reg)))
reg 62 dev/sdmmc/sdhc.c #define HREAD2(hp, reg) \
reg 63 dev/sdmmc/sdhc.c (bus_space_read_2((hp)->iot, (hp)->ioh, (reg)))
reg 64 dev/sdmmc/sdhc.c #define HREAD4(hp, reg) \
reg 65 dev/sdmmc/sdhc.c (bus_space_read_4((hp)->iot, (hp)->ioh, (reg)))
reg 66 dev/sdmmc/sdhc.c #define HWRITE1(hp, reg, val) \
reg 67 dev/sdmmc/sdhc.c bus_space_write_1((hp)->iot, (hp)->ioh, (reg), (val))
reg 68 dev/sdmmc/sdhc.c #define HWRITE2(hp, reg, val) \
reg 69 dev/sdmmc/sdhc.c bus_space_write_2((hp)->iot, (hp)->ioh, (reg), (val))
reg 70 dev/sdmmc/sdhc.c #define HWRITE4(hp, reg, val) \
reg 71 dev/sdmmc/sdhc.c bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val))
reg 72 dev/sdmmc/sdhc.c #define HCLR1(hp, reg, bits) \
reg 73 dev/sdmmc/sdhc.c HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits))
reg 74 dev/sdmmc/sdhc.c #define HCLR2(hp, reg, bits) \
reg 75 dev/sdmmc/sdhc.c HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits))
reg 76 dev/sdmmc/sdhc.c #define HSET1(hp, reg, bits) \
reg 77 dev/sdmmc/sdhc.c HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits))
reg 78 dev/sdmmc/sdhc.c #define HSET2(hp, reg, bits) \
reg 79 dev/sdmmc/sdhc.c HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits))
reg 55 dev/sdmmc/sdmmc_cis.c int reg;
reg 65 dev/sdmmc/sdmmc_cis.c reg = (int)sdmmc_cisptr(sf);
reg 66 dev/sdmmc/sdmmc_cis.c if (reg < SD_IO_CIS_START ||
reg 67 dev/sdmmc/sdmmc_cis.c reg >= (SD_IO_CIS_START+SD_IO_CIS_SIZE-16)) {
reg 68 dev/sdmmc/sdmmc_cis.c printf("%s: bad CIS ptr %#x\n", SDMMCDEVNAME(sf->sc), reg);
reg 73 dev/sdmmc/sdmmc_cis.c tplcode = sdmmc_io_read_1(sf, reg++);
reg 74 dev/sdmmc/sdmmc_cis.c tpllen = sdmmc_io_read_1(sf, reg++);
reg 80 dev/sdmmc/sdmmc_cis.c SDMMCDEVNAME(sf->sc), reg, tplcode, tpllen);
reg 89 dev/sdmmc/sdmmc_cis.c reg += tpllen;
reg 92 dev/sdmmc/sdmmc_cis.c cis->function = sdmmc_io_read_1(sf, reg);
reg 93 dev/sdmmc/sdmmc_cis.c reg += tpllen;
reg 99 dev/sdmmc/sdmmc_cis.c reg += tpllen;
reg 102 dev/sdmmc/sdmmc_cis.c cis->manufacturer = sdmmc_io_read_1(sf, reg++);
reg 103 dev/sdmmc/sdmmc_cis.c cis->manufacturer |= sdmmc_io_read_1(sf, reg++) << 8;
reg 104 dev/sdmmc/sdmmc_cis.c cis->product = sdmmc_io_read_1(sf, reg++);
reg 105 dev/sdmmc/sdmmc_cis.c cis->product |= sdmmc_io_read_1(sf, reg++) << 8;
reg 111 dev/sdmmc/sdmmc_cis.c reg += tpllen;
reg 117 dev/sdmmc/sdmmc_cis.c cis->cis1_major = sdmmc_io_read_1(sf, reg++);
reg 118 dev/sdmmc/sdmmc_cis.c cis->cis1_minor = sdmmc_io_read_1(sf, reg++);
reg 122 dev/sdmmc/sdmmc_cis.c ch = sdmmc_io_read_1(sf, reg + i);
reg 134 dev/sdmmc/sdmmc_cis.c reg += tpllen - 2;
reg 140 dev/sdmmc/sdmmc_cis.c reg += tpllen;
reg 340 dev/sdmmc/sdmmc_io.c int reg, u_char *datap, int arg)
reg 355 dev/sdmmc/sdmmc_io.c arg |= (reg & SD_ARG_CMD52_REG_MASK) <<
reg 380 dev/sdmmc/sdmmc_io.c int reg, u_char *datap, int datalen, int arg)
reg 397 dev/sdmmc/sdmmc_io.c arg |= (reg & SD_ARG_CMD53_REG_MASK) <<
reg 419 dev/sdmmc/sdmmc_io.c sdmmc_io_read_1(struct sdmmc_function *sf, int reg)
reg 423 dev/sdmmc/sdmmc_io.c (void)sdmmc_io_rw_direct(sf->sc, sf, reg, (u_char *)&data,
reg 429 dev/sdmmc/sdmmc_io.c sdmmc_io_write_1(struct sdmmc_function *sf, int reg, u_int8_t data)
reg 431 dev/sdmmc/sdmmc_io.c (void)sdmmc_io_rw_direct(sf->sc, sf, reg, (u_char *)&data,
reg 436 dev/sdmmc/sdmmc_io.c sdmmc_io_read_2(struct sdmmc_function *sf, int reg)
reg 440 dev/sdmmc/sdmmc_io.c (void)sdmmc_io_rw_extended(sf->sc, sf, reg, (u_char *)&data, 2,
reg 446 dev/sdmmc/sdmmc_io.c sdmmc_io_write_2(struct sdmmc_function *sf, int reg, u_int16_t data)
reg 448 dev/sdmmc/sdmmc_io.c (void)sdmmc_io_rw_extended(sf->sc, sf, reg, (u_char *)&data, 2,
reg 453 dev/sdmmc/sdmmc_io.c sdmmc_io_read_4(struct sdmmc_function *sf, int reg)
reg 457 dev/sdmmc/sdmmc_io.c (void)sdmmc_io_rw_extended(sf->sc, sf, reg, (u_char *)&data, 4,
reg 463 dev/sdmmc/sdmmc_io.c sdmmc_io_write_4(struct sdmmc_function *sf, int reg, u_int32_t data)
reg 465 dev/sdmmc/sdmmc_io.c (void)sdmmc_io_rw_extended(sf->sc, sf, reg, (u_char *)&data, 4,
reg 470 dev/sdmmc/sdmmc_io.c sdmmc_io_read_multi_1(struct sdmmc_function *sf, int reg, u_char *data,
reg 476 dev/sdmmc/sdmmc_io.c error = sdmmc_io_rw_extended(sf->sc, sf, reg, data,
reg 484 dev/sdmmc/sdmmc_io.c return sdmmc_io_rw_extended(sf->sc, sf, reg, data, datalen,
reg 489 dev/sdmmc/sdmmc_io.c sdmmc_io_write_multi_1(struct sdmmc_function *sf, int reg, u_char *data,
reg 495 dev/sdmmc/sdmmc_io.c error = sdmmc_io_rw_extended(sf->sc, sf, reg, data,
reg 503 dev/sdmmc/sdmmc_io.c return sdmmc_io_rw_extended(sf->sc, sf, reg, data, datalen,
reg 509 dev/sdmmc/sdmmc_io.c int reg, u_char *datap)
reg 511 dev/sdmmc/sdmmc_io.c return sdmmc_io_rw_direct(sc, sf, reg, datap,
reg 98 dev/tc/asc.c asc_read_reg(sc, reg)
reg 100 dev/tc/asc.c int reg;
reg 106 dev/tc/asc.c reg * sizeof(u_int32_t)) & 0xff;
reg 112 dev/tc/asc.c asc_write_reg(sc, reg, val)
reg 114 dev/tc/asc.c int reg;
reg 120 dev/tc/asc.c reg * sizeof(u_int32_t), val);
reg 268 dev/usb/if_aue.c #define AUE_SETBIT(sc, reg, x) \
reg 269 dev/usb/if_aue.c aue_csr_write_1(sc, reg, aue_csr_read_1(sc, reg) | (x))
reg 271 dev/usb/if_aue.c #define AUE_CLRBIT(sc, reg, x) \
reg 272 dev/usb/if_aue.c aue_csr_write_1(sc, reg, aue_csr_read_1(sc, reg) & ~(x))
reg 275 dev/usb/if_aue.c aue_csr_read_1(struct aue_softc *sc, int reg)
reg 287 dev/usb/if_aue.c USETW(req.wIndex, reg);
reg 294 dev/usb/if_aue.c sc->aue_dev.dv_xname, reg, usbd_errstr(err)));
reg 302 dev/usb/if_aue.c aue_csr_read_2(struct aue_softc *sc, int reg)
reg 314 dev/usb/if_aue.c USETW(req.wIndex, reg);
reg 321 dev/usb/if_aue.c sc->aue_dev.dv_xname, reg, usbd_errstr(err)));
reg 329 dev/usb/if_aue.c aue_csr_write_1(struct aue_softc *sc, int reg, int aval)
reg 342 dev/usb/if_aue.c USETW(req.wIndex, reg);
reg 349 dev/usb/if_aue.c sc->aue_dev.dv_xname, reg, usbd_errstr(err)));
reg 357 dev/usb/if_aue.c aue_csr_write_2(struct aue_softc *sc, int reg, int aval)
reg 370 dev/usb/if_aue.c USETW(req.wIndex, reg);
reg 377 dev/usb/if_aue.c sc->aue_dev.dv_xname, reg, usbd_errstr(err)));
reg 444 dev/usb/if_aue.c aue_miibus_readreg(struct device *dev, int phy, int reg)
reg 477 dev/usb/if_aue.c aue_csr_write_1(sc, AUE_PHY_CTL, reg | AUE_PHYCTL_READ);
reg 491 dev/usb/if_aue.c sc->aue_dev.dv_xname, __func__, phy, reg, val));
reg 498 dev/usb/if_aue.c aue_miibus_writereg(struct device *dev, int phy, int reg, int data)
reg 512 dev/usb/if_aue.c sc->aue_dev.dv_xname, __func__, phy, reg, data));
reg 517 dev/usb/if_aue.c aue_csr_write_1(sc, AUE_PHY_CTL, reg | AUE_PHYCTL_WRITE);
reg 264 dev/usb/if_axe.c axe_miibus_readreg(struct device *dev, int phy, int reg)
reg 281 dev/usb/if_axe.c DPRINTF(("axe_miibus_readreg: phy 0x%x reg 0x%x\n", phy, reg));
reg 296 dev/usb/if_axe.c err = axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, val);
reg 312 dev/usb/if_axe.c axe_miibus_writereg(struct device *dev, int phy, int reg, int val)
reg 325 dev/usb/if_axe.c err = axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, uval);
reg 157 dev/usb/if_cue.c #define CUE_SETBIT(sc, reg, x) \
reg 158 dev/usb/if_cue.c cue_csr_write_1(sc, reg, cue_csr_read_1(sc, reg) | (x))
reg 160 dev/usb/if_cue.c #define CUE_CLRBIT(sc, reg, x) \
reg 161 dev/usb/if_cue.c cue_csr_write_1(sc, reg, cue_csr_read_1(sc, reg) & ~(x))
reg 164 dev/usb/if_cue.c cue_csr_read_1(struct cue_softc *sc, int reg)
reg 176 dev/usb/if_cue.c USETW(req.wIndex, reg);
reg 183 dev/usb/if_cue.c sc->cue_dev.dv_xname, reg, usbd_errstr(err)));
reg 188 dev/usb/if_cue.c sc->cue_dev.dv_xname, reg, val));
reg 194 dev/usb/if_cue.c cue_csr_read_2(struct cue_softc *sc, int reg)
reg 206 dev/usb/if_cue.c USETW(req.wIndex, reg);
reg 212 dev/usb/if_cue.c sc->cue_dev.dv_xname, reg, UGETW(val)));
reg 216 dev/usb/if_cue.c sc->cue_dev.dv_xname, reg, usbd_errstr(err)));
reg 224 dev/usb/if_cue.c cue_csr_write_1(struct cue_softc *sc, int reg, int val)
reg 233 dev/usb/if_cue.c sc->cue_dev.dv_xname, reg, val));
reg 238 dev/usb/if_cue.c USETW(req.wIndex, reg);
reg 245 dev/usb/if_cue.c sc->cue_dev.dv_xname, reg, usbd_errstr(err)));
reg 250 dev/usb/if_cue.c sc->cue_dev.dv_xname, reg, cue_csr_read_1(sc, reg)));
reg 257 dev/usb/if_cue.c cue_csr_write_2(struct cue_softc *sc, int reg, int aval)
reg 268 dev/usb/if_cue.c sc->cue_dev.dv_xname, reg, aval));
reg 274 dev/usb/if_cue.c USETW(req.wIndex, reg);
reg 281 dev/usb/if_cue.c sc->cue_dev.dv_xname, reg, usbd_errstr(err)));
reg 170 dev/usb/if_ral.c uint16_t reg;
reg 177 dev/usb/if_ral.c uint8_t reg;
reg 1409 dev/usb/if_ral.c ural_read(struct ural_softc *sc, uint16_t reg)
reg 1418 dev/usb/if_ral.c USETW(req.wIndex, reg);
reg 1431 dev/usb/if_ral.c ural_read_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len)
reg 1439 dev/usb/if_ral.c USETW(req.wIndex, reg);
reg 1450 dev/usb/if_ral.c ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val)
reg 1458 dev/usb/if_ral.c USETW(req.wIndex, reg);
reg 1469 dev/usb/if_ral.c ural_write_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len)
reg 1477 dev/usb/if_ral.c USETW(req.wIndex, reg);
reg 1488 dev/usb/if_ral.c ural_bbp_write(struct ural_softc *sc, uint8_t reg, uint8_t val)
reg 1502 dev/usb/if_ral.c tmp = reg << 8 | val;
reg 1507 dev/usb/if_ral.c ural_bbp_read(struct ural_softc *sc, uint8_t reg)
reg 1512 dev/usb/if_ral.c val = RAL_BBP_WRITE | reg << 8;
reg 1527 dev/usb/if_ral.c ural_rf_write(struct ural_softc *sc, uint8_t reg, uint32_t val)
reg 1541 dev/usb/if_ral.c tmp = RAL_RF_BUSY | RAL_RF_20BIT | (val & 0xfffff) << 2 | (reg & 0x3);
reg 1546 dev/usb/if_ral.c sc->rf_regs[reg] = val;
reg 1548 dev/usb/if_ral.c DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff));
reg 1857 dev/usb/if_ral.c ural_bbp_write(sc, ural_def_bbp[i].reg, ural_def_bbp[i].val);
reg 1862 dev/usb/if_ral.c if (sc->bbp_prom[i].reg == 0xff)
reg 1864 dev/usb/if_ral.c ural_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);
reg 1935 dev/usb/if_ral.c ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val);
reg 115 dev/usb/if_ralvar.h uint8_t reg;
reg 188 dev/usb/if_rum.c uint32_t reg;
reg 195 dev/usb/if_rum.c uint8_t reg;
reg 1417 dev/usb/if_rum.c rum_read(struct rum_softc *sc, uint16_t reg)
reg 1421 dev/usb/if_rum.c rum_read_multi(sc, reg, &val, sizeof val);
reg 1427 dev/usb/if_rum.c rum_read_multi(struct rum_softc *sc, uint16_t reg, void *buf, int len)
reg 1435 dev/usb/if_rum.c USETW(req.wIndex, reg);
reg 1446 dev/usb/if_rum.c rum_write(struct rum_softc *sc, uint16_t reg, uint32_t val)
reg 1450 dev/usb/if_rum.c rum_write_multi(sc, reg, &tmp, sizeof tmp);
reg 1454 dev/usb/if_rum.c rum_write_multi(struct rum_softc *sc, uint16_t reg, void *buf, size_t len)
reg 1462 dev/usb/if_rum.c USETW(req.wIndex, reg);
reg 1473 dev/usb/if_rum.c rum_bbp_write(struct rum_softc *sc, uint8_t reg, uint8_t val)
reg 1487 dev/usb/if_rum.c tmp = RT2573_BBP_BUSY | (reg & 0x7f) << 8 | val;
reg 1492 dev/usb/if_rum.c rum_bbp_read(struct rum_softc *sc, uint8_t reg)
reg 1506 dev/usb/if_rum.c val = RT2573_BBP_BUSY | RT2573_BBP_READ | reg << 8;
reg 1521 dev/usb/if_rum.c rum_rf_write(struct rum_softc *sc, uint8_t reg, uint32_t val)
reg 1536 dev/usb/if_rum.c (reg & 3);
reg 1540 dev/usb/if_rum.c sc->rf_regs[reg] = val;
reg 1542 dev/usb/if_rum.c DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 3, val & 0xfffff));
reg 1906 dev/usb/if_rum.c if (sc->bbp_prom[i].reg == 0 || sc->bbp_prom[i].reg == 0xff)
reg 1908 dev/usb/if_rum.c DPRINTF(("BBP R%d=%02x\n", sc->bbp_prom[i].reg,
reg 1935 dev/usb/if_rum.c rum_bbp_write(sc, rum_def_bbp[i].reg, rum_def_bbp[i].val);
reg 1939 dev/usb/if_rum.c if (sc->bbp_prom[i].reg == 0 || sc->bbp_prom[i].reg == 0xff)
reg 1941 dev/usb/if_rum.c rum_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);
reg 1962 dev/usb/if_rum.c rum_write(sc, rum_def_mac[i].reg, rum_def_mac[i].val);
reg 2128 dev/usb/if_rum.c uint16_t reg = RT2573_MCU_CODE_BASE;
reg 2132 dev/usb/if_rum.c for (; size >= 4; reg += 4, ucode += 4, size -= 4)
reg 2133 dev/usb/if_rum.c rum_write(sc, reg, UGETDW(ucode));
reg 117 dev/usb/if_rumvar.h uint8_t reg;
reg 1041 dev/usb/if_uath.c uath_write_reg(struct uath_softc *sc, uint32_t reg, uint32_t val)
reg 1046 dev/usb/if_uath.c write.reg = htobe32(reg);
reg 1054 dev/usb/if_uath.c sc->sc_dev.dv_xname, reg);
reg 1060 dev/usb/if_uath.c uath_write_multi(struct uath_softc *sc, uint32_t reg, const void *data,
reg 1066 dev/usb/if_uath.c write.reg = htobe32(reg);
reg 1075 dev/usb/if_uath.c sc->sc_dev.dv_xname, len, reg);
reg 1081 dev/usb/if_uath.c uath_read_reg(struct uath_softc *sc, uint32_t reg, uint32_t *val)
reg 1086 dev/usb/if_uath.c reg = htobe32(reg);
reg 1087 dev/usb/if_uath.c error = uath_cmd_read(sc, UATH_CMD_READ_MAC, ®, sizeof reg, &read,
reg 1091 dev/usb/if_uath.c sc->sc_dev.dv_xname, betoh32(reg));
reg 1099 dev/usb/if_uath.c uath_read_eeprom(struct uath_softc *sc, uint32_t reg, void *odata)
reg 1104 dev/usb/if_uath.c reg = htobe32(reg);
reg 1105 dev/usb/if_uath.c error = uath_cmd_read(sc, UATH_CMD_READ_EEPROM, ®, sizeof reg,
reg 1109 dev/usb/if_uath.c sc->sc_dev.dv_xname, betoh32(reg));
reg 1653 dev/usb/if_uath.c uint32_t reg, val;
reg 1672 dev/usb/if_uath.c for (reg = 0x09; reg <= 0x24; reg++) {
reg 1673 dev/usb/if_uath.c if (reg == 0x0b || reg == 0x0c)
reg 1676 dev/usb/if_uath.c if ((error = uath_read_reg(sc, reg, &val)) != 0)
reg 1678 dev/usb/if_uath.c DPRINTFN(2, ("reg 0x%02x=0x%08x\n", reg, val));
reg 125 dev/usb/if_uathreg.h uint32_t reg;
reg 153 dev/usb/if_udav.c #define UDAV_SETBIT(sc, reg, x) \
reg 154 dev/usb/if_udav.c udav_csr_write1(sc, reg, udav_csr_read1(sc, reg) | (x))
reg 156 dev/usb/if_udav.c #define UDAV_CLRBIT(sc, reg, x) \
reg 157 dev/usb/if_udav.c udav_csr_write1(sc, reg, udav_csr_read1(sc, reg) & ~(x))
reg 1533 dev/usb/if_udav.c udav_miibus_readreg(struct device *dev, int phy, int reg)
reg 1545 dev/usb/if_udav.c sc->sc_dev.dv_xname, __func__, phy, reg));
reg 1566 dev/usb/if_udav.c UDAV_EPAR_PHY_ADR0 | (reg & UDAV_EPAR_EROA_MASK));
reg 1584 dev/usb/if_udav.c sc->sc_dev.dv_xname, __func__, phy, reg, data16));
reg 1590 dev/usb/if_udav.c udav_miibus_writereg(struct device *dev, int phy, int reg, int data)
reg 1601 dev/usb/if_udav.c sc->sc_dev.dv_xname, __func__, phy, reg, data));
reg 1622 dev/usb/if_udav.c UDAV_EPAR_PHY_ADR0 | (reg & UDAV_EPAR_EROA_MASK));
reg 147 dev/usb/if_url.c #define URL_SETBIT(sc, reg, x) \
reg 148 dev/usb/if_url.c url_csr_write_1(sc, reg, url_csr_read_1(sc, reg) | (x))
reg 150 dev/usb/if_url.c #define URL_SETBIT2(sc, reg, x) \
reg 151 dev/usb/if_url.c url_csr_write_2(sc, reg, url_csr_read_2(sc, reg) | (x))
reg 153 dev/usb/if_url.c #define URL_CLRBIT(sc, reg, x) \
reg 154 dev/usb/if_url.c url_csr_write_1(sc, reg, url_csr_read_1(sc, reg) & ~(x))
reg 156 dev/usb/if_url.c #define URL_CLRBIT2(sc, reg, x) \
reg 157 dev/usb/if_url.c url_csr_write_2(sc, reg, url_csr_read_2(sc, reg) & ~(x))
reg 428 dev/usb/if_url.c url_csr_read_1(struct url_softc *sc, int reg)
reg 438 dev/usb/if_url.c return (url_mem(sc, URL_CMD_READMEM, reg, &val, 1) ? 0 : val);
reg 443 dev/usb/if_url.c url_csr_read_2(struct url_softc *sc, int reg)
reg 454 dev/usb/if_url.c return (url_mem(sc, URL_CMD_READMEM, reg, &val, 2) ? 0 : UGETW(val));
reg 459 dev/usb/if_url.c url_csr_write_1(struct url_softc *sc, int reg, int aval)
reg 469 dev/usb/if_url.c return (url_mem(sc, URL_CMD_WRITEMEM, reg, &val, 1) ? -1 : 0);
reg 474 dev/usb/if_url.c url_csr_write_2(struct url_softc *sc, int reg, int aval)
reg 486 dev/usb/if_url.c return (url_mem(sc, URL_CMD_WRITEMEM, reg, &val, 2) ? -1 : 0);
reg 491 dev/usb/if_url.c url_csr_write_4(struct url_softc *sc, int reg, int aval)
reg 503 dev/usb/if_url.c return (url_mem(sc, URL_CMD_WRITEMEM, reg, &val, 4) ? -1 : 0);
reg 1421 dev/usb/if_url.c url_int_miibus_readreg(struct device *dev, int phy, int reg)
reg 1432 dev/usb/if_url.c sc->sc_dev.dv_xname, __func__, phy, reg));
reg 1451 dev/usb/if_url.c switch (reg) {
reg 1453 dev/usb/if_url.c reg = URL_BMCR;
reg 1456 dev/usb/if_url.c reg = URL_BMSR;
reg 1464 dev/usb/if_url.c reg = URL_ANAR;
reg 1467 dev/usb/if_url.c reg = URL_ANLP;
reg 1470 dev/usb/if_url.c reg = URL_MSR;
reg 1474 dev/usb/if_url.c sc->sc_dev.dv_xname, __func__, reg);
reg 1480 dev/usb/if_url.c if (reg == URL_MSR)
reg 1481 dev/usb/if_url.c val = url_csr_read_1(sc, reg);
reg 1483 dev/usb/if_url.c val = url_csr_read_2(sc, reg);
reg 1487 dev/usb/if_url.c sc->sc_dev.dv_xname, __func__, phy, reg, val));
reg 1494 dev/usb/if_url.c url_int_miibus_writereg(struct device *dev, int phy, int reg, int data)
reg 1504 dev/usb/if_url.c sc->sc_dev.dv_xname, __func__, phy, reg, data));
reg 1523 dev/usb/if_url.c switch (reg) {
reg 1525 dev/usb/if_url.c reg = URL_BMCR;
reg 1528 dev/usb/if_url.c reg = URL_BMSR;
reg 1535 dev/usb/if_url.c reg = URL_ANAR;
reg 1538 dev/usb/if_url.c reg = URL_ANLP;
reg 1541 dev/usb/if_url.c reg = URL_MSR;
reg 1545 dev/usb/if_url.c sc->sc_dev.dv_xname, __func__, reg);
reg 1550 dev/usb/if_url.c if (reg == URL_MSR)
reg 1551 dev/usb/if_url.c url_csr_write_1(sc, reg, data);
reg 1553 dev/usb/if_url.c url_csr_write_2(sc, reg, data);
reg 1580 dev/usb/if_url.c url_ext_miibus_redreg(struct device *dev, int phy, int reg)
reg 1586 dev/usb/if_url.c sc->sc_dev.dv_xname, __func__, phy, reg));
reg 1605 dev/usb/if_url.c (reg | URL_PHYCNT_PHYOWN) & ~URL_PHYCNT_RWCR);
reg 1617 dev/usb/if_url.c sc->sc_dev.dv_xname, __func__, phy, reg, val));
reg 1624 dev/usb/if_url.c url_ext_miibus_writereg(struct device *dev, int phy, int reg, int data)
reg 1629 dev/usb/if_url.c sc->sc_dev.dv_xname, __func__, phy, reg, data));
reg 1643 dev/usb/if_url.c url_csr_write_1(sc, URL_PHYCNT, reg | URL_PHYCNT_RWCR); /* Write */
reg 813 dev/usb/if_zyd.c zyd_read16(struct zyd_softc *sc, uint16_t reg, uint16_t *val)
reg 818 dev/usb/if_zyd.c reg = htole16(reg);
reg 819 dev/usb/if_zyd.c error = zyd_cmd(sc, ZYD_CMD_IORD, ®, sizeof reg, &tmp, sizeof tmp,
reg 827 dev/usb/if_zyd.c zyd_read32(struct zyd_softc *sc, uint16_t reg, uint32_t *val)
reg 833 dev/usb/if_zyd.c regs[0] = htole16(ZYD_REG32_HI(reg));
reg 834 dev/usb/if_zyd.c regs[1] = htole16(ZYD_REG32_LO(reg));
reg 843 dev/usb/if_zyd.c zyd_write16(struct zyd_softc *sc, uint16_t reg, uint16_t val)
reg 847 dev/usb/if_zyd.c pair.reg = htole16(reg);
reg 854 dev/usb/if_zyd.c zyd_write32(struct zyd_softc *sc, uint16_t reg, uint32_t val)
reg 858 dev/usb/if_zyd.c pair[0].reg = htole16(ZYD_REG32_HI(reg));
reg 860 dev/usb/if_zyd.c pair[1].reg = htole16(ZYD_REG32_LO(reg));
reg 921 dev/usb/if_zyd.c error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
reg 974 dev/usb/if_zyd.c error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
reg 999 dev/usb/if_zyd.c error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
reg 1062 dev/usb/if_zyd.c error = zyd_write16(sc, phyini_1[i].reg, phyini_1[i].val);
reg 1073 dev/usb/if_zyd.c error = zyd_write16(sc, phyini_2[i].reg, phyini_2[i].val);
reg 1084 dev/usb/if_zyd.c error = zyd_write16(sc, phyini_3[i].reg, phyini_3[i].val);
reg 1158 dev/usb/if_zyd.c error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
reg 1227 dev/usb/if_zyd.c error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
reg 1276 dev/usb/if_zyd.c error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
reg 1323 dev/usb/if_zyd.c error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
reg 1361 dev/usb/if_zyd.c error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
reg 1408 dev/usb/if_zyd.c error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
reg 1529 dev/usb/if_zyd.c for (; phyp->reg != 0; phyp++) {
reg 1530 dev/usb/if_zyd.c if ((error = zyd_write16(sc, phyp->reg, phyp->val)) != 0)
reg 1051 dev/usb/if_zydreg.h uint16_t reg;
reg 1053 dev/usb/if_zydreg.h #define ZYD_REG32_LO(reg) (reg)
reg 1054 dev/usb/if_zydreg.h #define ZYD_REG32_HI(reg) \
reg 1055 dev/usb/if_zydreg.h ((reg) + ((((reg) & 0xf000) == 0x9000) ? 2 : 1))
reg 1093 dev/usb/if_zydreg.h uint16_t reg;
reg 1098 dev/usb/if_zydreg.h uint16_t reg;
reg 343 dev/usb/moscom.c moscom_set(void *vsc, int portno, int reg, int onoff)
reg 348 dev/usb/moscom.c switch (reg) {
reg 441 dev/usb/moscom.c moscom_cmd(struct moscom_softc *sc, int reg, int val)
reg 449 dev/usb/moscom.c USETW(req.wIndex, reg);
reg 972 dev/usb/ohci.c u_int32_t reg;
reg 985 dev/usb/ohci.c reg = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK;
reg 991 dev/usb/ohci.c sc->sc_control = reg;
reg 996 dev/usb/ohci.c reg |= OHCI_HCFS_SUSPEND;
reg 997 dev/usb/ohci.c OWRITE4(sc, OHCI_CONTROL, reg);
reg 1012 dev/usb/ohci.c reg = sc->sc_control;
reg 1014 dev/usb/ohci.c reg = OREAD4(sc, OHCI_CONTROL);
reg 1015 dev/usb/ohci.c reg |= OHCI_HCFS_RESUME;
reg 1016 dev/usb/ohci.c OWRITE4(sc, OHCI_CONTROL, reg);
reg 1018 dev/usb/ohci.c reg = (reg & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL;
reg 1019 dev/usb/ohci.c OWRITE4(sc, OHCI_CONTROL, reg);
reg 1021 dev/usb/ohci.c reg = (OREAD4(sc, OHCI_FM_REMAINING) & OHCI_FIT) ^ OHCI_FIT;
reg 1022 dev/usb/ohci.c reg |= OHCI_FSMPS(sc->sc_ival) | sc->sc_ival;
reg 1023 dev/usb/ohci.c OWRITE4(sc, OHCI_FM_INTERVAL, reg);
reg 1027 dev/usb/ohci.c reg = OREAD4(sc, OHCI_RH_DESCRIPTOR_A);
reg 1028 dev/usb/ohci.c OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, reg | OHCI_NOCP);
reg 1031 dev/usb/ohci.c OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, reg);
reg 240 dev/usb/uark.c uark_set(void *vsc, int portno, int reg, int onoff)
reg 244 dev/usb/uark.c switch (reg) {
reg 504 dev/usb/ubsa.c ubsa_set(void *addr, int portno, int reg, int onoff)
reg 509 dev/usb/ubsa.c switch (reg) {
reg 51 dev/usb/ucomvar.h void (*ucom_set)(void *sc, int portno, int reg, int onoff);
reg 543 dev/usb/ucycom.c ucycom_set(void *addr, int portno, int reg, int onoff)
reg 548 dev/usb/ucycom.c switch (reg) {
reg 525 dev/usb/uftdi.c uftdi_set(void *vsc, int portno, int reg, int onoff)
reg 532 dev/usb/uftdi.c reg, onoff));
reg 534 dev/usb/uftdi.c switch (reg) {
reg 348 dev/usb/uipaq.c uipaq_set(void *addr, int portno, int reg, int onoff)
reg 352 dev/usb/uipaq.c switch (reg) {
reg 364 dev/usb/uipaq.c sc->sc_dev.dv_xname, reg, onoff);
reg 395 dev/usb/umct.c umct_set(void *addr, int portno, int reg, int onoff)
reg 399 dev/usb/umct.c switch (reg) {
reg 652 dev/usb/umodem.c umodem_set(void *addr, int portno, int reg, int onoff)
reg 656 dev/usb/umodem.c switch (reg) {
reg 511 dev/usb/uplcom.c uplcom_set(void *addr, int portno, int reg, int onoff)
reg 515 dev/usb/uplcom.c switch (reg) {
reg 315 dev/usb/uslcom.c uslcom_set(void *vsc, int portno, int reg, int onoff)
reg 321 dev/usb/uslcom.c switch (reg) {
reg 604 dev/usb/uvscom.c uvscom_set(void *addr, int portno, int reg, int onoff)
reg 608 dev/usb/uvscom.c switch (reg) {
reg 187 dev/vesa/vesafb.c vesafb_set_palette(struct vga_pci_softc *sc, int reg, struct paletteentry pe)
reg 213 dev/vesa/vesafb.c tf.tf_edx = reg;
reg 88 kern/sys_process.c struct reg *regs;
reg 594 miscfs/procfs/procfs_vnops.c vap->va_bytes = vap->va_size = sizeof(struct reg);
reg 93 sys/ptrace.h struct reg;
reg 102 sys/ptrace.h int process_read_regs(struct proc *p, struct reg *regs);
reg 108 sys/ptrace.h int process_write_regs(struct proc *p, struct reg *regs);