root/dev/pci/if_msk.c

DEFINITIONS

1. sk_win_read_4
2. sk_win_read_2
3. sk_win_read_1
4. sk_win_write_4
5. sk_win_write_2
6. sk_win_write_1
7. msk_miibus_readreg
8. msk_miibus_writereg
9. msk_miibus_statchg
10. msk_setfilt
11. msk_setmulti
12. msk_setpromisc
13. msk_init_rx_ring
14. msk_init_tx_ring
15. msk_newbuf
16. msk_alloc_jumbo_mem
17. msk_jalloc
18. msk_jfree
19. msk_ifmedia_upd
20. msk_ifmedia_sts
21. msk_ioctl
22. mskc_probe
23. mskc_reset
24. msk_probe
25. msk_reset
26. msk_attach
27. mskcprint
28. mskc_attach
29. msk_encap
30. msk_start
31. msk_watchdog
32. mskc_shutdown
33. msk_rxvalid
34. msk_rxeof
35. msk_txeof
36. msk_tick
37. msk_intr_yukon
38. msk_intr
39. msk_init_yukon
40. msk_init
41. msk_stop
42. msk_dump_txdesc
43. msk_dump_bytes
44. msk_dump_mbuf

    1 /*      $OpenBSD: if_msk.c,v 1.56 2007/06/27 19:15:47 kettenis Exp $    */
    3 /*
    4  * Copyright (c) 1997, 1998, 1999, 2000
    5  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. All advertising materials mentioning features or use of this software
   16  *    must display the following acknowledgement:
   17  *      This product includes software developed by Bill Paul.
   18  * 4. Neither the name of the author nor the names of any co-contributors
   19  *    may be used to endorse or promote products derived from this software
   20  *    without specific prior written permission.
   21  *
   22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   32  * THE POSSIBILITY OF SUCH DAMAGE.
   33  *
   34  * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $
   35  */
   37 /*
   38  * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
   39  *
   40  * Permission to use, copy, modify, and distribute this software for any
   41  * purpose with or without fee is hereby granted, provided that the above
   42  * copyright notice and this permission notice appear in all copies.
   43  *
   44  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   45  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   46  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
   47  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
   48  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
   49  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
   50  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
   51  */
   53 /*
   54  * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
   55  * the SK-984x series adapters, both single port and dual port.
   56  * References:
   57  *      The XaQti XMAC II datasheet,
   58  * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
   59  *      The SysKonnect GEnesis manual, http://www.syskonnect.com
   60  *
   61  * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the
   62  * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
   63  * convenience to others until Vitesse corrects this problem:
   64  *
   65  * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
   66  *
   67  * Written by Bill Paul <wpaul@ee.columbia.edu>
   68  * Department of Electrical Engineering
   69  * Columbia University, New York City
   70  */
   72 /*
   73  * The SysKonnect gigabit ethernet adapters consist of two main
   74  * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
   75  * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
   76  * components and a PHY while the GEnesis controller provides a PCI
   77  * interface with DMA support. Each card may have between 512K and
   78  * 2MB of SRAM on board depending on the configuration.
   79  *
   80  * The SysKonnect GEnesis controller can have either one or two XMAC
   81  * chips connected to it, allowing single or dual port NIC configurations.
   82  * SysKonnect has the distinction of being the only vendor on the market
   83  * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
   84  * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
   85  * XMAC registers. This driver takes advantage of these features to allow
   86  * both XMACs to operate as independent interfaces.
   87  */
   89 #include "bpfilter.h"
   91 #include <sys/param.h>
   92 #include <sys/systm.h>
   93 #include <sys/sockio.h>
   94 #include <sys/mbuf.h>
   95 #include <sys/malloc.h>
   96 #include <sys/kernel.h>
   97 #include <sys/socket.h>
   98 #include <sys/timeout.h>
   99 #include <sys/device.h>
  100 #include <sys/queue.h>
  102 #include <net/if.h>
  103 #include <net/if_dl.h>
  104 #include <net/if_types.h>
  106 #ifdef INET
  107 #include <netinet/in.h>
  108 #include <netinet/in_systm.h>
  109 #include <netinet/in_var.h>
  110 #include <netinet/ip.h>
  111 #include <netinet/udp.h>
  112 #include <netinet/tcp.h>
  113 #include <netinet/if_ether.h>
  114 #endif
  116 #include <net/if_media.h>
  117 #include <net/if_vlan_var.h>
  119 #if NBPFILTER > 0
  120 #include <net/bpf.h>
  121 #endif
  123 #include <dev/mii/mii.h>
  124 #include <dev/mii/miivar.h>
  125 #include <dev/mii/brgphyreg.h>
  127 #include <dev/pci/pcireg.h>
  128 #include <dev/pci/pcivar.h>
  129 #include <dev/pci/pcidevs.h>
  131 #include <dev/pci/if_skreg.h>
  132 #include <dev/pci/if_mskvar.h>
  134 int mskc_probe(struct device *, void *, void *);
  135 void mskc_attach(struct device *, struct device *self, void *aux);
  136 void mskc_reset(struct sk_softc *);
  137 void mskc_shutdown(void *);
  138 int msk_probe(struct device *, void *, void *);
  139 void msk_attach(struct device *, struct device *self, void *aux);
  140 void msk_reset(struct sk_if_softc *);
  141 int mskcprint(void *, const char *);
  142 int msk_intr(void *);
  143 void msk_intr_yukon(struct sk_if_softc *);
  144 static __inline int msk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t);
  145 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t);
  146 void msk_txeof(struct sk_if_softc *);
  147 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *);
  148 void msk_start(struct ifnet *);
  149 int msk_ioctl(struct ifnet *, u_long, caddr_t);
  150 void msk_init(void *);
  151 void msk_init_yukon(struct sk_if_softc *);
  152 void msk_stop(struct sk_if_softc *);
  153 void msk_watchdog(struct ifnet *);
  154 int msk_ifmedia_upd(struct ifnet *);
  155 void msk_ifmedia_sts(struct ifnet *, struct ifmediareq *);
  156 int msk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t);
  157 int msk_alloc_jumbo_mem(struct sk_if_softc *);
  158 void *msk_jalloc(struct sk_if_softc *);
  159 void msk_jfree(caddr_t, u_int, void *);
  160 int msk_init_rx_ring(struct sk_if_softc *);
  161 int msk_init_tx_ring(struct sk_if_softc *);
  163 int msk_miibus_readreg(struct device *, int, int);
  164 void msk_miibus_writereg(struct device *, int, int, int);
  165 void msk_miibus_statchg(struct device *);
  167 void msk_setfilt(struct sk_if_softc *, caddr_t, int);
  168 void msk_setmulti(struct sk_if_softc *);
  169 void msk_setpromisc(struct sk_if_softc *);
  170 void msk_tick(void *);
  172 #ifdef MSK_DEBUG
  173 #define DPRINTF(x)      if (mskdebug) printf x
  174 #define DPRINTFN(n,x)   if (mskdebug >= (n)) printf x
  175 int     mskdebug = 0;
  177 void msk_dump_txdesc(struct msk_tx_desc *, int);
  178 void msk_dump_mbuf(struct mbuf *);
  179 void msk_dump_bytes(const char *, int);
  180 #else
  181 #define DPRINTF(x)
  182 #define DPRINTFN(n,x)
  183 #endif
  185 /* supported device vendors */
  186 const struct pci_matchid mskc_devices[] = {
  187         { PCI_VENDOR_DLINK,             PCI_PRODUCT_DLINK_DGE550SX },
  188         { PCI_VENDOR_DLINK,             PCI_PRODUCT_DLINK_DGE550T_B1 },
  189         { PCI_VENDOR_DLINK,             PCI_PRODUCT_DLINK_DGE560SX },
  190         { PCI_VENDOR_DLINK,             PCI_PRODUCT_DLINK_DGE560T },
  191         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON_C032 },
  192         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON_C033 },
  193         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON_C034 },
  194         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON_C036 },
  195         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON_C042 },
  196         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON_8021CU },
  197         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON_8021X },
  198         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON_8022CU },
  199         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON_8022X },
  200         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON_8035 },
  201         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON_8036 },
  202         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON_8038 },
  203         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON_8039 },
  204         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON_8050 },
  205         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON_8052 },
  206         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON_8053 },
  207         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON_8055 },
  208         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON_8056 },
  209         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON_8058 },
  210         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON_8061CU },
  211         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON_8061X },
  212         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON_8062CU },
  213         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON_8062X },
  214         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON_8070 },
  215         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON_8071 },
  216         { PCI_VENDOR_SCHNEIDERKOCH,     PCI_PRODUCT_SCHNEIDERKOCH_SK9Sxx },
  217         { PCI_VENDOR_SCHNEIDERKOCH,     PCI_PRODUCT_SCHNEIDERKOCH_SK9Exx }
  218 };
  220 static inline u_int32_t
sk_win_read_4(struct sk_softc *sc, u_int32_t reg)
  222 {
  223         return CSR_READ_4(sc, reg);
  224 }
  226 static inline u_int16_t
sk_win_read_2(struct sk_softc *sc, u_int32_t reg)
  228 {
  229         return CSR_READ_2(sc, reg);
  230 }
  232 static inline u_int8_t
sk_win_read_1(struct sk_softc *sc, u_int32_t reg)
  234 {
  235         return CSR_READ_1(sc, reg);
  236 }
  238 static inline void
sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x)
  240 {
CSR_WRITE_4(sc, reg, x);
  242 }
  244 static inline void
sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x)
  246 {
CSR_WRITE_2(sc, reg, x);
  248 }
  250 static inline void
sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x)
  252 {
CSR_WRITE_1(sc, reg, x);
  254 }
  256 int
msk_miibus_readreg(struct device *dev, int phy, int reg)
  258 {
  259         struct sk_if_softc *sc_if = (struct sk_if_softc *)dev;
u_int16_t val;
  261         int i;
SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
  266         for (i = 0; i < SK_TIMEOUT; i++) {
DELAY(1);
val = SK_YU_READ_2(sc_if, YUKON_SMICR);
  269                 if (val & YU_SMICR_READ_VALID)
  270                         break;
  271         }
  273         if (i == SK_TIMEOUT) {
printf("%s: phy failed to come ready\n",
sc_if->sk_dev.dv_xname);
  276                 return (0);
  277         }
DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i,
SK_TIMEOUT));
val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n",
phy, reg, val));
  287         return (val);
  288 }
  290 void
msk_miibus_writereg(struct device *dev, int phy, int reg, int val)
  292 {
  293         struct sk_if_softc *sc_if = (struct sk_if_softc *)dev;
  294         int i;
DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n",
phy, reg, val));
SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
  303         for (i = 0; i < SK_TIMEOUT; i++) {
DELAY(1);
  305                 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY))
  306                         break;
  307         }
  309         if (i == SK_TIMEOUT)
printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname);
  311 }
  313 void
msk_miibus_statchg(struct device *dev)
  315 {
  316         struct sk_if_softc *sc_if = (struct sk_if_softc *)dev;
  317         struct mii_data *mii = &sc_if->sk_mii;
  318         struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
  319         int gpcr;
gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR);
gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN);
  324         if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
  325                 /* Set speed. */
gpcr |= YU_GPCR_SPEED_DIS;
  327                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
  328                 case IFM_1000_SX:
  329                 case IFM_1000_LX:
  330                 case IFM_1000_CX:
  331                 case IFM_1000_T:
gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED);
  333                         break;
  334                 case IFM_100_TX:
gpcr |= YU_GPCR_SPEED;
  336                         break;
  337                 }
  339                 /* Set duplex. */
gpcr |= YU_GPCR_DPLX_DIS;
  341                 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
gpcr |= YU_GPCR_DUPLEX;
  344                 /* Disable flow control. */
gpcr |= YU_GPCR_FCTL_DIS;
gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS);
  347         }
SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr);
DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n",
SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR)));
  353 }
  355 void
msk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot)
  357 {
  358         int base = XM_RXFILT_ENTRY(slot);
SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0]));
SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2]));
SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4]));
  363 }
  365 void
msk_setmulti(struct sk_if_softc *sc_if)
  367 {
  368         struct ifnet *ifp= &sc_if->arpcom.ac_if;
u_int32_t hashes[2] = { 0, 0 };
  370         int h;
  371         struct arpcom *ac = &sc_if->arpcom;
  372         struct ether_multi *enm;
  373         struct ether_multistep step;
  375         /* First, zot all the existing filters. */
SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0);
SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0);
SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0);
SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0);
  382         /* Now program new ones. */
allmulti:
  384         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
hashes[0] = 0xFFFFFFFF;
hashes[1] = 0xFFFFFFFF;
  387         } else {
  388                 /* First find the tail of the list. */
ETHER_FIRST_MULTI(step, ac, enm);
  390                 while (enm != NULL) {
  391                         if (bcmp(enm->enm_addrlo, enm->enm_addrhi,
ETHER_ADDR_LEN)) {
ifp->if_flags |= IFF_ALLMULTI;
  394                                 goto allmulti;
  395                         }
h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) &
  397                             ((1 << SK_HASH_BITS) - 1);
  398                         if (h < 32)
hashes[0] |= (1 << h);
  400                         else
hashes[1] |= (1 << (h - 32));
ETHER_NEXT_MULTI(step, enm);
  404                 }
  405         }
SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
  411 }
  413 void
msk_setpromisc(struct sk_if_softc *sc_if)
  415 {
  416         struct ifnet *ifp = &sc_if->arpcom.ac_if;
  418         if (ifp->if_flags & IFF_PROMISC)
SK_YU_CLRBIT_2(sc_if, YUKON_RCR,
YU_RCR_UFLEN | YU_RCR_MUFLEN);
  421         else
SK_YU_SETBIT_2(sc_if, YUKON_RCR,
YU_RCR_UFLEN | YU_RCR_MUFLEN);
  424 }
  426 int
msk_init_rx_ring(struct sk_if_softc *sc_if)
  428 {
  429         struct msk_chain_data   *cd = &sc_if->sk_cdata;
  430         struct msk_ring_data    *rd = sc_if->sk_rdata;
  431         int                     i, nexti;
bzero((char *)rd->sk_rx_ring,
  434             sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT);
  436         for (i = 0; i < MSK_RX_RING_CNT; i++) {
cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i];
  438                 if (i == (MSK_RX_RING_CNT - 1))
nexti = 0;
  440                 else
nexti = i + 1;
cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti];
  443         }
  445         for (i = 0; i < MSK_RX_RING_CNT; i++) {
  446                 if (msk_newbuf(sc_if, i, NULL,
sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) {
printf("%s: failed alloc of %dth mbuf\n",
sc_if->sk_dev.dv_xname, i);
  450                         return (ENOBUFS);
  451                 }
  452         }
sc_if->sk_cdata.sk_rx_prod = MSK_RX_RING_CNT - 1;
sc_if->sk_cdata.sk_rx_cons = 0;
  457         return (0);
  458 }
  460 int
msk_init_tx_ring(struct sk_if_softc *sc_if)
  462 {
  463         struct sk_softc         *sc = sc_if->sk_softc;
  464         struct msk_chain_data   *cd = &sc_if->sk_cdata;
  465         struct msk_ring_data    *rd = sc_if->sk_rdata;
bus_dmamap_t            dmamap;
  467         struct sk_txmap_entry   *entry;
  468         int                     i, nexti;
bzero((char *)sc_if->sk_rdata->sk_tx_ring,
  471             sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT);
SIMPLEQ_INIT(&sc_if->sk_txmap_head);
  474         for (i = 0; i < MSK_TX_RING_CNT; i++) {
cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i];
  476                 if (i == (MSK_TX_RING_CNT - 1))
nexti = 0;
  478                 else
nexti = i + 1;
cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti];
  482                 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG,
SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap))
  484                         return (ENOBUFS);
entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT);
  487                 if (!entry) {
bus_dmamap_destroy(sc->sc_dmatag, dmamap);
  489                         return (ENOBUFS);
  490                 }
entry->dmamap = dmamap;
SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link);
  493         }
sc_if->sk_cdata.sk_tx_prod = 0;
sc_if->sk_cdata.sk_tx_cons = 0;
sc_if->sk_cdata.sk_tx_cnt = 0;
MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT,
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
  502         return (0);
  503 }
  505 int
msk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m,
bus_dmamap_t dmamap)
  508 {
  509         struct mbuf             *m_new = NULL;
  510         struct sk_chain         *c;
  511         struct msk_rx_desc      *r;
  513         if (m == NULL) {
caddr_t buf = NULL;
MGETHDR(m_new, M_DONTWAIT, MT_DATA);
  517                 if (m_new == NULL)
  518                         return (ENOBUFS);
  520                 /* Allocate the jumbo buffer */
buf = msk_jalloc(sc_if);
  522                 if (buf == NULL) {
m_freem(m_new);
DPRINTFN(1, ("%s jumbo allocation failed -- packet "
  525                             "dropped!\n", sc_if->arpcom.ac_if.if_xname));
  526                         return (ENOBUFS);
  527                 }
  529                 /* Attach the buffer to the mbuf */
m_new->m_len = m_new->m_pkthdr.len = SK_JLEN;
MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if);
  532         } else {
  533                 /*
  534                  * We're re-using a previously allocated mbuf;
  535                  * be sure to re-init pointers and lengths to
  536                  * default values.
  537                  */
m_new = m;
m_new->m_len = m_new->m_pkthdr.len = SK_JLEN;
m_new->m_data = m_new->m_ext.ext_buf;
  541         }
m_adj(m_new, ETHER_ALIGN);
c = &sc_if->sk_cdata.sk_rx_chain[i];
r = c->sk_le;
c->sk_mbuf = m_new;
r->sk_addr = htole32(dmamap->dm_segs[0].ds_addr +
  548             (((vaddr_t)m_new->m_data
  549              - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf)));
r->sk_len = htole16(SK_JLEN);
r->sk_ctl = 0;
r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN;
MSK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
  556         return (0);
  557 }
  559 /*
  560  * Memory management for jumbo frames.
  561  */
  563 int
msk_alloc_jumbo_mem(struct sk_if_softc *sc_if)
  565 {
  566         struct sk_softc         *sc = sc_if->sk_softc;
caddr_t                 ptr, kva;
bus_dma_segment_t       seg;
  569         int             i, rseg, state, error;
  570         struct sk_jpool_entry   *entry;
state = error = 0;
  574         /* Grab a big chunk o' storage. */
  575         if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0,
  576                              &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
printf(": can't alloc rx buffers");
  578                 return (ENOBUFS);
  579         }
state = 1;
  582         if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, MSK_JMEM, &kva,
BUS_DMA_NOWAIT)) {
printf(": can't map dma buffers (%d bytes)", MSK_JMEM);
error = ENOBUFS;
  586                 goto out;
  587         }
state = 2;
  590         if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0,
BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) {
printf(": can't create dma map");
error = ENOBUFS;
  594                 goto out;
  595         }
state = 3;
  598         if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map,
kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) {
printf(": can't load dma map");
error = ENOBUFS;
  602                 goto out;
  603         }
state = 4;
sc_if->sk_cdata.sk_jumbo_buf = (caddr_t)kva;
DPRINTFN(1,("msk_jumbo_buf = 0x%08X\n", sc_if->sk_cdata.sk_jumbo_buf));
LIST_INIT(&sc_if->sk_jfree_listhead);
LIST_INIT(&sc_if->sk_jinuse_listhead);
  612         /*
  613          * Now divide it up into 9K pieces and save the addresses
  614          * in an array.
  615          */
ptr = sc_if->sk_cdata.sk_jumbo_buf;
  617         for (i = 0; i < MSK_JSLOTS; i++) {
sc_if->sk_cdata.sk_jslots[i] = ptr;
ptr += SK_JLEN;
entry = malloc(sizeof(struct sk_jpool_entry),
M_DEVBUF, M_NOWAIT);
  622                 if (entry == NULL) {
sc_if->sk_cdata.sk_jumbo_buf = NULL;
printf(": no memory for jumbo buffer queue!");
error = ENOBUFS;
  626                         goto out;
  627                 }
entry->slot = i;
LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead,
entry, jpool_entries);
  631         }
out:
  633         if (error != 0) {
  634                 switch (state) {
  635                 case 4:
bus_dmamap_unload(sc->sc_dmatag,
sc_if->sk_cdata.sk_rx_jumbo_map);
  638                 case 3:
bus_dmamap_destroy(sc->sc_dmatag,
sc_if->sk_cdata.sk_rx_jumbo_map);
  641                 case 2:
bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM);
  643                 case 1:
bus_dmamem_free(sc->sc_dmatag, &seg, rseg);
  645                         break;
  646                 default:
  647                         break;
  648                 }
  649         }
  651         return (error);
  652 }
  654 /*
  655  * Allocate a jumbo buffer.
  656  */
  657 void *
msk_jalloc(struct sk_if_softc *sc_if)
  659 {
  660         struct sk_jpool_entry   *entry;
entry = LIST_FIRST(&sc_if->sk_jfree_listhead);
  664         if (entry == NULL)
  665                 return (NULL);
LIST_REMOVE(entry, jpool_entries);
LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries);
  669         return (sc_if->sk_cdata.sk_jslots[entry->slot]);
  670 }
  672 /*
  673  * Release a jumbo buffer.
  674  */
  675 void
msk_jfree(caddr_t buf, u_int size, void *arg)
  677 {
  678         struct sk_jpool_entry *entry;
  679         struct sk_if_softc *sc;
  680         int i;
  682         /* Extract the softc struct pointer. */
sc = (struct sk_if_softc *)arg;
  685         if (sc == NULL)
panic("msk_jfree: can't find softc pointer!");
  688         /* calculate the slot this buffer belongs to */
i = ((vaddr_t)buf
  690              - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN;
  692         if ((i < 0) || (i >= MSK_JSLOTS))
panic("msk_jfree: asked to free buffer that we don't manage!");
entry = LIST_FIRST(&sc->sk_jinuse_listhead);
  696         if (entry == NULL)
panic("msk_jfree: buffer not in use!");
entry->slot = i;
LIST_REMOVE(entry, jpool_entries);
LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries);
  701 }
  703 /*
  704  * Set media options.
  705  */
  706 int
msk_ifmedia_upd(struct ifnet *ifp)
  708 {
  709         struct sk_if_softc *sc_if = ifp->if_softc;
mii_mediachg(&sc_if->sk_mii);
  712         return (0);
  713 }
  715 /*
  716  * Report current media status.
  717  */
  718 void
msk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
  720 {
  721         struct sk_if_softc *sc_if = ifp->if_softc;
mii_pollstat(&sc_if->sk_mii);
ifmr->ifm_active = sc_if->sk_mii.mii_media_active;
ifmr->ifm_status = sc_if->sk_mii.mii_media_status;
  726 }
  728 int
msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
  730 {
  731         struct sk_if_softc *sc_if = ifp->if_softc;
  732         struct ifreq *ifr = (struct ifreq *) data;
  733         struct ifaddr *ifa = (struct ifaddr *) data;
  734         struct mii_data *mii;
  735         int s, error = 0;
s = splnet();
  739         if ((error = ether_ioctl(ifp, &sc_if->arpcom, command, data)) > 0) {
splx(s);
  741                 return (error);
  742         }
  744         switch(command) {
  745         case SIOCSIFADDR:
ifp->if_flags |= IFF_UP;
  747                 if (!(ifp->if_flags & IFF_RUNNING))
msk_init(sc_if);
  749 #ifdef INET
  750                 if (ifa->ifa_addr->sa_family == AF_INET)
arp_ifinit(&sc_if->arpcom, ifa);
  752 #endif /* INET */
  753                 break;
  754         case SIOCSIFMTU:
  755                 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ifp->if_hardmtu)
error = EINVAL;
  757                 else if (ifp->if_mtu != ifr->ifr_mtu)
ifp->if_mtu = ifr->ifr_mtu;
  759                 break;
  760         case SIOCSIFFLAGS:
  761                 if (ifp->if_flags & IFF_UP) {
  762                         if (ifp->if_flags & IFF_RUNNING &&
  763                             (sc_if->sk_if_flags ^ ifp->if_flags) &
IFF_PROMISC) {
msk_setpromisc(sc_if);
msk_setmulti(sc_if);
  767                         } else {
  768                                 if (!(ifp->if_flags & IFF_RUNNING))
msk_init(sc_if);
  770                         }
  771                 } else {
  772                         if (ifp->if_flags & IFF_RUNNING)
msk_stop(sc_if);
  774                 }
sc_if->sk_if_flags = ifp->if_flags;
  776                 break;
  777         case SIOCADDMULTI:
  778         case SIOCDELMULTI:
error = (command == SIOCADDMULTI) ?
ether_addmulti(ifr, &sc_if->arpcom) :
ether_delmulti(ifr, &sc_if->arpcom);
  783                 if (error == ENETRESET) {
  784                         /*
  785                          * Multicast list has changed; set the hardware
  786                          * filter accordingly.
  787                          */
  788                         if (ifp->if_flags & IFF_RUNNING)
msk_setmulti(sc_if);
error = 0;
  791                 }
  792                 break;
  793         case SIOCGIFMEDIA:
  794         case SIOCSIFMEDIA:
mii = &sc_if->sk_mii;
error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
  797                 break;
  798         default:
error = ENOTTY;
  800                 break;
  801         }
splx(s);
  805         return (error);
  806 }
  808 /*
  809  * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
  810  * IDs against our list and return a device name if we find a match.
  811  */
  812 int
mskc_probe(struct device *parent, void *match, void *aux)
  814 {
  815         return (pci_matchbyid((struct pci_attach_args *)aux, mskc_devices,
  816             sizeof(mskc_devices)/sizeof(mskc_devices[0])));
  817 }
  819 /*
  820  * Force the GEnesis into reset, then bring it out of reset.
  821  */
  822 void
mskc_reset(struct sk_softc *sc)
  824 {
u_int32_t imtimer_ticks, reg1;
  826         int reg;
DPRINTFN(2, ("mskc_reset\n"));
CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET);
CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET);
DELAY(1000);
CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET);
DELAY(2);
CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
sk_win_write_1(sc, SK_TESTCTL1, 2);
reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1));
  841         if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1)
reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA);
  843         else
reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA);
sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1);
  847         if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1)
sk_win_write_1(sc, SK_Y2_CLKGATE,
SK_Y2_CLKGATE_LINK1_GATE_DIS |
SK_Y2_CLKGATE_LINK2_GATE_DIS |
SK_Y2_CLKGATE_LINK1_CORE_DIS |
SK_Y2_CLKGATE_LINK2_CORE_DIS |
SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS);
  854         else
sk_win_write_1(sc, SK_Y2_CLKGATE, 0);
CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET);
DELAY(1000);
CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR);
sk_win_write_1(sc, SK_TESTCTL1, 1);
DPRINTFN(2, ("mskc_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR)));
DPRINTFN(2, ("mskc_reset: sk_link_ctrl=%x\n",
CSR_READ_2(sc, SK_LINK_CTRL)));
  869         /* Disable ASF */
CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET);
CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF);
  873         /* Clear I2C IRQ noise */
CSR_WRITE_4(sc, SK_I2CHWIRQ, 1);
  876         /* Disable hardware timer */
CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP);
CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR);
  880         /* Disable descriptor polling */
CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP);
  883         /* Disable time stamps */
CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP);
CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR);
  887         /* Enable RAM interface */
sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
  889         for (reg = SK_TO0;reg <= SK_TO11; reg++)
sk_win_write_1(sc, reg, 36);
sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET);
  892         for (reg = SK_TO0;reg <= SK_TO11; reg++)
sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36);
  895         /*
  896          * Configure interrupt moderation. The moderation timer
  897          * defers interrupts specified in the interrupt moderation
  898          * timer mask based on the timeout specified in the interrupt
  899          * moderation timer init register. Each bit in the timer
  900          * register represents one tick, so to specify a timeout in
  901          * microseconds, we have to multiply by the correct number of
  902          * ticks-per-microsecond.
  903          */
  904         switch (sc->sk_type) {
  905         case SK_YUKON_EC:
  906         case SK_YUKON_XL:
  907         case SK_YUKON_FE:
imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC;
  909                 break;
  910         default:
imtimer_ticks = SK_IMTIMER_TICKS_YUKON;
  912         }
  914         /* Reset status ring. */
bzero((char *)sc->sk_status_ring,
MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc));
sc->sk_status_idx = 0;
sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET);
sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET);
sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1);
sk_win_write_4(sc, SK_STAT_BMU_ADDRLO,
sc->sk_status_map->dm_segs[0].ds_addr);
sk_win_write_4(sc, SK_STAT_BMU_ADDRHI,
  926             (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32);
sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 10);
sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 16);
sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 16);
  931 #if 0
sk_win_write_4(sc, SK_Y2_LEV_TIMERINIT, SK_IM_USECS(100));
sk_win_write_4(sc, 0x0ec0, SK_IM_USECS(1000));
sk_win_write_4(sc, 0x0ed0, SK_IM_USECS(20));
  936 #else
sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, SK_IM_USECS(4));
  938 #endif
sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON);
sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START);
sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START);
sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START);
  945 }
  947 int
msk_probe(struct device *parent, void *match, void *aux)
  949 {
  950         struct skc_attach_args *sa = aux;
  952         if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B)
  953                 return (0);
  955         switch (sa->skc_type) {
  956         case SK_YUKON_XL:
  957         case SK_YUKON_EC_U:
  958         case SK_YUKON_EX:
  959         case SK_YUKON_EC:
  960         case SK_YUKON_FE:
  961                 return (1);
  962         }
  964         return (0);
  965 }
  967 void
msk_reset(struct sk_if_softc *sc_if)
  969 {
  970         /* GMAC and GPHY Reset */
SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
DELAY(1000);
SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR);
SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
  977 }
  979 /*
  980  * Each XMAC chip is attached as a separate logical IP interface.
  981  * Single port cards will have only one logical interface of course.
  982  */
  983 void
msk_attach(struct device *parent, struct device *self, void *aux)
  985 {
  986         struct sk_if_softc *sc_if = (struct sk_if_softc *) self;
  987         struct sk_softc *sc = (struct sk_softc *)parent;
  988         struct skc_attach_args *sa = aux;
  989         struct ifnet *ifp;
caddr_t kva;
bus_dma_segment_t seg;
  992         int i, rseg;
u_int32_t chunk;
  994         int mii_flags;
sc_if->sk_port = sa->skc_port;
sc_if->sk_softc = sc;
sc->sk_if[sa->skc_port] = sc_if;
DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port));
 1002         /*
 1003          * Get station address for this interface. Note that
 1004          * dual port cards actually come with three station
 1005          * addresses: one for each port, plus an extra. The
 1006          * extra one is used by the SysKonnect driver software
 1007          * as a 'virtual' station address for when both ports
 1008          * are operating in failover mode. Currently we don't
 1009          * use this extra address.
 1010          */
 1011         for (i = 0; i < ETHER_ADDR_LEN; i++)
sc_if->arpcom.ac_enaddr[i] =
sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i);
printf(": address %s\n",
ether_sprintf(sc_if->arpcom.ac_enaddr));
 1018         /*
 1019          * Set up RAM buffer addresses. The Yukon2 has a small amount
 1020          * of SRAM on it, somewhere between 4K and 48K.  We need to
 1021          * divide this up between the transmitter and receiver.  We
 1022          * give the receiver 2/3 of the memory (rounded down), and the
 1023          * transmitter whatever remains.
 1024          */
chunk = (2 * (sc->sk_ramsize / sizeof(u_int64_t)) / 3) & ~0xff;
sc_if->sk_rx_ramstart = 0;
sc_if->sk_rx_ramend = sc_if->sk_rx_ramstart + chunk - 1;
chunk = (sc->sk_ramsize / sizeof(u_int64_t)) - chunk;
sc_if->sk_tx_ramstart = sc_if->sk_rx_ramend + 1;
sc_if->sk_tx_ramend = sc_if->sk_tx_ramstart + chunk - 1;
DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n"
 1033                      "           tx_ramstart=%#x tx_ramend=%#x\n",
sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend,
sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend));
 1037         /* Allocate the descriptor queues. */
 1038         if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data),
PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
printf(": can't alloc rx buffers\n");
 1041                 goto fail;
 1042         }
 1043         if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg,
 1044             sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) {
printf(": can't map dma buffers (%lu bytes)\n",
 1046                        (ulong)sizeof(struct msk_ring_data));
 1047                 goto fail_1;
 1048         }
 1049         if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1,
 1050             sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT,
 1051             &sc_if->sk_ring_map)) {
printf(": can't create dma map\n");
 1053                 goto fail_2;
 1054         }
 1055         if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva,
 1056             sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) {
printf(": can't load dma map\n");
 1058                 goto fail_3;
 1059         }
sc_if->sk_rdata = (struct msk_ring_data *)kva;
bzero(sc_if->sk_rdata, sizeof(struct msk_ring_data));
 1063         /* Try to allocate memory for jumbo buffers. */
 1064         if (msk_alloc_jumbo_mem(sc_if)) {
printf(": jumbo buffer allocation failed\n");
 1066                 goto fail_3;
 1067         }
ifp = &sc_if->arpcom.ac_if;
ifp->if_softc = sc_if;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_ioctl = msk_ioctl;
ifp->if_start = msk_start;
ifp->if_watchdog = msk_watchdog;
ifp->if_baudrate = 1000000000;
 1076         if (sc->sk_type != SK_YUKON_FE)
ifp->if_hardmtu = SK_JUMBO_MTU;
IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1);
IFQ_SET_READY(&ifp->if_snd);
bcopy(sc_if->sk_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
ifp->if_capabilities = IFCAP_VLAN_MTU;
msk_reset(sc_if);
 1086         /*
 1087          * Do miibus setup.
 1088          */
msk_init_yukon(sc_if);
DPRINTFN(2, ("msk_attach: 1\n"));
sc_if->sk_mii.mii_ifp = ifp;
sc_if->sk_mii.mii_readreg = msk_miibus_readreg;
sc_if->sk_mii.mii_writereg = msk_miibus_writereg;
sc_if->sk_mii.mii_statchg = msk_miibus_statchg;
ifmedia_init(&sc_if->sk_mii.mii_media, 0,
msk_ifmedia_upd, msk_ifmedia_sts);
mii_flags = MIIF_DOPAUSE;
 1101         if (sc->sk_fibertype)
mii_flags |= MIIF_HAVEFIBER;
mii_attach(self, &sc_if->sk_mii, 0xffffffff, 0,
MII_OFFSET_ANY, mii_flags);
 1105         if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) {
printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname);
ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL,
 1108                             0, NULL);
ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL);
 1110         } else
ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO);
timeout_set(&sc_if->sk_tick_ch, msk_tick, sc_if);
 1115         /*
 1116          * Call MI attach routines.
 1117          */
if_attach(ifp);
ether_ifattach(ifp);
shutdownhook_establish(mskc_shutdown, sc);
DPRINTFN(2, ("msk_attach: end\n"));
 1124         return;
fail_3:
bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map);
fail_2:
bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data));
fail_1:
bus_dmamem_free(sc->sc_dmatag, &seg, rseg);
fail:
sc->sk_if[sa->skc_port] = NULL;
 1134 }
 1136 int
mskcprint(void *aux, const char *pnp)
 1138 {
 1139         struct skc_attach_args *sa = aux;
 1141         if (pnp)
printf("sk port %c at %s",
 1143                     (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp);
 1144         else
printf(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B');
 1146         return (UNCONF);
 1147 }
 1149 /*
 1150  * Attach the interface. Allocate softc structures, do ifmedia
 1151  * setup and ethernet/BPF attach.
 1152  */
 1153 void
mskc_attach(struct device *parent, struct device *self, void *aux)
 1155 {
 1156         struct sk_softc *sc = (struct sk_softc *)self;
 1157         struct pci_attach_args *pa = aux;
 1158         struct skc_attach_args skca;
pci_chipset_tag_t pc = pa->pa_pc;
pcireg_t command, memtype;
pci_intr_handle_t ih;
 1162         const char *intrstr = NULL;
bus_size_t size;
u_int8_t hw, pmd;
 1165         char *revstr = NULL;
caddr_t kva;
bus_dma_segment_t seg;
 1168         int rseg;
DPRINTFN(2, ("begin mskc_attach\n"));
 1172         /*
 1173          * Handle power management nonsense.
 1174          */
command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF;
 1177         if (command == 0x01) {
command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL);
 1179                 if (command & SK_PSTATE_MASK) {
u_int32_t               iobase, membase, irq;
 1182                         /* Save important PCI config data. */
iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO);
membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM);
irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE);
 1187                         /* Reset the power state. */
printf("%s chip is in D%d power mode "
 1189                             "-- setting to D0\n", sc->sk_dev.dv_xname,
command & SK_PSTATE_MASK);
command &= 0xFFFFFFFC;
pci_conf_write(pc, pa->pa_tag,
SK_PCI_PWRMGMTCTRL, command);
 1195                         /* Restore PCI config data. */
pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase);
pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase);
pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq);
 1199                 }
 1200         }
 1202         /*
 1203          * Map control/status registers.
 1204          */
memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM);
 1207         switch (memtype) {
 1208         case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
 1209         case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
 1210                 if (pci_mapreg_map(pa, SK_PCI_LOMEM,
memtype, 0, &sc->sk_btag, &sc->sk_bhandle,
NULL, &size, 0) == 0)
 1213                         break;
 1214         default:
printf(": can't map mem space\n");
 1216                 return;
 1217         }
sc->sc_dmatag = pa->pa_dmat;
sc->sk_type = sk_win_read_1(sc, SK_CHIPVER);
sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4);
 1224         /* bail out here if chip is not recognized */
 1225         if (!(SK_IS_YUKON2(sc))) {
printf(": unknown chip type: %d\n", sc->sk_type);
 1227                 goto fail_1;
 1228         }
DPRINTFN(2, ("mskc_attach: allocate interrupt\n"));
 1231         /* Allocate interrupt */
 1232         if (pci_intr_map(pa, &ih)) {
printf(": couldn't map interrupt\n");
 1234                 goto fail_1;
 1235         }
intrstr = pci_intr_string(pc, ih);
sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, msk_intr, sc,
self->dv_xname);
 1240         if (sc->sk_intrhand == NULL) {
printf(": couldn't establish interrupt");
 1242                 if (intrstr != NULL)
printf(" at %s", intrstr);
printf("\n");
 1245                 goto fail_1;
 1246         }
 1248         if (bus_dmamem_alloc(sc->sc_dmatag,
MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc),
PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
printf(": can't alloc status buffers\n");
 1252                 goto fail_2;
 1253         }
 1255         if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg,
MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc),
 1257             &kva, BUS_DMA_NOWAIT)) {
printf(": can't map dma buffers (%lu bytes)\n",
 1259                     (ulong)(MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)));
 1260                 goto fail_3;
 1261         }
 1262         if (bus_dmamap_create(sc->sc_dmatag,
MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1,
MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0,
BUS_DMA_NOWAIT, &sc->sk_status_map)) {
printf(": can't create dma map\n");
 1267                 goto fail_4;
 1268         }
 1269         if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva,
MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc),
NULL, BUS_DMA_NOWAIT)) {
printf(": can't load dma map\n");
 1273                 goto fail_5;
 1274         }
sc->sk_status_ring = (struct msk_status_desc *)kva;
bzero(sc->sk_status_ring,
MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc));
 1279         /* Reset the adapter. */
mskc_reset(sc);
sc->sk_ramsize = sk_win_read_1(sc, SK_EPROM0) * 4096;
DPRINTFN(2, ("mskc_attach: ramsize=%dK\n", sc->sk_ramsize / 1024));
pmd = sk_win_read_1(sc, SK_PMDTYPE);
 1286         if (pmd == 'L' || pmd == 'S' || pmd == 'P')
sc->sk_fibertype = 1;
 1289         switch (sc->sk_type) {
 1290         case SK_YUKON_XL:
sc->sk_name = "Yukon-2 XL";
 1292                 break;
 1293         case SK_YUKON_EC_U:
sc->sk_name = "Yukon-2 EC Ultra";
 1295                 break;
 1296         case SK_YUKON_EX:
sc->sk_name = "Yukon-2 Extreme";
 1298                 break;
 1299         case SK_YUKON_EC:
sc->sk_name = "Yukon-2 EC";
 1301                 break;
 1302         case SK_YUKON_FE:
sc->sk_name = "Yukon-2 FE";
 1304                 break;
 1305         default:
sc->sk_name = "Yukon (Unknown)";
 1307         }
 1309         if (sc->sk_type == SK_YUKON_XL) {
 1310                 switch (sc->sk_rev) {
 1311                 case SK_YUKON_XL_REV_A0:
revstr = "A0";
 1313                         break;
 1314                 case SK_YUKON_XL_REV_A1:
revstr = "A1";
 1316                         break;
 1317                 case SK_YUKON_XL_REV_A2:
revstr = "A2";
 1319                         break;
 1320                 case SK_YUKON_XL_REV_A3:
revstr = "A3";
 1322                         break;
 1323                 default:
 1324                         ;
 1325                 }
 1326         }
 1328         if (sc->sk_type == SK_YUKON_EC) {
 1329                 switch (sc->sk_rev) {
 1330                 case SK_YUKON_EC_REV_A1:
revstr = "A1";
 1332                         break;
 1333                 case SK_YUKON_EC_REV_A2:
revstr = "A2";
 1335                         break;
 1336                 case SK_YUKON_EC_REV_A3:
revstr = "A3";
 1338                         break;
 1339                 default:
 1340                         ;
 1341                 }
 1342         }
 1344         if (sc->sk_type == SK_YUKON_EC_U) {
 1345                 switch (sc->sk_rev) {
 1346                 case SK_YUKON_EC_U_REV_A0:
revstr = "A0";
 1348                         break;
 1349                 case SK_YUKON_EC_U_REV_A1:
revstr = "A1";
 1351                         break;
 1352                 default:
 1353                         ;
 1354                 }
 1355         }
 1357         /* Announce the product name. */
printf(", %s", sc->sk_name);
 1359         if (revstr != NULL)
printf(" rev. %s", revstr);
printf(" (0x%x): %s\n", sc->sk_rev, intrstr);
sc->sk_macs = 1;
hw = sk_win_read_1(sc, SK_Y2_HWRES);
 1366         if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) {
 1367                 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) &
SK_Y2_CLKGATE_LINK2_INACTIVE) == 0)
sc->sk_macs++;
 1370         }
skca.skc_port = SK_PORT_A;
skca.skc_type = sc->sk_type;
skca.skc_rev = sc->sk_rev;
 1375         (void)config_found(&sc->sk_dev, &skca, mskcprint);
 1377         if (sc->sk_macs > 1) {
skca.skc_port = SK_PORT_B;
skca.skc_type = sc->sk_type;
skca.skc_rev = sc->sk_rev;
 1381                 (void)config_found(&sc->sk_dev, &skca, mskcprint);
 1382         }
 1384         /* Turn on the 'driver is loaded' LED. */
CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
 1387         return;
fail_5:
bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map);
fail_4:
bus_dmamem_unmap(sc->sc_dmatag, kva, 
MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc));
fail_3:
bus_dmamem_free(sc->sc_dmatag, &seg, rseg);
fail_2:
pci_intr_disestablish(pc, sc->sk_intrhand);
fail_1:
bus_space_unmap(sc->sk_btag, sc->sk_bhandle, size);
 1400 }
 1402 int
msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx)
 1404 {
 1405         struct sk_softc         *sc = sc_if->sk_softc;
 1406         struct msk_tx_desc              *f = NULL;
u_int32_t               frag, cur;
 1408         int                     i;
 1409         struct sk_txmap_entry   *entry;
bus_dmamap_t            txmap;
DPRINTFN(2, ("msk_encap\n"));
entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head);
 1415         if (entry == NULL) {
DPRINTFN(2, ("msk_encap: no txmap available\n"));
 1417                 return (ENOBUFS);
 1418         }
txmap = entry->dmamap;
cur = frag = *txidx;
 1423 #ifdef MSK_DEBUG
 1424         if (mskdebug >= 2)
msk_dump_mbuf(m_head);
 1426 #endif
 1428         /*
 1429          * Start packing the mbufs in this chain into
 1430          * the fragment pointers. Stop when we run out
 1431          * of fragments or hit the end of the mbuf chain.
 1432          */
 1433         if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head,
BUS_DMA_NOWAIT)) {
DPRINTFN(2, ("msk_encap: dmamap failed\n"));
 1436                 return (ENOBUFS);
 1437         }
 1439         if (txmap->dm_nsegs > (MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) {
DPRINTFN(2, ("msk_encap: too few descriptors free\n"));
bus_dmamap_unload(sc->sc_dmatag, txmap);
 1442                 return (ENOBUFS);
 1443         }
DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n", txmap->dm_nsegs));
 1447         /* Sync the DMA map. */
bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize,
BUS_DMASYNC_PREWRITE);
 1451         for (i = 0; i < txmap->dm_nsegs; i++) {
f = &sc_if->sk_rdata->sk_tx_ring[frag];
f->sk_addr = htole32(txmap->dm_segs[i].ds_addr);
f->sk_len = htole16(txmap->dm_segs[i].ds_len);
f->sk_ctl = 0;
 1456                 if (i == 0)
f->sk_opcode = SK_Y2_TXOPC_PACKET;
 1458                 else
f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN;
cur = frag;
SK_INC(frag, MSK_TX_RING_CNT);
 1462         }
sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head;
SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link);
sc_if->sk_cdata.sk_tx_map[cur] = entry;
sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG;
 1470         /* Sync descriptors before handing to chip */
MSK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs,
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN;
 1476         /* Sync first descriptor to hand it off */
MSK_CDTXSYNC(sc_if, *txidx, 1,
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs;
 1482 #ifdef MSK_DEBUG
 1483         if (mskdebug >= 2) {
 1484                 struct msk_tx_desc *le;
u_int32_t idx;
 1486                 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) {
le = &sc_if->sk_rdata->sk_tx_ring[idx];
msk_dump_txdesc(le, idx);
 1489                 }
 1490         }
 1491 #endif
 1493         *txidx = frag;
DPRINTFN(2, ("msk_encap: completed successfully\n"));
 1497         return (0);
 1498 }
 1500 void
msk_start(struct ifnet *ifp)
 1502 {
 1503         struct sk_if_softc      *sc_if = ifp->if_softc;
 1504         struct mbuf             *m_head = NULL;
u_int32_t               idx = sc_if->sk_cdata.sk_tx_prod;
 1506         int                     pkts = 0;
DPRINTFN(2, ("msk_start\n"));
 1510         while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) {
IFQ_POLL(&ifp->if_snd, m_head);
 1512                 if (m_head == NULL)
 1513                         break;
 1515                 /*
 1516                  * Pack the data into the transmit ring. If we
 1517                  * don't have room, set the OACTIVE flag and wait
 1518                  * for the NIC to drain the ring.
 1519                  */
 1520                 if (msk_encap(sc_if, m_head, &idx)) {
ifp->if_flags |= IFF_OACTIVE;
 1522                         break;
 1523                 }
 1525                 /* now we are committed to transmit the packet */
IFQ_DEQUEUE(&ifp->if_snd, m_head);
pkts++;
 1529                 /*
 1530                  * If there's a BPF listener, bounce a copy of this frame
 1531                  * to him.
 1532                  */
 1533 #if NBPFILTER > 0
 1534                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT);
 1536 #endif
 1537         }
 1538         if (pkts == 0)
 1539                 return;
 1541         /* Transmit */
 1542         if (idx != sc_if->sk_cdata.sk_tx_prod) {
sc_if->sk_cdata.sk_tx_prod = idx;
SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx);
 1546                 /* Set a timeout in case the chip goes out to lunch. */
ifp->if_timer = 5;
 1548         }
 1549 }
 1551 void
msk_watchdog(struct ifnet *ifp)
 1553 {
 1554         struct sk_if_softc *sc_if = ifp->if_softc;
 1556         /*
 1557          * Reclaim first as there is a possibility of losing Tx completion
 1558          * interrupts.
 1559          */
msk_txeof(sc_if);
 1561         if (sc_if->sk_cdata.sk_tx_cnt != 0) {
printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname);
ifp->if_oerrors++;
 1566                 /* XXX Resets both ports; we shouldn't do that. */
mskc_reset(sc_if->sk_softc);
msk_reset(sc_if);
msk_init(sc_if);
 1570         }
 1571 }
 1573 void
mskc_shutdown(void *v)
 1575 {
 1576         struct sk_softc         *sc = v;
DPRINTFN(2, ("msk_shutdown\n"));
 1580         /* Turn off the 'driver is loaded' LED. */
CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
 1583         /*
 1584          * Reset the GEnesis controller. Doing this should also
 1585          * assert the resets on the attached XMAC(s).
 1586          */
mskc_reset(sc);
 1588 }
 1590 static __inline int
msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len)
 1592 {
 1593         if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR |
YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC |
YU_RXSTAT_JABBER)) != 0 ||
 1596             (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK ||
YU_RXSTAT_BYTES(stat) != len)
 1598                 return (0);
 1600         return (1);
 1601 }
 1603 void
msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat)
 1605 {
 1606         struct sk_softc         *sc = sc_if->sk_softc;
 1607         struct ifnet            *ifp = &sc_if->arpcom.ac_if;
 1608         struct mbuf             *m;
 1609         struct sk_chain         *cur_rx;
 1610         int                     cur, total_len = len;
bus_dmamap_t            dmamap;
DPRINTFN(2, ("msk_rxeof\n"));
cur = sc_if->sk_cdata.sk_rx_cons;
SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT);
SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT);
 1619         /* Sync the descriptor */
MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur];
dmamap = sc_if->sk_cdata.sk_rx_jumbo_map;
bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0,
dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
m = cur_rx->sk_mbuf;
cur_rx->sk_mbuf = NULL;
 1631         if (total_len < SK_MIN_FRAMELEN ||
total_len > SK_JUMBO_FRAMELEN ||
msk_rxvalid(sc, rxstat, total_len) == 0) {
ifp->if_ierrors++;
msk_newbuf(sc_if, cur, m, dmamap);
 1636                 return;
 1637         }
 1639         /*
 1640          * Try to allocate a new jumbo buffer. If that fails, copy the
 1641          * packet to mbufs and put the jumbo buffer back in the ring
 1642          * so it can be re-used. If allocating mbufs fails, then we
 1643          * have to drop the packet.
 1644          */
 1645         if (msk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) {
 1646                 struct mbuf             *m0;
m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
total_len + ETHER_ALIGN, 0, ifp, NULL);
msk_newbuf(sc_if, cur, m, dmamap);
 1650                 if (m0 == NULL) {
ifp->if_ierrors++;
 1652                         return;
 1653                 }
m_adj(m0, ETHER_ALIGN);
m = m0;
 1656         } else {
m->m_pkthdr.rcvif = ifp;
m->m_pkthdr.len = m->m_len = total_len;
 1659         }
ifp->if_ipackets++;
 1663 #if NBPFILTER > 0
 1664         if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN);
 1666 #endif
 1668         /* pass it on. */
ether_input_mbuf(ifp, m);
 1670 }
 1672 void
msk_txeof(struct sk_if_softc *sc_if)
 1674 {
 1675         struct sk_softc         *sc = sc_if->sk_softc;
 1676         struct msk_tx_desc      *cur_tx;
 1677         struct ifnet            *ifp = &sc_if->arpcom.ac_if;
u_int32_t               idx, reg, sk_ctl;
 1679         struct sk_txmap_entry   *entry;
DPRINTFN(2, ("msk_txeof\n"));
 1683         if (sc_if->sk_port == SK_PORT_A)
reg = SK_STAT_BMU_TXA1_RIDX;
 1685         else
reg = SK_STAT_BMU_TXA2_RIDX;
 1688         /*
 1689          * Go through our tx ring and free mbufs for those
 1690          * frames that have been sent.
 1691          */
idx = sc_if->sk_cdata.sk_tx_cons;
 1693         while (idx != sk_win_read_2(sc, reg)) {
MSK_CDTXSYNC(sc_if, idx, 1,
BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx];
sk_ctl = cur_tx->sk_ctl;
 1699 #ifdef MSK_DEBUG
 1700                 if (mskdebug >= 2)
msk_dump_txdesc(cur_tx, idx);
 1702 #endif
 1703                 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG)
ifp->if_opackets++;
 1705                 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) {
entry = sc_if->sk_cdata.sk_tx_map[idx];
m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf);
sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL;
bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0,
entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->sc_dmatag, entry->dmamap);
SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry,
link);
sc_if->sk_cdata.sk_tx_map[idx] = NULL;
 1718                 }
sc_if->sk_cdata.sk_tx_cnt--;
SK_INC(idx, MSK_TX_RING_CNT);
 1721         }
ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0;
 1724         if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2)
ifp->if_flags &= ~IFF_OACTIVE;
sc_if->sk_cdata.sk_tx_cons = idx;
 1728 }
 1730 void
msk_tick(void *xsc_if)
 1732 {
 1733         struct sk_if_softc *sc_if = xsc_if;  
 1734         struct mii_data *mii = &sc_if->sk_mii;
 1735         int s;
s = splnet();
mii_tick(mii);
splx(s);
timeout_add(&sc_if->sk_tick_ch, hz);
 1741 }
 1743 void
msk_intr_yukon(struct sk_if_softc *sc_if)
 1745 {
u_int8_t status;
status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR);
 1749         /* RX overrun */
 1750         if ((status & SK_GMAC_INT_RX_OVER) != 0) {
SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
SK_RFCTL_RX_FIFO_OVER);
 1753         }
 1754         /* TX underrun */
 1755         if ((status & SK_GMAC_INT_TX_UNDER) != 0) {
SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST,
SK_TFCTL_TX_FIFO_UNDER);
 1758         }
DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status));
 1761 }
 1763 int
msk_intr(void *xsc)
 1765 {
 1766         struct sk_softc         *sc = xsc;
 1767         struct sk_if_softc      *sc_if0 = sc->sk_if[SK_PORT_A];
 1768         struct sk_if_softc      *sc_if1 = sc->sk_if[SK_PORT_B];
 1769         struct ifnet            *ifp0 = NULL, *ifp1 = NULL;
 1770         int                     claimed = 0;
u_int32_t               status;
 1772         struct msk_status_desc  *cur_st;
status = CSR_READ_4(sc, SK_Y2_ISSR2);
 1775         if (status == 0) {
CSR_WRITE_4(sc, SK_Y2_ICR, 2);
 1777                 return (0);
 1778         }
status = CSR_READ_4(sc, SK_ISR);
 1782         if (sc_if0 != NULL)
ifp0 = &sc_if0->arpcom.ac_if;
 1784         if (sc_if1 != NULL)
ifp1 = &sc_if1->arpcom.ac_if;
 1787         if (sc_if0 && (status & SK_Y2_IMR_MAC1) &&
 1788             (ifp0->if_flags & IFF_RUNNING)) {
msk_intr_yukon(sc_if0);
 1790         }
 1792         if (sc_if1 && (status & SK_Y2_IMR_MAC2) &&
 1793             (ifp1->if_flags & IFF_RUNNING)) {
msk_intr_yukon(sc_if1);
 1795         }
MSK_CDSTSYNC(sc, sc->sk_status_idx,
BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
cur_st = &sc->sk_status_ring[sc->sk_status_idx];
 1801         while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) {
cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN;
 1803                 switch (cur_st->sk_opcode) {
 1804                 case SK_Y2_STOPC_RXSTAT:
msk_rxeof(sc->sk_if[cur_st->sk_link],
letoh16(cur_st->sk_len),
letoh32(cur_st->sk_status));
SK_IF_WRITE_2(sc->sk_if[cur_st->sk_link], 0,
SK_RXQ1_Y2_PREF_PUTIDX,
sc->sk_if[cur_st->sk_link]->sk_cdata.sk_rx_prod);
 1811                         break;
 1812                 case SK_Y2_STOPC_TXSTAT:
 1813                         if (sc_if0)
msk_txeof(sc_if0);
 1815                         if (sc_if1)
msk_txeof(sc_if1);
 1817                         break;
 1818                 default:
printf("opcode=0x%x\n", cur_st->sk_opcode);
 1820                         break;
 1821                 }
SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT);
MSK_CDSTSYNC(sc, sc->sk_status_idx,
BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
cur_st = &sc->sk_status_ring[sc->sk_status_idx];
 1827         }
 1829         if (status & SK_Y2_IMR_BMU) {
CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR);
claimed = 1;
 1832         }
CSR_WRITE_4(sc, SK_Y2_ICR, 2);
 1836         if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd))
msk_start(ifp0);
 1838         if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd))
msk_start(ifp1);
 1841         return (claimed);
 1842 }
 1844 void
msk_init_yukon(struct sk_if_softc *sc_if)
 1846 {
u_int32_t               v;
u_int16_t               reg;
 1849         struct sk_softc         *sc;
 1850         int                     i;
sc = sc_if->sk_softc;
DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n",
CSR_READ_4(sc_if->sk_softc, SK_CSR)));
DPRINTFN(6, ("msk_init_yukon: 1\n"));
DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n",
SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL)));
DPRINTFN(6, ("msk_init_yukon: 3\n"));
 1864         /* unused read of the interrupt source register */
DPRINTFN(6, ("msk_init_yukon: 4\n"));
SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
DPRINTFN(6, ("msk_init_yukon: 4a\n"));
reg = SK_YU_READ_2(sc_if, YUKON_PAR);
DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg));
 1872         /* MIB Counter Clear Mode set */
reg |= YU_PAR_MIB_CLR;
DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg));
DPRINTFN(6, ("msk_init_yukon: 4b\n"));
SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
 1878         /* MIB Counter Clear Mode clear */
DPRINTFN(6, ("msk_init_yukon: 5\n"));
reg &= ~YU_PAR_MIB_CLR;
SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
 1883         /* receive control reg */
DPRINTFN(6, ("msk_init_yukon: 7\n"));
SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
 1887         /* transmit parameter register */
DPRINTFN(6, ("msk_init_yukon: 8\n"));
SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
 1892         /* serial mode register */
DPRINTFN(6, ("msk_init_yukon: 9\n"));
reg = YU_SMR_DATA_BLIND(0x1c) |
YU_SMR_MFL_VLAN |
YU_SMR_IPG_DATA(0x1e);
 1898         if (sc->sk_type != SK_YUKON_FE)
reg |= YU_SMR_MFL_JUMBO;
SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
DPRINTFN(6, ("msk_init_yukon: 10\n"));
 1904         /* Setup Yukon's address */
 1905         for (i = 0; i < 3; i++) {
 1906                 /* Write Source Address 1 (unicast filter) */
SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 
sc_if->arpcom.ac_enaddr[i * 2] |
sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8);
 1910         }
 1912         for (i = 0; i < 3; i++) {
reg = sk_win_read_2(sc_if->sk_softc,
SK_MAC1_0 + i * 2 + sc_if->sk_port * 8);
SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
 1916         }
 1918         /* Set promiscuous mode */
msk_setpromisc(sc_if);
 1921         /* Set multicast filter */
DPRINTFN(6, ("msk_init_yukon: 11\n"));
msk_setmulti(sc_if);
 1925         /* enable interrupt mask for counter overflows */
DPRINTFN(6, ("msk_init_yukon: 12\n"));
SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
 1931         /* Configure RX MAC FIFO Flush Mask */
v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR |
YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT |
YU_RXSTAT_JABBER;
SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v);
 1937         /* Configure RX MAC FIFO */
SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON |
SK_RFCTL_FIFO_FLUSH_ON);
 1942         /* Increase flush threshould to 64 bytes */
SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD,
SK_RFCTL_FIFO_THRESHOLD + 1);
 1946         /* Configure TX MAC FIFO */
SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
 1950 #if 1
SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN);
 1952 #endif
DPRINTFN(6, ("msk_init_yukon: end\n"));
 1954 }
 1956 /*
 1957  * Note that to properly initialize any part of the GEnesis chip,
 1958  * you first have to take it out of reset mode.
 1959  */
 1960 void
msk_init(void *xsc_if)
 1962 {
 1963         struct sk_if_softc      *sc_if = xsc_if;
 1964         struct sk_softc         *sc = sc_if->sk_softc;
 1965         struct ifnet            *ifp = &sc_if->arpcom.ac_if;
 1966         struct mii_data         *mii = &sc_if->sk_mii;
 1967         int                     s;
DPRINTFN(2, ("msk_init\n"));
s = splnet();
 1973         /* Cancel pending I/O and free all RX/TX buffers. */
msk_stop(sc_if);
 1976         /* Configure I2C registers */
 1978         /* Configure XMAC(s) */
msk_init_yukon(sc_if);
mii_mediachg(mii);
 1982         /* Configure transmit arbiter(s) */
SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON);
 1984 #if 0
SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON);
 1986 #endif
 1988         /* Configure RAMbuffers */
SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET);
SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON);
SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart);
SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart);
SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart);
SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend);
SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON);
 2004         /* Configure BMUs */
SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016);
SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28);
SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080);
SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_WATERMARK, 0x00000600);
SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016);
SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28);
SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080);
SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_WATERMARK, 0x00000600);
 2015         /* Make sure the sync transmit queue is disabled. */
SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET);
 2018         /* Init descriptors */
 2019         if (msk_init_rx_ring(sc_if) == ENOBUFS) {
printf("%s: initialization failed: no "
 2021                     "memory for rx buffers\n", sc_if->sk_dev.dv_xname);
msk_stop(sc_if);
splx(s);
 2024                 return;
 2025         }
 2027         if (msk_init_tx_ring(sc_if) == ENOBUFS) {
printf("%s: initialization failed: no "
 2029                     "memory for tx buffers\n", sc_if->sk_dev.dv_xname);
msk_stop(sc_if);
splx(s);
 2032                 return;
 2033         }
 2035         /* Initialize prefetch engine. */
SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001);
SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002);
SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1);
SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO,
MSK_RX_RING_ADDR(sc_if, 0));
SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI,
 2042             (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32);
SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008);
SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR);
SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001);
SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002);
SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1);
SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO,
MSK_TX_RING_ADDR(sc_if, 0));
SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI,
 2052             (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32);
SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008);
SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR);
SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX,
sc_if->sk_cdata.sk_rx_prod);
 2059         /* Configure interrupt handling */
 2060         if (sc_if->sk_port == SK_PORT_A)
sc->sk_intrmask |= SK_Y2_INTRS1;
 2062         else
sc->sk_intrmask |= SK_Y2_INTRS2;
sc->sk_intrmask |= SK_Y2_IMR_BMU;
CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
timeout_add(&sc_if->sk_tick_ch, hz);
splx(s);
 2073 }
 2075 void
msk_stop(struct sk_if_softc *sc_if)
 2077 {
 2078         struct sk_softc         *sc = sc_if->sk_softc;
 2079         struct ifnet            *ifp = &sc_if->arpcom.ac_if;
 2080         struct sk_txmap_entry   *dma;
 2081         int                     i;
DPRINTFN(2, ("msk_stop\n"));
timeout_del(&sc_if->sk_tick_ch);
ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
 2089         /* Stop transfer of Tx descriptors */
 2091         /* Stop transfer of Rx descriptors */
 2093         /* Turn off various components of this interface. */
SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE);
SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP);
SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001);
SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001);
 2110         /* Disable interrupts */
 2111         if (sc_if->sk_port == SK_PORT_A)
sc->sk_intrmask &= ~SK_Y2_INTRS1;
 2113         else
sc->sk_intrmask &= ~SK_Y2_INTRS2;
CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
SK_XM_READ_2(sc_if, XM_ISR);
SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
 2120         /* Free RX and TX mbufs still in the queues. */
 2121         for (i = 0; i < MSK_RX_RING_CNT; i++) {
 2122                 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) {
m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf);
sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL;
 2125                 }
 2126         }
 2128         for (i = 0; i < MSK_TX_RING_CNT; i++) {
 2129                 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) {
m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf);
sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL;
SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head,
sc_if->sk_cdata.sk_tx_map[i], link);
sc_if->sk_cdata.sk_tx_map[i] = 0;
 2135                 }
 2136         }
 2138         while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) {
SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link);
bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap);
free(dma, M_DEVBUF);
 2142         }
 2143 }
 2145 struct cfattach mskc_ca = {
 2146         sizeof(struct sk_softc), mskc_probe, mskc_attach,
 2147 };
 2149 struct cfdriver mskc_cd = {
 2150         0, "mskc", DV_DULL
 2151 };
 2153 struct cfattach msk_ca = {
 2154         sizeof(struct sk_if_softc), msk_probe, msk_attach,
 2155 };
 2157 struct cfdriver msk_cd = {
 2158         0, "msk", DV_IFNET
 2159 };
 2161 #ifdef MSK_DEBUG
 2162 void
msk_dump_txdesc(struct msk_tx_desc *le, int idx)
 2164 {
 2165 #define DESC_PRINT(X)                                   \
 2166         if (X)                                  \
printf("txdesc[%d]." #X "=%#x\n",       \
idx, X);
DESC_PRINT(letoh32(le->sk_addr));
DESC_PRINT(letoh16(le->sk_len));
DESC_PRINT(le->sk_ctl);
DESC_PRINT(le->sk_opcode);
 2174 #undef DESC_PRINT
 2175 }
 2177 void
msk_dump_bytes(const char *data, int len)
 2179 {
 2180         int c, i, j;
 2182         for (i = 0; i < len; i += 16) {
printf("%08x  ", i);
c = len - i;
 2185                 if (c > 16) c = 16;
 2187                 for (j = 0; j < c; j++) {
printf("%02x ", data[i + j] & 0xff);
 2189                         if ((j & 0xf) == 7 && j > 0)
printf(" ");
 2191                 }
 2193                 for (; j < 16; j++)
printf("   ");
printf("  ");
 2197                 for (j = 0; j < c; j++) {
 2198                         int ch = data[i + j] & 0xff;
printf("%c", ' ' <= ch && ch <= '~' ? ch : ' ');
 2200                 }
printf("\n");
 2204                 if (c < 16)
 2205                         break;
 2206         }
 2207 }
 2209 void
msk_dump_mbuf(struct mbuf *m)
 2211 {
 2212         int count = m->m_pkthdr.len;
printf("m=%#lx, m->m_pkthdr.len=%#d\n", m, m->m_pkthdr.len);
 2216         while (count > 0 && m) {
printf("m=%#lx, m->m_data=%#lx, m->m_len=%d\n",
m, m->m_data, m->m_len);
msk_dump_bytes(mtod(m, char *), m->m_len);
count -= m->m_len;
m = m->m_next;
 2223         }
 2224 }
 2225 #endif