reg1 1321 dev/ic/aic6915.c uint32_t reg0, reg1, reg2;
reg1 1324 dev/ic/aic6915.c reg1 = enaddr[3] | (enaddr[2] << 8);
reg1 1328 dev/ic/aic6915.c sf_genreg_write(sc, SF_PERFECT_BASE + (slot * 0x10) + 4, reg1);
reg1 4891 dev/ic/rtw.c u_int16_t reg0, reg1, reg2;
reg1 4901 dev/ic/rtw.c reg1 = RTW_READ16(regs, RTW8185_RFPINSENABLE);
reg1 4906 dev/ic/rtw.c RTW8185_RFPINSSELECT_ENABLE | reg1 /* XXX | SW_GPIO_CTL */);
reg1 5175 dev/ic/rtw.c rtw_barrier(void *arg, u_int32_t reg0, u_int32_t reg1, int flags)
reg1 5178 dev/ic/rtw.c bus_space_barrier(regs->r_bt, regs->r_bh, MIN(reg0, reg1),
reg1 5179 dev/ic/rtw.c MAX(reg0, reg1) - MIN(reg0, reg1) + 4, flags);
reg1 1174 dev/ic/rtwreg.h #define RTW_BARRIER(regs, reg0, reg1, flags) \
reg1 1175 dev/ic/rtwreg.h ((*(regs)->r_barrier)(regs, reg0, reg1, flags))
reg1 1181 dev/ic/rtwreg.h #define RTW_SYNC(regs, reg0, reg1) \
reg1 1182 dev/ic/rtwreg.h RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_SYNC)
reg1 1185 dev/ic/rtwreg.h #define RTW_WBW(regs, reg0, reg1) \
reg1 1186 dev/ic/rtwreg.h RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE)
reg1 1189 dev/ic/rtwreg.h #define RTW_WBR(regs, reg0, reg1) \
reg1 1190 dev/ic/rtwreg.h RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_READ)
reg1 1193 dev/ic/rtwreg.h #define RTW_RBR(regs, reg0, reg1) \
reg1 1194 dev/ic/rtwreg.h RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_READ)
reg1 1197 dev/ic/rtwreg.h #define RTW_RBW(regs, reg0, reg1) \
reg1 1198 dev/ic/rtwreg.h RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_WRITE)
reg1 1200 dev/ic/rtwreg.h #define RTW_WBRW(regs, reg0, reg1) \
reg1 1201 dev/ic/rtwreg.h RTW_BARRIER(regs, reg0, reg1, \
reg1 623 dev/isa/ess.c u_char reg1;
reg1 640 dev/isa/ess.c if ((reg1 = ess_rdsp(sc)) != 0x68) {
reg1 641 dev/isa/ess.c printf("ess: First ID byte wrong (0x%02x)\n", reg1);
reg1 655 dev/isa/ess.c sc->sc_version = (reg1 << 8) + reg2;
reg1 662 dev/isa/ess.c reg1 = ess_read_mix_reg(sc, ESS_MREG_VOLUME_CTRL);
reg1 663 dev/isa/ess.c reg2 = reg1 ^ 0x04; /* toggle bit 2 */
reg1 675 dev/isa/ess.c ess_write_mix_reg(sc, ESS_MREG_VOLUME_CTRL, reg1);
reg1 684 dev/isa/ess.c reg1 = ess_read_mix_reg(sc, ESS_MREG_SAMPLE_RATE);
reg1 685 dev/isa/ess.c reg2 = reg1 ^ 0xff; /* toggle all bits */
reg1 715 dev/isa/ess.c reg1 = ess_read_mix_reg(sc, ESS_MREG_VOLUME_CTRL);
reg1 716 dev/isa/ess.c reg2 = reg1 ^ 0x20; /* toggle bit 5 */
reg1 726 dev/isa/ess.c ess_write_mix_reg(sc, ESS_MREG_VOLUME_CTRL, reg1);
reg1 751 dev/isa/ess.c reg1 = ess_read_mix_reg(sc, 0x68);
reg1 770 dev/isa/ess.c ess_write_mix_reg(sc, 0x68, reg1);
reg1 202 dev/isa/viasio.c u_int8_t reg0, reg1;
reg1 238 dev/isa/viasio.c reg1 = viasio_conf_read(sc->sc_iot, sc->sc_ioh, VT1211_HM_ADDR_MSB);
reg1 239 dev/isa/viasio.c iobase = (reg1 << 8) | reg0;
reg1 322 dev/isa/viasio.c u_int8_t reg0, reg1;
reg1 328 dev/isa/viasio.c reg1 = bus_space_read_1(sc->sc_iot, sc->sc_hm_ioh, VT1211_HM_TCONF1);
reg1 329 dev/isa/viasio.c reg1 = VT1211_HM_TCONF1_TEMP1(reg1);
reg1 330 dev/isa/viasio.c val = (reg0 << 2) | reg1;
reg1 350 dev/isa/viasio.c reg1 = bus_space_read_1(sc->sc_iot,
reg1 352 dev/isa/viasio.c reg1 = VT1211_HM_VID4_UCH1(reg1);
reg1 354 dev/isa/viasio.c reg1 = bus_space_read_1(sc->sc_iot,
reg1 356 dev/isa/viasio.c reg1 = VT1211_HM_ETR_UCH(reg1, i);
reg1 358 dev/isa/viasio.c val = (reg0 << 2) | reg1;
reg1 398 dev/isa/viasio.c reg1 = bus_space_read_1(sc->sc_iot, sc->sc_hm_ioh, VT1211_HM_FSCTL);
reg1 399 dev/isa/viasio.c reg1 = VT1211_HM_FSCTL_DIV1(reg1);
reg1 400 dev/isa/viasio.c val = reg0 << reg1;
reg1 414 dev/isa/viasio.c reg1 = bus_space_read_1(sc->sc_iot, sc->sc_hm_ioh, VT1211_HM_FSCTL);
reg1 415 dev/isa/viasio.c reg1 = VT1211_HM_FSCTL_DIV2(reg1);
reg1 416 dev/isa/viasio.c val = reg0 << reg1;
reg1 434 dev/isa/viasio.c u_int8_t reg0, reg1;
reg1 469 dev/isa/viasio.c reg1 = viasio_conf_read(sc->sc_iot, sc->sc_ioh, VT1211_WDG_ADDR_MSB);
reg1 470 dev/isa/viasio.c iobase = (reg1 << 8) | reg0;
reg1 825 dev/pci/if_msk.c u_int32_t imtimer_ticks, reg1;
reg1 840 dev/pci/if_msk.c reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1));
reg1 842 dev/pci/if_msk.c reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA);
reg1 844 dev/pci/if_msk.c reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA);
reg1 845 dev/pci/if_msk.c sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1);