root/dev/ic/aic6915.c

DEFINITIONS

1. sf_reg_read
2. sf_reg_write
3. sf_attach
4. sf_shutdown
5. sf_start
6. sf_watchdog
7. sf_ioctl
8. sf_intr
9. sf_txintr
10. sf_rxintr
11. sf_tick
12. sf_stats_update
13. sf_reset
14. sf_macreset
15. sf_init
16. sf_rxdrain
17. sf_stop
18. sf_read_eeprom
19. sf_add_rxbuf
20. sf_set_filter_perfect
21. sf_set_filter_hash
22. sf_set_filter
23. sf_mii_read
24. sf_mii_write
25. sf_mii_statchg
26. sf_mediastatus
27. sf_mediachange

    1 /*      $OpenBSD: aic6915.c,v 1.3 2006/12/15 15:28:27 martin Exp $      */
    2 /*      $NetBSD: aic6915.c,v 1.15 2005/12/24 20:27:29 perry Exp $       */
    4 /*-
    5  * Copyright (c) 2001 The NetBSD Foundation, Inc.
    6  * All rights reserved.
    7  *
    8  * This code is derived from software contributed to The NetBSD Foundation
    9  * by Jason R. Thorpe.
   10  *
   11  * Redistribution and use in source and binary forms, with or without
   12  * modification, are permitted provided that the following conditions
   13  * are met:
   14  * 1. Redistributions of source code must retain the above copyright
   15  *    notice, this list of conditions and the following disclaimer.
   16  * 2. Redistributions in binary form must reproduce the above copyright
   17  *    notice, this list of conditions and the following disclaimer in the
   18  *    documentation and/or other materials provided with the distribution.
   19  * 3. All advertising materials mentioning features or use of this software
   20  *    must display the following acknowledgement:
   21  *      This product includes software developed by the NetBSD
   22  *      Foundation, Inc. and its contributors.
   23  * 4. Neither the name of The NetBSD Foundation nor the names of its
   24  *    contributors may be used to endorse or promote products derived
   25  *    from this software without specific prior written permission.
   26  *
   27  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   29  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   30  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   37  * POSSIBILITY OF SUCH DAMAGE.
   38  */
   40 /*
   41  * Device driver for the Adaptec AIC-6915 (``Starfire'')
   42  * 10/100 Ethernet controller.
   43  */
   45 #include "bpfilter.h"
   47 #include <sys/param.h>
   48 #include <sys/endian.h>
   49 #include <sys/systm.h>
   50 #include <sys/timeout.h>
   51 #include <sys/mbuf.h>
   52 #include <sys/malloc.h>
   53 #include <sys/kernel.h>
   54 #include <sys/socket.h>
   55 #include <sys/ioctl.h>
   56 #include <sys/errno.h>
   57 #include <sys/device.h>
   59 #include <uvm/uvm_extern.h>
   61 #include <net/if.h>
   62 #include <net/if_dl.h>
   64 #ifdef INET
   65 #include <netinet/in.h>
   66 #include <netinet/in_systm.h>
   67 #include <netinet/in_var.h>
   68 #include <netinet/ip.h>
   69 #include <netinet/if_ether.h>
   70 #endif
   72 #include <net/if_media.h>
   74 #if NBPFILTER > 0
   75 #include <net/bpf.h>
   76 #endif
   78 #include <machine/bus.h>
   79 #include <machine/intr.h>
   81 #include <dev/mii/miivar.h>
   83 #include <dev/ic/aic6915.h>
   85 void    sf_start(struct ifnet *);
   86 void    sf_watchdog(struct ifnet *);
   87 int     sf_ioctl(struct ifnet *, u_long, caddr_t);
   88 int     sf_init(struct ifnet *);
   89 void    sf_stop(struct ifnet *, int);
   91 void    sf_shutdown(void *);
   93 void    sf_txintr(struct sf_softc *);
   94 void    sf_rxintr(struct sf_softc *);
   95 void    sf_stats_update(struct sf_softc *);
   97 void    sf_reset(struct sf_softc *);
   98 void    sf_macreset(struct sf_softc *);
   99 void    sf_rxdrain(struct sf_softc *);
  100 int     sf_add_rxbuf(struct sf_softc *, int);
uint8_t sf_read_eeprom(struct sf_softc *, int);
  102 void    sf_set_filter(struct sf_softc *);
  104 int     sf_mii_read(struct device *, int, int);
  105 void    sf_mii_write(struct device *, int, int, int);
  106 void    sf_mii_statchg(struct device *);
  108 void    sf_tick(void *);
  110 int     sf_mediachange(struct ifnet *);
  111 void    sf_mediastatus(struct ifnet *, struct ifmediareq *);
uint32_t sf_reg_read(struct sf_softc *, bus_addr_t);
  114 void    sf_reg_write(struct sf_softc *, bus_addr_t , uint32_t);
  116 void    sf_set_filter_perfect(struct sf_softc *, int , uint8_t *);
  117 void    sf_set_filter_hash(struct sf_softc *, uint8_t *);
  119 struct cfdriver sf_cd = {
NULL, "sf", DV_IFNET
  121 };
  123 #define sf_funcreg_read(sc, reg)                                        \
bus_space_read_4((sc)->sc_st, (sc)->sc_sh_func, (reg))
  125 #define sf_funcreg_write(sc, reg, val)                                  \
bus_space_write_4((sc)->sc_st, (sc)->sc_sh_func, (reg), (val))
uint32_t
sf_reg_read(struct sf_softc *sc, bus_addr_t reg)
  130 {
  132         if (__predict_false(sc->sc_iomapped)) {
bus_space_write_4(sc->sc_st, sc->sc_sh, SF_IndirectIoAccess,
reg);
  135                 return (bus_space_read_4(sc->sc_st, sc->sc_sh,
SF_IndirectIoDataPort));
  137         }
  139         return (bus_space_read_4(sc->sc_st, sc->sc_sh, reg));
  140 }
  142 void
sf_reg_write(struct sf_softc *sc, bus_addr_t reg, uint32_t val)
  144 {
  146         if (__predict_false(sc->sc_iomapped)) {
bus_space_write_4(sc->sc_st, sc->sc_sh, SF_IndirectIoAccess,
reg);
bus_space_write_4(sc->sc_st, sc->sc_sh, SF_IndirectIoDataPort,
val);
  151                 return;
  152         }
bus_space_write_4(sc->sc_st, sc->sc_sh, reg, val);
  155 }
  157 #define sf_genreg_read(sc, reg)                                         \
sf_reg_read((sc), (reg) + SF_GENREG_OFFSET)
  159 #define sf_genreg_write(sc, reg, val)                                   \
sf_reg_write((sc), (reg) + SF_GENREG_OFFSET, (val))
  162 /*
  163  * sf_attach:
  164  *
  165  *      Attach a Starfire interface to the system.
  166  */
  167 void
sf_attach(struct sf_softc *sc)
  169 {
  170         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
  171         int i, rseg, error;
bus_dma_segment_t seg;
u_int8_t enaddr[ETHER_ADDR_LEN];
timeout_set(&sc->sc_mii_timeout, sf_tick, sc);
  177         /*
  178          * If we're I/O mapped, the functional register handle is
  179          * the same as the base handle.  If we're memory mapped,
  180          * carve off a chunk of the register space for the functional
  181          * registers, to save on arithmetic later.
  182          */
  183         if (sc->sc_iomapped)
sc->sc_sh_func = sc->sc_sh;
  185         else {
  186                 if ((error = bus_space_subregion(sc->sc_st, sc->sc_sh,
SF_GENREG_OFFSET, SF_FUNCREG_SIZE, &sc->sc_sh_func)) != 0) {
printf("%s: unable to sub-region functional "
  189                             "registers, error = %d\n", sc->sc_dev.dv_xname,
error);
  191                         return;
  192                 }
  193         }
  195         /*
  196          * Initialize the transmit threshold for this interface.  The
  197          * manual describes the default as 4 * 16 bytes.  We start out
  198          * at 10 * 16 bytes, to avoid a bunch of initial underruns on
  199          * several platforms.
  200          */
sc->sc_txthresh = 10;
  203         /*
  204          * Allocate the control data structures, and create and load the
  205          * DMA map for it.
  206          */
  207         if ((error = bus_dmamem_alloc(sc->sc_dmat,
  208             sizeof(struct sf_control_data), PAGE_SIZE, 0, &seg, 1, &rseg,
BUS_DMA_NOWAIT)) != 0) {
printf("%s: unable to allocate control data, error = %d\n",
sc->sc_dev.dv_xname, error);
  212                 goto fail_0;
  213         }
  215         if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
  216             sizeof(struct sf_control_data), (caddr_t *)&sc->sc_control_data,
BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
printf("%s: unable to map control data, error = %d\n",
sc->sc_dev.dv_xname, error);
  220                 goto fail_1;
  221         }
  223         if ((error = bus_dmamap_create(sc->sc_dmat,
  224             sizeof(struct sf_control_data), 1,
  225             sizeof(struct sf_control_data), 0, BUS_DMA_NOWAIT,
  226             &sc->sc_cddmamap)) != 0) {
printf("%s: unable to create control data DMA map, "
  228                     "error = %d\n", sc->sc_dev.dv_xname, error);
  229                 goto fail_2;
  230         }
  232         if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap,
sc->sc_control_data, sizeof(struct sf_control_data), NULL,
BUS_DMA_NOWAIT)) != 0) {
printf("%s: unable to load control data DMA map, error = %d\n",
sc->sc_dev.dv_xname, error);
  237                 goto fail_3;
  238         }
  240         /*
  241          * Create the transmit buffer DMA maps.
  242          */
  243         for (i = 0; i < SF_NTXDESC; i++) {
  244                 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES,
SF_NTXFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT,
  246                     &sc->sc_txsoft[i].ds_dmamap)) != 0) {
printf("%s: unable to create tx DMA map %d, "
  248                             "error = %d\n", sc->sc_dev.dv_xname, i, error);
  249                         goto fail_4;
  250                 }
  251         }
  253         /*
  254          * Create the receive buffer DMA maps.
  255          */
  256         for (i = 0; i < SF_NRXDESC; i++) {
  257                 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
MCLBYTES, 0, BUS_DMA_NOWAIT,
  259                     &sc->sc_rxsoft[i].ds_dmamap)) != 0) {
printf("%s: unable to create rx DMA map %d, "
  261                             "error = %d\n", sc->sc_dev.dv_xname, i, error);
  262                         goto fail_5;
  263                 }
  264         }
  266         /*
  267          * Reset the chip to a known state.
  268          */
sf_reset(sc);
  271         /*
  272          * Read the Ethernet address from the EEPROM.
  273          */
  274         for (i = 0; i < ETHER_ADDR_LEN; i++)
enaddr[i] = sf_read_eeprom(sc, (15 + (ETHER_ADDR_LEN - 1)) - i);
printf(", address %s\n", ether_sprintf(enaddr));
  279 #ifdef DEBUG
  280         if (sf_funcreg_read(sc, SF_PciDeviceConfig) & PDC_System64)
printf("%s: 64-bit PCI slot detected\n", sc->sc_dev.dv_xname);
  282 #endif
  284         /*
  285          * Initialize our media structures and probe the MII.
  286          */
sc->sc_mii.mii_ifp = ifp;
sc->sc_mii.mii_readreg = sf_mii_read;
sc->sc_mii.mii_writereg = sf_mii_write;
sc->sc_mii.mii_statchg = sf_mii_statchg;
ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, sf_mediachange,
sf_mediastatus);
mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
MII_OFFSET_ANY, 0);
  295         if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
  298         } else
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
bcopy(enaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN);
bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
ifp = &sc->sc_arpcom.ac_if;
ifp->if_softc = sc;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_ioctl = sf_ioctl;
ifp->if_start = sf_start;
ifp->if_watchdog = sf_watchdog;
IFQ_SET_MAXLEN(&ifp->if_snd, SF_NTXDESC_MASK);
IFQ_SET_READY(&ifp->if_snd);
  311         /*
  312          * Attach the interface.
  313          */
if_attach(ifp);
ether_ifattach(ifp);
  317         /*
  318          * Make sure the interface is shutdown during reboot.
  319          */
sc->sc_sdhook = shutdownhook_establish(sf_shutdown, sc);
  321         if (sc->sc_sdhook == NULL)
printf("%s: WARNING: unable to establish shutdown hook\n",
sc->sc_dev.dv_xname);
  324         return;
  326         /*
  327          * Free any resources we've allocated during the failed attach
  328          * attempt.  Do this in reverse order an fall through.
  329          */
fail_5:
  331         for (i = 0; i < SF_NRXDESC; i++) {
  332                 if (sc->sc_rxsoft[i].ds_dmamap != NULL)
bus_dmamap_destroy(sc->sc_dmat,
sc->sc_rxsoft[i].ds_dmamap);
  335         }
fail_4:
  337         for (i = 0; i < SF_NTXDESC; i++) {
  338                 if (sc->sc_txsoft[i].ds_dmamap != NULL)
bus_dmamap_destroy(sc->sc_dmat,
sc->sc_txsoft[i].ds_dmamap);
  341         }
bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
fail_3:
bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
fail_2:
bus_dmamem_unmap(sc->sc_dmat, (caddr_t) sc->sc_control_data,
  347             sizeof(struct sf_control_data));
fail_1:
bus_dmamem_free(sc->sc_dmat, &seg, rseg);
fail_0:
  351         return;
  352 }
  354 /*
  355  * sf_shutdown:
  356  *
  357  *      Shutdown hook -- make sure the interface is stopped at reboot.
  358  */
  359 void
sf_shutdown(void *arg)
  361 {
  362         struct sf_softc *sc = arg;
sf_stop(&sc->sc_arpcom.ac_if, 1);
  365 }
  367 /*
  368  * sf_start:            [ifnet interface function]
  369  *
  370  *      Start packet transmission on the interface.
  371  */
  372 void
sf_start(struct ifnet *ifp)
  374 {
  375         struct sf_softc *sc = ifp->if_softc;
  376         struct mbuf *m0, *m;
  377         struct sf_txdesc0 *txd;
  378         struct sf_descsoft *ds;
bus_dmamap_t dmamap;
  380         int error, producer, last = -1, opending, seg;
  382         /*
  383          * Remember the previous number of pending transmits.
  384          */
opending = sc->sc_txpending;
  387         /*
  388          * Find out where we're sitting.
  389          */
producer = SF_TXDINDEX_TO_HOST(
TDQPI_HiPrTxProducerIndex_get(
sf_funcreg_read(sc, SF_TxDescQueueProducerIndex)));
  394         /*
  395          * Loop through the send queue, setting up transmit descriptors
  396          * until we drain the queue, or use up all available transmit
  397          * descriptors.  Leave a blank one at the end for sanity's sake.
  398          */
  399         while (sc->sc_txpending < (SF_NTXDESC - 1)) {
  400                 /*
  401                  * Grab a packet off the queue.
  402                  */
IFQ_POLL(&ifp->if_snd, m0);
  404                 if (m0 == NULL)
  405                         break;
m = NULL;
  408                 /*
  409                  * Get the transmit descriptor.
  410                  */
txd = &sc->sc_txdescs[producer];
ds = &sc->sc_txsoft[producer];
dmamap = ds->ds_dmamap;
  415                 /*
  416                  * Load the DMA map.  If this fails, the packet either
  417                  * didn't fit in the allotted number of frags, or we were
  418                  * short on resources.  In this case, we'll copy and try
  419                  * again.
  420                  */
  421                 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) {
MGETHDR(m, M_DONTWAIT, MT_DATA);
  424                         if (m == NULL) {
printf("%s: unable to allocate Tx mbuf\n",
sc->sc_dev.dv_xname);
  427                                 break;
  428                         }
  429                         if (m0->m_pkthdr.len > MHLEN) {
MCLGET(m, M_DONTWAIT);
  431                                 if ((m->m_flags & M_EXT) == 0) {
printf("%s: unable to allocate Tx "
  433                                             "cluster\n", sc->sc_dev.dv_xname);
m_freem(m);
  435                                         break;
  436                                 }
  437                         }
m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t));
m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap,
m, BUS_DMA_WRITE|BUS_DMA_NOWAIT);
  442                         if (error) {
printf("%s: unable to load Tx buffer, "
  444                                     "error = %d\n", sc->sc_dev.dv_xname, error);
  445                                 break;
  446                         }
  447                 }
  449                 /*
  450                  * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
  451                  */
IFQ_DEQUEUE(&ifp->if_snd, m0);
  453                 if (m != NULL) {
m_freem(m0);
m0 = m;
  456                 }
  458                 /* Initialize the descriptor. */
txd->td_word0 =
htole32(TD_W0_ID | TD_W0_CRCEN | m0->m_pkthdr.len);
  461                 if (producer == (SF_NTXDESC - 1))
txd->td_word0 |= TD_W0_END;
txd->td_word1 = htole32(dmamap->dm_nsegs);
  464                 for (seg = 0; seg < dmamap->dm_nsegs; seg++) {
txd->td_frags[seg].fr_addr =
htole32(dmamap->dm_segs[seg].ds_addr);
txd->td_frags[seg].fr_len =
htole32(dmamap->dm_segs[seg].ds_len);
  469                 }
  471                 /* Sync the descriptor and the DMA map. */
SF_CDTXDSYNC(sc, producer, BUS_DMASYNC_PREWRITE);
bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
BUS_DMASYNC_PREWRITE);
  476                 /*
  477                  * Store a pointer to the packet so we can free it later.
  478                  */
ds->ds_mbuf = m0;
  481                 /* Advance the Tx pointer. */
sc->sc_txpending++;
last = producer;
producer = SF_NEXTTX(producer);
  486 #if NBPFILTER > 0
  487                 /*
  488                  * Pass the packet to any BPF listeners.
  489                  */
  490                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m0, BPF_DIRECTION_OUT);
  492 #endif
  493         }
  495         if (sc->sc_txpending == (SF_NTXDESC - 1)) {
  496                 /* No more slots left; notify upper layer. */
ifp->if_flags |= IFF_OACTIVE;
  498         }
  500         if (sc->sc_txpending != opending) {
KASSERT(last != -1);
  502                 /*
  503                  * We enqueued packets.  Cause a transmit interrupt to
  504                  * happen on the last packet we enqueued, and give the
  505                  * new descriptors to the chip by writing the new
  506                  * producer index.
  507                  */
sc->sc_txdescs[last].td_word0 |= TD_W0_INTR;
SF_CDTXDSYNC(sc, last, BUS_DMASYNC_PREWRITE);
sf_funcreg_write(sc, SF_TxDescQueueProducerIndex,
TDQPI_HiPrTxProducerIndex(SF_TXDINDEX_TO_CHIP(producer)));
  514                 /* Set a watchdog timer in case the chip flakes out. */
ifp->if_timer = 5;
  516         }
  517 }
  519 /*
  520  * sf_watchdog:         [ifnet interface function]
  521  *
  522  *      Watchdog timer handler.
  523  */
  524 void
sf_watchdog(struct ifnet *ifp)
  526 {
  527         struct sf_softc *sc = ifp->if_softc;
printf("%s: device timeout\n", sc->sc_dev.dv_xname);
ifp->if_oerrors++;
  532         (void) sf_init(ifp);
  534         /* Try to get more packets going. */
sf_start(ifp);
  536 }
  538 /*
  539  * sf_ioctl:            [ifnet interface function]
  540  *
  541  *      Handle control requests from the operator.
  542  */
  543 int
sf_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
  545 {
  546         struct sf_softc *sc = (struct sf_softc *)ifp->if_softc;
  547         struct ifaddr *ifa = (struct ifaddr *)data;
  548         struct ifreq *ifr = (struct ifreq *) data;
  549         int s, error = 0;
s = splnet();
  553         if ((error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data)) > 0) {
splx(s);
  555                 return (error);
  556         }
  558         switch (cmd) {
  559         case SIOCSIFADDR:
ifp->if_flags |= IFF_UP;
  561                 if (!(ifp->if_flags & IFF_RUNNING))
sf_init(ifp);
  563 #ifdef INET
  564                 if (ifa->ifa_addr->sa_family == AF_INET)
arp_ifinit(&sc->sc_arpcom, ifa);
  566 #endif
  567                 break;
  569         case SIOCSIFFLAGS:
  570                 if (ifp->if_flags & IFF_UP) {
  571                         if (ifp->if_flags & IFF_RUNNING &&
  572                             ((ifp->if_flags ^ sc->sc_flags) &
IFF_PROMISC)) {
sf_set_filter(sc);
  575                         } else {
  576                                 if (!(ifp->if_flags & IFF_RUNNING))
sf_init(ifp);
  578                         }
  579                 } else {
  580                         if (ifp->if_flags & IFF_RUNNING)
sf_stop(ifp, 1);
  582                 }
sc->sc_flags = ifp->if_flags;
  584                 break;
  586         case SIOCSIFMTU:
  587                 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ifp->if_hardmtu)
error = EINVAL;
  589                 else if (ifp->if_mtu != ifr->ifr_mtu)
ifp->if_mtu = ifr->ifr_mtu;
  591                 break;
  593         case SIOCADDMULTI:
  594         case SIOCDELMULTI:
ifr = (struct ifreq *)data;
error = (cmd == SIOCADDMULTI) ?
ether_addmulti(ifr, &sc->sc_arpcom) :
ether_delmulti(ifr, &sc->sc_arpcom);
  600                 if (error == ENETRESET) {
  601                         if (ifp->if_flags & IFF_RUNNING)
sf_set_filter(sc);
error = 0;
  604                 }
  605                 break;
  607         case SIOCGIFMEDIA:
  608         case SIOCSIFMEDIA:
error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
  610                 break;
  612         default:
error = ENOTTY;
  614         }
  616         /* Try to get more packets going. */
sf_start(ifp);
splx(s);
  620         return (error);
  621 }
  623 /*
  624  * sf_intr:
  625  *
  626  *      Interrupt service routine.
  627  */
  628 int
sf_intr(void *arg)
  630 {
  631         struct sf_softc *sc = arg;
uint32_t isr;
  633         int handled = 0, wantinit = 0;
  635         for (;;) {
  636                 /* Reading clears all interrupts we're interested in. */
isr = sf_funcreg_read(sc, SF_InterruptStatus);
  638                 if ((isr & IS_PCIPadInt) == 0)
  639                         break;
handled = 1;
  643                 /* Handle receive interrupts. */
  644                 if (isr & IS_RxQ1DoneInt)
sf_rxintr(sc);
  647                 /* Handle transmit completion interrupts. */
  648                 if (isr & (IS_TxDmaDoneInt|IS_TxQueueDoneInt))
sf_txintr(sc);
  651                 /* Handle abnormal interrupts. */
  652                 if (isr & IS_AbnormalInterrupt) {
  653                         /* Statistics. */
  654                         if (isr & IS_StatisticWrapInt)
sf_stats_update(sc);
  657                         /* DMA errors. */
  658                         if (isr & IS_DmaErrInt) {
wantinit = 1;
printf("%s: WARNING: DMA error\n",
sc->sc_dev.dv_xname);
  662                         }
  664                         /* Transmit FIFO underruns. */
  665                         if (isr & IS_TxDataLowInt) {
  666                                 if (sc->sc_txthresh < 0xff)
sc->sc_txthresh++;
  668 #ifdef DEBUG
printf("%s: transmit FIFO underrun, new "
  670                                     "threshold: %d bytes\n",
sc->sc_dev.dv_xname,
sc->sc_txthresh * 16);
  673 #endif
sf_funcreg_write(sc, SF_TransmitFrameCSR,
sc->sc_TransmitFrameCSR |
TFCSR_TransmitThreshold(sc->sc_txthresh));
sf_funcreg_write(sc, SF_TxDescQueueCtrl,
sc->sc_TxDescQueueCtrl |
TDQC_TxHighPriorityFifoThreshold(
sc->sc_txthresh));
  681                         }
  682                 }
  683         }
  685         if (handled) {
  686                 /* Reset the interface, if necessary. */
  687                 if (wantinit)
sf_init(&sc->sc_arpcom.ac_if);
  690                 /* Try and get more packets going. */
sf_start(&sc->sc_arpcom.ac_if);
  692         }
  694         return (handled);
  695 }
  697 /*
  698  * sf_txintr:
  699  *
  700  *      Helper -- handle transmit completion interrupts.
  701  */
  702 void
sf_txintr(struct sf_softc *sc)
  704 {
  705         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
  706         struct sf_descsoft *ds;
uint32_t cqci, tcd;
  708         int consumer, producer, txidx;
try_again:
cqci = sf_funcreg_read(sc, SF_CompletionQueueConsumerIndex);
consumer = CQCI_TxCompletionConsumerIndex_get(cqci);
producer = CQPI_TxCompletionProducerIndex_get(
sf_funcreg_read(sc, SF_CompletionQueueProducerIndex));
  717         if (consumer == producer)
  718                 return;
ifp->if_flags &= ~IFF_OACTIVE;
  722         while (consumer != producer) {
SF_CDTXCSYNC(sc, consumer, BUS_DMASYNC_POSTREAD);
tcd = letoh32(sc->sc_txcomp[consumer].tcd_word0);
txidx = SF_TCD_INDEX_TO_HOST(TCD_INDEX(tcd));
  727 #ifdef DIAGNOSTIC
  728                 if ((tcd & TCD_PR) == 0)
printf("%s: Tx queue mismatch, index %d\n",
sc->sc_dev.dv_xname, txidx);
  731 #endif
  732                 /*
  733                  * NOTE: stats are updated later.  We're just
  734                  * releasing packets that have been DMA'd to
  735                  * the chip.
  736                  */
ds = &sc->sc_txsoft[txidx];
SF_CDTXDSYNC(sc, txidx, BUS_DMASYNC_POSTWRITE);
bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap,
  740                     0, ds->ds_dmamap->dm_mapsize,
BUS_DMASYNC_POSTWRITE);
m_freem(ds->ds_mbuf);
ds->ds_mbuf = NULL;
consumer = SF_NEXTTCD(consumer);
sc->sc_txpending--;
  747         }
  749         /* XXXJRT -- should be KDASSERT() */
KASSERT(sc->sc_txpending >= 0);
  752         /* If all packets are done, cancel the watchdog timer. */
  753         if (sc->sc_txpending == 0)
ifp->if_timer = 0;
  756         /* Update the consumer index. */
sf_funcreg_write(sc, SF_CompletionQueueConsumerIndex,
  758             (cqci & ~CQCI_TxCompletionConsumerIndex(0x7ff)) |
CQCI_TxCompletionConsumerIndex(consumer));
  761         /* Double check for new completions. */
  762         goto try_again;
  763 }
  765 /*
  766  * sf_rxintr:
  767  *
  768  *      Helper -- handle receive interrupts.
  769  */
  770 void
sf_rxintr(struct sf_softc *sc)
  772 {
  773         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
  774         struct sf_descsoft *ds;
  775         struct sf_rcd_full *rcd;
  776         struct mbuf *m;
uint32_t cqci, word0;
  778         int consumer, producer, bufproducer, rxidx, len;
try_again:
cqci = sf_funcreg_read(sc, SF_CompletionQueueConsumerIndex);
consumer = CQCI_RxCompletionQ1ConsumerIndex_get(cqci);
producer = CQPI_RxCompletionQ1ProducerIndex_get(
sf_funcreg_read(sc, SF_CompletionQueueProducerIndex));
bufproducer = RXQ1P_RxDescQ1Producer_get(
sf_funcreg_read(sc, SF_RxDescQueue1Ptrs));
  789         if (consumer == producer)
  790                 return;
  792         while (consumer != producer) {
rcd = &sc->sc_rxcomp[consumer];
SF_CDRXCSYNC(sc, consumer,
BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
SF_CDRXCSYNC(sc, consumer,
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
word0 = letoh32(rcd->rcd_word0);
rxidx = RCD_W0_EndIndex(word0);
ds = &sc->sc_rxsoft[rxidx];
consumer = SF_NEXTRCD(consumer);
bufproducer = SF_NEXTRX(bufproducer);
  807                 if ((word0 & RCD_W0_OK) == 0) {
SF_INIT_RXDESC(sc, rxidx);
  809                         continue;
  810                 }
bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
  815                 /*
  816                  * No errors; receive the packet.  Note that we have
  817                  * configured the Starfire to NOT transfer the CRC
  818                  * with the packet.
  819                  */
len = RCD_W0_Length(word0);
  822 #ifndef __STRICT_ALIGNMENT
  823                 /*
  824                  * Allocate a new mbuf cluster.  If that fails, we are
  825                  * out of memory, and must drop the packet and recycle
  826                  * the buffer that's already attached to this descriptor.
  827                  */
m = ds->ds_mbuf;
  829                 if (sf_add_rxbuf(sc, rxidx) != 0) {
ifp->if_ierrors++;
SF_INIT_RXDESC(sc, rxidx);
bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
  834                         continue;
  835                 }
  836 #else
  837                 /*
  838                  * The Starfire's receive buffer must be 4-byte aligned.
  839                  * But this means that the data after the Ethernet header
  840                  * is misaligned.  We must allocate a new buffer and
  841                  * copy the data, shifted forward 2 bytes.
  842                  */
MGETHDR(m, M_DONTWAIT, MT_DATA);
  844                 if (m == NULL) {
dropit:
ifp->if_ierrors++;
SF_INIT_RXDESC(sc, rxidx);
bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
  850                         continue;
  851                 }
  852                 if (len > (MHLEN - 2)) {
MCLGET(m, M_DONTWAIT);
  854                         if ((m->m_flags & M_EXT) == 0) {
m_freem(m);
  856                                 goto dropit;
  857                         }
  858                 }
m->m_data += 2;
  861                 /*
  862                  * Note that we use cluster for incoming frames, so the
  863                  * buffer is virtually contiguous.
  864                  */
memcpy(mtod(m, caddr_t), mtod(ds->ds_mbuf, caddr_t), len);
  867                 /* Allow the receive descriptor to continue using its mbuf. */
SF_INIT_RXDESC(sc, rxidx);
bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
  871 #endif /* __STRICT_ALIGNMENT */
m->m_pkthdr.rcvif = ifp;
m->m_pkthdr.len = m->m_len = len;
  876 #if NBPFILTER > 0
  877                 /*
  878                  * Pass this up to any BPF listeners.
  879                  */
  880                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN);
  882 #endif /* NBPFILTER > 0 */
  884                 /* Pass it on. */
ether_input_mbuf(ifp, m);
ifp->if_ipackets++;
  887         }
  889         /* Update the chip's pointers. */
sf_funcreg_write(sc, SF_CompletionQueueConsumerIndex,
  891             (cqci & ~CQCI_RxCompletionQ1ConsumerIndex(0x7ff)) |
CQCI_RxCompletionQ1ConsumerIndex(consumer));
sf_funcreg_write(sc, SF_RxDescQueue1Ptrs,
RXQ1P_RxDescQ1Producer(bufproducer));
  896         /* Double-check for any new completions. */
  897         goto try_again;
  898 }
  900 /*
  901  * sf_tick:
  902  *
  903  *      One second timer, used to tick the MII and update stats.
  904  */
  905 void
sf_tick(void *arg)
  907 {
  908         struct sf_softc *sc = arg;
  909         int s;
s = splnet();
mii_tick(&sc->sc_mii);
sf_stats_update(sc);
splx(s);
timeout_add(&sc->sc_mii_timeout, hz);
  917 }
  919 /*
  920  * sf_stats_update:
  921  *
  922  *      Read the statitistics counters.
  923  */
  924 void
sf_stats_update(struct sf_softc *sc)
  926 {
  927         struct sf_stats stats;
  928         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
uint32_t *p;
u_int i;
p = &stats.TransmitOKFrames;
  933         for (i = 0; i < (sizeof(stats) / sizeof(uint32_t)); i++) {
  934                 *p++ = sf_genreg_read(sc,
SF_STATS_BASE + (i * sizeof(uint32_t)));
sf_genreg_write(sc, SF_STATS_BASE + (i * sizeof(uint32_t)), 0);
  937         }
ifp->if_opackets += stats.TransmitOKFrames;
ifp->if_collisions += stats.SingleCollisionFrames +
stats.MultipleCollisionFrames;
ifp->if_oerrors += stats.TransmitAbortDueToExcessiveCollisions +
stats.TransmitAbortDueToExcessingDeferral +
stats.FramesLostDueToInternalTransmitErrors;
ifp->if_ipackets += stats.ReceiveOKFrames;
ifp->if_ierrors += stats.ReceiveCRCErrors + stats.AlignmentErrors +
stats.ReceiveFramesTooLong + stats.ReceiveFramesTooShort +
stats.ReceiveFramesJabbersError +
stats.FramesLostDueToInternalReceiveErrors;
  954 }
  956 /*
  957  * sf_reset:
  958  *
  959  *      Perform a soft reset on the Starfire.
  960  */
  961 void
sf_reset(struct sf_softc *sc)
  963 {
  964         int i;
sf_funcreg_write(sc, SF_GeneralEthernetCtrl, 0);
sf_macreset(sc);
sf_funcreg_write(sc, SF_PciDeviceConfig, PDC_SoftReset);
  971         for (i = 0; i < 1000; i++) {
delay(10);
  973                 if ((sf_funcreg_read(sc, SF_PciDeviceConfig) &
PDC_SoftReset) == 0)
  975                         break;
  976         }
  978         if (i == 1000) {
printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname);
sf_funcreg_write(sc, SF_PciDeviceConfig, 0);
  981         }
delay(1000);
  984 }
  986 /*
  987  * sf_macreset:
  988  *
  989  *      Reset the MAC portion of the Starfire.
  990  */
  991 void
sf_macreset(struct sf_softc *sc)
  993 {
sf_genreg_write(sc, SF_MacConfig1, sc->sc_MacConfig1 | MC1_SoftRst);
delay(1000);
sf_genreg_write(sc, SF_MacConfig1, sc->sc_MacConfig1);
  998 }
 1000 /*
 1001  * sf_init:             [ifnet interface function]
 1002  *
 1003  *      Initialize the interface.  Must be called at splnet().
 1004  */
 1005 int
sf_init(struct ifnet *ifp)
 1007 {
 1008         struct sf_softc *sc = ifp->if_softc;
 1009         struct sf_descsoft *ds;
 1010         int error = 0;
u_int i;
 1013         /*
 1014          * Cancel any pending I/O.
 1015          */
sf_stop(ifp, 0);
 1018         /*
 1019          * Reset the Starfire to a known state.
 1020          */
sf_reset(sc);
 1023         /* Clear the stat counters. */
 1024         for (i = 0; i < sizeof(struct sf_stats); i += sizeof(uint32_t))
sf_genreg_write(sc, SF_STATS_BASE + i, 0);
 1027         /*
 1028          * Initialize the transmit descriptor ring.
 1029          */
memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
sf_funcreg_write(sc, SF_TxDescQueueHighAddr, 0);
sf_funcreg_write(sc, SF_HiPrTxDescQueueBaseAddr, SF_CDTXDADDR(sc, 0));
sf_funcreg_write(sc, SF_LoPrTxDescQueueBaseAddr, 0);
 1035         /*
 1036          * Initialize the transmit completion ring.
 1037          */
 1038         for (i = 0; i < SF_NTCD; i++) {
sc->sc_txcomp[i].tcd_word0 = TCD_DMA_ID;
SF_CDTXCSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
 1041         }
sf_funcreg_write(sc, SF_CompletionQueueHighAddr, 0);
sf_funcreg_write(sc, SF_TxCompletionQueueCtrl, SF_CDTXCADDR(sc, 0));
 1045         /*
 1046          * Initialize the receive descriptor ring.
 1047          */
 1048         for (i = 0; i < SF_NRXDESC; i++) {
ds = &sc->sc_rxsoft[i];
 1050                 if (ds->ds_mbuf == NULL) {
 1051                         if ((error = sf_add_rxbuf(sc, i)) != 0) {
printf("%s: unable to allocate or map rx "
 1053                                     "buffer %d, error = %d\n",
sc->sc_dev.dv_xname, i, error);
 1055                                 /*
 1056                                  * XXX Should attempt to run with fewer receive
 1057                                  * XXX buffers instead of just failing.
 1058                                  */
sf_rxdrain(sc);
 1060                                 goto out;
 1061                         }
 1062                 } else
SF_INIT_RXDESC(sc, i);
 1064         }
sf_funcreg_write(sc, SF_RxDescQueueHighAddress, 0);
sf_funcreg_write(sc, SF_RxDescQueue1LowAddress, SF_CDRXDADDR(sc, 0));
sf_funcreg_write(sc, SF_RxDescQueue2LowAddress, 0);
 1069         /*
 1070          * Initialize the receive completion ring.
 1071          */
 1072         for (i = 0; i < SF_NRCD; i++) {
sc->sc_rxcomp[i].rcd_word0 = RCD_W0_ID;
sc->sc_rxcomp[i].rcd_word1 = 0;
sc->sc_rxcomp[i].rcd_word2 = 0;
sc->sc_rxcomp[i].rcd_timestamp = 0;
SF_CDRXCSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
 1078         }
sf_funcreg_write(sc, SF_RxCompletionQueue1Ctrl, SF_CDRXCADDR(sc, 0) |
RCQ1C_RxCompletionQ1Type(3));
sf_funcreg_write(sc, SF_RxCompletionQueue2Ctrl, 0);
 1083         /*
 1084          * Initialize the Tx CSR.
 1085          */
sc->sc_TransmitFrameCSR = 0;
sf_funcreg_write(sc, SF_TransmitFrameCSR,
sc->sc_TransmitFrameCSR |
TFCSR_TransmitThreshold(sc->sc_txthresh));
 1091         /*
 1092          * Initialize the Tx descriptor control register.
 1093          */
sc->sc_TxDescQueueCtrl = TDQC_SkipLength(0) |
TDQC_TxDmaBurstSize(4) |    /* default */
TDQC_MinFrameSpacing(3) |   /* 128 bytes */
TDQC_TxDescType(0);
sf_funcreg_write(sc, SF_TxDescQueueCtrl,
sc->sc_TxDescQueueCtrl |
TDQC_TxHighPriorityFifoThreshold(sc->sc_txthresh));
 1102         /*
 1103          * Initialize the Rx descriptor control registers.
 1104          */
sf_funcreg_write(sc, SF_RxDescQueue1Ctrl,
RDQ1C_RxQ1BufferLength(MCLBYTES) |
RDQ1C_RxDescSpacing(0));
sf_funcreg_write(sc, SF_RxDescQueue2Ctrl, 0);
 1110         /*
 1111          * Initialize the Tx descriptor producer indices.
 1112          */
sf_funcreg_write(sc, SF_TxDescQueueProducerIndex,
TDQPI_HiPrTxProducerIndex(0) |
TDQPI_LoPrTxProducerIndex(0));
 1117         /*
 1118          * Initialize the Rx descriptor producer indices.
 1119          */
sf_funcreg_write(sc, SF_RxDescQueue1Ptrs,
RXQ1P_RxDescQ1Producer(SF_NRXDESC - 1));
sf_funcreg_write(sc, SF_RxDescQueue2Ptrs,
RXQ2P_RxDescQ2Producer(0));
 1125         /*
 1126          * Initialize the Tx and Rx completion queue consumer indices.
 1127          */
sf_funcreg_write(sc, SF_CompletionQueueConsumerIndex,
CQCI_TxCompletionConsumerIndex(0) |
CQCI_RxCompletionQ1ConsumerIndex(0));
sf_funcreg_write(sc, SF_RxHiPrCompletionPtrs, 0);
 1133         /*
 1134          * Initialize the Rx DMA control register.
 1135          */
sf_funcreg_write(sc, SF_RxDmaCtrl,
RDC_RxHighPriorityThreshold(6) |    /* default */
RDC_RxBurstSize(4));                /* default */
 1140         /*
 1141          * Set the receive filter.
 1142          */
sc->sc_RxAddressFilteringCtl = 0;
sf_set_filter(sc);
 1146         /*
 1147          * Set MacConfig1.  When we set the media, MacConfig1 will
 1148          * actually be written and the MAC part reset.
 1149          */
sc->sc_MacConfig1 = MC1_PadEn;
 1152         /*
 1153          * Set the media.
 1154          */
mii_mediachg(&sc->sc_mii);
 1157         /*
 1158          * Initialize the interrupt register.
 1159          */
sc->sc_InterruptEn = IS_PCIPadInt | IS_RxQ1DoneInt |
IS_TxQueueDoneInt | IS_TxDmaDoneInt | IS_DmaErrInt |
IS_StatisticWrapInt;
sf_funcreg_write(sc, SF_InterruptEn, sc->sc_InterruptEn);
sf_funcreg_write(sc, SF_PciDeviceConfig, PDC_IntEnable |
PDC_PCIMstDmaEn | (1 << PDC_FifoThreshold_SHIFT));
 1168         /*
 1169          * Start the transmit and receive processes.
 1170          */
sf_funcreg_write(sc, SF_GeneralEthernetCtrl,
GEC_TxDmaEn|GEC_RxDmaEn|GEC_TransmitEn|GEC_ReceiveEn);
 1174         /* Start the on second clock. */
timeout_add(&sc->sc_mii_timeout, hz);
 1177         /*
 1178          * Note that the interface is now running.
 1179          */
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
out:
 1184         if (error) {
ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
ifp->if_timer = 0;
printf("%s: interface not running\n", sc->sc_dev.dv_xname);
 1188         }
 1189         return (error);
 1190 }
 1192 /*
 1193  * sf_rxdrain:
 1194  *
 1195  *      Drain the receive queue.
 1196  */
 1197 void
sf_rxdrain(struct sf_softc *sc)
 1199 {
 1200         struct sf_descsoft *ds;
 1201         int i;
 1203         for (i = 0; i < SF_NRXDESC; i++) {
ds = &sc->sc_rxsoft[i];
 1205                 if (ds->ds_mbuf != NULL) {
bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
m_freem(ds->ds_mbuf);
ds->ds_mbuf = NULL;
 1209                 }
 1210         }
 1211 }
 1213 /*
 1214  * sf_stop:             [ifnet interface function]
 1215  *
 1216  *      Stop transmission on the interface.
 1217  */
 1218 void
sf_stop(struct ifnet *ifp, int disable)
 1220 {
 1221         struct sf_softc *sc = ifp->if_softc;
 1222         struct sf_descsoft *ds;
 1223         int i;
 1225         /* Stop the one second clock. */
timeout_del(&sc->sc_mii_timeout);
 1228         /* Down the MII. */
mii_down(&sc->sc_mii);
 1231         /* Disable interrupts. */
sf_funcreg_write(sc, SF_InterruptEn, 0);
 1234         /* Stop the transmit and receive processes. */
sf_funcreg_write(sc, SF_GeneralEthernetCtrl, 0);
 1237         /*
 1238          * Release any queued transmit buffers.
 1239          */
 1240         for (i = 0; i < SF_NTXDESC; i++) {
ds = &sc->sc_txsoft[i];
 1242                 if (ds->ds_mbuf != NULL) {
bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
m_freem(ds->ds_mbuf);
ds->ds_mbuf = NULL;
 1246                 }
 1247         }
 1249         if (disable)
sf_rxdrain(sc);
 1252         /*
 1253          * Mark the interface down and cancel the watchdog timer.
 1254          */
ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
ifp->if_timer = 0;
 1257 }
 1259 /*
 1260  * sf_read_eeprom:
 1261  *
 1262  *      Read from the Starfire EEPROM.
 1263  */
uint8_t
sf_read_eeprom(struct sf_softc *sc, int offset)
 1266 {
uint32_t reg;
reg = sf_genreg_read(sc, SF_EEPROM_BASE + (offset & ~3));
 1271         return ((reg >> (8 * (offset & 3))) & 0xff);
 1272 }
 1274 /*
 1275  * sf_add_rxbuf:
 1276  *
 1277  *      Add a receive buffer to the indicated descriptor.
 1278  */
 1279 int
sf_add_rxbuf(struct sf_softc *sc, int idx)
 1281 {
 1282         struct sf_descsoft *ds = &sc->sc_rxsoft[idx];
 1283         struct mbuf *m;
 1284         int error;
MGETHDR(m, M_DONTWAIT, MT_DATA);
 1287         if (m == NULL)
 1288                 return (ENOBUFS);
MCLGET(m, M_DONTWAIT);
 1291         if ((m->m_flags & M_EXT) == 0) {
m_freem(m);
 1293                 return (ENOBUFS);
 1294         }
 1296         if (ds->ds_mbuf != NULL)
bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
ds->ds_mbuf = m;
error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap,
m->m_ext.ext_buf, m->m_ext.ext_size, NULL,
BUS_DMA_READ|BUS_DMA_NOWAIT);
 1304         if (error) {
printf("%s: can't load rx DMA map %d, error = %d\n",
sc->sc_dev.dv_xname, idx, error);
panic("sf_add_rxbuf"); /* XXX */
 1308         }
bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
SF_INIT_RXDESC(sc, idx);
 1315         return (0);
 1316 }
 1318 void
sf_set_filter_perfect(struct sf_softc *sc, int slot, uint8_t *enaddr)
 1320 {
uint32_t reg0, reg1, reg2;
reg0 = enaddr[5] | (enaddr[4] << 8);
reg1 = enaddr[3] | (enaddr[2] << 8);
reg2 = enaddr[1] | (enaddr[0] << 8);
sf_genreg_write(sc, SF_PERFECT_BASE + (slot * 0x10) + 0, reg0);
sf_genreg_write(sc, SF_PERFECT_BASE + (slot * 0x10) + 4, reg1);
sf_genreg_write(sc, SF_PERFECT_BASE + (slot * 0x10) + 8, reg2);
 1330 }
 1332 void
sf_set_filter_hash(struct sf_softc *sc, uint8_t *enaddr)
 1334 {
uint32_t hash, slot, reg;
hash = ether_crc32_be(enaddr, ETHER_ADDR_LEN) >> 23;
slot = hash >> 4;
reg = sf_genreg_read(sc, SF_HASH_BASE + (slot * 0x10));
reg |= 1 << (hash & 0xf);
sf_genreg_write(sc, SF_HASH_BASE + (slot * 0x10), reg);
 1343 }
 1345 /*
 1346  * sf_set_filter:
 1347  *
 1348  *      Set the Starfire receive filter.
 1349  */
 1350 void
sf_set_filter(struct sf_softc *sc)
 1352 {
 1353         struct arpcom *ac = &sc->sc_arpcom;
 1354         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
 1355         struct ether_multi *enm;
 1356         struct ether_multistep step;
 1357         int i;
 1359         /* Start by clearing the perfect and hash tables. */
 1360         for (i = 0; i < SF_PERFECT_SIZE; i += sizeof(uint32_t))
sf_genreg_write(sc, SF_PERFECT_BASE + i, 0);
 1363         for (i = 0; i < SF_HASH_SIZE; i += sizeof(uint32_t))
sf_genreg_write(sc, SF_HASH_BASE + i, 0);
 1366         /*
 1367          * Clear the perfect and hash mode bits.
 1368          */
sc->sc_RxAddressFilteringCtl &=
 1370             ~(RAFC_PerfectFilteringMode(3) | RAFC_HashFilteringMode(3));
 1372         if (ifp->if_flags & IFF_BROADCAST)
sc->sc_RxAddressFilteringCtl |= RAFC_PassBroadcast;
 1374         else
sc->sc_RxAddressFilteringCtl &= ~RAFC_PassBroadcast;
 1377         if (ifp->if_flags & IFF_PROMISC) {
sc->sc_RxAddressFilteringCtl |= RAFC_PromiscuousMode;
 1379                 goto allmulti;
 1380         } else
sc->sc_RxAddressFilteringCtl &= ~RAFC_PromiscuousMode;
 1383         /*
 1384          * Set normal perfect filtering mode.
 1385          */
sc->sc_RxAddressFilteringCtl |= RAFC_PerfectFilteringMode(1);
 1388         /*
 1389          * First, write the station address to the perfect filter
 1390          * table.
 1391          */
sf_set_filter_perfect(sc, 0, LLADDR(ifp->if_sadl));
 1394         /*
 1395          * Now set the hash bits for each multicast address in our
 1396          * list.
 1397          */
ETHER_FIRST_MULTI(step, ac, enm);
 1399         if (enm == NULL)
 1400                 goto done;
 1401         while (enm != NULL) {
 1402                 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
 1403                         /*
 1404                          * We must listen to a range of multicast addresses.
 1405                          * For now, just accept all multicasts, rather than
 1406                          * trying to set only those filter bits needed to match
 1407                          * the range.  (At this time, the only use of address
 1408                          * ranges is for IP multicast routing, for which the
 1409                          * range is big enough to require all bits set.)
 1410                          */
 1411                         goto allmulti;
 1412                 }
sf_set_filter_hash(sc, enm->enm_addrlo);
ETHER_NEXT_MULTI(step, enm);
 1415         }
 1417         /*
 1418          * Set "hash only multicast dest, match regardless of VLAN ID".
 1419          */
sc->sc_RxAddressFilteringCtl |= RAFC_HashFilteringMode(2);
 1421         goto done;
allmulti:
 1424         /*
 1425          * XXX RAFC_PassMulticast is sub-optimal if using VLAN mode.
 1426          */
sc->sc_RxAddressFilteringCtl |= RAFC_PassMulticast;
ifp->if_flags |= IFF_ALLMULTI;
done:
sf_funcreg_write(sc, SF_RxAddressFilteringCtl,
sc->sc_RxAddressFilteringCtl);
 1433 }
 1435 /*
 1436  * sf_mii_read:         [mii interface function]
 1437  *
 1438  *      Read from the MII.
 1439  */
 1440 int
sf_mii_read(struct device *self, int phy, int reg)
 1442 {
 1443         struct sf_softc *sc = (void *) self;
uint32_t v;
 1445         int i;
 1447         for (i = 0; i < 1000; i++) {
v = sf_genreg_read(sc, SF_MII_PHY_REG(phy, reg));
 1449                 if (v & MiiDataValid)
 1450                         break;
delay(1);
 1452         }
 1454         if ((v & MiiDataValid) == 0)
 1455                 return (0);
 1457         if (MiiRegDataPort(v) == 0xffff)
 1458                 return (0);
 1460         return (MiiRegDataPort(v));
 1461 }
 1463 /*
 1464  * sf_mii_write:        [mii interface function]
 1465  *
 1466  *      Write to the MII.
 1467  */
 1468 void
sf_mii_write(struct device *self, int phy, int reg, int val)
 1470 {
 1471         struct sf_softc *sc = (void *) self;
 1472         int i;
sf_genreg_write(sc, SF_MII_PHY_REG(phy, reg), val);
 1476         for (i = 0; i < 1000; i++) {
 1477                 if ((sf_genreg_read(sc, SF_MII_PHY_REG(phy, reg)) &
MiiBusy) == 0)
 1479                         return;
delay(1);
 1481         }
printf("%s: MII write timed out\n", sc->sc_dev.dv_xname);
 1484 }
 1486 /*
 1487  * sf_mii_statchg:      [mii interface function]
 1488  *
 1489  *      Callback from the PHY when the media changes.
 1490  */
 1491 void
sf_mii_statchg(struct device *self)
 1493 {
 1494         struct sf_softc *sc = (void *) self;
uint32_t ipg;
 1497         if (sc->sc_mii.mii_media_active & IFM_FDX) {
sc->sc_MacConfig1 |= MC1_FullDuplex;
ipg = 0x15;
 1500         } else {
sc->sc_MacConfig1 &= ~MC1_FullDuplex;
ipg = 0x11;
 1503         }
sf_genreg_write(sc, SF_MacConfig1, sc->sc_MacConfig1);
sf_macreset(sc);
sf_genreg_write(sc, SF_BkToBkIPG, ipg);
 1509 }
 1511 /*
 1512  * sf_mediastatus:      [ifmedia interface function]
 1513  *
 1514  *      Callback from ifmedia to request current media status.
 1515  */
 1516 void
sf_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
 1518 {
 1519         struct sf_softc *sc = ifp->if_softc;
mii_pollstat(&sc->sc_mii);
ifmr->ifm_status = sc->sc_mii.mii_media_status;
ifmr->ifm_active = sc->sc_mii.mii_media_active;
 1524 }
 1526 /*
 1527  * sf_mediachange:      [ifmedia interface function]
 1528  *
 1529  *      Callback from ifmedia to request new media setting.
 1530  */
 1531 int
sf_mediachange(struct ifnet *ifp)
 1533 {
 1534         struct sf_softc *sc = ifp->if_softc;
 1536         if (ifp->if_flags & IFF_UP)
mii_mediachg(&sc->sc_mii);
 1538         return (0);
 1539 }