root/dev/ic/aic6915.h

INCLUDED FROM

    1 /*      $OpenBSD: aic6915.h,v 1.2 2006/12/07 13:30:24 martin Exp $      */
    2 /*      $NetBSD: aic6915reg.h,v 1.4 2005/12/11 12:21:25 christos Exp $  */
    4 /*-
    5  * Copyright (c) 2001 The NetBSD Foundation, Inc.
    6  * All rights reserved.
    7  *
    8  * This code is derived from software contributed to The NetBSD Foundation
    9  * by Jason R. Thorpe.
   10  *
   11  * Redistribution and use in source and binary forms, with or without
   12  * modification, are permitted provided that the following conditions
   13  * are met:
   14  * 1. Redistributions of source code must retain the above copyright
   15  *    notice, this list of conditions and the following disclaimer.
   16  * 2. Redistributions in binary form must reproduce the above copyright
   17  *    notice, this list of conditions and the following disclaimer in the
   18  *    documentation and/or other materials provided with the distribution.
   19  * 3. All advertising materials mentioning features or use of this software
   20  *    must display the following acknowledgement:
   21  *      This product includes software developed by the NetBSD
   22  *      Foundation, Inc. and its contributors.
   23  * 4. Neither the name of The NetBSD Foundation nor the names of its
   24  *    contributors may be used to endorse or promote products derived
   25  *    from this software without specific prior written permission.
   26  *
   27  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   29  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   30  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   37  * POSSIBILITY OF SUCH DAMAGE.
   38  */
   40 #ifndef _DEV_IC_AIC6915_H_
   41 #define _DEV_IC_AIC6915_H_
   43 #include <sys/timeout.h>
   45 /*
   46  * Register description for the Adaptec AIC-6915 (``Starfire'')
   47  * 10/100 Ethernet controller.
   48  */
   50 /*
   51  * Receive Buffer Descriptor (One-size, 32-bit addressing)
   52  */
   53 struct sf_rbd32 {
uint32_t        rbd32_addr;             /* address, flags */
   55 };
   57 /*
   58  * Receive Buffer Descriptor (One-size, 64-bit addressing)
   59  */
   60 struct sf_rbd64 {
uint32_t        rbd64_addr_lo;          /* address (LSD), flags */
uint32_t        rbd64_addr_hi;          /* address (MDS) */
   63 };
   65 #define RBD_V           (1U << 0)       /* valid descriptor */
   66 #define RBD_E           (1U << 1)       /* end of ring */
   68 /*
   69  * Short (Type 0) Completion Descriptor
   70  */
   71 struct sf_rcd_short {
uint32_t        rcd_word0;      /* length, end index, status1 */
   73 };
   75 /*
   76  * Basic (Type 1) Completion Descriptor
   77  */
   78 struct sf_rcd_basic {
uint32_t        rcd_word0;      /* length, end index, status1 */
uint32_t        rcd_word1;      /* VLAN ID, status2 */
   81 };
   83 /*
   84  * Checksum (Type 2) Completion Descriptor
   85  */
   86 struct sf_rcd_checksum {
uint32_t        rcd_word0;      /* length, end index, status1 */
uint32_t        rcd_word1;      /* partial TCP/UDP checksum, status2 */
   89 };
   91 /*
   92  * Full (Type 3) Completion Descriptor
   93  */
   94 struct sf_rcd_full {
uint32_t        rcd_word0;      /* length, end index, status1 */
uint32_t        rcd_word1;      /* start index, status3, status2 */
uint32_t        rcd_word2;      /* VLAN ID + priority, TCP/UDP csum */
uint32_t        rcd_timestamp;  /* timestamp */
   99 };
  101 #define RCD_W0_ID               (1U << 30)
  103 #define RCD_W0_Length(x)        ((x) & 0xffff)
  104 #define RCD_W0_EndIndex(x)      (((x) >> 16) & 0x7ff)
  105 #define RCD_W0_BufferQueue      (1U << 27)      /* 1 == Queue 2 */
  106 #define RCD_W0_FifoFull         (1U << 28)      /* FIFO full */
  107 #define RCD_W0_OK               (1U << 29)      /* packet is OK */
  109 /* Status2 field */
  110 #define RCD_W1_FrameType        (7U << 16)
  111 #define RCD_W1_FrameType_Unknown (0 << 16)
  112 #define RCD_W1_FrameType_IPv4   (1U << 16)
  113 #define RCD_W1_FrameType_IPv6   (2U << 16)
  114 #define RCD_W1_FrameType_IPX    (3U << 16)
  115 #define RCD_W1_FrameType_ICMP   (4U << 16)
  116 #define RCD_W1_FrameType_Unsupported (5U << 16)
  117 #define RCD_W1_UdpFrame         (1U << 19)
  118 #define RCD_W1_TcpFrame         (1U << 20)
  119 #define RCD_W1_Fragmented       (1U << 21)
  120 #define RCD_W1_PartialChecksumValid (1U << 22)
  121 #define RCD_W1_ChecksumBad      (1U << 23)
  122 #define RCD_W1_ChecksumOk       (1U << 24)
  123 #define RCD_W1_VlanFrame        (1U << 25)
  124 #define RCD_W1_ReceiveCodeViolation (1U << 26)
  125 #define RCD_W1_Dribble          (1U << 27)
  126 #define RCD_W1_ISLCRCerror      (1U << 28)
  127 #define RCD_W1_CRCerror         (1U << 29)
  128 #define RCD_W1_Hash             (1U << 30)
  129 #define RCD_W1_Perfect          (1U << 31)
  131 #define RCD_W1_VLANID(x)        ((x) & 0xffff)
  132 #define RCD_W1_TCP_UDP_Checksum(x) ((x) & 0xffff)
  134 /* Status3 field */
  135 #define RCD_W1_Trailer          (1U << 11)
  136 #define RCD_W1_Header           (1U << 12)
  137 #define RCD_W1_ControlFrame     (1U << 13)
  138 #define RCD_W1_PauseFrame       (1U << 14)
  139 #define RCD_W1_IslFrame         (1U << 15)
  141 #define RCD_W1_StartIndex(x)    ((x) & 0x7ff)
  143 #define RCD_W2_TCP_UDP_Checksum(x) ((x) >> 16)
  144 #define RCD_W2_VLANID(x)        ((x) & 0xffff)
  146 /*
  147  * Number of transmit buffer fragments we use.  This is arbitrary, but
  148  * we choose it carefully; see blow.
  149  */
  150 #define SF_NTXFRAGS             15
  152 /*
  153  * Type 0, 32-bit addressing mode (Frame Descriptor) Transmit Descriptor
  154  *
  155  * NOTE: The total length of this structure is: 8 + (15 * 8) == 128
  156  * This means 16 Tx indices per Type 0 descriptor.  This is important later
  157  * on; see below.
  158  */
  159 struct sf_txdesc0 {
  160         /* skip field */
uint32_t        td_word0;       /* ID, flags */
uint32_t        td_word1;       /* Tx buffer count */
  163         struct {
uint32_t fr_addr;       /* address */
uint32_t fr_len;        /* length */
  166         } td_frags[SF_NTXFRAGS];
  167 };
  169 #define TD_W1_NTXBUFS           (0xff << 0)
  171 /*
  172  * Type 1, 32-bit addressing mode (Buffer Descriptor) Transmit Descriptor
  173  */
  174 struct sf_txdesc1 {
  175         /* skip field */
uint32_t        td_word0;       /* ID, flags */
uint32_t        td_addr;        /* buffer address */
  178 };
  180 #define TD_W0_ID                (0xb << 28)
  181 #define TD_W0_INTR              (1U << 27)
  182 #define TD_W0_END               (1U << 26)
  183 #define TD_W0_CALTCP            (1U << 25)
  184 #define TD_W0_CRCEN             (1U << 24)
  185 #define TD_W0_LEN               (0xffff << 0)
  186 #define TD_W0_NTXBUFS           (0xff << 16)
  187 #define TD_W0_NTXBUFS_SHIFT     16
  189 /*
  190  * Type 2, 64-bit addressing mode (Buffer Descriptor) Transmit Descriptor
  191  */
  192 struct sf_txdesc2 {
  193         /* skip field */
uint32_t        td_word0;       /* ID, flags */
uint32_t        td_reserved;
uint32_t        td_addr_lo;     /* buffer address (LSD) */
uint32_t        td_addr_hi;     /* buffer address (MSD) */
  198 };
  200 /*
  201  * Transmit Completion Descriptor.
  202  */
  203 struct sf_tcd {
uint32_t        tcd_word0;      /* index, priority, flags */
  205 };
  207 #define TCD_DMA_ID              (0x4 << 29)
  208 #define TCD_INDEX(x)            ((x) & 0x7fff)
  209 #define TCD_PR                  (1U << 15)
  210 #define TCD_TIMESTAMP(x)        (((x) >> 16) & 0x1fff)
  212 #define TCD_TX_ID               (0x5 << 29)
  213 #define TCD_CRCerror            (1U << 16)
  214 #define TCD_FieldLengthCkError  (1U << 17)
  215 #define TCD_FieldLengthRngError (1U << 18)
  216 #define TCD_PacketTxOk          (1U << 19)
  217 #define TCD_Deferred            (1U << 20)
  218 #define TCD_ExDeferral          (1U << 21)
  219 #define TCD_ExCollisions        (1U << 22)
  220 #define TCD_LateCollision       (1U << 23)
  221 #define TCD_LongFrame           (1U << 24)
  222 #define TCD_FIFOUnderrun        (1U << 25)
  223 #define TCD_ControlTx           (1U << 26)
  224 #define TCD_PauseTx             (1U << 27)
  225 #define TCD_TxPaused            (1U << 28)
  227 /*
  228  * The Tx indices are in units of 8 bytes, and since we are using
  229  * Tx descriptors that are 128 bytes long, we need to divide by 16
  230  * to get the actual index that we care about.
  231  */
  232 #define SF_TXDINDEX_TO_HOST(x)          ((x) >> 4)
  233 #define SF_TXDINDEX_TO_CHIP(x)          ((x) << 4)
  235 /*
  236  * To make matters worse, the manual lies about the indices in the
  237  * completion queue entires.  It claims they are in 8-byte units,
  238  * but they're actually *BYTES*, which means we need to divide by
  239  * 128 to get the actual index.
  240  */
  241 #define SF_TCD_INDEX_TO_HOST(x)         ((x) >> 7)
  243 /*
  244  * PCI configuration space addresses.
  245  */
  246 #define SF_PCI_MEMBA            (PCI_MAPREG_START + 0x00)
  247 #define SF_PCI_IOBA             (PCI_MAPREG_START + 0x08)
  249 #define SF_GENREG_OFFSET        0x50000
  250 #define SF_FUNCREG_SIZE         0x100
  252 /*
  253  * PCI functional registers.
  254  */
  255 #define SF_PciDeviceConfig      0x40
  256 #define PDC_EnDpeInt            (1U << 31)      /* enable DPE PCIint */
  257 #define PDC_EnSseInt            (1U << 30)      /* enable SSE PCIint */
  258 #define PDC_EnRmaInt            (1U << 29)      /* enable RMA PCIint */
  259 #define PDC_EnRtaInt            (1U << 28)      /* enable RTA PCIint */
  260 #define PDC_EnStaInt            (1U << 27)      /* enable STA PCIint */
  261 #define PDC_EnDprInt            (1U << 24)      /* enable DPR PCIint */
  262 #define PDC_IntEnable           (1U << 23)      /* enable PCI_INTA_ */
  263 #define PDC_ExternalRegCsWidth  (7U << 20)      /* external chip-sel width */
  264 #define PDC_StopMWrOnCacheLineDis (1U << 19)
  265 #define PDC_EpromCsWidth        (7U << 16)
  266 #define PDC_EnBeLogic           (1U << 15)
  267 #define PDC_LatencyStopOnCacheLine (1U << 14)
  268 #define PDC_PCIMstDmaEn         (1U << 13)
  269 #define PDC_StopOnCachelineEn   (1U << 12)
  270 #define PDC_FifoThreshold       (0xf << 8)
  271 #define PDC_FifoThreshold_SHIFT 8
  272 #define PDC_MemRdCmdEn          (1U << 7)
  273 #define PDC_StopOnPerr          (1U << 6)
  274 #define PDC_AbortOnAddrParityErr (1U << 5)
  275 #define PDC_EnIncrement         (1U << 4)
  276 #define PDC_System64            (1U << 2)
  277 #define PDC_Force64             (1U << 1)
  278 #define PDC_SoftReset           (1U << 0)
  280 #define SF_BacControl           0x44
  281 #define BC_DescSwapMode         (0x3 << 6)
  282 #define BC_DataSwapMode         (0x3 << 4)
  283 #define BC_SingleDmaMode        (1U << 3)
  284 #define BC_PreferTxDmaReq       (1U << 2)
  285 #define BC_PreferRxDmaReq       (1U << 1)
  286 #define BC_BacDmaEn             (1U << 0)
  288 #define SF_PciMonitor1          0x48
  290 #define SF_PciMonitor2          0x4c
  292 #define SF_PMC                  0x50
  294 #define SF_PMCSR                0x54
  296 #define SF_PMEvent              0x58
  298 #define SF_SerialEpromControl   0x60
  299 #define SEC_InitDone            (1U << 3)
  300 #define SEC_Idle                (1U << 2)
  301 #define SEC_WriteEnable         (1U << 1)
  302 #define SEC_WriteDisable        (1U << 0)
  304 #define SF_PciComplianceTesting 0x64
  306 #define SF_IndirectIoAccess     0x68
  308 #define SF_IndirectIoDataPort   0x6c
  310 /*
  311  * Ethernet functional registers.
  312  */
  313 #define SF_GeneralEthernetCtrl  0x70
  314 #define GEC_SetSoftInt          (1U << 8)
  315 #define GEC_TxGfpEn             (1U << 5)
  316 #define GEC_RxGfpEn             (1U << 4)
  317 #define GEC_TxDmaEn             (1U << 3)
  318 #define GEC_RxDmaEn             (1U << 2)
  319 #define GEC_TransmitEn          (1U << 1)
  320 #define GEC_ReceiveEn           (1U << 0)
  322 #define SF_TimersControl        0x74
  323 #define TC_EarlyRxQ1IntDelayDisable     (1U << 31)
  324 #define TC_RxQ1DoneIntDelayDisable      (1U << 30)
  325 #define TC_EarlyRxQ2IntDelayDisable     (1U << 29)
  326 #define TC_RxQ2DoneIntDelayDisable      (1U << 28)
  327 #define TC_TimeStampResolution          (1U << 26)
  328 #define TC_GeneralTimerResolution       (1U << 25)
  329 #define TC_OneShotMode                  (1U << 24)
  330 #define TC_GeneralTimerInterval         (0xff << 16)
  331 #define TC_GeneralTimerInterval_SHIFT   16
  332 #define TC_TxFrameCompleteIntDelayDisable (1U << 15)
  333 #define TC_TxQueueDoneIntDelayDisable   (1U << 14)
  334 #define TC_TxDmaDoneIntDelayDisable     (1U << 13)
  335 #define TC_RxHiPrBypass                 (1U << 12)
  336 #define TC_Timer10X                     (1U << 11)
  337 #define TC_SmallRxFrame                 (3U << 9)
  338 #define TC_SmallFrameBypass             (1U << 8)
  339 #define TC_IntMaskMode                  (3U << 5)
  340 #define TC_IntMaskPeriod                (0x1f << 0)
  342 #define SF_CurrentTime          0x78
  344 #define SF_InterruptStatus      0x80
  345 #define IS_GPIO3                        (1U << 31)
  346 #define IS_GPIO2                        (1U << 30)
  347 #define IS_GPIO1                        (1U << 29)
  348 #define IS_GPIO0                        (1U << 28)
  349 #define IS_StatisticWrapInt             (1U << 27)
  350 #define IS_AbnormalInterrupt            (1U << 25)
  351 #define IS_GeneralTimerInt              (1U << 24)
  352 #define IS_SoftInt                      (1U << 23)
  353 #define IS_RxCompletionQueue1Int        (1U << 22)
  354 #define IS_TxCompletionQueueInt         (1U << 21)
  355 #define IS_PCIInt                       (1U << 20)
  356 #define IS_DmaErrInt                    (1U << 19)
  357 #define IS_TxDataLowInt                 (1U << 18)
  358 #define IS_RxCompletionQueue2Int        (1U << 17)
  359 #define IS_RxQ1LowBuffersInt            (1U << 16)
  360 #define IS_NormalInterrupt              (1U << 15)
  361 #define IS_TxFrameCompleteInt           (1U << 14)
  362 #define IS_TxDmaDoneInt                 (1U << 13)
  363 #define IS_TxQueueDoneInt               (1U << 12)
  364 #define IS_EarlyRxQ2Int                 (1U << 11)
  365 #define IS_EarlyRxQ1Int                 (1U << 10)
  366 #define IS_RxQ2DoneInt                  (1U << 9)
  367 #define IS_RxQ1DoneInt                  (1U << 8)
  368 #define IS_RxGfpNoResponseInt           (1U << 7)
  369 #define IS_RxQ2LowBuffersInt            (1U << 6)
  370 #define IS_NoTxChecksumInt              (1U << 5)
  371 #define IS_TxLowPrMismatchInt           (1U << 4)
  372 #define IS_TxHiPrMismatchInt            (1U << 3)
  373 #define IS_GfpRxInt                     (1U << 2)
  374 #define IS_GfpTxInt                     (1U << 1)
  375 #define IS_PCIPadInt                    (1U << 0)
  377 #define SF_ShadowInterruptStatus 0x84
  379 #define SF_InterruptEn          0x88
  381 #define SF_GPIO                 0x8c
  382 #define GPIOCtrl(x)             (1U << (24 + (x)))
  383 #define GPIOOutMode(x)          (1U << (16 + (x)))
  384 #define GPIOInpMode(x, y)       ((y) << (8 + ((x) * 2)))
  385 #define GPIOData(x)             (1U << (x))
  387 #define SF_TxDescQueueCtrl      0x90
  388 #define TDQC_TxHighPriorityFifoThreshold(x)     ((x) << 24)
  389 #define TDQC_SkipLength(x)                      ((x) << 16)
  390 #define TDQC_TxDmaBurstSize(x)                  ((x) << 8)
  391 #define TDQC_TxDescQueue64bitAddr               (1U << 7)
  392 #define TDQC_MinFrameSpacing(x)                 ((x) << 4)
  393 #define TDQC_DisableTxDmaCompletion             (1U << 3)
  394 #define TDQC_TxDescType(x)                      ((x) << 0)
  396 #define SF_HiPrTxDescQueueBaseAddr 0x94
  398 #define SF_LoPrTxDescQueueBaseAddr 0x98
  400 #define SF_TxDescQueueHighAddr  0x9c
  402 #define SF_TxDescQueueProducerIndex 0xa0
  403 #define TDQPI_HiPrTxProducerIndex(x)            ((x) << 16)
  404 #define TDQPI_LoPrTxProducerIndex(x)            ((x) << 0)
  405 #define TDQPI_HiPrTxProducerIndex_get(x)        (((x) >> 16) & 0x7ff)
  406 #define TDQPI_LoPrTxProducerIndex_get(x)        (((x) >> 0) & 0x7ff)
  408 #define SF_TxDescQueueConsumerIndex 0xa4
  409 #define TDQCI_HiPrTxConsumerIndex(x)            (((x) >> 16) & 0x7ff)
  410 #define TDQCI_LoPrTxConsumerIndex(s)            (((x) >> 0) & 0x7ff)
  412 #define SF_TxDmaStatus1         0xa8
  414 #define SF_TxDmaStatus2         0xac
  416 #define SF_TransmitFrameCSR     0xb0
  417 #define TFCSR_TxFrameStatus                     (0xff << 16)
  418 #define TFCSR_TxDebugConfigBits                 (0x7f << 9)
  419 #define TFCSR_DmaCompletionAfterTransmitComplete (1U << 8)
  420 #define TFCSR_TransmitThreshold(x)              ((x) << 0)
  422 #define SF_CompletionQueueHighAddr 0xb4
  424 #define SF_TxCompletionQueueCtrl 0xb8
  425 #define TCQC_TxCompletionBaseAddress            0xffffff00
  426 #define TCQC_TxCompletion64bitAddress           (1U << 7)
  427 #define TCQC_TxCompletionProducerWe             (1U << 6)
  428 #define TCQC_TxCompletionSize                   (1U << 5)
  429 #define TCQC_CommonQueueMode                    (1U << 4)
  430 #define TCQC_TxCompletionQueueThreshold         ((x) << 0)
  432 #define SF_RxCompletionQueue1Ctrl 0xbc
  433 #define RCQ1C_RxCompletionQ1BaseAddress         0xffffff00
  434 #define RCQ1C_RxCompletionQ164bitAddress        (1U << 7)
  435 #define RCQ1C_RxCompletionQ1ProducerWe          (1U << 6)
  436 #define RCQ1C_RxCompletionQ1Type(x)             ((x) << 4)
  437 #define RCQ1C_RxCompletionQ1Threshold(x)        ((x) << 0)
  439 #define SF_RxCompletionQueue2Ctrl 0xc0
  440 #define RCQ1C_RxCompletionQ2BaseAddress         0xffffff00
  441 #define RCQ1C_RxCompletionQ264bitAddress        (1U << 7)
  442 #define RCQ1C_RxCompletionQ2ProducerWe          (1U << 6)
  443 #define RCQ1C_RxCompletionQ2Type(x)             ((x) << 4)
  444 #define RCQ1C_RxCompletionQ2Threshold(x)        ((x) << 0)
  446 #define SF_CompletionQueueConsumerIndex 0xc4
  447 #define CQCI_TxCompletionThresholdMode          (1U << 31)
  448 #define CQCI_TxCompletionConsumerIndex(x)       ((x) << 16)
  449 #define CQCI_TxCompletionConsumerIndex_get(x)   (((x) >> 16) & 0x7ff)
  450 #define CQCI_RxCompletionQ1ThresholdMode        (1U << 15)
  451 #define CQCI_RxCompletionQ1ConsumerIndex(x)     ((x) << 0)
  452 #define CQCI_RxCompletionQ1ConsumerIndex_get(x) ((x) & 0x7ff)
  454 #define SF_CompletionQueueProducerIndex 0xc8
  455 #define CQPI_TxCompletionProducerIndex(x)       ((x) << 16)
  456 #define CQPI_TxCompletionProducerIndex_get(x)   (((x) >> 16) & 0x7ff)
  457 #define CQPI_RxCompletionQ1ProducerIndex(x)     ((x) << 0)
  458 #define CQPI_RxCompletionQ1ProducerIndex_get(x) ((x) & 0x7ff)
  460 #define SF_RxHiPrCompletionPtrs 0xcc
  461 #define RHPCP_RxCompletionQ2ProducerIndex(x)    ((x) << 16)
  462 #define RHPCP_RxCompletionQ2ThresholdMode       (1U << 15)
  463 #define RHPCP_RxCompletionQ2ConsumerIndex(x)    ((x) << 0)
  465 #define SF_RxDmaCtrl            0xd0
  466 #define RDC_RxReportBadFrames                   (1U << 31)
  467 #define RDC_RxDmaShortFrames                    (1U << 30)
  468 #define RDC_RxDmaBadFrames                      (1U << 29)
  469 #define RDC_RxDmaCrcErrorFrames                 (1U << 28)
  470 #define RDC_RxDmaControlFrame                   (1U << 27)
  471 #define RDC_RxDmaPauseFrame                     (1U << 26)
  472 #define RDC_RxChecksumMode(x)                   ((x) << 24)
  473 #define RDC_RxCompletionQ2Enable                (1U << 23)
  474 #define RDC_RxDmaQueueMode(x)                   ((x) << 20)
  475 #define RDC_RxUseBackupQueue                    (1U << 19)
  476 #define RDC_RxDmaCrc                            (1U << 18)
  477 #define RDC_RxEarlyIntThreshold(x)              ((x) << 12)
  478 #define RDC_RxHighPriorityThreshold(x)          ((x) << 8)
  479 #define RDC_RxBurstSize(x)                      ((x) << 0)
  481 #define SF_RxDescQueue1Ctrl     0xd4
  482 #define RDQ1C_RxQ1BufferLength(x)               ((x) << 16)
  483 #define RDQ1C_RxPrefetchDescriptorsMode         (1U << 15)
  484 #define RDQ1C_RxDescQ1Entries                   (1U << 14)
  485 #define RDQ1C_RxVariableSizeQueues              (1U << 13)
  486 #define RDQ1C_Rx64bitBufferAddresses            (1U << 12)
  487 #define RDQ1C_Rx64bitDescQueueAddress           (1U << 11)
  488 #define RDQ1C_RxDescSpacing(x)                  ((x) << 8)
  489 #define RDQ1C_RxQ1ConsumerWe                    (1U << 7)
  490 #define RDQ1C_RxQ1MinDescriptorsThreshold(x)    ((x) << 0)
  492 #define SF_RxDescQueue2Ctrl     0xd8
  493 #define RDQ2C_RxQ2BufferLength(x)               ((x) << 16)
  494 #define RDQ2C_RxDescQ2Entries                   (1U << 14)
  495 #define RDQ2C_RxQ2MinDescriptorsThreshold(x)    ((x) << 0)
  497 #define SF_RxDescQueueHighAddress 0xdc
  499 #define SF_RxDescQueue1LowAddress 0xe0
  501 #define SF_RxDescQueue2LowAddress 0xe4
  503 #define SF_RxDescQueue1Ptrs     0xe8
  504 #define RXQ1P_RxDescQ1Consumer(x)               ((x) << 16)
  505 #define RXQ1P_RxDescQ1Producer(x)               ((x) << 0)
  506 #define RXQ1P_RxDescQ1Producer_get(x)           ((x) & 0x7ff)
  508 #define SF_RxDescQueue2Ptrs     0xec
  509 #define RXQ2P_RxDescQ2Consumer(x)               ((x) << 16)
  510 #define RXQ2P_RxDescQ2Producer(x)               ((x) << 0)
  512 #define SF_RxDmaStatus          0xf0
  513 #define RDS_RxFramesLostCount(x)                ((x) & 0xffff)
  515 #define SF_RxAddressFilteringCtl 0xf4
  516 #define RAFC_PerfectAddressPriority(x)          (1U << ((x) + 16))
  517 #define RAFC_MinVlanPriority(x)                 ((x) << 13)
  518 #define RAFC_PassMulticastExceptBroadcast       (1U << 12)
  519 #define RAFC_WakeupMode(x)                      ((x) << 10)
  520 #define RAFC_VlanMode(x)                        ((x) << 8)
  521 #define RAFC_PerfectFilteringMode(x)            ((x) << 6)
  522 #define RAFC_HashFilteringMode(x)               ((x) << 4)
  523 #define RAFC_HashPriorityEnable                 (1U << 3)
  524 #define RAFC_PassBroadcast                      (1U << 2)
  525 #define RAFC_PassMulticast                      (1U << 1)
  526 #define RAFC_PromiscuousMode                    (1U << 0)
  528 #define SF_RxFrameTestOut       0xf8
  530 /*
  531  * Additional PCI registers.  To access these registers via I/O space,
  532  * indirect access must be used.
  533  */
  534 #define SF_PciTargetStatus      0x100
  536 #define SF_PciMasterStatus1     0x104
  538 #define SF_PciMasterStatus2     0x108
  540 #define SF_PciDmaLowHostAddr    0x10c
  542 #define SF_BacDmaDiagnostic0    0x110
  544 #define SF_BacDmaDiagnostic1    0x114
  546 #define SF_BacDmaDiagnostic2    0x118
  548 #define SF_BacDmaDiagnostic3    0x11c
  550 #define SF_MacAddr1             0x120
  552 #define SF_MacAddr2             0x124
  554 #define SF_FunctionEvent        0x130
  556 #define SF_FunctionEventMask    0x134
  558 #define SF_FunctionPresentState 0x138
  560 #define SF_ForceFunction        0x13c
  562 #define SF_EEPROM_BASE          0x1000
  564 #define SF_MII_BASE             0x2000
  565 #define MiiDataValid            (1U << 31)
  566 #define MiiBusy                 (1U << 30)
  567 #define MiiRegDataPort(x)       ((x) & 0xffff)
  569 #define SF_MII_PHY_REG(p, r)    (SF_MII_BASE +                          \
  570                                  ((p) * 32 * sizeof(uint32_t)) +        \
  571                                  ((r) * sizeof(uint32_t)))
  573 #define SF_TestMode             0x4000
  575 #define SF_RxFrameProcessorCtrl 0x4004
  577 #define SF_TxFrameProcessorCtrl 0x4008
  579 #define SF_MacConfig1           0x5000
  580 #define MC1_SoftRst                     (1U << 15)
  581 #define MC1_MiiLoopBack                 (1U << 14)
  582 #define MC1_TestMode(x)                 ((x) << 12)
  583 #define MC1_TxFlowEn                    (1U << 11)
  584 #define MC1_RxFlowEn                    (1U << 10)
  585 #define MC1_PreambleDetectCount         (1U << 9)
  586 #define MC1_PassAllRxPackets            (1U << 8)
  587 #define MC1_PurePreamble                (1U << 7)
  588 #define MC1_LengthCheck                 (1U << 6)
  589 #define MC1_NoBackoff                   (1U << 5)
  590 #define MC1_DelayCRC                    (1U << 4)
  591 #define MC1_TxHalfDuplexJam             (1U << 3)
  592 #define MC1_PadEn                       (1U << 2)
  593 #define MC1_FullDuplex                  (1U << 1)
  594 #define MC1_HugeFrame                   (1U << 0)
  596 #define SF_MacConfig2           0x5004
  597 #define MC2_TxCRCerr                    (1U << 15)
  598 #define MC2_TxIslCRCerr                 (1U << 14)
  599 #define MC2_RxCRCerr                    (1U << 13)
  600 #define MC2_RxIslCRCerr                 (1U << 12)
  601 #define MC2_TXCF                        (1U << 11)
  602 #define MC2_CtlSoftRst                  (1U << 10)
  603 #define MC2_RxSoftRst                   (1U << 9)
  604 #define MC2_TxSoftRst                   (1U << 8)
  605 #define MC2_RxISLEn                     (1U << 7)
  606 #define MC2_BackPressureNoBackOff       (1U << 6)
  607 #define MC2_AutoVlanPad                 (1U << 5)
  608 #define MC2_MandatoryVLANPad            (1U << 4)
  609 #define MC2_TxISLAppen                  (1U << 3)
  610 #define MC2_TxISLEn                     (1U << 2)
  611 #define MC2_SimuRst                     (1U << 1)
  612 #define MC2_TxXmtEn                     (1U << 0)
  614 #define SF_BkToBkIPG            0x5008
  616 #define SF_NonBkToBkIPG         0x500c
  618 #define SF_ColRetry             0x5010
  620 #define SF_MaxLength            0x5014
  622 #define SF_TxNibbleCnt          0x5018
  624 #define SF_TxByteCnt            0x501c
  626 #define SF_ReTxCnt              0x5020
  628 #define SF_RandomNumGen         0x5024
  630 #define SF_MskRandomNum         0x5028
  632 #define SF_TotalTxCnt           0x5034
  634 #define SF_RxByteCnt            0x5040
  636 #define SF_TxPauseTimer         0x5060
  638 #define SF_VLANType             0x5064
  640 #define SF_MiiStatus            0x5070
  642 #define SF_PERFECT_BASE         0x6000
  643 #define SF_PERFECT_SIZE         0x100
  645 #define SF_HASH_BASE            0x6100
  646 #define SF_HASH_SIZE            0x200
  648 #define SF_STATS_BASE           0x7000
  649 struct sf_stats {
uint32_t        TransmitOKFrames;
uint32_t        SingleCollisionFrames;
uint32_t        MultipleCollisionFrames;
uint32_t        TransmitCRCErrors;
uint32_t        TransmitOKOctets;
uint32_t        TransmitDeferredFrames;
uint32_t        TransmitLateCollisionCount;
uint32_t        TransmitPauseControlFrames;
uint32_t        TransmitControlFrames;
uint32_t        TransmitAbortDueToExcessiveCollisions;
uint32_t        TransmitAbortDueToExcessingDeferral;
uint32_t        MulticastFramesTransmittedOK;
uint32_t        BroadcastFramesTransmittedOK;
uint32_t        FramesLostDueToInternalTransmitErrors;
uint32_t        ReceiveOKFrames;
uint32_t        ReceiveCRCErrors;
uint32_t        AlignmentErrors;
uint32_t        ReceiveOKOctets;
uint32_t        PauseFramesReceivedOK;
uint32_t        ControlFramesReceivedOK;
uint32_t        ControlFramesReceivedWithUnsupportedOpcode;
uint32_t        ReceiveFramesTooLong;
uint32_t        ReceiveFramesTooShort;
uint32_t        ReceiveFramesJabbersError;
uint32_t        ReceiveFramesFragments;
uint32_t        ReceivePackets64Bytes;
uint32_t        ReceivePackets127Bytes;
uint32_t        ReceivePackets255Bytes;
uint32_t        ReceivePackets511Bytes;
uint32_t        ReceivePackets1023Bytes;
uint32_t        ReceivePackets1518Bytes;
uint32_t        FramesLostDueToInternalReceiveErrors;
uint32_t        TransmitFifoUnderflowCounts;
  683 };
  685 #define SF_TxGfpMem             0x8000
  687 #define SF_RxGfpMem             0xa000
  689 /*
  690  * Data structure definitions for the Adaptec AIC-6915 (``Starfire'')
  691  * PCI 10/100 Ethernet controller driver.
  692  */
  694 /*
  695  * Transmit descriptor list size.
  696  */
  697 #define SF_NTXDESC              256
  698 #define SF_NTXDESC_MASK         (SF_NTXDESC - 1)
  699 #define SF_NEXTTX(x)            ((x + 1) & SF_NTXDESC_MASK)
  701 /*
  702  * Transmit completion queue size.  1024 is a hardware requirement.
  703  */
  704 #define SF_NTCD                 1024
  705 #define SF_NTCD_MASK            (SF_NTCD - 1)
  706 #define SF_NEXTTCD(x)           ((x + 1) & SF_NTCD_MASK)
  708 /*
  709  * Receive descriptor list size.
  710  */
  711 #define SF_NRXDESC              256
  712 #define SF_NRXDESC_MASK         (SF_NRXDESC - 1)
  713 #define SF_NEXTRX(x)            ((x + 1) & SF_NRXDESC_MASK)
  715 /*
  716  * Receive completion queue size.  1024 is a hardware requirement.
  717  */
  718 #define SF_NRCD                 1024
  719 #define SF_NRCD_MASK            (SF_NRCD - 1)
  720 #define SF_NEXTRCD(x)           ((x + 1) & SF_NRCD_MASK)
  722 /*
  723  * Control structures are DMA to the Starfire chip.  We allocate them in
  724  * a single clump that maps to a single DMA segment to make several things
  725  * easier.
  726  */
  727 struct sf_control_data {
  728         /*
  729          * The transmit descriptors.
  730          */
  731         struct sf_txdesc0 scd_txdescs[SF_NTXDESC];
  733         /*
  734          * The transmit completion queue entires.
  735          */
  736         struct sf_tcd scd_txcomp[SF_NTCD];
  738         /*
  739          * The receive buffer descriptors.
  740          */
  741         struct sf_rbd32 scd_rxbufdescs[SF_NRXDESC];
  743         /*
  744          * The receive completion queue entries.
  745          */
  746         struct sf_rcd_full scd_rxcomp[SF_NRCD];
  747 };
  749 #define SF_CDOFF(x)             offsetof(struct sf_control_data, x)
  750 #define SF_CDTXDOFF(x)          SF_CDOFF(scd_txdescs[(x)])
  751 #define SF_CDTXCOFF(x)          SF_CDOFF(scd_txcomp[(x)])
  752 #define SF_CDRXDOFF(x)          SF_CDOFF(scd_rxbufdescs[(x)])
  753 #define SF_CDRXCOFF(x)          SF_CDOFF(scd_rxcomp[(x)])
  755 /*
  756  * Software state for transmit and receive descriptors.
  757  */
  758 struct sf_descsoft {
  759         struct mbuf *ds_mbuf;           /* head of mbuf chain */
bus_dmamap_t ds_dmamap;         /* our DMA map */
  761 };
  763 /*
  764  * Software state per device.
  765  */
  766 struct sf_softc {
  767         struct device sc_dev;           /* generic device information */
bus_space_tag_t sc_st;          /* bus space tag */
bus_space_handle_t sc_sh;       /* bus space handle */
bus_space_handle_t sc_sh_func;  /* sub-handle for func regs */
bus_dma_tag_t sc_dmat;          /* bus DMA tag */
  772         struct arpcom sc_arpcom;        /* ethernet common data */
  773         void *sc_sdhook;                /* shutdown hook */
  774         int sc_iomapped;                /* are we I/O mapped? */
  775         int sc_flags;                   /* misc. flags */
  777         struct mii_data sc_mii;         /* MII/media information */
  778         struct timeout sc_mii_timeout;  /* MII callout */
bus_dmamap_t sc_cddmamap;       /* control data DMA map */
  781 #define sc_cddma        sc_cddmamap->dm_segs[0].ds_addr
  783         /*
  784          * Software state for transmit and receive descriptors.
  785          */
  786         struct sf_descsoft sc_txsoft[SF_NTXDESC];
  787         struct sf_descsoft sc_rxsoft[SF_NRXDESC];
  789         /*
  790          * Control data structures.
  791          */
  792         struct sf_control_data *sc_control_data;
  793 #define sc_txdescs      sc_control_data->scd_txdescs
  794 #define sc_txcomp       sc_control_data->scd_txcomp
  795 #define sc_rxbufdescs   sc_control_data->scd_rxbufdescs
  796 #define sc_rxcomp       sc_control_data->scd_rxcomp
  798         int     sc_txpending;           /* number of Tx requests pending */
uint32_t sc_InterruptEn;        /* prototype InterruptEn register */
uint32_t sc_TransmitFrameCSR;   /* prototype TransmitFrameCSR reg */
uint32_t sc_TxDescQueueCtrl;    /* prototype TxDescQueueCtrl reg */
  804         int     sc_txthresh;            /* current Tx threshold */
uint32_t sc_MacConfig1;         /* prototype MacConfig1 register */
uint32_t sc_RxAddressFilteringCtl;
  809 };
  811 #define SF_CDTXDADDR(sc, x)     ((sc)->sc_cddma + SF_CDTXDOFF((x)))
  812 #define SF_CDTXCADDR(sc, x)     ((sc)->sc_cddma + SF_CDTXCOFF((x)))
  813 #define SF_CDRXDADDR(sc, x)     ((sc)->sc_cddma + SF_CDRXDOFF((x)))
  814 #define SF_CDRXCADDR(sc, x)     ((sc)->sc_cddma + SF_CDRXCOFF((x)))
  816 #define SF_CDTXDSYNC(sc, x, ops)                                        \
bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,               \
SF_CDTXDOFF((x)), sizeof(struct sf_txdesc0), (ops))
  820 #define SF_CDTXCSYNC(sc, x, ops)                                        \
bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,               \
SF_CDTXCOFF((x)), sizeof(struct sf_tcd), (ops))
  824 #define SF_CDRXDSYNC(sc, x, ops)                                        \
bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,               \
SF_CDRXDOFF((x)), sizeof(struct sf_rbd32), (ops))
  828 #define SF_CDRXCSYNC(sc, x, ops)                                        \
bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,               \
SF_CDRXCOFF((x)), sizeof(struct sf_rcd_full), (ops))
  832 #define SF_INIT_RXDESC(sc, x)                                           \
  833 do {                                                                    \
  834         struct sf_descsoft *__ds = &sc->sc_rxsoft[(x)];                 \
  835                                                                         \
  836         (sc)->sc_rxbufdescs[(x)].rbd32_addr =                           \
__ds->ds_dmamap->dm_segs[0].ds_addr | RBD_V;                \
SF_CDRXDSYNC((sc), (x), BUS_DMASYNC_PREWRITE);                  \
  839 } while (/*CONSTCOND*/0)
  841 #ifdef _KERNEL
  842 void    sf_attach(struct sf_softc *);
  843 int     sf_intr(void *);
  844 #endif /* _KERNEL */
  846 #endif /* _DEV_IC_AIC6915_H_ */