phy 1441 dev/ic/aic6915.c sf_mii_read(struct device *self, int phy, int reg)
phy 1448 dev/ic/aic6915.c v = sf_genreg_read(sc, SF_MII_PHY_REG(phy, reg));
phy 1469 dev/ic/aic6915.c sf_mii_write(struct device *self, int phy, int reg, int val)
phy 1474 dev/ic/aic6915.c sf_genreg_write(sc, SF_MII_PHY_REG(phy, reg), val);
phy 1477 dev/ic/aic6915.c if ((sf_genreg_read(sc, SF_MII_PHY_REG(phy, reg)) &
phy 440 dev/ic/ar5212.c u_int i, phy, mode, freq, off, ee_mode, ant[2];
phy 471 dev/ic/ar5212.c phy = AR5K_INI_PHY_5111;
phy 473 dev/ic/ar5212.c phy = AR5K_INI_PHY_5112;
phy 561 dev/ic/ar5212.c if (ar5k_rfgain(hal, phy, freq) == AH_FALSE)
phy 327 dev/ic/ar5xxx.c switch (rate->phy) {
phy 1702 dev/ic/ar5xxx.c ar5k_rfgain(struct ath_hal *hal, u_int phy, u_int freq)
phy 1706 dev/ic/ar5xxx.c switch (phy) {
phy 1725 dev/ic/ar5xxx.c ar5k_rfg[i].rfg_value[phy][freq]);
phy 336 dev/ic/ar5xxx.h u_int8_t phy;
phy 344 dev/ic/ar5xxx.h #define r_phy phy
phy 171 dev/ic/ax88190.c ax88190_mii_readreg(self, phy, reg)
phy 173 dev/ic/ax88190.c int phy, reg;
phy 175 dev/ic/ax88190.c return (mii_bitbang_readreg(self, &ax88190_mii_bitbang_ops, phy, reg));
phy 179 dev/ic/ax88190.c ax88190_mii_writereg(self, phy, reg, val)
phy 181 dev/ic/ax88190.c int phy, reg, val;
phy 183 dev/ic/ax88190.c mii_bitbang_writereg(self, &ax88190_mii_bitbang_ops, phy, reg, val);
phy 652 dev/ic/dc.c dc_miibus_readreg(self, phy, reg)
phy 654 dev/ic/dc.c int phy, reg;
phy 669 dev/ic/dc.c if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
phy 677 dev/ic/dc.c if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
phy 681 dev/ic/dc.c if (phy == (MII_NPHY - 1)) {
phy 710 dev/ic/dc.c (phy << 23) | (reg << 18));
phy 761 dev/ic/dc.c frame.mii_phyaddr = phy;
phy 775 dev/ic/dc.c dc_miibus_writereg(self, phy, reg, data)
phy 777 dev/ic/dc.c int phy, reg, data;
phy 785 dev/ic/dc.c if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
phy 787 dev/ic/dc.c if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
phy 792 dev/ic/dc.c (phy << 23) | (reg << 10) | data);
phy 834 dev/ic/dc.c frame.mii_phyaddr = phy;
phy 212 dev/ic/dl10019.c dl10019_mii_readreg(struct device *self, int phy, int reg)
phy 220 dev/ic/dl10019.c return (mii_bitbang_readreg(self, ops, phy, reg));
phy 224 dev/ic/dl10019.c dl10019_mii_writereg(struct device *self, int phy, int reg, int val)
phy 232 dev/ic/dl10019.c mii_bitbang_writereg(self, ops, phy, reg, val);
phy 1834 dev/ic/elink3.c ep_mii_readreg(self, phy, reg)
phy 1836 dev/ic/elink3.c int phy, reg;
phy 1852 dev/ic/elink3.c ep_mii_sendbits(sc, phy, 5);
phy 1880 dev/ic/elink3.c ep_mii_writereg(self, phy, reg, val)
phy 1882 dev/ic/elink3.c int phy, reg, val;
phy 1895 dev/ic/elink3.c ep_mii_sendbits(sc, phy, 5);
phy 1563 dev/ic/fxp.c fxp_mdi_read(struct device *self, int phy, int reg)
phy 1570 dev/ic/fxp.c (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
phy 1589 dev/ic/fxp.c fxp_mdi_write(struct device *self, int phy, int reg, int value)
phy 1595 dev/ic/fxp.c (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
phy 1192 dev/ic/gem.c gem_mii_readreg(struct device *self, int phy, int reg)
phy 1202 dev/ic/gem.c printf("gem_mii_readreg: phy %d reg %d\n", phy, reg);
phy 1206 dev/ic/gem.c v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) |
phy 1222 dev/ic/gem.c gem_mii_writereg(struct device *self, int phy, int reg, int val)
phy 1233 dev/ic/gem.c phy, reg, val);
phy 1238 dev/ic/gem.c (phy << GEM_MIF_PHY_SHIFT) |
phy 1310 dev/ic/gem.c gem_pcs_readreg(struct device *self, int phy, int reg)
phy 1318 dev/ic/gem.c printf("gem_pcs_readreg: phy %d reg %d\n", phy, reg);
phy 1321 dev/ic/gem.c if (phy != GEM_PHYAD_EXTERNAL)
phy 1347 dev/ic/gem.c gem_pcs_writereg(struct device *self, int phy, int reg, int val)
phy 1356 dev/ic/gem.c phy, reg, val);
phy 1359 dev/ic/gem.c if (phy != GEM_PHYAD_EXTERNAL)
phy 984 dev/ic/hme.c int phy;
phy 988 dev/ic/hme.c phy = HME_PHYAD_EXTERNAL;
phy 990 dev/ic/hme.c phy = sc->sc_tcvr = HME_PHYAD_EXTERNAL;
phy 992 dev/ic/hme.c phy = sc->sc_tcvr = HME_PHYAD_INTERNAL;
phy 998 dev/ic/hme.c if (phy == HME_PHYAD_EXTERNAL)
phy 1005 dev/ic/hme.c if (phy == HME_PHYAD_EXTERNAL)
phy 1014 dev/ic/hme.c hme_mii_readreg(self, phy, reg)
phy 1016 dev/ic/hme.c int phy, reg;
phy 1025 dev/ic/hme.c if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL)
phy 1031 dev/ic/hme.c if (phy == HME_PHYAD_EXTERNAL)
phy 1037 dev/ic/hme.c if (phy == HME_PHYAD_EXTERNAL)
phy 1047 dev/ic/hme.c (phy << HME_MIF_FO_PHYAD_SHIFT) |
phy 1072 dev/ic/hme.c hme_mii_writereg(self, phy, reg, val)
phy 1074 dev/ic/hme.c int phy, reg, val;
phy 1084 dev/ic/hme.c if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL)
phy 1090 dev/ic/hme.c if (phy == HME_PHYAD_EXTERNAL)
phy 1096 dev/ic/hme.c if (phy == HME_PHYAD_EXTERNAL)
phy 1106 dev/ic/hme.c (phy << HME_MIF_FO_PHYAD_SHIFT) |
phy 1137 dev/ic/hme.c printf("hme_mii_statchg: status change\n", phy);
phy 1164 dev/ic/hme.c int phy = sc->sc_phys[instance];
phy 1169 dev/ic/hme.c printf("hme_mediachange: phy = %d\n", phy);
phy 1177 dev/ic/hme.c if (phy == HME_PHYAD_EXTERNAL)
phy 1184 dev/ic/hme.c if (phy == HME_PHYAD_EXTERNAL)
phy 220 dev/ic/mtd8xx.c mtd_mii_command(struct mtd_softc *sc, int opcode, int phy, int reg)
phy 235 dev/ic/mtd8xx.c data = opcode | (phy << 7) | (reg << 2);
phy 255 dev/ic/mtd8xx.c mtd_miibus_readreg(struct device *self, int phy, int reg)
phy 260 dev/ic/mtd8xx.c return (phy ? 0 : (int)CSR_READ_2(MTD_PHYCSR + (reg << 1)));
phy 264 dev/ic/mtd8xx.c miir = mtd_mii_command(sc, MII_OPCODE_RD, phy, reg);
phy 284 dev/ic/mtd8xx.c mtd_miibus_writereg(struct device *self, int phy, int reg, int val)
phy 289 dev/ic/mtd8xx.c if (!phy)
phy 294 dev/ic/mtd8xx.c miir = mtd_mii_command(sc, MII_OPCODE_WR, phy, reg);
phy 323 dev/ic/re.c re_gmii_readreg(struct device *self, int phy, int reg)
phy 329 dev/ic/re.c if (phy != 7)
phy 358 dev/ic/re.c re_gmii_writereg(struct device *dev, int phy, int reg, int data)
phy 380 dev/ic/re.c re_miibus_readreg(struct device *dev, int phy, int reg)
phy 390 dev/ic/re.c rval = re_gmii_readreg(dev, phy, reg);
phy 396 dev/ic/re.c if (phy) {
phy 445 dev/ic/re.c re_miibus_writereg(struct device *dev, int phy, int reg, int data)
phy 454 dev/ic/re.c re_gmii_writereg(dev, phy, reg, data);
phy 460 dev/ic/re.c if (phy) {
phy 1367 dev/ic/rtl81x9.c rl_miibus_readreg(self, phy, reg)
phy 1369 dev/ic/rtl81x9.c int phy, reg;
phy 1380 dev/ic/rtl81x9.c if (phy != 0)
phy 1411 dev/ic/rtl81x9.c frame.mii_phyaddr = phy;
phy 1419 dev/ic/rtl81x9.c rl_miibus_writereg(self, phy, reg, val)
phy 1421 dev/ic/rtl81x9.c int phy, reg, val;
phy 1428 dev/ic/rtl81x9.c if (phy)
phy 1456 dev/ic/rtl81x9.c frame.mii_phyaddr = phy;
phy 1400 dev/ic/smc83c170.c epic_mii_read(struct device *self, int phy, int reg)
phy 1408 dev/ic/smc83c170.c MMCTL_ARG(phy, reg, MMCTL_READ));
phy 1421 dev/ic/smc83c170.c epic_mii_write(struct device *self, int phy, int reg, int val)
phy 1430 dev/ic/smc83c170.c MMCTL_ARG(phy, reg, MMCTL_WRITE));
phy 281 dev/ic/smc83c170reg.h #define MMCTL_ARG(phy, reg, cmd) (((phy) << 9) | ((reg) << 4) | (cmd))
phy 1301 dev/ic/smc91cxx.c smc91cxx_mii_readreg(self, phy, reg)
phy 1303 dev/ic/smc91cxx.c int phy, reg;
phy 1310 dev/ic/smc91cxx.c val = mii_bitbang_readreg(self, &smc91cxx_mii_bitbang_ops, phy, reg);
phy 1318 dev/ic/smc91cxx.c smc91cxx_mii_writereg(self, phy, reg, val)
phy 1320 dev/ic/smc91cxx.c int phy, reg, val;
phy 1326 dev/ic/smc91cxx.c mii_bitbang_writereg(self, &smc91cxx_mii_bitbang_ops, phy, reg, val);
phy 440 dev/ic/xl.c xl_miibus_readreg(struct device *self, int phy, int reg)
phy 445 dev/ic/xl.c if (!(sc->xl_flags & XL_FLAG_PHYOK) && phy != 24)
phy 450 dev/ic/xl.c frame.mii_phyaddr = phy;
phy 458 dev/ic/xl.c xl_miibus_writereg(struct device *self, int phy, int reg, int data)
phy 463 dev/ic/xl.c if (!(sc->xl_flags & XL_FLAG_PHYOK) && phy != 24)
phy 468 dev/ic/xl.c frame.mii_phyaddr = phy;
phy 850 dev/isa/if_ef_isapnp.c ef_miibus_readreg(dev, phy, reg)
phy 852 dev/isa/if_ef_isapnp.c int phy, reg;
phy 878 dev/isa/if_ef_isapnp.c ef_mii_writeb(sc, (phy & i) ? 1 : 0);
phy 923 dev/isa/if_ef_isapnp.c ef_miibus_writereg(dev, phy, reg, val)
phy 925 dev/isa/if_ef_isapnp.c int phy, reg, val;
phy 946 dev/isa/if_ef_isapnp.c ef_mii_writeb(sc, (phy & i) ? 1 : 0);
phy 121 dev/mii/mii_bitbang.c mii_bitbang_readreg(struct device *sc, mii_bitbang_ops_t ops, int phy,
phy 130 dev/mii/mii_bitbang.c mii_bitbang_sendbits(sc, ops, phy, 5);
phy 170 dev/mii/mii_bitbang.c int phy, int reg, int val)
phy 177 dev/mii/mii_bitbang.c mii_bitbang_sendbits(sc, ops, phy, 5);
phy 62 dev/mii/ukphy_subr.c ukphy_status(struct mii_softc *phy)
phy 64 dev/mii/ukphy_subr.c struct mii_data *mii = phy->mii_pdata;
phy 71 dev/mii/ukphy_subr.c bmsr = PHY_READ(phy, MII_BMSR) | PHY_READ(phy, MII_BMSR);
phy 75 dev/mii/ukphy_subr.c bmcr = PHY_READ(phy, MII_BMCR);
phy 97 dev/mii/ukphy_subr.c anlpar = PHY_READ(phy, MII_ANAR) & PHY_READ(phy, MII_ANLPAR);
phy 98 dev/mii/ukphy_subr.c if ((phy->mii_flags & MIIF_HAVE_GTCR) != 0 &&
phy 99 dev/mii/ukphy_subr.c (phy->mii_extcapabilities &
phy 101 dev/mii/ukphy_subr.c gtcr = PHY_READ(phy, MII_100T2CR);
phy 102 dev/mii/ukphy_subr.c gtsr = PHY_READ(phy, MII_100T2SR);
phy 1377 dev/pci/if_bce.c bce_mii_read(struct device *self, int phy, int reg)
phy 1389 dev/pci/if_bce.c (MII_COMMAND_ACK << 16) | BCE_MIPHY(phy) | BCE_MIREG(reg)); /* MAGIC */
phy 1400 dev/pci/if_bce.c "0x%08x\n", sc->bce_dev.dv_xname, phy, reg, val);
phy 1408 dev/pci/if_bce.c bce_mii_write(struct device *self, int phy, int reg, int val)
phy 1422 dev/pci/if_bce.c BCE_MIPHY(phy) | BCE_MIREG(reg));
phy 1435 dev/pci/if_bce.c "= 0x%08x\n", sc->bce_dev.dv_xname, phy, reg, val);
phy 483 dev/pci/if_bge.c bge_miibus_readreg(struct device *dev, int phy, int reg)
phy 498 dev/pci/if_bge.c if (phy != 1)
phy 509 dev/pci/if_bge.c BGE_MIPHY(phy)|BGE_MIREG(reg));
phy 540 dev/pci/if_bge.c bge_miibus_writereg(struct device *dev, int phy, int reg, int val)
phy 555 dev/pci/if_bge.c BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
phy 1084 dev/pci/if_bnx.c bnx_miibus_read_reg(struct device *dev, int phy, int reg)
phy 1091 dev/pci/if_bnx.c if (phy != sc->bnx_phy_addr) {
phy 1093 dev/pci/if_bnx.c "Invalid PHY address %d for PHY read!\n", phy);
phy 1107 dev/pci/if_bnx.c val = BNX_MIPHY(phy) | BNX_MIREG(reg) |
phy 1128 dev/pci/if_bnx.c "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg);
phy 1134 dev/pci/if_bnx.c "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", __FUNCTION__, phy,
phy 1159 dev/pci/if_bnx.c bnx_miibus_write_reg(struct device *dev, int phy, int reg, int val)
phy 1166 dev/pci/if_bnx.c if (phy != sc->bnx_phy_addr) {
phy 1168 dev/pci/if_bnx.c phy);
phy 1174 dev/pci/if_bnx.c phy, (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff);
phy 1186 dev/pci/if_bnx.c val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val |
phy 1423 dev/pci/if_cas.c cas_mii_readreg(struct device *self, int phy, int reg)
phy 1433 dev/pci/if_cas.c printf("cas_mii_readreg: phy %d reg %d\n", phy, reg);
phy 1437 dev/pci/if_cas.c v = (reg << CAS_MIF_REG_SHIFT) | (phy << CAS_MIF_PHY_SHIFT) |
phy 1453 dev/pci/if_cas.c cas_mii_writereg(struct device *self, int phy, int reg, int val)
phy 1464 dev/pci/if_cas.c phy, reg, val);
phy 1472 dev/pci/if_cas.c if (phy == CAS_PHYAD_EXTERNAL)
phy 1479 dev/pci/if_cas.c (phy << CAS_MIF_PHY_SHIFT) |
phy 1545 dev/pci/if_cas.c cas_pcs_readreg(struct device *self, int phy, int reg)
phy 1553 dev/pci/if_cas.c printf("cas_pcs_readreg: phy %d reg %d\n", phy, reg);
phy 1556 dev/pci/if_cas.c if (phy != CAS_PHYAD_EXTERNAL)
phy 1582 dev/pci/if_cas.c cas_pcs_writereg(struct device *self, int phy, int reg, int val)
phy 1591 dev/pci/if_cas.c phy, reg, val);
phy 1594 dev/pci/if_cas.c if (phy != CAS_PHYAD_EXTERNAL)
phy 698 dev/pci/if_che.c che_miibus_readreg(struct device *dev, int phy, int reg)
phy 701 dev/pci/if_che.c u_int32_t addr = CHE_MI1_PHYADDR(phy) | reg;
phy 713 dev/pci/if_che.c che_miibus_writereg(struct device *dev, int phy, int reg, int val)
phy 716 dev/pci/if_che.c u_int32_t addr = CHE_MI1_PHYADDR(phy) | reg;
phy 725 dev/pci/if_che.c che_miibus_ind_readreg(struct device *dev, int phy, int reg)
phy 729 dev/pci/if_che.c che_write(sc->sc_cheg, CHE_REG_MI1_ADDR, CHE_MI1_PHYADDR(phy));
phy 745 dev/pci/if_che.c che_miibus_ind_writereg(struct device *dev, int phy, int reg, int val)
phy 749 dev/pci/if_che.c che_write(sc->sc_cheg, CHE_REG_MI1_ADDR, CHE_MI1_PHYADDR(phy));
phy 238 dev/pci/if_lge.c lge_miibus_readreg(struct device *dev, int phy, int reg)
phy 248 dev/pci/if_lge.c if (sc->lge_pcs == 0 && phy == 0)
phy 251 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);
phy 266 dev/pci/if_lge.c lge_miibus_writereg(struct device *dev, int phy, int reg, int data)
phy 272 dev/pci/if_lge.c (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE);
phy 257 dev/pci/if_msk.c msk_miibus_readreg(struct device *dev, int phy, int reg)
phy 263 dev/pci/if_msk.c SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
phy 285 dev/pci/if_msk.c phy, reg, val));
phy 291 dev/pci/if_msk.c msk_miibus_writereg(struct device *dev, int phy, int reg, int val)
phy 297 dev/pci/if_msk.c phy, reg, val));
phy 300 dev/pci/if_msk.c SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
phy 342 dev/pci/if_nfe.c uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET;
phy 344 dev/pci/if_nfe.c phy = NFE_READ(sc, NFE_PHY_IFACE);
phy 345 dev/pci/if_nfe.c phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T);
phy 351 dev/pci/if_nfe.c phy |= NFE_PHY_HDX; /* half-duplex */
phy 359 dev/pci/if_nfe.c phy |= NFE_PHY_1000T;
phy 364 dev/pci/if_nfe.c phy |= NFE_PHY_100TX;
phy 374 dev/pci/if_nfe.c NFE_WRITE(sc, NFE_PHY_IFACE, phy);
phy 380 dev/pci/if_nfe.c nfe_miibus_readreg(struct device *dev, int phy, int reg)
phy 393 dev/pci/if_nfe.c NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg);
phy 414 dev/pci/if_nfe.c sc->mii_phyaddr = phy;
phy 417 dev/pci/if_nfe.c sc->sc_dev.dv_xname, phy, reg, val));
phy 423 dev/pci/if_nfe.c nfe_miibus_writereg(struct device *dev, int phy, int reg, int val)
phy 437 dev/pci/if_nfe.c ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg;
phy 535 dev/pci/if_nge.c nge_miibus_readreg(dev, phy, reg)
phy 537 dev/pci/if_nge.c int phy, reg;
phy 546 dev/pci/if_nge.c frame.mii_phyaddr = phy;
phy 554 dev/pci/if_nge.c nge_miibus_writereg(dev, phy, reg, data)
phy 556 dev/pci/if_nge.c int phy, reg, data;
phy 566 dev/pci/if_nge.c frame.mii_phyaddr = phy;
phy 2135 dev/pci/if_pcn.c pcn_mii_readreg(struct device *self, int phy, int reg)
phy 2140 dev/pci/if_pcn.c pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT));
phy 2154 dev/pci/if_pcn.c pcn_mii_writereg(struct device *self, int phy, int reg, int val)
phy 2158 dev/pci/if_pcn.c pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT));
phy 560 dev/pci/if_sis.c sis_miibus_readreg(struct device *self, int phy, int reg)
phy 566 dev/pci/if_sis.c if (phy != 0)
phy 592 dev/pci/if_sis.c if (phy != 0)
phy 596 dev/pci/if_sis.c (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
phy 619 dev/pci/if_sis.c frame.mii_phyaddr = phy;
phy 628 dev/pci/if_sis.c sis_miibus_writereg(struct device *self, int phy, int reg, int data)
phy 634 dev/pci/if_sis.c if (phy != 0)
phy 649 dev/pci/if_sis.c if (phy != 0)
phy 652 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
phy 667 dev/pci/if_sis.c frame.mii_phyaddr = phy;
phy 248 dev/pci/if_sk.c sk_xmac_miibus_readreg(struct device *dev, int phy, int reg)
phy 255 dev/pci/if_sk.c if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0)
phy 258 dev/pci/if_sk.c SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
phy 279 dev/pci/if_sk.c sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val)
phy 286 dev/pci/if_sk.c SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
phy 330 dev/pci/if_sk.c sk_marv_miibus_readreg(struct device *dev, int phy, int reg)
phy 336 dev/pci/if_sk.c if (phy != 0 ||
phy 340 dev/pci/if_sk.c phy, reg));
phy 344 dev/pci/if_sk.c SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
phy 366 dev/pci/if_sk.c phy, reg, val));
phy 372 dev/pci/if_sk.c sk_marv_miibus_writereg(struct device *dev, int phy, int reg, int val)
phy 378 dev/pci/if_sk.c phy, reg, val));
phy 381 dev/pci/if_sk.c SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
phy 2360 dev/pci/if_sk.c u_int32_t phy, v;
phy 2402 dev/pci/if_sk.c phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
phy 2406 dev/pci/if_sk.c phy |= SK_GPHY_COPPER;
phy 2408 dev/pci/if_sk.c phy |= SK_GPHY_FIBER;
phy 2410 dev/pci/if_sk.c DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy));
phy 2412 dev/pci/if_sk.c SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
phy 2414 dev/pci/if_sk.c SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
phy 334 dev/pci/if_ste.c ste_miibus_readreg(struct device *self, int phy, int reg)
phy 339 dev/pci/if_ste.c if (sc->ste_one_phy && phy != 0)
phy 344 dev/pci/if_ste.c frame.mii_phyaddr = phy;
phy 352 dev/pci/if_ste.c ste_miibus_writereg(struct device *self, int phy, int reg, int data)
phy 359 dev/pci/if_ste.c frame.mii_phyaddr = phy;
phy 1638 dev/pci/if_stge.c stge_mii_readreg(struct device *self, int phy, int reg)
phy 1641 dev/pci/if_stge.c return (mii_bitbang_readreg(self, &stge_mii_bitbang_ops, phy, reg));
phy 1650 dev/pci/if_stge.c stge_mii_writereg(struct device *self, int phy, int reg, int val)
phy 1653 dev/pci/if_stge.c mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg, val);
phy 738 dev/pci/if_tl.c int tl_miibus_readreg(dev, phy, reg)
phy 740 dev/pci/if_tl.c int phy, reg;
phy 747 dev/pci/if_tl.c frame.mii_phyaddr = phy;
phy 754 dev/pci/if_tl.c void tl_miibus_writereg(dev, phy, reg, data)
phy 756 dev/pci/if_tl.c int phy, reg, data;
phy 763 dev/pci/if_tl.c frame.mii_phyaddr = phy;
phy 312 dev/pci/if_vge.c vge_miibus_readreg(struct device *dev, int phy, int reg)
phy 318 dev/pci/if_vge.c if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F))
phy 350 dev/pci/if_vge.c vge_miibus_writereg(struct device *dev, int phy, int reg, int data)
phy 355 dev/pci/if_vge.c if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F))
phy 430 dev/pci/if_vr.c vr_miibus_readreg(struct device *dev, int phy, int reg)
phy 438 dev/pci/if_vr.c if (phy != 1)
phy 446 dev/pci/if_vr.c frame.mii_phyaddr = phy;
phy 454 dev/pci/if_vr.c vr_miibus_writereg(struct device *dev, int phy, int reg, int data)
phy 462 dev/pci/if_vr.c if (phy != 1)
phy 470 dev/pci/if_vr.c frame.mii_phyaddr = phy;
phy 481 dev/pci/if_wb.c wb_miibus_readreg(dev, phy, reg)
phy 483 dev/pci/if_wb.c int phy, reg;
phy 490 dev/pci/if_wb.c frame.mii_phyaddr = phy;
phy 498 dev/pci/if_wb.c wb_miibus_writereg(dev, phy, reg, data)
phy 500 dev/pci/if_wb.c int phy, reg, data;
phy 507 dev/pci/if_wb.c frame.mii_phyaddr = phy;
phy 929 dev/pcmcia/if_xe.c xe_mdi_read(self, phy, reg)
phy 931 dev/pcmcia/if_xe.c int phy;
phy 943 dev/pcmcia/if_xe.c xe_mdi_pulse_bits(sc, phy, 5); /* PHY address */
phy 954 dev/pcmcia/if_xe.c ("xe_mdi_read: phy %d reg %d -> %x\n", phy, reg, data));
phy 960 dev/pcmcia/if_xe.c xe_mdi_write(self, phy, reg, value)
phy 962 dev/pcmcia/if_xe.c int phy;
phy 973 dev/pcmcia/if_xe.c xe_mdi_pulse_bits(sc, phy, 5); /* PHY address */
phy 980 dev/pcmcia/if_xe.c ("xe_mdi_write: phy %d reg %d val %x\n", phy, reg, value));
phy 1224 dev/sbus/be.c be_pal_gate(struct be_softc *sc, int phy)
phy 1233 dev/sbus/be.c if (phy == BE_PHY_INTERNAL)
phy 1241 dev/sbus/be.c be_tcvr_read_bit(struct be_softc *sc, int phy)
phy 1247 dev/sbus/be.c if (phy == BE_PHY_INTERNAL) {
phy 1269 dev/sbus/be.c be_tcvr_write_bit(struct be_softc *sc, int phy, int bit)
phy 1275 dev/sbus/be.c if (phy == BE_PHY_INTERNAL) {
phy 1289 dev/sbus/be.c be_mii_sendbits(struct be_softc *sc, int phy, u_int32_t data, int nbits)
phy 1294 dev/sbus/be.c be_tcvr_write_bit(sc, phy, (data & i) != 0);
phy 1298 dev/sbus/be.c be_mii_readreg(struct device *self, int phy, int reg)
phy 1307 dev/sbus/be.c be_mii_sendbits(sc, phy, MII_COMMAND_START, 2);
phy 1308 dev/sbus/be.c be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2);
phy 1309 dev/sbus/be.c be_mii_sendbits(sc, phy, phy, 5);
phy 1310 dev/sbus/be.c be_mii_sendbits(sc, phy, reg, 5);
phy 1312 dev/sbus/be.c (void) be_tcvr_read_bit(sc, phy);
phy 1313 dev/sbus/be.c (void) be_tcvr_read_bit(sc, phy);
phy 1316 dev/sbus/be.c val |= (be_tcvr_read_bit(sc, phy) << i);
phy 1318 dev/sbus/be.c (void) be_tcvr_read_bit(sc, phy);
phy 1319 dev/sbus/be.c (void) be_tcvr_read_bit(sc, phy);
phy 1320 dev/sbus/be.c (void) be_tcvr_read_bit(sc, phy);
phy 1326 dev/sbus/be.c be_mii_writereg(struct device *self, int phy, int reg, int val)
phy 1335 dev/sbus/be.c be_mii_sendbits(sc, phy, MII_COMMAND_START, 2);
phy 1336 dev/sbus/be.c be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2);
phy 1337 dev/sbus/be.c be_mii_sendbits(sc, phy, phy, 5);
phy 1338 dev/sbus/be.c be_mii_sendbits(sc, phy, reg, 5);
phy 1340 dev/sbus/be.c be_tcvr_write_bit(sc, phy, 1);
phy 1341 dev/sbus/be.c be_tcvr_write_bit(sc, phy, 0);
phy 1344 dev/sbus/be.c be_tcvr_write_bit(sc, phy, (val >> i) & 1);
phy 1348 dev/sbus/be.c be_mii_reset(struct be_softc *sc, int phy)
phy 1352 dev/sbus/be.c be_mii_writereg((struct device *)sc, phy, MII_BMCR,
phy 1354 dev/sbus/be.c be_mii_writereg((struct device *)sc, phy, MII_BMCR, BMCR_RESET);
phy 1357 dev/sbus/be.c int bmcr = be_mii_readreg((struct device *)sc, phy, MII_BMCR);
phy 444 dev/usb/if_aue.c aue_miibus_readreg(struct device *dev, int phy, int reg)
phy 470 dev/usb/if_aue.c if (phy == 3)
phy 476 dev/usb/if_aue.c aue_csr_write_1(sc, AUE_PHY_ADDR, phy);
phy 491 dev/usb/if_aue.c sc->aue_dev.dv_xname, __func__, phy, reg, val));
phy 498 dev/usb/if_aue.c aue_miibus_writereg(struct device *dev, int phy, int reg, int data)
phy 506 dev/usb/if_aue.c if (phy == 3)
phy 512 dev/usb/if_aue.c sc->aue_dev.dv_xname, __func__, phy, reg, data));
phy 516 dev/usb/if_aue.c aue_csr_write_1(sc, AUE_PHY_ADDR, phy);
phy 264 dev/usb/if_axe.c axe_miibus_readreg(struct device *dev, int phy, int reg)
phy 281 dev/usb/if_axe.c DPRINTF(("axe_miibus_readreg: phy 0x%x reg 0x%x\n", phy, reg));
phy 283 dev/usb/if_axe.c if (sc->axe_phyaddrs[0] != AXE_NOPHY && phy != sc->axe_phyaddrs[0])
phy 286 dev/usb/if_axe.c if (sc->axe_phyaddrs[1] != AXE_NOPHY && phy != sc->axe_phyaddrs[1])
phy 289 dev/usb/if_axe.c if (sc->axe_phyaddrs[0] != 0xFF && sc->axe_phyaddrs[0] != phy)
phy 296 dev/usb/if_axe.c err = axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, val);
phy 306 dev/usb/if_axe.c sc->axe_phyaddrs[0] = phy;
phy 312 dev/usb/if_axe.c axe_miibus_writereg(struct device *dev, int phy, int reg, int val)
phy 325 dev/usb/if_axe.c err = axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, uval);
phy 1533 dev/usb/if_udav.c udav_miibus_readreg(struct device *dev, int phy, int reg)
phy 1545 dev/usb/if_udav.c sc->sc_dev.dv_xname, __func__, phy, reg));
phy 1556 dev/usb/if_udav.c if (phy != 0) {
phy 1558 dev/usb/if_udav.c sc->sc_dev.dv_xname, __func__, phy));
phy 1584 dev/usb/if_udav.c sc->sc_dev.dv_xname, __func__, phy, reg, data16));
phy 1590 dev/usb/if_udav.c udav_miibus_writereg(struct device *dev, int phy, int reg, int data)
phy 1601 dev/usb/if_udav.c sc->sc_dev.dv_xname, __func__, phy, reg, data));
phy 1612 dev/usb/if_udav.c if (phy != 0) {
phy 1614 dev/usb/if_udav.c sc->sc_dev.dv_xname, __func__, phy));
phy 1421 dev/usb/if_url.c url_int_miibus_readreg(struct device *dev, int phy, int reg)
phy 1432 dev/usb/if_url.c sc->sc_dev.dv_xname, __func__, phy, reg));
phy 1443 dev/usb/if_url.c if (phy != 0) {
phy 1445 dev/usb/if_url.c sc->sc_dev.dv_xname, __func__, phy));
phy 1487 dev/usb/if_url.c sc->sc_dev.dv_xname, __func__, phy, reg, val));
phy 1494 dev/usb/if_url.c url_int_miibus_writereg(struct device *dev, int phy, int reg, int data)
phy 1504 dev/usb/if_url.c sc->sc_dev.dv_xname, __func__, phy, reg, data));
phy 1515 dev/usb/if_url.c if (phy != 0) {
phy 1517 dev/usb/if_url.c sc->sc_dev.dv_xname, __func__, phy));
phy 1580 dev/usb/if_url.c url_ext_miibus_redreg(struct device *dev, int phy, int reg)
phy 1586 dev/usb/if_url.c sc->sc_dev.dv_xname, __func__, phy, reg));
phy 1598 dev/usb/if_url.c url_csr_write_1(sc, URL_PHYADD, phy & URL_PHYADD_MASK);
phy 1617 dev/usb/if_url.c sc->sc_dev.dv_xname, __func__, phy, reg, val));
phy 1624 dev/usb/if_url.c url_ext_miibus_writereg(struct device *dev, int phy, int reg, int data)
phy 1629 dev/usb/if_url.c sc->sc_dev.dv_xname, __func__, phy, reg, data));
phy 1642 dev/usb/if_url.c url_csr_write_1(sc, URL_PHYADD, phy);
phy 2113 dev/usb/if_zyd.c desc->phy = zyd_plcp_signal(rate);
phy 2115 dev/usb/if_zyd.c desc->phy |= ZYD_TX_PHY_OFDM;
phy 2117 dev/usb/if_zyd.c desc->phy |= ZYD_TX_PHY_5GHZ;
phy 2119 dev/usb/if_zyd.c desc->phy |= ZYD_TX_PHY_SHPREAMBLE;
phy 961 dev/usb/if_zydreg.h uint8_t phy;
phy 522 dev/usb/ueagle.c CR(sc, UEAGLE_CMV_STAT, 0, &sc->stats.phy.status);
phy 523 dev/usb/ueagle.c switch ((sc->stats.phy.status >> 8) & 0xf) {
phy 544 dev/usb/ueagle.c CR(sc, UEAGLE_CMV_DIAG, 1, &sc->stats.phy.flags);
phy 545 dev/usb/ueagle.c if (sc->stats.phy.flags & 0x10) {
phy 547 dev/usb/ueagle.c sc->stats.phy.status = 0;
phy 553 dev/usb/ueagle.c sc->stats.phy.dsrate = ((data >> 16) & 0x1ff) * 32;
phy 554 dev/usb/ueagle.c sc->stats.phy.usrate = (data & 0xff) * 32;
phy 557 dev/usb/ueagle.c sc->stats.phy.attenuation = (data & 0xff) / 2;
phy 560 dev/usb/ueagle.c CR(sc, UEAGLE_CMV_DIAG, 22, &sc->stats.phy.dserror);
phy 561 dev/usb/ueagle.c CR(sc, UEAGLE_CMV_DIAG, 25, &sc->stats.phy.dsmargin);
phy 562 dev/usb/ueagle.c CR(sc, UEAGLE_CMV_DIAG, 46, &sc->stats.phy.userror);
phy 563 dev/usb/ueagle.c CR(sc, UEAGLE_CMV_DIAG, 49, &sc->stats.phy.usmargin);
phy 564 dev/usb/ueagle.c CR(sc, UEAGLE_CMV_DIAG, 51, &sc->stats.phy.rxflow);
phy 565 dev/usb/ueagle.c CR(sc, UEAGLE_CMV_DIAG, 52, &sc->stats.phy.txflow);
phy 566 dev/usb/ueagle.c CR(sc, UEAGLE_CMV_DIAG, 54, &sc->stats.phy.dsunc);
phy 567 dev/usb/ueagle.c CR(sc, UEAGLE_CMV_DIAG, 58, &sc->stats.phy.usunc);
phy 568 dev/usb/ueagle.c CR(sc, UEAGLE_CMV_INFO, 8, &sc->stats.phy.vidco);
phy 569 dev/usb/ueagle.c CR(sc, UEAGLE_CMV_INFO, 14, &sc->stats.phy.vidcpe);
phy 139 dev/usb/ueaglevar.h } phy;