root/dev/pci/if_stge.c

DEFINITIONS

1. stge_match
2. stge_attach
3. stge_shutdown
4. stge_dma_wait
5. stge_start
6. stge_watchdog
7. stge_ioctl
8. stge_intr
9. stge_txintr
10. stge_rxintr
11. stge_tick
12. stge_stats_update
13. stge_reset
14. stge_init
15. stge_rxdrain
16. stge_stop
17. stge_eeprom_wait
18. stge_read_eeprom
19. stge_add_rxbuf
20. stge_set_filter
21. stge_mii_readreg
22. stge_mii_writereg
23. stge_mii_statchg
24. stge_mii_bitbang_read
25. stge_mii_bitbang_write
26. stge_mediastatus
27. stge_mediachange

    1 /*      $OpenBSD: if_stge.c,v 1.35 2006/12/29 22:16:05 kettenis Exp $   */
    2 /*      $NetBSD: if_stge.c,v 1.27 2005/05/16 21:35:32 bouyer Exp $      */
    4 /*-
    5  * Copyright (c) 2001 The NetBSD Foundation, Inc.
    6  * All rights reserved.
    7  *
    8  * This code is derived from software contributed to The NetBSD Foundation
    9  * by Jason R. Thorpe.
   10  *
   11  * Redistribution and use in source and binary forms, with or without
   12  * modification, are permitted provided that the following conditions
   13  * are met:
   14  * 1. Redistributions of source code must retain the above copyright
   15  *    notice, this list of conditions and the following disclaimer.
   16  * 2. Redistributions in binary form must reproduce the above copyright
   17  *    notice, this list of conditions and the following disclaimer in the
   18  *    documentation and/or other materials provided with the distribution.
   19  * 3. All advertising materials mentioning features or use of this software
   20  *    must display the following acknowledgement:
   21  *      This product includes software developed by the NetBSD
   22  *      Foundation, Inc. and its contributors.
   23  * 4. Neither the name of The NetBSD Foundation nor the names of its
   24  *    contributors may be used to endorse or promote products derived
   25  *    from this software without specific prior written permission.
   26  *
   27  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   29  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   30  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   37  * POSSIBILITY OF SUCH DAMAGE.
   38  */
   40 /*
   41  * Device driver for the Sundance Tech. TC9021 10/100/1000
   42  * Ethernet controller.
   43  */
   45 #include "bpfilter.h"
   46 #include "vlan.h"
   48 #include <sys/param.h>
   49 #include <sys/systm.h>
   50 #include <sys/timeout.h>
   51 #include <sys/mbuf.h>
   52 #include <sys/malloc.h>
   53 #include <sys/kernel.h>
   54 #include <sys/socket.h>
   55 #include <sys/ioctl.h>
   56 #include <sys/errno.h>
   57 #include <sys/device.h>
   58 #include <sys/queue.h>
   60 #include <net/if.h>
   61 #include <net/if_dl.h>
   63 #ifdef INET
   64 #include <netinet/in.h>
   65 #include <netinet/in_systm.h>
   66 #include <netinet/in_var.h>
   67 #include <netinet/ip.h>
   68 #include <netinet/if_ether.h>
   69 #endif
   71 #include <net/if_media.h>
   73 #if NVLAN > 0
   74 #include <net/if_types.h>
   75 #include <net/if_vlan_var.h>
   76 #endif
   78 #if NBPFILTER > 0
   79 #include <net/bpf.h>
   80 #endif
   82 #include <machine/bus.h>
   83 #include <machine/intr.h>
   85 #include <dev/mii/mii.h>
   86 #include <dev/mii/miivar.h>
   87 #include <dev/mii/mii_bitbang.h>
   89 #include <dev/pci/pcireg.h>
   90 #include <dev/pci/pcivar.h>
   91 #include <dev/pci/pcidevs.h>
   93 #include <dev/pci/if_stgereg.h>
   95 void    stge_start(struct ifnet *);
   96 void    stge_watchdog(struct ifnet *);
   97 int     stge_ioctl(struct ifnet *, u_long, caddr_t);
   98 int     stge_init(struct ifnet *);
   99 void    stge_stop(struct ifnet *, int);
  101 void    stge_shutdown(void *);
  103 void    stge_reset(struct stge_softc *);
  104 void    stge_rxdrain(struct stge_softc *);
  105 int     stge_add_rxbuf(struct stge_softc *, int);
  106 void    stge_read_eeprom(struct stge_softc *, int, uint16_t *);
  107 void    stge_tick(void *);
  109 void    stge_stats_update(struct stge_softc *);
  111 void    stge_set_filter(struct stge_softc *);
  113 int     stge_intr(void *);
  114 void    stge_txintr(struct stge_softc *);
  115 void    stge_rxintr(struct stge_softc *);
  117 int     stge_mii_readreg(struct device *, int, int);
  118 void    stge_mii_writereg(struct device *, int, int, int);
  119 void    stge_mii_statchg(struct device *);
  121 int     stge_mediachange(struct ifnet *);
  122 void    stge_mediastatus(struct ifnet *, struct ifmediareq *);
  124 int     stge_match(struct device *, void *, void *);
  125 void    stge_attach(struct device *, struct device *, void *);
  127 int     stge_copy_small = 0;
  129 struct cfattach stge_ca = {
  130         sizeof(struct stge_softc), stge_match, stge_attach,
  131 };
  133 struct cfdriver stge_cd = {
  134         0, "stge", DV_IFNET
  135 };
uint32_t stge_mii_bitbang_read(struct device *);
  138 void    stge_mii_bitbang_write(struct device *, uint32_t);
  140 const struct mii_bitbang_ops stge_mii_bitbang_ops = {
stge_mii_bitbang_read,
stge_mii_bitbang_write,
  143         {
PC_MgmtData,            /* MII_BIT_MDO */
PC_MgmtData,            /* MII_BIT_MDI */
PC_MgmtClk,             /* MII_BIT_MDC */
PC_MgmtDir,             /* MII_BIT_DIR_HOST_PHY */
  148                 0,                      /* MII_BIT_DIR_PHY_HOST */
  149         }
  150 };
  152 /*
  153  * Devices supported by this driver.
  154  */
  155 const struct pci_matchid stge_devices[] = {
  156         { PCI_VENDOR_SUNDANCE, PCI_PRODUCT_SUNDANCE_ST1023 },
  157         { PCI_VENDOR_SUNDANCE, PCI_PRODUCT_SUNDANCE_ST2021 },
  158         { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021 },
  159         { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021_ALT },
  160         /*
  161          * The Sundance sample boards use the Sundance vendor ID,
  162          * but the Tamarack product ID.
  163          */
  164         { PCI_VENDOR_SUNDANCE, PCI_PRODUCT_SUNDANCE_TC9021 },
  165         { PCI_VENDOR_SUNDANCE, PCI_PRODUCT_SUNDANCE_TC9021_ALT },
  166         { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550T },
  167         { PCI_VENDOR_ANTARES, PCI_PRODUCT_ANTARES_TC9021 }
  168 };
  170 int
stge_match(struct device *parent, void *match, void *aux)
  172 {
  173         return (pci_matchbyid((struct pci_attach_args *)aux, stge_devices,
  174             sizeof(stge_devices) / sizeof(stge_devices[0])));
  175 }
  177 void
stge_attach(struct device *parent, struct device *self, void *aux)
  179 {
  180         struct stge_softc *sc = (struct stge_softc *) self;
  181         struct pci_attach_args *pa = aux;
  182         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
pci_chipset_tag_t pc = pa->pa_pc;
pci_intr_handle_t ih;
  185         const char *intrstr = NULL;
bus_space_tag_t iot, memt;
bus_space_handle_t ioh, memh;
bus_dma_segment_t seg;
bus_size_t iosize;
  190         int ioh_valid, memh_valid;
  191         int i, rseg, error;
pcireg_t pmode;
  193         int pmreg;
timeout_set(&sc->sc_timeout, stge_tick, sc);
sc->sc_rev = PCI_REVISION(pa->pa_class);
  199         /*
  200          * Map the device.
  201          */
ioh_valid = (pci_mapreg_map(pa, STGE_PCI_IOBA,
PCI_MAPREG_TYPE_IO, 0,
  204             &iot, &ioh, NULL, &iosize, 0) == 0);
memh_valid = (pci_mapreg_map(pa, STGE_PCI_MMBA,
PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
  207             &memt, &memh, NULL, &iosize, 0) == 0);
  209         if (memh_valid) {
sc->sc_st = memt;
sc->sc_sh = memh;
  212         } else if (ioh_valid) {
sc->sc_st = iot;
sc->sc_sh = ioh;
  215         } else {
printf(": unable to map device registers\n");
  217                 return;
  218         }
sc->sc_dmat = pa->pa_dmat;
  222         /* Get it out of power save mode if needed. */
  223         if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) {
pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) &
PCI_PMCSR_STATE_MASK;
  226                 if (pmode == PCI_PMCSR_STATE_D3) {
  227                         /*
  228                          * The card has lost all configuration data in
  229                          * this state, so punt.
  230                          */
printf(": unable to wake up from power state D3\n");
  232                         return;
  233                 }
  234                 if (pmode != 0) {
printf(": waking up from power state D%d\n", pmode);
pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR,
PCI_PMCSR_STATE_D0);
  238                 }
  239         }
  241         /*
  242          * Map and establish our interrupt.
  243          */
  244         if (pci_intr_map(pa, &ih)) {
printf(": unable to map interrupt\n");
  246                 goto fail_0;
  247         }
intrstr = pci_intr_string(pc, ih);
sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, stge_intr, sc,
sc->sc_dev.dv_xname);
  251         if (sc->sc_ih == NULL) {
printf(": unable to establish interrupt");
  253                 if (intrstr != NULL)
printf(" at %s", intrstr);
printf("\n");
  256                 goto fail_0;
  257         }
printf(": %s", intrstr);
  260         /*
  261          * Allocate the control data structures, and create and load the
  262          * DMA map for it.
  263          */
  264         if ((error = bus_dmamem_alloc(sc->sc_dmat,
  265             sizeof(struct stge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg,
  266             0)) != 0) {
printf("%s: unable to allocate control data, error = %d\n",
sc->sc_dev.dv_xname, error);
  269                 goto fail_0;
  270         }
  272         if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
  273             sizeof(struct stge_control_data), (caddr_t *)&sc->sc_control_data,
BUS_DMA_COHERENT)) != 0) {
printf("%s: unable to map control data, error = %d\n",
sc->sc_dev.dv_xname, error);
  277                 goto fail_1;
  278         }
  280         if ((error = bus_dmamap_create(sc->sc_dmat,
  281             sizeof(struct stge_control_data), 1,
  282             sizeof(struct stge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) {
printf("%s: unable to create control data DMA map, "
  284                     "error = %d\n", sc->sc_dev.dv_xname, error);
  285                 goto fail_2;
  286         }
  288         if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap,
sc->sc_control_data, sizeof(struct stge_control_data), NULL,
  290             0)) != 0) {
printf("%s: unable to load control data DMA map, error = %d\n",
sc->sc_dev.dv_xname, error);
  293                 goto fail_3;
  294         }
  296         /*
  297          * Create the transmit buffer DMA maps.  Note that rev B.3
  298          * and earlier seem to have a bug regarding multi-fragment
  299          * packets.  We need to limit the number of Tx segments on
  300          * such chips to 1.
  301          */
  302         for (i = 0; i < STGE_NTXDESC; i++) {
  303                 if ((error = bus_dmamap_create(sc->sc_dmat,
STGE_JUMBO_FRAMELEN, STGE_NTXFRAGS, MCLBYTES, 0, 0,
  305                     &sc->sc_txsoft[i].ds_dmamap)) != 0) {
printf("%s: unable to create tx DMA map %d, "
  307                             "error = %d\n", sc->sc_dev.dv_xname, i, error);
  308                         goto fail_4;
  309                 }
  310         }
  312         /*
  313          * Create the receive buffer DMA maps.
  314          */
  315         for (i = 0; i < STGE_NRXDESC; i++) {
  316                 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) {
printf("%s: unable to create rx DMA map %d, "
  319                             "error = %d\n", sc->sc_dev.dv_xname, i, error);
  320                         goto fail_5;
  321                 }
sc->sc_rxsoft[i].ds_mbuf = NULL;
  323         }
  325         /*
  326          * Determine if we're copper or fiber.  It affects how we
  327          * reset the card.
  328          */
  329         if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia)
sc->sc_usefiber = 1;
  331         else
sc->sc_usefiber = 0;
  334         /*
  335          * Reset the chip to a known state.
  336          */
stge_reset(sc);
  339         /*
  340          * Reading the station address from the EEPROM doesn't seem
  341          * to work, at least on my sample boards.  Instead, since
  342          * the reset sequence does AutoInit, read it from the station
  343          * address registers. For Sundance 1023 you can only read it
  344          * from EEPROM.
  345          */
  346         if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_SUNDANCE_ST1023) {
sc->sc_arpcom.ac_enaddr[0] = CSR_READ_2(sc,
STGE_StationAddress0) & 0xff;
sc->sc_arpcom.ac_enaddr[1] = CSR_READ_2(sc,
STGE_StationAddress0) >> 8;
sc->sc_arpcom.ac_enaddr[2] = CSR_READ_2(sc,
STGE_StationAddress1) & 0xff;
sc->sc_arpcom.ac_enaddr[3] = CSR_READ_2(sc,
STGE_StationAddress1) >> 8;
sc->sc_arpcom.ac_enaddr[4] = CSR_READ_2(sc,
STGE_StationAddress2) & 0xff;
sc->sc_arpcom.ac_enaddr[5] = CSR_READ_2(sc,
STGE_StationAddress2) >> 8;
sc->sc_stge1023 = 0;
  360         } else {
uint16_t myaddr[ETHER_ADDR_LEN / 2];
  362                 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) {
stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i, 
  364                             &myaddr[i]);
myaddr[i] = letoh16(myaddr[i]);
  366                 }
  367                 (void)memcpy(sc->sc_arpcom.ac_enaddr, myaddr,
  368                     sizeof(sc->sc_arpcom.ac_enaddr));
sc->sc_stge1023 = 1;
  370         }
printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr));
  374         /*
  375          * Read some important bits from the PhyCtrl register.
  376          */
sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) &
  378             (PC_PhyDuplexPolarity | PC_PhyLnkPolarity);
  380         /*
  381          * Initialize our media structures and probe the MII.
  382          */
sc->sc_mii.mii_ifp = ifp;
sc->sc_mii.mii_readreg = stge_mii_readreg;
sc->sc_mii.mii_writereg = stge_mii_writereg;
sc->sc_mii.mii_statchg = stge_mii_statchg;
ifmedia_init(&sc->sc_mii.mii_media, 0, stge_mediachange,
stge_mediastatus);
mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
MII_OFFSET_ANY, MIIF_DOPAUSE);
  391         if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
  394         } else
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
ifp = &sc->sc_arpcom.ac_if;
strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, sizeof ifp->if_xname);
ifp->if_softc = sc;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_ioctl = stge_ioctl;
ifp->if_start = stge_start;
ifp->if_watchdog = stge_watchdog;
  404 #ifdef STGE_JUMBO
ifp->if_hardmtu = STGE_JUMBO_MTU;
  406 #endif
IFQ_SET_MAXLEN(&ifp->if_snd, STGE_NTXDESC - 1);
IFQ_SET_READY(&ifp->if_snd);
ifp->if_capabilities = IFCAP_VLAN_MTU;
  412         /*
  413          * The manual recommends disabling early transmit, so we
  414          * do.  It's disabled anyway, if using IP checksumming,
  415          * since the entire packet must be in the FIFO in order
  416          * for the chip to perform the checksum.
  417          */
sc->sc_txthresh = 0x0fff;
  420         /*
  421          * Disable MWI if the PCI layer tells us to.
  422          */
sc->sc_DMACtrl = 0;
  424 #ifdef fake
  425         if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0)
sc->sc_DMACtrl |= DMAC_MWIDisable;
  427 #endif
  429 #ifdef STGE_CHECKSUM
  430         /*
  431          * We can do IPv4/TCPv4/UDPv4 checksums in hardware.
  432          */
sc->sc_arpcom.ac_if.if_capabilities |= IFCAP_CSUM_IPv4 |
IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4;
  435 #endif
  437         /*
  438          * Attach the interface.
  439          */
if_attach(ifp);
ether_ifattach(ifp);
  443         /*
  444          * Make sure the interface is shutdown during reboot.
  445          */
sc->sc_sdhook = shutdownhook_establish(stge_shutdown, sc);
  447         if (sc->sc_sdhook == NULL)
printf("%s: WARNING: unable to establish shutdown hook\n",
sc->sc_dev.dv_xname);
  450         return;
  452         /*
  453          * Free any resources we've allocated during the failed attach
  454          * attempt.  Do this in reverse order and fall through.
  455          */
fail_5:
  457         for (i = 0; i < STGE_NRXDESC; i++) {
  458                 if (sc->sc_rxsoft[i].ds_dmamap != NULL)
bus_dmamap_destroy(sc->sc_dmat,
sc->sc_rxsoft[i].ds_dmamap);
  461         }
fail_4:
  463         for (i = 0; i < STGE_NTXDESC; i++) {
  464                 if (sc->sc_txsoft[i].ds_dmamap != NULL)
bus_dmamap_destroy(sc->sc_dmat,
sc->sc_txsoft[i].ds_dmamap);
  467         }
bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
fail_3:
bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
fail_2:
bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data,
  473             sizeof(struct stge_control_data));
fail_1:
bus_dmamem_free(sc->sc_dmat, &seg, rseg);
fail_0:
bus_space_unmap(sc->sc_st, sc->sc_sh, iosize);
  478         return;
  479 }
  481 /*
  482  * stge_shutdown:
  483  *
  484  *      Make sure the interface is stopped at reboot time.
  485  */
  486 void
stge_shutdown(void *arg)
  488 {
  489         struct stge_softc *sc = arg;
stge_stop(&sc->sc_arpcom.ac_if, 1);
  492 }
  494 static void
stge_dma_wait(struct stge_softc *sc)
  496 {
  497         int i;
  499         for (i = 0; i < STGE_TIMEOUT; i++) {
delay(2);
  501                 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0)
  502                         break;
  503         }
  505         if (i == STGE_TIMEOUT)
printf("%s: DMA wait timed out\n", sc->sc_dev.dv_xname);
  507 }
  509 /*
  510  * stge_start:          [ifnet interface function]
  511  *
  512  *      Start packet transmission on the interface.
  513  */
  514 void
stge_start(struct ifnet *ifp)
  516 {
  517         struct stge_softc *sc = ifp->if_softc;
  518         struct mbuf *m0;
  519         struct stge_descsoft *ds;
  520         struct stge_tfd *tfd;
bus_dmamap_t dmamap;
  522         int error, firsttx, nexttx, opending, seg, totlen;
uint64_t csum_flags = 0;
  525         if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
  526                 return;
  528         /*
  529          * Remember the previous number of pending transmissions
  530          * and the first descriptor we will use.
  531          */
opending = sc->sc_txpending;
firsttx = STGE_NEXTTX(sc->sc_txlast);
  535         /*
  536          * Loop through the send queue, setting up transmit descriptors
  537          * until we drain the queue, or use up all available transmit
  538          * descriptors.
  539          */
  540         for (;;) {
  541                 /*
  542                  * Grab a packet off the queue.
  543                  */
IFQ_POLL(&ifp->if_snd, m0);
  545                 if (m0 == NULL)
  546                         break;
  548                 /*
  549                  * Leave one unused descriptor at the end of the
  550                  * list to prevent wrapping completely around.
  551                  */
  552                 if (sc->sc_txpending == (STGE_NTXDESC - 1))
  553                         break;
  555                 /*
  556                  * Get the last and next available transmit descriptor.
  557                  */
nexttx = STGE_NEXTTX(sc->sc_txlast);
tfd = &sc->sc_txdescs[nexttx];
ds = &sc->sc_txsoft[nexttx];
dmamap = ds->ds_dmamap;
  564                 /*
  565                  * Load the DMA map.  If this fails, the packet either
  566                  * didn't fit in the alloted number of segments, or we
  567                  * were short on resources.  For the too-many-segments
  568                  * case, we simply report an error and drop the packet,
  569                  * since we can't sanely copy a jumbo packet to a single
  570                  * buffer.
  571                  */
error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
BUS_DMA_NOWAIT);
  574                 if (error) {
  575                         if (error == EFBIG) {
printf("%s: Tx packet consumes too many "
  577                                     "DMA segments (%u), dropping...\n",
sc->sc_dev.dv_xname, dmamap->dm_nsegs);
IFQ_DEQUEUE(&ifp->if_snd, m0);
m_freem(m0);
  581                                 continue;
  582                         }
  583                         /*
  584                          * Short on resources, just stop for now.
  585                          */
  586                         break;
  587                 }
IFQ_DEQUEUE(&ifp->if_snd, m0);
  591                 /*
  592                  * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
  593                  */
  595                 /* Sync the DMA map. */
bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
BUS_DMASYNC_PREWRITE);
  599                 /* Initialize the fragment list. */
  600                 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) {
tfd->tfd_frags[seg].frag_word0 =
htole64(FRAG_ADDR(dmamap->dm_segs[seg].ds_addr) |
FRAG_LEN(dmamap->dm_segs[seg].ds_len));
totlen += dmamap->dm_segs[seg].ds_len;
  605                 }
  607 #ifdef STGE_CHECKSUM
  608                 /*
  609                  * Initialize checksumming flags in the descriptor.
  610                  * Byte-swap constants so the compiler can optimize.
  611                  */
  612                 if (m0->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT)
csum_flags |= TFD_IPChecksumEnable;
  615                 if (m0->m_pkthdr.csum_flags & M_TCPV4_CSUM_OUT)
csum_flags |= TFD_TCPChecksumEnable;
  617                 else if (m0->m_pkthdr.csum_flags & M_UDPV4_CSUM_OUT)
csum_flags |= TFD_UDPChecksumEnable;
  619 #endif
  621                 /*
  622                  * Initialize the descriptor and give it to the chip.
  623                  */
tfd->tfd_control = htole64(TFD_FrameId(nexttx) |
TFD_WordAlign(/*totlen & */3) |
TFD_FragCount(seg) | csum_flags |
  627                     (((nexttx & STGE_TXINTR_SPACING_MASK) == 0) ?
TFD_TxDMAIndicate : 0));
  630                 /* Sync the descriptor. */
STGE_CDTXSYNC(sc, nexttx,
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
  634                 /*
  635                  * Kick the transmit DMA logic.
  636                  */
CSR_WRITE_4(sc, STGE_DMACtrl,
sc->sc_DMACtrl | DMAC_TxDMAPollNow);
  640                 /*
  641                  * Store a pointer to the packet so we can free it later.
  642                  */
ds->ds_mbuf = m0;
  645                 /* Advance the tx pointer. */
sc->sc_txpending++;
sc->sc_txlast = nexttx;
  649 #if NBPFILTER > 0
  650                 /*
  651                  * Pass the packet to any BPF listeners.
  652                  */
  653                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m0, BPF_DIRECTION_OUT);
  655 #endif /* NBPFILTER > 0 */
  656         }
  658         if (sc->sc_txpending == (STGE_NTXDESC - 1)) {
  659                 /* No more slots left; notify upper layer. */
ifp->if_flags |= IFF_OACTIVE;
  661         }
  663         if (sc->sc_txpending != opending) {
  664                 /*
  665                  * We enqueued packets.  If the transmitter was idle,
  666                  * reset the txdirty pointer.
  667                  */
  668                 if (opending == 0)
sc->sc_txdirty = firsttx;
  671                 /* Set a watchdog timer in case the chip flakes out. */
ifp->if_timer = 5;
  673         }
  674 }
  676 /*
  677  * stge_watchdog:       [ifnet interface function]
  678  *
  679  *      Watchdog timer handler.
  680  */
  681 void
stge_watchdog(struct ifnet *ifp)
  683 {
  684         struct stge_softc *sc = ifp->if_softc;
  686         /*
  687          * Sweep up first, since we don't interrupt every frame.
  688          */
stge_txintr(sc);
  690         if (sc->sc_txpending != 0) {
printf("%s: device timeout\n", sc->sc_dev.dv_xname);
ifp->if_oerrors++;
  694                 (void) stge_init(ifp);
  696                 /* Try to get more packets going. */
stge_start(ifp);
  698         }
  699 }
  701 /*
  702  * stge_ioctl:          [ifnet interface function]
  703  *
  704  *      Handle control requests from the operator.
  705  */
  706 int
stge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
  708 {
  709         struct stge_softc *sc = ifp->if_softc;
  710         struct ifreq *ifr = (struct ifreq *)data;
  711         struct ifaddr *ifa = (struct ifaddr *)data;
  712         int s, error;
s = splnet();
  716         if ((error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data)) > 0) {
  717                 /* Try to get more packets going. */
stge_start(ifp);
splx(s);
  721                 return (error);
  722         }
  724         switch (cmd) {
  725         case SIOCSIFADDR:
ifp->if_flags |= IFF_UP;
  727                 if (!(ifp->if_flags & IFF_RUNNING))
stge_init(ifp);
  730 #ifdef INET
  731                 if (ifa->ifa_addr->sa_family == AF_INET)
arp_ifinit(&sc->sc_arpcom, ifa);
  733 #endif
  734                 break;
  736         case SIOCSIFMTU:
  737                 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ifp->if_hardmtu)
error = EINVAL;
  739                 else if (ifp->if_mtu != ifr->ifr_mtu)
ifp->if_mtu = ifr->ifr_mtu;
  741                 break;
  743         case SIOCSIFFLAGS:
  744                 if (ifp->if_flags & IFF_UP) {
  745                         if (ifp->if_flags & IFF_RUNNING &&
  746                             (ifp->if_flags ^ sc->stge_if_flags) &
IFF_PROMISC) {
stge_set_filter(sc);
  749                         } else {
  750                                 if (!(ifp->if_flags & IFF_RUNNING))
stge_init(ifp);
  752                         }
  753                 } else {
  754                         if (ifp->if_flags & IFF_RUNNING)
stge_stop(ifp, 1);
  756                 }
sc->stge_if_flags = ifp->if_flags;
  758                 break;
  760         case SIOCADDMULTI:
  761         case SIOCDELMULTI:
error = (cmd == SIOCADDMULTI) ?
ether_addmulti(ifr, &sc->sc_arpcom) :
ether_delmulti(ifr, &sc->sc_arpcom);
  766                 if (error == ENETRESET) {
  767                         /*
  768                          * Multicast list has changed; set the hardware
  769                          * filter accordingly.
  770                          */
  771                         if (ifp->if_flags & IFF_RUNNING)
stge_set_filter(sc);
error = 0;
  774                 }
  775                 break;
  777         case SIOCSIFMEDIA:
  778         case SIOCGIFMEDIA:
error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
  780                 break;
  782         default:
error = ENOTTY;
  784         }
  786         /* Try to get more packets going. */
stge_start(ifp);
splx(s);
  790         return (error);
  791 }
  793 /*
  794  * stge_intr:
  795  *
  796  *      Interrupt service routine.
  797  */
  798 int
stge_intr(void *arg)
  800 {
  801         struct stge_softc *sc = arg;
  802         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
uint32_t txstat;
  804         int wantinit;
uint16_t isr;
  807         if ((CSR_READ_2(sc, STGE_IntStatus) & IS_InterruptStatus) == 0)
  808                 return (0);
  810         for (wantinit = 0; wantinit == 0;) {
isr = CSR_READ_2(sc, STGE_IntStatusAck);
  812                 if ((isr & sc->sc_IntEnable) == 0)
  813                         break;
  815                 /* Host interface errors. */
  816                 if (isr & IS_HostError) {
printf("%s: Host interface error\n",
sc->sc_dev.dv_xname);
wantinit = 1;
  820                         continue;
  821                 }
  823                 /* Receive interrupts. */
  824                 if (isr & (IS_RxDMAComplete|IS_RFDListEnd)) {
stge_rxintr(sc);
  826                         if (isr & IS_RFDListEnd) {
printf("%s: receive ring overflow\n",
sc->sc_dev.dv_xname);
  829                                 /*
  830                                  * XXX Should try to recover from this
  831                                  * XXX more gracefully.
  832                                  */
wantinit = 1;
  834                         }
  835                 }
  837                 /* Transmit interrupts. */
  838                 if (isr & (IS_TxDMAComplete|IS_TxComplete))
stge_txintr(sc);
  841                 /* Statistics overflow. */
  842                 if (isr & IS_UpdateStats)
stge_stats_update(sc);
  845                 /* Transmission errors. */
  846                 if (isr & IS_TxComplete) {
  847                         for (;;) {
txstat = CSR_READ_4(sc, STGE_TxStatus);
  849                                 if ((txstat & TS_TxComplete) == 0)
  850                                         break;
  851                                 if (txstat & TS_TxUnderrun) {
sc->sc_txthresh++;
  853                                         if (sc->sc_txthresh > 0x0fff)
sc->sc_txthresh = 0x0fff;
printf("%s: transmit underrun, new "
  856                                             "threshold: %d bytes\n",
sc->sc_dev.dv_xname,
sc->sc_txthresh << 5);
  859                                 }
  860                                 if (txstat & TS_MaxCollisions)
printf("%s: excessive collisions\n",
sc->sc_dev.dv_xname);
  863                         }
wantinit = 1;
  865                 }
  867         }
  869         if (wantinit)
stge_init(ifp);
CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
  874         /* Try to get more packets going. */
stge_start(ifp);
  877         return (1);
  878 }
  880 /*
  881  * stge_txintr:
  882  *
  883  *      Helper; handle transmit interrupts.
  884  */
  885 void
stge_txintr(struct stge_softc *sc)
  887 {
  888         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
  889         struct stge_descsoft *ds;
uint64_t control;
  891         int i;
ifp->if_flags &= ~IFF_OACTIVE;
  895         /*
  896          * Go through our Tx list and free mbufs for those
  897          * frames which have been transmitted.
  898          */
  899         for (i = sc->sc_txdirty; sc->sc_txpending != 0;
i = STGE_NEXTTX(i), sc->sc_txpending--) {
ds = &sc->sc_txsoft[i];
STGE_CDTXSYNC(sc, i,
BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
control = letoh64(sc->sc_txdescs[i].tfd_control);
  907                 if ((control & TFD_TFDDone) == 0)
  908                         break;
bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap,
  911                     0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
m_freem(ds->ds_mbuf);
ds->ds_mbuf = NULL;
  915         }
  917         /* Update the dirty transmit buffer pointer. */
sc->sc_txdirty = i;
  920         /*
  921          * If there are no more pending transmissions, cancel the watchdog
  922          * timer.
  923          */
  924         if (sc->sc_txpending == 0)
ifp->if_timer = 0;
  926 }
  928 /*
  929  * stge_rxintr:
  930  *
  931  *      Helper; handle receive interrupts.
  932  */
  933 void
stge_rxintr(struct stge_softc *sc)
  935 {
  936         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
  937         struct stge_descsoft *ds;
  938         struct mbuf *m, *tailm;
uint64_t status;
  940         int i, len;
  942         for (i = sc->sc_rxptr;; i = STGE_NEXTRX(i)) {
ds = &sc->sc_rxsoft[i];
STGE_CDRXSYNC(sc, i,
BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
status = letoh64(sc->sc_rxdescs[i].rfd_status);
  950                 if ((status & RFD_RFDDone) == 0)
  951                         break;
  953                 if (__predict_false(sc->sc_rxdiscard)) {
STGE_INIT_RXDESC(sc, i);
  955                         if (status & RFD_FrameEnd) {
  956                                 /* Reset our state. */
sc->sc_rxdiscard = 0;
  958                         }
  959                         continue;
  960                 }
bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
m = ds->ds_mbuf;
  967                 /*
  968                  * Add a new receive buffer to the ring.
  969                  */
  970                 if (stge_add_rxbuf(sc, i) != 0) {
  971                         /*
  972                          * Failed, throw away what we've done so
  973                          * far, and discard the rest of the packet.
  974                          */
ifp->if_ierrors++;
bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
STGE_INIT_RXDESC(sc, i);
  979                         if ((status & RFD_FrameEnd) == 0)
sc->sc_rxdiscard = 1;
  981                         if (sc->sc_rxhead != NULL)
m_freem(sc->sc_rxhead);
STGE_RXCHAIN_RESET(sc);
  984                         continue;
  985                 }
  987 #ifdef DIAGNOSTIC
  988                 if (status & RFD_FrameStart) {
KASSERT(sc->sc_rxhead == NULL);
KASSERT(sc->sc_rxtailp == &sc->sc_rxhead);
  991                 }
  992 #endif
STGE_RXCHAIN_LINK(sc, m);
  996                 /*
  997                  * If this is not the end of the packet, keep
  998                  * looking.
  999                  */
 1000                 if ((status & RFD_FrameEnd) == 0) {
sc->sc_rxlen += m->m_len;
 1002                         continue;
 1003                 }
 1005                 /*
 1006                  * Okay, we have the entire packet now...
 1007                  */
 1008                 *sc->sc_rxtailp = NULL;
m = sc->sc_rxhead;
tailm = sc->sc_rxtail;
STGE_RXCHAIN_RESET(sc);
 1014                 /*
 1015                  * If the packet had an error, drop it.  Note we
 1016                  * count the error later in the periodic stats update.
 1017                  */
 1018                 if (status & (RFD_RxFIFOOverrun | RFD_RxRuntFrame |
RFD_RxAlignmentError | RFD_RxFCSError |
RFD_RxLengthError)) {
m_freem(m);
 1022                         continue;
 1023                 }
 1025                 /*
 1026                  * No errors.
 1027                  *
 1028                  * Note we have configured the chip to not include
 1029                  * the CRC at the end of the packet.
 1030                  */
len = RFD_RxDMAFrameLen(status);
tailm->m_len = len - sc->sc_rxlen;
 1034                 /*
 1035                  * If the packet is small enough to fit in a
 1036                  * single header mbuf, allocate one and copy
 1037                  * the data into it.  This greatly reduces
 1038                  * memory consumption when we receive lots
 1039                  * of small packets.
 1040                  */
 1041                 if (stge_copy_small != 0 && len <= (MHLEN - 2)) {
 1042                         struct mbuf *nm;
MGETHDR(nm, M_DONTWAIT, MT_DATA);
 1044                         if (nm == NULL) {
ifp->if_ierrors++;
m_freem(m);
 1047                                 continue;
 1048                         }
nm->m_data += 2;
nm->m_pkthdr.len = nm->m_len = len;
m_copydata(m, 0, len, mtod(nm, caddr_t));
m_freem(m);
m = nm;
 1054                 }
 1056                 /*
 1057                  * Set the incoming checksum information for the packet.
 1058                  */
 1059                 if (status & RFD_IPDetected) {
 1060                         if (!(status & RFD_IPError))
m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK;
 1062                         if ((status & RFD_TCPDetected) &&
 1063                            (!(status & RFD_TCPError)))
m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK;
 1065                         else if ((status & RFD_UDPDetected) &&
 1066                                 (!(status & RFD_UDPError)))
m->m_pkthdr.csum_flags |= M_UDP_CSUM_IN_OK;
 1068                 }
m->m_pkthdr.rcvif = ifp;
m->m_pkthdr.len = len;
 1073 #if NBPFILTER > 0
 1074                 /*
 1075                  * Pass this up to any BPF listeners, but only
 1076                  * pass if up the stack if it's for us.
 1077                  */
 1078                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN);
 1080 #endif /* NBPFILTER > 0 */
 1082                 /* Pass it on. */
ether_input_mbuf(ifp, m);
 1084         }
 1086         /* Update the receive pointer. */
sc->sc_rxptr = i;
 1088 }
 1090 /*
 1091  * stge_tick:
 1092  *
 1093  *      One second timer, used to tick the MII.
 1094  */
 1095 void
stge_tick(void *arg)
 1097 {
 1098         struct stge_softc *sc = arg;
 1099         int s;
s = splnet();
mii_tick(&sc->sc_mii);
stge_stats_update(sc);
splx(s);
timeout_add(&sc->sc_timeout, hz);
 1107 }
 1109 /*
 1110  * stge_stats_update:
 1111  *
 1112  *      Read the TC9021 statistics counters.
 1113  */
 1114 void
stge_stats_update(struct stge_softc *sc)
 1116 {
 1117         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
 1119         (void) CSR_READ_4(sc, STGE_OctetRcvOk);
ifp->if_ipackets +=
CSR_READ_4(sc, STGE_FramesRcvdOk);
ifp->if_ierrors +=
 1125             (u_int) CSR_READ_2(sc, STGE_FramesLostRxErrors);
 1127         (void) CSR_READ_4(sc, STGE_OctetXmtdOk);
ifp->if_opackets +=
CSR_READ_4(sc, STGE_FramesXmtdOk);
ifp->if_collisions +=
CSR_READ_4(sc, STGE_LateCollisions) +
CSR_READ_4(sc, STGE_MultiColFrames) +
CSR_READ_4(sc, STGE_SingleColFrames);
ifp->if_oerrors +=
 1138             (u_int) CSR_READ_2(sc, STGE_FramesAbortXSColls) +
 1139             (u_int) CSR_READ_2(sc, STGE_FramesWEXDeferal);
 1140 }
 1142 /*
 1143  * stge_reset:
 1144  *
 1145  *      Perform a soft reset on the TC9021.
 1146  */
 1147 void
stge_reset(struct stge_softc *sc)
 1149 {
uint32_t ac;
 1151         int i;
ac = CSR_READ_4(sc, STGE_AsicCtrl);
 1155         /*
 1156          * Only assert RstOut if we're fiber.  We need GMII clocks
 1157          * to be present in order for the reset to complete on fiber
 1158          * cards.
 1159          */
CSR_WRITE_4(sc, STGE_AsicCtrl,
ac | AC_GlobalReset | AC_RxReset | AC_TxReset |
AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit |
 1163             (sc->sc_usefiber ? AC_RstOut : 0));
delay(50000);
 1167         for (i = 0; i < STGE_TIMEOUT; i++) {
delay(5000);
 1169                 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
 1170                         break;
 1171         }
 1173         if (i == STGE_TIMEOUT)
printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname);
delay(1000);
 1177 }
 1179 /*
 1180  * stge_init:           [ ifnet interface function ]
 1181  *
 1182  *      Initialize the interface.  Must be called at splnet().
 1183  */
 1184 int
stge_init(struct ifnet *ifp)
 1186 {
 1187         struct stge_softc *sc = ifp->if_softc;
 1188         struct stge_descsoft *ds;
 1189         int i, error = 0;
 1191         /*
 1192          * Cancel any pending I/O.
 1193          */
stge_stop(ifp, 0);
 1196         /*
 1197          * Reset the chip to a known state.
 1198          */
stge_reset(sc);
 1201         /*
 1202          * Initialize the transmit descriptor ring.
 1203          */
memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
 1205         for (i = 0; i < STGE_NTXDESC; i++) {
sc->sc_txdescs[i].tfd_next = htole64(
STGE_CDTXADDR(sc, STGE_NEXTTX(i)));
sc->sc_txdescs[i].tfd_control = htole64(TFD_TFDDone);
 1209         }
sc->sc_txpending = 0;
sc->sc_txdirty = 0;
sc->sc_txlast = STGE_NTXDESC - 1;
 1214         /*
 1215          * Initialize the receive descriptor and receive job
 1216          * descriptor rings.
 1217          */
 1218         for (i = 0; i < STGE_NRXDESC; i++) {
ds = &sc->sc_rxsoft[i];
 1220                 if (ds->ds_mbuf == NULL) {
 1221                         if ((error = stge_add_rxbuf(sc, i)) != 0) {
printf("%s: unable to allocate or map rx "
 1223                                     "buffer %d, error = %d\n",
sc->sc_dev.dv_xname, i, error);
 1225                                 /*
 1226                                  * XXX Should attempt to run with fewer receive
 1227                                  * XXX buffers instead of just failing.
 1228                                  */
stge_rxdrain(sc);
 1230                                 goto out;
 1231                         }
 1232                 } else
STGE_INIT_RXDESC(sc, i);
 1234         }
sc->sc_rxptr = 0;
sc->sc_rxdiscard = 0;
STGE_RXCHAIN_RESET(sc);
 1239         /* Set the station address. */
 1240         for (i = 0; i < 6; i++)
CSR_WRITE_1(sc, STGE_StationAddress0 + i,
sc->sc_arpcom.ac_enaddr[i]);
 1244         /*
 1245          * Set the statistics masks.  Disable all the RMON stats,
 1246          * and disable selected stats in the non-RMON stats registers.
 1247          */
CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff);
CSR_WRITE_4(sc, STGE_StatisticsMask,
 1250             (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) |
 1251             (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) |
 1252             (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) |
 1253             (1U << 21));
 1255         /* Set up the receive filter. */
stge_set_filter(sc);
 1258         /*
 1259          * Give the transmit and receive ring to the chip.
 1260          */
CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0); /* NOTE: 32-bit DMA */
CSR_WRITE_4(sc, STGE_TFDListPtrLo,
STGE_CDTXADDR(sc, sc->sc_txdirty));
CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0); /* NOTE: 32-bit DMA */
CSR_WRITE_4(sc, STGE_RFDListPtrLo,
STGE_CDRXADDR(sc, sc->sc_rxptr));
 1269         /*
 1270          * Initialize the Tx auto-poll period.  It's OK to make this number
 1271          * large (255 is the max, but we use 127) -- we explicitly kick the
 1272          * transmit engine when there's actually a packet.
 1273          */
CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
 1276         /* ..and the Rx auto-poll period. */
CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 64);
 1279         /* Initialize the Tx start threshold. */
CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh);
 1282         /* RX DMA thresholds, from linux */
CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30);
CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30);
 1286         /* Rx early threhold, from Linux */
CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff);
 1289         /* Tx DMA thresholds, from Linux */
CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30);
CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04);
 1293         /*
 1294          * Initialize the Rx DMA interrupt control register.  We
 1295          * request an interrupt after every incoming packet, but
 1296          * defer it for 32us (64 * 512 ns).  When the number of
 1297          * interrupts pending reaches 8, we stop deferring the
 1298          * interrupt, and signal it immediately.
 1299          */
CSR_WRITE_4(sc, STGE_RxDMAIntCtrl,
RDIC_RxFrameCount(8) | RDIC_RxDMAWaitTime(512));
 1303         /*
 1304          * Initialize the interrupt mask.
 1305          */
sc->sc_IntEnable = IS_HostError | IS_TxComplete | IS_UpdateStats |
IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd;
CSR_WRITE_2(sc, STGE_IntStatus, 0xffff);
CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
 1311         /*
 1312          * Configure the DMA engine.
 1313          * XXX Should auto-tune TxBurstLimit.
 1314          */
CSR_WRITE_4(sc, STGE_DMACtrl, sc->sc_DMACtrl |
DMAC_TxBurstLimit(3));
 1318         /*
 1319          * Send a PAUSE frame when we reach 29,696 bytes in the Rx
 1320          * FIFO, and send an un-PAUSE frame when the FIFO is totally
 1321          * empty again.
 1322          */
CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16);
CSR_WRITE_2(sc, STGE_FlowOffThresh, 0);
 1326         /*
 1327          * Set the maximum frame size.
 1328          */
 1329 #ifdef STGE_JUMBO
CSR_WRITE_2(sc, STGE_MaxFrameSize, STGE_JUMBO_FRAMELEN);
 1331 #else
CSR_WRITE_2(sc, STGE_MaxFrameSize, ETHER_MAX_LEN);
 1333 #endif
 1335         /*
 1336          * Initialize MacCtrl -- do it before setting the media,
 1337          * as setting the media will actually program the register.
 1338          *
 1339          * Note: We have to poke the IFS value before poking
 1340          * anything else.
 1341          */
sc->sc_MACCtrl = MC_IFSSelect(0);
CSR_WRITE_4(sc, STGE_MACCtrl, sc->sc_MACCtrl);
sc->sc_MACCtrl |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable;
 1346         if (sc->sc_rev >= 6) {          /* >= B.2 */
 1347                 /* Multi-frag frame bug work-around. */
CSR_WRITE_2(sc, STGE_DebugCtrl,
CSR_READ_2(sc, STGE_DebugCtrl) | 0x0200);
 1351                 /* Tx Poll Now bug work-around. */
CSR_WRITE_2(sc, STGE_DebugCtrl,
CSR_READ_2(sc, STGE_DebugCtrl) | 0x0010);
 1354                 /* XXX ? from linux */
CSR_WRITE_2(sc, STGE_DebugCtrl,
CSR_READ_2(sc, STGE_DebugCtrl) | 0x0020);
 1357         }
 1359         /*
 1360          * Set the current media.
 1361          */
mii_mediachg(&sc->sc_mii);
 1364         /*
 1365          * Start the one second MII clock.
 1366          */
timeout_add(&sc->sc_timeout, hz);
 1369         /*
 1370          * ...all done!
 1371          */
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
out:
 1376         if (error)
printf("%s: interface not running\n", sc->sc_dev.dv_xname);
 1378         return (error);
 1379 }
 1381 /*
 1382  * stge_drain:
 1383  *
 1384  *      Drain the receive queue.
 1385  */
 1386 void
stge_rxdrain(struct stge_softc *sc)
 1388 {
 1389         struct stge_descsoft *ds;
 1390         int i;
 1392         for (i = 0; i < STGE_NRXDESC; i++) {
ds = &sc->sc_rxsoft[i];
 1394                 if (ds->ds_mbuf != NULL) {
bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
ds->ds_mbuf->m_next = NULL;
m_freem(ds->ds_mbuf);
ds->ds_mbuf = NULL;
 1399                 }
 1400         }
 1401 }
 1403 /*
 1404  * stge_stop:           [ ifnet interface function ]
 1405  *
 1406  *      Stop transmission on the interface.
 1407  */
 1408 void
stge_stop(struct ifnet *ifp, int disable)
 1410 {
 1411         struct stge_softc *sc = ifp->if_softc;
 1412         struct stge_descsoft *ds;
 1413         int i;
 1415         /*
 1416          * Stop the one second clock.
 1417          */
timeout_del(&sc->sc_timeout);
 1420         /*
 1421          * Mark the interface down and cancel the watchdog timer.
 1422          */
ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
ifp->if_timer = 0;
 1426         /* Down the MII. */
mii_down(&sc->sc_mii);
 1429         /*
 1430          * Disable interrupts.
 1431          */
CSR_WRITE_2(sc, STGE_IntEnable, 0);
 1434         /*
 1435          * Stop receiver, transmitter, and stats update.
 1436          */
CSR_WRITE_4(sc, STGE_MACCtrl,
MC_StatisticsDisable | MC_TxDisable | MC_RxDisable);
 1440         /*
 1441          * Stop the transmit and receive DMA.
 1442          */
stge_dma_wait(sc);
CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0);
CSR_WRITE_4(sc, STGE_TFDListPtrLo, 0);
CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0);
CSR_WRITE_4(sc, STGE_RFDListPtrLo, 0);
 1449         /*
 1450          * Release any queued transmit buffers.
 1451          */
 1452         for (i = 0; i < STGE_NTXDESC; i++) {
ds = &sc->sc_txsoft[i];
 1454                 if (ds->ds_mbuf != NULL) {
bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
m_freem(ds->ds_mbuf);
ds->ds_mbuf = NULL;
 1458                 }
 1459         }
 1461         if (disable)
stge_rxdrain(sc);
 1463 }
 1465 static int
stge_eeprom_wait(struct stge_softc *sc)
 1467 {
 1468         int i;
 1470         for (i = 0; i < STGE_TIMEOUT; i++) {
delay(1000);
 1472                 if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0)
 1473                         return (0);
 1474         }
 1475         return (1);
 1476 }
 1478 /*
 1479  * stge_read_eeprom:
 1480  *
 1481  *      Read data from the serial EEPROM.
 1482  */
 1483 void
stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data)
 1485 {
 1487         if (stge_eeprom_wait(sc))
printf("%s: EEPROM failed to come ready\n",
sc->sc_dev.dv_xname);
CSR_WRITE_2(sc, STGE_EepromCtrl,
EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR));
 1493         if (stge_eeprom_wait(sc))
printf("%s: EEPROM read timed out\n",
sc->sc_dev.dv_xname);
 1496         *data = CSR_READ_2(sc, STGE_EepromData);
 1497 }
 1499 /*
 1500  * stge_add_rxbuf:
 1501  *
 1502  *      Add a receive buffer to the indicated descriptor.
 1503  */
 1504 int
stge_add_rxbuf(struct stge_softc *sc, int idx)
 1506 {
 1507         struct stge_descsoft *ds = &sc->sc_rxsoft[idx];
 1508         struct mbuf *m;
 1509         int error;
MGETHDR(m, M_DONTWAIT, MT_DATA);
 1512         if (m == NULL)
 1513                 return (ENOBUFS);
MCLGET(m, M_DONTWAIT);
 1516         if ((m->m_flags & M_EXT) == 0) {
m_freem(m);
 1518                 return (ENOBUFS);
 1519         }
m->m_data = m->m_ext.ext_buf + 2;
m->m_len = MCLBYTES - 2;
 1524         if (ds->ds_mbuf != NULL)
bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
ds->ds_mbuf = m;
error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap,
m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT);
 1531         if (error) {
printf("%s: can't load rx DMA map %d, error = %d\n",
sc->sc_dev.dv_xname, idx, error);
panic("stge_add_rxbuf");        /* XXX */
 1535         }
bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
STGE_INIT_RXDESC(sc, idx);
 1542         return (0);
 1543 }
 1545 /*
 1546  * stge_set_filter:
 1547  *
 1548  *      Set up the receive filter.
 1549  */
 1550 void
stge_set_filter(struct stge_softc *sc)
 1552 {
 1553         struct arpcom *ac = &sc->sc_arpcom;
 1554         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
 1555         struct ether_multi *enm;
 1556         struct ether_multistep step;
uint32_t crc;
uint32_t mchash[2];
sc->sc_ReceiveMode = RM_ReceiveUnicast;
 1561         if (ifp->if_flags & IFF_BROADCAST)
sc->sc_ReceiveMode |= RM_ReceiveBroadcast;
 1564         /* XXX: ST1023 only works in promiscuous mode */
 1565         if (sc->sc_stge1023)
ifp->if_flags |= IFF_PROMISC;
 1568         if (ifp->if_flags & IFF_PROMISC) {
sc->sc_ReceiveMode |= RM_ReceiveAllFrames;
 1570                 goto allmulti;
 1571         }
 1573         /*
 1574          * Set up the multicast address filter by passing all multicast
 1575          * addresses through a CRC generator, and then using the low-order
 1576          * 6 bits as an index into the 64 bit multicast hash table.  The
 1577          * high order bits select the register, while the rest of the bits
 1578          * select the bit within the register.
 1579          */
memset(mchash, 0, sizeof(mchash));
ETHER_FIRST_MULTI(step, ac, enm);
 1584         if (enm == NULL)
 1585                 goto done;
 1587         while (enm != NULL) {
 1588                 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
 1589                         /*
 1590                          * We must listen to a range of multicast addresses.
 1591                          * For now, just accept all multicasts, rather than
 1592                          * trying to set only those filter bits needed to match
 1593                          * the range.  (At this time, the only use of address
 1594                          * ranges is for IP multicast routing, for which the
 1595                          * range is big enough to require all bits set.)
 1596                          */
 1597                         goto allmulti;
 1598                 }
crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN);
 1602                 /* Just want the 6 least significant bits. */
crc &= 0x3f;
 1605                 /* Set the corresponding bit in the hash table. */
mchash[crc >> 5] |= 1 << (crc & 0x1f);
ETHER_NEXT_MULTI(step, enm);
 1609         }
sc->sc_ReceiveMode |= RM_ReceiveMulticastHash;
ifp->if_flags &= ~IFF_ALLMULTI;
 1614         goto done;
allmulti:
ifp->if_flags |= IFF_ALLMULTI;
sc->sc_ReceiveMode |= RM_ReceiveMulticast;
done:
 1621         if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
 1622                 /*
 1623                  * Program the multicast hash table.
 1624                  */
CSR_WRITE_4(sc, STGE_HashTable0, mchash[0]);
CSR_WRITE_4(sc, STGE_HashTable1, mchash[1]);
 1627         }
CSR_WRITE_2(sc, STGE_ReceiveMode, sc->sc_ReceiveMode);
 1630 }
 1632 /*
 1633  * stge_mii_readreg:    [mii interface function]
 1634  *
 1635  *      Read a PHY register on the MII of the TC9021.
 1636  */
 1637 int
stge_mii_readreg(struct device *self, int phy, int reg)
 1639 {
 1641         return (mii_bitbang_readreg(self, &stge_mii_bitbang_ops, phy, reg));
 1642 }
 1644 /*
 1645  * stge_mii_writereg:   [mii interface function]
 1646  *
 1647  *      Write a PHY register on the MII of the TC9021.
 1648  */
 1649 void
stge_mii_writereg(struct device *self, int phy, int reg, int val)
 1651 {
mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg, val);
 1654 }
 1656 /*
 1657  * stge_mii_statchg:    [mii interface function]
 1658  *
 1659  *      Callback from MII layer when media changes.
 1660  */
 1661 void
stge_mii_statchg(struct device *self)
 1663 {
 1664         struct stge_softc *sc = (struct stge_softc *) self;
 1666         if (sc->sc_mii.mii_media_active & IFM_FDX)
sc->sc_MACCtrl |= MC_DuplexSelect;
 1668         else
sc->sc_MACCtrl &= ~MC_DuplexSelect;
 1671         /* XXX 802.1x flow-control? */
CSR_WRITE_4(sc, STGE_MACCtrl, sc->sc_MACCtrl);
 1674 }
 1676 /*
 1677  * sste_mii_bitbang_read: [mii bit-bang interface function]
 1678  *
 1679  *      Read the MII serial port for the MII bit-bang module.
 1680  */
uint32_t
stge_mii_bitbang_read(struct device *self)
 1683 {
 1684         struct stge_softc *sc = (void *) self;
 1686         return (CSR_READ_1(sc, STGE_PhyCtrl));
 1687 }
 1689 /*
 1690  * stge_mii_bitbang_write: [mii big-bang interface function]
 1691  *
 1692  *      Write the MII serial port for the MII bit-bang module.
 1693  */
 1694 void
stge_mii_bitbang_write(struct device *self, uint32_t val)
 1696 {
 1697         struct stge_softc *sc = (void *) self;
CSR_WRITE_1(sc, STGE_PhyCtrl, val | sc->sc_PhyCtrl);
 1700 }
 1702 /*
 1703  * stge_mediastatus:    [ifmedia interface function]
 1704  *
 1705  *      Get the current interface media status.
 1706  */
 1707 void
stge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
 1709 {
 1710         struct stge_softc *sc = ifp->if_softc;
mii_pollstat(&sc->sc_mii);
ifmr->ifm_status = sc->sc_mii.mii_media_status;
ifmr->ifm_active = sc->sc_mii.mii_media_active;
 1715 }
 1717 /*
 1718  * stge_mediachange:    [ifmedia interface function]
 1719  *
 1720  *      Set hardware to newly-selected media.
 1721  */
 1722 int
stge_mediachange(struct ifnet *ifp)
 1724 {
 1725         struct stge_softc *sc = ifp->if_softc;
 1727         if (ifp->if_flags & IFF_UP)
mii_mediachg(&sc->sc_mii);
 1729         return (0);
 1730 }