1 /* $OpenBSD: intrdefs.h,v 1.8 2007/04/21 21:06:15 gwk Exp $ */
2 /* $NetBSD: intrdefs.h,v 1.2 2003/05/04 22:01:56 fvdl Exp $ */
3
4 #ifndef _i386_INTRDEFS_H
5 #define _i386_INTRDEFS_H
6
7 /*
8 * Intel APICs (advanced programmable interrupt controllers) have
9 * bytesized priority registers where the upper nibble is the actual
10 * interrupt priority level (a.k.a. IPL). Interrupt vectors are
11 * closely tied to these levels as interrupts whose vectors' upper
12 * nibble is lower than or equal to the current level are blocked.
13 * Not all 256 possible vectors are available for interrupts in
14 * APIC systems, only
15 *
16 * For systems where instead the older ICU (interrupt controlling
17 * unit, a.k.a. PIC or 82C59) is used, the IPL is not directly useful,
18 * since the interrupt blocking is handled via interrupt masks instead
19 * of levels. However the IPL is easily used as an offset into arrays
20 * of masks.
21 */
22 #define IPLSHIFT 4 /* The upper nibble of vectors is the IPL. */
23 #define NIPL 16 /* Four bits of information gives as much. */
24 #define IPL(level) ((level) >> IPLSHIFT) /* Extract the IPL. */
25 /* XXX Maybe this IDTVECOFF definition should be elsewhere? */
26 #define IDTVECOFF 0x20 /* The lower 32 IDT vectors are reserved. */
27
28 /*
29 * This macro is only defined for 0 <= x < 14, i.e. there are fourteen
30 * distinct priority levels available for interrupts.
31 */
32 #define MAKEIPL(priority) (IDTVECOFF + ((priority) << IPLSHIFT))
33
34 /*
35 * Interrupt priority levels.
36 *
37 * XXX We are somewhat sloppy about what we mean by IPLs, sometimes
38 * XXX we refer to the eight-bit value suitable for storing into APICs'
39 * XXX priority registers, other times about the four-bit entity found
40 * XXX in the former values' upper nibble, which can be used as offsets
41 * XXX in various arrays of our implementation. We are hoping that
42 * XXX the context will provide enough information to not make this
43 * XXX sloppy naming a real problem.
44 *
45 * There are tty, network and disk drivers that use free() at interrupt
46 * time, so imp > (tty | net | bio).
47 *
48 * Since run queues may be manipulated by both the statclock and tty,
49 * network, and disk drivers, clock > imp.
50 *
51 * IPL_HIGH must block everything that can manipulate a run queue.
52 *
53 * XXX Ultimately we may need serial drivers to run at the absolute highest
54 * XXX priority to avoid overruns, then we must make serial > high.
55 *
56 * The level numbers are picked to fit into APIC vector priorities.
57 */
58 #define IPL_NONE 0 /* nothing */
59 #define IPL_SOFTAST MAKEIPL(0) /* AST */
60 #define IPL_SOFTCLOCK MAKEIPL(1) /* timeouts */
61 #define IPL_SOFTNET MAKEIPL(2) /* protocol stacks */
62 #define IPL_BIO MAKEIPL(3) /* block I/O */
63 #define IPL_NET MAKEIPL(4) /* network */
64 #define IPL_SOFTTTY MAKEIPL(5) /* delayed terminal handling */
65 #define IPL_TTY MAKEIPL(6) /* terminal */
66 #define IPL_VM MAKEIPL(7) /* memory allocation */
67 #define IPL_AUDIO MAKEIPL(8) /* audio */
68 #define IPL_CLOCK MAKEIPL(9) /* clock */
69 #define IPL_STATCLOCK MAKEIPL(10) /* statclock */
70 #define IPL_SCHED IPL_STATCLOCK
71 #define IPL_HIGH MAKEIPL(11) /* everything */
72 #define IPL_IPI MAKEIPL(12) /* interprocessor interrupt */
73
74 /* Interrupt sharing types. */
75 #define IST_NONE 0 /* none */
76 #define IST_PULSE 1 /* pulsed */
77 #define IST_EDGE 2 /* edge-triggered */
78 #define IST_LEVEL 3 /* level-triggered */
79
80 /*
81 * Local APIC masks. Must not conflict with SIR_* below, and must
82 * be >= NUM_LEGACY_IRQs. Note that LIR_IPI must be first.
83 */
84 #define LIR_IPI 31
85 #define LIR_TIMER 30
86
87 /* Soft interrupt masks. */
88 #define SIR_CLOCK 29
89 #define SIR_NET 28
90 #define SIR_TTY 27
91 #define SIR_AST 26
92
93
94 /*
95 * Maximum # of interrupt sources per CPU. 32 to fit in one word.
96 * ioapics can theoretically produce more, but it's not likely to
97 * happen. For multiple ioapics, things can be routed to different
98 * CPUs.
99 */
100 #define MAX_INTR_SOURCES 32
101 #define NUM_LEGACY_IRQS 16
102
103 /*
104 * Low and high boundaries between which interrupt gates will
105 * be allocated in the IDT.
106 */
107 #define IDT_INTR_LOW (0x20 + NUM_LEGACY_IRQS)
108 #define IDT_INTR_HIGH 0xef
109
110 #define I386_IPI_HALT 0x00000001
111 #define I386_IPI_MICROSET 0x00000002
112 #define I386_IPI_FLUSH_FPU 0x00000004
113 #define I386_IPI_SYNCH_FPU 0x00000008
114 #define I386_IPI_TLB 0x00000010
115 #define I386_IPI_MTRR 0x00000020
116 #define I386_IPI_GDT 0x00000040
117 #define I386_IPI_DDB 0x00000080 /* synchronize while in ddb */
118 #define I386_IPI_SETPERF 0x00000100
119
120 #define I386_NIPI 9
121
122 #define I386_IPI_NAMES { "halt IPI", "timeset IPI", "FPU flush IPI", \
123 "FPU synch IPI", "TLB shootdown IPI", \
124 "MTRR update IPI", "GDT update IPI", \
125 "DDB IPI", "setperf IPI" }
126
127 #define IREENT_MAGIC 0x18041969
128
129 #endif /* _I386_INTRDEFS_H */