root/dev/pci/if_stgereg.h

INCLUDED FROM

    1 /*      $OpenBSD: if_stgereg.h,v 1.8 2006/07/12 19:02:25 brad Exp $     */
    2 /*      $NetBSD: if_stgereg.h,v 1.3 2003/02/10 21:10:07 christos Exp $  */
    4 /*-
    5  * Copyright (c) 2001 The NetBSD Foundation, Inc.
    6  * All rights reserved.
    7  *
    8  * This code is derived from software contributed to The NetBSD Foundation
    9  * by Jason R. Thorpe.
   10  *
   11  * Redistribution and use in source and binary forms, with or without
   12  * modification, are permitted provided that the following conditions
   13  * are met:
   14  * 1. Redistributions of source code must retain the above copyright
   15  *    notice, this list of conditions and the following disclaimer.
   16  * 2. Redistributions in binary form must reproduce the above copyright
   17  *    notice, this list of conditions and the following disclaimer in the
   18  *    documentation and/or other materials provided with the distribution.
   19  * 3. All advertising materials mentioning features or use of this software
   20  *    must display the following acknowledgement:
   21  *      This product includes software developed by the NetBSD
   22  *      Foundation, Inc. and its contributors.
   23  * 4. Neither the name of The NetBSD Foundation nor the names of its
   24  *    contributors may be used to endorse or promote products derived
   25  *    from this software without specific prior written permission.
   26  *
   27  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   29  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   30  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   37  * POSSIBILITY OF SUCH DAMAGE.
   38  */
   40 #ifndef _DEV_PCI_IF_STGEREG_H_
   41 #define _DEV_PCI_IF_STGEREG_H_
   43 /*
   44  * Register description for the Sundance Tech. TC9021 10/100/1000
   45  * Ethernet controller.
   46  *
   47  * Note that while DMA addresses are all in 64-bit fields, only
   48  * the lower 40 bits of a DMA address are valid.
   49  */
   51 /*
   52  * Register access macros
   53  */
   54 #define CSR_WRITE_4(_sc, reg, val)      \
bus_space_write_4((_sc)->sc_st, (_sc)->sc_sh, (reg), (val))
   56 #define CSR_WRITE_2(_sc, reg, val)      \
bus_space_write_2((_sc)->sc_st, (_sc)->sc_sh, (reg), (val))
   58 #define CSR_WRITE_1(_sc, reg, val)      \
bus_space_write_1((_sc)->sc_st, (_sc)->sc_sh, (reg), (val))
   61 #define CSR_READ_4(_sc, reg)            \
bus_space_read_4((_sc)->sc_st, (_sc)->sc_sh, (reg))
   63 #define CSR_READ_2(_sc, reg)            \
bus_space_read_2((_sc)->sc_st, (_sc)->sc_sh, (reg))
   65 #define CSR_READ_1(_sc, reg)            \
bus_space_read_1((_sc)->sc_st, (_sc)->sc_sh, (reg))
   68 /*
   69  * TC9021 buffer fragment descriptor.
   70  */
   71 struct stge_frag {
uint64_t        frag_word0;     /* address, length */
   73 } __packed;
   75 #define FRAG_ADDR(x)    (((uint64_t)(x)) << 0)
   76 #define FRAG_ADDR_MASK  FRAG_ADDR(0xfffffffffULL)
   77 #define FRAG_LEN(x)     (((uint64_t)(x)) << 48)
   78 #define FRAG_LEN_MASK   FRAG_LEN(0xffffULL)
   80 /*
   81  * TC9021 Transmit Frame Descriptor.  Note the number of fragments
   82  * here is arbitrary, but we can't have any more than 15.
   83  */
   84 #define STGE_NTXFRAGS   12
   85 struct stge_tfd {
uint64_t        tfd_next;       /* next TFD in list */
uint64_t        tfd_control;    /* control bits */
   88                                         /* the buffer fragments */
   89         struct stge_frag tfd_frags[STGE_NTXFRAGS];
   90 } __packed;
   92 #define TFD_FrameId(x)          ((x) << 0)
   93 #define TFD_FrameId_MAX         0xffff
   94 #define TFD_WordAlign(x)        ((x) << 16)
   95 #define TFD_WordAlign_dword     0               /* align to dword in TxFIFO */
   96 #define TFD_WordAlign_word      2               /* align to word in TxFIFO */
   97 #define TFD_WordAlign_disable   1               /* disable alignment */
   98 #define TFD_TCPChecksumEnable   (1ULL << 18)
   99 #define TFD_UDPChecksumEnable   (1ULL << 19)
  100 #define TFD_IPChecksumEnable    (1ULL << 20)
  101 #define TFD_FcsAppendDisable    (1ULL << 21)
  102 #define TFD_TxIndicate          (1ULL << 22)
  103 #define TFD_TxDMAIndicate       (1ULL << 23)
  104 #define TFD_FragCount(x)        ((x) << 24)
  105 #define TFD_VLANTagInsert       (1ULL << 28)
  106 #define TFD_TFDDone             (1ULL << 31)
  107 #define TFD_VID(x)              (((uint64_t)(x)) << 32)
  108 #define TFD_CFI                 (1ULL << 44)
  109 #define TFD_UserPriority(x)     (((uint64_t)(x)) << 45)
  111 /*
  112  * TC9021 Receive Frame Descriptor.  Each RFD has a single fragment
  113  * in it, and the chip tells us the beginning and end of the frame.
  114  */
  115 struct stge_rfd {
uint64_t        rfd_next;       /* next RFD in list */
uint64_t        rfd_status;     /* status bits */
  118         struct stge_frag rfd_frag;      /* the buffer */
  119 } __packed;
  121 #define RFD_RxDMAFrameLen(x)    ((x) & 0xffff)
  122 #define RFD_RxFIFOOverrun       (1ULL << 16)
  123 #define RFD_RxRuntFrame         (1ULL << 17)
  124 #define RFD_RxAlignmentError    (1ULL << 18)
  125 #define RFD_RxFCSError          (1ULL << 19)
  126 #define RFD_RxOversizedFrame    (1ULL << 20)
  127 #define RFD_RxLengthError       (1ULL << 21)
  128 #define RFD_VLANDetected        (1ULL << 22)
  129 #define RFD_TCPDetected         (1ULL << 23)
  130 #define RFD_TCPError            (1ULL << 24)
  131 #define RFD_UDPDetected         (1ULL << 25)
  132 #define RFD_UDPError            (1ULL << 26)
  133 #define RFD_IPDetected          (1ULL << 27)
  134 #define RFD_IPError             (1ULL << 28)
  135 #define RFD_FrameStart          (1ULL << 29)
  136 #define RFD_FrameEnd            (1ULL << 30)
  137 #define RFD_RFDDone             (1ULL << 31)
  138 #define RFD_TCI(x)              ((((uint64_t)(x)) >> 32) & 0xffff)
  140 /*
  141  * PCI configuration registers used by the TC9021.
  142  */
  144 #define STGE_PCI_IOBA           (PCI_MAPREG_START + 0x00)
  145 #define STGE_PCI_MMBA           (PCI_MAPREG_START + 0x04)
  147 /*
  148  * EEPROM offsets.
  149  */
  150 #define STGE_EEPROM_ConfigParam         0x00
  151 #define STGE_EEPROM_AsicCtrl            0x01
  152 #define STGE_EEPROM_SubSystemVendorId   0x02
  153 #define STGE_EEPROM_SubSystemId         0x03
  154 #define STGE_EEPROM_StationAddress0     0x10
  155 #define STGE_EEPROM_StationAddress1     0x11
  156 #define STGE_EEPROM_StationAddress2     0x12
  158 /*
  159  * The TC9021 register space.
  160  */
  162 #define STGE_DMACtrl                    0x00
  163 #define DMAC_RxDMAComplete              (1U << 3)
  164 #define DMAC_RxDMAPollNow               (1U << 4)
  165 #define DMAC_TxDMAComplete              (1U << 11)
  166 #define DMAC_TxDMAPollNow               (1U << 12)
  167 #define DMAC_TxDMAInProg                (1U << 15)
  168 #define DMAC_RxEarlyDisable             (1U << 16)
  169 #define DMAC_MWIDisable                 (1U << 18)
  170 #define DMAC_TxWiteBackDisable          (1U << 19)
  171 #define DMAC_TxBurstLimit(x)            ((x) << 20)
  172 #define DMAC_TargetAbort                (1U << 30)
  173 #define DMAC_MasterAbort                (1U << 31)
  175 #define STGE_RxDMAStatus                0x08
  177 #define STGE_TFDListPtrLo               0x10
  179 #define STGE_TFDListPtrHi               0x14
  181 #define STGE_TxDMABurstThresh           0x18    /* 8-bit */
  183 #define STGE_TxDMAUrgentThresh          0x19    /* 8-bit */
  185 #define STGE_TxDMAPollPeriod            0x1a    /* 8-bit */
  187 #define STGE_RFDListPtrLo               0x1c
  189 #define STGE_RFDListPtrHi               0x20
  191 #define STGE_RxDMABurstThresh           0x24    /* 8-bit */
  193 #define STGE_RxDMAUrgentThresh          0x25    /* 8-bit */
  195 #define STGE_RxDMAPollPeriod            0x26    /* 8-bit */
  197 #define STGE_RxDMAIntCtrl               0x28
  198 #define RDIC_RxFrameCount(x)            ((x) & 0xff)
  199 #define RDIC_PriorityThresh(x)          ((x) << 10)
  200 #define RDIC_RxDMAWaitTime(x)           ((x) << 16)
  202 #define STGE_DebugCtrl                  0x2c    /* 16-bit */
  203 #define DC_GPIO0Ctrl                    (1U << 0)
  204 #define DC_GPIO1Ctrl                    (1U << 1)
  205 #define DC_GPIO0                        (1U << 2)
  206 #define DC_GPIO1                        (1U << 3)
  208 #define STGE_AsicCtrl                   0x30
  209 #define AC_ExpRomDisable                (1U << 0)
  210 #define AC_ExpRomSize                   (1U << 1)
  211 #define AC_PhySpeed10                   (1U << 4)
  212 #define AC_PhySpeed100                  (1U << 5)
  213 #define AC_PhySpeed1000                 (1U << 6)
  214 #define AC_PhyMedia                     (1U << 7)
  215 #define AC_ForcedConfig(x)              ((x) << 8)
  216 #define AC_ForcedConfig_MASK            AC_ForcedConfig(7)
  217 #define AC_D3ResetDisable               (1U << 11)
  218 #define AC_SpeedupMode                  (1U << 13)
  219 #define AC_LEDMode                      (1U << 14)
  220 #define AC_RstOutPolarity               (1U << 15)
  221 #define AC_GlobalReset                  (1U << 16)
  222 #define AC_RxReset                      (1U << 17)
  223 #define AC_TxReset                      (1U << 18)
  224 #define AC_DMA                          (1U << 19)
  225 #define AC_FIFO                         (1U << 20)
  226 #define AC_Network                      (1U << 21)
  227 #define AC_Host                         (1U << 22)
  228 #define AC_AutoInit                     (1U << 23)
  229 #define AC_RstOut                       (1U << 24)
  230 #define AC_InterruptRequest             (1U << 25)
  231 #define AC_ResetBusy                    (1U << 26)
  233 #define STGE_FIFOCtrl                   0x38    /* 16-bit */
  234 #define FC_RAMTestMode                  (1U << 0)
  235 #define FC_Transmitting                 (1U << 14)
  236 #define FC_Receiving                    (1U << 15)
  238 #define STGE_RxEarlyThresh              0x3a    /* 16-bit */
  240 #define STGE_FlowOffThresh              0x3c    /* 16-bit */
  242 #define STGE_FlowOnTresh                0x3e    /* 16-bit */
  244 #define STGE_TxStartThresh              0x44    /* 16-bit */
  246 #define STGE_EepromData                 0x48    /* 16-bit */
  248 #define STGE_EepromCtrl                 0x4a    /* 16-bit */
  249 #define EC_EepromAddress(x)             ((x) & 0xff)
  250 #define EC_EepromOpcode(x)              ((x) << 8)
  251 #define EC_OP_WE                        0
  252 #define EC_OP_WR                        1
  253 #define EC_OP_RR                        2
  254 #define EC_OP_ER                        3
  255 #define EC_EepromBusy                   (1U << 15)
  257 #define STGE_ExpRomAddr                 0x4c
  259 #define STGE_ExpRomData                 0x50    /* 8-bit */
  261 #define STGE_WakeEvent                  0x51    /* 8-bit */
  263 #define STGE_Countdown                  0x54
  264 #define CD_Count(x)                     ((x) & 0xffff)
  265 #define CD_CountdownSpeed               (1U << 24)
  266 #define CD_CountdownMode                (1U << 25)
  267 #define CD_CountdownIntEnabled          (1U << 26)
  269 #define STGE_IntStatusAck               0x5a    /* 16-bit */
  271 #define STGE_IntStatus                  0x5e    /* 16-bit */
  273 #define STGE_IntEnable                  0x5c    /* 16-bit */
  275 #define IS_InterruptStatus              (1U << 0)
  276 #define IS_HostError                    (1U << 1)
  277 #define IS_TxComplete                   (1U << 2)
  278 #define IS_MACControlFrame              (1U << 3)
  279 #define IS_RxComplete                   (1U << 4)
  280 #define IS_RxEarly                      (1U << 5)
  281 #define IS_InRequested                  (1U << 6)
  282 #define IS_UpdateStats                  (1U << 7)
  283 #define IS_LinkEvent                    (1U << 8)
  284 #define IS_TxDMAComplete                (1U << 9)
  285 #define IS_RxDMAComplete                (1U << 10)
  286 #define IS_RFDListEnd                   (1U << 11)
  287 #define IS_RxDMAPriority                (1U << 12)
  289 #define STGE_TxStatus                   0x60
  290 #define TS_TxError                      (1U << 0)
  291 #define TS_LateCollision                (1U << 2)
  292 #define TS_MaxCollisions                (1U << 3)
  293 #define TS_TxUnderrun                   (1U << 4)
  294 #define TS_TxIndicateReqd               (1U << 6)
  295 #define TS_TxComplete                   (1U << 7)
  296 #define TS_TxFrameId_get(x)             ((x) >> 16)
  298 #define STGE_MACCtrl                    0x6c
  299 #define MC_IFSSelect(x)                 ((x) & 3)
  300 #define MC_DuplexSelect                 (1U << 5)
  301 #define MC_RcvLargeFrames               (1U << 6)
  302 #define MC_TxFlowControlEnable          (1U << 7)
  303 #define MC_RxFlowControlEnable          (1U << 8)
  304 #define MC_RcvFCS                       (1U << 9)
  305 #define MC_FIFOLoopback                 (1U << 10)
  306 #define MC_MACLoopback                  (1U << 11)
  307 #define MC_AutoVLANtagging              (1U << 12)
  308 #define MC_AutoVLANuntagging            (1U << 13)
  309 #define MC_CollisionDetect              (1U << 16)
  310 #define MC_CarrierSense                 (1U << 17)
  311 #define MC_StatisticsEnable             (1U << 21)
  312 #define MC_StatisticsDisable            (1U << 22)
  313 #define MC_StatisticsEnabled            (1U << 23)
  314 #define MC_TxEnable                     (1U << 24)
  315 #define MC_TxDisable                    (1U << 25)
  316 #define MC_TxEnabled                    (1U << 26)
  317 #define MC_RxEnable                     (1U << 27)
  318 #define MC_RxDisable                    (1U << 28)
  319 #define MC_RxEnabled                    (1U << 29)
  320 #define MC_Paused                       (1U << 30)
  322 #define STGE_VLANTag                    0x70
  324 #define STGE_PhyCtrl                    0x76    /* 8-bit */
  325 #define PC_MgmtClk                      (1U << 0)
  326 #define PC_MgmtData                     (1U << 1)
  327 #define PC_MgmtDir                      (1U << 2)       /* MAC->PHY */
  328 #define PC_PhyDuplexPolarity            (1U << 3)
  329 #define PC_PhyDuplexStatus              (1U << 4)
  330 #define PC_PhyLnkPolarity               (1U << 5)
  331 #define PC_LinkSpeed(x)                 (((x) >> 6) & 3)
  332 #define PC_LinkSpeed_Down               0
  333 #define PC_LinkSpeed_10                 1
  334 #define PC_LinkSpeed_100                2
  335 #define PC_LinkSpeed_1000               3
  337 #define STGE_StationAddress0            0x78    /* 16-bit */
  339 #define STGE_StationAddress1            0x7a    /* 16-bit */
  341 #define STGE_StationAddress2            0x7c    /* 16-bit */
  343 #define STGE_VLANHashTable              0x7e    /* 16-bit */
  345 #define STGE_VLANId                     0x80
  347 #define STGE_MaxFrameSize               0x86
  349 #define STGE_ReceiveMode                0x88    /* 16-bit */
  350 #define RM_ReceiveUnicast               (1U << 0)
  351 #define RM_ReceiveMulticast             (1U << 1)
  352 #define RM_ReceiveBroadcast             (1U << 2)
  353 #define RM_ReceiveAllFrames             (1U << 3)
  354 #define RM_ReceiveMulticastHash         (1U << 4)
  355 #define RM_ReceiveIPMulticast           (1U << 5)
  356 #define RM_ReceiveVLANMatch             (1U << 8)
  357 #define RM_ReceiveVLANHash              (1U << 9)
  359 #define STGE_HashTable0                 0x8c
  361 #define STGE_HashTable1                 0x90
  363 #define STGE_RMONStatisticsMask         0x98    /* set to disable */
  365 #define STGE_StatisticsMask             0x9c    /* set to disable */
  367 #define STGE_RxJumboFrames              0xbc    /* 16-bit */
  369 #define STGE_TCPCheckSumErrors          0xc0    /* 16-bit */
  371 #define STGE_IPCheckSumErrors           0xc2    /* 16-bit */
  373 #define STGE_UDPCheckSumErrors          0xc4    /* 16-bit */
  375 #define STGE_TxJumboFrames              0xf4    /* 16-bit */
  377 /*
  378  * TC9021 statistics.  Available memory and I/O mapped.
  379  */
  381 #define STGE_OctetRcvOk                 0xa8
  383 #define STGE_McstOctetRcvdOk            0xac
  385 #define STGE_BcstOctetRcvdOk            0xb0
  387 #define STGE_FramesRcvdOk               0xb4
  389 #define STGE_McstFramesRcvdOk           0xb8
  391 #define STGE_BcstFramesRcvdOk           0xbe    /* 16-bit */
  393 #define STGE_MacControlFramesRcvd       0xc6    /* 16-bit */
  395 #define STGE_FrameTooLongErrors         0xc8    /* 16-bit */
  397 #define STGE_InRangeLengthErrors        0xca    /* 16-bit */
  399 #define STGE_FramesCheckSeqErrors       0xcc    /* 16-bit */
  401 #define STGE_FramesLostRxErrors         0xce    /* 16-bit */
  403 #define STGE_OctetXmtdOk                0xd0
  405 #define STGE_McstOctetXmtdOk            0xd4
  407 #define STGE_BcstOctetXmtdOk            0xd8
  409 #define STGE_FramesXmtdOk               0xdc
  411 #define STGE_McstFramesXmtdOk           0xe0
  413 #define STGE_FramesWDeferredXmt         0xe4
  415 #define STGE_LateCollisions             0xe8
  417 #define STGE_MultiColFrames             0xec
  419 #define STGE_SingleColFrames            0xf0
  421 #define STGE_BcstFramesXmtdOk           0xf6    /* 16-bit */
  423 #define STGE_CarrierSenseErrors         0xf8    /* 16-bit */
  425 #define STGE_MacControlFramesXmtd       0xfa    /* 16-bit */
  427 #define STGE_FramesAbortXSColls         0xfc    /* 16-bit */
  429 #define STGE_FramesWEXDeferal           0xfe    /* 16-bit */
  431 /*
  432  * RMON-compatible statistics.  Only accessible if memory-mapped.
  433  */
  435 #define STGE_EtherStatsCollisions                       0x100
  437 #define STGE_EtherStatsOctetsTransmit                   0x104
  439 #define STGE_EtherStatsPktsTransmit                     0x108
  441 #define STGE_EtherStatsPkts64OctetsTransmit             0x10c
  443 #define STGE_EtherStatsPkts64to127OctetsTransmit        0x110
  445 #define STGE_EtherStatsPkts128to255OctetsTransmit       0x114
  447 #define STGE_EtherStatsPkts256to511OctetsTransmit       0x118
  449 #define STGE_EtherStatsPkts512to1023OctetsTransmit      0x11c
  451 #define STGE_EtherStatsPkts1024to1518OctetsTransmit     0x120
  453 #define STGE_EtherStatsCRCAlignErrors                   0x124
  455 #define STGE_EtherStatsUndersizePkts                    0x128
  457 #define STGE_EtherStatsFragments                        0x12c
  459 #define STGE_EtherStatsJabbers                          0x130
  461 #define STGE_EtherStatsOctets                           0x134
  463 #define STGE_EtherStatsPkts                             0x138
  465 #define STGE_EtherStatsPkts64Octets                     0x13c
  467 #define STGE_EtherStatsPkts65to127Octets                0x140
  469 #define STGE_EtherStatsPkts128to255Octets               0x144
  471 #define STGE_EtherStatsPkts256to511Octets               0x148
  473 #define STGE_EtherStatsPkts512to1023Octets              0x14c
  475 #define STGE_EtherStatsPkts1024to1518Octets             0x150
  477 /*
  478  * Transmit descriptor list size.
  479  */
  480 #define STGE_NTXDESC            256
  481 #define STGE_NTXDESC_MASK       (STGE_NTXDESC - 1)
  482 #define STGE_NEXTTX(x)          (((x) + 1) & STGE_NTXDESC_MASK)
  484 /*
  485  * Receive descriptor list size.
  486  */
  487 #define STGE_NRXDESC            256
  488 #define STGE_NRXDESC_MASK       (STGE_NRXDESC - 1)
  489 #define STGE_NEXTRX(x)          (((x) + 1) & STGE_NRXDESC_MASK)
  491 /*
  492  * Only interrupt every N frames.  Must be a power-of-two.
  493  */   
  494 #define STGE_TXINTR_SPACING     16
  495 #define STGE_TXINTR_SPACING_MASK (STGE_TXINTR_SPACING - 1)
  497 #define STGE_JUMBO_FRAMELEN     9022
  498 #define STGE_JUMBO_MTU \
  499         (STGE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
  501 /*
  502  * Control structures are DMA'd to the TC9021 chip.  We allocate them in
  503  * a single clump that maps to a single DMA segment to make several things
  504  * easier.
  505  */
  506 struct stge_control_data {
  507         /*
  508          * The transmit descriptors.
  509          */
  510         struct stge_tfd scd_txdescs[STGE_NTXDESC];
  512         /*
  513          * The receive descriptors.
  514          */
  515         struct stge_rfd scd_rxdescs[STGE_NRXDESC];
  516 };
  518 #define STGE_CDOFF(x)   offsetof(struct stge_control_data, x)
  519 #define STGE_CDTXOFF(x) STGE_CDOFF(scd_txdescs[(x)])
  520 #define STGE_CDRXOFF(x) STGE_CDOFF(scd_rxdescs[(x)])
  522 /*
  523  * Software state for transmit and receive jobs.
  524  */
  525 struct stge_descsoft {
  526         struct mbuf *ds_mbuf;           /* head of our mbuf chain */
bus_dmamap_t ds_dmamap;         /* our DMA map */
  528 };
  530 /*
  531  * Software state per device.
  532  */
  533 struct stge_softc {
  534         struct device sc_dev;           /* generic device information */
bus_space_tag_t sc_st;          /* bus space tag */
bus_space_handle_t sc_sh;       /* bus space handle */ 
bus_dma_tag_t sc_dmat;          /* bus DMA tag */ 
  538         struct arpcom sc_arpcom;        /* ethernet common data */
  539         void *sc_sdhook;                /* shutdown hook */
  540         int sc_rev;                     /* silicon revision */ 
  541         int stge_if_flags;
  542         void *sc_ih;                    /* interrupt cookie */
  544         struct mii_data sc_mii;         /* MII/media information */
  546         struct timeout sc_timeout;      /* tick timeout */
bus_dmamap_t sc_cddmamap;       /* control data DMA map */
  549 #define sc_cddma        sc_cddmamap->dm_segs[0].ds_addr
  551         /*
  552          * Software state for transmit and receive descriptors.
  553         */
  554         struct stge_descsoft sc_txsoft[STGE_NTXDESC];
  555         struct stge_descsoft sc_rxsoft[STGE_NRXDESC];
  557         /*
  558          * Control data structures.
  559         */
  560         struct stge_control_data *sc_control_data;
  561 #define sc_txdescs      sc_control_data->scd_txdescs
  562 #define sc_rxdescs      sc_control_data->scd_rxdescs
  564         int     sc_txpending;           /* number of Tx requests pending */
  565         int     sc_txdirty;             /* first dirty Tx descriptor */
  566         int     sc_txlast;              /* last used Tx descriptor */
  568         int     sc_rxptr;               /* next ready Rx descriptor/descsoft */
  569         int     sc_rxdiscard;
  570         int     sc_rxlen;
  571         struct mbuf *sc_rxhead;
  572         struct mbuf *sc_rxtail;
  573         struct mbuf **sc_rxtailp;
  575         int     sc_txthresh;            /* Tx threshold */
uint32_t sc_usefiber:1;         /* if we're fiber */
uint32_t sc_stge1023:1;         /* are we a 1023 */
uint32_t sc_DMACtrl;            /* prototype DMACtrl register */
uint32_t sc_MACCtrl;            /* prototype MacCtrl register */
uint16_t sc_IntEnable;          /* prototype IntEnable register */
uint16_t sc_ReceiveMode;        /* prototype ReceiveMode register */
uint8_t sc_PhyCtrl;             /* prototype PhyCtrl register */
  583 };
  585 #define STGE_RXCHAIN_RESET(sc)                                          \
  586 do {                                                                    \
  587         (sc)->sc_rxtailp = &(sc)->sc_rxhead;                            \
  588         *(sc)->sc_rxtailp = NULL;                                       \
  589         (sc)->sc_rxlen = 0;                                             \
  590 } while (/*CONSTCOND*/0)
  592 #define STGE_RXCHAIN_LINK(sc, m)                                        \
  593 do {                                                                    \
  594         *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m);                      \
  595         (sc)->sc_rxtailp = &(m)->m_next;                                \
  596 } while (/*CONSTCOND*/0)
  598 #define STGE_CDTXADDR(sc, x)    ((sc)->sc_cddma + STGE_CDTXOFF((x)))
  599 #define STGE_CDRXADDR(sc, x)    ((sc)->sc_cddma + STGE_CDRXOFF((x)))
  601 #define STGE_CDTXSYNC(sc, x, ops)                                       \
bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,               \
STGE_CDTXOFF((x)), sizeof(struct stge_tfd), (ops))
  605 #define STGE_CDRXSYNC(sc, x, ops)                                       \
bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,               \
STGE_CDRXOFF((x)), sizeof(struct stge_rfd), (ops))
  609 #define STGE_INIT_RXDESC(sc, x)                                         \
  610 do {                                                                    \
  611         struct stge_descsoft *__ds = &(sc)->sc_rxsoft[(x)];             \
  612         struct stge_rfd *__rfd = &(sc)->sc_rxdescs[(x)];                \
  613                                                                         \
  614         /*                                                              \
  615          * Note: We scoot the packet forward 2 bytes in the buffer      \
  616          * so that the payload after the Ethernet header is aligned     \
  617          * to a 4-byte boundary.                                        \
  618          */                                                             \
__rfd->rfd_frag.frag_word0 =                                    \
htole64(FRAG_ADDR(__ds->ds_dmamap->dm_segs[0].ds_addr + 2) |\
FRAG_LEN(MCLBYTES - 2));                                    \
__rfd->rfd_next =                                               \
htole64((uint64_t)STGE_CDRXADDR((sc), STGE_NEXTRX((x))));   \
__rfd->rfd_status = 0;                                          \
STGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
  626 } while (/*CONSTCOND*/0)
  628 #define STGE_TIMEOUT    1000
  630 #endif /* _DEV_PCI_IF_STGEREG_H_ */