CSR_WRITE_4 1459 dev/ic/acx.c CSR_WRITE_4(sc, ACXREG_EEPROM_CONF, 0); CSR_WRITE_4 1460 dev/ic/acx.c CSR_WRITE_4(sc, ACXREG_EEPROM_ADDR, offset); CSR_WRITE_4 1461 dev/ic/acx.c CSR_WRITE_4(sc, ACXREG_EEPROM_CTRL, ACXRV_EEPROM_READ); CSR_WRITE_4 1487 dev/ic/acx.c CSR_WRITE_4(sc, ACXREG_PHY_ADDR, reg); CSR_WRITE_4 1488 dev/ic/acx.c CSR_WRITE_4(sc, ACXREG_PHY_CTRL, ACXRV_PHY_READ); CSR_WRITE_4 1511 dev/ic/acx.c CSR_WRITE_4(sc, ACXREG_PHY_DATA, val); CSR_WRITE_4 1512 dev/ic/acx.c CSR_WRITE_4(sc, ACXREG_PHY_ADDR, reg); CSR_WRITE_4 1513 dev/ic/acx.c CSR_WRITE_4(sc, ACXREG_PHY_CTRL, ACXRV_PHY_WRITE); CSR_WRITE_4 1665 dev/ic/acx.c CSR_WRITE_4(sc, ACXREG_FWMEM_START, ACXRV_FWMEM_START_OP); CSR_WRITE_4 1667 dev/ic/acx.c CSR_WRITE_4(sc, ACXREG_FWMEM_CTRL, 0); CSR_WRITE_4 1669 dev/ic/acx.c CSR_WRITE_4(sc, ACXREG_FWMEM_CTRL, ACXRV_FWMEM_ADDR_AUTOINC); CSR_WRITE_4 1670 dev/ic/acx.c CSR_WRITE_4(sc, ACXREG_FWMEM_ADDR, offset); CSR_WRITE_4 1675 dev/ic/acx.c CSR_WRITE_4(sc, ACXREG_FWMEM_ADDR, offset + (i * 4)); CSR_WRITE_4 1677 dev/ic/acx.c CSR_WRITE_4(sc, ACXREG_FWMEM_DATA, betoh32(fw[i])); CSR_WRITE_4 1681 dev/ic/acx.c CSR_WRITE_4(sc, ACXREG_FWMEM_START, ACXRV_FWMEM_START_OP); CSR_WRITE_4 1683 dev/ic/acx.c CSR_WRITE_4(sc, ACXREG_FWMEM_CTRL, 0); CSR_WRITE_4 1685 dev/ic/acx.c CSR_WRITE_4(sc, ACXREG_FWMEM_CTRL, ACXRV_FWMEM_ADDR_AUTOINC); CSR_WRITE_4 1686 dev/ic/acx.c CSR_WRITE_4(sc, ACXREG_FWMEM_ADDR, offset); CSR_WRITE_4 1693 dev/ic/acx.c CSR_WRITE_4(sc, ACXREG_FWMEM_ADDR, offset + (i * 4)); CSR_WRITE_4 198 dev/ic/dc.c CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) CSR_WRITE_4 201 dev/ic/dc.c CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) CSR_WRITE_4 226 dev/ic/dc.c CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); CSR_WRITE_4 268 dev/ic/dc.c CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); CSR_WRITE_4 287 dev/ic/dc.c CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); CSR_WRITE_4 307 dev/ic/dc.c CSR_WRITE_4(sc, DC_SIO, 0x00000000); CSR_WRITE_4 365 dev/ic/dc.c CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); CSR_WRITE_4 388 dev/ic/dc.c CSR_WRITE_4(sc, DC_ROM, addr | 0x160); CSR_WRITE_4 391 dev/ic/dc.c CSR_WRITE_4(sc, DC_ROM, addr | 0x160); CSR_WRITE_4 413 dev/ic/dc.c CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); CSR_WRITE_4 485 dev/ic/dc.c CSR_WRITE_4(sc, DC_SIO, CSR_WRITE_4 488 dev/ic/dc.c CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); CSR_WRITE_4 501 dev/ic/dc.c CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); CSR_WRITE_4 519 dev/ic/dc.c CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); CSR_WRITE_4 709 dev/ic/dc.c CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | CSR_WRITE_4 765 dev/ic/dc.c CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); CSR_WRITE_4 769 dev/ic/dc.c CSR_WRITE_4(sc, DC_NETCFG, phy_reg); CSR_WRITE_4 791 dev/ic/dc.c CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | CSR_WRITE_4 830 dev/ic/dc.c CSR_WRITE_4(sc, phy_reg, data); CSR_WRITE_4 840 dev/ic/dc.c CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); CSR_WRITE_4 844 dev/ic/dc.c CSR_WRITE_4(sc, DC_NETCFG, phy_reg); CSR_WRITE_4 999 dev/ic/dc.c CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); CSR_WRITE_4 1026 dev/ic/dc.c CSR_WRITE_4(sc, DC_AL_PAR0, ac->ac_enaddr[3] << 24 | CSR_WRITE_4 1028 dev/ic/dc.c CSR_WRITE_4(sc, DC_AL_PAR1, ac->ac_enaddr[5] << 8 | ac->ac_enaddr[4]); CSR_WRITE_4 1043 dev/ic/dc.c CSR_WRITE_4(sc, DC_AL_MAR0, 0); CSR_WRITE_4 1044 dev/ic/dc.c CSR_WRITE_4(sc, DC_AL_MAR1, 0); CSR_WRITE_4 1072 dev/ic/dc.c CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); CSR_WRITE_4 1073 dev/ic/dc.c CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); CSR_WRITE_4 1090 dev/ic/dc.c CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); CSR_WRITE_4 1091 dev/ic/dc.c CSR_WRITE_4(sc, DC_AX_FILTDATA, CSR_WRITE_4 1093 dev/ic/dc.c CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); CSR_WRITE_4 1094 dev/ic/dc.c CSR_WRITE_4(sc, DC_AX_FILTDATA, CSR_WRITE_4 1118 dev/ic/dc.c CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); CSR_WRITE_4 1119 dev/ic/dc.c CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); CSR_WRITE_4 1120 dev/ic/dc.c CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); CSR_WRITE_4 1121 dev/ic/dc.c CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); CSR_WRITE_4 1141 dev/ic/dc.c CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); CSR_WRITE_4 1142 dev/ic/dc.c CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); CSR_WRITE_4 1143 dev/ic/dc.c CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); CSR_WRITE_4 1144 dev/ic/dc.c CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); CSR_WRITE_4 1210 dev/ic/dc.c CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); CSR_WRITE_4 1283 dev/ic/dc.c CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); CSR_WRITE_4 1324 dev/ic/dc.c CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); CSR_WRITE_4 1419 dev/ic/dc.c CSR_WRITE_4(sc, DC_IMR, 0x00000000); CSR_WRITE_4 1420 dev/ic/dc.c CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); CSR_WRITE_4 1421 dev/ic/dc.c CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); CSR_WRITE_4 1431 dev/ic/dc.c CSR_WRITE_4(sc, DC_10BTCTRL, 0); CSR_WRITE_4 1432 dev/ic/dc.c CSR_WRITE_4(sc, DC_WATCHDOG, 0); CSR_WRITE_4 1462 dev/ic/dc.c CSR_WRITE_4(sc, DC_WATCHDOG, reg); CSR_WRITE_4 1467 dev/ic/dc.c CSR_WRITE_4(sc, DC_WATCHDOG, reg); CSR_WRITE_4 1798 dev/ic/dc.c CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | CSR_WRITE_4 1801 dev/ic/dc.c CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | CSR_WRITE_4 2533 dev/ic/dc.c CSR_WRITE_4(sc, DC_IMR, 0x00000000); CSR_WRITE_4 2540 dev/ic/dc.c CSR_WRITE_4(sc, DC_ISR, status); CSR_WRITE_4 2559 dev/ic/dc.c CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); CSR_WRITE_4 2584 dev/ic/dc.c CSR_WRITE_4(sc, DC_IMR, DC_INTRS); CSR_WRITE_4 2783 dev/ic/dc.c CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); CSR_WRITE_4 2814 dev/ic/dc.c CSR_WRITE_4(sc, DC_BUSCTL, 0); CSR_WRITE_4 2816 dev/ic/dc.c CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); CSR_WRITE_4 2876 dev/ic/dc.c CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | CSR_WRITE_4 2879 dev/ic/dc.c CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | CSR_WRITE_4 2911 dev/ic/dc.c CSR_WRITE_4(sc, DC_RXADDR, sc->sc_listmap->dm_segs[0].ds_addr + CSR_WRITE_4 2913 dev/ic/dc.c CSR_WRITE_4(sc, DC_TXADDR, sc->sc_listmap->dm_segs[0].ds_addr + CSR_WRITE_4 2919 dev/ic/dc.c CSR_WRITE_4(sc, DC_IMR, DC_INTRS); CSR_WRITE_4 2920 dev/ic/dc.c CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); CSR_WRITE_4 2931 dev/ic/dc.c CSR_WRITE_4(sc, DC_WATCHDOG, CSR_WRITE_4 2933 dev/ic/dc.c CSR_WRITE_4(sc, DC_WATCHDOG, 0); CSR_WRITE_4 2946 dev/ic/dc.c CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); CSR_WRITE_4 3158 dev/ic/dc.c CSR_WRITE_4(sc, DC_IMR, 0x00000000); CSR_WRITE_4 3159 dev/ic/dc.c CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); CSR_WRITE_4 3160 dev/ic/dc.c CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); CSR_WRITE_4 349 dev/ic/fxp.c CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); CSR_WRITE_4 946 dev/ic/fxp.c CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, CSR_WRITE_4 1077 dev/ic/fxp.c CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); CSR_WRITE_4 1172 dev/ic/fxp.c CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); CSR_WRITE_4 1176 dev/ic/fxp.c CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); CSR_WRITE_4 1203 dev/ic/fxp.c CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, CSR_WRITE_4 1302 dev/ic/fxp.c CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->tx_cb_map->dm_segs->ds_addr + CSR_WRITE_4 1326 dev/ic/fxp.c CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->tx_cb_map->dm_segs->ds_addr + CSR_WRITE_4 1363 dev/ic/fxp.c CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->tx_cb_map->dm_segs->ds_addr + CSR_WRITE_4 1569 dev/ic/fxp.c CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, CSR_WRITE_4 1594 dev/ic/fxp.c CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, CSR_WRITE_4 1748 dev/ic/fxp.c CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->tx_cb_map->dm_segs->ds_addr + CSR_WRITE_4 1854 dev/ic/fxp.c CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->tx_cb_map->dm_segs->ds_addr CSR_WRITE_4 230 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_MIIMGT, miir); CSR_WRITE_4 232 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_MIIMGT, miir); CSR_WRITE_4 241 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_MIIMGT, miir); CSR_WRITE_4 243 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_MIIMGT, miir); CSR_WRITE_4 267 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_MIIMGT, miir); CSR_WRITE_4 272 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_MIIMGT, miir); CSR_WRITE_4 276 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_MIIMGT, miir); CSR_WRITE_4 299 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_MIIMGT, miir); CSR_WRITE_4 301 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_MIIMGT, miir); CSR_WRITE_4 305 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_MIIMGT, miir); CSR_WRITE_4 330 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_TCRRCR, rxfilt); CSR_WRITE_4 331 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_MAR0, 0xffffffff); CSR_WRITE_4 332 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_MAR4, 0xffffffff); CSR_WRITE_4 337 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_MAR0, 0); CSR_WRITE_4 338 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_MAR4, 0); CSR_WRITE_4 355 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_MAR0, hash[0]); CSR_WRITE_4 356 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_MAR4, hash[1]); CSR_WRITE_4 357 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_TCRRCR, rxfilt); CSR_WRITE_4 555 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_BCR, BCR_SWR); CSR_WRITE_4 665 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_BCR, BCR_PBL8); CSR_WRITE_4 666 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_TCRRCR, TCR_TFTSF | RCR_RBLEN | RCR_RPBL512); CSR_WRITE_4 692 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_RXLBA, sc->sc_listmap->dm_segs[0].ds_addr + CSR_WRITE_4 694 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_TXLBA, sc->sc_listmap->dm_segs[0].ds_addr + CSR_WRITE_4 700 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_IMR, IMR_INTRS); CSR_WRITE_4 701 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_ISR, 0xffffffff); CSR_WRITE_4 705 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_RXPDR, 0xffffffff); CSR_WRITE_4 757 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_TXPDR, 0xffffffff); CSR_WRITE_4 776 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_IMR, 0); CSR_WRITE_4 777 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_TXLBA, 0); CSR_WRITE_4 778 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_RXLBA, 0); CSR_WRITE_4 855 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_IMR, 0); CSR_WRITE_4 860 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_ISR, status); CSR_WRITE_4 888 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_IMR, IMR_INTRS); CSR_WRITE_4 1097 dev/ic/mtd8xx.c CSR_WRITE_4(MTD_TXPDR, 0xffffffff); CSR_WRITE_4 212 dev/ic/mtd8xxreg.h #define CSR_SETBIT(reg, val) CSR_WRITE_4(reg, CSR_READ_4(reg) | (val)) CSR_WRITE_4 213 dev/ic/mtd8xxreg.h #define CSR_CLRBIT(reg, val) CSR_WRITE_4(reg, CSR_READ_4(reg) & ~(val)) CSR_WRITE_4 339 dev/ic/re.c CSR_WRITE_4(sc, RL_PHYAR, reg << 16); CSR_WRITE_4 364 dev/ic/re.c CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | CSR_WRITE_4 524 dev/ic/re.c CSR_WRITE_4(sc, RL_RXCFG, rxfilt); CSR_WRITE_4 525 dev/ic/re.c CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); CSR_WRITE_4 526 dev/ic/re.c CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); CSR_WRITE_4 531 dev/ic/re.c CSR_WRITE_4(sc, RL_MAR0, 0); CSR_WRITE_4 532 dev/ic/re.c CSR_WRITE_4(sc, RL_MAR4, 0); CSR_WRITE_4 559 dev/ic/re.c CSR_WRITE_4(sc, RL_RXCFG, rxfilt); CSR_WRITE_4 571 dev/ic/re.c CSR_WRITE_4(sc, RL_MAR0, swap32(hashes[1])); CSR_WRITE_4 572 dev/ic/re.c CSR_WRITE_4(sc, RL_MAR4, swap32(hashes[0])); CSR_WRITE_4 574 dev/ic/re.c CSR_WRITE_4(sc, RL_MAR0, hashes[0]); CSR_WRITE_4 575 dev/ic/re.c CSR_WRITE_4(sc, RL_MAR4, hashes[1]); CSR_WRITE_4 592 dev/ic/re.c CSR_WRITE_4(sc, RL_RXCFG, rxcfg); CSR_WRITE_4 1437 dev/ic/re.c CSR_WRITE_4(sc, RL_TIMERCNT, 1); CSR_WRITE_4 1766 dev/ic/re.c CSR_WRITE_4(sc, RL_TIMERCNT, 1); CSR_WRITE_4 1782 dev/ic/re.c CSR_WRITE_4(sc, RL_TIMERCNT, 1); CSR_WRITE_4 1823 dev/ic/re.c CSR_WRITE_4(sc, RL_IDR4, CSR_WRITE_4 1825 dev/ic/re.c CSR_WRITE_4(sc, RL_IDR0, CSR_WRITE_4 1838 dev/ic/re.c CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, CSR_WRITE_4 1840 dev/ic/re.c CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, CSR_WRITE_4 1843 dev/ic/re.c CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, CSR_WRITE_4 1845 dev/ic/re.c CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, CSR_WRITE_4 1858 dev/ic/re.c CSR_WRITE_4(sc, RL_TXCFG, CSR_WRITE_4 1861 dev/ic/re.c CSR_WRITE_4(sc, RL_TXCFG, CSR_WRITE_4 1864 dev/ic/re.c CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); CSR_WRITE_4 1868 dev/ic/re.c CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); CSR_WRITE_4 1882 dev/ic/re.c CSR_WRITE_4(sc, RL_RXCFG, rxcfg); CSR_WRITE_4 1902 dev/ic/re.c CSR_WRITE_4(sc, RL_MISSEDPKT, 0); CSR_WRITE_4 1916 dev/ic/re.c CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); CSR_WRITE_4 1918 dev/ic/re.c CSR_WRITE_4(sc, RL_TIMERINT, 0x400); CSR_WRITE_4 482 dev/ic/rtl81x9.c CSR_WRITE_4(sc, RL_RXCFG, rxfilt); CSR_WRITE_4 483 dev/ic/rtl81x9.c CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); CSR_WRITE_4 484 dev/ic/rtl81x9.c CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); CSR_WRITE_4 489 dev/ic/rtl81x9.c CSR_WRITE_4(sc, RL_MAR0, 0); CSR_WRITE_4 490 dev/ic/rtl81x9.c CSR_WRITE_4(sc, RL_MAR4, 0); CSR_WRITE_4 514 dev/ic/rtl81x9.c CSR_WRITE_4(sc, RL_RXCFG, rxfilt); CSR_WRITE_4 515 dev/ic/rtl81x9.c CSR_WRITE_4(sc, RL_MAR0, hashes[0]); CSR_WRITE_4 516 dev/ic/rtl81x9.c CSR_WRITE_4(sc, RL_MAR4, hashes[1]); CSR_WRITE_4 550 dev/ic/rtl81x9.c CSR_WRITE_4(sc, CSR_WRITE_4 780 dev/ic/rtl81x9.c CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); CSR_WRITE_4 939 dev/ic/rtl81x9.c CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), CSR_WRITE_4 941 dev/ic/rtl81x9.c CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), CSR_WRITE_4 992 dev/ic/rtl81x9.c CSR_WRITE_4(sc, RL_RXADDR, sc->rl_cdata.rl_rx_buf_pa); CSR_WRITE_4 1005 dev/ic/rtl81x9.c CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); CSR_WRITE_4 1006 dev/ic/rtl81x9.c CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); CSR_WRITE_4 1017 dev/ic/rtl81x9.c CSR_WRITE_4(sc, RL_RXCFG, rxcfg); CSR_WRITE_4 1026 dev/ic/rtl81x9.c CSR_WRITE_4(sc, RL_RXCFG, rxcfg); CSR_WRITE_4 1042 dev/ic/rtl81x9.c CSR_WRITE_4(sc, RL_MISSEDPKT, 0); CSR_WRITE_4 1211 dev/ic/rtl81x9.c CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(u_int32_t)), CSR_WRITE_4 801 dev/ic/rtl81x9reg.h CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) CSR_WRITE_4 804 dev/ic/rtl81x9reg.h CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) CSR_WRITE_4 706 dev/ic/xl.c CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); CSR_WRITE_4 792 dev/ic/xl.c CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); CSR_WRITE_4 1302 dev/ic/xl.c CSR_WRITE_4(sc, XL_UPLIST_PTR, CSR_WRITE_4 1369 dev/ic/xl.c CSR_WRITE_4(sc, XL_DOWNLIST_PTR, CSR_WRITE_4 1447 dev/ic/xl.c CSR_WRITE_4(sc, XL_DOWNLIST_PTR, CSR_WRITE_4 1453 dev/ic/xl.c CSR_WRITE_4(sc, XL_DOWNLIST_PTR, CSR_WRITE_4 1819 dev/ic/xl.c CSR_WRITE_4(sc, XL_DOWNLIST_PTR, CSR_WRITE_4 2061 dev/ic/xl.c CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->sc_listmap->dm_segs[0].ds_addr + CSR_WRITE_4 2072 dev/ic/xl.c CSR_WRITE_4(sc, XL_DOWNLIST_PTR, CSR_WRITE_4 72 dev/mii/dcphy.c CSR_WRITE_4(sc, reg, \ CSR_WRITE_4 76 dev/mii/dcphy.c CSR_WRITE_4(sc, reg, \ CSR_WRITE_4 144 dev/mii/dcphy.c CSR_WRITE_4(dc_sc, DC_10BTSTAT, 0); CSR_WRITE_4 145 dev/mii/dcphy.c CSR_WRITE_4(dc_sc, DC_10BTCTRL, 0); CSR_WRITE_4 235 dev/mii/dcphy.c CSR_WRITE_4(dc_sc, DC_NETCFG, mode); CSR_WRITE_4 252 dev/mii/dcphy.c CSR_WRITE_4(dc_sc, DC_NETCFG, mode); CSR_WRITE_4 404 dev/mii/dcphy.c CSR_WRITE_4(sc, DC_10BTCTRL, 0x3FFFF); CSR_WRITE_4 406 dev/mii/dcphy.c CSR_WRITE_4(sc, DC_10BTCTRL, 0xFFFF); CSR_WRITE_4 436 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_EE_ADDR, CSR_WRITE_4 441 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); CSR_WRITE_4 508 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| CSR_WRITE_4 554 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| CSR_WRITE_4 909 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); CSR_WRITE_4 957 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); CSR_WRITE_4 959 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); CSR_WRITE_4 1029 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); CSR_WRITE_4 1031 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); CSR_WRITE_4 1034 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); CSR_WRITE_4 1036 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); CSR_WRITE_4 1094 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_RX_MODE, rxmode); CSR_WRITE_4 1112 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MAC_MODE, 0); CSR_WRITE_4 1206 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS| CSR_WRITE_4 1210 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS| CSR_WRITE_4 1233 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); CSR_WRITE_4 1251 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); CSR_WRITE_4 1255 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, CSR_WRITE_4 1259 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); CSR_WRITE_4 1261 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); CSR_WRITE_4 1264 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, CSR_WRITE_4 1266 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); CSR_WRITE_4 1272 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); CSR_WRITE_4 1273 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); CSR_WRITE_4 1274 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); CSR_WRITE_4 1276 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); CSR_WRITE_4 1277 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); CSR_WRITE_4 1278 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); CSR_WRITE_4 1282 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); CSR_WRITE_4 1283 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); CSR_WRITE_4 1286 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_BMAN_MODE, CSR_WRITE_4 1303 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); CSR_WRITE_4 1304 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); CSR_WRITE_4 1328 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); CSR_WRITE_4 1329 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); CSR_WRITE_4 1330 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); CSR_WRITE_4 1331 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); CSR_WRITE_4 1349 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, CSR_WRITE_4 1351 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, CSR_WRITE_4 1353 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, CSR_WRITE_4 1355 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, CSR_WRITE_4 1362 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, CSR_WRITE_4 1389 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, i); CSR_WRITE_4 1390 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT / 8); CSR_WRITE_4 1425 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + CSR_WRITE_4 1431 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); CSR_WRITE_4 1432 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); CSR_WRITE_4 1433 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); CSR_WRITE_4 1450 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, CSR_WRITE_4 1457 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); CSR_WRITE_4 1463 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); CSR_WRITE_4 1469 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); CSR_WRITE_4 1472 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); CSR_WRITE_4 1473 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); CSR_WRITE_4 1476 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); CSR_WRITE_4 1492 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); CSR_WRITE_4 1493 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); CSR_WRITE_4 1494 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); CSR_WRITE_4 1495 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); CSR_WRITE_4 1497 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); CSR_WRITE_4 1498 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); CSR_WRITE_4 1500 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); CSR_WRITE_4 1501 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); CSR_WRITE_4 1505 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0); CSR_WRITE_4 1506 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, CSR_WRITE_4 1509 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); CSR_WRITE_4 1510 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); CSR_WRITE_4 1511 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); CSR_WRITE_4 1516 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); CSR_WRITE_4 1517 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); CSR_WRITE_4 1523 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); CSR_WRITE_4 1526 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_RBDC_MODE, CSR_WRITE_4 1530 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); CSR_WRITE_4 1534 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); CSR_WRITE_4 1537 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| CSR_WRITE_4 1544 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); CSR_WRITE_4 1556 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); CSR_WRITE_4 1566 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_WDMA_MODE, val); CSR_WRITE_4 1578 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_RDMA_MODE, dma_read_modebits); CSR_WRITE_4 1582 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); CSR_WRITE_4 1585 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); CSR_WRITE_4 1588 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); CSR_WRITE_4 1592 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); CSR_WRITE_4 1595 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); CSR_WRITE_4 1598 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); CSR_WRITE_4 1601 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); CSR_WRITE_4 1604 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); CSR_WRITE_4 1607 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); CSR_WRITE_4 1609 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); CSR_WRITE_4 1610 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, CSR_WRITE_4 1614 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| CSR_WRITE_4 1620 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); CSR_WRITE_4 1625 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, CSR_WRITE_4 1636 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| CSR_WRITE_4 2110 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); CSR_WRITE_4 2117 dev/pci/if_bge.c CSR_WRITE_4(sc, 0x7e2c, 0x20); CSR_WRITE_4 2124 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29)); CSR_WRITE_4 2171 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); CSR_WRITE_4 2173 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); CSR_WRITE_4 2221 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); CSR_WRITE_4 2223 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MAC_MODE, 0); CSR_WRITE_4 2236 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); CSR_WRITE_4 2245 dev/pci/if_bge.c CSR_WRITE_4(sc, 0x7c00, v | (1<<25)); CSR_WRITE_4 2400 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); CSR_WRITE_4 2402 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); CSR_WRITE_4 2404 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); CSR_WRITE_4 2504 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); CSR_WRITE_4 2524 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); CSR_WRITE_4 2890 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); CSR_WRITE_4 2892 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); CSR_WRITE_4 2933 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_RX_MTU, CSR_WRITE_4 2936 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_RX_MTU, CSR_WRITE_4 2941 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); CSR_WRITE_4 2942 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); CSR_WRITE_4 2987 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); CSR_WRITE_4 2995 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); CSR_WRITE_4 3030 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); CSR_WRITE_4 3035 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_SGDIG_CFG, CSR_WRITE_4 3038 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); CSR_WRITE_4 3278 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); CSR_WRITE_4 3279 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); CSR_WRITE_4 3288 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); CSR_WRITE_4 3389 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, CSR_WRITE_4 3406 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); CSR_WRITE_4 3445 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| CSR_WRITE_4 1823 dev/pci/if_bgereg.h CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ CSR_WRITE_4 2246 dev/pci/if_bgereg.h CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) CSR_WRITE_4 2248 dev/pci/if_bgereg.h CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) CSR_WRITE_4 121 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); CSR_WRITE_4 128 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); CSR_WRITE_4 197 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); CSR_WRITE_4 967 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, sc->rxcur); CSR_WRITE_4 1043 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); CSR_WRITE_4 1064 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_INTR, r); CSR_WRITE_4 1067 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); CSR_WRITE_4 1111 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); CSR_WRITE_4 1290 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); CSR_WRITE_4 1475 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); CSR_WRITE_4 1477 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); CSR_WRITE_4 1487 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | CSR_WRITE_4 1501 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | CSR_WRITE_4 1513 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | CSR_WRITE_4 1518 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | CSR_WRITE_4 1530 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_RST, 0); CSR_WRITE_4 1600 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | CSR_WRITE_4 1604 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); CSR_WRITE_4 1607 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_RST, 0); CSR_WRITE_4 1608 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | CSR_WRITE_4 1618 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | CSR_WRITE_4 1904 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_TX_BD_BASE, sc->tbd_map->dm_segs[0].ds_addr); CSR_WRITE_4 1905 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_TX_BD_SIZE, IPW_NTBD); CSR_WRITE_4 1906 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_TX_READ_INDEX, 0); CSR_WRITE_4 1907 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, 0); CSR_WRITE_4 1912 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_RX_BD_BASE, sc->rbd_map->dm_segs[0].ds_addr); CSR_WRITE_4 1913 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_RX_BD_SIZE, IPW_NRBD); CSR_WRITE_4 1914 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_RX_READ_INDEX, 0); CSR_WRITE_4 1915 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, IPW_NRBD - 1); CSR_WRITE_4 1918 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_RX_STATUS_BASE, CSR_WRITE_4 1959 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); CSR_WRITE_4 1978 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); CSR_WRITE_4 1988 dev/pci/if_ipw.c CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); CSR_WRITE_4 302 dev/pci/if_ipwreg.h CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ CSR_WRITE_4 307 dev/pci/if_ipwreg.h CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ CSR_WRITE_4 312 dev/pci/if_ipwreg.h CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ CSR_WRITE_4 313 dev/pci/if_ipwreg.h CSR_WRITE_4((sc), IPW_CSR_INDIRECT_DATA, (val)); \ CSR_WRITE_4 317 dev/pci/if_ipwreg.h CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ CSR_WRITE_4 132 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_INDIRECT_ADDR, addr); CSR_WRITE_4 139 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_INDIRECT_ADDR, addr); CSR_WRITE_4 925 dev/pci/if_iwi.c CSR_WRITE_4(sc, data->reg, data->map->dm_segs[0].ds_addr); CSR_WRITE_4 1130 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_RX_WIDX, hw); CSR_WRITE_4 1174 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_INTR_MASK, 0); CSR_WRITE_4 1177 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_INTR, r); CSR_WRITE_4 1200 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_CMD_WIDX, sc->cmdq.next); CSR_WRITE_4 1221 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_INTR_MASK, IWI_INTR_MASK); CSR_WRITE_4 1250 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_CMD_WIDX, sc->cmdq.next); CSR_WRITE_4 1391 dev/pci/if_iwi.c CSR_WRITE_4(sc, txq->csr_widx, txq->cur); CSR_WRITE_4 1538 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_INTR_MASK, 0); CSR_WRITE_4 1540 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_RST, IWI_RST_STOP_MASTER); CSR_WRITE_4 1551 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_RST, CSR_READ_4(sc, IWI_CSR_RST) | CSR_WRITE_4 1565 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_CTL, CSR_READ_4(sc, IWI_CSR_CTL) | CSR_WRITE_4 1568 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_READ_INT, IWI_READ_INT_INIT_HOST); CSR_WRITE_4 1582 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_RST, CSR_READ_4(sc, IWI_CSR_RST) | CSR_WRITE_4 1587 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_CTL, CSR_READ_4(sc, IWI_CSR_CTL) | CSR_WRITE_4 1591 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_AUTOINC_ADDR, 0); CSR_WRITE_4 1593 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_AUTOINC_DATA, 0); CSR_WRITE_4 1604 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_RST, CSR_READ_4(sc, IWI_CSR_RST) | CSR_WRITE_4 1620 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_RST, CSR_READ_4(sc, IWI_CSR_RST) & CSR_WRITE_4 1725 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_AUTOINC_ADDR, 0x27000); CSR_WRITE_4 1739 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_AUTOINC_DATA, ctl); CSR_WRITE_4 1740 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_AUTOINC_DATA, src); CSR_WRITE_4 1741 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_AUTOINC_DATA, dst); CSR_WRITE_4 1742 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_AUTOINC_DATA, sum); CSR_WRITE_4 1752 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_AUTOINC_DATA, 0); CSR_WRITE_4 1754 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_RST, CSR_READ_4(sc, IWI_CSR_RST) & CSR_WRITE_4 1776 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_INTR_MASK, IWI_INTR_MASK); CSR_WRITE_4 1779 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_RST, 0); CSR_WRITE_4 1781 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_CTL, CSR_READ_4(sc, IWI_CSR_CTL) | CSR_WRITE_4 2200 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_CMD_BASE, sc->cmdq.map->dm_segs[0].ds_addr); CSR_WRITE_4 2201 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_CMD_SIZE, IWI_CMD_RING_COUNT); CSR_WRITE_4 2202 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_CMD_WIDX, sc->cmdq.cur); CSR_WRITE_4 2204 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_TX1_BASE, sc->txq[0].map->dm_segs[0].ds_addr); CSR_WRITE_4 2205 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_TX1_SIZE, IWI_TX_RING_COUNT); CSR_WRITE_4 2206 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_TX1_WIDX, sc->txq[0].cur); CSR_WRITE_4 2208 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_TX2_BASE, sc->txq[1].map->dm_segs[0].ds_addr); CSR_WRITE_4 2209 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_TX2_SIZE, IWI_TX_RING_COUNT); CSR_WRITE_4 2210 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_TX2_WIDX, sc->txq[1].cur); CSR_WRITE_4 2212 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_TX3_BASE, sc->txq[2].map->dm_segs[0].ds_addr); CSR_WRITE_4 2213 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_TX3_SIZE, IWI_TX_RING_COUNT); CSR_WRITE_4 2214 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_TX3_WIDX, sc->txq[2].cur); CSR_WRITE_4 2216 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_TX4_BASE, sc->txq[3].map->dm_segs[0].ds_addr); CSR_WRITE_4 2217 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_TX4_SIZE, IWI_TX_RING_COUNT); CSR_WRITE_4 2218 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_TX4_WIDX, sc->txq[3].cur); CSR_WRITE_4 2222 dev/pci/if_iwi.c CSR_WRITE_4(sc, data->reg, data->map->dm_segs[0].ds_addr); CSR_WRITE_4 2225 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_RX_WIDX, IWI_RX_RING_COUNT - 1); CSR_WRITE_4 2274 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_RST, IWI_RST_SW_RESET); CSR_WRITE_4 454 dev/pci/if_iwireg.h CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ CSR_WRITE_4 459 dev/pci/if_iwireg.h CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ CSR_WRITE_4 464 dev/pci/if_iwireg.h CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ CSR_WRITE_4 465 dev/pci/if_iwireg.h CSR_WRITE_4((sc), IWI_CSR_INDIRECT_DATA, (val)); \ CSR_WRITE_4 469 dev/pci/if_iwireg.h CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ CSR_WRITE_4 175 dev/pci/if_lge.c CSR_WRITE_4(sc, reg, \ CSR_WRITE_4 179 dev/pci/if_lge.c CSR_WRITE_4(sc, reg, \ CSR_WRITE_4 183 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) CSR_WRITE_4 186 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) CSR_WRITE_4 197 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| CSR_WRITE_4 251 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); CSR_WRITE_4 271 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_GMIICTL, CSR_WRITE_4 328 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); CSR_WRITE_4 332 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); CSR_WRITE_4 333 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); CSR_WRITE_4 338 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MAR0, 0); CSR_WRITE_4 339 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MAR1, 0); CSR_WRITE_4 357 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); CSR_WRITE_4 358 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); CSR_WRITE_4 664 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); CSR_WRITE_4 740 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, VTOPHYS(c)); CSR_WRITE_4 1029 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); CSR_WRITE_4 1031 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); CSR_WRITE_4 1096 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); CSR_WRITE_4 1144 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, VTOPHYS(cur_tx)); CSR_WRITE_4 1227 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); CSR_WRITE_4 1228 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); CSR_WRITE_4 1245 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| CSR_WRITE_4 1252 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, CSR_WRITE_4 1255 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); CSR_WRITE_4 1262 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, CSR_WRITE_4 1265 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); CSR_WRITE_4 1269 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); CSR_WRITE_4 1272 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); CSR_WRITE_4 1275 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); CSR_WRITE_4 1278 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); CSR_WRITE_4 1279 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); CSR_WRITE_4 1282 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); CSR_WRITE_4 1285 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); CSR_WRITE_4 1288 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| CSR_WRITE_4 1293 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); CSR_WRITE_4 1304 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| CSR_WRITE_4 1312 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); CSR_WRITE_4 1315 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); CSR_WRITE_4 1316 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); CSR_WRITE_4 1318 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); CSR_WRITE_4 1319 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); CSR_WRITE_4 1324 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| CSR_WRITE_4 1403 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, CSR_WRITE_4 1410 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, CSR_WRITE_4 1487 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); CSR_WRITE_4 1490 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); CSR_WRITE_4 241 dev/pci/if_msk.c CSR_WRITE_4(sc, reg, x); CSR_WRITE_4 874 dev/pci/if_msk.c CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); CSR_WRITE_4 881 dev/pci/if_msk.c CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); CSR_WRITE_4 1776 dev/pci/if_msk.c CSR_WRITE_4(sc, SK_Y2_ICR, 2); CSR_WRITE_4 1830 dev/pci/if_msk.c CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); CSR_WRITE_4 1834 dev/pci/if_msk.c CSR_WRITE_4(sc, SK_Y2_ICR, 2); CSR_WRITE_4 2065 dev/pci/if_msk.c CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); CSR_WRITE_4 2115 dev/pci/if_msk.c CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); CSR_WRITE_4 201 dev/pci/if_nge.c CSR_WRITE_4(sc, reg, \ CSR_WRITE_4 205 dev/pci/if_nge.c CSR_WRITE_4(sc, reg, \ CSR_WRITE_4 209 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x)) CSR_WRITE_4 212 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x)) CSR_WRITE_4 246 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); CSR_WRITE_4 413 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_MEAR, 0); CSR_WRITE_4 596 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_TX_CFG, txcfg); CSR_WRITE_4 597 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_RX_CFG, rxcfg); CSR_WRITE_4 639 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i); CSR_WRITE_4 640 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0); CSR_WRITE_4 659 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_RXFILT_CTL, CSR_WRITE_4 665 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave); CSR_WRITE_4 691 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS); CSR_WRITE_4 692 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_CLKRUN, 0); CSR_WRITE_4 799 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_IER, 0); CSR_WRITE_4 919 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) CSR_WRITE_4 1455 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); CSR_WRITE_4 1479 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_TX_CFG, txcfg); CSR_WRITE_4 1480 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_RX_CFG, rxcfg); CSR_WRITE_4 1523 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_IER, 0); CSR_WRITE_4 1527 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) CSR_WRITE_4 1576 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_IER, 1); CSR_WRITE_4 1583 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) CSR_WRITE_4 1742 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0); CSR_WRITE_4 1743 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_RXFILT_DATA, CSR_WRITE_4 1745 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1); CSR_WRITE_4 1746 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_RXFILT_DATA, CSR_WRITE_4 1748 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2); CSR_WRITE_4 1749 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_RXFILT_DATA, CSR_WRITE_4 1800 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_RX_LISTPTR, CSR_WRITE_4 1802 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_TX_LISTPTR, CSR_WRITE_4 1806 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG); CSR_WRITE_4 1812 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB); CSR_WRITE_4 1815 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG); CSR_WRITE_4 1849 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_TX_CFG, txcfg); CSR_WRITE_4 1850 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_RX_CFG, rxcfg); CSR_WRITE_4 1872 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_IHR, 0x01); CSR_WRITE_4 1877 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS); CSR_WRITE_4 1878 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_IER, 1); CSR_WRITE_4 1955 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_TBI_ANAR, anar); CSR_WRITE_4 1959 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_TBI_BMCR, bmcr); CSR_WRITE_4 1962 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_TBI_BMCR, bmcr); CSR_WRITE_4 1978 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_TX_CFG, txcfg); CSR_WRITE_4 1979 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_RX_CFG, rxcfg); CSR_WRITE_4 2185 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_IER, 0); CSR_WRITE_4 2186 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_IMR, 0); CSR_WRITE_4 2189 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0); CSR_WRITE_4 2190 dev/pci/if_nge.c CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0); CSR_WRITE_4 161 dev/pci/if_sis.c CSR_WRITE_4(sc, reg, \ CSR_WRITE_4 165 dev/pci/if_sis.c CSR_WRITE_4(sc, reg, \ CSR_WRITE_4 169 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) CSR_WRITE_4 172 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) CSR_WRITE_4 225 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); CSR_WRITE_4 354 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); CSR_WRITE_4 356 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); CSR_WRITE_4 358 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); CSR_WRITE_4 595 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_PHYCTL, CSR_WRITE_4 636 dev/pci/if_sis.c CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); CSR_WRITE_4 652 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | CSR_WRITE_4 753 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); CSR_WRITE_4 754 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); CSR_WRITE_4 762 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); CSR_WRITE_4 769 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); CSR_WRITE_4 827 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); CSR_WRITE_4 828 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); CSR_WRITE_4 831 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); CSR_WRITE_4 869 dev/pci/if_sis.c CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); CSR_WRITE_4 870 dev/pci/if_sis.c CSR_WRITE_4(sc, NS_CLKRUN, 0); CSR_WRITE_4 1488 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_IER, 0); CSR_WRITE_4 1524 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_IER, 1); CSR_WRITE_4 1669 dev/pci/if_sis.c CSR_WRITE_4(sc, NS_IHR, NS_IHR_VALUE); CSR_WRITE_4 1676 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); CSR_WRITE_4 1677 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_RXFILT_DATA, CSR_WRITE_4 1679 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); CSR_WRITE_4 1680 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_RXFILT_DATA, CSR_WRITE_4 1682 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); CSR_WRITE_4 1683 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_RXFILT_DATA, CSR_WRITE_4 1686 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); CSR_WRITE_4 1687 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_RXFILT_DATA, CSR_WRITE_4 1689 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); CSR_WRITE_4 1690 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_RXFILT_DATA, CSR_WRITE_4 1692 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); CSR_WRITE_4 1693 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_RXFILT_DATA, CSR_WRITE_4 1714 dev/pci/if_sis.c CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); CSR_WRITE_4 1715 dev/pci/if_sis.c CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); CSR_WRITE_4 1718 dev/pci/if_sis.c CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); CSR_WRITE_4 1720 dev/pci/if_sis.c CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); CSR_WRITE_4 1722 dev/pci/if_sis.c CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); CSR_WRITE_4 1724 dev/pci/if_sis.c CSR_WRITE_4(sc, NS_PHY_PAGE, 0); CSR_WRITE_4 1760 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sc_listmap->dm_segs[0].ds_addr + CSR_WRITE_4 1762 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sc_listmap->dm_segs[0].ds_addr + CSR_WRITE_4 1770 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); CSR_WRITE_4 1772 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); CSR_WRITE_4 1779 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); CSR_WRITE_4 1781 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); CSR_WRITE_4 1809 dev/pci/if_sis.c CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); CSR_WRITE_4 1811 dev/pci/if_sis.c CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000); CSR_WRITE_4 1819 dev/pci/if_sis.c CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8); CSR_WRITE_4 1823 dev/pci/if_sis.c CSR_WRITE_4(sc, NS_PHY_PAGE, 0); CSR_WRITE_4 1829 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); CSR_WRITE_4 1830 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_IER, 1); CSR_WRITE_4 2019 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_IER, 0); CSR_WRITE_4 2020 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_IMR, 0); CSR_WRITE_4 2024 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); CSR_WRITE_4 2025 dev/pci/if_sis.c CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); CSR_WRITE_4 232 dev/pci/if_sk.c CSR_WRITE_4(sc, reg, x); CSR_WRITE_4 1660 dev/pci/if_sk.c CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); CSR_WRITE_4 2139 dev/pci/if_sk.c CSR_WRITE_4(sc, SK_BMU_RX_CSR0, CSR_WRITE_4 2144 dev/pci/if_sk.c CSR_WRITE_4(sc, SK_BMU_RX_CSR1, CSR_WRITE_4 2151 dev/pci/if_sk.c CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, CSR_WRITE_4 2156 dev/pci/if_sk.c CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, CSR_WRITE_4 2190 dev/pci/if_sk.c CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); CSR_WRITE_4 2648 dev/pci/if_sk.c CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); CSR_WRITE_4 2669 dev/pci/if_sk.c CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); CSR_WRITE_4 2698 dev/pci/if_sk.c CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP); CSR_WRITE_4 2765 dev/pci/if_sk.c CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); CSR_WRITE_4 124 dev/pci/if_ste.c CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) CSR_WRITE_4 127 dev/pci/if_ste.c CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) CSR_WRITE_4 1157 dev/pci/if_ste.c CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, CSR_WRITE_4 1168 dev/pci/if_ste.c CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); CSR_WRITE_4 1466 dev/pci/if_ste.c CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, CSR_WRITE_4 637 dev/pci/if_stge.c CSR_WRITE_4(sc, STGE_DMACtrl, CSR_WRITE_4 1160 dev/pci/if_stge.c CSR_WRITE_4(sc, STGE_AsicCtrl, CSR_WRITE_4 1248 dev/pci/if_stge.c CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff); CSR_WRITE_4 1249 dev/pci/if_stge.c CSR_WRITE_4(sc, STGE_StatisticsMask, CSR_WRITE_4 1261 dev/pci/if_stge.c CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0); /* NOTE: 32-bit DMA */ CSR_WRITE_4 1262 dev/pci/if_stge.c CSR_WRITE_4(sc, STGE_TFDListPtrLo, CSR_WRITE_4 1265 dev/pci/if_stge.c CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0); /* NOTE: 32-bit DMA */ CSR_WRITE_4 1266 dev/pci/if_stge.c CSR_WRITE_4(sc, STGE_RFDListPtrLo, CSR_WRITE_4 1300 dev/pci/if_stge.c CSR_WRITE_4(sc, STGE_RxDMAIntCtrl, CSR_WRITE_4 1315 dev/pci/if_stge.c CSR_WRITE_4(sc, STGE_DMACtrl, sc->sc_DMACtrl | CSR_WRITE_4 1343 dev/pci/if_stge.c CSR_WRITE_4(sc, STGE_MACCtrl, sc->sc_MACCtrl); CSR_WRITE_4 1437 dev/pci/if_stge.c CSR_WRITE_4(sc, STGE_MACCtrl, CSR_WRITE_4 1444 dev/pci/if_stge.c CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0); CSR_WRITE_4 1445 dev/pci/if_stge.c CSR_WRITE_4(sc, STGE_TFDListPtrLo, 0); CSR_WRITE_4 1446 dev/pci/if_stge.c CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0); CSR_WRITE_4 1447 dev/pci/if_stge.c CSR_WRITE_4(sc, STGE_RFDListPtrLo, 0); CSR_WRITE_4 1625 dev/pci/if_stge.c CSR_WRITE_4(sc, STGE_HashTable0, mchash[0]); CSR_WRITE_4 1626 dev/pci/if_stge.c CSR_WRITE_4(sc, STGE_HashTable1, mchash[1]); CSR_WRITE_4 1673 dev/pci/if_stge.c CSR_WRITE_4(sc, STGE_MACCtrl, sc->sc_MACCtrl); CSR_WRITE_4 355 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); CSR_WRITE_4 385 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); CSR_WRITE_4 412 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); CSR_WRITE_4 470 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tf->FwStartAddr); CSR_WRITE_4 483 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); CSR_WRITE_4 485 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); CSR_WRITE_4 501 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); CSR_WRITE_4 504 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), CSR_WRITE_4 508 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); CSR_WRITE_4 557 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); CSR_WRITE_4 1055 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); CSR_WRITE_4 1091 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); CSR_WRITE_4 1092 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); CSR_WRITE_4 1117 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); CSR_WRITE_4 1118 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); CSR_WRITE_4 1169 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); CSR_WRITE_4 1184 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); CSR_WRITE_4 1199 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); CSR_WRITE_4 1212 dev/pci/if_ti.c CSR_WRITE_4(sc, 0x600, 0); CSR_WRITE_4 1213 dev/pci/if_ti.c CSR_WRITE_4(sc, 0x604, 0); CSR_WRITE_4 1214 dev/pci/if_ti.c CSR_WRITE_4(sc, 0x600, 0x5555AAAA); CSR_WRITE_4 1244 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_MISC_HOST_CTL, CSR_WRITE_4 1281 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); CSR_WRITE_4 1309 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, CSR_WRITE_4 1332 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_DMA_SWAP_OPTIONS | CSR_WRITE_4 1337 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); CSR_WRITE_4 1338 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); CSR_WRITE_4 1363 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); CSR_WRITE_4 1371 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); CSR_WRITE_4 1372 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, CSR_WRITE_4 1388 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); CSR_WRITE_4 1398 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); CSR_WRITE_4 1400 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); CSR_WRITE_4 1401 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); CSR_WRITE_4 1460 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); CSR_WRITE_4 1485 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, (sc->ti_rx_coal_ticks / 10)); CSR_WRITE_4 1486 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); CSR_WRITE_4 1487 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); CSR_WRITE_4 1488 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); CSR_WRITE_4 1489 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); CSR_WRITE_4 1490 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); CSR_WRITE_4 1493 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); CSR_WRITE_4 1494 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); CSR_WRITE_4 1831 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, CSR_WRITE_4 1947 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); CSR_WRITE_4 1963 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); CSR_WRITE_4 2215 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); CSR_WRITE_4 2256 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->sc_dv.dv_unit); CSR_WRITE_4 2257 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_IFMTU, CSR_WRITE_4 2263 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); CSR_WRITE_4 2264 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); CSR_WRITE_4 2299 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); CSR_WRITE_4 2309 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); CSR_WRITE_4 2345 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| CSR_WRITE_4 2348 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| CSR_WRITE_4 2356 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| CSR_WRITE_4 2358 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_LINK, 0); CSR_WRITE_4 2369 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_GLINK, 0); CSR_WRITE_4 2370 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); CSR_WRITE_4 2557 dev/pci/if_ti.c CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); CSR_WRITE_4 923 dev/pci/if_tireg.h CSR_WRITE_4(x, TI_MB_JUMBORXPROD_IDX, y); \ CSR_WRITE_4 927 dev/pci/if_tireg.h CSR_WRITE_4(x, TI_MB_MINIRXPROD_IDX, y); CSR_WRITE_4 933 dev/pci/if_tireg.h CSR_WRITE_4(x, TI_MB_STDRXPROD_IDX, y); \ CSR_WRITE_4 982 dev/pci/if_tireg.h CSR_WRITE_4(sc, (reg), (CSR_READ_4(sc, (reg)) | (x))) CSR_WRITE_4 984 dev/pci/if_tireg.h CSR_WRITE_4(sc, (reg), (CSR_READ_4(sc, (reg)) & ~(x))) CSR_WRITE_4 356 dev/pci/if_tl.c CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val); CSR_WRITE_4 1207 dev/pci/if_tl.c CSR_WRITE_4(sc, TL_CH_PARM, VTOPHYS(sc->tl_cdata.tl_rx_head->tl_ptr)); CSR_WRITE_4 1287 dev/pci/if_tl.c CSR_WRITE_4(sc, TL_CH_PARM, CSR_WRITE_4 1626 dev/pci/if_tl.c CSR_WRITE_4(sc, TL_CH_PARM, VTOPHYS(start_tx->tl_ptr)); CSR_WRITE_4 1707 dev/pci/if_tl.c CSR_WRITE_4(sc, TL_CH_PARM, VTOPHYS(&sc->tl_ldata->tl_rx_list[0])); CSR_WRITE_4 1902 dev/pci/if_tl.c CSR_WRITE_4(sc, TL_CH_PARM, 0); CSR_WRITE_4 1907 dev/pci/if_tl.c CSR_WRITE_4(sc, TL_CH_PARM, 0); CSR_WRITE_4 1917 dev/pci/if_tl.c CSR_WRITE_4(sc, TL_CH_PARM, 0); CSR_WRITE_4 515 dev/pci/if_tlreg.h #define CMD_PUT(sc, x) CSR_WRITE_4(sc, TL_HOSTCMD, x) CSR_WRITE_4 517 dev/pci/if_tlreg.h CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) | (x)) CSR_WRITE_4 519 dev/pci/if_tlreg.h CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) & ~(x)) CSR_WRITE_4 486 dev/pci/if_vge.c CSR_WRITE_4(sc, VGE_MAR0, 0); CSR_WRITE_4 487 dev/pci/if_vge.c CSR_WRITE_4(sc, VGE_MAR1, 0); CSR_WRITE_4 496 dev/pci/if_vge.c CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); CSR_WRITE_4 497 dev/pci/if_vge.c CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); CSR_WRITE_4 528 dev/pci/if_vge.c CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); CSR_WRITE_4 529 dev/pci/if_vge.c CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); CSR_WRITE_4 1242 dev/pci/if_vge.c CSR_WRITE_4(sc, VGE_ISR, status); CSR_WRITE_4 1550 dev/pci/if_vge.c CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, CSR_WRITE_4 1554 dev/pci/if_vge.c CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, CSR_WRITE_4 1641 dev/pci/if_vge.c CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); CSR_WRITE_4 1642 dev/pci/if_vge.c CSR_WRITE_4(sc, VGE_ISR, 0); CSR_WRITE_4 1850 dev/pci/if_vge.c CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); CSR_WRITE_4 1853 dev/pci/if_vge.c CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); CSR_WRITE_4 117 dev/pci/if_vgevar.h CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) CSR_WRITE_4 124 dev/pci/if_vgevar.h CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) CSR_WRITE_4 171 dev/pci/if_vr.c CSR_WRITE_4(sc, reg, \ CSR_WRITE_4 175 dev/pci/if_vr.c CSR_WRITE_4(sc, reg, \ CSR_WRITE_4 508 dev/pci/if_vr.c CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); CSR_WRITE_4 509 dev/pci/if_vr.c CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); CSR_WRITE_4 514 dev/pci/if_vr.c CSR_WRITE_4(sc, VR_MAR0, 0); CSR_WRITE_4 515 dev/pci/if_vr.c CSR_WRITE_4(sc, VR_MAR1, 0); CSR_WRITE_4 539 dev/pci/if_vr.c CSR_WRITE_4(sc, VR_MAR0, hashes[0]); CSR_WRITE_4 540 dev/pci/if_vr.c CSR_WRITE_4(sc, VR_MAR1, hashes[1]); CSR_WRITE_4 1065 dev/pci/if_vr.c CSR_WRITE_4(sc, VR_RXADDR, sc->vr_cdata.vr_rx_head->vr_paddr); CSR_WRITE_4 1107 dev/pci/if_vr.c CSR_WRITE_4(sc, VR_TXADDR, cur_tx->vr_paddr); CSR_WRITE_4 1471 dev/pci/if_vr.c CSR_WRITE_4(sc, VR_RXADDR, sc->vr_cdata.vr_rx_head->vr_paddr); CSR_WRITE_4 1478 dev/pci/if_vr.c CSR_WRITE_4(sc, VR_TXADDR, sc->sc_listmap->dm_segs[0].ds_addr + CSR_WRITE_4 1649 dev/pci/if_vr.c CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); CSR_WRITE_4 1650 dev/pci/if_vr.c CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); CSR_WRITE_4 179 dev/pci/if_wb.c CSR_WRITE_4(sc, reg, \ CSR_WRITE_4 183 dev/pci/if_wb.c CSR_WRITE_4(sc, reg, \ CSR_WRITE_4 187 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_SIO, \ CSR_WRITE_4 191 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_SIO, \ CSR_WRITE_4 236 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); CSR_WRITE_4 243 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); CSR_WRITE_4 258 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_SIO, 0); CSR_WRITE_4 355 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_SIO, 0); CSR_WRITE_4 547 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_NETCFG, rxfilt); CSR_WRITE_4 548 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); CSR_WRITE_4 549 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); CSR_WRITE_4 554 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_MAR0, 0); CSR_WRITE_4 555 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_MAR1, 0); CSR_WRITE_4 578 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_MAR0, hashes[0]); CSR_WRITE_4 579 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_MAR1, hashes[1]); CSR_WRITE_4 580 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_NETCFG, rxfilt); CSR_WRITE_4 636 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_NETCFG, 0); CSR_WRITE_4 637 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_BUSCTL, 0); CSR_WRITE_4 638 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_TXADDR, 0); CSR_WRITE_4 639 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_RXADDR, 0); CSR_WRITE_4 1085 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_RXADDR, VTOPHYS(&sc->wb_ldata->wb_rx_list[0])); CSR_WRITE_4 1088 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); CSR_WRITE_4 1169 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); CSR_WRITE_4 1191 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_IMR, 0x00000000); CSR_WRITE_4 1197 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_ISR, status); CSR_WRITE_4 1229 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); CSR_WRITE_4 1252 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_IMR, WB_INTRS); CSR_WRITE_4 1438 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); CSR_WRITE_4 1484 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); CSR_WRITE_4 1489 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); CSR_WRITE_4 1552 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_RXADDR, VTOPHYS(&sc->wb_ldata->wb_rx_list[0])); CSR_WRITE_4 1557 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_IMR, WB_INTRS); CSR_WRITE_4 1558 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); CSR_WRITE_4 1562 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); CSR_WRITE_4 1565 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_TXADDR, VTOPHYS(&sc->wb_ldata->wb_tx_list[0])); CSR_WRITE_4 1723 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_IMR, 0x00000000); CSR_WRITE_4 1724 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); CSR_WRITE_4 1725 dev/pci/if_wb.c CSR_WRITE_4(sc, WB_RXADDR, 0x00000000);