root/dev/pci/if_ti.c

DEFINITIONS

1. ti_eeprom_putbyte
2. ti_eeprom_getbyte
3. ti_read_eeprom
4. ti_mem_read
5. ti_mem_write
6. ti_mem_set
7. ti_loadfw
8. ti_cmd
9. ti_cmd_ext
10. ti_handle_events
11. ti_alloc_jumbo_mem
12. ti_jalloc
13. ti_jfree
14. ti_newbuf_std
15. ti_newbuf_mini
16. ti_newbuf_jumbo
17. ti_init_rx_ring_std
18. ti_free_rx_ring_std
19. ti_init_rx_ring_jumbo
20. ti_free_rx_ring_jumbo
21. ti_init_rx_ring_mini
22. ti_free_rx_ring_mini
23. ti_free_tx_ring
24. ti_init_tx_ring
25. ti_add_mcast
26. ti_del_mcast
27. ti_setmulti
28. ti_64bitslot_war
29. ti_chipinit
30. ti_gibinit
31. ti_probe
32. ti_attach
33. ti_rxeof
34. ti_txeof_tigon1
35. ti_txeof_tigon2
36. ti_intr
37. ti_stats_update
38. ti_encap_tigon1
39. ti_encap_tigon2
40. ti_start
41. ti_init
42. ti_init2
43. ti_ifmedia_upd
44. ti_ifmedia_sts
45. ti_ioctl
46. ti_watchdog
47. ti_stop
48. ti_shutdown

    1 /*      $OpenBSD: if_ti.c,v 1.84 2006/11/20 22:49:32 brad Exp $ */
    3 /*
    4  * Copyright (c) 1997, 1998, 1999
    5  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. All advertising materials mentioning features or use of this software
   16  *    must display the following acknowledgement:
   17  *      This product includes software developed by Bill Paul.
   18  * 4. Neither the name of the author nor the names of any co-contributors
   19  *    may be used to endorse or promote products derived from this software
   20  *    without specific prior written permission.
   21  *
   22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   32  * THE POSSIBILITY OF SUCH DAMAGE.
   33  *
   34  * $FreeBSD: src/sys/pci/if_ti.c,v 1.25 2000/01/18 00:26:29 wpaul Exp $
   35  */
   37 /*
   38  * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
   39  * Manuals, sample driver and firmware source kits are available
   40  * from http://www.alteon.com/support/openkits.
   41  *
   42  * Written by Bill Paul <wpaul@ctr.columbia.edu>
   43  * Electrical Engineering Department
   44  * Columbia University, New York City
   45  */
   47 /*
   48  * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
   49  * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
   50  * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
   51  * Tigon supports hardware IP, TCP and UCP checksumming, multicast
   52  * filtering and jumbo (9014 byte) frames. The hardware is largely
   53  * controlled by firmware, which must be loaded into the NIC during
   54  * initialization.
   55  *
   56  * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
   57  * revision, which supports new features such as extended commands,
   58  * extended jumbo receive ring desciptors and a mini receive ring.
   59  *
   60  * Alteon Networks is to be commended for releasing such a vast amount
   61  * of development material for the Tigon NIC without requiring an NDA
   62  * (although they really should have done it a long time ago). With
   63  * any luck, the other vendors will finally wise up and follow Alteon's
   64  * stellar example.
   65  *
   66  * The firmware for the Tigon 1 and 2 NICs is compiled directly into
   67  * this driver by #including it as a C header file. This bloats the
   68  * driver somewhat, but it's the easiest method considering that the
   69  * driver code and firmware code need to be kept in sync. The source
   70  * for the firmware is not provided with the FreeBSD distribution since
   71  * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
   72  *
   73  * The following people deserve special thanks:
   74  * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
   75  *   for testing
   76  * - Raymond Lee of Netgear, for providing a pair of Netgear
   77  *   GA620 Tigon 2 boards for testing
   78  * - Ulf Zimmermann, for bringing the GA260 to my attention and
   79  *   convincing me to write this driver.
   80  * - Andrew Gallatin for providing FreeBSD/Alpha support.
   81  */
   83 #include "bpfilter.h"
   84 #include "vlan.h"
   86 #include <sys/param.h>
   87 #include <sys/systm.h>
   88 #include <sys/sockio.h>
   89 #include <sys/mbuf.h>
   90 #include <sys/malloc.h>
   91 #include <sys/kernel.h>
   92 #include <sys/socket.h>
   93 #include <sys/device.h>
   94 #include <sys/queue.h>
   96 #include <net/if.h>
   97 #include <net/if_dl.h>
   98 #include <net/if_types.h>
  100 #ifdef INET
  101 #include <netinet/in.h>
  102 #include <netinet/in_systm.h>
  103 #include <netinet/in_var.h>
  104 #include <netinet/ip.h>
  105 #include <netinet/if_ether.h>
  106 #endif
  108 #include <net/if_media.h>
  110 #if NBPFILTER > 0
  111 #include <net/bpf.h>
  112 #endif
  114 #if NVLAN > 0
  115 #include <net/if_types.h>
  116 #include <net/if_vlan_var.h>
  117 #endif
  119 #include <dev/pci/pcireg.h>
  120 #include <dev/pci/pcivar.h>
  121 #include <dev/pci/pcidevs.h>
  123 #include <dev/pci/if_tireg.h>
  124 #include <dev/pci/if_tivar.h>
  126 int ti_probe(struct device *, void *, void *);
  127 void ti_attach(struct device *, struct device *, void *);
  129 struct cfattach ti_ca = {
  130         sizeof(struct ti_softc), ti_probe, ti_attach
  131 };
  133 struct cfdriver ti_cd = {
  134         0, "ti", DV_IFNET
  135 };
  137 void ti_txeof_tigon1(struct ti_softc *);
  138 void ti_txeof_tigon2(struct ti_softc *);
  139 void ti_rxeof(struct ti_softc *);
  141 void ti_stats_update(struct ti_softc *);
  142 int ti_encap_tigon1(struct ti_softc *, struct mbuf *, u_int32_t *);
  143 int ti_encap_tigon2(struct ti_softc *, struct mbuf *, u_int32_t *);
  145 int ti_intr(void *);
  146 void ti_start(struct ifnet *);
  147 int ti_ioctl(struct ifnet *, u_long, caddr_t);
  148 void ti_init(void *);
  149 void ti_init2(struct ti_softc *);
  150 void ti_stop(struct ti_softc *);
  151 void ti_watchdog(struct ifnet *);
  152 void ti_shutdown(void *);
  153 int ti_ifmedia_upd(struct ifnet *);
  154 void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *);
u_int32_t ti_eeprom_putbyte(struct ti_softc *, int);
u_int8_t ti_eeprom_getbyte(struct ti_softc *, int, u_int8_t *);
  158 int ti_read_eeprom(struct ti_softc *, caddr_t, int, int);
  160 void ti_add_mcast(struct ti_softc *, struct ether_addr *);
  161 void ti_del_mcast(struct ti_softc *, struct ether_addr *);
  162 void ti_setmulti(struct ti_softc *);
  164 void ti_mem_read(struct ti_softc *, u_int32_t, u_int32_t, void *);
  165 void ti_mem_write(struct ti_softc *, u_int32_t, u_int32_t, const void*);
  166 void ti_mem_set(struct ti_softc *, u_int32_t, u_int32_t);
  167 void ti_loadfw(struct ti_softc *);
  168 void ti_cmd(struct ti_softc *, struct ti_cmd_desc *);
  169 void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *,
caddr_t, int);
  171 void ti_handle_events(struct ti_softc *);
  172 int ti_alloc_jumbo_mem(struct ti_softc *);
  173 void *ti_jalloc(struct ti_softc *);
  174 void ti_jfree(caddr_t, u_int, void *);
  175 int ti_newbuf_std(struct ti_softc *, int, struct mbuf *, bus_dmamap_t);
  176 int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *, bus_dmamap_t);
  177 int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *);
  178 int ti_init_rx_ring_std(struct ti_softc *);
  179 void ti_free_rx_ring_std(struct ti_softc *);
  180 int ti_init_rx_ring_jumbo(struct ti_softc *);
  181 void ti_free_rx_ring_jumbo(struct ti_softc *);
  182 int ti_init_rx_ring_mini(struct ti_softc *);
  183 void ti_free_rx_ring_mini(struct ti_softc *);
  184 void ti_free_tx_ring(struct ti_softc *);
  185 int ti_init_tx_ring(struct ti_softc *);
  187 int ti_64bitslot_war(struct ti_softc *);
  188 int ti_chipinit(struct ti_softc *);
  189 int ti_gibinit(struct ti_softc *);
  191 const struct pci_matchid ti_devices[] = {
  192         { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620 },
  193         { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620T },
  194         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC },
  195         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENICT },
  196         { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C985 },
  197         { PCI_VENDOR_SGI, PCI_PRODUCT_SGI_TIGON },
  198         { PCI_VENDOR_DEC, PCI_PRODUCT_DEC_PN9000SX }
  199 };
  201 /*
  202  * Send an instruction or address to the EEPROM, check for ACK.
  203  */
u_int32_t
ti_eeprom_putbyte(struct ti_softc *sc, int byte)
  206 {
  207         int             i, ack = 0;
  209         /*
  210          * Make sure we're in TX mode.
  211          */
TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
  214         /*
  215          * Feed in each bit and strobe the clock.
  216          */
  217         for (i = 0x80; i; i >>= 1) {
  218                 if (byte & i)
TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
  220                 else
TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
DELAY(1);
TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
DELAY(1);
TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
  226         }
  228         /*
  229          * Turn off TX mode.
  230          */
TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
  233         /*
  234          * Check for ack.
  235          */
TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
  240         return (ack);
  241 }
  243 /*
  244  * Read a byte of data stored in the EEPROM at address 'addr.'
  245  * We have to send two address bytes since the EEPROM can hold
  246  * more than 256 bytes of data.
  247  */
u_int8_t
ti_eeprom_getbyte(struct ti_softc *sc, int addr, u_int8_t *dest)
  250 {
  251         int             i;
u_int8_t                byte = 0;
EEPROM_START;
  256         /*
  257          * Send write control code to EEPROM.
  258          */
  259         if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
printf("%s: failed to send write command, status: %x\n",
sc->sc_dv.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
  262                 return (1);
  263         }
  265         /*
  266          * Send first byte of address of byte we want to read.
  267          */
  268         if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
printf("%s: failed to send address, status: %x\n",
sc->sc_dv.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
  271                 return (1);
  272         }
  273         /*
  274          * Send second byte address of byte we want to read.
  275          */
  276         if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
printf("%s: failed to send address, status: %x\n",
sc->sc_dv.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
  279                 return (1);
  280         }
EEPROM_STOP;
EEPROM_START;
  284         /*
  285          * Send read control code to EEPROM.
  286          */
  287         if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
printf("%s: failed to send read command, status: %x\n",
sc->sc_dv.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
  290                 return (1);
  291         }
  293         /*
  294          * Start reading bits from EEPROM.
  295          */
TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
  297         for (i = 0x80; i; i >>= 1) {
TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
DELAY(1);
  300                 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
byte |= i;
TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
DELAY(1);
  304         }
EEPROM_STOP;
  308         /*
  309          * No ACK generated for read, so just return byte.
  310          */
  312         *dest = byte;
  314         return (0);
  315 }
  317 /*
  318  * Read a sequence of bytes from the EEPROM.
  319  */
  320 int
ti_read_eeprom(struct ti_softc *sc, caddr_t dest, int off, int cnt)
  322 {
  323         int                     err = 0, i;
u_int8_t                byte = 0;
  326         for (i = 0; i < cnt; i++) {
err = ti_eeprom_getbyte(sc, off + i, &byte);
  328                 if (err)
  329                         break;
  330                 *(dest + i) = byte;
  331         }
  333         return (err ? 1 : 0);
  334 }
  336 /*
  337  * NIC memory read function.
  338  * Can be used to copy data from NIC local memory.
  339  */
  340 void
ti_mem_read(struct ti_softc *sc, u_int32_t addr, u_int32_t len, void *buf)
  342 {
  343         int                     segptr, segsize, cnt;
caddr_t                 ptr;
segptr = addr;
cnt = len;
ptr = buf;
  350         while(cnt) {
  351                 if (cnt < TI_WINLEN)
segsize = cnt;
  353                 else
segsize = TI_WINLEN - (segptr % TI_WINLEN);
CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
TI_WINDOW + (segptr & (TI_WINLEN - 1)), (u_int32_t *)ptr,
segsize / 4);
ptr += segsize;
segptr += segsize;
cnt -= segsize;
  362         }
  363 }
  365 /*
  366  * NIC memory write function.
  367  * Can be used to copy data into  NIC local memory.
  368  */
  369 void
ti_mem_write(struct ti_softc *sc, u_int32_t addr, u_int32_t len,
  371     const void *buf)
  372 {
  373         int                     segptr, segsize, cnt;
  374         const char              *ptr;
segptr = addr;
cnt = len;
ptr = buf;
  380         while(cnt) {
  381                 if (cnt < TI_WINLEN)
segsize = cnt;
  383                 else
segsize = TI_WINLEN - (segptr % TI_WINLEN);
CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
TI_WINDOW + (segptr & (TI_WINLEN - 1)), (u_int32_t *)ptr,
segsize / 4);
ptr += segsize;
segptr += segsize;
cnt -= segsize;
  392         }
  393 }
  395 /*
  396  * NIC memory write function.
  397  * Can be used to clear a section of NIC local memory.
  398  */
  399 void
ti_mem_set(struct ti_softc *sc, u_int32_t addr, u_int32_t len)
  401 {
  402         int                     segptr, segsize, cnt;
segptr = addr;
cnt = len;
  407         while(cnt) {
  408                 if (cnt < TI_WINLEN)
segsize = cnt;
  410                 else
segsize = TI_WINLEN - (segptr % TI_WINLEN);
CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle,
TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, segsize / 4);
segptr += segsize;
cnt -= segsize;
  417         }
  418 }
  420 /*
  421  * Load firmware image into the NIC. Check that the firmware revision
  422  * is acceptable and see if we want the firmware for the Tigon 1 or
  423  * Tigon 2.
  424  */
  425 void
ti_loadfw(struct ti_softc *sc)
  427 {
  428         struct tigon_firmware *tf;
u_char *buf = NULL;
size_t buflen;
  431         char *name;
  432         int error;
  434         switch(sc->ti_hwrev) {
  435         case TI_HWREV_TIGON:
name = "tigon1";
  437                 break;
  438         case TI_HWREV_TIGON_II:
name = "tigon2";
  440                 break;
  441         default:
printf("%s: can't load firmware: unknown hardware rev\n",
sc->sc_dv.dv_xname);
  444                 return;
  445         }
error = loadfirmware(name, &buf, &buflen);
  448         if (error)
  449                 return;
tf = (struct tigon_firmware *)buf;
  451         if (tf->FwReleaseMajor != TI_FIRMWARE_MAJOR ||
tf->FwReleaseMinor != TI_FIRMWARE_MINOR ||
tf->FwReleaseFix != TI_FIRMWARE_FIX) {
printf("%s: firmware revision mismatch; want "
  455                     "%d.%d.%d, got %d.%d.%d\n", sc->sc_dv.dv_xname,
TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
TI_FIRMWARE_FIX, tf->FwReleaseMajor,
tf->FwReleaseMinor, tf->FwReleaseFix);
free(buf, M_DEVBUF);
  460                 return;
  461         }
ti_mem_write(sc, tf->FwTextAddr, tf->FwTextLen,
  463             (caddr_t)&tf->data[tf->FwTextOffset]);
ti_mem_write(sc, tf->FwRodataAddr, tf->FwRodataLen,
  465             (caddr_t)&tf->data[tf->FwRodataOffset]);
ti_mem_write(sc, tf->FwDataAddr, tf->FwDataLen,
  467             (caddr_t)&tf->data[tf->FwDataOffset]);
ti_mem_set(sc, tf->FwBssAddr, tf->FwBssLen);
ti_mem_set(sc, tf->FwSbssAddr, tf->FwSbssLen);
CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tf->FwStartAddr);
free(buf, M_DEVBUF);
  472 }
  474 /*
  475  * Send the NIC a command via the command ring.
  476  */
  477 void
ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd)
  479 {
u_int32_t               index;
index = sc->ti_cmd_saved_prodidx;
CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
TI_INC(index, TI_CMD_RING_CNT);
CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
sc->ti_cmd_saved_prodidx = index;
  487 }
  489 /*
  490  * Send the NIC an extended command. The 'len' parameter specifies the
  491  * number of command slots to include after the initial command.
  492  */
  493 void
ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, caddr_t arg,
  495     int len)
  496 {
u_int32_t               index;
  498         int             i;
index = sc->ti_cmd_saved_prodidx;
CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
TI_INC(index, TI_CMD_RING_CNT);
  503         for (i = 0; i < len; i++) {
CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
  505                     *(u_int32_t *)(&arg[i * 4]));
TI_INC(index, TI_CMD_RING_CNT);
  507         }
CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
sc->ti_cmd_saved_prodidx = index;
  510 }
  512 /*
  513  * Handle events that have triggered interrupts.
  514  */
  515 void
ti_handle_events(struct ti_softc *sc)
  517 {
  518         struct ti_event_desc    *e;
  520         if (sc->ti_rdata->ti_event_ring == NULL)
  521                 return;
  523         while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
  525                 switch (TI_EVENT_EVENT(e)) {
  526                 case TI_EV_LINKSTAT_CHANGED:
sc->ti_linkstat = TI_EVENT_CODE(e);
  528                         break;
  529                 case TI_EV_ERROR:
  530                         if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD)
printf("%s: invalid command\n",
sc->sc_dv.dv_xname);
  533                         else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD)
printf("%s: unknown command\n",
sc->sc_dv.dv_xname);
  536                         else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG)
printf("%s: bad config data\n",
sc->sc_dv.dv_xname);
  539                         break;
  540                 case TI_EV_FIRMWARE_UP:
ti_init2(sc);
  542                         break;
  543                 case TI_EV_STATS_UPDATED:
ti_stats_update(sc);
  545                         break;
  546                 case TI_EV_RESET_JUMBO_RING:
  547                 case TI_EV_MCAST_UPDATED:
  548                         /* Who cares. */
  549                         break;
  550                 default:
printf("%s: unknown event: %d\n", sc->sc_dv.dv_xname,
TI_EVENT_EVENT(e));
  553                         break;
  554                 }
  555                 /* Advance the consumer index. */
TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
  558         }
  559 }
  561 /*
  562  * Memory management for the jumbo receive ring is a pain in the
  563  * butt. We need to allocate at least 9018 bytes of space per frame,
  564  * _and_ it has to be contiguous (unless you use the extended
  565  * jumbo descriptor format). Using malloc() all the time won't
  566  * work: malloc() allocates memory in powers of two, which means we
  567  * would end up wasting a considerable amount of space by allocating
  568  * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
  569  * to do our own memory management.
  570  *
  571  * The driver needs to allocate a contiguous chunk of memory at boot
  572  * time. We then chop this up ourselves into 9K pieces and use them
  573  * as external mbuf storage.
  574  *
  575  * One issue here is how much memory to allocate. The jumbo ring has
  576  * 256 slots in it, but at 9K per slot than can consume over 2MB of
  577  * RAM. This is a bit much, especially considering we also need
  578  * RAM for the standard ring and mini ring (on the Tigon 2). To
  579  * save space, we only actually allocate enough memory for 64 slots
  580  * by default, which works out to between 500 and 600K. This can
  581  * be tuned by changing a #define in if_tireg.h.
  582  */
  584 int
ti_alloc_jumbo_mem(struct ti_softc *sc)
  586 {
caddr_t ptr, kva;
bus_dma_segment_t seg;
  589         int i, rseg, state, error;
  590         struct ti_jpool_entry *entry;
state = error = 0;
  594         /* Grab a big chunk o' storage. */
  595         if (bus_dmamem_alloc(sc->sc_dmatag, TI_JMEM, PAGE_SIZE, 0,
  596             &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
printf("%s: can't alloc rx buffers\n", sc->sc_dv.dv_xname);
  598                 return (ENOBUFS);
  599         }
state = 1;
  602         if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, TI_JMEM, &kva,
BUS_DMA_NOWAIT)) {
printf("%s: can't map dma buffers (%d bytes)\n",
sc->sc_dv.dv_xname, TI_JMEM);
error = ENOBUFS;
  607                 goto out;
  608         }
state = 2;
  611         if (bus_dmamap_create(sc->sc_dmatag, TI_JMEM, 1, TI_JMEM, 0,
BUS_DMA_NOWAIT, &sc->ti_cdata.ti_rx_jumbo_map)) {
printf("%s: can't create dma map\n", sc->sc_dv.dv_xname);
error = ENOBUFS;
  615                 goto out;
  616         }
state = 3;
  619         if (bus_dmamap_load(sc->sc_dmatag, sc->ti_cdata.ti_rx_jumbo_map, kva,
TI_JMEM, NULL, BUS_DMA_NOWAIT)) {
printf("%s: can't load dma map\n", sc->sc_dv.dv_xname);
error = ENOBUFS;
  623                 goto out;
  624         }
state = 4;
sc->ti_cdata.ti_jumbo_buf = (caddr_t)kva;
SLIST_INIT(&sc->ti_jfree_listhead);
SLIST_INIT(&sc->ti_jinuse_listhead);
  632         /*
  633          * Now divide it up into 9K pieces and save the addresses
  634          * in an array.
  635          */
ptr = sc->ti_cdata.ti_jumbo_buf;
  637         for (i = 0; i < TI_JSLOTS; i++) {
sc->ti_cdata.ti_jslots[i].ti_buf = ptr;
sc->ti_cdata.ti_jslots[i].ti_inuse = 0;
ptr += TI_JLEN;
entry = malloc(sizeof(struct ti_jpool_entry),
M_DEVBUF, M_NOWAIT);
  643                 if (entry == NULL) {
sc->ti_cdata.ti_jumbo_buf = NULL;
printf("%s: no memory for jumbo buffer queue\n",
sc->sc_dv.dv_xname);
error = ENOBUFS;
  648                         goto out;
  649                 }
entry->slot = i;
SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
  652         }
out:
  654         if (error != 0) {
  655                 switch (state) {
  656                 case 4:
bus_dmamap_unload(sc->sc_dmatag,
sc->ti_cdata.ti_rx_jumbo_map);
  659                 case 3:
bus_dmamap_destroy(sc->sc_dmatag,
sc->ti_cdata.ti_rx_jumbo_map);
  662                 case 2:
bus_dmamem_unmap(sc->sc_dmatag, kva, TI_JMEM);
  664                 case 1:
bus_dmamem_free(sc->sc_dmatag, &seg, rseg);
  666                         break;
  667                 default:
  668                         break;
  669                 }
  670         }
  672         return (error);
  673 }
  675 /*
  676  * Allocate a jumbo buffer.
  677  */
  678 void *
ti_jalloc(struct ti_softc *sc)
  680 {
  681         struct ti_jpool_entry   *entry;
entry = SLIST_FIRST(&sc->ti_jfree_listhead);
  685         if (entry == NULL)
  686                 return (NULL);
SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries);
SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries);
sc->ti_cdata.ti_jslots[entry->slot].ti_inuse = 1;
  691         return (sc->ti_cdata.ti_jslots[entry->slot].ti_buf);
  692 }
  694 /*
  695  * Release a jumbo buffer.
  696  */
  697 void
ti_jfree(caddr_t buf, u_int size, void *arg)
  699 {
  700         struct ti_softc         *sc;
  701         int                     i;
  702         struct ti_jpool_entry   *entry;
  704         /* Extract the softc struct pointer. */
sc = (struct ti_softc *)arg;
  707         if (sc == NULL)
panic("ti_jfree: can't find softc pointer!");
  710         /* calculate the slot this buffer belongs to */
i = ((vaddr_t)buf - (vaddr_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
  713         if ((i < 0) || (i >= TI_JSLOTS))
panic("ti_jfree: asked to free buffer that we don't manage!");
  715         else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0)
panic("ti_jfree: buffer already free!");
sc->ti_cdata.ti_jslots[i].ti_inuse--;
  719         if(sc->ti_cdata.ti_jslots[i].ti_inuse == 0) {
entry = SLIST_FIRST(&sc->ti_jinuse_listhead);
  721                 if (entry == NULL)
panic("ti_jfree: buffer not in use!");
entry->slot = i;
SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries);
SLIST_INSERT_HEAD(&sc->ti_jfree_listhead,
entry, jpool_entries);
  727         }
  728 }
  730 /*
  731  * Intialize a standard receive ring descriptor.
  732  */
  733 int
ti_newbuf_std(struct ti_softc *sc, int i, struct mbuf *m,
bus_dmamap_t dmamap)
  736 {
  737         struct mbuf             *m_new = NULL;
  738         struct ti_rx_desc       *r;
  740         if (dmamap == NULL) {
  741                 /* if (m) panic() */
  743                 if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, MCLBYTES,
  744                                       0, BUS_DMA_NOWAIT, &dmamap)) {
printf("%s: can't create recv map\n",
sc->sc_dv.dv_xname);
  747                         return (ENOMEM);
  748                 }
  749         } else if (m == NULL)
bus_dmamap_unload(sc->sc_dmatag, dmamap);
sc->ti_cdata.ti_rx_std_map[i] = dmamap;
  754         if (m == NULL) {
MGETHDR(m_new, M_DONTWAIT, MT_DATA);
  756                 if (m_new == NULL)
  757                         return (ENOBUFS);
MCLGET(m_new, M_DONTWAIT);
  760                 if (!(m_new->m_flags & M_EXT)) {
m_freem(m_new);
  762                         return (ENOBUFS);
  763                 }
m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
m_adj(m_new, ETHER_ALIGN);
  768                 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m_new,
BUS_DMA_NOWAIT))
  770                         return (ENOBUFS);
  772         } else {
  773                 /*
  774                  * We're re-using a previously allocated mbuf;
  775                  * be sure to re-init pointers and lengths to
  776                  * default values.
  777                  */
m_new = m;
m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
m_new->m_data = m_new->m_ext.ext_buf;
m_adj(m_new, ETHER_ALIGN);
  782         }
sc->ti_cdata.ti_rx_std_chain[i] = m_new;
r = &sc->ti_rdata->ti_rx_std_ring[i];
TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr;
r->ti_type = TI_BDTYPE_RECV_BD;
r->ti_flags = TI_BDFLAG_IP_CKSUM;
r->ti_len = dmamap->dm_segs[0].ds_len;
r->ti_idx = i;
  792         if ((dmamap->dm_segs[0].ds_addr & ~(MCLBYTES - 1)) !=
  793             ((dmamap->dm_segs[0].ds_addr + dmamap->dm_segs[0].ds_len - 1) & 
  794              ~(MCLBYTES - 1)))
panic("%s: overwritten!!!", sc->sc_dv.dv_xname);
  797         return (0);
  798 }
  800 /*
  801  * Intialize a mini receive ring descriptor. This only applies to
  802  * the Tigon 2.
  803  */
  804 int
ti_newbuf_mini(struct ti_softc *sc, int i, struct mbuf *m,
bus_dmamap_t dmamap)
  807 {
  808         struct mbuf             *m_new = NULL;
  809         struct ti_rx_desc       *r;
  811         if (dmamap == NULL) {
  812                 /* if (m) panic() */
  814                 if (bus_dmamap_create(sc->sc_dmatag, MHLEN, 1, MHLEN,
  815                                       0, BUS_DMA_NOWAIT, &dmamap)) {
printf("%s: can't create recv map\n",
sc->sc_dv.dv_xname);
  818                         return (ENOMEM);
  819                 }
  820         } else if (m == NULL)
bus_dmamap_unload(sc->sc_dmatag, dmamap);
sc->ti_cdata.ti_rx_mini_map[i] = dmamap;
  825         if (m == NULL) {
MGETHDR(m_new, M_DONTWAIT, MT_DATA);
  827                 if (m_new == NULL)
  828                         return (ENOBUFS);
m_new->m_len = m_new->m_pkthdr.len = MHLEN;
m_adj(m_new, ETHER_ALIGN);
  832                 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m_new,
BUS_DMA_NOWAIT))
  834                 return (ENOBUFS);
  836         } else {
  837                 /*
  838                  * We're re-using a previously allocated mbuf;
  839                  * be sure to re-init pointers and lengths to
  840                  * default values.
  841                  */
m_new = m;
m_new->m_data = m_new->m_pktdat;
m_new->m_len = m_new->m_pkthdr.len = MHLEN;
  845         }
r = &sc->ti_rdata->ti_rx_mini_ring[i];
sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr;
r->ti_type = TI_BDTYPE_RECV_BD;
r->ti_flags = TI_BDFLAG_MINI_RING | TI_BDFLAG_IP_CKSUM;
r->ti_len = dmamap->dm_segs[0].ds_len;
r->ti_idx = i;
  855         return (0);
  856 }
  858 /*
  859  * Initialize a jumbo receive ring descriptor. This allocates
  860  * a jumbo buffer from the pool managed internally by the driver.
  861  */
  862 int
ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *m)
  864 {
  865         struct mbuf             *m_new = NULL;
  866         struct ti_rx_desc       *r;
  868         if (m == NULL) {
caddr_t                 buf = NULL;
  871                 /* Allocate the mbuf. */
MGETHDR(m_new, M_DONTWAIT, MT_DATA);
  873                 if (m_new == NULL)
  874                         return (ENOBUFS);
  876                 /* Allocate the jumbo buffer */
buf = ti_jalloc(sc);
  878                 if (buf == NULL) {
m_freem(m_new);
  880                         return (ENOBUFS);
  881                 }
  883                 /* Attach the buffer to the mbuf. */
m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN;
MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, 0, ti_jfree, sc);
  886         } else {
  887                 /*
  888                  * We're re-using a previously allocated mbuf;
  889                  * be sure to re-init pointers and lengths to
  890                  * default values.
  891                  */
m_new = m;
m_new->m_data = m_new->m_ext.ext_buf;
m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
  895         }
m_adj(m_new, ETHER_ALIGN);
  898         /* Set up the descriptor. */
r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
TI_HOSTADDR(r->ti_addr) = TI_JUMBO_DMA_ADDR(sc, m_new);
r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
r->ti_flags = TI_BDFLAG_JUMBO_RING | TI_BDFLAG_IP_CKSUM;
r->ti_len = m_new->m_len;
r->ti_idx = i;
  907         return (0);
  908 }
  910 /*
  911  * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
  912  * that's 1MB of memory, which is a lot. For now, we fill only the first
  913  * 256 ring entries and hope that our CPU is fast enough to keep up with
  914  * the NIC.
  915  */
  916 int
ti_init_rx_ring_std(struct ti_softc *sc)
  918 {
  919         int             i;
  920         struct ti_cmd_desc      cmd;
  922         for (i = 0; i < TI_SSLOTS; i++) {
  923                 if (ti_newbuf_std(sc, i, NULL, 0) == ENOBUFS)
  924                         return (ENOBUFS);
  925         }
TI_UPDATE_STDPROD(sc, i - 1);
sc->ti_std = i - 1;
  930         return (0);
  931 }
  933 void
ti_free_rx_ring_std(struct ti_softc *sc)
  935 {
  936         int             i;
  938         for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
  939                 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
sc->ti_cdata.ti_rx_std_chain[i] = NULL;
bus_dmamap_destroy(sc->sc_dmatag,
sc->ti_cdata.ti_rx_std_map[i]);
sc->ti_cdata.ti_rx_std_map[i] = 0;
  945                 }
bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i],
  947                     sizeof(struct ti_rx_desc));
  948         }
  949 }
  951 int
ti_init_rx_ring_jumbo(struct ti_softc *sc)
  953 {
  954         int             i;
  955         struct ti_cmd_desc      cmd;
  957         for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
  958                 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
  959                         return (ENOBUFS);
  960         };
TI_UPDATE_JUMBOPROD(sc, i - 1);
sc->ti_jumbo = i - 1;
  965         return (0);
  966 }
  968 void
ti_free_rx_ring_jumbo(struct ti_softc *sc)
  970 {
  971         int             i;
  973         for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
  974                 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
  977                 }
bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i],
  979                     sizeof(struct ti_rx_desc));
  980         }
  981 }
  983 int
ti_init_rx_ring_mini(struct ti_softc *sc)
  985 {
  986         int             i;
  988         for (i = 0; i < TI_MSLOTS; i++) {
  989                 if (ti_newbuf_mini(sc, i, NULL, 0) == ENOBUFS)
  990                         return (ENOBUFS);
  991         };
TI_UPDATE_MINIPROD(sc, i - 1);
sc->ti_mini = i - 1;
  996         return (0);
  997 }
  999 void
ti_free_rx_ring_mini(struct ti_softc *sc)
 1001 {
 1002         int             i;
 1004         for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
 1005                 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
bus_dmamap_destroy(sc->sc_dmatag,
sc->ti_cdata.ti_rx_mini_map[i]);
sc->ti_cdata.ti_rx_mini_map[i] = 0;
 1011                 }
bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i],
 1013                     sizeof(struct ti_rx_desc));
 1014         }
 1015 }
 1017 void
ti_free_tx_ring(struct ti_softc *sc)
 1019 {
 1020         int             i;
 1021         struct ti_txmap_entry *entry;
 1023         if (sc->ti_rdata->ti_tx_ring == NULL)
 1024                 return;
 1026         for (i = 0; i < TI_TX_RING_CNT; i++) {
 1027                 if (sc->ti_cdata.ti_tx_chain[i] != NULL) {
m_freem(sc->ti_cdata.ti_tx_chain[i]);
sc->ti_cdata.ti_tx_chain[i] = NULL;
SLIST_INSERT_HEAD(&sc->ti_tx_map_listhead,
sc->ti_cdata.ti_tx_map[i], link);
sc->ti_cdata.ti_tx_map[i] = 0;
 1033                 }
bzero((char *)&sc->ti_rdata->ti_tx_ring[i],
 1035                     sizeof(struct ti_tx_desc));
 1036         }
 1038         while ((entry = SLIST_FIRST(&sc->ti_tx_map_listhead))) {
SLIST_REMOVE_HEAD(&sc->ti_tx_map_listhead, link);
bus_dmamap_destroy(sc->sc_dmatag, entry->dmamap);
free(entry, M_DEVBUF);
 1042         }
 1043 }
 1045 int
ti_init_tx_ring(struct ti_softc *sc)
 1047 {
 1048         int i;
bus_dmamap_t dmamap;
 1050         struct ti_txmap_entry *entry;
sc->ti_txcnt = 0;
sc->ti_tx_saved_considx = 0;
sc->ti_tx_saved_prodidx = 0;
CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
SLIST_INIT(&sc->ti_tx_map_listhead);
 1058         for (i = 0; i < TI_TX_RING_CNT; i++) {
 1059                 if (bus_dmamap_create(sc->sc_dmatag, TI_JUMBO_FRAMELEN,
TI_NTXSEG, MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap))
 1061                         return (ENOBUFS);
entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT);
 1064                 if (!entry) {
bus_dmamap_destroy(sc->sc_dmatag, dmamap);
 1066                         return (ENOBUFS);
 1067                 }
entry->dmamap = dmamap;
SLIST_INSERT_HEAD(&sc->ti_tx_map_listhead, entry, link);
 1070         }
 1072         return (0);
 1073 }
 1075 /*
 1076  * The Tigon 2 firmware has a new way to add/delete multicast addresses,
 1077  * but we have to support the old way too so that Tigon 1 cards will
 1078  * work.
 1079  */
 1080 void
ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr)
 1082 {
 1083         struct ti_cmd_desc      cmd;
u_int16_t               *m;
u_int32_t               ext[2] = {0, 0};
m = (u_int16_t *)&addr->ether_addr_octet[0];
 1089         switch(sc->ti_hwrev) {
 1090         case TI_HWREV_TIGON:
CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
 1094                 break;
 1095         case TI_HWREV_TIGON_II:
ext[0] = htons(m[0]);
ext[1] = (htons(m[1]) << 16) | htons(m[2]);
TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
 1099                 break;
 1100         default:
printf("%s: unknown hwrev\n", sc->sc_dv.dv_xname);
 1102                 break;
 1103         }
 1104 }
 1106 void
ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr)
 1108 {
 1109         struct ti_cmd_desc      cmd;
u_int16_t               *m;
u_int32_t               ext[2] = {0, 0};
m = (u_int16_t *)&addr->ether_addr_octet[0];
 1115         switch(sc->ti_hwrev) {
 1116         case TI_HWREV_TIGON:
CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
 1120                 break;
 1121         case TI_HWREV_TIGON_II:
ext[0] = htons(m[0]);
ext[1] = (htons(m[1]) << 16) | htons(m[2]);
TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
 1125                 break;
 1126         default:
printf("%s: unknown hwrev\n", sc->sc_dv.dv_xname);
 1128                 break;
 1129         }
 1130 }
 1132 /*
 1133  * Configure the Tigon's multicast address filter.
 1134  *
 1135  * The actual multicast table management is a bit of a pain, thanks to
 1136  * slight brain damage on the part of both Alteon and us. With our
 1137  * multicast code, we are only alerted when the multicast address table
 1138  * changes and at that point we only have the current list of addresses:
 1139  * we only know the current state, not the previous state, so we don't
 1140  * actually know what addresses were removed or added. The firmware has
 1141  * state, but we can't get our grubby mits on it, and there is no 'delete
 1142  * all multicast addresses' command. Hence, we have to maintain our own
 1143  * state so we know what addresses have been programmed into the NIC at
 1144  * any given time.
 1145  */
 1146 void
ti_setmulti(struct ti_softc *sc)
 1148 {
 1149         struct ifnet            *ifp;
 1150         struct arpcom           *ac = &sc->arpcom;
 1151         struct ether_multi      *enm;
 1152         struct ether_multistep  step;
 1153         struct ti_cmd_desc      cmd;
 1154         struct ti_mc_entry      *mc;
u_int32_t               intrs;
ifp = &sc->arpcom.ac_if;
allmulti:
 1160         if (ifp->if_flags & IFF_ALLMULTI) {
TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
 1162                 return;
 1163         } else {
TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
 1165         }
 1167         /* Disable interrupts. */
intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
 1171         /* First, zot all the existing filters. */
 1172         while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) {
mc = SLIST_FIRST(&sc->ti_mc_listhead);
ti_del_mcast(sc, &mc->mc_addr);
SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
free(mc, M_DEVBUF);
 1177         }
 1179         /* Now program new ones. */
ETHER_FIRST_MULTI(step, ac, enm);
 1181         while (enm != NULL) {
 1182                 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
 1183                         /* Re-enable interrupts. */
CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
ifp->if_flags |= IFF_ALLMULTI;
 1187                         goto allmulti;
 1188                 }
mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT);
 1190                 if (mc == NULL)
panic("ti_setmulti");
bcopy(enm->enm_addrlo, (char *)&mc->mc_addr, ETHER_ADDR_LEN);
SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
ti_add_mcast(sc, &mc->mc_addr);
ETHER_NEXT_MULTI(step, enm);
 1196         }
 1198         /* Re-enable interrupts. */
CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
 1200 }
 1202 /*
 1203  * Check to see if the BIOS has configured us for a 64 bit slot when
 1204  * we aren't actually in one. If we detect this condition, we can work
 1205  * around it on the Tigon 2 by setting a bit in the PCI state register,
 1206  * but for the Tigon 1 we must give up and abort the interface attach.
 1207  */
 1208 int
ti_64bitslot_war(struct ti_softc *sc)
 1210 {
 1211         if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
CSR_WRITE_4(sc, 0x600, 0);
CSR_WRITE_4(sc, 0x604, 0);
CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
 1215                 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
 1216                         if (sc->ti_hwrev == TI_HWREV_TIGON)
 1217                                 return (EINVAL);
 1218                         else {
TI_SETBIT(sc, TI_PCI_STATE,
TI_PCISTATE_32BIT_BUS);
 1221                                 return (0);
 1222                         }
 1223                 }
 1224         }
 1226         return (0);
 1227 }
 1229 /*
 1230  * Do endian, PCI and DMA initialization. Also check the on-board ROM
 1231  * self-test results.
 1232  */
 1233 int
ti_chipinit(struct ti_softc *sc)
 1235 {
u_int32_t               cacheline;
u_int32_t               pci_writemax = 0;
u_int32_t               chip_rev;
 1240         /* Initialize link to down state. */
sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
 1243         /* Set endianness before we access any non-PCI registers. */
CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
 1247         /* Check the ROM failed bit to see if self-tests passed. */
 1248         if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
printf("%s: board self-diagnostics failed!\n",
sc->sc_dv.dv_xname);
 1251                 return (ENODEV);
 1252         }
 1254         /* Halt the CPU. */
TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
 1257         /* Figure out the hardware revision. */
chip_rev = CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK;
 1259         switch(chip_rev) {
 1260         case TI_REV_TIGON_I:
sc->ti_hwrev = TI_HWREV_TIGON;
 1262                 break;
 1263         case TI_REV_TIGON_II:
sc->ti_hwrev = TI_HWREV_TIGON_II;
 1265                 break;
 1266         default:
printf("\n");
printf("%s: unsupported chip revision: %x\n",
chip_rev, sc->sc_dv.dv_xname);
 1270                 return (ENODEV);
 1271         }
 1273         /* Do special setup for Tigon 2. */
 1274         if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
 1278         }
 1280         /* Set up the PCI state register. */
CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
 1282         if (sc->ti_hwrev == TI_HWREV_TIGON_II)
TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
 1285         /* Clear the read/write max DMA parameters. */
TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
TI_PCISTATE_READ_MAXDMA));
 1289         /* Get cache line size. */
cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
 1292         /*
 1293          * If the system has set enabled the PCI memory write
 1294          * and invalidate command in the command register, set
 1295          * the write max parameter accordingly. This is necessary
 1296          * to use MWI with the Tigon 2.
 1297          */
 1298         if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCI_COMMAND_INVALIDATE_ENABLE) {
 1299                 switch(cacheline) {
 1300                 case 1:
 1301                 case 4:
 1302                 case 8:
 1303                 case 16:
 1304                 case 32:
 1305                 case 64:
 1306                         break;
 1307                 default:
 1308                 /* Disable PCI memory write and invalidate. */
CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
TI_PCI_CMDSTAT) & ~PCI_COMMAND_INVALIDATE_ENABLE);
 1311                         break;
 1312                 }
 1313         }
 1315 #ifdef __brokenalpha__
 1316         /*
 1317          * From the Alteon sample driver:
 1318          * Must insure that we do not cross an 8K (bytes) boundary
 1319          * for DMA reads.  Our highest limit is 1K bytes.  This is a
 1320          * restriction on some ALPHA platforms with early revision
 1321          * 21174 PCI chipsets, such as the AlphaPC 164lx
 1322          */
TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024);
 1324 #else
TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
 1326 #endif
 1328         /* This sets the min dma param all the way up (0xff). */
TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
 1331         /* Configure DMA variables. */
CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_DMA_SWAP_OPTIONS |
TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
TI_OPMODE_DONT_FRAG_JUMBO);
 1336         /* Recommended settings from Tigon manual. */
CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
 1340         if (ti_64bitslot_war(sc)) {
printf("%s: bios thinks we're in a 64 bit slot, "
 1342                     "but we aren't", sc->sc_dv.dv_xname);
 1343                 return (EINVAL);
 1344         }
 1346         return (0);
 1347 }
 1349 /*
 1350  * Initialize the general information block and firmware, and
 1351  * start the CPU(s) running.
 1352  */
 1353 int
ti_gibinit(struct ti_softc *sc)
 1355 {
 1356         struct ti_rcb           *rcb;
 1357         int                     i;
 1358         struct ifnet            *ifp;
ifp = &sc->arpcom.ac_if;
 1362         /* Disable interrupts for now. */
CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
 1365         /*
 1366          * Tell the chip where to find the general information block.
 1367          * While this struct could go into >4GB memory, we allocate it in a
 1368          * single slab with the other descriptors, and those don't seem to
 1369          * support being located in a 64-bit region.
 1370          */
CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
CSR_WRITE_4(sc, TI_GCR_GENINFO_LO,
TI_RING_DMA_ADDR(sc, ti_info) & 0xffffffff);
 1375         /* Load the firmware into SRAM. */
ti_loadfw(sc);
 1378         /* Set up the contents of the general info and ring control blocks. */
 1380         /* Set up the event ring and producer pointer. */
rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
TI_HOSTADDR(rcb->ti_hostaddr) = TI_RING_DMA_ADDR(sc, ti_event_ring);
rcb->ti_flags = 0;
TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) =
TI_RING_DMA_ADDR(sc, ti_ev_prodidx_r);
sc->ti_ev_prodidx.ti_idx = 0;
CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
sc->ti_ev_saved_considx = 0;
 1391         /* Set up the command ring and producer mailbox. */
rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING);
rcb->ti_flags = 0;
rcb->ti_max_len = 0;
 1397         for (i = 0; i < TI_CMD_RING_CNT; i++) {
CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
 1399         }
CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
sc->ti_cmd_saved_prodidx = 0;
 1404         /*
 1405          * Assign the address of the stats refresh buffer.
 1406          * We re-use the current stats buffer for this to
 1407          * conserve memory.
 1408          */
TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) =
TI_RING_DMA_ADDR(sc, ti_info.ti_stats);
 1412         /* Set up the standard receive ring. */
rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
TI_HOSTADDR(rcb->ti_hostaddr) =
TI_RING_DMA_ADDR(sc, ti_rx_std_ring);
rcb->ti_max_len = ETHER_MAX_LEN;
rcb->ti_flags = 0;
rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
 1420         /* Set up the jumbo receive ring. */
rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
TI_HOSTADDR(rcb->ti_hostaddr) = TI_RING_DMA_ADDR(sc, ti_rx_jumbo_ring);
rcb->ti_max_len = TI_JUMBO_FRAMELEN;
rcb->ti_flags = 0;
rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
 1427         /*
 1428          * Set up the mini ring. Only activated on the
 1429          * Tigon 2 but the slot in the config block is
 1430          * still there on the Tigon 1.
 1431          */
rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
TI_HOSTADDR(rcb->ti_hostaddr) = TI_RING_DMA_ADDR(sc, ti_rx_mini_ring);
rcb->ti_max_len = MHLEN - ETHER_ALIGN;
 1435         if (sc->ti_hwrev == TI_HWREV_TIGON)
rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
 1437         else
rcb->ti_flags = 0;
rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
 1441         /*
 1442          * Set up the receive return ring.
 1443          */
rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
TI_HOSTADDR(rcb->ti_hostaddr) = TI_RING_DMA_ADDR(sc,ti_rx_return_ring);
rcb->ti_flags = 0;
rcb->ti_max_len = TI_RETURN_RING_CNT;
TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) =
TI_RING_DMA_ADDR(sc, ti_return_prodidx_r);
 1451         /*
 1452          * Set up the tx ring. Note: for the Tigon 2, we have the option
 1453          * of putting the transmit ring in the host's address space and
 1454          * letting the chip DMA it instead of leaving the ring in the NIC's
 1455          * memory and accessing it through the shared memory region. We
 1456          * do this for the Tigon 2, but it doesn't work on the Tigon 1,
 1457          * so we have to revert to the shared memory scheme if we detect
 1458          * a Tigon 1 chip.
 1459          */
CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
bzero((char *)sc->ti_rdata->ti_tx_ring,
TI_TX_RING_CNT * sizeof(struct ti_tx_desc));
rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
 1464         if (sc->ti_hwrev == TI_HWREV_TIGON)
rcb->ti_flags = 0;
 1466         else
rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
 1469 #if NVLAN > 0
 1470         if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)
rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
 1472 #endif
rcb->ti_max_len = TI_TX_RING_CNT;
 1474         if (sc->ti_hwrev == TI_HWREV_TIGON)
TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE;
 1476         else
TI_HOSTADDR(rcb->ti_hostaddr) =
TI_RING_DMA_ADDR(sc, ti_tx_ring);
TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) =
TI_RING_DMA_ADDR(sc, ti_tx_considx_r);
TI_RING_DMASYNC(sc, ti_info, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
 1484         /* Set up tuneables */
CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, (sc->ti_rx_coal_ticks / 10));
CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
 1492         /* Turn interrupts on. */
CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
 1496         /* Start CPU. */
TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
 1499         return (0);
 1500 }
 1502 /*
 1503  * Probe for a Tigon chip. Check the PCI vendor and device IDs
 1504  * against our list and return its name if we find a match.
 1505  */
 1506 int
ti_probe(struct device *parent, void *match, void *aux)
 1508 {
 1509         return (pci_matchbyid((struct pci_attach_args *)aux, ti_devices,
 1510             sizeof(ti_devices)/sizeof(ti_devices[0])));
 1511 }
 1513 void
ti_attach(struct device *parent, struct device *self, void *aux)
 1515 {
 1516         struct ti_softc *sc = (struct ti_softc *)self;
 1517         struct pci_attach_args *pa = aux;
pci_chipset_tag_t pc = pa->pa_pc;
pci_intr_handle_t ih;
 1520         const char *intrstr = NULL;
bus_size_t size;
bus_dma_segment_t seg;
 1523         int rseg;
 1524         struct ifnet *ifp;
caddr_t kva;
 1527         /*
 1528          * Map control/status registers.
 1529          */
 1531         if (pci_mapreg_map(pa, TI_PCI_LOMEM,
PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
 1533             &sc->ti_btag, &sc->ti_bhandle, NULL, &size, 0)) {
printf(": can't map mem space\n");
 1535                 return;
 1536         }
 1538         if (pci_intr_map(pa, &ih)) {
printf(": couldn't map interrupt\n");
 1540                 goto fail_1;
 1541         }
intrstr = pci_intr_string(pc, ih);
sc->ti_intrhand = pci_intr_establish(pc, ih, IPL_NET, ti_intr, sc,
self->dv_xname);
 1545         if (sc->ti_intrhand == NULL) {
printf(": couldn't establish interrupt");
 1547                 if (intrstr != NULL)
printf(" at %s", intrstr);
printf("\n");
 1550                 goto fail_1;
 1551         }
 1553         if (ti_chipinit(sc)) {
printf("%s: chip initialization failed\n", sc->sc_dv.dv_xname);
 1555                 goto fail_2;
 1556         }
 1558         /* Zero out the NIC's on-board SRAM. */
ti_mem_set(sc, 0x2000, 0x100000 - 0x2000);
 1561         /* Init again -- zeroing memory may have clobbered some registers. */
 1562         if (ti_chipinit(sc)) {
printf("%s: chip initialization failed\n", sc->sc_dv.dv_xname);
 1564                 goto fail_2;
 1565         }
 1567         /*
 1568          * Get station address from the EEPROM. Note: the manual states
 1569          * that the MAC address is at offset 0x8c, however the data is
 1570          * stored as two longwords (since that's how it's loaded into
 1571          * the NIC). This means the MAC address is actually preceded
 1572          * by two zero bytes. We need to skip over those.
 1573          */
 1574         if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
printf("%s: failed to read station address\n",
sc->sc_dv.dv_xname);
free(sc, M_DEVBUF);
 1579                 goto fail_2;
 1580         }
 1582         /*
 1583          * A Tigon chip was detected. Inform the world.
 1584          */
printf(": %s, address %s\n", intrstr,
ether_sprintf(sc->arpcom.ac_enaddr));
 1588         /* Allocate the general information block and ring buffers. */
sc->sc_dmatag = pa->pa_dmat;
 1590         if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct ti_ring_data),
PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
printf("%s: can't alloc rx buffers\n", sc->sc_dv.dv_xname);
 1593                 goto fail_2;
 1594         }
 1595         if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg,
 1596             sizeof(struct ti_ring_data), &kva, BUS_DMA_NOWAIT)) {
printf("%s: can't map dma buffers (%d bytes)\n",
sc->sc_dv.dv_xname, sizeof(struct ti_ring_data));
 1599                 goto fail_3;
 1600         }
 1601         if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct ti_ring_data), 1,
 1602             sizeof(struct ti_ring_data), 0, BUS_DMA_NOWAIT,
 1603             &sc->ti_ring_map)) {
printf("%s: can't create dma map\n", sc->sc_dv.dv_xname);
 1605                 goto fail_4;
 1606         }
 1607         if (bus_dmamap_load(sc->sc_dmatag, sc->ti_ring_map, kva,
 1608             sizeof(struct ti_ring_data), NULL, BUS_DMA_NOWAIT)) {
 1609                 goto fail_5;
 1610         }
sc->ti_rdata = (struct ti_ring_data *)kva;
bzero(sc->ti_rdata, sizeof(struct ti_ring_data));
 1614         /* Try to allocate memory for jumbo buffers. */
 1615         if (ti_alloc_jumbo_mem(sc)) {
printf("%s: jumbo buffer allocation failed\n",
sc->sc_dv.dv_xname);
 1618                 goto fail_5;
 1619         }
 1621         /*
 1622          * We really need a better way to tell a 1000baseTX card
 1623          * from a 1000baseSX one, since in theory there could be
 1624          * OEMed 1000baseTX cards from lame vendors who aren't
 1625          * clever enough to change the PCI ID. For the moment
 1626          * though, the AceNIC is the only copper card available.
 1627          */
 1628         if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALTEON &&
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALTEON_ACENICT)
sc->ti_copper = 1;
 1631         /* Ok, it's not the only copper card available */
 1632         if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NETGEAR &&
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NETGEAR_GA620T)
sc->ti_copper = 1;
 1636         /* Set default tuneable values. */
sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000;
sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
sc->ti_rx_max_coal_bds = 64;
sc->ti_tx_max_coal_bds = 128;
sc->ti_tx_buf_ratio = 21;
 1644         /* Set up ifnet structure */
ifp = &sc->arpcom.ac_if;
ifp->if_softc = sc;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_ioctl = ti_ioctl;
ifp->if_start = ti_start;
ifp->if_watchdog = ti_watchdog;
ifp->if_hardmtu = TI_JUMBO_FRAMELEN - ETHER_HDR_LEN;
IFQ_SET_MAXLEN(&ifp->if_snd, TI_TX_RING_CNT - 1);
IFQ_SET_READY(&ifp->if_snd);
bcopy(sc->sc_dv.dv_xname, ifp->if_xname, IFNAMSIZ);
ifp->if_capabilities = IFCAP_VLAN_MTU;
 1658 #if NVLAN > 0
ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
 1660 #endif
 1662         /* Set up ifmedia support. */
ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
 1664         if (sc->ti_copper) {
 1665                 /*
 1666                  * Copper cards allow manual 10/100 mode selection,
 1667                  * but not manual 1000baseTX mode selection. Why?
 1668                  * Because currently there's no way to specify the
 1669                  * master/slave setting through the firmware interface,
 1670                  * so Alteon decided to just bag it and handle it
 1671                  * via autonegotiation.
 1672                  */
ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
ifmedia_add(&sc->ifmedia,
IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
ifmedia_add(&sc->ifmedia,
IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL);
ifmedia_add(&sc->ifmedia,
IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL);
 1682         } else {
 1683                 /* Fiber cards don't support 10/100 modes. */
ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
ifmedia_add(&sc->ifmedia,
IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
 1687         }
ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
 1691         /*
 1692          * Call MI attach routines.
 1693          */
if_attach(ifp);
ether_ifattach(ifp);
shutdownhook_establish(ti_shutdown, sc);
 1698         return;
fail_5:
bus_dmamap_destroy(sc->sc_dmatag, sc->ti_ring_map);
fail_4:
bus_dmamem_unmap(sc->sc_dmatag, kva,
 1705             sizeof(struct ti_ring_data));
fail_3:
bus_dmamem_free(sc->sc_dmatag, &seg, rseg);
fail_2:
pci_intr_disestablish(pc, sc->ti_intrhand);
fail_1:
bus_space_unmap(sc->ti_btag, sc->ti_bhandle, size);
 1715 }
 1717 /*
 1718  * Frame reception handling. This is called if there's a frame
 1719  * on the receive return list.
 1720  *
 1721  * Note: we have to be able to handle three possibilities here:
 1722  * 1) the frame is from the mini receive ring (can only happen)
 1723  *    on Tigon 2 boards)
 1724  * 2) the frame is from the jumbo receive ring
 1725  * 3) the frame is from the standard receive ring
 1726  */
 1728 void
ti_rxeof(struct ti_softc *sc)
 1730 {
 1731         struct ifnet            *ifp;
 1732         struct ti_cmd_desc      cmd;
ifp = &sc->arpcom.ac_if;
 1736         while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
 1737                 struct ti_rx_desc       *cur_rx;
u_int32_t               rxidx;
 1739                 struct mbuf             *m = NULL;
 1740                 int                     sumflags = 0;
bus_dmamap_t            dmamap;
cur_rx =
 1744                     &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
rxidx = cur_rx->ti_idx;
TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
 1748                 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
 1752                         if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
ifp->if_ierrors++;
ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
 1755                                 continue;
 1756                         }
 1757                         if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL)
 1758                             == ENOBUFS) {
 1759                                 struct mbuf             *m0;
m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
cur_rx->ti_len + ETHER_ALIGN, 0, ifp, NULL);
ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
 1763                                 if (m0 == NULL) {
ifp->if_ierrors++;
 1765                                         continue;
 1766                                 }
m_adj(m0, ETHER_ALIGN);
m = m0;
 1769                         }
 1770                 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
dmamap = sc->ti_cdata.ti_rx_mini_map[rxidx];
sc->ti_cdata.ti_rx_mini_map[rxidx] = 0;
 1776                         if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
ifp->if_ierrors++;
ti_newbuf_mini(sc, sc->ti_mini, m, dmamap);
 1779                                 continue;
 1780                         }
 1781                         if (ti_newbuf_mini(sc, sc->ti_mini, NULL, dmamap)
 1782                             == ENOBUFS) {
ifp->if_ierrors++;
ti_newbuf_mini(sc, sc->ti_mini, m, dmamap);
 1785                                 continue;
 1786                         }
 1787                 } else {
TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
m = sc->ti_cdata.ti_rx_std_chain[rxidx];
sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
dmamap = sc->ti_cdata.ti_rx_std_map[rxidx];
sc->ti_cdata.ti_rx_std_map[rxidx] = 0;
 1793                         if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
ifp->if_ierrors++;
ti_newbuf_std(sc, sc->ti_std, m, dmamap);
 1796                                 continue;
 1797                         }
 1798                         if (ti_newbuf_std(sc, sc->ti_std, NULL, dmamap)
 1799                             == ENOBUFS) {
ifp->if_ierrors++;
ti_newbuf_std(sc, sc->ti_std, m, dmamap);
 1802                                 continue;
 1803                         }
 1804                 }
 1806                 if (m == NULL)
panic("%s: couldn't get mbuf", sc->sc_dv.dv_xname);
m->m_pkthdr.len = m->m_len = cur_rx->ti_len;
ifp->if_ipackets++;
m->m_pkthdr.rcvif = ifp;
 1813 #if NBPFILTER > 0
 1814                 /*
 1815                  * Handle BPF listeners. Let the BPF user see the packet.
 1816                  */
 1817                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN);
 1819 #endif
 1821                 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
sumflags |= M_IPV4_CSUM_IN_OK;
m->m_pkthdr.csum_flags = sumflags;
sumflags = 0;
ether_input_mbuf(ifp, m);
 1827         }
 1829         /* Only necessary on the Tigon 1. */
 1830         if (sc->ti_hwrev == TI_HWREV_TIGON)
CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
sc->ti_rx_saved_considx);
TI_UPDATE_STDPROD(sc, sc->ti_std);
TI_UPDATE_MINIPROD(sc, sc->ti_mini);
TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
 1837 }
 1839 void
ti_txeof_tigon1(struct ti_softc *sc)
 1841 {
 1842         struct ifnet            *ifp;
 1843         struct ti_txmap_entry   *entry;
 1844         int                     active = 1;
ifp = &sc->arpcom.ac_if;
 1848         /*
 1849          * Go through our tx ring and free mbufs for those
 1850          * frames that have been sent.
 1851          */
 1852         while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) {
u_int32_t               idx = 0;
 1854                 struct ti_tx_desc       txdesc;
idx = sc->ti_tx_saved_considx;
ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc),
 1858                             sizeof(txdesc), (caddr_t)&txdesc);
 1860                 if (txdesc.ti_flags & TI_BDFLAG_END)
ifp->if_opackets++;
 1863                 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) {
m_freem(sc->ti_cdata.ti_tx_chain[idx]);
sc->ti_cdata.ti_tx_chain[idx] = NULL;
entry = sc->ti_cdata.ti_tx_map[idx];
bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0,
entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->sc_dmatag, entry->dmamap);
SLIST_INSERT_HEAD(&sc->ti_tx_map_listhead, entry,
link);
sc->ti_cdata.ti_tx_map[idx] = NULL;
 1876                 }
sc->ti_txcnt--;
TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT);
ifp->if_timer = 0;
active = 0;
 1882         }
 1884         if (!active)
ifp->if_flags &= ~IFF_OACTIVE;
 1886 }
 1888 void
ti_txeof_tigon2(struct ti_softc *sc)
 1890 {
 1891         struct ti_tx_desc       *cur_tx = NULL;
 1892         struct ifnet            *ifp;
 1893         struct ti_txmap_entry   *entry;
ifp = &sc->arpcom.ac_if;
 1897         /*
 1898          * Go through our tx ring and free mbufs for those
 1899          * frames that have been sent.
 1900          */
 1901         while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) {
u_int32_t               idx = 0;
idx = sc->ti_tx_saved_considx;
cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
 1907                 if (cur_tx->ti_flags & TI_BDFLAG_END)
ifp->if_opackets++;
 1909                 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) {
m_freem(sc->ti_cdata.ti_tx_chain[idx]);
sc->ti_cdata.ti_tx_chain[idx] = NULL;
entry = sc->ti_cdata.ti_tx_map[idx];
bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0,
entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->sc_dmatag, entry->dmamap);
SLIST_INSERT_HEAD(&sc->ti_tx_map_listhead, entry,
link);
sc->ti_cdata.ti_tx_map[idx] = NULL;
 1922                 }
sc->ti_txcnt--;
TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT);
ifp->if_timer = 0;
 1926         }
 1928         if (cur_tx != NULL)
ifp->if_flags &= ~IFF_OACTIVE;
 1930 }
 1932 int
ti_intr(void *xsc)
 1934 {
 1935         struct ti_softc         *sc;
 1936         struct ifnet            *ifp;
sc = xsc;
ifp = &sc->arpcom.ac_if;
 1941         /* XXX checking this register is expensive. */
 1942         /* Make sure this is really our interrupt. */
 1943         if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE))
 1944                 return (0);
 1946         /* Ack interrupt and stop others from occurring. */
CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
 1949         if (ifp->if_flags & IFF_RUNNING) {
 1950                 /* Check RX return ring producer/consumer */
ti_rxeof(sc);
 1953                 /* Check TX ring producer/consumer */
 1954                 if (sc->ti_hwrev == TI_HWREV_TIGON)
ti_txeof_tigon1(sc);
 1956                 else
ti_txeof_tigon2(sc);
 1958         }
ti_handle_events(sc);
 1962         /* Re-enable interrupts. */
CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
 1965         if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd))
ti_start(ifp);
 1968         return (1);
 1969 }
 1971 void
ti_stats_update(struct ti_softc *sc)
 1973 {
 1974         struct ifnet            *ifp;
 1975         struct ti_stats         *stats = &sc->ti_rdata->ti_info.ti_stats;
ifp = &sc->arpcom.ac_if;
TI_RING_DMASYNC(sc, ti_info.ti_stats, BUS_DMASYNC_POSTREAD);
ifp->if_collisions += stats->dot3StatsSingleCollisionFrames +
stats->dot3StatsMultipleCollisionFrames +
stats->dot3StatsExcessiveCollisions +
stats->dot3StatsLateCollisions -
ifp->if_collisions;
TI_RING_DMASYNC(sc, ti_info.ti_stats, BUS_DMASYNC_PREREAD);
 1988 }
 1990 /*
 1991  * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
 1992  * pointers to descriptors.
 1993  */
 1994 int
ti_encap_tigon1(struct ti_softc *sc, struct mbuf *m_head, u_int32_t *txidx)
 1996 {
u_int32_t               frag, cur, cnt = 0;
 1998         struct ti_txmap_entry   *entry;
bus_dmamap_t            txmap;
 2000         struct ti_tx_desc       txdesc;
 2001         int                     i = 0;
 2002 #if NVLAN > 0
 2003         struct ifvlan           *ifv = NULL;
 2005         if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
m_head->m_pkthdr.rcvif != NULL)
ifv = m_head->m_pkthdr.rcvif->if_softc;
 2008 #endif
entry = SLIST_FIRST(&sc->ti_tx_map_listhead);
 2011         if (entry == NULL)
 2012                 return (ENOBUFS);
txmap = entry->dmamap;
cur = frag = *txidx;
 2017         /*
 2018          * Start packing the mbufs in this chain into
 2019          * the fragment pointers. Stop when we run out
 2020          * of fragments or hit the end of the mbuf chain.
 2021          */
 2022         if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head,
BUS_DMA_NOWAIT))
 2024                 return (ENOBUFS);
 2026         for (i = 0; i < txmap->dm_nsegs; i++) {
 2027                 if (sc->ti_cdata.ti_tx_chain[frag] != NULL)
 2028                         break;
memset(&txdesc, 0, sizeof(txdesc));
TI_HOSTADDR(txdesc.ti_addr) = txmap->dm_segs[i].ds_addr;
txdesc.ti_len = txmap->dm_segs[i].ds_len & 0xffff;
txdesc.ti_flags = 0;
 2036 #if NVLAN > 0
 2037                 if (ifv != NULL) {
txdesc.ti_flags |= TI_BDFLAG_VLAN_TAG;
txdesc.ti_vlan_tag = ifv->ifv_tag;
 2040                 }
 2041 #endif
ti_mem_write(sc, TI_TX_RING_BASE + frag * sizeof(txdesc),
 2044                              sizeof(txdesc), (caddr_t)&txdesc);
 2046                 /*
 2047                  * Sanity check: avoid coming within 16 descriptors
 2048                  * of the end of the ring.
 2049                  */
 2050                 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16)
 2051                         return (ENOBUFS);
cur = frag;
TI_INC(frag, TI_TX_RING_CNT);
cnt++;
 2055         }
 2057         if (frag == sc->ti_tx_saved_considx)
 2058                 return (ENOBUFS);
txdesc.ti_flags |= TI_BDFLAG_END;
ti_mem_write(sc, TI_TX_RING_BASE + cur * sizeof(txdesc),
 2062                      sizeof(txdesc), (caddr_t)&txdesc);
bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize,
BUS_DMASYNC_PREWRITE);
sc->ti_cdata.ti_tx_chain[cur] = m_head;
SLIST_REMOVE_HEAD(&sc->ti_tx_map_listhead, link);
sc->ti_cdata.ti_tx_map[cur] = entry;
sc->ti_txcnt += cnt;
 2072         *txidx = frag;
 2074         return (0);
 2075 }
 2077 /*
 2078  * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
 2079  * pointers to descriptors.
 2080  */
 2081 int
ti_encap_tigon2(struct ti_softc *sc, struct mbuf *m_head, u_int32_t *txidx)
 2083 {
 2084         struct ti_tx_desc       *f = NULL;
u_int32_t               frag, cur, cnt = 0;
 2086         struct ti_txmap_entry   *entry;
bus_dmamap_t            txmap;
 2088         int                     i = 0;
 2089 #if NVLAN > 0
 2090         struct ifvlan           *ifv = NULL;
 2092         if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
m_head->m_pkthdr.rcvif != NULL)
ifv = m_head->m_pkthdr.rcvif->if_softc;
 2095 #endif
entry = SLIST_FIRST(&sc->ti_tx_map_listhead);
 2098         if (entry == NULL)
 2099                 return (ENOBUFS);
txmap = entry->dmamap;
cur = frag = *txidx;
 2104         /*
 2105          * Start packing the mbufs in this chain into
 2106          * the fragment pointers. Stop when we run out
 2107          * of fragments or hit the end of the mbuf chain.
 2108          */
 2109         if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head,
BUS_DMA_NOWAIT))
 2111                 return (ENOBUFS);
 2113         for (i = 0; i < txmap->dm_nsegs; i++) {
f = &sc->ti_rdata->ti_tx_ring[frag];
 2116                 if (sc->ti_cdata.ti_tx_chain[frag] != NULL)
 2117                         break;
TI_HOSTADDR(f->ti_addr) = txmap->dm_segs[i].ds_addr;
f->ti_len = txmap->dm_segs[i].ds_len & 0xffff;
f->ti_flags = 0;
 2122 #if NVLAN > 0
 2123                 if (ifv != NULL) {
f->ti_flags |= TI_BDFLAG_VLAN_TAG;
f->ti_vlan_tag = ifv->ifv_tag;
 2126                 } else {
f->ti_vlan_tag = 0;
 2128                 }
 2129 #endif
 2130                 /*
 2131                  * Sanity check: avoid coming within 16 descriptors
 2132                  * of the end of the ring.
 2133                  */
 2134                 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16)
 2135                         return(ENOBUFS);
cur = frag;
TI_INC(frag, TI_TX_RING_CNT);
cnt++;
 2139         }
 2141         if (frag == sc->ti_tx_saved_considx)
 2142                 return(ENOBUFS);
sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END;
bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize,
BUS_DMASYNC_PREWRITE);
TI_RING_DMASYNC(sc, ti_tx_ring[cur], BUS_DMASYNC_POSTREAD);
sc->ti_cdata.ti_tx_chain[cur] = m_head;
SLIST_REMOVE_HEAD(&sc->ti_tx_map_listhead, link);
sc->ti_cdata.ti_tx_map[cur] = entry;
sc->ti_txcnt += cnt;
 2156         *txidx = frag;
 2158         return (0);
 2159 }
 2161 /*
 2162  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
 2163  * to the mbuf data regions directly in the transmit descriptors.
 2164  */
 2165 void
ti_start(struct ifnet *ifp)
 2167 {
 2168         struct ti_softc         *sc;
 2169         struct mbuf             *m_head = NULL;
u_int32_t               prodidx;
 2171         int                     pkts = 0, error;
sc = ifp->if_softc;
prodidx = sc->ti_tx_saved_prodidx;
 2177         while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) {
IFQ_POLL(&ifp->if_snd, m_head);
 2179                 if (m_head == NULL)
 2180                         break;
 2182                 /*
 2183                  * Pack the data into the transmit ring. If we
 2184                  * don't have room, set the OACTIVE flag and wait
 2185                  * for the NIC to drain the ring.
 2186                  */
 2187                 if (sc->ti_hwrev == TI_HWREV_TIGON)
error = ti_encap_tigon1(sc, m_head, &prodidx);
 2189                 else
error = ti_encap_tigon2(sc, m_head, &prodidx);
 2192                 if (error) {
ifp->if_flags |= IFF_OACTIVE;
 2194                         break;
 2195                 }
 2197                 /* now we are committed to transmit the packet */
IFQ_DEQUEUE(&ifp->if_snd, m_head);
pkts++;
 2201                 /*
 2202                  * If there's a BPF listener, bounce a copy of this frame
 2203                  * to him.
 2204                  */
 2205 #if NBPFILTER > 0
 2206                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT);
 2208 #endif
 2209         }
 2210         if (pkts == 0)
 2211                 return;
 2213         /* Transmit */
sc->ti_tx_saved_prodidx = prodidx;
CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx);
 2217         /*
 2218          * Set a timeout in case the chip goes out to lunch.
 2219          */
ifp->if_timer = 5;
 2221 }
 2223 void
ti_init(void *xsc)
 2225 {
 2226         struct ti_softc         *sc = xsc;
 2227         int                     s;
s = splnet();
 2231         /* Cancel pending I/O and flush buffers. */
ti_stop(sc);
 2234         /* Init the gen info block, ring control blocks and firmware. */
 2235         if (ti_gibinit(sc)) {
printf("%s: initialization failure\n", sc->sc_dv.dv_xname);
splx(s);
 2238                 return;
 2239         }
splx(s);
 2242 }
 2244 void
ti_init2(struct ti_softc *sc)
 2246 {
 2247         struct ti_cmd_desc      cmd;
 2248         struct ifnet            *ifp;
u_int16_t               *m;
 2250         struct ifmedia          *ifm;
 2251         int                     tmp;
ifp = &sc->arpcom.ac_if;
 2255         /* Specify MTU and interface index. */
CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->sc_dv.dv_unit);
CSR_WRITE_4(sc, TI_GCR_IFMTU,
TI_JUMBO_FRAMELEN + ETHER_VLAN_ENCAP_LEN);
TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
 2261         /* Load our MAC address. */
m = (u_int16_t *)&sc->arpcom.ac_enaddr[0];
CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0]));
CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2]));
TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
 2267         /* Enable or disable promiscuous mode as needed. */
 2268         if (ifp->if_flags & IFF_PROMISC) {
TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
 2270         } else {
TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
 2272         }
 2274         /* Program multicast filter. */
ti_setmulti(sc);
 2277         /*
 2278          * If this is a Tigon 1, we should tell the
 2279          * firmware to use software packet filtering.
 2280          */
 2281         if (sc->ti_hwrev == TI_HWREV_TIGON) {
TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
 2283         }
 2285         /* Init RX ring. */
 2286         if (ti_init_rx_ring_std(sc) == ENOBUFS)
panic("not enough mbufs for rx ring");
 2289         /* Init jumbo RX ring. */
ti_init_rx_ring_jumbo(sc);
 2292         /*
 2293          * If this is a Tigon 2, we can also configure the
 2294          * mini ring.
 2295          */
 2296         if (sc->ti_hwrev == TI_HWREV_TIGON_II)
ti_init_rx_ring_mini(sc);
CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
sc->ti_rx_saved_considx = 0;
 2302         /* Init TX ring. */
ti_init_tx_ring(sc);
 2305         /* Tell firmware we're alive. */
TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
 2308         /* Enable host interrupts. */
CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
 2314         /*
 2315          * Make sure to set media properly. We have to do this
 2316          * here since we have to issue commands in order to set
 2317          * the link negotiation and we can't issue commands until
 2318          * the firmware is running.
 2319          */
ifm = &sc->ifmedia;
tmp = ifm->ifm_media;
ifm->ifm_media = ifm->ifm_cur->ifm_media;
ti_ifmedia_upd(ifp);
ifm->ifm_media = tmp;
 2325 }
 2327 /*
 2328  * Set media options.
 2329  */
 2330 int
ti_ifmedia_upd(struct ifnet *ifp)
 2332 {
 2333         struct ti_softc         *sc;
 2334         struct ifmedia          *ifm;
 2335         struct ti_cmd_desc      cmd;
sc = ifp->if_softc;
ifm = &sc->ifmedia;
 2340         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
 2341                 return(EINVAL);
 2343         switch(IFM_SUBTYPE(ifm->ifm_media)) {
 2344         case IFM_AUTO:
CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y|
TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX|
TI_LNK_AUTONEGENB|TI_LNK_ENB);
TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
TI_CMD_CODE_NEGOTIATE_BOTH, 0);
 2353                 break;
 2354         case IFM_1000_SX:
 2355         case IFM_1000_T:
CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB);
CSR_WRITE_4(sc, TI_GCR_LINK, 0);
 2359                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
 2361                 }
TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
 2364                 break;
 2365         case IFM_100_FX:
 2366         case IFM_10_FL:
 2367         case IFM_100_TX:
 2368         case IFM_10_T:
CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF);
 2371                 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
 2374                 } else {
TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
 2376                 }
 2377                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
 2379                 } else {
TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
 2381                 }
TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
TI_CMD_CODE_NEGOTIATE_10_100, 0);
 2384                 break;
 2385         }
 2387         return (0);
 2388 }
 2390 /*
 2391  * Report current media status.
 2392  */
 2393 void
ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
 2395 {
 2396         struct ti_softc         *sc;
u_int32_t               media = 0;
sc = ifp->if_softc;
ifmr->ifm_status = IFM_AVALID;
ifmr->ifm_active = IFM_ETHER;
 2404         if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) {
ifmr->ifm_active |= IFM_NONE;
 2406                 return;
 2407         }
ifmr->ifm_status |= IFM_ACTIVE;
 2411         if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
 2413                 if (sc->ti_copper)
ifmr->ifm_active |= IFM_1000_T;
 2415                 else
ifmr->ifm_active |= IFM_1000_SX;
 2417                 if (media & TI_GLNK_FULL_DUPLEX)
ifmr->ifm_active |= IFM_FDX;
 2419                 else
ifmr->ifm_active |= IFM_HDX;
 2421         } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
 2423                 if (sc->ti_copper) {
 2424                         if (media & TI_LNK_100MB)
ifmr->ifm_active |= IFM_100_TX;
 2426                         if (media & TI_LNK_10MB)
ifmr->ifm_active |= IFM_10_T;
 2428                 } else {
 2429                         if (media & TI_LNK_100MB)
ifmr->ifm_active |= IFM_100_FX;
 2431                         if (media & TI_LNK_10MB)
ifmr->ifm_active |= IFM_10_FL;
 2433                 }
 2434                 if (media & TI_LNK_FULL_DUPLEX)
ifmr->ifm_active |= IFM_FDX;
 2436                 if (media & TI_LNK_HALF_DUPLEX)
ifmr->ifm_active |= IFM_HDX;
 2438         }
 2439 }
 2441 int
ti_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
 2443 {
 2444         struct ti_softc         *sc = ifp->if_softc;
 2445         struct ifreq            *ifr = (struct ifreq *)data;
 2446         struct ifaddr           *ifa = (struct ifaddr *)data;
 2447         int                     s, error = 0;
 2448         struct ti_cmd_desc      cmd;
s = splnet();
 2452         if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) {
splx(s);
 2454                 return (error);
 2455         }
 2457         switch(command) {
 2458         case SIOCSIFADDR:
ifp->if_flags |= IFF_UP;
 2460                 if ((ifp->if_flags & IFF_RUNNING) == 0)
ti_init(sc);
 2462 #ifdef INET
 2463                 if (ifa->ifa_addr->sa_family == AF_INET)
arp_ifinit(&sc->arpcom, ifa);
 2465 #endif /* INET */
 2466                 break;
 2467         case SIOCSIFMTU:
 2468                 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ifp->if_hardmtu)
error = EINVAL;
 2470                 else if (ifp->if_mtu != ifr->ifr_mtu)
ifp->if_mtu = ifr->ifr_mtu;
 2472                 break;
 2473         case SIOCSIFFLAGS:
 2474                 if (ifp->if_flags & IFF_UP) {
 2475                         /*
 2476                          * If only the state of the PROMISC flag changed,
 2477                          * then just use the 'set promisc mode' command
 2478                          * instead of reinitializing the entire NIC. Doing
 2479                          * a full re-init means reloading the firmware and
 2480                          * waiting for it to start up, which may take a
 2481                          * second or two.
 2482                          */
 2483                         if (ifp->if_flags & IFF_RUNNING &&
ifp->if_flags & IFF_PROMISC &&
 2485                             !(sc->ti_if_flags & IFF_PROMISC)) {
TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
TI_CMD_CODE_PROMISC_ENB, 0);
 2488                         } else if (ifp->if_flags & IFF_RUNNING &&
 2489                             !(ifp->if_flags & IFF_PROMISC) &&
sc->ti_if_flags & IFF_PROMISC) {
TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
TI_CMD_CODE_PROMISC_DIS, 0);
 2493                         } else {
 2494                                 if ((ifp->if_flags & IFF_RUNNING) == 0)
ti_init(sc);
 2496                         }
 2497                 } else {
 2498                         if (ifp->if_flags & IFF_RUNNING)
ti_stop(sc);
 2500                 }
sc->ti_if_flags = ifp->if_flags;
 2502                 break;
 2503         case SIOCADDMULTI:
 2504         case SIOCDELMULTI:
error = (command == SIOCADDMULTI) ?
ether_addmulti(ifr, &sc->arpcom) :
ether_delmulti(ifr, &sc->arpcom);
 2509                 if (error == ENETRESET) {
 2510                         if (ifp->if_flags & IFF_RUNNING)
ti_setmulti(sc);
error = 0;
 2513                 }
 2514                 break;
 2515         case SIOCSIFMEDIA:
 2516         case SIOCGIFMEDIA:
error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
 2518                 break;
 2519         default:
error = ENOTTY;
 2521                 break;
 2522         }
splx(s);
 2525         return (error);
 2526 }
 2528 void
ti_watchdog(struct ifnet *ifp)
 2530 {
 2531         struct ti_softc         *sc;
sc = ifp->if_softc;
printf("%s: watchdog timeout -- resetting\n", sc->sc_dv.dv_xname);
ti_stop(sc);
ti_init(sc);
ifp->if_oerrors++;
 2540 }
 2542 /*
 2543  * Stop the adapter and free any mbufs allocated to the
 2544  * RX and TX lists.
 2545  */
 2546 void
ti_stop(struct ti_softc *sc)
 2548 {
 2549         struct ifnet            *ifp;
 2550         struct ti_cmd_desc      cmd;
ifp = &sc->arpcom.ac_if;
ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 2556         /* Disable host interrupts. */
CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
 2558         /*
 2559          * Tell firmware we're shutting down.
 2560          */
TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
 2563         /* Halt and reinitialize. */
ti_chipinit(sc);
ti_mem_set(sc, 0x2000, 0x100000 - 0x2000);
ti_chipinit(sc);
 2568         /* Free the RX lists. */
ti_free_rx_ring_std(sc);
 2571         /* Free jumbo RX list. */
ti_free_rx_ring_jumbo(sc);
 2574         /* Free mini RX list. */
ti_free_rx_ring_mini(sc);
 2577         /* Free TX buffers. */
ti_free_tx_ring(sc);
sc->ti_ev_prodidx.ti_idx = 0;
sc->ti_return_prodidx.ti_idx = 0;
sc->ti_tx_considx.ti_idx = 0;
sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
 2584 }
 2586 /*
 2587  * Stop all chip I/O so that the kernel's probe routines don't
 2588  * get confused by errant DMAs when rebooting.
 2589  */
 2590 void
ti_shutdown(void *xsc)
 2592 {
 2593         struct ti_softc         *sc;
sc = xsc;
ti_chipinit(sc);
 2598 }