cacheline        1236 dev/pci/if_ti.c 	u_int32_t		cacheline;
cacheline        1290 dev/pci/if_ti.c 	cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
cacheline        1299 dev/pci/if_ti.c 		switch(cacheline) {