root/dev/ic/mtd8xx.c

DEFINITIONS

1. mtd_attach
2. mtd_ifmedia_upd
3. mtd_ifmedia_sts
4. mtd_mii_command
5. mtd_miibus_readreg
6. mtd_miibus_writereg
7. mtd_miibus_statchg
8. mtd_setmulti
9. mtd_encap
10. mtd_list_tx_init
11. mtd_list_rx_init
12. mtd_newbuf
13. mtd_reset
14. mtd_ioctl
15. mtd_init
16. mtd_start
17. mtd_stop
18. mtd_watchdog
19. mtd_intr
20. mtd_rxeof
21. mtd_rx_resync
22. mtd_txeof

    1 /*      $OpenBSD: mtd8xx.c,v 1.12 2006/03/25 22:41:43 djm Exp $ */
    3 /*
    4  * Copyright (c) 2003 Oleg Safiullin <form@pdp11.org.ru>
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice unmodified, this list of conditions, and the following
   12  *    disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  *
   29  */
   31 #include "bpfilter.h"
   33 #include <sys/param.h>
   34 #include <sys/mbuf.h>
   35 #include <sys/systm.h>
   36 #include <sys/device.h>
   37 #include <sys/socket.h>
   38 #include <sys/ioctl.h>
   40 #include <net/if.h>
   41 #include <net/if_media.h>
   43 #if NBPFILTER > 0
   44 #include <net/bpf.h>
   45 #endif
   47 #ifdef INET
   48 #include <netinet/in.h>
   49 #include <netinet/if_ether.h>
   50 #endif
   52 #include <machine/bus.h>
   54 #include <dev/mii/mii.h>
   55 #include <dev/mii/miivar.h>
   57 #include <dev/pci/pcidevs.h>
   58 #include <dev/pci/pcivar.h>
   60 #include <dev/ic/mtd8xxreg.h>
   61 #include <dev/ic/mtd8xxvar.h>
   64 static int mtd_ifmedia_upd(struct ifnet *);
   65 static void mtd_ifmedia_sts(struct ifnet *, struct ifmediareq *);
   67 static u_int32_t mtd_mii_command(struct mtd_softc *, int, int, int);
   68 static int mtd_miibus_readreg(struct device *, int, int);
   69 static void mtd_miibus_writereg(struct device *, int, int, int);
   70 static void mtd_miibus_statchg(struct device *);
   71 static void mtd_setmulti(struct mtd_softc *);
   73 static int mtd_encap(struct mtd_softc *, struct mbuf *, u_int32_t *);
   74 static int mtd_list_rx_init(struct mtd_softc *);
   75 static void mtd_list_tx_init(struct mtd_softc *);
   76 static int mtd_newbuf(struct mtd_softc *, int, struct mbuf *);
   78 static void mtd_reset(struct mtd_softc *sc);
   79 static int mtd_ioctl(struct ifnet *, u_long, caddr_t);
   80 static void mtd_init(struct ifnet *);
   81 static void mtd_start(struct ifnet *);
   82 static void mtd_stop(struct ifnet *);
   83 static void mtd_watchdog(struct ifnet *);
   85 static void mtd_rxeof(struct mtd_softc *);
   86 static int mtd_rx_resync(struct mtd_softc *);
   87 static void mtd_txeof(struct mtd_softc *);
   90 void
mtd_attach(struct mtd_softc *sc)
   92 {
   93         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
u_int32_t enaddr[2];
   95         int i;
   97         /* Reset the adapter. */
mtd_reset(sc);
  100         if (bus_dmamem_alloc(sc->sc_dmat, sizeof(struct mtd_list_data),
PAGE_SIZE, 0, sc->sc_listseg, 1, &sc->sc_listnseg,
BUS_DMA_NOWAIT) != 0) {
printf(": can't alloc list mem\n");
  104                 return;
  105         }
  106         if (bus_dmamem_map(sc->sc_dmat, sc->sc_listseg, sc->sc_listnseg,
  107             sizeof(struct mtd_list_data), &sc->sc_listkva,
BUS_DMA_NOWAIT) != 0) {
printf(": can't map list mem\n");
  110                 return;
  111         }
  112         if (bus_dmamap_create(sc->sc_dmat, sizeof(struct mtd_list_data), 1,
  113             sizeof(struct mtd_list_data), 0, BUS_DMA_NOWAIT,
  114             &sc->sc_listmap) != 0) {
printf(": can't alloc list map\n");
  116                 return;
  117         }
  118         if (bus_dmamap_load(sc->sc_dmat, sc->sc_listmap, sc->sc_listkva,
  119             sizeof(struct mtd_list_data), NULL, BUS_DMA_NOWAIT) != 0) {
printf(": can't load list map\n");
  121                 return;
  122         }
sc->mtd_ldata = (struct mtd_list_data *)sc->sc_listkva;
bzero(sc->mtd_ldata, sizeof(struct mtd_list_data));
  126         for (i = 0; i < MTD_RX_LIST_CNT; i++) {
  127                 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES,
  128                     0, BUS_DMA_NOWAIT,
  129                     &sc->mtd_cdata.mtd_rx_chain[i].sd_map) != 0) {
printf(": can't create rx map\n");
  131                         return;
  132                 }
  133         }
  134         if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0,
BUS_DMA_NOWAIT, &sc->sc_rx_sparemap) != 0) {
printf(": can't create rx spare map\n");
  137                 return;
  138         }
  140         for (i = 0; i < MTD_TX_LIST_CNT; i++) {
  141                 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES,
MTD_TX_LIST_CNT - 5, MCLBYTES, 0, BUS_DMA_NOWAIT,
  143                     &sc->mtd_cdata.mtd_tx_chain[i].sd_map) != 0) {
printf(": can't create tx map\n");
  145                         return;
  146                 }
  147         }
  148         if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, MTD_TX_LIST_CNT - 5,
MCLBYTES, 0, BUS_DMA_NOWAIT, &sc->sc_tx_sparemap) != 0) {
printf(": can't create tx spare map\n");
  151                 return;
  152         }
  155         /* Get station address. */
enaddr[0] = letoh32(CSR_READ_4(MTD_PAR0));
enaddr[1] = letoh32(CSR_READ_4(MTD_PAR4));
bcopy(enaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN);
printf(" address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr));
  161         /* Initialize interface */
ifp->if_softc = sc;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_ioctl = mtd_ioctl;
ifp->if_start = mtd_start;
ifp->if_watchdog = mtd_watchdog;
ifp->if_baudrate = 10000000;
IFQ_SET_READY(&ifp->if_snd);
bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
ifp->if_capabilities = IFCAP_VLAN_MTU;
  173         /*
  174          * Initialize our media structures and probe the MII.
  175          */
sc->sc_mii.mii_ifp = ifp;
sc->sc_mii.mii_readreg = mtd_miibus_readreg;
sc->sc_mii.mii_writereg = mtd_miibus_writereg;
sc->sc_mii.mii_statchg = mtd_miibus_statchg;
ifmedia_init(&sc->sc_mii.mii_media, 0, mtd_ifmedia_upd,
mtd_ifmedia_sts);
mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
MII_OFFSET_ANY, 0);
  184         if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_NONE, 0,
NULL);
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_NONE);
  188         } else
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO);
  191         /*
  192          * Attach us everywhere
  193          */
if_attach(ifp);
ether_ifattach(ifp);
  196 }
  199 static int
mtd_ifmedia_upd(struct ifnet *ifp)
  201 {
  202         struct mtd_softc *sc = ifp->if_softc;
  204         return (mii_mediachg(&sc->sc_mii));
  205 }
  208 static void
mtd_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
  210 {
  211         struct mtd_softc *sc = ifp->if_softc;
mii_pollstat(&sc->sc_mii);
ifmr->ifm_active = sc->sc_mii.mii_media_active;
ifmr->ifm_status = sc->sc_mii.mii_media_status;
  216 }
  219 static u_int32_t
mtd_mii_command(struct mtd_softc *sc, int opcode, int phy, int reg)
  221 {
u_int32_t miir, mask, data;
  223         int i;
miir = (CSR_READ_4(MTD_MIIMGT) & ~MIIMGT_MASK) | MIIMGT_WRITE |
MIIMGT_MDO;
  228         for (i = 0; i < 32; i++) {
miir &= ~MIIMGT_MDC;
CSR_WRITE_4(MTD_MIIMGT, miir);
miir |= MIIMGT_MDC;
CSR_WRITE_4(MTD_MIIMGT, miir);
  233         }
data = opcode | (phy << 7) | (reg << 2);
  237         for (mask = 0; mask; mask >>= 1) {
miir &= ~(MIIMGT_MDC | MIIMGT_MDO);
  239                 if (mask & data)
miir |= MIIMGT_MDO;
CSR_WRITE_4(MTD_MIIMGT, miir);
miir |= MIIMGT_MDC;
CSR_WRITE_4(MTD_MIIMGT, miir);
DELAY(30);
  246                 if (mask == 0x4 && opcode == MII_OPCODE_RD)
miir &= ~MIIMGT_WRITE;
  248         }
  249         return (miir);
  250 }
  254 static int
mtd_miibus_readreg(struct device *self, int phy, int reg)
  256 {
  257         struct mtd_softc *sc = (void *)self;
  259         if (sc->sc_devid == PCI_PRODUCT_MYSON_MTD803)
  260                 return (phy ? 0 : (int)CSR_READ_2(MTD_PHYCSR + (reg << 1)));
  261         else {
u_int32_t miir, mask, data;
miir = mtd_mii_command(sc, MII_OPCODE_RD, phy, reg);
  265                 for (mask = 0x8000, data = 0; mask; mask >>= 1) {
miir &= ~MIIMGT_MDC;
CSR_WRITE_4(MTD_MIIMGT, miir);
miir = CSR_READ_4(MTD_MIIMGT);
  269                         if (miir & MIIMGT_MDI)
data |= mask;
miir |= MIIMGT_MDC;
CSR_WRITE_4(MTD_MIIMGT, miir);
DELAY(30);
  274                 }
miir &= ~MIIMGT_MDC;
CSR_WRITE_4(MTD_MIIMGT, miir);
  278                 return ((int)data);
  279         }
  280 }
  283 static void
mtd_miibus_writereg(struct device *self, int phy, int reg, int val)
  285 {
  286         struct mtd_softc *sc = (void *)self;
  288         if (sc->sc_devid == PCI_PRODUCT_MYSON_MTD803) {
  289                 if (!phy)
CSR_WRITE_2(MTD_PHYCSR + (reg << 1), val);
  291         } else {
u_int32_t miir, mask;
miir = mtd_mii_command(sc, MII_OPCODE_WR, phy, reg);
  295                 for (mask = 0x8000; mask; mask >>= 1) {
miir &= ~(MIIMGT_MDC | MIIMGT_MDO);
  297                         if (mask & (u_int32_t)val)
miir |= MIIMGT_MDO;
CSR_WRITE_4(MTD_MIIMGT, miir);
miir |= MIIMGT_MDC;
CSR_WRITE_4(MTD_MIIMGT, miir);
DELAY(1);
  303                 }
miir &= ~MIIMGT_MDC;
CSR_WRITE_4(MTD_MIIMGT, miir);
  306         }
  307 }
  310 static void
mtd_miibus_statchg(struct device *self)
  312 {
  313         /* NOTHING */
  314 }
  317 void
mtd_setmulti(struct mtd_softc *sc)
  319 {
  320         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
u_int32_t rxfilt, crc, hash[2] = { 0, 0 };
  322         struct ether_multistep step;
  323         struct ether_multi *enm;
  324         int mcnt = 0;
allmulti:
rxfilt = CSR_READ_4(MTD_TCRRCR) & ~RCR_AM;
  328         if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
rxfilt |= RCR_AM;
CSR_WRITE_4(MTD_TCRRCR, rxfilt);
CSR_WRITE_4(MTD_MAR0, 0xffffffff);
CSR_WRITE_4(MTD_MAR4, 0xffffffff);
  333                 return;
  334         }
  336         /* First, zot all the existing hash bits. */
CSR_WRITE_4(MTD_MAR0, 0);
CSR_WRITE_4(MTD_MAR4, 0);
  340         /* Now program new ones. */
ETHER_FIRST_MULTI(step, &sc->sc_arpcom, enm);
  342         while (enm != NULL) {
  343                 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
ifp->if_flags |= IFF_ALLMULTI;
  345                         goto allmulti;
  346                 }
crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26;
hash[crc >> 5] |= 1 << (crc & 0xf);
  349                 ++mcnt;
ETHER_NEXT_MULTI(step, enm);
  351         }
  353         if (mcnt)
rxfilt |= RCR_AM;
CSR_WRITE_4(MTD_MAR0, hash[0]);
CSR_WRITE_4(MTD_MAR4, hash[1]);
CSR_WRITE_4(MTD_TCRRCR, rxfilt);
  358 }
  361 /*
  362  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
  363  * pointers to the fragment pointers.
  364  */
  365 int
mtd_encap(struct mtd_softc *sc, struct mbuf *m_head, u_int32_t *txidx)
  367 {
  368         struct mtd_tx_desc *f = NULL;
  369         int frag, cur, cnt = 0, i, total_len = 0;
bus_dmamap_t map;
  372         /*
  373          * Start packing the mbufs in this chain into
  374          * the fragment pointers. Stop when we run out
  375          * of fragments or hit the end of the mbuf chain.
  376          */
map = sc->sc_tx_sparemap;
  379         if (bus_dmamap_load_mbuf(sc->sc_dmat, map,
m_head, BUS_DMA_NOWAIT) != 0)
  381                 return (1);
cur = frag = *txidx;
  385         for (i = 0; i < map->dm_nsegs; i++) {
  386                 if ((MTD_TX_LIST_CNT -
  387                     (sc->mtd_cdata.mtd_tx_cnt + cnt)) < 5) {
bus_dmamap_unload(sc->sc_dmat, map);
  389                         return (1);
  390                 }
f = &sc->mtd_ldata->mtd_tx_list[frag];
f->td_tcw = htole32(map->dm_segs[i].ds_len);
total_len += map->dm_segs[i].ds_len;
  395                 if (cnt == 0) {
f->td_tsw = 0;
f->td_tcw |= htole32(TCW_FD | TCW_CRC | TCW_PAD);
  398                 } else
f->td_tsw = htole32(TSW_OWN);
f->td_buf = htole32(map->dm_segs[i].ds_addr);
cur = frag;
frag = (frag + 1) % MTD_TX_LIST_CNT;
cnt++;
  404         }
sc->mtd_cdata.mtd_tx_cnt += cnt;
sc->mtd_cdata.mtd_tx_chain[cur].sd_mbuf = m_head;
sc->sc_tx_sparemap = sc->mtd_cdata.mtd_tx_chain[cur].sd_map;
sc->mtd_cdata.mtd_tx_chain[cur].sd_map = map;
sc->mtd_ldata->mtd_tx_list[cur].td_tcw |= htole32(TCW_LD | TCW_IC);
  411         if (sc->sc_devid == PCI_PRODUCT_MYSON_MTD891)
sc->mtd_ldata->mtd_tx_list[cur].td_tcw |=
htole32(TCW_EIC | TCW_RTLC);
bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
BUS_DMASYNC_PREWRITE);
sc->mtd_ldata->mtd_tx_list[*txidx].td_tsw = htole32(TSW_OWN);
sc->mtd_ldata->mtd_tx_list[*txidx].td_tcw |=
htole32(total_len << TCW_PKTS_SHIFT);
bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
offsetof(struct mtd_list_data, mtd_tx_list[0]),
  424             sizeof(struct mtd_tx_desc) * MTD_TX_LIST_CNT,
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
  427         *txidx = frag;
  429         return (0);
  430 }
  433 /*
  434  * Initialize the transmit descriptors.
  435  */
  436 static void
mtd_list_tx_init(struct mtd_softc *sc)
  438 {
  439         struct mtd_chain_data *cd;
  440         struct mtd_list_data *ld;
  441         int i;
cd = &sc->mtd_cdata;
ld = sc->mtd_ldata;
  445         for (i = 0; i < MTD_TX_LIST_CNT; i++) {
cd->mtd_tx_chain[i].sd_mbuf = NULL;
ld->mtd_tx_list[i].td_tsw = 0;
ld->mtd_tx_list[i].td_tcw = 0;
ld->mtd_tx_list[i].td_buf = 0;
ld->mtd_tx_list[i].td_next = htole32(
sc->sc_listmap->dm_segs[0].ds_addr +
offsetof(struct mtd_list_data,
mtd_tx_list[(i + 1) % MTD_TX_LIST_CNT]));
  454         }
cd->mtd_tx_prod = cd->mtd_tx_cons = cd->mtd_tx_cnt = 0;
  457 }
  460 /*
  461  * Initialize the RX descriptors and allocate mbufs for them. Note that
  462  * we arrange the descriptors in a closed ring, so that the last descriptor
  463  * points back to the first.
  464  */
  465 static int
mtd_list_rx_init(struct mtd_softc *sc)
  467 {
  468         struct mtd_list_data *ld;
  469         int i;
ld = sc->mtd_ldata;
  473         for (i = 0; i < MTD_RX_LIST_CNT; i++) {
  474                 if (mtd_newbuf(sc, i, NULL))
  475                         return (1);
ld->mtd_rx_list[i].rd_next = htole32(
sc->sc_listmap->dm_segs[0].ds_addr +
offsetof(struct mtd_list_data,
mtd_rx_list[(i + 1) % MTD_RX_LIST_CNT])
  480                 );
  481         }
sc->mtd_cdata.mtd_rx_prod = 0;
  485         return (0);
  486 }
  489 /*
  490  * Initialize an RX descriptor and attach an MBUF cluster.
  491  */
  492 static int
mtd_newbuf(struct mtd_softc *sc, int i, struct mbuf *m)
  494 {
  495         struct mbuf *m_new = NULL;
  496         struct mtd_rx_desc *c;
bus_dmamap_t map;
c = &sc->mtd_ldata->mtd_rx_list[i];
  501         if (m == NULL) {
MGETHDR(m_new, M_DONTWAIT, MT_DATA);
  503                 if (m_new == NULL)
  504                         return (1);
MCLGET(m_new, M_DONTWAIT);
  507                 if (!(m_new->m_flags & M_EXT)) {
m_freem(m_new);
  509                         return (1);
  510                 }
m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
  512                 if (bus_dmamap_load(sc->sc_dmat, sc->sc_rx_sparemap,
mtod(m_new, caddr_t), MCLBYTES, NULL,
BUS_DMA_NOWAIT) != 0) {
m_freem(m_new);
  516                         return (1);
  517                 }
map = sc->mtd_cdata.mtd_rx_chain[i].sd_map;
sc->mtd_cdata.mtd_rx_chain[i].sd_map = sc->sc_rx_sparemap;
sc->sc_rx_sparemap = map;
  521         } else {
m_new = m;
m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
m_new->m_data = m_new->m_ext.ext_buf;
  525         }
m_adj(m_new, sizeof(u_int64_t));
bus_dmamap_sync(sc->sc_dmat, sc->mtd_cdata.mtd_rx_chain[i].sd_map, 0,
sc->mtd_cdata.mtd_rx_chain[i].sd_map->dm_mapsize,
BUS_DMASYNC_PREREAD);
sc->mtd_cdata.mtd_rx_chain[i].sd_mbuf = m_new;
c->rd_buf = htole32(
sc->mtd_cdata.mtd_rx_chain[i].sd_map->dm_segs[0].ds_addr +
  536             sizeof(u_int64_t));
c->rd_rcw = htole32(ETHER_MAX_DIX_LEN);
c->rd_rsr = htole32(RSR_OWN);
bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
offsetof(struct mtd_list_data, mtd_rx_list[i]),
  542             sizeof(struct mtd_rx_desc),
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
  545         return (0);
  546 }
  549 static void
mtd_reset(struct mtd_softc *sc)
  551 {
  552         int i;
  554         /* Set software reset bit */
CSR_WRITE_4(MTD_BCR, BCR_SWR);
  557         /*
  558          * Wait until software reset completed.
  559          */
  560         for (i = 0; i < MTD_TIMEOUT; ++i) {
DELAY(10);
  562                 if (!(CSR_READ_4(MTD_BCR) & BCR_SWR)) {
  563                         /*
  564                          * Wait a little while for the chip to get
  565                          * its brains in order.
  566                          */
DELAY(1000);
  568                         return;
  569                 }
  570         }
  572         /* Reset timed out. */
printf("%s: reset never completed!\n", sc->sc_dev.dv_xname);
  574 }
  577 static int
mtd_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
  579 {
  580         struct mtd_softc *sc = ifp->if_softc;
  581         struct ifreq *ifr = (struct ifreq *)data;
  582         struct ifaddr *ifa = (struct ifaddr *)data;
  583         int s, error;
s = splnet();
  586         if ((error = ether_ioctl(ifp, &sc->sc_arpcom, command, data)) > 0) {
splx(s);
  588                 return (error);
  589         }
  591         switch (command) {
  592         case SIOCSIFADDR:
ifp->if_flags |= IFF_UP;
mtd_init(ifp);
  595                 switch (ifa->ifa_addr->sa_family) {
  596 #ifdef INET
  597                 case AF_INET:
arp_ifinit(&sc->sc_arpcom, ifa);
  599                         break;
  600 #endif /* INET */
  601                 }
  602                 break;
  603         case SIOCSIFMTU:
  604                 if (ifr->ifr_mtu >= ETHERMIN && ifr->ifr_mtu <= ETHERMTU)
ifp->if_mtu = ifr->ifr_mtu;
  606                 else
error = EINVAL;
  608                 break;
  610         case SIOCSIFFLAGS:
  611                 if (ifp->if_flags & IFF_UP)
mtd_init(ifp);
  613                 else {
  614                         if (ifp->if_flags & IFF_RUNNING)
mtd_stop(ifp);
  616                 }
error = 0;
  618                 break;
  619         case SIOCADDMULTI:
  620         case SIOCDELMULTI:
error = (command == SIOCADDMULTI) ?
ether_addmulti(ifr, &sc->sc_arpcom) :
ether_delmulti(ifr, &sc->sc_arpcom);
  625                 if (error == ENETRESET) {
  626                         /*
  627                          * Multicast list has changed; set the hardware
  628                          * filter accordingly.
  629                          */
  630                         if (ifp->if_flags & IFF_RUNNING)
mtd_setmulti(sc);
error = 0;
  633                 }
  634                 break;
  635         case SIOCGIFMEDIA:
  636         case SIOCSIFMEDIA:
error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command);
  638                 break;
  639         default:
error = EINVAL;
  641                 break;
  642         }
splx(s);
  645         return (error);
  646 }
  649 static void
mtd_init(struct ifnet *ifp)
  651 {
  652         struct mtd_softc *sc = ifp->if_softc;
  653         int s;
s = splnet();
  657         /*
  658          * Cancel pending I/O and free all RX/TX buffers.
  659          */
mtd_stop(ifp);
  662         /*
  663          * Set cache alignment and burst length.
  664          */
CSR_WRITE_4(MTD_BCR, BCR_PBL8);
CSR_WRITE_4(MTD_TCRRCR, TCR_TFTSF | RCR_RBLEN | RCR_RPBL512);
  667         if (sc->sc_devid == PCI_PRODUCT_MYSON_MTD891) {
CSR_SETBIT(MTD_BCR, BCR_PROG);
CSR_SETBIT(MTD_TCRRCR, TCR_ENHANCED);
  670         }
  672         if (ifp->if_flags & IFF_PROMISC)
CSR_SETBIT(MTD_TCRRCR, RCR_PROM);
  674         else
CSR_CLRBIT(MTD_TCRRCR, RCR_PROM);
  677         if (ifp->if_flags & IFF_BROADCAST)
CSR_SETBIT(MTD_TCRRCR, RCR_AB);
  679         else
CSR_CLRBIT(MTD_TCRRCR, RCR_AB);
mtd_setmulti(sc);
  684         if (mtd_list_rx_init(sc)) {
printf("%s: can't allocate memeory for rx buffers\n",
sc->sc_dev.dv_xname);
splx(s);
  688                 return;
  689         }
mtd_list_tx_init(sc);
CSR_WRITE_4(MTD_RXLBA, sc->sc_listmap->dm_segs[0].ds_addr +
offsetof(struct mtd_list_data, mtd_rx_list[0]));
CSR_WRITE_4(MTD_TXLBA, sc->sc_listmap->dm_segs[0].ds_addr +
offsetof(struct mtd_list_data, mtd_tx_list[0]));
  697         /*
  698          * Enable interrupts.
  699          */
CSR_WRITE_4(MTD_IMR, IMR_INTRS);
CSR_WRITE_4(MTD_ISR, 0xffffffff);
  703         /* Enable receiver and transmitter */
CSR_SETBIT(MTD_TCRRCR, TCR_TE | RCR_RE);
CSR_WRITE_4(MTD_RXPDR, 0xffffffff);
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
splx(s);
  710 }
  713 /*
  714  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
  715  * to the mbuf data regions directly in the transmit lists. We also save a
  716  * copy of the pointers since the transmit list fragment pointers are
  717  * physical addresses.
  718  */
  719 static void
mtd_start(struct ifnet *ifp)
  721 {
  722         struct mtd_softc *sc = ifp->if_softc;
  723         struct mbuf *m_head = NULL;
  724         int idx;
  726         if (sc->mtd_cdata.mtd_tx_cnt) {
ifp->if_flags |= IFF_OACTIVE;
  728                 return;
  729         }
idx = sc->mtd_cdata.mtd_tx_prod;
  732         while (sc->mtd_cdata.mtd_tx_chain[idx].sd_mbuf == NULL) {
IFQ_DEQUEUE(&ifp->if_snd, m_head);
  734                 if (m_head == NULL)
  735                         break;
  737                 if (mtd_encap(sc, m_head, &idx)) {
ifp->if_flags |= IFF_OACTIVE;
  739                         break;
  740                 }
  742                 /*
  743                  * If there's a BPF listener, bounce a copy of this frame
  744                  * to him.
  745                  */
  746 #if NBPFILTER > 0
  747                 if (ifp->if_bpf != NULL)
bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT);
  749 #endif
  750         }
  752         if (idx == sc->mtd_cdata.mtd_tx_prod)
  753                 return;
  755         /* Transmit */
sc->mtd_cdata.mtd_tx_prod = idx;
CSR_WRITE_4(MTD_TXPDR, 0xffffffff);
  759         /*
  760          * Set a timeout in case the chip goes out to lunch.
  761          */
ifp->if_timer = 5;
  763 }
  766 static void
mtd_stop(struct ifnet *ifp)
  768 {
  769         struct mtd_softc *sc = ifp->if_softc;
  770         int i;
ifp->if_timer = 0;
ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
CSR_CLRBIT(MTD_TCRRCR, (RCR_RE | TCR_TE));
CSR_WRITE_4(MTD_IMR, 0);
CSR_WRITE_4(MTD_TXLBA, 0);
CSR_WRITE_4(MTD_RXLBA, 0);
  780         /*
  781          * Free data in the RX lists.
  782          */
  783         for (i = 0; i < MTD_RX_LIST_CNT; i++) {
  784                 if (sc->mtd_cdata.mtd_rx_chain[i].sd_map->dm_nsegs != 0) {
bus_dmamap_t map = sc->mtd_cdata.mtd_rx_chain[i].sd_map;
bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
BUS_DMASYNC_POSTREAD);
bus_dmamap_unload(sc->sc_dmat, map);
  790                 }
  791                 if (sc->mtd_cdata.mtd_rx_chain[i].sd_mbuf != NULL) {
m_freem(sc->mtd_cdata.mtd_rx_chain[i].sd_mbuf);
sc->mtd_cdata.mtd_rx_chain[i].sd_mbuf = NULL;
  794                 }
  795         }
bzero((char *)&sc->mtd_ldata->mtd_rx_list,
  797                 sizeof(sc->mtd_ldata->mtd_rx_list));
  799         /*
  800          * Free the TX list buffers.
  801          */
  802         for (i = 0; i < MTD_TX_LIST_CNT; i++) {
  803                 if (sc->mtd_cdata.mtd_tx_chain[i].sd_map->dm_nsegs != 0) {
bus_dmamap_t map = sc->mtd_cdata.mtd_tx_chain[i].sd_map;
bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->sc_dmat, map);
  809                 }
  810                 if (sc->mtd_cdata.mtd_tx_chain[i].sd_mbuf != NULL) {
m_freem(sc->mtd_cdata.mtd_tx_chain[i].sd_mbuf);
sc->mtd_cdata.mtd_tx_chain[i].sd_mbuf = NULL;
  813                 }
  814         }
bzero((char *)&sc->mtd_ldata->mtd_tx_list,
  817                 sizeof(sc->mtd_ldata->mtd_tx_list));
  819 }
  822 static void
mtd_watchdog(struct ifnet *ifp)
  824 {
  825         struct mtd_softc *sc = ifp->if_softc;
ifp->if_oerrors++;
printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname);
mtd_stop(ifp);
mtd_reset(sc);
mtd_init(ifp);
  834         if (!IFQ_IS_EMPTY(&ifp->if_snd))
mtd_start(ifp);
  836 }
  839 int
mtd_intr(void *xsc)
  841 {
  842         struct mtd_softc *sc = xsc;
  843         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
u_int32_t status;
  845         int claimed = 0;
  847         /* Supress unwanted interrupts */
  848         if (!(ifp->if_flags & IFF_RUNNING)) {
  849                 if (CSR_READ_4(MTD_ISR) & ISR_INTRS)
mtd_stop(ifp);
  851                 return (claimed);
  852         }
  854         /* Disable interrupts. */
CSR_WRITE_4(MTD_IMR, 0);
  857         while((status = CSR_READ_4(MTD_ISR)) & ISR_INTRS) {
claimed = 1;
CSR_WRITE_4(MTD_ISR, status);
  862                 /* RX interrupt. */
  863                 if (status & ISR_RI) {
  864                         int curpkts = ifp->if_ipackets;
mtd_rxeof(sc);
  867                         if (curpkts == ifp->if_ipackets)
  868                                 while(mtd_rx_resync(sc))
mtd_rxeof(sc);
  870                 }
  872                 /* RX error interrupt. */
  873                 if (status & (ISR_RXERI | ISR_RBU))
ifp->if_ierrors++;
  876                 /* TX interrupt. */
  877                 if (status & (ISR_TI | ISR_ETI | ISR_TBU))
mtd_txeof(sc);
  880                 /* Fatal bus error interrupt. */
  881                 if (status & ISR_FBE) {
mtd_reset(sc);
mtd_start(ifp);
  884                 }
  885         }
  887         /* Re-enable interrupts. */
CSR_WRITE_4(MTD_IMR, IMR_INTRS);
  890         if (!IFQ_IS_EMPTY(&ifp->if_snd))
mtd_start(ifp);
  893         return (claimed);
  894 }
  897 /*
  898  * A frame has been uploaded: pass the resulting mbuf chain up to
  899  * the higher level protocols.
  900  */
  901 static void
mtd_rxeof(struct mtd_softc *sc)
  903 {
  904         struct mbuf *m;
  905         struct ifnet *ifp;
  906         struct mtd_rx_desc *cur_rx;
  907         int i, total_len = 0;
u_int32_t rxstat;
ifp = &sc->sc_arpcom.ac_if;
i = sc->mtd_cdata.mtd_rx_prod;
  913         while(!(sc->mtd_ldata->mtd_rx_list[i].rd_rsr & htole32(RSR_OWN))) {
  914                 struct mbuf *m0 = NULL;
bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
offsetof(struct mtd_list_data, mtd_rx_list[i]),
  918                     sizeof(struct mtd_rx_desc),
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
cur_rx = &sc->mtd_ldata->mtd_rx_list[i];
rxstat = letoh32(cur_rx->rd_rsr);
m = sc->mtd_cdata.mtd_rx_chain[i].sd_mbuf;
total_len = RSR_FLNG_GET(rxstat);
sc->mtd_cdata.mtd_rx_chain[i].sd_mbuf = NULL;
  928                 /*
  929                  * If an error occurs, update stats, clear the
  930                  * status word and leave the mbuf cluster in place:
  931                  * it should simply get re-used next time this descriptor
  932                  * comes up in the ring.
  933                  */
  934                 if (rxstat & RSR_RXER) {
ifp->if_ierrors++;
mtd_newbuf(sc, i, m);
  937                         if (rxstat & RSR_CRC) {
i = (i + 1) % MTD_RX_LIST_CNT;
  939                                 continue;
  940                         } else {
mtd_init(ifp);
  942                                 return;
  943                         }
  944                 }
  946                 /* No errors; receive the packet. */    
total_len -= ETHER_CRC_LEN;
bus_dmamap_sync(sc->sc_dmat, sc->mtd_cdata.mtd_rx_chain[i].sd_map,
  950                     0, sc->mtd_cdata.mtd_rx_chain[i].sd_map->dm_mapsize,
BUS_DMASYNC_POSTREAD);
m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, total_len + ETHER_ALIGN,
  954                     0, ifp, NULL);
mtd_newbuf(sc, i, m);
i = (i + 1) % MTD_RX_LIST_CNT;
  957                 if (m0 == NULL) {
ifp->if_ierrors++;
  959                         continue;
  960                 }
m_adj(m0, ETHER_ALIGN);
m = m0;
ifp->if_ipackets++;
  966 #if NBPFILTER > 0
  967                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN);
  969 #endif
ether_input_mbuf(ifp, m);
  971         }
sc->mtd_cdata.mtd_rx_prod = i;
  974 }
  977 /*
  978  * This routine searches the RX ring for dirty descriptors in the
  979  * event that the rxeof routine falls out of sync with the chip's
  980  * current descriptor pointer. This may happen sometimes as a result
  981  * of a "no RX buffer available" condition that happens when the chip
  982  * consumes all of the RX buffers before the driver has a chance to
  983  * process the RX ring. This routine may need to be called more than
  984  * once to bring the driver back in sync with the chip, however we
  985  * should still be getting RX DONE interrupts to drive the search
  986  * for new packets in the RX ring, so we should catch up eventually.
  987  */
  988 static int
mtd_rx_resync(sc)
  990         struct mtd_softc *sc;
  991 {
  992         int i, pos;
  993         struct mtd_rx_desc *cur_rx;
pos = sc->mtd_cdata.mtd_rx_prod;
  997         for (i = 0; i < MTD_RX_LIST_CNT; i++) {
bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
offsetof(struct mtd_list_data, mtd_rx_list[pos]),
 1000                     sizeof(struct mtd_rx_desc),
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
cur_rx = &sc->mtd_ldata->mtd_rx_list[pos];
 1004                 if (!(cur_rx->rd_rsr & htole32(RSR_OWN)))
 1005                         break;
pos = (pos + 1) % MTD_RX_LIST_CNT;
 1007         }
 1009         /* If the ring really is empty, then just return. */
 1010         if (i == MTD_RX_LIST_CNT)
 1011                 return (0);
 1013         /* We've fallen behind the chip: catch it. */
sc->mtd_cdata.mtd_rx_prod = pos;
 1016         return (EAGAIN);
 1017 }
 1020 /*
 1021  * A frame was downloaded to the chip. It's safe for us to clean up
 1022  * the list buffers.
 1023  */
 1024 static void
mtd_txeof(struct mtd_softc *sc)
 1026 {
 1027         struct mtd_tx_desc *cur_tx = NULL;
 1028         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
 1029         int idx;
 1031         /* Clear the timeout timer. */
ifp->if_timer = 0;
 1034         /*
 1035          * Go through our tx list and free mbufs for those
 1036          * frames that have been transmitted.
 1037          */
idx = sc->mtd_cdata.mtd_tx_cons;
 1039         while(idx != sc->mtd_cdata.mtd_tx_prod) {
u_int32_t txstat;
bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
offsetof(struct mtd_list_data, mtd_tx_list[idx]),
 1044                     sizeof(struct mtd_tx_desc),
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
cur_tx = &sc->mtd_ldata->mtd_tx_list[idx];
txstat = letoh32(cur_tx->td_tsw);
 1050                 if (txstat & TSW_OWN || txstat == TSW_UNSENT)
 1051                         break;
 1053                 if (!(cur_tx->td_tcw & htole32(TCW_LD))) {
sc->mtd_cdata.mtd_tx_cnt--;
idx = (idx + 1) % MTD_TX_LIST_CNT;
 1056                         continue;
 1057                 }
 1059                 if (CSR_READ_4(MTD_TCRRCR) & TCR_ENHANCED)
ifp->if_collisions += TSR_NCR_GET(CSR_READ_4(MTD_TSR));
 1061                 else {
 1062                         if (txstat & TSW_TXERR) {
ifp->if_oerrors++;
 1064                                 if (txstat & TSW_EC)
ifp->if_collisions++;
 1066                                 if (txstat & TSW_LC)
ifp->if_collisions++;
 1068                         }
ifp->if_collisions += TSW_NCR_GET(txstat);
 1070                 }
ifp->if_opackets++;
 1073                 if (sc->mtd_cdata.mtd_tx_chain[idx].sd_map->dm_nsegs != 0) {
bus_dmamap_t map =
sc->mtd_cdata.mtd_tx_chain[idx].sd_map;
bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->sc_dmat, map);
 1079                 }
 1080                 if (sc->mtd_cdata.mtd_tx_chain[idx].sd_mbuf != NULL) {
m_freem(sc->mtd_cdata.mtd_tx_chain[idx].sd_mbuf);
sc->mtd_cdata.mtd_tx_chain[idx].sd_mbuf = NULL;
 1083                 }
sc->mtd_cdata.mtd_tx_cnt--;
idx = (idx + 1) % MTD_TX_LIST_CNT;
 1086         }
 1088         if (cur_tx != NULL) {
ifp->if_flags &= ~IFF_OACTIVE;
sc->mtd_cdata.mtd_tx_cons = idx;
 1091         } else
 1092                 if (sc->mtd_ldata->mtd_tx_list[idx].td_tsw ==
htole32(TSW_UNSENT)) {
sc->mtd_ldata->mtd_tx_list[idx].td_tsw =
htole32(TSW_OWN);
ifp->if_timer = 5;
CSR_WRITE_4(MTD_TXPDR, 0xffffffff);
 1098                 }
 1099 }
 1101 struct cfdriver mtd_cd = {
 1102         0, "mtd", DV_IFNET
 1103 };