1 /* $OpenBSD: mtd8xxvar.h,v 1.3 2004/09/28 04:37:32 brad Exp $ */
2
3 /*
4 * Copyright (c) 2003 Oleg Safiullin <form@pdp11.org.ru>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 */
30
31 #ifndef __DEV_IC_MTD8XXVAR_H__
32 #define __DEV_IC_MTD8XXVAR_H__
33
34 #define MTD_RX_LIST_CNT 64
35 #define MTD_TX_LIST_CNT 128
36
37 /*
38 * Transmit descriptor structure.
39 */
40 struct mtd_tx_desc {
41 u_int32_t td_tsw; /* Transmit status word */
42 #define TSW_OWN 0x80000000U /* Descriptor owned by NIC */
43 #define TSW_TXERR 0x00008000U /* Transmission error */
44 #define TSW_ABORT 0x00002000U /* Transmission aborted */
45 #define TSW_CSL 0x00001000U /* Carrier sense lost */
46 #define TSW_LC 0x00000800U /* Late collision occurs */
47 #define TSW_EC 0x00000400U /* Excessive collisions */
48 #define TSW_DFR 0x00000200U /* Deferred */
49 #define TSW_HF 0x00000100U /* Heart beat failure */
50 #define TSW_NCR_MASK 0x000000FFU
51 #define TSW_NCR_SHIFT 0
52 #define TSW_NCR_GET(x) (((x) & TSW_NCR_MASK) >> TSW_NCR_SHIFT)
53 /* Collision retry count */
54 #define TSW_UNSENT 0x00001234U /* Unsent packet magic */
55 u_int32_t td_tcw; /* Transmit configure word */
56 #define TCW_IC 0x80000000U /* Interrupt control */
57 #define TCW_EIC 0x40000000U /* Early interrupt control */
58 #define TCW_LD 0x20000000U /* Last descriptor */
59 #define TCW_FD 0x10000000U /* First descriptor */
60 #define TCW_CRC 0x08000000U /* Append CRC field to packet */
61 #define TCW_PAD 0x04000000U /* Pad zeroes to the end of packet */
62 #define TCW_RTLC 0x02000000U /* Retry late collision */
63 #define TCW_PKTS_MASK 0x00003FF8U
64 #define TCW_PKTS_SHIFT 11
65 #define TCW_PKTS_GET(x) (((x) & TCW_PKTS_MASK) >> TCW_PKTS_SHIFT)
66 /* Packet size */
67 #define TCW_TBS_MASK 0x000007FFU
68 #define TCW_TBS_SHIFT 0
69 #define TCW_TBS_GET(x) (((x) & TCW_TBS_MASK) >> TCW_TBS_SHIFT)
70 /* Transmit buffer size */
71 u_int32_t td_buf; /* Transmit buffer address */
72 u_int32_t td_next; /* Next descriptor address */
73 };
74
75
76 /*
77 * Receive descriptor structure.
78 */
79 struct mtd_rx_desc {
80 u_int32_t rd_rsr; /* Receive status register */
81 #define RSR_OWN 0x80000000U /* Descriptor owned by NIC */
82 #define RSR_FLNG_MASK 0x0FFF0000U
83 #define RSR_FLNG_SHIFT 16
84 #define RSR_FLNG_GET(x) (((x) & RSR_FLNG_MASK) >> RSR_FLNG_SHIFT)
85 /* Frame length */
86 #define RSR_MAR 0x00004000U /* Multicast address received */
87 #define RSR_BAR 0x00002000U /* Broadcast address received */
88 #define RSR_PHY 0x00001000U /* Physical address received */
89 #define RSR_FSD 0x00000800U /* First descriptor */
90 #define RSR_LSD 0x00000400U /* Last descriptor */
91 #define RSR_ES 0x00000080U /* Error summary */
92 #define RSR_RUNT 0x00000040U /* Runt packet received */
93 #define RSR_LONG 0x00000020U /* Long packet received */
94 #define RSR_FAE 0x00000010U /* Frame alignment error */
95 #define RSR_CRC 0x00000008U /* CRC error */
96 #define RSR_RXER 0x00000004U /* Receive error */
97 u_int32_t rd_rcw; /* Receive configure word */
98 #define RCW_RBS_MASK 0x000007FFU
99 #define RCW_RBS_SHIFT 0
100 #define RCW_RBS_GET(x) (((x) & RCW_RBS_MASK) >> RCW_RBS_SHIFT)
101 u_int32_t rd_buf; /* Receive buffer address */
102 u_int32_t rd_next; /* Next descriptor address */
103 };
104
105
106 struct mtd_list_data {
107 struct mtd_rx_desc mtd_rx_list[MTD_RX_LIST_CNT];
108 struct mtd_tx_desc mtd_tx_list[MTD_TX_LIST_CNT];
109 };
110
111
112 struct mtd_swdesc {
113 bus_dmamap_t sd_map;
114 struct mbuf *sd_mbuf;
115 };
116
117
118 struct mtd_chain_data {
119 struct mtd_swdesc mtd_rx_chain[MTD_RX_LIST_CNT];
120 struct mtd_swdesc mtd_tx_chain[MTD_TX_LIST_CNT];
121 int mtd_tx_prod;
122 int mtd_tx_cons;
123 int mtd_tx_cnt;
124 int mtd_rx_prod;
125 };
126
127
128 struct mtd_softc {
129 struct device sc_dev;
130 struct arpcom sc_arpcom;
131 struct mii_data sc_mii;
132 pci_product_id_t sc_devid;
133
134 bus_space_handle_t sc_bush;
135 bus_space_tag_t sc_bust;
136
137 struct mtd_list_data *mtd_ldata;
138 struct mtd_chain_data mtd_cdata;
139
140 bus_dma_tag_t sc_dmat;
141 bus_dmamap_t sc_listmap;
142 bus_dma_segment_t sc_listseg[1];
143 int sc_listnseg;
144 caddr_t sc_listkva;
145 bus_dmamap_t sc_rx_sparemap;
146 bus_dmamap_t sc_tx_sparemap;
147 };
148
149 __BEGIN_DECLS
150 void mtd_attach(struct mtd_softc *);
151 int mtd_intr(void *);
152 __END_DECLS
153
154 #endif /* __DEV_IC_MTD8XXVAR_H__ */