val 581 altq/altq_red.c int32_t val;
val 586 altq/altq_red.c val = 1 << FP_SHIFT;
val 588 altq/altq_red.c return (val);
val 594 altq/altq_red.c val = (val * w->w_tab[i]) >> FP_SHIFT;
val 600 altq/altq_red.c return (val);
val 826 altq/altq_subr.c u_int64_t val;
val 830 altq/altq_subr.c val = rdtsc();
val 847 altq/altq_subr.c val = ((u_int64_t)upper << 32) + pcc;
val 855 altq/altq_subr.c val = (((u_int64_t)(tv.tv_sec) * 1000000
val 858 altq/altq_subr.c return (val);
val 237 arch/i386/i386/amd64errata.c uint64_t val;
val 241 arch/i386/i386/amd64errata.c val = rdmsr_locked(e->e_data1, OPTERON_MSR_PASSCODE);
val 242 arch/i386/i386/amd64errata.c if ((val & e->e_data2) != 0)
val 252 arch/i386/i386/amd64errata.c uint64_t val;
val 256 arch/i386/i386/amd64errata.c val = rdmsr_locked(e->e_data1, OPTERON_MSR_PASSCODE);
val 257 arch/i386/i386/amd64errata.c if ((val & e->e_data2) != 0)
val 260 arch/i386/i386/amd64errata.c wrmsr_locked(e->e_data1, OPTERON_MSR_PASSCODE, val | e->e_data2);
val 264 arch/i386/i386/amd64errata.c val = rdmsr_locked(e->e_data1, OPTERON_MSR_PASSCODE);
val 265 arch/i386/i386/amd64errata.c if ((val & e->e_data2) != 0)
val 353 arch/i386/i386/esm.c struct esm_smb_resp_val *val = &resp.resp_val;
val 386 arch/i386/i386/esm.c es->es_sensor->value = esm_val2temp(val->v_reading);
val 389 arch/i386/i386/esm.c es->es_sensor->value = esm_val2volts(val->v_reading);
val 393 arch/i386/i386/esm.c esm_val2volts(val->v_reading) * 10;
val 396 arch/i386/i386/esm.c es->es_sensor->value = esm_val2amps(val->v_reading);
val 401 arch/i386/i386/esm.c (val->v_reading >> i * 8) & 0xf;
val 407 arch/i386/i386/esm.c (val->v_reading >> i) & 0x1;
val 411 arch/i386/i386/esm.c es->es_sensor->value = val->v_reading;
val 420 arch/i386/i386/esm.c if (val->v_reading >= es->es_thresholds.th_hi_crit ||
val 421 arch/i386/i386/esm.c val->v_reading <= es->es_thresholds.th_lo_crit) {
val 426 arch/i386/i386/esm.c if (val->v_reading >= es->es_thresholds.th_hi_warn ||
val 427 arch/i386/i386/esm.c val->v_reading <= es->es_thresholds.th_lo_warn) {
val 436 arch/i386/i386/esm.c if (val->v_status & ESM2_VS_PSU_FAIL) {
val 823 arch/i386/i386/esm.c struct esm_smb_resp_val *val = &resp.resp_val;
val 847 arch/i386/i386/esm.c val->v_reading, val->v_status, val->v_checksum);
val 851 arch/i386/i386/esm.c if (val->v_status == 0x00)
val 855 arch/i386/i386/esm.c if (!(val->v_status & ESM2_VS_VALID))
val 978 arch/i386/i386/esm.c esm_bmc_ready(struct esm_softc *sc, int port, u_int8_t mask, u_int8_t val,
val 984 arch/i386/i386/esm.c if ((EREAD(sc, port) & mask) == val)
val 77 arch/i386/i386/freebsd_machdep.c union sigval val)
val 83 arch/i386/i386/i686_mem.c int i686_mtrr2mrt(int val);
val 110 arch/i386/i386/i686_mem.c i686_mtrr2mrt(int val)
val 112 arch/i386/i386/i686_mem.c if (val < 0 || val >= MTRRTOMRTLEN)
val 114 arch/i386/i386/i686_mem.c return i686_mtrrtomrt[val];
val 250 arch/i386/i386/i686_mem.c int val;
val 252 arch/i386/i386/i686_mem.c if ((val = i686_mtrrtype(flags)) == -1)
val 254 arch/i386/i386/i686_mem.c return val & 0xff;
val 143 arch/i386/i386/ioapic.c u_int32_t val;
val 149 arch/i386/i386/ioapic.c val = *sc->sc_data;
val 151 arch/i386/i386/ioapic.c return (val);
val 156 arch/i386/i386/ioapic.c ioapic_write(struct ioapic_softc *sc, int regid, int val)
val 162 arch/i386/i386/ioapic.c *(sc->sc_data) = val;
val 108 arch/i386/i386/linux_machdep.c union sigval val)
val 632 arch/i386/i386/linux_machdep.c if (SCARG(uap, val))
val 1066 arch/i386/i386/machdep.c unsigned int val;
val 1083 arch/i386/i386/machdep.c val = regs[3];
val 1084 arch/i386/i386/machdep.c if (val & (1U << 31)) {
val 1110 arch/i386/i386/machdep.c val = regs[0];
val 1111 arch/i386/i386/machdep.c if (val >= 0xC0000001) {
val 1113 arch/i386/i386/machdep.c val = regs[3];
val 1115 arch/i386/i386/machdep.c val = 0;
val 1117 arch/i386/i386/machdep.c if (val & (C3_CPUID_HAS_RNG | C3_CPUID_HAS_ACE))
val 1121 arch/i386/i386/machdep.c if (val & C3_CPUID_HAS_RNG) {
val 1124 arch/i386/i386/machdep.c if (!(val & C3_CPUID_DO_RNG)) {
val 1134 arch/i386/i386/machdep.c if (val & C3_CPUID_HAS_ACE) {
val 1136 arch/i386/i386/machdep.c if (!(val & C3_CPUID_DO_ACE)) {
val 1147 arch/i386/i386/machdep.c if (val & C3_CPUID_HAS_ACE2) {
val 1149 arch/i386/i386/machdep.c if (!(val & C3_CPUID_DO_ACE2)) {
val 1160 arch/i386/i386/machdep.c if (val & C3_CPUID_HAS_PHE) {
val 1162 arch/i386/i386/machdep.c if (!(val & C3_CPUID_DO_PHE)) {
val 1173 arch/i386/i386/machdep.c if (val & C3_CPUID_HAS_PMM) {
val 1175 arch/i386/i386/machdep.c if (!(val & C3_CPUID_DO_PMM)) {
val 2118 arch/i386/i386/machdep.c union sigval val)
val 2122 arch/i386/i386/machdep.c sendsig(catcher, bsd_to_ibcs2_sig[sig], mask, code, type, val);
val 2161 arch/i386/i386/machdep.c union sigval val)
val 2237 arch/i386/i386/machdep.c initsiginfo(&frame.sf_si, sig, code, type, val);
val 175 arch/i386/i386/powernow-k8.c u_int val;
val 204 arch/i386/i386/powernow-k8.c val = cvid - (1 << cstate->mvs);
val 205 arch/i386/i386/powernow-k8.c WRITE_FIDVID(cfid, (val > 0) ? val : 0, 1ULL);
val 234 arch/i386/i386/powernow-k8.c val = cfid + 2;
val 236 arch/i386/i386/powernow-k8.c val = FID_TO_VCO_FID(cfid) + 2;
val 238 arch/i386/i386/powernow-k8.c val = cfid - 2;
val 239 arch/i386/i386/powernow-k8.c WRITE_FIDVID(val, cvid, (uint64_t)
val 310 arch/i386/i386/svr4_machdep.c union sigval val)
val 344 arch/i386/i386/svr4_machdep.c svr4_getsiginfo(&frame.sf_si, sig, code, type, val.sival_ptr);
val 82 arch/i386/i386/vm86.c #define putword(base, ptr, val) \
val 89 arch/i386/i386/vm86.c : "r" (base), "q" (val), "0" (ptr))
val 91 arch/i386/i386/vm86.c #define putdword(base, ptr, val) \
val 104 arch/i386/i386/vm86.c : "r" (base), "q" (val), "0" (ptr))
val 40 arch/i386/include/_types.h int val[6];
val 61 arch/i386/include/atomic.h i386_atomic_testset_uq(volatile u_int64_t *ptr, u_int64_t val)
val 63 arch/i386/include/atomic.h __asm__ volatile ("\n1:\t" LOCK " cmpxchg8b (%1); jnz 1b" : "+A" (val) :
val 64 arch/i386/include/atomic.h "r" (ptr), "b" ((u_int32_t)val), "c" ((u_int32_t)(val >> 32)));
val 65 arch/i386/include/atomic.h return val;
val 69 arch/i386/include/atomic.h i386_atomic_testset_ul(volatile u_int32_t *ptr, unsigned long val)
val 71 arch/i386/include/atomic.h __asm__ volatile ("xchgl %0,(%2)" :"=r" (val):"0" (val),"r" (ptr));
val 72 arch/i386/include/atomic.h return val;
val 76 arch/i386/include/atomic.h i386_atomic_testset_i(volatile int *ptr, unsigned long val)
val 78 arch/i386/include/atomic.h __asm__ volatile ("xchgl %0,(%2)" :"=r" (val):"0" (val),"r" (ptr));
val 79 arch/i386/include/atomic.h return val;
val 95 arch/i386/include/cpufunc.h lcr0(u_int val)
val 97 arch/i386/include/cpufunc.h __asm __volatile("movl %0,%%cr0" : : "r" (val));
val 103 arch/i386/include/cpufunc.h u_int val;
val 104 arch/i386/include/cpufunc.h __asm __volatile("movl %%cr0,%0" : "=r" (val));
val 105 arch/i386/include/cpufunc.h return val;
val 111 arch/i386/include/cpufunc.h u_int val;
val 112 arch/i386/include/cpufunc.h __asm __volatile("movl %%cr2,%0" : "=r" (val));
val 113 arch/i386/include/cpufunc.h return val;
val 117 arch/i386/include/cpufunc.h lcr3(u_int val)
val 119 arch/i386/include/cpufunc.h __asm __volatile("movl %0,%%cr3" : : "r" (val));
val 125 arch/i386/include/cpufunc.h u_int val;
val 126 arch/i386/include/cpufunc.h __asm __volatile("movl %%cr3,%0" : "=r" (val));
val 127 arch/i386/include/cpufunc.h return val;
val 131 arch/i386/include/cpufunc.h lcr4(u_int val)
val 133 arch/i386/include/cpufunc.h __asm __volatile("movl %0,%%cr4" : : "r" (val));
val 139 arch/i386/include/cpufunc.h u_int val;
val 140 arch/i386/include/cpufunc.h __asm __volatile("movl %%cr4,%0" : "=r" (val));
val 141 arch/i386/include/cpufunc.h return val;
val 147 arch/i386/include/cpufunc.h u_int val;
val 148 arch/i386/include/cpufunc.h __asm __volatile("movl %%cr3,%0" : "=r" (val));
val 149 arch/i386/include/cpufunc.h __asm __volatile("movl %0,%%cr3" : : "r" (val));
val 59 arch/i386/include/i82489var.h i82489_writereg(reg, val)
val 61 arch/i386/include/i82489var.h u_int32_t val;
val 64 arch/i386/include/i82489var.h val;
val 71 arch/i386/include/i82489var.h val = *((volatile u_int32_t *)(((volatile u_int8_t *)local_apic) +
val 194 arch/i386/pci/ali1543.c int val;
val 203 arch/i386/pci/ali1543.c val = ALI1543_PIRQ(reg, clink);
val 204 arch/i386/pci/ali1543.c *irqp = (val == 0) ?
val 205 arch/i386/pci/ali1543.c I386_PCI_INTERRUPT_LINE_NO_CONNECTION : val;
val 214 arch/i386/pci/ali1543.c int shift, val;
val 221 arch/i386/pci/ali1543.c ali1543_get_intr(v, clink, &val);
val 226 arch/i386/pci/ali1543.c if (ali1543_get_intr(v, clink, &val) != 0 || val != irq)
val 149 arch/i386/pci/amd756.c int val;
val 155 arch/i386/pci/amd756.c val = (reg >> (4*clink)) & 0x0f;
val 156 arch/i386/pci/amd756.c *irqp = (val == 0) ?
val 157 arch/i386/pci/amd756.c I386_PCI_INTERRUPT_LINE_NO_CONNECTION : val;
val 166 arch/i386/pci/amd756.c int val;
val 173 arch/i386/pci/amd756.c amd756_get_intr(v, clink, &val);
val 84 arch/i386/pci/elan520.c #define elansc_wdogctl_write(sc, val) elansc_wdogctl(sc, 0, val)
val 257 arch/i386/pci/elan520.c elansc_wdogctl(struct elansc_softc *sc, int do_reset, uint16_t val)
val 284 arch/i386/pci/elan520.c val);
val 31 arch/i386/pci/gscpmreg.h #define GSCPM_P_CNT_CLK(val) ((val) & 0x7)
val 162 arch/i386/pci/opti82c558.c int val;
val 168 arch/i386/pci/opti82c558.c val = VIPER_PIRQ(reg, clink);
val 169 arch/i386/pci/opti82c558.c *irqp = (val == VIPER_PIRQ_NONE) ? 0xff : viper_pirq_decode[val];
val 204 arch/i386/pci/opti82c700.c int val, addrofs, ofs;
val 210 arch/i386/pci/opti82c700.c val = (reg >> ofs) & FIRESTAR_CFG_PIRQ_MASK;
val 212 arch/i386/pci/opti82c700.c *irqp = (val == FIRESTAR_PIRQ_NONE) ?
val 213 arch/i386/pci/opti82c700.c I386_PCI_INTERRUPT_LINE_NO_CONNECTION : val;
val 243 arch/i386/pci/opti82c700.c int i, val, addrofs, ofs;
val 259 arch/i386/pci/opti82c700.c val = (reg >> ofs) & FIRESTAR_CFG_PIRQ_MASK;
val 260 arch/i386/pci/opti82c700.c if (val != irq)
val 262 arch/i386/pci/opti82c700.c val = ((reg >> ofs) >> FIRESTAR_TRIGGER_SHIFT) &
val 264 arch/i386/pci/opti82c700.c *triggerp = val ? IST_LEVEL : IST_EDGE;
val 275 arch/i386/pci/opti82c700.c val = (reg >> ofs) & FIRESTAR_CFG_PIRQ_MASK;
val 276 arch/i386/pci/opti82c700.c if (val != irq)
val 289 arch/i386/pci/opti82c700.c int i, val, addrofs, ofs;
val 304 arch/i386/pci/opti82c700.c val = (reg >> ofs) & FIRESTAR_CFG_PIRQ_MASK;
val 305 arch/i386/pci/opti82c700.c if (val != irq)
val 324 arch/i386/pci/opti82c700.c val = (reg >> ofs) & FIRESTAR_CFG_PIRQ_MASK;
val 325 arch/i386/pci/opti82c700.c if (val != irq)
val 185 arch/i386/pci/pci_addr_fixup.c pcireg_t val, mask;
val 190 arch/i386/pci/pci_addr_fixup.c val = pci_conf_read(pc, tag, PCI_BHLC_REG);
val 191 arch/i386/pci/pci_addr_fixup.c switch (PCI_HDRTYPE_TYPE(val)) {
val 194 arch/i386/pci/pci_addr_fixup.c PCI_HDRTYPE_TYPE(val));
val 214 arch/i386/pci/pci_addr_fixup.c val = pci_conf_read(pc, tag, mapreg);
val 218 arch/i386/pci/pci_addr_fixup.c pci_conf_write(pc, tag, mapreg, val);
val 220 arch/i386/pci/pci_addr_fixup.c type = PCI_MAPREG_TYPE(val);
val 223 arch/i386/pci/pci_addr_fixup.c if (PCI_MAPREG_MEM_TYPE(val) ==
val 236 arch/i386/pci/pci_addr_fixup.c addr = PCI_MAPREG_MEM_ADDR(val);
val 241 arch/i386/pci/pci_addr_fixup.c addr = PCI_MAPREG_IO_ADDR(val) & PCIADDR_PORT_END;
val 314 arch/i386/pci/pci_addr_fixup.c pcireg_t val;
val 320 arch/i386/pci/pci_addr_fixup.c val = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
val 322 arch/i386/pci/pci_addr_fixup.c (val & PCI_COMMAND_MEM_ENABLE) != PCI_COMMAND_MEM_ENABLE)
val 325 arch/i386/pci/pci_addr_fixup.c (val & PCI_COMMAND_IO_ENABLE) != PCI_COMMAND_IO_ENABLE)
val 343 arch/i386/pci/pci_addr_fixup.c pcireg_t val;
val 349 arch/i386/pci/pci_addr_fixup.c val = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
val 351 arch/i386/pci/pci_addr_fixup.c (val & PCI_COMMAND_MEM_ENABLE) == PCI_COMMAND_MEM_ENABLE)
val 354 arch/i386/pci/pci_addr_fixup.c (val & PCI_COMMAND_IO_ENABLE) == PCI_COMMAND_IO_ENABLE)
val 371 arch/i386/pci/pci_addr_fixup.c pciaddr_ioaddr(u_int32_t val)
val 373 arch/i386/pci/pci_addr_fixup.c return ((PCI_MAPREG_TYPE(val) == PCI_MAPREG_TYPE_MEM)
val 374 arch/i386/pci/pci_addr_fixup.c ? PCI_MAPREG_MEM_ADDR(val)
val 375 arch/i386/pci/pci_addr_fixup.c : (PCI_MAPREG_IO_ADDR(val) & PCIADDR_PORT_END));
val 313 arch/i386/pci/pci_machdep.c u_int32_t sav, val;
val 376 arch/i386/pci/pci_machdep.c val = inl(PCI_MODE1_ADDRESS_REG);
val 377 arch/i386/pci/pci_machdep.c if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) {
val 380 arch/i386/pci/pci_machdep.c val);
val 385 arch/i386/pci/pci_machdep.c val = inl(PCI_MODE1_ADDRESS_REG);
val 386 arch/i386/pci/pci_machdep.c if ((val & 0x80fffffc) != 0)
val 189 arch/i386/pci/via8231.c int reg, val;
val 196 arch/i386/pci/via8231.c val = VIA8231_GET_ROUTING_CNFG(reg, clink);
val 199 arch/i386/pci/via8231.c val = (reg >> ((clink & 3) * 4)) & 0xf;
val 202 arch/i386/pci/via8231.c *irqp = (val == VIA8231_ROUTING_CNFG_DISABLED) ?
val 203 arch/i386/pci/via8231.c I386_PCI_INTERRUPT_LINE_NO_CONNECTION : val;
val 162 arch/i386/pci/via82c586.c int val;
val 168 arch/i386/pci/via82c586.c val = VP3_PIRQ(reg, clink);
val 169 arch/i386/pci/via82c586.c *irqp = (val == VP3_PIRQ_NONE)?
val 170 arch/i386/pci/via82c586.c I386_PCI_INTERRUPT_LINE_NO_CONNECTION : val;
val 179 arch/i386/pci/via82c586.c int shift, val;
val 186 arch/i386/pci/via82c586.c via82c586_get_intr(v, clink, &val);
val 191 arch/i386/pci/via82c586.c if (via82c586_get_intr(v, clink, &val) != 0 ||
val 192 arch/i386/pci/via82c586.c val != irq)
val 145 arch/i386/stand/pxeboot/net.c u_long val;
val 157 arch/i386/stand/pxeboot/net.c val = 0;
val 160 arch/i386/stand/pxeboot/net.c val = (val * 10) + (c - '0');
val 173 arch/i386/stand/pxeboot/net.c if (pp >= parts + 3 || val > 0xff)
val 175 arch/i386/stand/pxeboot/net.c *pp++ = val, cp++;
val 196 arch/i386/stand/pxeboot/net.c if (val > 0xffffff)
val 198 arch/i386/stand/pxeboot/net.c val |= parts[0] << 24;
val 202 arch/i386/stand/pxeboot/net.c if (val > 0xffff)
val 204 arch/i386/stand/pxeboot/net.c val |= (parts[0] << 24) | (parts[1] << 16);
val 208 arch/i386/stand/pxeboot/net.c if (val > 0xff)
val 210 arch/i386/stand/pxeboot/net.c val |= (parts[0] << 24) | (parts[1] << 16) | (parts[2] << 8);
val 214 arch/i386/stand/pxeboot/net.c return (htonl(val));
val 80 compat/common/vfs_syscalls_25.c osp->f_fsid.val[0] = osp->f_fsid.val[1] = 0;
val 553 compat/freebsd/freebsd_file.c fsp->f_fsid.val[0] = fsp->f_fsid.val[1] = 0;
val 70 compat/hpux/m68k/hpux_net.c syscallarg(caddr_t) val;
val 209 compat/hpux/m68k/hpux_net.c if (SCARG(uap, val)) {
val 211 compat/hpux/m68k/hpux_net.c if ((error = copyin(SCARG(uap, val), mtod(m, caddr_t),
val 254 compat/hpux/m68k/hpux_net.c if (SCARG(uap, val)) {
val 256 compat/hpux/m68k/hpux_net.c if ((error = copyin(SCARG(uap, val), mtod(m, caddr_t),
val 283 compat/hpux/m68k/hpux_net.c if (SCARG(uap, val)) {
val 293 compat/hpux/m68k/hpux_net.c if (SCARG(uap, val) && valsize && m != NULL) {
val 303 compat/hpux/m68k/hpux_net.c error = copyout(mtod(m, caddr_t), SCARG(uap, val),
val 371 compat/hpux/m68k/hpux_syscallargs.h syscallarg(caddr_t) val;
val 128 compat/ibcs2/ibcs2_exec.h #define COFF_ROUND(val, by) (((val) + by - 1) & ~(by - 1))
val 1340 compat/ibcs2/ibcs2_misc.c int val, error;
val 1344 compat/ibcs2/ibcs2_misc.c val = IBCS2_FP_NO;
val 1346 compat/ibcs2/ibcs2_misc.c val = IBCS2_FP_SW;
val 1348 compat/ibcs2/ibcs2_misc.c val = IBCS2_FP_387; /* a real coprocessor */
val 1350 compat/ibcs2/ibcs2_misc.c if ((error = copyout((caddr_t)&val, (caddr_t)SCARG(uap, arg),
val 1351 compat/ibcs2/ibcs2_misc.c sizeof(val))))
val 312 compat/linux/linux_file.c int fd, cmd, error, val;
val 348 compat/linux/linux_file.c val = linux_to_bsd_ioflags((int)SCARG(uap, arg));
val 351 compat/linux/linux_file.c SCARG(&fca, arg) = (caddr_t) val;
val 406 compat/linux/linux_misc.c lsp->l_ffsid.val[0] = bsp->f_fsid.val[0];
val 407 compat/linux/linux_misc.c lsp->l_ffsid.val[1] = bsp->f_fsid.val[1];
val 320 compat/linux/linux_socket.c SCARG(&bga, val) = status;
val 558 compat/linux/linux_socket.c caddr_t val;
val 560 compat/linux/linux_socket.c int size_val = sizeof val;
val 563 compat/linux/linux_socket.c val = stackgap_alloc(sgp, sizeof(optval));
val 571 compat/linux/linux_socket.c SCARG(&gsa, val) = val;
val 576 compat/linux/linux_socket.c if ((error = copyin(val, &optval, sizeof(optval))))
val 916 compat/linux/linux_socket.c SCARG(&bsa, val) = lsa.optval;
val 968 compat/linux/linux_socket.c SCARG(&bga, val) = lga.optval;
val 261 compat/linux/linux_syscallargs.h syscallarg(int) val;
val 39 compat/linux/linux_types.h long val[2];
val 562 compat/sunos/sunos_misc.c if (SCARG(uap, val)) {
val 564 compat/sunos/sunos_misc.c error = copyin(SCARG(uap, val), mtod(m, caddr_t),
val 134 compat/sunos/sunos_syscallargs.h syscallarg(caddr_t) val;
val 203 compat/svr4/svr4_ipc.c SCARG(&ap, arg)->val = (int) SCARG(uap, arg);
val 1149 compat/svr4/svr4_misc.c sfs->f_fsid = bfs->f_fsid.val[0];
val 1175 compat/svr4/svr4_misc.c sfs->f_fsid = bfs->f_fsid.val[0];
val 365 compat/ultrix/ultrix_misc.c if (SCARG(uap, val)) {
val 367 compat/ultrix/ultrix_misc.c if ((error = copyin(SCARG(uap, val), mtod(m, caddr_t),
val 115 compat/ultrix/ultrix_syscallargs.h syscallarg(caddr_t) val;
val 210 ddb/db_output.c db_format(char *buf, size_t bufsize, long val, int format, int alt, int width)
val 222 ddb/db_output.c if (val < 0 && format != DB_FORMAT_N)
val 223 ddb/db_output.c val = -val;
val 227 ddb/db_output.c snprintf(buf, bufsize, fmt, width, val);
val 445 ddb/db_sym.c db_search_symbol(db_addr_t val, db_strategy_t strategy, db_expr_t *offp)
val 457 ddb/db_sym.c sym = X_db_search_symbol(&db_symtabs[i], val, strategy, &newdiff);
val 134 ddb/db_sym.h #define db_find_sym_and_offset(val,namep,offp) \
val 135 ddb/db_sym.h db_symbol_values(db_search_symbol(val,DB_STGY_ANY,offp),namep,0)
val 138 ddb/db_sym.h #define db_find_xtrn_sym_and_offset(val,namep,offp) \
val 139 ddb/db_sym.h db_symbol_values(db_search_symbol(val,DB_STGY_XTRN,offp),namep,0)
val 202 dev/acpi/acpicpu.c acpicpu_add_cstatepkg(struct aml_value *val, void *arg)
val 207 dev/acpi/acpicpu.c aml_showvalue(val, 0);
val 209 dev/acpi/acpicpu.c if (val->type != AML_OBJTYPE_PACKAGE || val->length != 4)
val 211 dev/acpi/acpicpu.c acpicpu_add_cstate(sc, val->v_package[1]->v_integer,
val 212 dev/acpi/acpicpu.c val->v_package[2]->v_integer,
val 213 dev/acpi/acpicpu.c val->v_package[3]->v_integer,
val 197 dev/acpi/acpidebug.c db_aml_objtype(struct aml_value *val)
val 199 dev/acpi/acpidebug.c if (val == NULL)
val 202 dev/acpi/acpidebug.c switch (val->type) {
val 239 dev/acpi/acpidebug.c return aml_mnem(val->v_field.type, NULL);
val 118 dev/acpi/acpiec.c acpiec_wait(struct acpiec_softc *sc, u_int8_t mask, u_int8_t val)
val 124 dev/acpi/acpiec.c "\20\x8IGN\x7SMI\x6SCI\05BURST\04CMD\03IGN\02IBF\01OBF", (int)val);
val 126 dev/acpi/acpiec.c while (((stat = acpiec_status(sc)) & mask) != val) {
val 146 dev/acpi/acpiec.c acpiec_write_data(struct acpiec_softc *sc, u_int8_t val)
val 149 dev/acpi/acpiec.c dnprintf(40, "acpiec: write_data -- %d\n", (int)val);
val 150 dev/acpi/acpiec.c bus_space_write_1(sc->sc_data_bt, sc->sc_data_bh, 0, val);
val 154 dev/acpi/acpiec.c acpiec_write_cmd(struct acpiec_softc *sc, u_int8_t val)
val 157 dev/acpi/acpiec.c dnprintf(40, "acpiec: write_cmd -- %d\n", (int)val);
val 158 dev/acpi/acpiec.c bus_space_write_1(sc->sc_cmd_bt, sc->sc_cmd_bh, 0, val);
val 164 dev/acpi/acpiec.c u_int8_t val;
val 167 dev/acpi/acpiec.c dnprintf(40, "acpiec: read_data\n", (int)val);
val 168 dev/acpi/acpiec.c val = bus_space_read_1(sc->sc_data_bt, sc->sc_data_bh, 0);
val 170 dev/acpi/acpiec.c return (val);
val 196 dev/acpi/acpiec.c u_int8_t val;
val 204 dev/acpi/acpiec.c val = acpiec_read_data(sc);
val 206 dev/acpi/acpiec.c return (val);
val 77 dev/acpi/dsdt.c void _aml_delref(struct aml_value **val, const char *, int);
val 469 dev/acpi/dsdt.c acpi_mutex_acquire(struct aml_value *val, int timeout)
val 476 dev/acpi/dsdt.c struct acpi_mutex *mtx = val->v_mutex;
val 479 dev/acpi/dsdt.c if (val->type != AML_OBJTYPE_MUTEX) {
val 509 dev/acpi/dsdt.c acpi_mutex_release(struct aml_value *val)
val 513 dev/acpi/dsdt.c struct acpi_mutex *mtx = val->v_mutex;
val 516 dev/acpi/dsdt.c if (val->type != AML_OBJTYPE_MUTEX) {
val 561 dev/acpi/dsdt.c aml_setbit(u_int8_t *pb, int bit, int val)
val 565 dev/acpi/dsdt.c if (val)
val 1048 dev/acpi/dsdt.c aml_getbuffer(struct aml_value *val, int *bitlen)
val 1050 dev/acpi/dsdt.c switch (val->type) {
val 1054 dev/acpi/dsdt.c return (&val->v_integer);
val 1058 dev/acpi/dsdt.c *bitlen = val->length<<3;
val 1059 dev/acpi/dsdt.c return (val->v_buffer);
val 1260 dev/acpi/dsdt.c aml_showvalue(struct aml_value *val, int lvl)
val 1264 dev/acpi/dsdt.c if (val == NULL)
val 1267 dev/acpi/dsdt.c if (val->node)
val 1268 dev/acpi/dsdt.c printf(" [%s]", aml_nodename(val->node));
val 1269 dev/acpi/dsdt.c printf(" %p cnt:%.2x stk:%.2x", val, val->refcnt, val->stack);
val 1270 dev/acpi/dsdt.c switch (val->type) {
val 1273 dev/acpi/dsdt.c printf(" integer: %llx\n", val->v_integer);
val 1276 dev/acpi/dsdt.c printf(" string: %s\n", val->v_string);
val 1279 dev/acpi/dsdt.c printf(" method: %.2x\n", val->v_method.flags);
val 1282 dev/acpi/dsdt.c printf(" package: %.2x\n", val->length);
val 1283 dev/acpi/dsdt.c for (idx = 0; idx < val->length; idx++)
val 1284 dev/acpi/dsdt.c aml_showvalue(val->v_package[idx], lvl);
val 1287 dev/acpi/dsdt.c printf(" buffer: %.2x {", val->length);
val 1288 dev/acpi/dsdt.c for (idx = 0; idx < val->length; idx++)
val 1289 dev/acpi/dsdt.c printf("%s%.2x", idx ? ", " : "", val->v_buffer[idx]);
val 1295 dev/acpi/dsdt.c val->v_field.bitpos, val->v_field.bitlen,
val 1296 dev/acpi/dsdt.c val->v_field.ref1, val->v_field.ref2,
val 1297 dev/acpi/dsdt.c aml_mnem(val->v_field.type, NULL));
val 1298 dev/acpi/dsdt.c aml_showvalue(val->v_field.ref1, lvl);
val 1299 dev/acpi/dsdt.c aml_showvalue(val->v_field.ref2, lvl);
val 1303 dev/acpi/dsdt.c val->v_mutex ? val->v_mutex->amt_name : "",
val 1304 dev/acpi/dsdt.c val->v_mutex ? val->v_mutex->amt_ref_count : 0);
val 1311 dev/acpi/dsdt.c val->v_opregion.iospace, val->v_opregion.iobase,
val 1312 dev/acpi/dsdt.c val->v_opregion.iolen);
val 1315 dev/acpi/dsdt.c printf(" nameref: %s\n", aml_getname(val->v_nameref));
val 1322 dev/acpi/dsdt.c val->v_processor.proc_id, val->v_processor.proc_addr,
val 1323 dev/acpi/dsdt.c val->v_processor.proc_len);
val 1330 dev/acpi/dsdt.c val->v_powerrsrc.pwr_level, val->v_powerrsrc.pwr_order);
val 1333 dev/acpi/dsdt.c printf(" objref: %p index:%x\n", val->v_objref.ref,
val 1334 dev/acpi/dsdt.c val->v_objref.index);
val 1335 dev/acpi/dsdt.c aml_showvalue(val->v_objref.ref, lvl);
val 1338 dev/acpi/dsdt.c printf(" !!type: %x\n", val->type);
val 1576 dev/acpi/dsdt.c int is_local(struct aml_scope *scope, struct aml_value *val)
val 1578 dev/acpi/dsdt.c return val->stack;
val 1688 dev/acpi/dsdt.c aml_freevalue(struct aml_value *val)
val 1692 dev/acpi/dsdt.c if (val == NULL)
val 1694 dev/acpi/dsdt.c switch (val->type) {
val 1696 dev/acpi/dsdt.c acpi_os_free(val->v_string);
val 1699 dev/acpi/dsdt.c acpi_os_free(val->v_buffer);
val 1702 dev/acpi/dsdt.c for (idx = 0; idx < val->length; idx++) {
val 1703 dev/acpi/dsdt.c aml_freevalue(val->v_package[idx]);
val 1704 dev/acpi/dsdt.c acpi_os_free(val->v_package[idx]);
val 1706 dev/acpi/dsdt.c acpi_os_free(val->v_package);
val 1710 dev/acpi/dsdt.c aml_delref(&val->v_field.ref1);
val 1711 dev/acpi/dsdt.c aml_delref(&val->v_field.ref2);
val 1714 dev/acpi/dsdt.c val->type = 0;
val 1715 dev/acpi/dsdt.c memset(&val->_, 0, sizeof(val->_));
val 1720 dev/acpi/dsdt.c aml_addref(struct aml_value *val)
val 1722 dev/acpi/dsdt.c if (val)
val 1723 dev/acpi/dsdt.c val->refcnt++;
val 1729 dev/acpi/dsdt.c _aml_delref(struct aml_value **val, const char *fn, int line)
val 1731 dev/acpi/dsdt.c if (val == NULL || *val == NULL)
val 1733 dev/acpi/dsdt.c if ((*val)->stack > 0) {
val 1737 dev/acpi/dsdt.c if ((*val)->refcnt & ~0xFF)
val 1738 dev/acpi/dsdt.c printf("-- invalid ref: %x:%s:%d\n", (*val)->refcnt, fn, line);
val 1739 dev/acpi/dsdt.c if (--(*val)->refcnt == 0) {
val 1740 dev/acpi/dsdt.c aml_freevalue(*val);
val 1741 dev/acpi/dsdt.c acpi_os_free(*val);
val 1742 dev/acpi/dsdt.c *val = NULL;
val 1753 dev/acpi/dsdt.c aml_convradix(u_int64_t val, int iradix, int oradix)
val 1759 dev/acpi/dsdt.c while (val) {
val 1760 dev/acpi/dsdt.c rv += (val % iradix) * pwr;
val 1761 dev/acpi/dsdt.c val /= iradix;
val 1769 dev/acpi/dsdt.c aml_lsb(u_int64_t val)
val 1773 dev/acpi/dsdt.c if (val == 0)
val 1776 dev/acpi/dsdt.c for (lsb = 1; !(val & 0x1); lsb++)
val 1777 dev/acpi/dsdt.c val >>= 1;
val 1784 dev/acpi/dsdt.c aml_msb(u_int64_t val)
val 1788 dev/acpi/dsdt.c if (val == 0)
val 1791 dev/acpi/dsdt.c for (msb = 1; val != 0x1; msb++)
val 1792 dev/acpi/dsdt.c val >>= 1;
val 1961 dev/acpi/dsdt.c aml_callmethod(struct aml_scope *scope, struct aml_value *val)
val 1964 dev/acpi/dsdt.c aml_parseterm(scope, val);
val 1965 dev/acpi/dsdt.c return val;
val 2254 dev/acpi/dsdt.c void aml_resize(struct aml_value *val, int newsize);
val 2257 dev/acpi/dsdt.c aml_resize(struct aml_value *val, int newsize)
val 2262 dev/acpi/dsdt.c if (val->length >= newsize)
val 2264 dev/acpi/dsdt.c oldsize = val->length;
val 2265 dev/acpi/dsdt.c switch (val->type) {
val 2267 dev/acpi/dsdt.c oldptr = val->v_buffer;
val 2268 dev/acpi/dsdt.c _aml_setvalue(val, val->type, newsize, NULL);
val 2269 dev/acpi/dsdt.c memcpy(val->v_buffer, oldptr, oldsize);
val 2273 dev/acpi/dsdt.c oldptr = val->v_string;
val 2274 dev/acpi/dsdt.c _aml_setvalue(val, val->type, newsize+1, NULL);
val 2275 dev/acpi/dsdt.c memcpy(val->v_string, oldptr, oldsize);
val 3321 dev/acpi/dsdt.c aml_callosi(struct aml_scope *scope, struct aml_value *val)
val 3338 dev/acpi/dsdt.c aml_setvalue(scope, val, NULL, result);
val 3339 dev/acpi/dsdt.c return val;
val 3496 dev/acpi/dsdt.c struct aml_value *val = arg;
val 3503 dev/acpi/dsdt.c else if (val->type == AML_OBJTYPE_NAMEREF) {
val 3504 dev/acpi/dsdt.c node = aml_searchname(node, val->v_nameref);
val 3506 dev/acpi/dsdt.c _aml_setvalue(val, AML_OBJTYPE_OBJREF, -1,
val 3509 dev/acpi/dsdt.c } else if (val->type == AML_OBJTYPE_PACKAGE) {
val 3510 dev/acpi/dsdt.c for (i = 0; i < val->length; i++)
val 3511 dev/acpi/dsdt.c aml_fixup_node(node, val->v_package[i]);
val 3512 dev/acpi/dsdt.c } else if (val->type == AML_OBJTYPE_OPREGION) {
val 3513 dev/acpi/dsdt.c if (val->v_opregion.iospace != GAS_PCI_CFG_SPACE)
val 3515 dev/acpi/dsdt.c if (ACPI_PCI_FN(val->v_opregion.iobase) != 0xFFFF)
val 3517 dev/acpi/dsdt.c val->v_opregion.iobase =
val 3518 dev/acpi/dsdt.c ACPI_PCI_REG(val->v_opregion.iobase) +
val 3521 dev/acpi/dsdt.c aml_nodename(node), val->v_opregion.iobase);
val 539 dev/adb/akbd.c int press, val;
val 543 dev/adb/akbd.c val = ADBK_KEYVAL(key);
val 557 dev/adb/akbd.c c = keyboard[val];
val 582 dev/adb/akbd.c wskbd_input(sc->sc_wskbddev, type, val);
val 110 dev/cardbus/cardbus_exrom.c u_int16_t val;
val 114 dev/cardbus/cardbus_exrom.c val = READ_INT16(romt, romh, addr + CARDBUS_EXROM_SIGNATURE);
val 115 dev/cardbus/cardbus_exrom.c if (val != 0xaa55) {
val 117 dev/cardbus/cardbus_exrom.c "%u: 0x%04x\n", __func__, rom_image, val));
val 443 dev/cardbus/cardbusvar.h #define Cardbus_conf_write(ct, tag, offs, val) \
val 444 dev/cardbus/cardbusvar.h (*(ct)->ct_cf->cardbus_conf_write)((ct)->ct_cf, (tag), (offs), (val))
val 445 dev/cardbus/cardbusvar.h #define cardbus_conf_write(cc, cf, tag, offs, val) \
val 446 dev/cardbus/cardbusvar.h ((cf)->cardbus_conf_write)((cc), (tag), (offs), (val))
val 75 dev/cardbus/rbus.c int val;
val 122 dev/cardbus/rbus.c val = 1;
val 125 dev/cardbus/rbus.c val = extent_alloc_subregion(
val 133 dev/cardbus/rbus.c if (val == 0)
val 137 dev/cardbus/rbus.c if (val != 0) {
val 64 dev/dec/if_le_dec.c void le_dec_writereg(volatile u_short *regptr, u_short val);
val 96 dev/dec/if_le_dec.c le_dec_wrcsr(struct am7990_softc *sc, u_int16_t port, u_int16_t val)
val 101 dev/dec/if_le_dec.c LERDWR(port, val, ler1->ler1_rdp);
val 108 dev/dec/if_le_dec.c u_int16_t val;
val 111 dev/dec/if_le_dec.c LERDWR(0, ler1->ler1_rdp, val);
val 112 dev/dec/if_le_dec.c return (val);
val 121 dev/dec/if_le_dec.c le_dec_writereg(volatile u_short *regptr, u_short val)
val 125 dev/dec/if_le_dec.c while (*regptr != val) {
val 126 dev/dec/if_le_dec.c *regptr = val;
val 129 dev/dec/if_le_dec.c printf("le: Reg did not settle (to x%x): x%x\n", val,
val 109 dev/i2c/i2c_bitbang.c uint8_t val = 0;
val 116 dev/i2c/i2c_bitbang.c val <<= 1;
val 120 dev/i2c/i2c_bitbang.c val |= 1;
val 141 dev/i2c/i2c_bitbang.c *valp = val;
val 146 dev/i2c/i2c_bitbang.c i2c_bitbang_write_byte(void *v, uint8_t val, int flags,
val 156 dev/i2c/i2c_bitbang.c bit = (val & mask) ? SDA : 0;
val 124 dev/i2c/i2c_exec.c uint8_t val, int flags)
val 128 dev/i2c/i2c_exec.c &val, 1, flags));
val 334 dev/i2c/i2c_scan.c u_int8_t reg, val;
val 337 dev/i2c/i2c_scan.c val = iicprobe(0x00);
val 343 dev/i2c/i2c_scan.c if (val == iicprobe(reg))
val 348 dev/i2c/i2c_scan.c val = iicprobe(0x09);
val 350 dev/i2c/i2c_scan.c if (iicprobe(reg) != val)
val 384 dev/i2c/i2c_scan.c u_int8_t val, val2, max;
val 394 dev/i2c/i2c_scan.c val = iicprobe(0);
val 395 dev/i2c/i2c_scan.c iicvalcnt[val]++;
val 399 dev/i2c/i2c_scan.c if (val == val2)
val 403 dev/i2c/i2c_scan.c for (val = max = i = 0; i <= 0xff; i++)
val 406 dev/i2c/i2c_scan.c val = i;
val 412 dev/i2c/i2c_scan.c if (iicprobe(i) != val)
val 244 dev/i2c/lm75.c int val;
val 247 dev/i2c/lm75.c error = lmtemp_temp_read(sc, LM75_REG_TEMP, &val);
val 257 dev/i2c/lm75.c sc->sc_sensor.value = val * 500000 + 273150000;
val 127 dev/i2c/lm78_i2c.c lm_i2c_writereg(struct lm_softc *lmsc, int reg, int val)
val 135 dev/i2c/lm78_i2c.c data = val;
val 247 dev/i2c/rs5c372.c ricohrtc_reg_write(struct ricohrtc_softc *sc, int reg, uint8_t val)
val 255 dev/i2c/rs5c372.c &cmd, 1, &val, 1, I2C_F_POLL)) {
val 255 dev/i2o/iop.c iop_outl(struct iop_softc *sc, int off, u_int32_t val)
val 258 dev/i2o/iop.c bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val);
val 205 dev/ic/aacvar.h #define AAC_SETREG4(sc, reg, val) \
val 206 dev/ic/aacvar.h bus_space_write_4((sc)->aac_memt, (sc)->aac_memh, (reg), (val))
val 209 dev/ic/aacvar.h #define AAC_SETREG2(sc, reg, val) \
val 210 dev/ic/aacvar.h bus_space_write_2((sc)->aac_memt, (sc)->aac_memh, (reg), (val))
val 213 dev/ic/aacvar.h #define AAC_SETREG1(sc, reg, val) \
val 214 dev/ic/aacvar.h bus_space_write_1((sc)->aac_memt, (sc)->aac_memh, (reg), (val))
val 558 dev/ic/ac97.c ac97_read(struct ac97_softc *as, u_int8_t reg, u_int16_t *val)
val 566 dev/ic/ac97.c *val = as->shadow_reg[reg >> 1];
val 570 dev/ic/ac97.c if ((error = as->host_if->read(as->host_if->arg, reg, val)))
val 571 dev/ic/ac97.c *val = as->shadow_reg[reg >> 1];
val 576 dev/ic/ac97.c ac97_write(struct ac97_softc *as, u_int8_t reg, u_int16_t val)
val 578 dev/ic/ac97.c as->shadow_reg[reg >> 1] = val;
val 579 dev/ic/ac97.c return (as->host_if->write(as->host_if->arg, reg, val));
val 873 dev/ic/ac97.c u_int16_t val, newval;
val 880 dev/ic/ac97.c ac97_read(as, si->reg, &val);
val 882 dev/ic/ac97.c DPRINTFN(5, ("read(%x) = %x\n", si->reg, val));
val 945 dev/ic/ac97.c error = ac97_write(as, si->reg, (val & ~mask) | newval);
val 976 dev/ic/ac97.c u_int16_t val;
val 982 dev/ic/ac97.c ac97_read(as, si->reg, &val);
val 984 dev/ic/ac97.c DPRINTFN(5, ("read(%x) = %x\n", si->reg, val));
val 990 dev/ic/ac97.c cp->un.ord = (val >> si->ofs) & mask;
val 991 dev/ic/ac97.c DPRINTFN(4, ("AUDIO_MIXER_ENUM: %x %d %x %d\n", val, si->ofs,
val 1004 dev/ic/ac97.c l = r = (val >> si->ofs) & mask;
val 1007 dev/ic/ac97.c l = (val >> si->ofs) & mask;
val 1008 dev/ic/ac97.c r = (val >> (si->ofs + 8)) & mask;
val 1010 dev/ic/ac97.c r = (val >> si->ofs) & mask;
val 1011 dev/ic/ac97.c l = (val >> (si->ofs + 8)) & mask;
val 1048 dev/ic/ac97.c u_int16_t reg, val, regval, id = 0;
val 1071 dev/ic/ac97.c if (ac97_read(as, AC97_REG_POWER, &val) ||
val 1072 dev/ic/ac97.c ac97_write(as, AC97_REG_POWER, val |
val 1088 dev/ic/ac97.c if (ac97_write(as, AC97_REG_POWER, val))
val 46 dev/ic/ac97.h int (*read)(void *arg, u_int8_t reg, u_int16_t *val);
val 47 dev/ic/ac97.h int (*write)(void *arg, u_int8_t reg, u_int16_t val);
val 267 dev/ic/acx.c uint8_t val;
val 269 dev/ic/acx.c error = acx_read_eeprom(sc, i, &val);
val 272 dev/ic/acx.c printf("%02x ", val);
val 1454 dev/ic/acx.c acx_read_eeprom(struct acx_softc *sc, uint32_t offset, uint8_t *val)
val 1476 dev/ic/acx.c *val = CSR_READ_1(sc, ACXREG_EEPROM_DATA);
val 1482 dev/ic/acx.c acx_read_phyreg(struct acx_softc *sc, uint32_t reg, uint8_t *val)
val 1503 dev/ic/acx.c *val = CSR_READ_1(sc, ACXREG_PHY_DATA);
val 1509 dev/ic/acx.c acx_write_phyreg(struct acx_softc *sc, uint32_t reg, uint8_t val)
val 1511 dev/ic/acx.c CSR_WRITE_4(sc, ACXREG_PHY_DATA, val);
val 1690 dev/ic/acx.c uint32_t val;
val 1695 dev/ic/acx.c val = CSR_READ_4(sc, ACXREG_FWMEM_DATA);
val 1696 dev/ic/acx.c if (betoh32(fw[i]) != val) {
val 1698 dev/ic/acx.c ifp->if_xname, fw[i], val);
val 88 dev/ic/acxreg.h #define ACXREG(reg, val) [ACXREG_##reg] = val
val 443 dev/ic/acxreg.h #define CMD_WRITE_4(sc, val) \
val 445 dev/ic/acxreg.h (sc)->sc_cmd, (val))
val 86 dev/ic/acxvar.h #define CSR_WRITE_2(sc, reg, val) \
val 88 dev/ic/acxvar.h (sc)->chip_ioreg[(reg)], val)
val 89 dev/ic/acxvar.h #define CSR_WRITE_4(sc, reg, val) \
val 91 dev/ic/acxvar.h (sc)->chip_ioreg[(reg)], val)
val 102 dev/ic/acxvar.h #define FW_TXDESC_SETFIELD_1(sc, mb, field, val) \
val 104 dev/ic/acxvar.h (mb)->tb_fwdesc_ofs + offsetof(struct acx_fw_txdesc, field), (val))
val 105 dev/ic/acxvar.h #define FW_TXDESC_SETFIELD_2(sc, mb, field, val) \
val 107 dev/ic/acxvar.h (mb)->tb_fwdesc_ofs + offsetof(struct acx_fw_txdesc, field), (val))
val 108 dev/ic/acxvar.h #define FW_TXDESC_SETFIELD_4(sc, mb, field, val) \
val 110 dev/ic/acxvar.h (mb)->tb_fwdesc_ofs + offsetof(struct acx_fw_txdesc, field), (val))
val 775 dev/ic/advlib.c u_int8_t val;
val 777 dev/ic/advlib.c val = ASC_GET_CHIP_CONTROL(iot, ioh) &
val 784 dev/ic/advlib.c val |= ASC_CC_BANK_ONE;
val 788 dev/ic/advlib.c val |= ASC_CC_DIAG | ASC_CC_BANK_ONE;
val 792 dev/ic/advlib.c val &= ~ASC_CC_BANK_ONE;
val 795 dev/ic/advlib.c ASC_SET_CHIP_CONTROL(iot, ioh, val);
val 2024 dev/ic/advlib.c u_int16_t val;
val 2028 dev/ic/advlib.c val = ASC_GET_CHIP_LRAM_DATA(iot, ioh);
val 2029 dev/ic/advlib.c scsiq->d2.ccb_ptr = MAKELONG(val, ASC_GET_CHIP_LRAM_DATA(iot, ioh));
val 2030 dev/ic/advlib.c val = ASC_GET_CHIP_LRAM_DATA(iot, ioh);
val 2031 dev/ic/advlib.c scsiq->d2.target_ix = LO_BYTE(val);
val 2032 dev/ic/advlib.c scsiq->d2.flag = HI_BYTE(val);
val 2033 dev/ic/advlib.c val = ASC_GET_CHIP_LRAM_DATA(iot, ioh);
val 2034 dev/ic/advlib.c scsiq->d2.cdb_len = LO_BYTE(val);
val 2035 dev/ic/advlib.c scsiq->d2.tag_code = HI_BYTE(val);
val 2038 dev/ic/advlib.c val = ASC_GET_CHIP_LRAM_DATA(iot, ioh);
val 2039 dev/ic/advlib.c scsiq->d3.done_stat = LO_BYTE(val);
val 2040 dev/ic/advlib.c scsiq->d3.host_stat = HI_BYTE(val);
val 2041 dev/ic/advlib.c val = ASC_GET_CHIP_LRAM_DATA(iot, ioh);
val 2042 dev/ic/advlib.c scsiq->d3.scsi_stat = LO_BYTE(val);
val 2043 dev/ic/advlib.c scsiq->d3.scsi_msg = HI_BYTE(val);
val 2799 dev/ic/advlib.c u_int16_t val;
val 2805 dev/ic/advlib.c val = MAKEWORD(scsiq->q1.cntl, scsiq->q1.sg_queue_cnt);
val 2806 dev/ic/advlib.c ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
val 2807 dev/ic/advlib.c val = MAKEWORD(scsiq->q1.target_id, scsiq->q1.target_lun);
val 2808 dev/ic/advlib.c ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
val 2809 dev/ic/advlib.c val = LO_WORD(scsiq->q1.data_addr);
val 2810 dev/ic/advlib.c ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
val 2811 dev/ic/advlib.c val = HI_WORD(scsiq->q1.data_addr);
val 2812 dev/ic/advlib.c ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
val 2813 dev/ic/advlib.c val = LO_WORD(scsiq->q1.data_cnt);
val 2814 dev/ic/advlib.c ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
val 2815 dev/ic/advlib.c val = HI_WORD(scsiq->q1.data_cnt);
val 2816 dev/ic/advlib.c ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
val 2817 dev/ic/advlib.c val = LO_WORD(scsiq->q1.sense_addr);
val 2818 dev/ic/advlib.c ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
val 2819 dev/ic/advlib.c val = HI_WORD(scsiq->q1.sense_addr);
val 2820 dev/ic/advlib.c ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
val 2821 dev/ic/advlib.c val = MAKEWORD(scsiq->q1.sense_len, scsiq->q1.extra_bytes);
val 2822 dev/ic/advlib.c ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
val 2825 dev/ic/advlib.c val = LO_WORD(scsiq->q2.ccb_ptr);
val 2826 dev/ic/advlib.c ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
val 2827 dev/ic/advlib.c val = HI_WORD(scsiq->q2.ccb_ptr);
val 2828 dev/ic/advlib.c ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
val 2829 dev/ic/advlib.c val = MAKEWORD(scsiq->q2.target_ix, scsiq->q2.flag);
val 2830 dev/ic/advlib.c ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
val 2831 dev/ic/advlib.c val = MAKEWORD(scsiq->q2.cdb_len, scsiq->q2.tag_code);
val 2832 dev/ic/advlib.c ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
val 1243 dev/ic/advlib.h #define ASC_PUT_QDONE_IN_PROGRESS(iot, ioh, val) AscWriteLramByte((iot), (ioh), ASCV_Q_DONE_IN_PROGRESS_B, val)
val 1246 dev/ic/advlib.h #define ASC_PUT_VAR_FREE_QHEAD(iot, ioh, val) AscWriteLramWord((iot), (ioh), ASCV_FREE_Q_HEAD_W, val)
val 1247 dev/ic/advlib.h #define ASC_PUT_VAR_DONE_QTAIL(iot, ioh, val) AscWriteLramWord((iot), (ioh), ASCV_DONE_Q_TAIL_W, val)
val 1250 dev/ic/advlib.h #define ASC_PUT_RISC_VAR_FREE_QHEAD(iot, ioh, val) AscWriteLramByte((iot), (ioh), ASCV_NEXTRDY_B, val)
val 1251 dev/ic/advlib.h #define ASC_PUT_RISC_VAR_DONE_QTAIL(iot, ioh, val) AscWriteLramByte((iot), (ioh), ASCV_DONENEXT_B, val)
val 125 dev/ic/aic6915.c #define sf_funcreg_write(sc, reg, val) \
val 126 dev/ic/aic6915.c bus_space_write_4((sc)->sc_st, (sc)->sc_sh_func, (reg), (val))
val 143 dev/ic/aic6915.c sf_reg_write(struct sf_softc *sc, bus_addr_t reg, uint32_t val)
val 150 dev/ic/aic6915.c val);
val 154 dev/ic/aic6915.c bus_space_write_4(sc->sc_st, sc->sc_sh, reg, val);
val 159 dev/ic/aic6915.c #define sf_genreg_write(sc, reg, val) \
val 160 dev/ic/aic6915.c sf_reg_write((sc), (reg) + SF_GENREG_OFFSET, (val))
val 1469 dev/ic/aic6915.c sf_mii_write(struct device *self, int phy, int reg, int val)
val 1474 dev/ic/aic6915.c sf_genreg_write(sc, SF_MII_PHY_REG(phy, reg), val);
val 135 dev/ic/am79c930.c static void io_write_1 (sc, off, val)
val 138 dev/ic/am79c930.c u_int8_t val;
val 146 dev/ic/am79c930.c bus_space_write_1(sc->sc_iot, sc->sc_ioh, AM79C930_IODPA, val);
val 150 dev/ic/am79c930.c static void io_write_2 (sc, off, val)
val 153 dev/ic/am79c930.c u_int16_t val;
val 161 dev/ic/am79c930.c bus_space_write_1(sc->sc_iot,sc->sc_ioh,AM79C930_IODPA, val & 0xff);
val 163 dev/ic/am79c930.c bus_space_write_1(sc->sc_iot,sc->sc_ioh,AM79C930_IODPA, (val>>8)&0xff);
val 167 dev/ic/am79c930.c static void io_write_4 (sc, off, val)
val 170 dev/ic/am79c930.c u_int32_t val;
val 178 dev/ic/am79c930.c bus_space_write_1(sc->sc_iot,sc->sc_ioh,AM79C930_IODPA,val & 0xff);
val 180 dev/ic/am79c930.c bus_space_write_1(sc->sc_iot,sc->sc_ioh,AM79C930_IODPA,(val>>8)&0xff);
val 182 dev/ic/am79c930.c bus_space_write_1(sc->sc_iot,sc->sc_ioh,AM79C930_IODPA,(val>>16)&0xff);
val 184 dev/ic/am79c930.c bus_space_write_1(sc->sc_iot,sc->sc_ioh,AM79C930_IODPA,(val>>24)&0xff);
val 210 dev/ic/am79c930.c u_int8_t val;
val 217 dev/ic/am79c930.c val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, AM79C930_IODPA);
val 219 dev/ic/am79c930.c return val;
val 226 dev/ic/am79c930.c u_int16_t val;
val 233 dev/ic/am79c930.c val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, AM79C930_IODPA);
val 235 dev/ic/am79c930.c val |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, AM79C930_IODPA) << 8;
val 237 dev/ic/am79c930.c return val;
val 244 dev/ic/am79c930.c u_int32_t val;
val 251 dev/ic/am79c930.c val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, AM79C930_IODPA);
val 253 dev/ic/am79c930.c val |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, AM79C930_IODPA) << 8;
val 255 dev/ic/am79c930.c val |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, AM79C930_IODPA) << 16;
val 257 dev/ic/am79c930.c val |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, AM79C930_IODPA) << 24;
val 259 dev/ic/am79c930.c return val;
val 280 dev/ic/am79c930.c static void mem_write_1 (sc, off, val)
val 283 dev/ic/am79c930.c u_int8_t val;
val 285 dev/ic/am79c930.c bus_space_write_1(sc->sc_memt, sc->sc_memh, off, val);
val 288 dev/ic/am79c930.c static void mem_write_2 (sc, off, val)
val 291 dev/ic/am79c930.c u_int16_t val;
val 298 dev/ic/am79c930.c bus_space_write_2(t, h, off, val);
val 300 dev/ic/am79c930.c bus_space_write_1(t, h, off, val & 0xff);
val 301 dev/ic/am79c930.c bus_space_write_1(t, h, off+1, (val >> 8) & 0xff);
val 305 dev/ic/am79c930.c static void mem_write_4 (sc, off, val)
val 308 dev/ic/am79c930.c u_int32_t val;
val 315 dev/ic/am79c930.c bus_space_write_4(t, h, off, val);
val 317 dev/ic/am79c930.c bus_space_write_1(t, h, off, val & 0xff);
val 318 dev/ic/am79c930.c bus_space_write_1(t, h, off+1, (val >> 8) & 0xff);
val 319 dev/ic/am79c930.c bus_space_write_1(t, h, off+2, (val >> 16) & 0xff);
val 320 dev/ic/am79c930.c bus_space_write_1(t, h, off+3, (val >> 24) & 0xff);
val 176 dev/ic/an.c #define an_switch32(val) (val >> 16 | (val & 0xFFFF) << 16)
val 179 dev/ic/an.c #define an_switch32(val) val
val 584 dev/ic/an.c an_cmd(struct an_softc *sc, int cmd, int val)
val 596 dev/ic/an.c CSR_WRITE_2(sc, AN_PARAM0, val);
val 624 dev/ic/an.c sc->sc_dev.dv_xname, cmd, val);
val 631 dev/ic/an.c sc->sc_dev.dv_xname, cmd, val, stat,
val 49 dev/ic/anvar.h #define CSR_WRITE_2(sc, reg, val) \
val 50 dev/ic/anvar.h bus_space_write_2(sc->sc_iot, sc->sc_ioh, reg, val)
val 60 dev/ic/anvar.h #define CSR_WRITE_MULTI_STREAM_2(sc, reg, val, count) \
val 61 dev/ic/anvar.h bus_space_write_multi_stream_2(sc->sc_iot, sc->sc_ioh, reg, val, count)
val 238 dev/ic/ar5210.c ar5k_ar5210_nic_reset(struct ath_hal *hal, u_int32_t val)
val 241 dev/ic/ar5210.c u_int32_t mask = val ? val : ~0;
val 246 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_RC, val);
val 251 dev/ic/ar5210.c val &=
val 259 dev/ic/ar5210.c ret = ar5k_register_timeout(hal, AR5K_AR5210_RC, mask, val, AH_FALSE);
val 264 dev/ic/ar5210.c if ((val & AR5K_AR5210_RC_MAC) == 0) {
val 1630 dev/ic/ar5210.c ar5k_ar5210_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val)
val 1641 dev/ic/ar5210.c data |= (val&1) << gpio;
val 235 dev/ic/ar5211.c ar5k_ar5211_nic_reset(struct ath_hal *hal, u_int32_t val)
val 238 dev/ic/ar5211.c u_int32_t mask = val ? val : ~0;
val 246 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_RC, val);
val 251 dev/ic/ar5211.c val &=
val 257 dev/ic/ar5211.c ret = ar5k_register_timeout(hal, AR5K_AR5211_RC, mask, val, AH_FALSE);
val 262 dev/ic/ar5211.c if ((val & AR5K_AR5211_RC_PCU) == 0)
val 1736 dev/ic/ar5211.c ar5k_ar5211_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val)
val 1747 dev/ic/ar5211.c data |= (val&1) << gpio;
val 238 dev/ic/ar5212.c ar5k_ar5212_nic_reset(struct ath_hal *hal, u_int32_t val)
val 241 dev/ic/ar5212.c u_int32_t mask = val ? val : ~0;
val 249 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_RC, val);
val 254 dev/ic/ar5212.c val &=
val 260 dev/ic/ar5212.c ret = ar5k_register_timeout(hal, AR5K_AR5212_RC, mask, val, AH_FALSE);
val 265 dev/ic/ar5212.c if ((val & AR5K_AR5212_RC_PCU) == 0)
val 2031 dev/ic/ar5212.c ar5k_ar5212_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val)
val 2042 dev/ic/ar5212.c data |= (val&1) << gpio;
val 526 dev/ic/ar5xxx.c ar5k_printver(enum ar5k_srev_type type, u_int32_t val)
val 535 dev/ic/ar5xxx.c names[i].sr_val == val) {
val 544 dev/ic/ar5xxx.c if ((val & 0xff) < names[i + 1].sr_val) {
val 627 dev/ic/ar5xxx.c ar5k_bitswap(u_int32_t val, u_int bits)
val 630 dev/ic/ar5xxx.c val = ((val & 0xF0) >> 4) | ((val & 0x0F) << 4);
val 631 dev/ic/ar5xxx.c val = ((val & 0xCC) >> 2) | ((val & 0x33) << 2);
val 632 dev/ic/ar5xxx.c val = ((val & 0xAA) >> 1) | ((val & 0x55) << 1);
val 634 dev/ic/ar5xxx.c return val;
val 639 dev/ic/ar5xxx.c bit = (val >> i) & 1;
val 669 dev/ic/ar5xxx.c u_int32_t val, HAL_BOOL is_set)
val 678 dev/ic/ar5xxx.c else if ((data & flag) == val)
val 696 dev/ic/ar5xxx.c u_int16_t val;
val 703 dev/ic/ar5xxx.c val = (5 * bin) + 4800;
val 705 dev/ic/ar5xxx.c val = bin > 62 ?
val 710 dev/ic/ar5xxx.c val = bin + 2300;
val 712 dev/ic/ar5xxx.c val = bin + 2400;
val 715 dev/ic/ar5xxx.c return (val);
val 723 dev/ic/ar5xxx.c u_int16_t val;
val 726 dev/ic/ar5xxx.c AR5K_EEPROM_READ(o++, val);
val 727 dev/ic/ar5xxx.c ee->ee_switch_settling[mode] = (val >> 8) & 0x7f;
val 728 dev/ic/ar5xxx.c ee->ee_ant_tx_rx[mode] = (val >> 2) & 0x3f;
val 729 dev/ic/ar5xxx.c ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
val 731 dev/ic/ar5xxx.c AR5K_EEPROM_READ(o++, val);
val 732 dev/ic/ar5xxx.c ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
val 733 dev/ic/ar5xxx.c ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
val 734 dev/ic/ar5xxx.c ee->ee_ant_control[mode][i++] = val & 0x3f;
val 736 dev/ic/ar5xxx.c AR5K_EEPROM_READ(o++, val);
val 737 dev/ic/ar5xxx.c ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f;
val 738 dev/ic/ar5xxx.c ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f;
val 739 dev/ic/ar5xxx.c ee->ee_ant_control[mode][i] = (val << 2) & 0x3f;
val 741 dev/ic/ar5xxx.c AR5K_EEPROM_READ(o++, val);
val 742 dev/ic/ar5xxx.c ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3;
val 743 dev/ic/ar5xxx.c ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f;
val 744 dev/ic/ar5xxx.c ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f;
val 745 dev/ic/ar5xxx.c ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
val 747 dev/ic/ar5xxx.c AR5K_EEPROM_READ(o++, val);
val 748 dev/ic/ar5xxx.c ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
val 749 dev/ic/ar5xxx.c ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
val 750 dev/ic/ar5xxx.c ee->ee_ant_control[mode][i++] = val & 0x3f;
val 779 dev/ic/ar5xxx.c u_int16_t val;
val 782 dev/ic/ar5xxx.c AR5K_EEPROM_READ(o++, val);
val 783 dev/ic/ar5xxx.c ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff;
val 784 dev/ic/ar5xxx.c ee->ee_thr_62[mode] = val & 0xff;
val 790 dev/ic/ar5xxx.c AR5K_EEPROM_READ(o++, val);
val 791 dev/ic/ar5xxx.c ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff;
val 792 dev/ic/ar5xxx.c ee->ee_tx_frm2xpa_enable[mode] = val & 0xff;
val 794 dev/ic/ar5xxx.c AR5K_EEPROM_READ(o++, val);
val 795 dev/ic/ar5xxx.c ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff;
val 797 dev/ic/ar5xxx.c if ((val & 0xff) & 0x80)
val 798 dev/ic/ar5xxx.c ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1);
val 800 dev/ic/ar5xxx.c ee->ee_noise_floor_thr[mode] = val & 0xff;
val 806 dev/ic/ar5xxx.c AR5K_EEPROM_READ(o++, val);
val 807 dev/ic/ar5xxx.c ee->ee_xlna_gain[mode] = (val >> 5) & 0xff;
val 808 dev/ic/ar5xxx.c ee->ee_x_gain[mode] = (val >> 1) & 0xf;
val 809 dev/ic/ar5xxx.c ee->ee_xpd[mode] = val & 0x1;
val 812 dev/ic/ar5xxx.c ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
val 815 dev/ic/ar5xxx.c AR5K_EEPROM_READ(o++, val);
val 816 dev/ic/ar5xxx.c ee->ee_false_detect[mode] = (val >> 6) & 0x7f;
val 819 dev/ic/ar5xxx.c ee->ee_xr_power[mode] = val & 0x3f;
val 821 dev/ic/ar5xxx.c ee->ee_ob[mode][0] = val & 0x7;
val 822 dev/ic/ar5xxx.c ee->ee_db[mode][0] = (val >> 3) & 0x7;
val 830 dev/ic/ar5xxx.c ee->ee_i_gain[mode] = (val >> 13) & 0x7;
val 832 dev/ic/ar5xxx.c AR5K_EEPROM_READ(o++, val);
val 833 dev/ic/ar5xxx.c ee->ee_i_gain[mode] |= (val << 3) & 0x38;
val 836 dev/ic/ar5xxx.c ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff;
val 841 dev/ic/ar5xxx.c ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
val 842 dev/ic/ar5xxx.c ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
val 847 dev/ic/ar5xxx.c ee->ee_scaled_cck_delta = (val >> 11) & 0x1f;
val 860 dev/ic/ar5xxx.c u_int16_t val;
val 888 dev/ic/ar5xxx.c AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val);
val 889 dev/ic/ar5xxx.c cksum ^= val;
val 906 dev/ic/ar5xxx.c AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val);
val 907 dev/ic/ar5xxx.c ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7;
val 908 dev/ic/ar5xxx.c ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7;
val 910 dev/ic/ar5xxx.c AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val);
val 911 dev/ic/ar5xxx.c ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7;
val 912 dev/ic/ar5xxx.c ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
val 922 dev/ic/ar5xxx.c AR5K_EEPROM_READ(offset++, val);
val 923 dev/ic/ar5xxx.c ee->ee_ctl[i] = (val >> 8) & 0xff;
val 924 dev/ic/ar5xxx.c ee->ee_ctl[i + 1] = val & 0xff;
val 940 dev/ic/ar5xxx.c AR5K_EEPROM_READ(offset++, val);
val 941 dev/ic/ar5xxx.c ee->ee_adc_desired_size[mode] = (int8_t)((val >> 8) & 0xff);
val 942 dev/ic/ar5xxx.c ee->ee_ob[mode][3] = (val >> 5) & 0x7;
val 943 dev/ic/ar5xxx.c ee->ee_db[mode][3] = (val >> 2) & 0x7;
val 944 dev/ic/ar5xxx.c ee->ee_ob[mode][2] = (val << 1) & 0x7;
val 946 dev/ic/ar5xxx.c AR5K_EEPROM_READ(offset++, val);
val 947 dev/ic/ar5xxx.c ee->ee_ob[mode][2] |= (val >> 15) & 0x1;
val 948 dev/ic/ar5xxx.c ee->ee_db[mode][2] = (val >> 12) & 0x7;
val 949 dev/ic/ar5xxx.c ee->ee_ob[mode][1] = (val >> 9) & 0x7;
val 950 dev/ic/ar5xxx.c ee->ee_db[mode][1] = (val >> 6) & 0x7;
val 951 dev/ic/ar5xxx.c ee->ee_ob[mode][0] = (val >> 3) & 0x7;
val 952 dev/ic/ar5xxx.c ee->ee_db[mode][0] = val & 0x7;
val 958 dev/ic/ar5xxx.c AR5K_EEPROM_READ(offset++, val);
val 959 dev/ic/ar5xxx.c ee->ee_margin_tx_rx[mode] = val & 0x3f;
val 971 dev/ic/ar5xxx.c AR5K_EEPROM_READ(offset++, val);
val 972 dev/ic/ar5xxx.c ee->ee_adc_desired_size[mode] = (int8_t)((val >> 8) & 0xff);
val 973 dev/ic/ar5xxx.c ee->ee_ob[mode][1] = (val >> 4) & 0x7;
val 974 dev/ic/ar5xxx.c ee->ee_db[mode][1] = val & 0x7;
val 980 dev/ic/ar5xxx.c AR5K_EEPROM_READ(offset++, val);
val 982 dev/ic/ar5xxx.c ar5k_eeprom_bin2freq(hal, val & 0xff, mode);
val 984 dev/ic/ar5xxx.c ar5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode);
val 986 dev/ic/ar5xxx.c AR5K_EEPROM_READ(offset++, val);
val 988 dev/ic/ar5xxx.c ar5k_eeprom_bin2freq(hal, val & 0xff, mode);
val 992 dev/ic/ar5xxx.c ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
val 1004 dev/ic/ar5xxx.c AR5K_EEPROM_READ(offset++, val);
val 1005 dev/ic/ar5xxx.c ee->ee_adc_desired_size[mode] = (int8_t)((val >> 8) & 0xff);
val 1006 dev/ic/ar5xxx.c ee->ee_ob[mode][1] = (val >> 4) & 0x7;
val 1007 dev/ic/ar5xxx.c ee->ee_db[mode][1] = val & 0x7;
val 1013 dev/ic/ar5xxx.c AR5K_EEPROM_READ(offset++, val);
val 1015 dev/ic/ar5xxx.c ar5k_eeprom_bin2freq(hal, val & 0xff, mode);
val 1017 dev/ic/ar5xxx.c ar5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode);
val 1019 dev/ic/ar5xxx.c AR5K_EEPROM_READ(offset++, val);
val 1020 dev/ic/ar5xxx.c ee->ee_turbo_max_power[mode] = val & 0x7f;
val 1021 dev/ic/ar5xxx.c ee->ee_xr_power[mode] = (val >> 7) & 0x3f;
val 1023 dev/ic/ar5xxx.c AR5K_EEPROM_READ(offset++, val);
val 1025 dev/ic/ar5xxx.c ar5k_eeprom_bin2freq(hal, val & 0xff, mode);
val 1028 dev/ic/ar5xxx.c ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
val 1031 dev/ic/ar5xxx.c AR5K_EEPROM_READ(offset++, val);
val 1032 dev/ic/ar5xxx.c ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
val 1033 dev/ic/ar5xxx.c ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
val 1036 dev/ic/ar5xxx.c AR5K_EEPROM_READ(offset++, val);
val 1037 dev/ic/ar5xxx.c ee->ee_cck_ofdm_gain_delta = val & 0xff;
val 1017 dev/ic/ar5xxx.h u_int32_t val); \
val 1182 dev/ic/ath.c u_int32_t val;
val 1185 dev/ic/ath.c val = LE_READ_4(dl + 0);
val 1186 dev/ic/ath.c pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
val 1187 dev/ic/ath.c val = LE_READ_4(dl + 3);
val 1188 dev/ic/ath.c pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
val 1560 dev/ic/atw.c u_int addr, val;
val 1567 dev/ic/atw.c if (atw_si4126_read(sc, addr, &val) == 0) {
val 1571 dev/ic/atw.c printf("%05x\n", val);
val 1787 dev/ic/atw.c u_int addr, val;
val 1794 dev/ic/atw.c if (atw_rf3000_read(sc, addr, &val) != 0) {
val 1798 dev/ic/atw.c printf("%08x\n", val);
val 1877 dev/ic/atw.c atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val)
val 1883 dev/ic/atw.c LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) |
val 1915 dev/ic/atw.c atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val)
val 1949 dev/ic/atw.c if (val != NULL)
val 1950 dev/ic/atw.c *val = MASK_AND_RSHIFT(reg, ATW_BBPCTL_DATA_MASK);
val 1963 dev/ic/atw.c atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val)
val 1971 dev/ic/atw.c val &= 0x3ffff;
val 1973 dev/ic/atw.c bits = val | (addr << 18);
val 1978 dev/ic/atw.c KASSERT((val & ~PRESHIFT(SI4126_TWI_DATA_MASK)) == 0);
val 1980 dev/ic/atw.c bits = LSHIFT(val, SI4126_TWI_DATA_MASK) |
val 2012 dev/ic/atw.c atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val)
val 2048 dev/ic/atw.c if (val != NULL)
val 2049 dev/ic/atw.c *val = MASK_AND_RSHIFT(ATW_READ(sc, ATW_SYNCTL),
val 91 dev/ic/atwreg.h #define MASK_AND_REPLACE(reg, val, mask) ((reg & ~mask) | LSHIFT(val, mask))
val 447 dev/ic/atwvar.h #define ATW_WRITE(sc, reg, val) \
val 448 dev/ic/atwvar.h bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
val 176 dev/ic/awivar.h #define awi_write_1(sc, off, val) \
val 177 dev/ic/awivar.h ((sc)->sc_chip.sc_ops->write_1)(&sc->sc_chip, off, val)
val 178 dev/ic/awivar.h #define awi_write_2(sc, off, val) \
val 179 dev/ic/awivar.h ((sc)->sc_chip.sc_ops->write_2)(&sc->sc_chip, off, val)
val 180 dev/ic/awivar.h #define awi_write_4(sc, off, val) \
val 181 dev/ic/awivar.h ((sc)->sc_chip.sc_ops->write_4)(&sc->sc_chip, off, val)
val 161 dev/ic/ax88190.c ax88190_mii_bitbang_write(self, val)
val 163 dev/ic/ax88190.c u_int32_t val;
val 167 dev/ic/ax88190.c bus_space_write_1(sc->sc_asict, sc->sc_asich, AX88190_MEMR, val);
val 179 dev/ic/ax88190.c ax88190_mii_writereg(self, phy, reg, val)
val 181 dev/ic/ax88190.c int phy, reg, val;
val 183 dev/ic/ax88190.c mii_bitbang_writereg(self, &ax88190_mii_bitbang_ops, phy, reg, val);
val 169 dev/ic/bt463.c #define BTWREG(data, addr, val) do { bt463_wraddr((data), (addr)); \
val 170 dev/ic/bt463.c (data)->ramdac_wr((data)->cookie, BT463_REG_IREG_DATA, (val)); } while (0)
val 171 dev/ic/bt463.c #define BTWNREG(data, val) (data)->ramdac_wr((data)->cookie, \
val 172 dev/ic/bt463.c BT463_REG_IREG_DATA, (val))
val 531 dev/ic/bt463.c u_int8_t val;
val 535 dev/ic/bt463.c val = BTRREG(data, i);
val 536 dev/ic/bt463.c printf(" $%04x %02x\n", i, val);
val 540 dev/ic/bt463.c val = BTRREG(data, 0x220);
val 541 dev/ic/bt463.c printf(" $%04x %02x\n", 0x220, val);
val 511 dev/ic/bt485.c bt485_wr_i(data, ireg, val)
val 514 dev/ic/bt485.c u_int8_t val;
val 517 dev/ic/bt485.c data->ramdac_wr(data->cookie, BT485_REG_EXTENDED, val);
val 54 dev/ic/cacvar.h #define cac_outb(sc, port, val) \
val 55 dev/ic/cacvar.h bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, port, val)
val 56 dev/ic/cacvar.h #define cac_outw(sc, port, val) \
val 57 dev/ic/cacvar.h bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, port, val)
val 58 dev/ic/cacvar.h #define cac_outl(sc, port, val) \
val 59 dev/ic/cacvar.h bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, port, val)
val 108 dev/ic/cyreg.h #define cd_write_reg(cy,reg,val) bus_space_write_1(cy->cy_memt, cy->cy_memh, \
val 110 dev/ic/cyreg.h (val))
val 120 dev/ic/cyreg.h #define cd_write_reg_sc(sc,chip,reg,val) bus_space_write_1(sc->sc_memt, \
val 124 dev/ic/cyreg.h (val))
val 779 dev/ic/dcreg.h #define CSR_WRITE_4(sc, reg, val) \
val 780 dev/ic/dcreg.h bus_space_write_4(sc->dc_btag, sc->dc_bhandle, reg, val)
val 200 dev/ic/dl10019.c dl10019_mii_bitbang_write(struct device *self, u_int32_t val)
val 208 dev/ic/dl10019.c (val & ~DL0_GPIO_PRESERVE) | (gpio & DL0_GPIO_PRESERVE));
val 224 dev/ic/dl10019.c dl10019_mii_writereg(struct device *self, int phy, int reg, int val)
val 232 dev/ic/dl10019.c mii_bitbang_writereg(self, ops, phy, reg, val);
val 149 dev/ic/dp8390var.h #define NIC_PUT(t, h, reg, val) bus_space_write_1(t, h, \
val 150 dev/ic/dp8390var.h ((sc)->sc_reg_map[reg]), (val))
val 1765 dev/ic/elink3.c u_int16_t val;
val 1768 dev/ic/elink3.c val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT);
val 1770 dev/ic/elink3.c val | bit);
val 1778 dev/ic/elink3.c u_int16_t val;
val 1781 dev/ic/elink3.c val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT);
val 1783 dev/ic/elink3.c val & ~bit);
val 1839 dev/ic/elink3.c int val = 0, i, err;
val 1865 dev/ic/elink3.c val <<= 1;
val 1868 dev/ic/elink3.c val |= 1;
val 1876 dev/ic/elink3.c return (err ? 0 : val);
val 1880 dev/ic/elink3.c ep_mii_writereg(self, phy, reg, val)
val 1882 dev/ic/elink3.c int phy, reg, val;
val 1898 dev/ic/elink3.c ep_mii_sendbits(sc, val, 16);
val 155 dev/ic/fxpvar.h #define CSR_WRITE_1(sc, reg, val) \
val 156 dev/ic/fxpvar.h bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
val 157 dev/ic/fxpvar.h #define CSR_WRITE_2(sc, reg, val) \
val 158 dev/ic/fxpvar.h bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
val 159 dev/ic/fxpvar.h #define CSR_WRITE_4(sc, reg, val) \
val 160 dev/ic/fxpvar.h bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
val 1222 dev/ic/gem.c gem_mii_writereg(struct device *self, int phy, int reg, int val)
val 1233 dev/ic/gem.c phy, reg, val);
val 1240 dev/ic/gem.c (val & GEM_MIF_FRAME_DATA);
val 1347 dev/ic/gem.c gem_pcs_writereg(struct device *self, int phy, int reg, int val)
val 1356 dev/ic/gem.c phy, reg, val);
val 1379 dev/ic/gem.c bus_space_write_4(t, pcs, reg, val);
val 1072 dev/ic/hme.c hme_mii_writereg(self, phy, reg, val)
val 1074 dev/ic/hme.c int phy, reg, val;
val 1108 dev/ic/hme.c (val & HME_MIF_FO_DATA);
val 937 dev/ic/i82596.c int n, off, val;
val 941 dev/ic/i82596.c val = sc->ie_bus_read16(sc, off);
val 942 dev/ic/i82596.c if ((n == sc->rbtail) ^ ((val & IE_RBD_EOL) != 0)) {
val 955 dev/ic/i82596.c val = sc->ie_bus_read16(sc, off);
val 956 dev/ic/i82596.c if ((n == sc->rftail) ^ ((val & (IE_FD_EOL|IE_FD_SUSP)) != 0)) {
val 506 dev/ic/ibm561.c ibm561_regcont10bit(struct ibm561data *data, u_int16_t reg, u_int16_t val)
val 508 dev/ic/ibm561.c data->ramdac_wr(data->cookie, IBM561_CMD_GAMMA, (val >> 2) & 0xff);
val 509 dev/ic/ibm561.c data->ramdac_wr(data->cookie, IBM561_CMD_GAMMA, (val & 0x3) << 6);
val 520 dev/ic/ibm561.c ibm561_regcont(struct ibm561data *data, u_int16_t reg, u_int8_t val)
val 522 dev/ic/ibm561.c data->ramdac_wr(data->cookie, reg, val);
val 526 dev/ic/ibm561.c ibm561_regwr(struct ibm561data *data, u_int16_t reg, u_int8_t val)
val 529 dev/ic/ibm561.c ibm561_regcont(data, IBM561_CMD, val);
val 1158 dev/ic/if_wi.c u_int16_t val = 0;
val 1193 dev/ic/if_wi.c val = PRIVACY_INVOKED;
val 1204 dev/ic/if_wi.c val |= EXCLUDE_UNENCRYPTED;
val 1213 dev/ic/if_wi.c val |= HOST_ENCRYPT;
val 1216 dev/ic/if_wi.c val |= HOST_ENCRYPT|HOST_DECRYPT;
val 1219 dev/ic/if_wi.c p2ltv.wi_val = htole16(val);
val 90 dev/ic/if_wireg.h #define CSR_WRITE_4(sc, reg, val) \
val 93 dev/ic/if_wireg.h WI_BIG_ENDIAN_POSSIBLE ? htole32(val) : (val))
val 94 dev/ic/if_wireg.h #define CSR_WRITE_2(sc, reg, val) \
val 97 dev/ic/if_wireg.h WI_BIG_ENDIAN_POSSIBLE ? htole16(val) : (val))
val 98 dev/ic/if_wireg.h #define CSR_WRITE_1(sc, reg, val) \
val 100 dev/ic/if_wireg.h (sc->sc_pci ? reg * 2: reg), val)
val 357 dev/ic/if_wireg.h #define WI_SETVAL(recno, val) \
val 363 dev/ic/if_wireg.h g.wi_val = htole16(val); \
val 262 dev/ic/isp_target.h #define AT_HAS_TAG(val) ((val) & 0xffff)
val 263 dev/ic/isp_target.h #define AT_GET_TAG(val) AT_HAS_TAG(val) - 1
val 264 dev/ic/isp_target.h #define AT_GET_HANDLE(val) ((val) >> 16)
val 108 dev/ic/ispvar.h #define ISP_WRITE(isp, reg, val) \
val 109 dev/ic/ispvar.h (*(isp)->isp_mdvec->dv_wr_reg)((isp), (reg), (val))
val 128 dev/ic/ispvar.h #define ISP_SETBITS(isp, reg, val) \
val 129 dev/ic/ispvar.h (*(isp)->isp_mdvec->dv_wr_reg)((isp), (reg), ISP_READ((isp), (reg)) | (val))
val 131 dev/ic/ispvar.h #define ISP_CLRBITS(isp, reg, val) \
val 132 dev/ic/ispvar.h (*(isp)->isp_mdvec->dv_wr_reg)((isp), (reg), ISP_READ((isp), (reg)) & ~(val))
val 2345 dev/ic/midway.c u_int32_t reg, kick, val, mask, chip, vci, slot, dtq, drq;
val 2391 dev/ic/midway.c val = EN_READ(sc, MIDX_READPTR(lcv)); /* current read pointer */
val 2392 dev/ic/midway.c val = (val * sizeof(u_int32_t)) + sc->txslot[lcv].start;
val 2394 dev/ic/midway.c if (val > sc->txslot[lcv].cur)
val 2395 dev/ic/midway.c sc->txslot[lcv].bfree = val - sc->txslot[lcv].cur;
val 2397 dev/ic/midway.c sc->txslot[lcv].bfree = (val + (EN_TXSZ*1024)) - sc->txslot[lcv].cur;
val 2413 dev/ic/midway.c val = EN_READ(sc, MID_DMA_RDTX); /* chip's current location */
val 2422 dev/ic/midway.c while (idx != val) {
val 2439 dev/ic/midway.c sc->dtq_chip = MID_DTQ_REG2A(val); /* sync softc */
val 2468 dev/ic/midway.c val = EN_READ(sc, MID_DMA_RDRX); /* chip's current location */
val 2470 dev/ic/midway.c while (idx != val) {
val 2523 dev/ic/midway.c sc->drq_chip = MID_DRQ_REG2A(val); /* sync softc */
val 284 dev/ic/mtd8xx.c mtd_miibus_writereg(struct device *self, int phy, int reg, int val)
val 290 dev/ic/mtd8xx.c CSR_WRITE_2(MTD_PHYCSR + (reg << 1), val);
val 297 dev/ic/mtd8xx.c if (mask & (u_int32_t)val)
val 201 dev/ic/mtd8xxreg.h #define CSR_WRITE_1(reg, val) \
val 202 dev/ic/mtd8xxreg.h bus_space_write_1(sc->sc_bust, sc->sc_bush, reg, val)
val 206 dev/ic/mtd8xxreg.h bus_space_write_2(sc->sc_bust, sc->sc_bush, reg, val)
val 209 dev/ic/mtd8xxreg.h #define CSR_WRITE_4(reg, val) \
val 210 dev/ic/mtd8xxreg.h bus_space_write_4(sc->sc_bust, sc->sc_bush, reg, val)
val 212 dev/ic/mtd8xxreg.h #define CSR_SETBIT(reg, val) CSR_WRITE_4(reg, CSR_READ_4(reg) | (val))
val 213 dev/ic/mtd8xxreg.h #define CSR_CLRBIT(reg, val) CSR_WRITE_4(reg, CSR_READ_4(reg) & ~(val))
val 2480 dev/ic/ncr5380sbc.c long val;
val 2484 dev/ic/ncr5380sbc.c ncr5380_trace(msg, val)
val 2486 dev/ic/ncr5380sbc.c long val;
val 2500 dev/ic/ncr5380sbc.c tr->val = val;
val 2526 dev/ic/ncr5380sbc.c db_printf(tr->msg, tr->val);
val 181 dev/ic/ncr5380var.h void ncr5380_trace(char *msg, long val);
val 182 dev/ic/ncr5380var.h #define NCR_TRACE(msg, val) ncr5380_trace(msg, val)
val 184 dev/ic/ncr5380var.h #define NCR_TRACE(msg, val) /* nada */
val 402 dev/ic/ncr53c9xvar.h #define NCR_WRITE_REG(sc, reg, val) \
val 403 dev/ic/ncr53c9xvar.h (*(sc)->sc_glue->gl_write_reg)((sc), (reg), (val))
val 66 dev/ic/osiopvar.h #define osiop_write_1(sc, reg, val) \
val 67 dev/ic/osiopvar.h bus_space_write_1((sc)->sc_bst, (sc)->sc_reg, reg, val)
val 71 dev/ic/osiopvar.h #define osiop_write_4(sc, reg, val) \
val 72 dev/ic/osiopvar.h bus_space_write_4((sc)->sc_bst, (sc)->sc_reg, reg, val)
val 237 dev/ic/pcdisplay_subr.c u_int16_t val;
val 242 dev/ic/pcdisplay_subr.c val = (fillattr << 8) | ' ';
val 246 dev/ic/pcdisplay_subr.c val, ncols);
val 249 dev/ic/pcdisplay_subr.c scr->mem[off + i] = val;
val 286 dev/ic/pcdisplay_subr.c u_int16_t val;
val 291 dev/ic/pcdisplay_subr.c val = (fillattr << 8) | ' ';
val 295 dev/ic/pcdisplay_subr.c val, count);
val 298 dev/ic/pcdisplay_subr.c scr->mem[off + n] = val;
val 66 dev/ic/pcdisplayvar.h static inline void _pcdisplay_6845_write(ph, reg, val)
val 69 dev/ic/pcdisplayvar.h u_int8_t val;
val 72 dev/ic/pcdisplayvar.h bus_space_write_1(ph->ph_iot, ph->ph_ioh_6845, MC6845_DATA, val);
val 77 dev/ic/pcdisplayvar.h #define pcdisplay_6845_write(ph, reg, val) \
val 78 dev/ic/pcdisplayvar.h _pcdisplay_6845_write(ph, offsetof(struct reg_mc6845, reg), val)
val 124 dev/ic/pckbc.c pckbc_send_cmd(iot, ioh_c, val)
val 127 dev/ic/pckbc.c u_char val;
val 131 dev/ic/pckbc.c bus_space_write_1(iot, ioh_c, 0, val);
val 216 dev/ic/pckbc.c pckbc_send_devcmd(t, slot, val)
val 219 dev/ic/pckbc.c u_char val;
val 231 dev/ic/pckbc.c bus_space_write_1(iot, ioh_d, 0, val);
val 152 dev/ic/rt2560.c uint32_t val;
val 159 dev/ic/rt2560.c uint8_t val;
val 826 dev/ic/rt2560.c uint16_t val;
val 858 dev/ic/rt2560.c val = 0;
val 862 dev/ic/rt2560.c val |= ((tmp & RT2560_Q) >> RT2560_SHIFT_Q) << n;
val 873 dev/ic/rt2560.c return val;
val 2083 dev/ic/rt2560.c rt2560_bbp_write(struct rt2560_softc *sc, uint8_t reg, uint8_t val)
val 2098 dev/ic/rt2560.c tmp = RT2560_BBP_WRITE | RT2560_BBP_BUSY | reg << 8 | val;
val 2101 dev/ic/rt2560.c DPRINTFN(15, ("BBP R%u <- 0x%02x\n", reg, val));
val 2107 dev/ic/rt2560.c uint32_t val;
val 2110 dev/ic/rt2560.c val = RT2560_BBP_BUSY | reg << 8;
val 2111 dev/ic/rt2560.c RAL_WRITE(sc, RT2560_BBPCSR, val);
val 2114 dev/ic/rt2560.c val = RAL_READ(sc, RT2560_BBPCSR);
val 2115 dev/ic/rt2560.c if (!(val & RT2560_BBP_BUSY))
val 2116 dev/ic/rt2560.c return val & 0xff;
val 2125 dev/ic/rt2560.c rt2560_rf_write(struct rt2560_softc *sc, uint8_t reg, uint32_t val)
val 2140 dev/ic/rt2560.c tmp = RT2560_RF_BUSY | RT2560_RF_20BIT | (val & 0xfffff) << 2 |
val 2145 dev/ic/rt2560.c sc->rf_regs[reg] = val;
val 2147 dev/ic/rt2560.c DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff));
val 2522 dev/ic/rt2560.c uint16_t val;
val 2525 dev/ic/rt2560.c val = rt2560_eeprom_read(sc, RT2560_EEPROM_CONFIG0);
val 2526 dev/ic/rt2560.c sc->rf_rev = (val >> 11) & 0x1f;
val 2527 dev/ic/rt2560.c sc->hw_radio = (val >> 10) & 0x1;
val 2528 dev/ic/rt2560.c sc->led_mode = (val >> 6) & 0x7;
val 2529 dev/ic/rt2560.c sc->rx_ant = (val >> 4) & 0x3;
val 2530 dev/ic/rt2560.c sc->tx_ant = (val >> 2) & 0x3;
val 2531 dev/ic/rt2560.c sc->nb_ant = val & 0x3;
val 2535 dev/ic/rt2560.c val = rt2560_eeprom_read(sc, RT2560_EEPROM_BBP_BASE + i);
val 2536 dev/ic/rt2560.c sc->bbp_prom[i].reg = val >> 8;
val 2537 dev/ic/rt2560.c sc->bbp_prom[i].val = val & 0xff;
val 2542 dev/ic/rt2560.c val = rt2560_eeprom_read(sc, RT2560_EEPROM_TXPOWER + i);
val 2543 dev/ic/rt2560.c sc->txpow[i * 2] = val >> 8;
val 2544 dev/ic/rt2560.c sc->txpow[i * 2 + 1] = val & 0xff;
val 2568 dev/ic/rt2560.c rt2560_def_bbp[i].val);
val 2575 dev/ic/rt2560.c rt2560_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);
val 2625 dev/ic/rt2560.c RAL_WRITE(sc, rt2560_def_mac[i].reg, rt2560_def_mac[i].val);
val 306 dev/ic/rt2560reg.h #define RAL_WRITE(sc, reg, val) \
val 307 dev/ic/rt2560reg.h bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
val 312 dev/ic/rt2560reg.h #define RT2560_EEPROM_CTL(sc, val) do { \
val 313 dev/ic/rt2560reg.h RAL_WRITE((sc), RT2560_CSR21, (val)); \
val 137 dev/ic/rt2560var.h uint8_t val;
val 161 dev/ic/rt2661.c uint32_t val;
val 168 dev/ic/rt2661.c uint8_t val;
val 188 dev/ic/rt2661.c uint32_t val;
val 200 dev/ic/rt2661.c if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0)
val 214 dev/ic/rt2661.c printf("%s: MAC/BBP RT%X, RF %s\n", sc->sc_dev.dv_xname, val,
val 842 dev/ic/rt2661.c uint16_t val;
val 874 dev/ic/rt2661.c val = 0;
val 878 dev/ic/rt2661.c val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n;
val 889 dev/ic/rt2661.c return val;
val 903 dev/ic/rt2661.c const uint32_t val = RAL_READ(sc, RT2661_STA_CSR4);
val 904 dev/ic/rt2661.c if (!(val & RT2661_TX_STAT_VALID))
val 908 dev/ic/rt2661.c qid = RT2661_TX_QID(val);
val 919 dev/ic/rt2661.c switch (RT2661_TX_RESULT(val)) {
val 921 dev/ic/rt2661.c retrycnt = RT2661_TX_RETRYCNT(val);
val 942 dev/ic/rt2661.c sc->sc_dev.dv_xname, val);
val 1927 dev/ic/rt2661.c rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val)
val 1942 dev/ic/rt2661.c tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val;
val 1945 dev/ic/rt2661.c DPRINTFN(15, ("BBP R%u <- 0x%02x\n", reg, val));
val 1951 dev/ic/rt2661.c uint32_t val;
val 1964 dev/ic/rt2661.c val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8;
val 1965 dev/ic/rt2661.c RAL_WRITE(sc, RT2661_PHY_CSR3, val);
val 1968 dev/ic/rt2661.c val = RAL_READ(sc, RT2661_PHY_CSR3);
val 1969 dev/ic/rt2661.c if (!(val & RT2661_BBP_BUSY))
val 1970 dev/ic/rt2661.c return val & 0xff;
val 1979 dev/ic/rt2661.c rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val)
val 1994 dev/ic/rt2661.c tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 |
val 1999 dev/ic/rt2661.c sc->rf_regs[reg] = val;
val 2001 dev/ic/rt2661.c DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff));
val 2306 dev/ic/rt2661.c uint16_t val;
val 2310 dev/ic/rt2661.c val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01);
val 2311 dev/ic/rt2661.c ic->ic_myaddr[0] = val & 0xff;
val 2312 dev/ic/rt2661.c ic->ic_myaddr[1] = val >> 8;
val 2314 dev/ic/rt2661.c val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23);
val 2315 dev/ic/rt2661.c ic->ic_myaddr[2] = val & 0xff;
val 2316 dev/ic/rt2661.c ic->ic_myaddr[3] = val >> 8;
val 2318 dev/ic/rt2661.c val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45);
val 2319 dev/ic/rt2661.c ic->ic_myaddr[4] = val & 0xff;
val 2320 dev/ic/rt2661.c ic->ic_myaddr[5] = val >> 8;
val 2322 dev/ic/rt2661.c val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA);
val 2324 dev/ic/rt2661.c sc->rf_rev = (val >> 11) & 0x1f;
val 2325 dev/ic/rt2661.c sc->hw_radio = (val >> 10) & 0x1;
val 2326 dev/ic/rt2661.c sc->rx_ant = (val >> 4) & 0x3;
val 2327 dev/ic/rt2661.c sc->tx_ant = (val >> 2) & 0x3;
val 2328 dev/ic/rt2661.c sc->nb_ant = val & 0x3;
val 2332 dev/ic/rt2661.c val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2);
val 2333 dev/ic/rt2661.c sc->ext_5ghz_lna = (val >> 6) & 0x1;
val 2334 dev/ic/rt2661.c sc->ext_2ghz_lna = (val >> 4) & 0x1;
val 2339 dev/ic/rt2661.c val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET);
val 2340 dev/ic/rt2661.c if ((val & 0xff) != 0xff)
val 2341 dev/ic/rt2661.c sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */
val 2343 dev/ic/rt2661.c val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET);
val 2344 dev/ic/rt2661.c if ((val & 0xff) != 0xff)
val 2345 dev/ic/rt2661.c sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */
val 2356 dev/ic/rt2661.c val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET);
val 2357 dev/ic/rt2661.c if ((val >> 8) != 0xff)
val 2358 dev/ic/rt2661.c sc->rfprog = (val >> 8) & 0x3;
val 2359 dev/ic/rt2661.c if ((val & 0xff) != 0xff)
val 2360 dev/ic/rt2661.c sc->rffreq = val & 0xff;
val 2366 dev/ic/rt2661.c val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i);
val 2367 dev/ic/rt2661.c sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */
val 2370 dev/ic/rt2661.c sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */
val 2377 dev/ic/rt2661.c val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i);
val 2378 dev/ic/rt2661.c if (val == 0 || val == 0xffff)
val 2380 dev/ic/rt2661.c sc->bbp_prom[i].reg = val >> 8;
val 2381 dev/ic/rt2661.c sc->bbp_prom[i].val = val & 0xff;
val 2383 dev/ic/rt2661.c sc->bbp_prom[i].val));
val 2395 dev/ic/rt2661.c const uint8_t val = rt2661_bbp_read(sc, 0);
val 2396 dev/ic/rt2661.c if (val != 0 && val != 0xff)
val 2408 dev/ic/rt2661.c rt2661_def_bbp[i].val);
val 2415 dev/ic/rt2661.c rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);
val 2519 dev/ic/rt2661.c RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val);
val 324 dev/ic/rt2661reg.h #define RAL_WRITE(sc, reg, val) \
val 325 dev/ic/rt2661reg.h bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
val 327 dev/ic/rt2661reg.h #define RAL_WRITE_1(sc, reg, val) \
val 328 dev/ic/rt2661reg.h bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
val 341 dev/ic/rt2661reg.h #define RT2661_EEPROM_CTL(sc, val) do { \
val 342 dev/ic/rt2661reg.h RAL_WRITE((sc), RT2661_E2PROM_CSR, (val)); \
val 134 dev/ic/rt2661var.h uint8_t val;
val 1419 dev/ic/rtl81x9.c rl_miibus_writereg(self, phy, reg, val)
val 1421 dev/ic/rtl81x9.c int phy, reg, val;
val 1451 dev/ic/rtl81x9.c CSR_WRITE_2(sc, rl8139_reg, val);
val 1458 dev/ic/rtl81x9.c frame.mii_data = val;
val 772 dev/ic/rtl81x9reg.h #define CSR_WRITE_RAW_4(sc, csr, val) \
val 773 dev/ic/rtl81x9reg.h bus_space_write_raw_region_4(sc->rl_btag, sc->rl_bhandle, csr, val, 4)
val 774 dev/ic/rtl81x9reg.h #define CSR_WRITE_4(sc, csr, val) \
val 775 dev/ic/rtl81x9reg.h bus_space_write_4(sc->rl_btag, sc->rl_bhandle, csr, val)
val 776 dev/ic/rtl81x9reg.h #define CSR_WRITE_2(sc, csr, val) \
val 777 dev/ic/rtl81x9reg.h bus_space_write_2(sc->rl_btag, sc->rl_bhandle, csr, val)
val 778 dev/ic/rtl81x9reg.h #define CSR_WRITE_1(sc, csr, val) \
val 779 dev/ic/rtl81x9reg.h bus_space_write_1(sc->rl_btag, sc->rl_bhandle, csr, val)
val 788 dev/ic/rtl81x9reg.h #define CSR_SETBIT_1(sc, offset, val) \
val 789 dev/ic/rtl81x9reg.h CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))
val 791 dev/ic/rtl81x9reg.h #define CSR_CLRBIT_1(sc, offset, val) \
val 792 dev/ic/rtl81x9reg.h CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))
val 794 dev/ic/rtl81x9reg.h #define CSR_SETBIT_2(sc, offset, val) \
val 795 dev/ic/rtl81x9reg.h CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))
val 797 dev/ic/rtl81x9reg.h #define CSR_CLRBIT_2(sc, offset, val) \
val 798 dev/ic/rtl81x9reg.h CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))
val 800 dev/ic/rtl81x9reg.h #define CSR_SETBIT_4(sc, offset, val) \
val 801 dev/ic/rtl81x9reg.h CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val))
val 803 dev/ic/rtl81x9reg.h #define CSR_CLRBIT_4(sc, offset, val) \
val 804 dev/ic/rtl81x9reg.h CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val))
val 2559 dev/ic/rtw.c u_int8_t mask, newval, val;
val 2591 dev/ic/rtw.c val = RTW_READ8(regs, ofs);
val 2593 dev/ic/rtw.c ("%s: read % from reg[%#02]\n", __func__, val,
val 2595 dev/ic/rtw.c val &= ~mask;
val 2596 dev/ic/rtw.c val |= newval;
val 2597 dev/ic/rtw.c RTW_WRITE8(regs, ofs, val);
val 2599 dev/ic/rtw.c ("%s: wrote % to reg[%#02]\n", __func__, val,
val 4238 dev/ic/rtw.c #define RTW_BBP_WRITE_OR_RETURN(reg, val) \
val 4239 dev/ic/rtw.c if ((rc = rtw_bbp_write(regs, reg, val)) != 0) \
val 4268 dev/ic/rtw.c rtw_verify_syna(u_int freq, u_int32_t val)
val 4270 dev/ic/rtw.c u_int32_t expected_val = ~val;
val 4316 dev/ic/rtw.c KASSERT(val == expected_val);
val 4787 dev/ic/rtw.c rtw_bbp_write(struct rtw_regs *regs, u_int addr, u_int val)
val 4795 dev/ic/rtw.c ("%s: bbp[%u] <- %u\n", __func__, addr, val));
val 4798 dev/ic/rtw.c KASSERT((val & ~PRESHIFT(RTW_BB_WR_MASK)) == 0);
val 4801 dev/ic/rtw.c LSHIFT(val, RTW_BB_WR_MASK) | RTW_BB_RD_MASK,
val 4817 dev/ic/rtw.c RTW_BB_RD_MASK) == val) {
val 4978 dev/ic/rtw.c rtw_grf5101_host_crypt(u_int addr, u_int32_t val)
val 4985 dev/ic/rtw.c rtw_grf5101_mac_crypt(u_int addr, u_int32_t val)
val 4996 dev/ic/rtw.c caesar[EXTRACT_NIBBLE(val, 2)] |
val 4997 dev/ic/rtw.c (caesar[EXTRACT_NIBBLE(val, 1)] << 4) |
val 4998 dev/ic/rtw.c (caesar[EXTRACT_NIBBLE(val, 0)] << 8) |
val 5001 dev/ic/rtw.c (caesar[EXTRACT_NIBBLE(val, 3)] << 24);
val 5009 dev/ic/rtw.c rtw_rf_hostwrite(struct rtw_softc *sc, u_int addr, u_int32_t val)
val 5018 dev/ic/rtw.c addr, val));
val 5024 dev/ic/rtw.c bits = LSHIFT(val, MAX2820_TWI_DATA_MASK) |
val 5029 dev/ic/rtw.c KASSERT((val & ~PRESHIFT(SA2400_TWI_DATA_MASK)) == 0);
val 5030 dev/ic/rtw.c bits = LSHIFT(val, SA2400_TWI_DATA_MASK) |
val 5037 dev/ic/rtw.c KASSERT((val & ~PRESHIFT(SI4126_TWI_DATA_MASK)) == 0);
val 5038 dev/ic/rtw.c bits = rtw_grf5101_host_crypt(addr, val);
val 5044 dev/ic/rtw.c KASSERT((val & ~PRESHIFT(SI4126_TWI_DATA_MASK)) == 0);
val 5045 dev/ic/rtw.c bits = LSHIFT(val, SI4126_TWI_DATA_MASK) |
val 5054 dev/ic/rtw.c bits = LSHIFT(val, RTL8225_TWI_DATA_MASK) |
val 5072 dev/ic/rtw.c rtw_maxim_swizzle(u_int addr, u_int32_t val)
val 5076 dev/ic/rtw.c KASSERT((val & ~(RTW_MAXIM_LODATA_MASK|RTW_MAXIM_HIDATA_MASK)) == 0);
val 5077 dev/ic/rtw.c lodata = MASK_AND_RSHIFT(val, RTW_MAXIM_LODATA_MASK);
val 5078 dev/ic/rtw.c hidata = MASK_AND_RSHIFT(val, RTW_MAXIM_HIDATA_MASK);
val 5086 dev/ic/rtw.c rtw_rf_macwrite(struct rtw_softc *sc, u_int addr, u_int32_t val)
val 5091 dev/ic/rtw.c addr, val));
val 5095 dev/ic/rtw.c reg = rtw_grf5101_mac_crypt(addr, val);
val 5098 dev/ic/rtw.c reg = rtw_maxim_swizzle(addr, val);
val 5104 dev/ic/rtw.c KASSERT((val &
val 5108 dev/ic/rtw.c LSHIFT(val, RTW8180_PHYCFG_MAC_PHILIPS_DATA_MASK);
val 5154 dev/ic/rtw.c rtw_write8(void *arg, u_int32_t off, u_int8_t val)
val 5157 dev/ic/rtw.c bus_space_write_1(regs->r_bt, regs->r_bh, off, val);
val 5161 dev/ic/rtw.c rtw_write16(void *arg, u_int32_t off, u_int16_t val)
val 5164 dev/ic/rtw.c bus_space_write_2(regs->r_bt, regs->r_bh, off, val);
val 5168 dev/ic/rtw.c rtw_write32(void *arg, u_int32_t off, u_int32_t val)
val 5171 dev/ic/rtw.c bus_space_write_4(regs->r_bt, regs->r_bh, off, val);
val 76 dev/ic/rtwreg.h #define MASK_AND_REPLACE(reg, val, mask) ((reg & ~mask) | LSHIFT(val, mask))
val 1131 dev/ic/rtwreg.h #define RTW_WRITE8(regs, ofs, val) \
val 1132 dev/ic/rtwreg.h ((*(regs)->r_write8)(regs, ofs, val))
val 1134 dev/ic/rtwreg.h #define RTW_WRITE16(regs, ofs, val) \
val 1135 dev/ic/rtwreg.h ((*(regs)->r_write16)(regs, ofs, val))
val 1137 dev/ic/rtwreg.h #define RTW_WRITE(regs, ofs, val) \
val 1138 dev/ic/rtwreg.h ((*(regs)->r_write32)(regs, ofs, val))
val 172 dev/ic/siop.c siop_script_write(sc, offset, val)
val 175 dev/ic/siop.c u_int32_t val;
val 179 dev/ic/siop.c offset * 4, val);
val 181 dev/ic/siop.c sc->sc_c.sc_script[offset] = siop_htoc32(&sc->sc_c, val);
val 1421 dev/ic/smc83c170.c epic_mii_write(struct device *self, int phy, int reg, int val)
val 1428 dev/ic/smc83c170.c bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA, val);
val 1290 dev/ic/smc91cxx.c smc91cxx_mii_bitbang_write(self, val)
val 1292 dev/ic/smc91cxx.c u_int32_t val;
val 1297 dev/ic/smc91cxx.c bus_space_write_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W, val);
val 1306 dev/ic/smc91cxx.c int val;
val 1310 dev/ic/smc91cxx.c val = mii_bitbang_readreg(self, &smc91cxx_mii_bitbang_ops, phy, reg);
val 1314 dev/ic/smc91cxx.c return (val);
val 1318 dev/ic/smc91cxx.c smc91cxx_mii_writereg(self, phy, reg, val)
val 1320 dev/ic/smc91cxx.c int phy, reg, val;
val 1326 dev/ic/smc91cxx.c mii_bitbang_writereg(self, &smc91cxx_mii_bitbang_ops, phy, reg, val);
val 114 dev/ic/tcic2.c int val, auxreg;
val 118 dev/ic/tcic2.c val = (bus_space_read_2(iot, ioh, TCIC_R_ADDR2) & TCIC_SS_MASK)
val 120 dev/ic/tcic2.c if (val > 1)
val 125 dev/ic/tcic2.c val = bus_space_read_1(iot, ioh, TCIC_R_SCTRL);
val 126 dev/ic/tcic2.c if (val & TCIC_SCTRL_RSVD)
val 131 dev/ic/tcic2.c val = bus_space_read_1(iot, ioh, TCIC_R_ICSR);
val 132 dev/ic/tcic2.c if (((val >> 1) & 1) != ((val >> 2) & 1))
val 137 dev/ic/tcic2.c val = bus_space_read_1(iot, ioh, TCIC_R_IENA);
val 138 dev/ic/tcic2.c if (val & TCIC_IENA_RSVD)
val 146 dev/ic/tcic2.c val = bus_space_read_2(iot, ioh, TCIC_R_AUX);
val 147 dev/ic/tcic2.c DPRINTF(("tcic: auxreg 0x%02x val 0x%04x\n", auxreg, val));
val 150 dev/ic/tcic2.c if (INVALID_AR_SYSCFG(val))
val 154 dev/ic/tcic2.c if (INVALID_AR_ILOCK(val))
val 158 dev/ic/tcic2.c if (INVALID_AR_TEST(val))
val 166 dev/ic/tcic2.c val = bus_space_read_1(iot, ioh, TCIC_R_SCTRL);
val 167 dev/ic/tcic2.c if (val & TCIC_SCTRL_RESET) {
val 170 dev/ic/tcic2.c val = bus_space_read_2(iot, ioh, TCIC_R_ADDR);
val 171 dev/ic/tcic2.c if (val != 0)
val 173 dev/ic/tcic2.c val = bus_space_read_2(iot, ioh, TCIC_R_ADDR2);
val 174 dev/ic/tcic2.c if (val != 0)
val 178 dev/ic/tcic2.c val = bus_space_read_2(iot, ioh, TCIC_R_EDC);
val 179 dev/ic/tcic2.c if (val != 0)
val 189 dev/ic/tcic2.c val = bus_space_read_1(iot, ioh, TCIC_R_SSTAT);
val 190 dev/ic/tcic2.c if ((val & (TCIC_SSTAT_6US|TCIC_SSTAT_10US|TCIC_SSTAT_PROGTIME))
val 758 dev/ic/tcic2.c int val, reg;
val 777 dev/ic/tcic2.c val = tcic_read_ind_2(h, reg);
val 778 dev/ic/tcic2.c tcic_write_ind_2(h, reg, (val & ~TCIC_SCF1_IRQ_MASK)|TCIC_SCF1_IRQOFF);
val 780 dev/ic/tcic2.c val = tcic_read_ind_2(h, reg);
val 782 dev/ic/tcic2.c (val | (TCIC_SCF2_MLBAT1|TCIC_SCF2_MLBAT2|TCIC_SCF2_MRDY
val 1351 dev/ic/tcic2.c int val;
val 1358 dev/ic/tcic2.c val = tcic_read_ind_2(h, TCIC_IR_SCF1_N(h->sock));
val 1359 dev/ic/tcic2.c val &= TCIC_SCF1_IRQ_MASK;
val 1360 dev/ic/tcic2.c tcic_write_ind_2(h, TCIC_IR_SCF1_N(h->sock), val);
val 1364 dev/ic/tcic2.c val = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK);
val 1365 dev/ic/tcic2.c val &= ~TCIC_ILOCK_CRESENA;
val 1366 dev/ic/tcic2.c tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, val);
val 1388 dev/ic/tcic2.c tcic_log2(val)
val 1389 dev/ic/tcic2.c u_int val;
val 1394 dev/ic/tcic2.c while (val) {
val 1395 dev/ic/tcic2.c if (val & 1)
val 1398 dev/ic/tcic2.c val >>= 1;
val 210 dev/ic/tcic2var.h int val;
val 211 dev/ic/tcic2var.h val = bus_space_read_2(h->sc->iot, h->sc->ioh, reg);
val 212 dev/ic/tcic2var.h val |= bus_space_read_2(h->sc->iot, h->sc->ioh, reg+2) << 16;
val 213 dev/ic/tcic2var.h return val;
val 253 dev/ic/tcic2var.h int r_addr, val;
val 256 dev/ic/tcic2var.h val = bus_space_read_2(h->sc->iot, h->sc->ioh, TCIC_R_DATA);
val 258 dev/ic/tcic2var.h return val;
val 312 dev/ic/tcic2var.h int mode, val;
val 315 dev/ic/tcic2var.h val = bus_space_read_1(iot, ioh, reg);
val 316 dev/ic/tcic2var.h return val;
val 326 dev/ic/tcic2var.h int mode, val;
val 329 dev/ic/tcic2var.h val = bus_space_read_2(iot, ioh, TCIC_R_AUX);
val 330 dev/ic/tcic2var.h return val;
val 335 dev/ic/tcic2var.h tcic_write_aux_1(iot, ioh, auxreg, reg, val)
val 338 dev/ic/tcic2var.h int auxreg, reg, val;
val 343 dev/ic/tcic2var.h bus_space_write_1(iot, ioh, reg, val);
val 348 dev/ic/tcic2var.h tcic_write_aux_2(iot, ioh, auxreg, val)
val 351 dev/ic/tcic2var.h int auxreg, val;
val 356 dev/ic/tcic2var.h bus_space_write_2(iot, ioh, TCIC_R_AUX, val);
val 93 dev/ic/vgavar.h static inline void _vga_attr_write(vh, reg, val)
val 96 dev/ic/vgavar.h u_int8_t val;
val 102 dev/ic/vgavar.h bus_space_write_1(vh->vh_iot, vh->vh_ioh_vga, VGA_ATC_DATAW, val);
val 119 dev/ic/vgavar.h static inline void _vga_ts_write(vh, reg, val)
val 122 dev/ic/vgavar.h u_int8_t val;
val 125 dev/ic/vgavar.h bus_space_write_1(vh->vh_iot, vh->vh_ioh_vga, VGA_TS_DATA, val);
val 136 dev/ic/vgavar.h static inline void _vga_gdc_write(vh, reg, val)
val 139 dev/ic/vgavar.h u_int8_t val;
val 142 dev/ic/vgavar.h bus_space_write_1(vh->vh_iot, vh->vh_ioh_vga, VGA_GDC_DATA, val);
val 147 dev/ic/vgavar.h #define vga_attr_write(vh, reg, val) \
val 148 dev/ic/vgavar.h _vga_attr_write(vh, offsetof(struct reg_vgaattr, reg), val)
val 151 dev/ic/vgavar.h #define vga_ts_write(vh, reg, val) \
val 152 dev/ic/vgavar.h _vga_ts_write(vh, offsetof(struct reg_vgats, reg), val)
val 155 dev/ic/vgavar.h #define vga_gdc_write(vh, reg, val) \
val 156 dev/ic/vgavar.h _vga_gdc_write(vh, offsetof(struct reg_vgagdc, reg), val)
val 160 dev/ic/vgavar.h #define vga_6845_write(vh, reg, val) \
val 161 dev/ic/vgavar.h pcdisplay_6845_write(&(vh)->vh_ph, reg, val)
val 157 dev/ic/wdc.c unsigned int size, char val[])
val 216 dev/ic/wdc.c memcpy(ptr, val, size);
val 318 dev/ic/wdc.c wdc_default_write_reg(chp, reg, val)
val 321 dev/ic/wdc.c u_int8_t val;
val 331 dev/ic/wdc.c reg & _WDC_REGMASK, val);
val 334 dev/ic/wdc.c reg & _WDC_REGMASK, val);
val 338 dev/ic/wdc.c wdc_default_lba48_write_reg(chp, reg, val)
val 341 dev/ic/wdc.c u_int16_t val;
val 344 dev/ic/wdc.c CHP_WRITE_REG(chp, reg, val >> 8);
val 345 dev/ic/wdc.c CHP_WRITE_REG(chp, reg, val);
val 48 dev/ic/wdcevent.h unsigned int size, char val[]);
val 101 dev/ic/wdcevent.h enum wdc_regs reg, u_int16_t val) {
val 105 dev/ic/wdcevent.h record[1] = (val >> 8);
val 106 dev/ic/wdcevent.h record[2] = val & 0xff;
val 634 dev/ic/xlreg.h #define CSR_WRITE_4(sc, reg, val) \
val 635 dev/ic/xlreg.h bus_space_write_4(sc->xl_btag, sc->xl_bhandle, reg, val)
val 636 dev/ic/xlreg.h #define CSR_WRITE_2(sc, reg, val) \
val 637 dev/ic/xlreg.h bus_space_write_2(sc->xl_btag, sc->xl_bhandle, reg, val)
val 638 dev/ic/xlreg.h #define CSR_WRITE_1(sc, reg, val) \
val 639 dev/ic/xlreg.h bus_space_write_1(sc->xl_btag, sc->xl_bhandle, reg, val)
val 254 dev/ipmi.c bmc_write(struct ipmi_softc *sc, int offset, u_int8_t val)
val 257 dev/ipmi.c offset * sc->sc_if_iospacing, val);
val 492 dev/ipmi.c smic_wait(struct ipmi_softc *sc, u_int8_t mask, u_int8_t val, const char *lbl)
val 497 dev/ipmi.c v = bmc_io_wait(sc, _SMIC_FLAG_REG, mask, val, "smicwait");
val 1235 dev/ipmi.c ipow(long val, int exp)
val 1238 dev/ipmi.c val *= 10;
val 1243 dev/ipmi.c val /= 10;
val 1247 dev/ipmi.c return (val);
val 1252 dev/ipmi.c signextend(unsigned long val, int bits)
val 1256 dev/ipmi.c return (-(val & ~msk) | val);
val 1265 dev/ipmi.c long val;
val 1278 dev/ipmi.c val = ipow(M * v, K2 + adj) + ipow(B, K1 + K2 + adj);
val 1284 dev/ipmi.c return (val);
val 295 dev/isa/aps.c u_int8_t val)
val 302 dev/isa/aps.c if (cr == val)
val 306 dev/isa/aps.c DPRINTF(("aps: reg 0x%x not val 0x%x!\n", reg, val));
val 935 dev/isa/aria.c aria_putdspmem(iobase, loc, val)
val 938 dev/isa/aria.c register u_short val;
val 941 dev/isa/aria.c outw(iobase + ARIADSP_DMADATA, val);
val 257 dev/isa/ega.c u_int16_t oldval, val;
val 263 dev/isa/ega.c val = bus_space_read_2(memt, memh, 0);
val 266 dev/isa/ega.c if (val != 0xa55a)
val 281 dev/isa/ega.c u_int16_t oldval, val;
val 287 dev/isa/ega.c val = bus_space_read_2(memt, memh, 0);
val 290 dev/isa/ega.c if (val != 0xa55a)
val 2601 dev/isa/ess.c ess_write_x_reg(sc, reg, val)
val 2604 dev/isa/ess.c u_char val;
val 2608 dev/isa/ess.c DPRINTFN(2,("ess_write_x_reg: %02x=%02x\n", reg, val));
val 2610 dev/isa/ess.c error = ess_wdsp(sc, val);
val 2624 dev/isa/ess.c int val;
val 2631 dev/isa/ess.c val = ess_rdsp(sc);
val 2632 dev/isa/ess.c DPRINTFN(2,("ess_read_x_reg: %02x=%02x\n", reg, val));
val 2633 dev/isa/ess.c return val;
val 2663 dev/isa/ess.c ess_write_mix_reg(sc, reg, val)
val 2666 dev/isa/ess.c u_char val;
val 2672 dev/isa/ess.c DPRINTFN(2,("ess_write_mix_reg: %x=%x\n", reg, val));
val 2676 dev/isa/ess.c EWRITE1(iot, ioh, ESS_MIX_REG_DATA, val);
val 2691 dev/isa/ess.c u_char val;
val 2695 dev/isa/ess.c val = EREAD1(iot, ioh, ESS_MIX_REG_DATA);
val 2698 dev/isa/ess.c DPRINTFN(2,("ess_read_mix_reg: %x=%x\n", reg, val));
val 2699 dev/isa/ess.c return val;
val 97 dev/isa/gscsio.c #define ACB_WRITE(reg, val) \
val 98 dev/isa/gscsio.c bus_space_write_1(sc->sc_iot, acb->ioh, (reg), (val))
val 96 dev/isa/i82365_isa.c int val, found;
val 124 dev/isa/i82365_isa.c val = bus_space_read_1(iot, ioh, PCIC_REG_DATA);
val 125 dev/isa/i82365_isa.c if (pcic_ident_ok(val))
val 129 dev/isa/i82365_isa.c val = bus_space_read_1(iot, ioh, PCIC_REG_DATA);
val 130 dev/isa/i82365_isa.c if (pcic_ident_ok(val))
val 134 dev/isa/i82365_isa.c val = bus_space_read_1(iot, ioh, PCIC_REG_DATA);
val 135 dev/isa/i82365_isa.c if (pcic_ident_ok(val))
val 139 dev/isa/i82365_isa.c val = bus_space_read_1(iot, ioh, PCIC_REG_DATA);
val 140 dev/isa/i82365_isa.c if (pcic_ident_ok(val))
val 68 dev/isa/ics2101.c #define cvt_value(val) ((val) >> 1)
val 855 dev/isa/if_ef_isapnp.c int i, ack, s, val = 0;
val 907 dev/isa/if_ef_isapnp.c val |= i;
val 919 dev/isa/if_ef_isapnp.c return (val);
val 923 dev/isa/if_ef_isapnp.c ef_miibus_writereg(dev, phy, reg, val)
val 925 dev/isa/if_ef_isapnp.c int phy, reg, val;
val 955 dev/isa/if_ef_isapnp.c ef_mii_writeb(sc, (val & i) ? 1 : 0);
val 70 dev/isa/if_le.c le_isa_wrcsr(struct am7990_softc *sc, u_int16_t port, u_int16_t val)
val 77 dev/isa/if_le.c bus_space_write_2(iot, ioh, lesc->sc_rdp, val);
val 86 dev/isa/if_le.c u_int16_t val;
val 89 dev/isa/if_le.c val = bus_space_read_2(iot, ioh, lesc->sc_rdp);
val 90 dev/isa/if_le.c return (val);
val 313 dev/isa/if_le_isa.c u_char *mem, val;
val 318 dev/isa/if_le_isa.c val = 0xff;
val 321 dev/isa/if_le_isa.c mem[i] = val;
val 323 dev/isa/if_le_isa.c if (mem[i] != val) {
val 328 dev/isa/if_le_isa.c if (val == 0x00)
val 330 dev/isa/if_le_isa.c val -= 0x55;
val 185 dev/isa/it.c it_writereg(struct it_softc *sc, int reg, int val)
val 188 dev/isa/it.c bus_space_write_1(sc->it_iot, sc->it_ioh, ITC_DATA, val);
val 190 dev/isa/lm78_isa.c lm_isa_writereg(struct lm_softc *lmsc, int reg, int val)
val 195 dev/isa/lm78_isa.c bus_space_write_1(sc->sc_iot, sc->sc_ioh, LMC_DATA, val);
val 186 dev/isa/nsclpcsio_isa.c #define GPIO_WRITE(sc, reg, val) \
val 188 dev/isa/nsclpcsio_isa.c (sc)->sc_ld_ioh[SIO_LDN_GPIO], (reg), (val))
val 189 dev/isa/nsclpcsio_isa.c #define TMS_WRITE(sc, reg, val) \
val 191 dev/isa/nsclpcsio_isa.c (sc)->sc_ld_ioh[SIO_LDN_TMS], (reg), (val))
val 195 dev/isa/nsclpcsio_isa.c #define VLM_WRITE(sc, reg, val) \
val 197 dev/isa/nsclpcsio_isa.c (sc)->sc_ld_ioh[SIO_LDN_VLM], (reg), (val))
val 130 dev/isa/pcdisplay.c u_int16_t oldval, val;
val 136 dev/isa/pcdisplay.c val = bus_space_read_2(memt, memh, 0);
val 139 dev/isa/pcdisplay.c if (val != 0xa55a)
val 154 dev/isa/pcdisplay.c u_int16_t oldval, val;
val 160 dev/isa/pcdisplay.c val = bus_space_read_2(memt, memh, 0);
val 163 dev/isa/pcdisplay.c if (val != 0xa55a)
val 325 dev/isa/pss.c int val;
val 327 dev/isa/pss.c val = inw(configAddr);
val 328 dev/isa/pss.c val &= ADDR_MASK;
val 329 dev/isa/pss.c val |= (addr << 4);
val 330 dev/isa/pss.c outw(configAddr,val);
val 343 dev/isa/pss.c int val;
val 347 dev/isa/pss.c val = inw(configAddress);
val 348 dev/isa/pss.c val &= INT_MASK;
val 349 dev/isa/pss.c val |= INT_3_BITS;
val 352 dev/isa/pss.c val = inw(configAddress);
val 353 dev/isa/pss.c val &= INT_MASK;
val 354 dev/isa/pss.c val |= INT_5_BITS;
val 357 dev/isa/pss.c val = inw(configAddress);
val 358 dev/isa/pss.c val &= INT_MASK;
val 359 dev/isa/pss.c val |= INT_7_BITS;
val 362 dev/isa/pss.c val = inw(configAddress);
val 363 dev/isa/pss.c val &= INT_MASK;
val 364 dev/isa/pss.c val |= INT_9_BITS;
val 367 dev/isa/pss.c val = inw(configAddress);
val 368 dev/isa/pss.c val &= INT_MASK;
val 369 dev/isa/pss.c val |= INT_10_BITS;
val 372 dev/isa/pss.c val = inw(configAddress);
val 373 dev/isa/pss.c val &= INT_MASK;
val 374 dev/isa/pss.c val |= INT_11_BITS;
val 377 dev/isa/pss.c val = inw(configAddress);
val 378 dev/isa/pss.c val &= INT_MASK;
val 379 dev/isa/pss.c val |= INT_12_BITS;
val 385 dev/isa/pss.c outw(configAddress,val);
val 394 dev/isa/pss.c int val;
val 398 dev/isa/pss.c val = inw(configAddress);
val 399 dev/isa/pss.c val &= DMA_MASK;
val 400 dev/isa/pss.c val |= DMA_0_BITS;
val 403 dev/isa/pss.c val = inw(configAddress);
val 404 dev/isa/pss.c val &= DMA_MASK;
val 405 dev/isa/pss.c val |= DMA_1_BITS;
val 408 dev/isa/pss.c val = inw(configAddress);
val 409 dev/isa/pss.c val &= DMA_MASK;
val 410 dev/isa/pss.c val |= DMA_3_BITS;
val 413 dev/isa/pss.c val = inw(configAddress);
val 414 dev/isa/pss.c val &= DMA_MASK;
val 415 dev/isa/pss.c val |= DMA_5_BITS;
val 418 dev/isa/pss.c val = inw(configAddress);
val 419 dev/isa/pss.c val &= DMA_MASK;
val 420 dev/isa/pss.c val |= DMA_6_BITS;
val 423 dev/isa/pss.c val = inw(configAddress);
val 424 dev/isa/pss.c val &= DMA_MASK;
val 425 dev/isa/pss.c val |= DMA_7_BITS;
val 431 dev/isa/pss.c outw(configAddress, val);
val 445 dev/isa/pss.c int val;
val 452 dev/isa/pss.c val = inw(config);
val 453 dev/isa/pss.c val &= INT_MASK; /* Special: 0 */
val 456 dev/isa/pss.c val = inw(config);
val 457 dev/isa/pss.c val &= INT_MASK;
val 458 dev/isa/pss.c val |= INT_TEST_BIT | INT_5_BITS;
val 461 dev/isa/pss.c val = inw(config);
val 462 dev/isa/pss.c val &= INT_MASK;
val 463 dev/isa/pss.c val |= INT_TEST_BIT | INT_7_BITS;
val 466 dev/isa/pss.c val = inw(config);
val 467 dev/isa/pss.c val &= INT_MASK;
val 468 dev/isa/pss.c val |= INT_TEST_BIT | INT_9_BITS;
val 471 dev/isa/pss.c val = inw(config);
val 472 dev/isa/pss.c val &= INT_MASK;
val 473 dev/isa/pss.c val |= INT_TEST_BIT | INT_10_BITS;
val 476 dev/isa/pss.c val = inw(config);
val 477 dev/isa/pss.c val &= INT_MASK;
val 478 dev/isa/pss.c val |= INT_TEST_BIT | INT_11_BITS;
val 481 dev/isa/pss.c val = inw(config);
val 482 dev/isa/pss.c val &= INT_MASK;
val 483 dev/isa/pss.c val |= INT_TEST_BIT | INT_12_BITS;
val 489 dev/isa/pss.c outw(config, val);
val 495 dev/isa/pss.c val = inw(config);
val 496 dev/isa/pss.c if (val & INT_TEST_PASS) {
val 503 dev/isa/pss.c val = inw(config);
val 504 dev/isa/pss.c val &= INT_TEST_BIT_MASK & INT_MASK;
val 505 dev/isa/pss.c outw(config, val);
val 521 dev/isa/pss.c int val;
val 526 dev/isa/pss.c val = inw(config);
val 527 dev/isa/pss.c val &= DMA_MASK;
val 528 dev/isa/pss.c val |= DMA_TEST_BIT | DMA_0_BITS;
val 531 dev/isa/pss.c val = inw(config);
val 532 dev/isa/pss.c val &= DMA_MASK;
val 533 dev/isa/pss.c val |= DMA_TEST_BIT | DMA_1_BITS;
val 536 dev/isa/pss.c val = inw(config);
val 537 dev/isa/pss.c val &= DMA_MASK;
val 538 dev/isa/pss.c val |= DMA_TEST_BIT | DMA_3_BITS;
val 541 dev/isa/pss.c val = inw(config);
val 542 dev/isa/pss.c val &= DMA_MASK;
val 543 dev/isa/pss.c val |= DMA_TEST_BIT | DMA_5_BITS;
val 546 dev/isa/pss.c val = inw(config);
val 547 dev/isa/pss.c val &= DMA_MASK;
val 548 dev/isa/pss.c val |= DMA_TEST_BIT | DMA_6_BITS;
val 551 dev/isa/pss.c val = inw(config);
val 552 dev/isa/pss.c val &= DMA_MASK;
val 553 dev/isa/pss.c val |= DMA_TEST_BIT | DMA_7_BITS;
val 559 dev/isa/pss.c outw(config, val);
val 565 dev/isa/pss.c val = inw(config);
val 566 dev/isa/pss.c if (val & DMA_TEST_PASS) {
val 573 dev/isa/pss.c val = inw(config);
val 574 dev/isa/pss.c val &= DMA_TEST_BIT_MASK & DMA_MASK;
val 575 dev/isa/pss.c outw(config, val);
val 614 dev/isa/pss.c int i, val, count;
val 662 dev/isa/pss.c val = inw(pss_base+PSS_STATUS);
val 663 dev/isa/pss.c if (val & PSS_READ_FULL)
val 669 dev/isa/pss.c val = inw(pss_base+PSS_STATUS);
val 670 dev/isa/pss.c if (val & PSS_READ_FULL)
val 961 dev/isa/pss.c u_short val;
val 968 dev/isa/pss.c val = inw(pc->sc_iobase+CD_CONFIG);
val 970 dev/isa/pss.c val &= CD_POL_MASK;
val 971 dev/isa/pss.c val |= CD_POL_BIT; /* XXX if (pol) */
val 972 dev/isa/pss.c outw(pc->sc_iobase+CD_CONFIG, val);
val 177 dev/isa/radiotrack.c int val;
val 183 dev/isa/radiotrack.c val = vol ? RT_CARD_ON : RT_CARD_OFF;
val 185 dev/isa/radiotrack.c sc->sc_mute ? RT_CARD_OFF : val);
val 199 dev/isa/radiotrack.c val = sc->sc_vol - vol;
val 200 dev/isa/radiotrack.c if (val < 0) {
val 201 dev/isa/radiotrack.c val *= -1;
val 208 dev/isa/radiotrack.c DELAY(val * RT_VOLUME_DELAY);
val 408 dev/isa/sbdsp.c sbdsp_mix_write(sc, mixerport, val)
val 411 dev/isa/sbdsp.c int val;
val 420 dev/isa/sbdsp.c bus_space_write_1(iot, ioh, SBP_MIXER_DATA, val);
val 432 dev/isa/sbdsp.c int val;
val 438 dev/isa/sbdsp.c val = bus_space_read_1(iot, ioh, SBP_MIXER_DATA);
val 441 dev/isa/sbdsp.c return val;
val 1489 dev/isa/sbdsp.c sbdsp_adjust(val, mask)
val 1490 dev/isa/sbdsp.c int val, mask;
val 1492 dev/isa/sbdsp.c val += (MAXVAL - mask) >> 1;
val 1493 dev/isa/sbdsp.c if (val >= MAXVAL)
val 1494 dev/isa/sbdsp.c val = MAXVAL-1;
val 1495 dev/isa/sbdsp.c return val & mask;
val 149 dev/isa/tcic2_isa.c int val, found;
val 173 dev/isa/tcic2_isa.c if ((val = tcic_chipid(iot, ioh))) {
val 174 dev/isa/tcic2_isa.c DPRINTF(("tcic id: 0x%02x\n", val));
val 175 dev/isa/tcic2_isa.c if (tcic_chipid_known(val))
val 320 dev/isa/tcic2_isa.c int irq, ist, val, reg;
val 351 dev/isa/tcic2_isa.c val = (tcic_read_ind_2(h, reg) & (~TCIC_SCF1_IRQ_MASK)) | irqmap[irq];
val 352 dev/isa/tcic2_isa.c tcic_write_ind_2(h, reg, val);
val 364 dev/isa/tcic2_isa.c int val, reg;
val 371 dev/isa/tcic2_isa.c val = tcic_read_ind_2(h, reg);
val 372 dev/isa/tcic2_isa.c val &= ~TCIC_SCF1_IRQ_MASK;
val 373 dev/isa/tcic2_isa.c tcic_write_ind_2(h, reg, val);
val 323 dev/isa/viasio.c int64_t val, rfact;
val 330 dev/isa/viasio.c val = (reg0 << 2) | reg1;
val 334 dev/isa/viasio.c val = viasio_raw2temp(val);
val 335 dev/isa/viasio.c if (val == -1) {
val 339 dev/isa/viasio.c sc->sc_hm_sensors[VT1211_HMS_TEMP1].value = val;
val 358 dev/isa/viasio.c val = (reg0 << 2) | reg1;
val 362 dev/isa/viasio.c val = viasio_raw2temp(val);
val 363 dev/isa/viasio.c if (val == -1) {
val 370 dev/isa/viasio.c i - 1].value = val;
val 376 dev/isa/viasio.c val = reg0;
val 382 dev/isa/viasio.c ((val * 100000000000ULL) / (rfact * 958));
val 388 dev/isa/viasio.c val = reg0;
val 393 dev/isa/viasio.c sc->sc_hm_sensors[VT1211_HMS_33V].value = ((val * 100000000000ULL) /
val 400 dev/isa/viasio.c val = reg0 << reg1;
val 404 dev/isa/viasio.c if (val != 0) {
val 406 dev/isa/viasio.c (sc->sc_hm_clock * 60 / 2) / val;
val 416 dev/isa/viasio.c val = reg0 << reg1;
val 420 dev/isa/viasio.c if (val != 0) {
val 422 dev/isa/viasio.c (sc->sc_hm_clock * 60 / 2) / val;
val 203 dev/isa/wds.c wds_wait(iot, ioh, port, mask, val)
val 208 dev/isa/wds.c int val;
val 210 dev/isa/wds.c while ((bus_space_read_1(iot, ioh, port) & mask) != val)
val 291 dev/isa/ym.c ym_set_3d(sc, cp, val, reg)
val 294 dev/isa/ym.c struct ad1848_volume *val;
val 299 dev/isa/ym.c ad1848_to_vol(cp, val);
val 301 dev/isa/ym.c e = (val->left * (SA3_3D_BITS + 1) + (SA3_3D_BITS + 1) / 2) /
val 303 dev/isa/ym.c (val->right * (SA3_3D_BITS + 1) + (SA3_3D_BITS + 1) / 2) /
val 46 dev/microcode/esa/esadsp.h u_int16_t addr, val;
val 71 dev/microcode/esa/esadsp.h u_int16_t addr, val;
val 473 dev/microcode/siop/ncr53cxxx.c void setarch(char *val)
val 475 dev/microcode/siop/ncr53cxxx.c switch (atoi(val)) {
val 532 dev/mii/brgphy.c uint16_t val;
val 550 dev/mii/brgphy.c PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
val 560 dev/mii/brgphy.c uint16_t val;
val 570 dev/mii/brgphy.c PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
val 597 dev/mii/brgphy.c uint16_t val;
val 606 dev/mii/brgphy.c PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
val 614 dev/mii/brgphy.c uint16_t val;
val 627 dev/mii/brgphy.c PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
val 635 dev/mii/brgphy.c uint16_t val;
val 644 dev/mii/brgphy.c PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
val 652 dev/mii/brgphy.c uint16_t val;
val 667 dev/mii/brgphy.c PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
val 673 dev/mii/brgphy.c u_int32_t val;
val 681 dev/mii/brgphy.c val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
val 683 dev/mii/brgphy.c val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
val 686 dev/mii/brgphy.c val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
val 688 dev/mii/brgphy.c val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
val 694 dev/mii/brgphy.c u_int32_t val;
val 698 dev/mii/brgphy.c val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
val 700 dev/mii/brgphy.c (val | (1 << 15) | (1 << 4)));
val 124 dev/mii/mii_bitbang.c int val = 0, err = 0, i;
val 148 dev/mii/mii_bitbang.c val <<= 1;
val 151 dev/mii/mii_bitbang.c val |= 1;
val 160 dev/mii/mii_bitbang.c return (err ? 0 : val);
val 170 dev/mii/mii_bitbang.c int phy, int reg, int val)
val 180 dev/mii/mii_bitbang.c mii_bitbang_sendbits(sc, ops, val, 16);
val 394 dev/mii/rgephy.c int val;
val 405 dev/mii/rgephy.c val = PHY_READ(sc, 4) & 0xFFF;
val 406 dev/mii/rgephy.c PHY_WRITE(sc, 4, val);
val 413 dev/mii/rgephy.c val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000;
val 414 dev/mii/rgephy.c PHY_WRITE(sc, 4, val);
val 419 dev/mii/rgephy.c val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000;
val 420 dev/mii/rgephy.c PHY_WRITE(sc, 4, val);
val 425 dev/mii/rgephy.c val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000;
val 426 dev/mii/rgephy.c PHY_WRITE(sc, 4, val);
val 431 dev/mii/rgephy.c val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000;
val 432 dev/mii/rgephy.c PHY_WRITE(sc, 4, val);
val 142 dev/onewire/owtemp.c int count_perc, count_remain, val;
val 179 dev/onewire/owtemp.c val = temp * 500000 - 250000 +
val 183 dev/onewire/owtemp.c val = temp * 500000;
val 185 dev/onewire/owtemp.c sc->sc_sensor.value = 273150000 + val;
val 210 dev/pci/amdiic.c amdiic_write(struct amdiic_softc *sc, u_int8_t reg, u_int8_t val)
val 221 dev/pci/amdiic.c bus_space_write_1(sc->sc_iot, sc->sc_ioh, AMD8111_SMB_SC_DATA, val);
val 544 dev/pci/auich.c auich_read_codec(v, reg, val)
val 547 dev/pci/auich.c u_int16_t *val;
val 562 dev/pci/auich.c *val = bus_space_read_2(sc->iot_mix, sc->mix_ioh, reg);
val 564 dev/pci/auich.c sc->sc_dev.dv_xname, reg, *val));
val 569 dev/pci/auich.c auich_write_codec(v, reg, val)
val 572 dev/pci/auich.c u_int16_t val;
val 583 dev/pci/auich.c sc->sc_dev.dv_xname, reg, val));
val 584 dev/pci/auich.c bus_space_write_2(sc->iot_mix, sc->mix_ioh, reg, val);
val 403 dev/pci/auvia.c auvia_write_codec(void *addr, u_int8_t reg, u_int16_t val)
val 411 dev/pci/auvia.c AUVIA_CODEC_PRIVALID | AUVIA_CODEC_INDEX(reg) | val);
val 418 dev/pci/auvia.c auvia_read_codec(void *addr, u_int8_t reg, u_int16_t *val)
val 434 dev/pci/auvia.c *val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, AUVIA_CODEC_CTL);
val 67 dev/pci/bktr/bktr_audio.c void bctv_gpio_write( bktr_ptr_t bktr, int port, int val );
val 363 dev/pci/bktr/bktr_audio.c bctv_gpio_write( bktr_ptr_t bktr, int port, int val )
val 371 dev/pci/bktr/bktr_audio.c data = ((val << BCTV_GPIO_VAL_SHIFT) & BCTV_GPIO_VAL_MASK) |
val 218 dev/pci/cmpci.c cmpci_mixerreg_write(struct cmpci_softc *sc, uint8_t no, uint8_t val)
val 222 dev/pci/cmpci.c bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBDATA, val);
val 229 dev/pci/cmpci.c unsigned mask, unsigned val)
val 232 dev/pci/cmpci.c (val<<shift) |
val 239 dev/pci/cmpci.c uint32_t mask, uint32_t val)
val 242 dev/pci/cmpci.c (val<<shift) |
val 1222 dev/pci/cmpci.c cmpci_adjust(int val, int mask)
val 1224 dev/pci/cmpci.c val += (MAXVAL - mask) >> 1;
val 1225 dev/pci/cmpci.c if (val >= MAXVAL)
val 1226 dev/pci/cmpci.c val = MAXVAL-1;
val 1227 dev/pci/cmpci.c return val & mask;
val 1334 dev/pci/cs4280.c int val;
val 1336 dev/pci/cs4280.c val = sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp);
val 1337 dev/pci/cs4280.c DPRINTFN(3,("mixer_set_port: val=%d\n", val));
val 1338 dev/pci/cs4280.c return (val);
val 392 dev/pci/cs4281.c u_int32_t intr, val;
val 403 dev/pci/cs4281.c val = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */
val 405 dev/pci/cs4281.c val = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */
val 429 dev/pci/cs4281.c val = BA0READ4(sc, CS4281_HDSR1);
val 1323 dev/pci/cs4281.c int val;
val 1326 dev/pci/cs4281.c val = sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp);
val 1327 dev/pci/cs4281.c DPRINTFN(3,("mixer_set_port: val=%d\n", val));
val 1328 dev/pci/cs4281.c return (val);
val 133 dev/pci/cy82c693.c cy82c693_write(const struct cy82c693_handle *cyhc, int reg, u_int8_t val)
val 145 dev/pci/cy82c693.c bus_space_write_1(cyhc->cyhc_iot, cyhc->cyhc_ioh, 1, val);
val 206 dev/pci/cz.c #define CZ_PLX_WRITE(cz, reg, val) \
val 208 dev/pci/cz.c (reg), (val))
val 216 dev/pci/cz.c #define CZ_FPGA_WRITE(cz, reg, val) \
val 217 dev/pci/cz.c bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg), (val))
val 226 dev/pci/cz.c #define CZ_FWCTL_WRITE(cz, off, val) \
val 228 dev/pci/cz.c (cz)->cz_fwctl + (off), (val))
val 236 dev/pci/cz.c #define CZTTY_CHAN_WRITE(sc, off, val) \
val 238 dev/pci/cz.c (off), (val))
val 243 dev/pci/cz.c #define CZTTY_BUF_WRITE(sc, off, val) \
val 245 dev/pci/cz.c (off), (val))
val 1853 dev/pci/emuxki.c u_int32_t val;
val 1869 dev/pci/emuxki.c val = EMU_A_ADCCR_LCHANENABLE;
val 1871 dev/pci/emuxki.c val |= EMU_A_ADCCR_RCHANENABLE;
val 1873 dev/pci/emuxki.c val = EMU_ADCCR_LCHANENABLE;
val 1875 dev/pci/emuxki.c val |= EMU_ADCCR_RCHANENABLE;
val 1877 dev/pci/emuxki.c val |= emuxki_voice_adc_rate(voice);
val 1879 dev/pci/emuxki.c emuxki_write(voice->sc, 0, EMU_ADCCR, val);
val 1893 dev/pci/emuxki.c val = emu_rd(sc, INTE, 4);
val 1894 dev/pci/emuxki.c val |= emuxki_recsrc_intrmasks[voice->dataloc.source];
val 1895 dev/pci/emuxki.c emu_wr(sc, INTE, val, 4);
val 1929 dev/pci/emuxki.c val = emu_rd(sc, INTE, 4);
val 1930 dev/pci/emuxki.c val &= ~emuxki_recsrc_intrmasks[voice->dataloc.source];
val 1931 dev/pci/emuxki.c emu_wr(sc, INTE, val, 4);
val 2462 dev/pci/emuxki.c emuxki_ac97_read(void *arg, u_int8_t reg, u_int16_t *val)
val 2469 dev/pci/emuxki.c *val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EMU_AC97DATA);
val 2476 dev/pci/emuxki.c emuxki_ac97_write(void *arg, u_int8_t reg, u_int16_t val)
val 2483 dev/pci/emuxki.c bus_space_write_2(sc->sc_iot, sc->sc_ioh, EMU_AC97DATA, val);
val 683 dev/pci/esa.c esa_playvals[i].addr, esa_playvals[i].val);
val 816 dev/pci/esa.c esa_recvals[i].addr, esa_recvals[i].val);
val 1271 dev/pci/esa.c int i, val;
val 1276 dev/pci/esa.c val = bus_space_read_1(iot, ioh, ESA_CODEC_STATUS);
val 1277 dev/pci/esa.c if ((val & 1) == 0)
val 1548 dev/pci/esa.c u_int16_t val, int index)
val 1555 dev/pci/esa.c val);
val 1564 dev/pci/esa.c u_int16_t val;
val 1573 dev/pci/esa.c val = esa_read_assp(sc, ESA_MEMTYPE_INTERNAL_DATA,
val 1577 dev/pci/esa.c val);
val 449 dev/pci/eso.c eso_write_ctlreg(sc, reg, val)
val 451 dev/pci/eso.c uint8_t reg, val;
val 457 dev/pci/eso.c eso_write_cmd(sc, val);
val 494 dev/pci/eso.c eso_write_mixreg(sc, reg, val)
val 496 dev/pci/eso.c uint8_t reg, val;
val 504 dev/pci/eso.c bus_space_write_1(sc->sc_sb_iot, sc->sc_sb_ioh, ESO_SB_MIXERDATA, val);
val 514 dev/pci/eso.c uint8_t val;
val 518 dev/pci/eso.c val = bus_space_read_1(sc->sc_sb_iot, sc->sc_sb_ioh, ESO_SB_MIXERDATA);
val 521 dev/pci/eso.c return (val);
val 308 dev/pci/fms.c fms_read_codec(addr, reg, val)
val 311 dev/pci/fms.c u_int16_t *val;
val 339 dev/pci/fms.c *val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, FM_CODEC_DATA);
val 344 dev/pci/fms.c fms_write_codec(addr, reg, val)
val 347 dev/pci/fms.c u_int16_t val;
val 362 dev/pci/fms.c bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_CODEC_DATA, val);
val 2794 dev/pci/hifn7751.c u_int32_t val)
val 2810 dev/pci/hifn7751.c bus_space_write_4(sc->sc_st0, sc->sc_sh0, reg, val);
val 2812 dev/pci/hifn7751.c bus_space_write_4(sc->sc_st1, sc->sc_sh1, reg, val);
val 169 dev/pci/hifn7751var.h #define WRITE_REG_0(sc,reg,val) hifn_write_4((sc), 0, (reg), (val))
val 170 dev/pci/hifn7751var.h #define WRITE_REG_1(sc,reg,val) hifn_write_4((sc), 1, (reg), (val))
val 74 dev/pci/ichwdt.c ichwdt_unlock_write(struct ichwdt_softc *sc, int reg, u_int32_t val)
val 81 dev/pci/ichwdt.c bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, val);
val 1108 dev/pci/if_bce.c u_int32_t val;
val 1128 dev/pci/if_bce.c val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
val 1130 dev/pci/if_bce.c if (!(val & EC_ED))
val 1159 dev/pci/if_bce.c u_int32_t val;
val 1174 dev/pci/if_bce.c val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
val 1176 dev/pci/if_bce.c if (!(val & EC_ED))
val 1186 dev/pci/if_bce.c val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS);
val 1188 dev/pci/if_bce.c if (val & RS_ERROR) {
val 1190 dev/pci/if_bce.c val = bus_space_read_4(sc->bce_btag,
val 1192 dev/pci/if_bce.c if (val & RS_DMA_IDLE)
val 1207 dev/pci/if_bce.c val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
val 1209 dev/pci/if_bce.c if (!(val & EC_ES))
val 1252 dev/pci/if_bce.c val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
val 1254 dev/pci/if_bce.c if (val & SBTML_REJ)
val 1263 dev/pci/if_bce.c val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
val 1265 dev/pci/if_bce.c if (!(val & 0x4))
val 1276 dev/pci/if_bce.c val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
val 1286 dev/pci/if_bce.c val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW);
val 1290 dev/pci/if_bce.c val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI);
val 1291 dev/pci/if_bce.c if (val & 1)
val 1294 dev/pci/if_bce.c val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE);
val 1295 dev/pci/if_bce.c if (val & SBIM_ERRORBITS)
val 1297 dev/pci/if_bce.c val & ~SBIM_ERRORBITS);
val 1302 dev/pci/if_bce.c val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW);
val 1308 dev/pci/if_bce.c val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW);
val 1315 dev/pci/if_bce.c val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL);
val 1316 dev/pci/if_bce.c if (!(val & BCE_DC_IP)) {
val 1319 dev/pci/if_bce.c } else if (val & BCE_DC_ER) { /* internal, clear reset bit if on */
val 1321 dev/pci/if_bce.c val & ~BCE_DC_ER);
val 1381 dev/pci/if_bce.c u_int32_t val;
val 1392 dev/pci/if_bce.c val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS);
val 1393 dev/pci/if_bce.c if (val & BCE_MIINTR)
val 1397 dev/pci/if_bce.c val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM);
val 1400 dev/pci/if_bce.c "0x%08x\n", sc->bce_dev.dv_xname, phy, reg, val);
val 1403 dev/pci/if_bce.c return (val & BCE_MICOMM_DATA);
val 1408 dev/pci/if_bce.c bce_mii_write(struct device *self, int phy, int reg, int val)
val 1421 dev/pci/if_bce.c (MII_COMMAND_ACK << 16) | (val & BCE_MICOMM_DATA) | /* MAGIC */
val 1435 dev/pci/if_bce.c "= 0x%08x\n", sc->bce_dev.dv_xname, phy, reg, val);
val 400 dev/pci/if_bge.c bge_writemem_ind(struct bge_softc *sc, int off, int val)
val 405 dev/pci/if_bge.c pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA, val);
val 409 dev/pci/if_bge.c bge_writereg_ind(struct bge_softc *sc, int off, int val)
val 414 dev/pci/if_bge.c pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA, val);
val 486 dev/pci/if_bge.c u_int32_t val, autopoll;
val 513 dev/pci/if_bge.c val = CSR_READ_4(sc, BGE_MI_COMM);
val 514 dev/pci/if_bge.c if (!(val & BGE_MICOMM_BUSY))
val 521 dev/pci/if_bge.c val = 0;
val 525 dev/pci/if_bge.c val = CSR_READ_4(sc, BGE_MI_COMM);
val 533 dev/pci/if_bge.c if (val & BGE_MICOMM_READFAIL)
val 536 dev/pci/if_bge.c return (val & 0xFFFF);
val 540 dev/pci/if_bge.c bge_miibus_writereg(struct device *dev, int phy, int reg, int val)
val 555 dev/pci/if_bge.c BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
val 1243 dev/pci/if_bge.c u_int32_t val;
val 1558 dev/pci/if_bge.c val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
val 1563 dev/pci/if_bge.c val |= (1 << 29);
val 1566 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
val 2095 dev/pci/if_bge.c int i, val = 0;
val 2168 dev/pci/if_bge.c u_int32_t val;
val 2170 dev/pci/if_bge.c val = CSR_READ_4(sc, BGE_MARB_MODE);
val 2171 dev/pci/if_bge.c CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
val 2188 dev/pci/if_bge.c val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
val 2189 dev/pci/if_bge.c if (val == ~BGE_MAGIC_NUMBER)
val 1812 dev/pci/if_bgereg.h #define BGE_MEMWIN_READ(pc, tag, x, val) \
val 1816 dev/pci/if_bgereg.h val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \
val 1819 dev/pci/if_bgereg.h #define BGE_MEMWIN_WRITE(pc, tag, x, val) \
val 1823 dev/pci/if_bgereg.h CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \
val 1855 dev/pci/if_bgereg.h #define RCB_WRITE_4(sc, rcb, offset, val) \
val 1857 dev/pci/if_bgereg.h rcb + offsetof(struct bge_rcb, offset), val)
val 1859 dev/pci/if_bgereg.h #define RCB_WRITE_2(sc, rcb, offset, val) \
val 1861 dev/pci/if_bgereg.h rcb + offsetof(struct bge_rcb, offset), val)
val 2239 dev/pci/if_bgereg.h #define CSR_WRITE_4(sc, reg, val) \
val 2240 dev/pci/if_bgereg.h bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val)
val 622 dev/pci/if_bnx.c u_int32_t val;
val 685 dev/pci/if_bnx.c val = REG_RD_IND(sc, BNX_SHM_HDR_SIGNATURE);
val 686 dev/pci/if_bnx.c if ((val & BNX_SHM_HDR_SIGNATURE_SIG_MASK) == BNX_SHM_HDR_SIGNATURE_SIG)
val 698 dev/pci/if_bnx.c val = REG_RD(sc, BNX_PCICFG_MISC_STATUS);
val 699 dev/pci/if_bnx.c if (val & BNX_PCICFG_MISC_STATUS_PCIX_DET) {
val 732 dev/pci/if_bnx.c } else if (val & BNX_PCICFG_MISC_STATUS_M66EN)
val 737 dev/pci/if_bnx.c if (val & BNX_PCICFG_MISC_STATUS_32BIT_DET)
val 765 dev/pci/if_bnx.c u_int32_t val;
val 843 dev/pci/if_bnx.c val = REG_RD_IND(sc, sc->bnx_shmem_base +
val 845 dev/pci/if_bnx.c if (val & BNX_SHARED_HW_CFG_PHY_2_5G)
val 1018 dev/pci/if_bnx.c u_int32_t val;
val 1019 dev/pci/if_bnx.c val = pci_conf_read(pa->pa_pc, pa->pa_tag,
val 1022 dev/pci/if_bnx.c "val = 0x%08X\n", __FUNCTION__, offset, val);
val 1023 dev/pci/if_bnx.c return (val);
val 1041 dev/pci/if_bnx.c bnx_reg_wr_ind(struct bnx_softc *sc, u_int32_t offset, u_int32_t val)
val 1046 dev/pci/if_bnx.c __FUNCTION__, offset, val);
val 1050 dev/pci/if_bnx.c pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW, val);
val 1064 dev/pci/if_bnx.c u_int32_t val)
val 1068 dev/pci/if_bnx.c "val = 0x%08X\n", __FUNCTION__, cid_addr, offset, val);
val 1072 dev/pci/if_bnx.c REG_WR(sc, BNX_CTX_DATA, val);
val 1087 dev/pci/if_bnx.c u_int32_t val;
val 1098 dev/pci/if_bnx.c val = REG_RD(sc, BNX_EMAC_MDIO_MODE);
val 1099 dev/pci/if_bnx.c val &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL;
val 1101 dev/pci/if_bnx.c REG_WR(sc, BNX_EMAC_MDIO_MODE, val);
val 1107 dev/pci/if_bnx.c val = BNX_MIPHY(phy) | BNX_MIREG(reg) |
val 1110 dev/pci/if_bnx.c REG_WR(sc, BNX_EMAC_MDIO_COMM, val);
val 1115 dev/pci/if_bnx.c val = REG_RD(sc, BNX_EMAC_MDIO_COMM);
val 1116 dev/pci/if_bnx.c if (!(val & BNX_EMAC_MDIO_COMM_START_BUSY)) {
val 1119 dev/pci/if_bnx.c val = REG_RD(sc, BNX_EMAC_MDIO_COMM);
val 1120 dev/pci/if_bnx.c val &= BNX_EMAC_MDIO_COMM_DATA;
val 1126 dev/pci/if_bnx.c if (val & BNX_EMAC_MDIO_COMM_START_BUSY) {
val 1129 dev/pci/if_bnx.c val = 0x0;
val 1131 dev/pci/if_bnx.c val = REG_RD(sc, BNX_EMAC_MDIO_COMM);
val 1135 dev/pci/if_bnx.c (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff);
val 1138 dev/pci/if_bnx.c val = REG_RD(sc, BNX_EMAC_MDIO_MODE);
val 1139 dev/pci/if_bnx.c val |= BNX_EMAC_MDIO_MODE_AUTO_POLL;
val 1141 dev/pci/if_bnx.c REG_WR(sc, BNX_EMAC_MDIO_MODE, val);
val 1147 dev/pci/if_bnx.c return (val & 0xffff);
val 1159 dev/pci/if_bnx.c bnx_miibus_write_reg(struct device *dev, int phy, int reg, int val)
val 1174 dev/pci/if_bnx.c phy, (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff);
val 1186 dev/pci/if_bnx.c val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val |
val 1268 dev/pci/if_bnx.c u_int32_t val;
val 1276 dev/pci/if_bnx.c val = REG_RD(sc, BNX_NVM_SW_ARB);
val 1277 dev/pci/if_bnx.c if (val & BNX_NVM_SW_ARB_ARB_ARB2)
val 1305 dev/pci/if_bnx.c u_int32_t val;
val 1313 dev/pci/if_bnx.c val = REG_RD(sc, BNX_NVM_SW_ARB);
val 1314 dev/pci/if_bnx.c if (!(val & BNX_NVM_SW_ARB_ARB_ARB2))
val 1340 dev/pci/if_bnx.c u_int32_t val;
val 1344 dev/pci/if_bnx.c val = REG_RD(sc, BNX_MISC_CFG);
val 1345 dev/pci/if_bnx.c REG_WR(sc, BNX_MISC_CFG, val | BNX_MISC_CFG_NVM_WR_EN_PCI);
val 1357 dev/pci/if_bnx.c val = REG_RD(sc, BNX_NVM_COMMAND);
val 1358 dev/pci/if_bnx.c if (val & BNX_NVM_COMMAND_DONE)
val 1383 dev/pci/if_bnx.c u_int32_t val;
val 1387 dev/pci/if_bnx.c val = REG_RD(sc, BNX_MISC_CFG);
val 1388 dev/pci/if_bnx.c REG_WR(sc, BNX_MISC_CFG, val & ~BNX_MISC_CFG_NVM_WR_EN);
val 1404 dev/pci/if_bnx.c u_int32_t val;
val 1408 dev/pci/if_bnx.c val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE);
val 1411 dev/pci/if_bnx.c val | BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN);
val 1425 dev/pci/if_bnx.c u_int32_t val;
val 1429 dev/pci/if_bnx.c val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE);
val 1433 dev/pci/if_bnx.c val & ~(BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN));
val 1472 dev/pci/if_bnx.c u_int32_t val;
val 1476 dev/pci/if_bnx.c val = REG_RD(sc, BNX_NVM_COMMAND);
val 1477 dev/pci/if_bnx.c if (val & BNX_NVM_COMMAND_DONE)
val 1525 dev/pci/if_bnx.c u_int32_t val;
val 1529 dev/pci/if_bnx.c val = REG_RD(sc, BNX_NVM_COMMAND);
val 1530 dev/pci/if_bnx.c if (val & BNX_NVM_COMMAND_DONE) {
val 1531 dev/pci/if_bnx.c val = REG_RD(sc, BNX_NVM_READ);
val 1533 dev/pci/if_bnx.c val = bnx_be32toh(val);
val 1534 dev/pci/if_bnx.c memcpy(ret_val, &val, 4);
val 1561 dev/pci/if_bnx.c bnx_nvram_write_dword(struct bnx_softc *sc, u_int32_t offset, u_int8_t *val,
val 1581 dev/pci/if_bnx.c memcpy(&val32, val, 4);
val 1616 dev/pci/if_bnx.c u_int32_t val;
val 1623 dev/pci/if_bnx.c val = REG_RD(sc, BNX_NVM_CFG1);
val 1636 dev/pci/if_bnx.c if (val & 0x40000000) {
val 1644 dev/pci/if_bnx.c if ((val & FLASH_BACKUP_STRAP_MASK) ==
val 1657 dev/pci/if_bnx.c if (val & (1 << 23))
val 1666 dev/pci/if_bnx.c if ((val & mask) == (flash->strapping & mask)) {
val 1697 dev/pci/if_bnx.c val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_SHARED_HW_CFG_CONFIG2);
val 1698 dev/pci/if_bnx.c val &= BNX_SHARED_HW_CFG2_NVM_SIZE_MASK;
val 1699 dev/pci/if_bnx.c if (val)
val 1700 dev/pci/if_bnx.c sc->bnx_flash_size = val;
val 2434 dev/pci/if_bnx.c u_int32_t val;
val 2455 dev/pci/if_bnx.c val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_FW_MB);
val 2456 dev/pci/if_bnx.c if ((val & BNX_FW_MSG_ACK) == (msg_data & BNX_DRV_MSG_SEQ))
val 2462 dev/pci/if_bnx.c if (((val & BNX_FW_MSG_ACK) != (msg_data & BNX_DRV_MSG_SEQ)) &&
val 2491 dev/pci/if_bnx.c u_int32_t val;
val 2500 dev/pci/if_bnx.c val = (i / 8) | BNX_RV2P_PROC1_ADDR_CMD_RDWR;
val 2501 dev/pci/if_bnx.c REG_WR(sc, BNX_RV2P_PROC1_ADDR_CMD, val);
val 2504 dev/pci/if_bnx.c val = (i / 8) | BNX_RV2P_PROC2_ADDR_CMD_RDWR;
val 2505 dev/pci/if_bnx.c REG_WR(sc, BNX_RV2P_PROC2_ADDR_CMD, val);
val 2530 dev/pci/if_bnx.c u_int32_t val;
val 2533 dev/pci/if_bnx.c val = REG_RD_IND(sc, cpu_reg->mode);
val 2534 dev/pci/if_bnx.c val |= cpu_reg->mode_value_halt;
val 2535 dev/pci/if_bnx.c REG_WR_IND(sc, cpu_reg->mode, val);
val 2589 dev/pci/if_bnx.c val = REG_RD_IND(sc, cpu_reg->mode);
val 2590 dev/pci/if_bnx.c val &= ~cpu_reg->mode_value_halt;
val 2592 dev/pci/if_bnx.c REG_WR_IND(sc, cpu_reg->mode, val);
val 2886 dev/pci/if_bnx.c u_int32_t val;
val 2892 dev/pci/if_bnx.c val = (mac_addr[0] << 8) | mac_addr[1];
val 2894 dev/pci/if_bnx.c REG_WR(sc, BNX_EMAC_MAC_MATCH0, val);
val 2896 dev/pci/if_bnx.c val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
val 2899 dev/pci/if_bnx.c REG_WR(sc, BNX_EMAC_MAC_MATCH1, val);
val 2950 dev/pci/if_bnx.c u_int32_t val;
val 2961 dev/pci/if_bnx.c val = REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS);
val 2977 dev/pci/if_bnx.c val = REG_RD(sc, BNX_MISC_ID);
val 2980 dev/pci/if_bnx.c val = BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ |
val 2983 dev/pci/if_bnx.c REG_WR(sc, BNX_PCICFG_MISC_CONFIG, val);
val 2987 dev/pci/if_bnx.c val = REG_RD(sc, BNX_PCICFG_MISC_CONFIG);
val 2988 dev/pci/if_bnx.c if ((val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ |
val 2996 dev/pci/if_bnx.c if (val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ |
val 3004 dev/pci/if_bnx.c val = REG_RD(sc, BNX_PCI_SWAP_DIAG0);
val 3005 dev/pci/if_bnx.c if (val != 0x01020304) {
val 3031 dev/pci/if_bnx.c u_int32_t val;
val 3041 dev/pci/if_bnx.c val = BNX_DMA_CONFIG_DATA_BYTE_SWAP |
val 3050 dev/pci/if_bnx.c val |= (0x2 << 20) | BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY;
val 3053 dev/pci/if_bnx.c val |= BNX_DMA_CONFIG_PCI_FAST_CLK_CMP;
val 3063 dev/pci/if_bnx.c val |= BNX_DMA_CONFIG_CNTL_PING_PONG_DMA;
val 3065 dev/pci/if_bnx.c REG_WR(sc, BNX_DMA_CONFIG, val);
val 3069 dev/pci/if_bnx.c u_int16_t val;
val 3071 dev/pci/if_bnx.c val = pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD);
val 3073 dev/pci/if_bnx.c val & ~0x2);
val 3095 dev/pci/if_bnx.c val = REG_RD(sc, BNX_MQ_CONFIG);
val 3096 dev/pci/if_bnx.c val &= ~BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE;
val 3097 dev/pci/if_bnx.c val |= BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
val 3098 dev/pci/if_bnx.c REG_WR(sc, BNX_MQ_CONFIG, val);
val 3100 dev/pci/if_bnx.c val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
val 3101 dev/pci/if_bnx.c REG_WR(sc, BNX_MQ_KNL_BYP_WIND_START, val);
val 3102 dev/pci/if_bnx.c REG_WR(sc, BNX_MQ_KNL_WIND_END, val);
val 3104 dev/pci/if_bnx.c val = (BCM_PAGE_BITS - 8) << 24;
val 3105 dev/pci/if_bnx.c REG_WR(sc, BNX_RV2P_CONFIG, val);
val 3108 dev/pci/if_bnx.c val = REG_RD(sc, BNX_TBDR_CONFIG);
val 3109 dev/pci/if_bnx.c val &= ~BNX_TBDR_CONFIG_PAGE_SIZE;
val 3110 dev/pci/if_bnx.c val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
val 3111 dev/pci/if_bnx.c REG_WR(sc, BNX_TBDR_CONFIG, val);
val 3128 dev/pci/if_bnx.c u_int32_t reg, val;
val 3137 dev/pci/if_bnx.c val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) +
val 3139 dev/pci/if_bnx.c REG_WR(sc, BNX_EMAC_BACKOFF_SEED, val);
val 3395 dev/pci/if_bnx.c u_int32_t val, addr;
val 3438 dev/pci/if_bnx.c val = BNX_L2CTX_TYPE_TYPE_L2;
val 3439 dev/pci/if_bnx.c val |= BNX_L2CTX_TYPE_SIZE_L2;
val 3440 dev/pci/if_bnx.c CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE, val);
val 3442 dev/pci/if_bnx.c val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
val 3443 dev/pci/if_bnx.c CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE, val);
val 3446 dev/pci/if_bnx.c val = (u_int32_t)((u_int64_t)sc->tx_bd_chain_paddr[0] >> 32);
val 3447 dev/pci/if_bnx.c CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_HI, val);
val 3448 dev/pci/if_bnx.c val = (u_int32_t)(sc->tx_bd_chain_paddr[0]);
val 3449 dev/pci/if_bnx.c CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_LO, val);
val 3509 dev/pci/if_bnx.c u_int32_t prod_bseq, val, addr;
val 3540 dev/pci/if_bnx.c val = BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
val 3541 dev/pci/if_bnx.c val |= BNX_L2CTX_CTX_TYPE_SIZE_L2;
val 3542 dev/pci/if_bnx.c val |= 0x02 << 8;
val 3543 dev/pci/if_bnx.c CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_CTX_TYPE, val);
val 3546 dev/pci/if_bnx.c val = (u_int32_t)((u_int64_t)sc->rx_bd_chain_paddr[0] >> 32);
val 3547 dev/pci/if_bnx.c CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_HI, val);
val 3548 dev/pci/if_bnx.c val = (u_int32_t)(sc->rx_bd_chain_paddr[0]);
val 3549 dev/pci/if_bnx.c CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_LO, val);
val 4171 dev/pci/if_bnx.c u_int32_t val;
val 4179 dev/pci/if_bnx.c val = REG_RD(sc, BNX_HC_COMMAND);
val 4180 dev/pci/if_bnx.c REG_WR(sc, BNX_HC_COMMAND, val | BNX_HC_COMMAND_COAL_NOW);
val 4273 dev/pci/if_bnx.c u_int32_t val;
val 4282 dev/pci/if_bnx.c val = (BCM_PAGE_BITS - 8) << 24;
val 4283 dev/pci/if_bnx.c REG_WR(sc, BNX_RV2P_CONFIG, val);
val 663 dev/pci/if_bnxreg.h #define REG_WR(sc, reg, val) bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, reg, val)
val 664 dev/pci/if_bnxreg.h #define REG_WR16(sc, reg, val) bus_space_write_2(sc->bnx_btag, sc->bnx_bhandle, reg, val)
val 667 dev/pci/if_bnxreg.h #define REG_WR_IND(sc, offset, val) bnx_reg_wr_ind(sc, offset, val)
val 668 dev/pci/if_bnxreg.h #define CTX_WR(sc, cid_addr, offset, val) bnx_ctx_wr(sc, cid_addr, offset, val)
val 1453 dev/pci/if_cas.c cas_mii_writereg(struct device *self, int phy, int reg, int val)
val 1464 dev/pci/if_cas.c phy, reg, val);
val 1481 dev/pci/if_cas.c (val & CAS_MIF_FRAME_DATA);
val 1582 dev/pci/if_cas.c cas_pcs_writereg(struct device *self, int phy, int reg, int val)
val 1591 dev/pci/if_cas.c phy, reg, val);
val 1614 dev/pci/if_cas.c bus_space_write_4(t, pcs, reg, val);
val 713 dev/pci/if_che.c che_miibus_writereg(struct device *dev, int phy, int reg, int val)
val 719 dev/pci/if_che.c che_write(sc->sc_cheg, CHE_REG_MI1_DATA, val);
val 745 dev/pci/if_che.c che_miibus_ind_writereg(struct device *dev, int phy, int reg, int val)
val 756 dev/pci/if_che.c che_write(sc->sc_cheg, CHE_REG_MI1_DATA, val);
val 32 dev/pci/if_devar.h #define TULIP_CSR_WRITE(sc, csr, val) \
val 33 dev/pci/if_devar.h bus_space_write_4((sc)->tulip_bustag, (sc)->tulip_bushandle, (sc)->tulip_csrs.csr, (val))
val 37 dev/pci/if_devar.h #define TULIP_CSR_WRITEBYTE(sc, csr, val) \
val 38 dev/pci/if_devar.h bus_space_write_1((sc)->tulip_bustag, (sc)->tulip_bushandle, (sc)->tulip_csrs.csr, (val))
val 1432 dev/pci/if_em.c int val, rid;
val 1438 dev/pci/if_em.c val = pci_conf_read(pa->pa_pc, pa->pa_tag, EM_MMBA);
val 1439 dev/pci/if_em.c if (PCI_MAPREG_TYPE(val) != PCI_MAPREG_TYPE_MEM) {
val 1443 dev/pci/if_em.c if (pci_mapreg_map(pa, EM_MMBA, PCI_MAPREG_MEM_TYPE(val), 0,
val 1453 dev/pci/if_em.c val = pci_conf_read(pa->pa_pc, pa->pa_tag, rid);
val 1454 dev/pci/if_em.c if (PCI_MAPREG_TYPE(val) == PCI_MAPREG_TYPE_IO) {
val 1459 dev/pci/if_em.c if (PCI_MAPREG_MEM_TYPE(val) ==
val 1476 dev/pci/if_em.c val = pci_conf_read(pa->pa_pc, pa->pa_tag, EM_FLASH);
val 1477 dev/pci/if_em.c if (PCI_MAPREG_TYPE(val) != PCI_MAPREG_TYPE_MEM) {
val 1482 dev/pci/if_em.c if (pci_mapreg_map(pa, EM_FLASH, PCI_MAPREG_MEM_TYPE(val), 0,
val 420 dev/pci/if_em_hw.h #define E1000_WRITE_REG_IO(a, reg, val) \
val 421 dev/pci/if_em_hw.h em_write_reg_io((a), E1000_##reg, val)
val 173 dev/pci/if_ipw.c uint16_t val;
val 240 dev/pci/if_ipw.c val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0);
val 241 dev/pci/if_ipw.c ic->ic_myaddr[0] = val >> 8;
val 242 dev/pci/if_ipw.c ic->ic_myaddr[1] = val & 0xff;
val 243 dev/pci/if_ipw.c val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1);
val 244 dev/pci/if_ipw.c ic->ic_myaddr[2] = val >> 8;
val 245 dev/pci/if_ipw.c ic->ic_myaddr[3] = val & 0xff;
val 246 dev/pci/if_ipw.c val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2);
val 247 dev/pci/if_ipw.c ic->ic_myaddr[4] = val >> 8;
val 248 dev/pci/if_ipw.c ic->ic_myaddr[5] = val & 0xff;
val 620 dev/pci/if_ipw.c uint32_t val;
val 628 dev/pci/if_ipw.c uint32_t val;
val 637 dev/pci/if_ipw.c val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE);
val 638 dev/pci/if_ipw.c val &= 0xf;
val 641 dev/pci/if_ipw.c for (i = 0; i < N(rates) && rates[i].val != val; i++);
val 708 dev/pci/if_ipw.c uint16_t val;
val 738 dev/pci/if_ipw.c val = 0;
val 743 dev/pci/if_ipw.c val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n;
val 753 dev/pci/if_ipw.c return val;
val 285 dev/pci/if_ipwreg.h #define CSR_WRITE_1(sc, reg, val) \
val 286 dev/pci/if_ipwreg.h bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
val 288 dev/pci/if_ipwreg.h #define CSR_WRITE_2(sc, reg, val) \
val 289 dev/pci/if_ipwreg.h bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
val 291 dev/pci/if_ipwreg.h #define CSR_WRITE_4(sc, reg, val) \
val 292 dev/pci/if_ipwreg.h bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
val 301 dev/pci/if_ipwreg.h #define MEM_WRITE_1(sc, addr, val) do { \
val 303 dev/pci/if_ipwreg.h CSR_WRITE_1((sc), IPW_CSR_INDIRECT_DATA, (val)); \
val 306 dev/pci/if_ipwreg.h #define MEM_WRITE_2(sc, addr, val) do { \
val 308 dev/pci/if_ipwreg.h CSR_WRITE_2((sc), IPW_CSR_INDIRECT_DATA, (val)); \
val 311 dev/pci/if_ipwreg.h #define MEM_WRITE_4(sc, addr, val) do { \
val 313 dev/pci/if_ipwreg.h CSR_WRITE_4((sc), IPW_CSR_INDIRECT_DATA, (val)); \
val 324 dev/pci/if_ipwreg.h #define IPW_EEPROM_CTL(sc, val) do { \
val 325 dev/pci/if_ipwreg.h MEM_WRITE_4((sc), IPW_MEM_EEPROM_CTL, (val)); \
val 178 dev/pci/if_iwi.c uint16_t val;
val 281 dev/pci/if_iwi.c val = iwi_read_prom_word(sc, IWI_EEPROM_MAC + 0);
val 282 dev/pci/if_iwi.c ic->ic_myaddr[0] = val & 0xff;
val 283 dev/pci/if_iwi.c ic->ic_myaddr[1] = val >> 8;
val 284 dev/pci/if_iwi.c val = iwi_read_prom_word(sc, IWI_EEPROM_MAC + 1);
val 285 dev/pci/if_iwi.c ic->ic_myaddr[2] = val & 0xff;
val 286 dev/pci/if_iwi.c ic->ic_myaddr[3] = val >> 8;
val 287 dev/pci/if_iwi.c val = iwi_read_prom_word(sc, IWI_EEPROM_MAC + 2);
val 288 dev/pci/if_iwi.c ic->ic_myaddr[4] = val & 0xff;
val 289 dev/pci/if_iwi.c ic->ic_myaddr[5] = val >> 8;
val 675 dev/pci/if_iwi.c uint32_t val;
val 684 dev/pci/if_iwi.c val = CSR_READ_4(sc, IWI_CSR_CURRENT_TX_RATE);
val 686 dev/pci/if_iwi.c rate = iwi_rate(val);
val 791 dev/pci/if_iwi.c uint16_t val;
val 821 dev/pci/if_iwi.c val = 0;
val 826 dev/pci/if_iwi.c val |= ((tmp & IWI_EEPROM_Q) >> IWI_EEPROM_SHIFT_Q) << n;
val 836 dev/pci/if_iwi.c return val;
val 438 dev/pci/if_iwireg.h #define CSR_WRITE_1(sc, reg, val) \
val 439 dev/pci/if_iwireg.h bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
val 441 dev/pci/if_iwireg.h #define CSR_WRITE_2(sc, reg, val) \
val 442 dev/pci/if_iwireg.h bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
val 444 dev/pci/if_iwireg.h #define CSR_WRITE_4(sc, reg, val) \
val 445 dev/pci/if_iwireg.h bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
val 453 dev/pci/if_iwireg.h #define MEM_WRITE_1(sc, addr, val) do { \
val 455 dev/pci/if_iwireg.h CSR_WRITE_1((sc), IWI_CSR_INDIRECT_DATA, (val)); \
val 458 dev/pci/if_iwireg.h #define MEM_WRITE_2(sc, addr, val) do { \
val 460 dev/pci/if_iwireg.h CSR_WRITE_2((sc), IWI_CSR_INDIRECT_DATA, (val)); \
val 463 dev/pci/if_iwireg.h #define MEM_WRITE_4(sc, addr, val) do { \
val 465 dev/pci/if_iwireg.h CSR_WRITE_4((sc), IWI_CSR_INDIRECT_DATA, (val)); \
val 476 dev/pci/if_iwireg.h #define IWI_EEPROM_CTL(sc, val) do { \
val 477 dev/pci/if_iwireg.h MEM_WRITE_4((sc), IWI_MEM_EEPROM_CTL, (val)); \
val 929 dev/pci/if_ixgb.c int val;
val 935 dev/pci/if_ixgb.c val = pci_conf_read(pa->pa_pc, pa->pa_tag, IXGB_MMBA);
val 936 dev/pci/if_ixgb.c if (PCI_MAPREG_TYPE(val) != PCI_MAPREG_TYPE_MEM) {
val 940 dev/pci/if_ixgb.c if (pci_mapreg_map(pa, IXGB_MMBA, PCI_MAPREG_MEM_TYPE(val), 0,
val 195 dev/pci/if_lge.c u_int32_t val;
val 209 dev/pci/if_lge.c val = CSR_READ_4(sc, LGE_EEDATA);
val 212 dev/pci/if_lge.c *dest = (val >> 16) & 0xFFFF;
val 214 dev/pci/if_lge.c *dest = val & 0xFFFF;
val 537 dev/pci/if_lgereg.h #define CSR_WRITE_4(sc, reg, val) \
val 538 dev/pci/if_lgereg.h bus_space_write_4(sc->lge_btag, sc->lge_bhandle, reg, val)
val 543 dev/pci/if_lgereg.h #define CSR_WRITE_2(sc, reg, val) \
val 544 dev/pci/if_lgereg.h bus_space_write_2(sc->lge_btag, sc->lge_bhandle, reg, val)
val 549 dev/pci/if_lgereg.h #define CSR_WRITE_1(sc, reg, val) \
val 550 dev/pci/if_lgereg.h bus_space_write_1(sc->lge_btag, sc->lge_bhandle, reg, val)
val 184 dev/pci/if_lmc_common.c u_int32_t val;
val 244 dev/pci/if_lmc_common.c val = LMC_CSR_READ(sc, csr_sia_general);
val 245 dev/pci/if_lmc_common.c val |= (TULIP_WATCHDOG_TXDISABLE | TULIP_WATCHDOG_RXDISABLE);
val 246 dev/pci/if_lmc_common.c LMC_CSR_WRITE(sc, csr_sia_general, val);
val 142 dev/pci/if_lmcvar.h #define LMC_CSR_WRITE(sc, csr, val) \
val 143 dev/pci/if_lmcvar.h bus_space_write_4((sc)->lmc_bustag, (sc)->lmc_bushandle, (sc)->lmc_csrs.csr, (val))
val 147 dev/pci/if_lmcvar.h #define LMC_CSR_WRITEBYTE(sc, csr, val) \
val 148 dev/pci/if_lmcvar.h bus_space_write_1((sc)->lmc_bustag, (sc)->lmc_bushandle, (sc)->lmc_csrs.csr, (val))
val 260 dev/pci/if_msk.c u_int16_t val;
val 268 dev/pci/if_msk.c val = SK_YU_READ_2(sc_if, YUKON_SMICR);
val 269 dev/pci/if_msk.c if (val & YU_SMICR_READ_VALID)
val 282 dev/pci/if_msk.c val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
val 285 dev/pci/if_msk.c phy, reg, val));
val 287 dev/pci/if_msk.c return (val);
val 291 dev/pci/if_msk.c msk_miibus_writereg(struct device *dev, int phy, int reg, int val)
val 297 dev/pci/if_msk.c phy, reg, val));
val 299 dev/pci/if_msk.c SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
val 383 dev/pci/if_nfe.c uint32_t val;
val 412 dev/pci/if_nfe.c val = NFE_READ(sc, NFE_PHY_DATA);
val 413 dev/pci/if_nfe.c if (val != 0xffffffff && val != 0)
val 417 dev/pci/if_nfe.c sc->sc_dev.dv_xname, phy, reg, val));
val 419 dev/pci/if_nfe.c return val;
val 423 dev/pci/if_nfe.c nfe_miibus_writereg(struct device *dev, int phy, int reg, int val)
val 436 dev/pci/if_nfe.c NFE_WRITE(sc, NFE_PHY_DATA, val);
val 191 dev/pci/if_nfereg.h #define NFE_WRITE(sc, reg, val) \
val 192 dev/pci/if_nfereg.h bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, (reg), (val))
val 674 dev/pci/if_ngereg.h #define CSR_WRITE_4(sc, reg, val) \
val 675 dev/pci/if_ngereg.h bus_space_write_4(sc->nge_btag, sc->nge_bhandle, reg, val)
val 513 dev/pci/if_pcn.c pcn_csr_write(struct pcn_softc *sc, int reg, uint32_t val)
val 517 dev/pci/if_pcn.c bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, val);
val 529 dev/pci/if_pcn.c pcn_bcr_write(struct pcn_softc *sc, int reg, uint32_t val)
val 533 dev/pci/if_pcn.c bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_BDP, val);
val 658 dev/pci/if_pcn.c uint32_t val;
val 659 dev/pci/if_pcn.c val = pcn_csr_read(sc, LE_CSR12 + i);
val 660 dev/pci/if_pcn.c enaddr[2*i] = val & 0x0ff;
val 661 dev/pci/if_pcn.c enaddr[2*i+1] = (val >> 8) & 0x0ff;
val 2154 dev/pci/if_pcn.c pcn_mii_writereg(struct device *self, int phy, int reg, int val)
val 2159 dev/pci/if_pcn.c pcn_bcr_write(sc, LE_BCR34, val);
val 815 dev/pci/if_san_te1.h #define ALOS_ALARM(val) (val & BIT_ALOS_ALARM) ? "ON" : "OFF"
val 816 dev/pci/if_san_te1.h #define LOS_ALARM(val) (val & BIT_LOS_ALARM) ? "ON" : "OFF"
val 817 dev/pci/if_san_te1.h #define ALTLOS_ALARM(val) (val & BIT_ALTLOS_ALARM) ? "ON" : "OFF"
val 818 dev/pci/if_san_te1.h #define OOF_ALARM(val) (val & BIT_OOF_ALARM) ? "ON" : "OFF"
val 819 dev/pci/if_san_te1.h #define RED_ALARM(val) (val & BIT_RED_ALARM) ? "ON" : "OFF"
val 820 dev/pci/if_san_te1.h #define AIS_ALARM(val) (val & BIT_AIS_ALARM) ? "ON" : "OFF"
val 821 dev/pci/if_san_te1.h #define OOSMF_ALARM(val) (val & BIT_OOSMF_ALARM) ? "ON" : "OFF"
val 822 dev/pci/if_san_te1.h #define OOCMF_ALARM(val) (val & BIT_OOCMF_ALARM) ? "ON" : "OFF"
val 823 dev/pci/if_san_te1.h #define OOOF_ALARM(val) (val & BIT_OOOF_ALARM) ? "ON" : "OFF"
val 824 dev/pci/if_san_te1.h #define RAI_ALARM(val) (val & BIT_RAI_ALARM) ? "ON" : "OFF"
val 825 dev/pci/if_san_te1.h #define YEL_ALARM(val) (val & BIT_YEL_ALARM) ? "ON" : "OFF"
val 827 dev/pci/if_san_te1.h #define MEDIA_DECODE(val) (val == WAN_MEDIA_T1) ? "T1" : \
val 828 dev/pci/if_san_te1.h (val == WAN_MEDIA_E1) ? "E1" : "Unknown"
val 830 dev/pci/if_san_te1.h #define LCODE_DECODE(val) (val == WAN_LC_AMI) ? "AMI" : \
val 831 dev/pci/if_san_te1.h (val == WAN_LC_B8ZS) ? "B8ZS" : \
val 832 dev/pci/if_san_te1.h (val == WAN_LC_HDB3) ? "HDB3" : "Unknown"
val 834 dev/pci/if_san_te1.h #define FRAME_DECODE(val) (val == WAN_FR_ESF) ? "ESF" : \
val 835 dev/pci/if_san_te1.h (val == WAN_FR_D4) ? "D4" : \
val 836 dev/pci/if_san_te1.h (val == WAN_FR_CRC4) ? "CRC4" : \
val 837 dev/pci/if_san_te1.h (val == WAN_FR_NCRC4) ? "non-CRC4" : \
val 838 dev/pci/if_san_te1.h (val == WAN_FR_UNFRAMED) ? \
val 841 dev/pci/if_san_te1.h #define TECLK_DECODE(val) (val == WAN_NORMAL_CLK) ? "Normal" : \
val 842 dev/pci/if_san_te1.h (val == WAN_MASTER_CLK) ? "Master" : \
val 845 dev/pci/if_san_te1.h #define LBO_DECODE(val) \
val 846 dev/pci/if_san_te1.h (val == WAN_T1_LBO_0_DB) ? "0db" : \
val 847 dev/pci/if_san_te1.h (val == WAN_T1_LBO_75_DB) ? "7.5db" : \
val 848 dev/pci/if_san_te1.h (val == WAN_T1_LBO_15_DB) ? "15dB" : \
val 849 dev/pci/if_san_te1.h (val == WAN_T1_LBO_225_DB) ? "22.5dB" : \
val 850 dev/pci/if_san_te1.h (val == WAN_T1_0_110) ? "0-110ft" : \
val 851 dev/pci/if_san_te1.h (val == WAN_T1_110_220) ? "110-220ft" : \
val 852 dev/pci/if_san_te1.h (val == WAN_T1_220_330) ? "220-330ft" : \
val 853 dev/pci/if_san_te1.h (val == WAN_T1_330_440) ? "330-440ft" : \
val 854 dev/pci/if_san_te1.h (val == WAN_T1_440_550) ? "440-550ft" : \
val 855 dev/pci/if_san_te1.h (val == WAN_T1_550_660) ? "550-660ft" : "Unknown"
val 235 dev/pci/if_sandrv.h #define WAN_ASSERT(val) \
val 236 dev/pci/if_sandrv.h if (val){ \
val 243 dev/pci/if_sandrv.h #define WAN_ASSERT1(val) \
val 244 dev/pci/if_sandrv.h if (val){ \
val 251 dev/pci/if_sandrv.h #define WAN_ASSERT2(val, ret) \
val 252 dev/pci/if_sandrv.h if (val){ \
val 590 dev/pci/if_sis.c int i, val = 0;
val 610 dev/pci/if_sis.c val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
val 612 dev/pci/if_sis.c if (val == 0xFFFF)
val 615 dev/pci/if_sis.c return (val);
val 470 dev/pci/if_sisreg.h #define CSR_WRITE_4(sc, reg, val) \
val 471 dev/pci/if_sisreg.h bus_space_write_4(sc->sis_btag, sc->sis_bhandle, reg, val)
val 279 dev/pci/if_sk.c sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val)
val 298 dev/pci/if_sk.c SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
val 333 dev/pci/if_sk.c u_int16_t val;
val 349 dev/pci/if_sk.c val = SK_YU_READ_2(sc_if, YUKON_SMICR);
val 350 dev/pci/if_sk.c if (val & YU_SMICR_READ_VALID)
val 363 dev/pci/if_sk.c val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
val 366 dev/pci/if_sk.c phy, reg, val));
val 368 dev/pci/if_sk.c return (val);
val 372 dev/pci/if_sk.c sk_marv_miibus_writereg(struct device *dev, int phy, int reg, int val)
val 378 dev/pci/if_sk.c phy, reg, val));
val 380 dev/pci/if_sk.c SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
val 1088 dev/pci/if_sk.c u_int32_t chunk, val;
val 1091 dev/pci/if_sk.c val = sc->sk_rboff / sizeof(u_int64_t);
val 1092 dev/pci/if_sk.c sc_if->sk_rx_ramstart = val;
val 1093 dev/pci/if_sk.c val += (chunk / sizeof(u_int64_t));
val 1094 dev/pci/if_sk.c sc_if->sk_rx_ramend = val - 1;
val 1095 dev/pci/if_sk.c sc_if->sk_tx_ramstart = val;
val 1096 dev/pci/if_sk.c val += (chunk / sizeof(u_int64_t));
val 1097 dev/pci/if_sk.c sc_if->sk_tx_ramend = val - 1;
val 1099 dev/pci/if_sk.c u_int32_t chunk, val;
val 1102 dev/pci/if_sk.c val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
val 1104 dev/pci/if_sk.c sc_if->sk_rx_ramstart = val;
val 1105 dev/pci/if_sk.c val += (chunk / sizeof(u_int64_t));
val 1106 dev/pci/if_sk.c sc_if->sk_rx_ramend = val - 1;
val 1107 dev/pci/if_sk.c sc_if->sk_tx_ramstart = val;
val 1108 dev/pci/if_sk.c val += (chunk / sizeof(u_int64_t));
val 1109 dev/pci/if_sk.c sc_if->sk_tx_ramend = val - 1;
val 2230 dev/pci/if_sk.c u_int32_t val;
val 2233 dev/pci/if_sk.c val = sk_win_read_4(sc, SK_GPIO);
val 2235 dev/pci/if_sk.c val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
val 2237 dev/pci/if_sk.c val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
val 2238 dev/pci/if_sk.c sk_win_write_4(sc, SK_GPIO, val);
val 2260 dev/pci/if_sk.c bhack[i].val);
val 2687 dev/pci/if_sk.c u_int32_t val;
val 2700 dev/pci/if_sk.c val = CSR_READ_4(sc, sc_if->sk_tx_bmu);
val 2701 dev/pci/if_sk.c if (!(val & SK_TXBMU_TX_STOP))
val 2711 dev/pci/if_sk.c val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR);
val 2712 dev/pci/if_sk.c if (!(val & SK_RXBMU_RX_STOP))
val 2721 dev/pci/if_sk.c u_int32_t val;
val 2724 dev/pci/if_sk.c val = sk_win_read_4(sc, SK_GPIO);
val 2726 dev/pci/if_sk.c val |= SK_GPIO_DIR0;
val 2727 dev/pci/if_sk.c val &= ~SK_GPIO_DAT0;
val 2729 dev/pci/if_sk.c val |= SK_GPIO_DIR2;
val 2730 dev/pci/if_sk.c val &= ~SK_GPIO_DAT2;
val 2732 dev/pci/if_sk.c sk_win_write_4(sc, SK_GPIO, val);
val 116 dev/pci/if_skreg.h #define SK_IF_WRITE_4(sc_if, skip, reg, val) \
val 118 dev/pci/if_skreg.h reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
val 119 dev/pci/if_skreg.h #define SK_IF_WRITE_2(sc_if, skip, reg, val) \
val 121 dev/pci/if_skreg.h reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
val 122 dev/pci/if_skreg.h #define SK_IF_WRITE_1(sc_if, skip, reg, val) \
val 124 dev/pci/if_skreg.h reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
val 1366 dev/pci/if_skreg.h #define SK_XM_WRITE_4(sc, reg, val) \
val 1368 dev/pci/if_skreg.h ((val) & 0xFFFF)); \
val 1370 dev/pci/if_skreg.h ((val) >> 16) & 0xFFFF)
val 1375 dev/pci/if_skreg.h #define SK_XM_WRITE_4(sc, reg, val) \
val 1376 dev/pci/if_skreg.h sk_win_write_4(sc->sk_softc, SK_XMAC_REG(sc, reg), (val))
val 1382 dev/pci/if_skreg.h #define SK_XM_WRITE_2(sc, reg, val) \
val 1383 dev/pci/if_skreg.h sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), val)
val 1408 dev/pci/if_skreg.h #define SK_YU_WRITE_4(sc, reg, val) \
val 1409 dev/pci/if_skreg.h sk_win_write_4((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val))
val 1411 dev/pci/if_skreg.h #define SK_YU_WRITE_2(sc, reg, val) \
val 1412 dev/pci/if_skreg.h sk_win_write_2((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val))
val 1472 dev/pci/if_skreg.h #define CSR_WRITE_4(sc, reg, val) \
val 1473 dev/pci/if_skreg.h bus_space_write_4((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val))
val 1474 dev/pci/if_skreg.h #define CSR_WRITE_2(sc, reg, val) \
val 1475 dev/pci/if_skreg.h bus_space_write_2((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val))
val 1476 dev/pci/if_skreg.h #define CSR_WRITE_1(sc, reg, val) \
val 1477 dev/pci/if_skreg.h bus_space_write_1((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val))
val 181 dev/pci/if_skvar.h int val;
val 451 dev/pci/if_stereg.h #define CSR_WRITE_4(sc, reg, val) \
val 452 dev/pci/if_stereg.h bus_space_write_4(sc->ste_btag, sc->ste_bhandle, reg, val)
val 453 dev/pci/if_stereg.h #define CSR_WRITE_2(sc, reg, val) \
val 454 dev/pci/if_stereg.h bus_space_write_2(sc->ste_btag, sc->ste_bhandle, reg, val)
val 455 dev/pci/if_stereg.h #define CSR_WRITE_1(sc, reg, val) \
val 456 dev/pci/if_stereg.h bus_space_write_1(sc->ste_btag, sc->ste_bhandle, reg, val)
val 1650 dev/pci/if_stge.c stge_mii_writereg(struct device *self, int phy, int reg, int val)
val 1653 dev/pci/if_stge.c mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg, val);
val 1695 dev/pci/if_stge.c stge_mii_bitbang_write(struct device *self, uint32_t val)
val 1699 dev/pci/if_stge.c CSR_WRITE_1(sc, STGE_PhyCtrl, val | sc->sc_PhyCtrl);
val 54 dev/pci/if_stgereg.h #define CSR_WRITE_4(_sc, reg, val) \
val 55 dev/pci/if_stgereg.h bus_space_write_4((_sc)->sc_st, (_sc)->sc_sh, (reg), (val))
val 56 dev/pci/if_stgereg.h #define CSR_WRITE_2(_sc, reg, val) \
val 57 dev/pci/if_stgereg.h bus_space_write_2((_sc)->sc_st, (_sc)->sc_sh, (reg), (val))
val 58 dev/pci/if_stgereg.h #define CSR_WRITE_1(_sc, reg, val) \
val 59 dev/pci/if_stgereg.h bus_space_write_1((_sc)->sc_st, (_sc)->sc_sh, (reg), (val))
val 975 dev/pci/if_tireg.h #define CSR_WRITE_4(sc, reg, val) \
val 976 dev/pci/if_tireg.h bus_space_write_4(sc->ti_btag, sc->ti_bhandle, (reg), (val))
val 330 dev/pci/if_tl.c void tl_dio_write8(sc, reg, val)
val 333 dev/pci/if_tl.c int val;
val 336 dev/pci/if_tl.c CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val);
val 340 dev/pci/if_tl.c void tl_dio_write16(sc, reg, val)
val 343 dev/pci/if_tl.c int val;
val 346 dev/pci/if_tl.c CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val);
val 350 dev/pci/if_tl.c void tl_dio_write32(sc, reg, val)
val 353 dev/pci/if_tl.c int val;
val 356 dev/pci/if_tl.c CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val);
val 501 dev/pci/if_tlreg.h #define CSR_WRITE_4(sc, reg, val) \
val 502 dev/pci/if_tlreg.h bus_space_write_4(sc->tl_btag, sc->tl_bhandle, reg, val)
val 503 dev/pci/if_tlreg.h #define CSR_WRITE_2(sc, reg, val) \
val 504 dev/pci/if_tlreg.h bus_space_write_2(sc->tl_btag, sc->tl_bhandle, reg, val)
val 505 dev/pci/if_tlreg.h #define CSR_WRITE_1(sc, reg, val) \
val 506 dev/pci/if_tlreg.h bus_space_write_1(sc->tl_btag, sc->tl_bhandle, reg, val)
val 611 dev/pci/if_txpreg.h #define WRITE_REG(sc,reg,val) \
val 612 dev/pci/if_txpreg.h bus_space_write_4((sc)->sc_bt, (sc)->sc_bh, reg, val)
val 98 dev/pci/if_vgevar.h #define CSR_WRITE_4(sc, reg, val) \
val 99 dev/pci/if_vgevar.h bus_space_write_4(sc->vge_btag, sc->vge_bhandle, reg, val)
val 100 dev/pci/if_vgevar.h #define CSR_WRITE_2(sc, reg, val) \
val 101 dev/pci/if_vgevar.h bus_space_write_2(sc->vge_btag, sc->vge_bhandle, reg, val)
val 102 dev/pci/if_vgevar.h #define CSR_WRITE_1(sc, reg, val) \
val 103 dev/pci/if_vgevar.h bus_space_write_1(sc->vge_btag, sc->vge_bhandle, reg, val)
val 482 dev/pci/if_vrreg.h #define CSR_WRITE_4(sc, reg, val) \
val 483 dev/pci/if_vrreg.h bus_space_write_4(sc->vr_btag, sc->vr_bhandle, reg, val)
val 484 dev/pci/if_vrreg.h #define CSR_WRITE_2(sc, reg, val) \
val 485 dev/pci/if_vrreg.h bus_space_write_2(sc->vr_btag, sc->vr_bhandle, reg, val)
val 486 dev/pci/if_vrreg.h #define CSR_WRITE_1(sc, reg, val) \
val 487 dev/pci/if_vrreg.h bus_space_write_1(sc->vr_btag, sc->vr_bhandle, reg, val)
val 385 dev/pci/if_wbreg.h #define CSR_WRITE_4(sc, reg, val) \
val 386 dev/pci/if_wbreg.h bus_space_write_4(sc->wb_btag, sc->wb_bhandle, reg, val)
val 387 dev/pci/if_wbreg.h #define CSR_WRITE_2(sc, reg, val) \
val 388 dev/pci/if_wbreg.h bus_space_write_2(sc->wb_btag, sc->wb_bhandle, reg, val)
val 389 dev/pci/if_wbreg.h #define CSR_WRITE_1(sc, reg, val) \
val 390 dev/pci/if_wbreg.h bus_space_write_1(sc->wb_btag, sc->wb_bhandle, reg, val)
val 939 dev/pci/if_wpi.c uint32_t val;
val 947 dev/pci/if_wpi.c if ((val = WPI_READ(sc, WPI_EEPROM_CTL)) &
val 957 dev/pci/if_wpi.c *out++ = val >> 16;
val 959 dev/pci/if_wpi.c *out++ = val >> 24;
val 2126 dev/pci/if_wpi.c uint64_t val, mod;
val 2134 dev/pci/if_wpi.c val = (uint64_t)ni->ni_intval * 1024; /* msecs -> usecs */
val 2135 dev/pci/if_wpi.c mod = letoh64(tsf.tstamp) % val;
val 2136 dev/pci/if_wpi.c tsf.binitval = htole32((uint32_t)(val - mod));
val 2139 dev/pci/if_wpi.c ni->ni_intval, letoh64(tsf.tstamp), (uint32_t)(val - mod)));
val 722 dev/pci/if_wpireg.h #define WPI_WRITE(sc, reg, val) \
val 723 dev/pci/if_wpireg.h bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
val 242 dev/pci/if_xge.c #define PIF_WCSR(csr, val) pif_wcsr(sc, csr, val)
val 244 dev/pci/if_xge.c #define TXP_WCSR(csr, val) txp_wcsr(sc, csr, val)
val 245 dev/pci/if_xge.c #define PIF_WKEY(csr, val) pif_wkey(sc, csr, val)
val 248 dev/pci/if_xge.c pif_wcsr(struct xge_softc *sc, bus_size_t csr, uint64_t val)
val 252 dev/pci/if_xge.c lval = val&0xffffffff;
val 253 dev/pci/if_xge.c hval = val>>32;
val 262 dev/pci/if_xge.c uint64_t val, val2;
val 264 dev/pci/if_xge.c val = bus_space_read_4(sc->sc_st, sc->sc_sh, csr);
val 266 dev/pci/if_xge.c val |= (val2 << 32);
val 267 dev/pci/if_xge.c return (val);
val 271 dev/pci/if_xge.c txp_wcsr(struct xge_softc *sc, bus_size_t csr, uint64_t val)
val 275 dev/pci/if_xge.c lval = val&0xffffffff;
val 276 dev/pci/if_xge.c hval = val>>32;
val 284 dev/pci/if_xge.c pif_wkey(struct xge_softc *sc, bus_size_t csr, uint64_t val)
val 288 dev/pci/if_xge.c lval = val&0xffffffff;
val 289 dev/pci/if_xge.c hval = val>>32;
val 349 dev/pci/if_xge.c uint64_t val;
val 383 dev/pci/if_xge.c val = (uint64_t)0xFFFFFFFFFFFFFFFFULL;
val 384 dev/pci/if_xge.c val &= ~(TxF_R_SE|RxF_W_SE);
val 385 dev/pci/if_xge.c PIF_WCSR(SWAPPER_CTRL, val);
val 386 dev/pci/if_xge.c PIF_WCSR(SWAPPER_CTRL, val);
val 389 dev/pci/if_xge.c if ((val = PIF_RCSR(PIF_RD_SWAPPER_Fb)) != SWAPPER_MAGIC) {
val 391 dev/pci/if_xge.c (unsigned long long)val, SWAPPER_MAGIC);
val 422 dev/pci/if_xge.c val = (uint64_t)0xFFFFFFFFFFFFFFFFULL;
val 423 dev/pci/if_xge.c val &= ~(TxF_R_SE|RxF_W_SE);
val 424 dev/pci/if_xge.c PIF_WCSR(SWAPPER_CTRL, val);
val 425 dev/pci/if_xge.c PIF_WCSR(SWAPPER_CTRL, val);
val 428 dev/pci/if_xge.c if ((val = PIF_RCSR(PIF_RD_SWAPPER_Fb)) != SWAPPER_MAGIC) {
val 430 dev/pci/if_xge.c (unsigned long long)val, SWAPPER_MAGIC);
val 443 dev/pci/if_xge.c val = PIF_RCSR(SW_RESET);
val 444 dev/pci/if_xge.c val &= 0xffff00ffffffffffULL;
val 445 dev/pci/if_xge.c PIF_WCSR(SW_RESET,val);
val 450 dev/pci/if_xge.c val = PIF_RCSR(SW_RESET);
val 451 dev/pci/if_xge.c val &= 0xffffff00ffffffffULL;
val 452 dev/pci/if_xge.c PIF_WCSR(SW_RESET, val);
val 460 dev/pci/if_xge.c val = PIF_RCSR(ADAPTER_STATUS);
val 461 dev/pci/if_xge.c if (!(val & RIC_RUNNING))
val 484 dev/pci/if_xge.c val = PIF_RCSR(RMAC_ADDR_DATA0_MEM);
val 486 dev/pci/if_xge.c enaddr[i] = (uint8_t)(val >> (56 - (8*i)));
val 505 dev/pci/if_xge.c val = PIF_RCSR(TX_FIFO_P0);
val 506 dev/pci/if_xge.c val |= TX_FIFO_ENABLE;
val 507 dev/pci/if_xge.c PIF_WCSR(TX_FIFO_P0, val);
val 567 dev/pci/if_xge.c val = RING_MODE_1;
val 569 dev/pci/if_xge.c val = RING_MODE_3;
val 571 dev/pci/if_xge.c val = RING_MODE_5;
val 573 dev/pci/if_xge.c PIF_WCSR(PRC_CTRL_0, RC_IN_SVC|val);
val 597 dev/pci/if_xge.c val = PIF_RCSR(MC_RLDRAM_MRS);
val 598 dev/pci/if_xge.c val |= MC_QUEUE_SIZE_ENABLE|MC_RLDRAM_MRS_ENABLE;
val 599 dev/pci/if_xge.c PIF_WCSR(MC_RLDRAM_MRS, val);
val 700 dev/pci/if_xge.c uint64_t val;
val 703 dev/pci/if_xge.c val = PIF_RCSR(ADAPTER_CONTROL);
val 704 dev/pci/if_xge.c val |= ADAPTER_EN;
val 705 dev/pci/if_xge.c PIF_WCSR(ADAPTER_CONTROL, val);
val 708 dev/pci/if_xge.c val = PIF_RCSR(ADAPTER_CONTROL);
val 709 dev/pci/if_xge.c val |= LED_ON;
val 710 dev/pci/if_xge.c PIF_WCSR(ADAPTER_CONTROL, val);
val 720 dev/pci/if_xge.c uint64_t val;
val 737 dev/pci/if_xge.c val = PIF_RCSR(ADAPTER_STATUS);
val 738 dev/pci/if_xge.c if ((val & QUIESCENT) != QUIESCENT) {
val 743 dev/pci/if_xge.c val = (val & QUIESCENT) ^ QUIESCENT;
val 745 dev/pci/if_xge.c bitmask_snprintf(val, QUIESCENT_BMSK, buf, sizeof buf);
val 753 dev/pci/if_xge.c val = PIF_RCSR(RX_PA_CFG);
val 754 dev/pci/if_xge.c val &= ~STRIP_VLAN_TAG;
val 755 dev/pci/if_xge.c PIF_WCSR(RX_PA_CFG, val);
val 765 dev/pci/if_xge.c val = PIF_RCSR(ADAPTER_CONTROL);
val 766 dev/pci/if_xge.c val |= EOI_TX_ON;
val 767 dev/pci/if_xge.c PIF_WCSR(ADAPTER_CONTROL, val);
val 800 dev/pci/if_xge.c uint64_t val;
val 804 dev/pci/if_xge.c val = PIF_RCSR(ADAPTER_CONTROL);
val 805 dev/pci/if_xge.c val &= ~ADAPTER_EN;
val 806 dev/pci/if_xge.c PIF_WCSR(ADAPTER_CONTROL, val);
val 828 dev/pci/if_xge.c uint64_t val;
val 831 dev/pci/if_xge.c val = PIF_RCSR(GENERAL_INT_STATUS);
val 832 dev/pci/if_xge.c if (val == 0)
val 835 dev/pci/if_xge.c PIF_WCSR(GENERAL_INT_STATUS, val);
val 837 dev/pci/if_xge.c if ((val = PIF_RCSR(MAC_RMAC_ERR_REG)) & RMAC_LINK_STATE_CHANGE_INT) {
val 846 dev/pci/if_xge.c val = PIF_RCSR(ADAPTER_STATUS);
val 847 dev/pci/if_xge.c if ((val & (RMAC_REMOTE_FAULT|RMAC_LOCAL_FAULT)) == 0)
val 851 dev/pci/if_xge.c if ((val = PIF_RCSR(TX_TRAFFIC_INT)))
val 852 dev/pci/if_xge.c PIF_WCSR(TX_TRAFFIC_INT, val); /* clear interrupt bits */
val 883 dev/pci/if_xge.c if ((val = PIF_RCSR(RX_TRAFFIC_INT)))
val 884 dev/pci/if_xge.c PIF_WCSR(RX_TRAFFIC_INT, val);
val 918 dev/pci/if_xge.c val = rxd->rxd_control1;
val 936 dev/pci/if_xge.c if (RXD_CTL1_PROTOS(val) & RXD_CTL1_P_IPv4)
val 938 dev/pci/if_xge.c if (RXD_CTL1_PROTOS(val) & RXD_CTL1_P_TCP)
val 940 dev/pci/if_xge.c if (RXD_CTL1_PROTOS(val) & RXD_CTL1_P_UDP)
val 1037 dev/pci/if_xge.c uint64_t val;
val 1047 dev/pci/if_xge.c for (val = 0, i = 0; i < ETHER_ADDR_LEN; i++) {
val 1048 dev/pci/if_xge.c val <<= 8;
val 1049 dev/pci/if_xge.c val |= enm->enm_addrlo[i];
val 1051 dev/pci/if_xge.c PIF_WCSR(RMAC_ADDR_DATA0_MEM, val << 16);
val 1087 dev/pci/if_xge.c uint64_t val;
val 1089 dev/pci/if_xge.c val = PIF_RCSR(MAC_CFG);
val 1092 dev/pci/if_xge.c val |= RMAC_PROM_EN;
val 1094 dev/pci/if_xge.c val &= ~RMAC_PROM_EN;
val 1096 dev/pci/if_xge.c PIF_WCSR(MAC_CFG, val);
val 1446 dev/pci/if_xge.c val = PIF_RCSR(MDIO_CONTROL);
val 1447 dev/pci/if_xge.c if (val != 0x1804001c0F001cULL) {
val 1449 dev/pci/if_xge.c XNAME, val, 0x1804001c0F001cULL);
val 1463 dev/pci/if_xge.c val = PIF_RCSR(DTX_CONTROL);
val 1464 dev/pci/if_xge.c if (val != 0x5152040001cULL) {
val 1466 dev/pci/if_xge.c XNAME, val, 0x5152040001cULL);
val 1477 dev/pci/if_xge.c val = PIF_RCSR(MDIO_CONTROL);
val 1478 dev/pci/if_xge.c if (val != 0x1804001c0f001cULL) {
val 1480 dev/pci/if_xge.c XNAME, val, 0x1804001c0f001cULL);
val 89 dev/pci/ises.c #define WRITE_REG(sc,reg,val) \
val 90 dev/pci/ises.c bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, reg, val)
val 875 dev/pci/isp_pci.c isp_pci_wr_reg(struct ispsoftc *isp, int regoff, u_int16_t val)
val 888 dev/pci/isp_pci.c BXW2(pcs, IspVirt2Off(isp, regoff), val);
val 927 dev/pci/isp_pci.c isp_pci_wr_reg_1080(struct ispsoftc *isp, int regoff, u_int16_t val)
val 950 dev/pci/isp_pci.c BXW2(pcs, IspVirt2Off(isp, regoff), val);
val 701 dev/pci/noct.c u_int64_t val;
val 710 dev/pci/noct.c val = sc->sc_rngbuf[rd];
val 711 dev/pci/noct.c add_true_randomness((val >> 32) & 0xffffffff);
val 712 dev/pci/noct.c add_true_randomness((val >> 0) & 0xffffffff);
val 1329 dev/pci/noct.c noct_write_8(sc, reg, val)
val 1332 dev/pci/noct.c u_int64_t val;
val 1334 dev/pci/noct.c NOCT_WRITE_4(sc, reg, (val >> 32) & 0xffffffff);
val 1335 dev/pci/noct.c NOCT_WRITE_4(sc, reg + 4, (val >> 0) & 0xffffffff);
val 1371 dev/pci/noct.c noct_write_4(sc, off, val)
val 1374 dev/pci/noct.c u_int32_t val;
val 1382 dev/pci/noct.c bus_space_write_4(sc->sc_st, sc->sc_sh, off, val);
val 101 dev/pci/pccbb.c #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val)))
val 1020 dev/pci/pccbb.c int retval = 0, val;
val 1059 dev/pci/pccbb.c val = (*pil->pil_func)(pil->pil_arg);
val 1060 dev/pci/pccbb.c if (val != 0)
val 1068 dev/pci/pccbb.c retval == 0 ? val : val != 0 ? val : retval;
val 1123 dev/pci/pccbb.c pccbb_pcmcia_write(ph, reg, val)
val 1126 dev/pci/pccbb.c u_int8_t val;
val 1132 dev/pci/pccbb.c val);
val 1788 dev/pci/pccbb.c pccbb_conf_write(cc, tag, reg, val)
val 1792 dev/pci/pccbb.c cardbusreg_t val;
val 1796 dev/pci/pccbb.c pci_conf_write(sc->sc_pc, tag, reg, val);
val 57 dev/pci/pci_subr.c int val; /* as wide as pci_{,sub}class_t */
val 353 dev/pci/pci_subr.c if (class == classp->val)
val 360 dev/pci/pci_subr.c if (subclass == subclassp->val)
val 155 dev/pci/pciide.c pciide_pci_write(pci_chipset_tag_t pc, pcitag_t pa, int reg, u_int8_t val)
val 161 dev/pci/pciide.c pcival |= (val << ((reg & 0x03) * 8));
val 1547 dev/pci/pciide.c pciide_dmacmd_write(struct pciide_softc *sc, int chan, u_int8_t val)
val 1550 dev/pci/pciide.c IDEDMA_CMD(chan), val);
val 1561 dev/pci/pciide.c pciide_dmactl_write(struct pciide_softc *sc, int chan, u_int8_t val)
val 1564 dev/pci/pciide.c IDEDMA_CTL(chan), val);
val 1568 dev/pci/pciide.c pciide_dmatbl_write(struct pciide_softc *sc, int chan, u_int32_t val)
val 1571 dev/pci/pciide.c IDEDMA_TBL(chan), val);
val 3679 dev/pci/pciide.c u_int16_t val;
val 3720 dev/pci/pciide.c val = pciide_pci_read(pc, pa, off) & ~0x3f;
val 3722 dev/pci/pciide.c val |= udma2_tbl[drvp->UDMA_mode];
val 3724 dev/pci/pciide.c val |= udma_tbl[drvp->UDMA_mode];
val 3725 dev/pci/pciide.c pciide_pci_write(pc, pa, off, val);
val 3730 dev/pci/pciide.c val = dma_tbl[drvp->DMA_mode];
val 3731 dev/pci/pciide.c pciide_pci_write(pc, pa, off, val & 0xff);
val 3732 dev/pci/pciide.c pciide_pci_write(pc, pa, off, val >> 8);
val 3737 dev/pci/pciide.c val = pio_tbl[drvp->PIO_mode];
val 3738 dev/pci/pciide.c pciide_pci_write(pc, pa, off, val & 0xff);
val 3739 dev/pci/pciide.c pciide_pci_write(pc, pa, off, val >> 8);
val 4341 dev/pci/pciide.c sii3114_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int8_t val)
val 4349 dev/pci/pciide.c sl->regs[chp->channel].ctl_ioh, reg & _WDC_REGMASK, val);
val 4353 dev/pci/pciide.c 0, val);
val 4366 dev/pci/pciide.c sii3114_dmacmd_write(struct pciide_softc *sc, int chan, u_int8_t val)
val 4371 dev/pci/pciide.c sl->regs[chan].dma_iohs[IDEDMA_CMD(0)], 0, val);
val 4384 dev/pci/pciide.c sii3114_dmactl_write(struct pciide_softc *sc, int chan, u_int8_t val)
val 4389 dev/pci/pciide.c sl->regs[chan].dma_iohs[IDEDMA_CTL(0)], 0, val);
val 4393 dev/pci/pciide.c sii3114_dmatbl_write(struct pciide_softc *sc, int chan, u_int32_t val)
val 4398 dev/pci/pciide.c sl->regs[chan].dma_iohs[IDEDMA_TBL(0)], 0, val);
val 6718 dev/pci/pciide.c u_int8_t val;
val 6724 dev/pci/pciide.c val = bus_space_read_1(ps->regs[chp->channel].cmd_iot,
val 6726 dev/pci/pciide.c return (val);
val 6731 dev/pci/pciide.c pdc203xx_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int8_t val)
val 6739 dev/pci/pciide.c ps->regs[chp->channel].ctl_ioh, reg & _WDC_REGMASK, val);
val 6743 dev/pci/pciide.c 0, val);
val 6892 dev/pci/pciide.c opti_write_config(struct channel_softc *chp, int reg, u_int8_t val)
val 6904 dev/pci/pciide.c bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, reg, val);
val 7372 dev/pci/pciide.c svwsata_dmacmd_write(struct pciide_softc *sc, int chan, u_int8_t val)
val 7375 dev/pci/pciide.c (chan << 8) + SVWSATA_DMA + IDEDMA_CMD(0), val);
val 7386 dev/pci/pciide.c svwsata_dmactl_write(struct pciide_softc *sc, int chan, u_int8_t val)
val 7389 dev/pci/pciide.c (chan << 8) + SVWSATA_DMA + IDEDMA_CTL(0), val);
val 7393 dev/pci/pciide.c svwsata_dmatbl_write(struct pciide_softc *sc, int chan, u_int32_t val)
val 7396 dev/pci/pciide.c (chan << 8) + SVWSATA_DMA + IDEDMA_TBL(0), val);
val 7566 dev/pci/pciide.c svwsata_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int8_t val)
val 7570 dev/pci/pciide.c (reg & _WDC_REGMASK) << 2, val);
val 7573 dev/pci/pciide.c (reg & _WDC_REGMASK) << 2, val);
val 7578 dev/pci/pciide.c svwsata_lba48_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int16_t val)
val 7582 dev/pci/pciide.c (reg & _WDC_REGMASK) << 2, val);
val 7585 dev/pci/pciide.c (reg & _WDC_REGMASK) << 2, val);
val 76 dev/pci/pciide_acer_reg.h #define ACER_FTH_VAL(chan, drv, val) \
val 77 dev/pci/pciide_acer_reg.h (((val) & 0x3) << ((drv) * 4 + (chan) * 8))
val 78 dev/pci/pciide_acer_reg.h #define ACER_FTH_OPL(chan, drv, val) \
val 79 dev/pci/pciide_acer_reg.h (((val) & 0x3) << (2 + (drv) * 4 + (chan) * 8))
val 82 dev/pci/pciide_acer_reg.h #define ACER_UDMA_TIM(chan, drv, val) \
val 83 dev/pci/pciide_acer_reg.h (((val) & 0x7) << (16 + (drv) * 4 + (chan) * 8))
val 369 dev/pci/pciide_sii3112_reg.h ba5_write_4_ind(struct pciide_softc *sc, pcireg_t reg, uint32_t val)
val 375 dev/pci/pciide_sii3112_reg.h pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA, val);
val 380 dev/pci/pciide_sii3112_reg.h ba5_write_4(struct pciide_softc *sc, bus_size_t reg, uint32_t val)
val 385 dev/pci/pciide_sii3112_reg.h bus_space_write_4(sl->ba5_st, sl->ba5_sh, reg, val);
val 387 dev/pci/pciide_sii3112_reg.h ba5_write_4_ind(sc, reg, val);
val 390 dev/pci/pciide_sii3112_reg.h #define BA5_WRITE_4(sc, chan, reg, val) \
val 391 dev/pci/pciide_sii3112_reg.h ba5_write_4((sc), satalink_ba5_regmap[(chan)].reg, (val))
val 116 dev/pci/pciidevar.h #define PCIIDE_DMACMD_WRITE(sc, chan, val) \
val 117 dev/pci/pciidevar.h (sc)->sc_dmacmd_write((sc), (chan), (val))
val 120 dev/pci/pciidevar.h #define PCIIDE_DMACTL_WRITE(sc, chan, val) \
val 121 dev/pci/pciidevar.h (sc)->sc_dmactl_write((sc), (chan), (val))
val 122 dev/pci/pciidevar.h #define PCIIDE_DMATBL_WRITE(sc, chan, val) \
val 123 dev/pci/pciidevar.h (sc)->sc_dmatbl_write((sc), (chan), (val))
val 100 dev/pci/pcscp.c #define PCSCP_WRITE_REG(sc, reg, val) \
val 101 dev/pci/pcscp.c bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg) << 2, (val))
val 321 dev/pci/puc.c #define checkreg(val, index) \
val 322 dev/pci/puc.c (((val) & puc_devices[i].rmask[(index)]) == puc_devices[i].rval[(index)])
val 133 dev/pci/safe.c #define WRITE_REG(sc,reg,val) \
val 134 dev/pci/safe.c bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val)
val 199 dev/pci/sv.c sv_write (sc, reg, val)
val 201 dev/pci/sv.c u_int8_t reg, val;
val 204 dev/pci/sv.c bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val);
val 233 dev/pci/sv.c sv_write_indirect (sc, reg, val)
val 235 dev/pci/sv.c u_int8_t reg, val;
val 253 dev/pci/sv.c sv_write (sc, SV_CODEC_IDATA, val);
val 670 dev/pci/sv.c u_int32_t mode, val;
val 728 dev/pci/sv.c val = p->sample_rate * 65536 / 48000;
val 730 dev/pci/sv.c sv_write_indirect(sc, SV_PCM_SAMPLE_RATE_0, (val & 0xff));
val 731 dev/pci/sv.c sv_write_indirect(sc, SV_PCM_SAMPLE_RATE_1, (val >> 8));
val 1245 dev/pci/sv.c int val;
val 1253 dev/pci/sv.c val = (cp->un.value.level[AUDIO_MIXER_LEVEL_MONO] * SV_REC_GAIN_MASK)
val 1258 dev/pci/sv.c reg |= val;
val 1263 dev/pci/sv.c reg |= val;
val 1308 dev/pci/sv.c int val;
val 1340 dev/pci/sv.c val = AUDIO_MAX_GAIN - ((reg * AUDIO_MAX_GAIN) / ports[idx].mask);
val 1343 dev/pci/sv.c cp->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = val;
val 1348 dev/pci/sv.c val = AUDIO_MAX_GAIN - ((reg * AUDIO_MAX_GAIN) / ports[idx].mask);
val 1349 dev/pci/sv.c cp->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = val;
val 1351 dev/pci/sv.c cp->un.value.level[AUDIO_MIXER_LEVEL_MONO] = val;
val 1432 dev/pci/tga.c tga_ramdac_wr(v, btreg, val)
val 1435 dev/pci/tga.c u_int8_t val;
val 1442 dev/pci/tga.c TGAWREG(dc, TGA_REG_EPDR, (btreg << 9) | (0 << 8 ) | val); /* XXX */
val 1447 dev/pci/tga.c tga2_ramdac_wr(v, btreg, val)
val 1450 dev/pci/tga.c u_int8_t val;
val 1460 dev/pci/tga.c bus_space_write_4(dc->dc_memt, ramdac, 0, val & 0xff);
val 1492 dev/pci/tga.c tga_bt463_wr(v, btreg, val)
val 1495 dev/pci/tga.c u_int8_t val;
val 1510 dev/pci/tga.c TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val);
val 1512 dev/pci/tga.c TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x000 | val);
val 1514 dev/pci/tga.c TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val);
val 144 dev/pci/tgavar.h #define TGAWREG(dc,reg,val) bus_space_write_4((dc)->dc_memt, (dc)->dc_regs, \
val 145 dev/pci/tgavar.h (reg) << 2, (val))
val 148 dev/pci/tgavar.h #define TGAWALREG(dc,reg,alias,val) bus_space_write_4( \
val 151 dev/pci/tgavar.h (val))
val 117 dev/pci/ubsec.c #define WRITE_REG(sc,reg,val) \
val 118 dev/pci/ubsec.c bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val)
val 166 dev/pci/viaenv.c val_to_uK(unsigned int val)
val 168 dev/pci/viaenv.c int i = val / 4;
val 169 dev/pci/viaenv.c int j = val % 4;
val 182 dev/pci/viaenv.c val_to_rpm(unsigned int val, int div)
val 185 dev/pci/viaenv.c if (val == 0)
val 188 dev/pci/viaenv.c return 1350000 / val / div;
val 192 dev/pci/viaenv.c val_to_uV(unsigned int val, int index)
val 199 dev/pci/viaenv.c return (25LL * val + 133) * mult[index] / 2628;
val 686 dev/pckbc/pckbd.c int val;
val 689 dev/pckbc/pckbd.c val = pckbc_poll_data(t->t_kbctag, t->t_kbcslot);
val 690 dev/pckbc/pckbd.c if ((val != -1) && pckbd_decode(t, val, type, data))
val 173 dev/pcmcia/cfxga.c #define cfxga_write_1(sc, addr, val) \
val 175 dev/pcmcia/cfxga.c (sc)->sc_offset + (addr), (val))
val 176 dev/pcmcia/cfxga.c #define cfxga_write_2(sc, addr, val) \
val 178 dev/pcmcia/cfxga.c (sc)->sc_offset + (addr), (val))
val 381 dev/pcmcia/esp_pcmcia.c esp_pcmcia_write_reg(sc, reg, val)
val 384 dev/pcmcia/esp_pcmcia.c u_char val;
val 387 dev/pcmcia/esp_pcmcia.c u_char v = val;
val 356 dev/pcmcia/gpr.c u_int8_t val;
val 361 dev/pcmcia/gpr.c val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, GPR400_HAP_CTRL);
val 363 dev/pcmcia/gpr.c val & ~GPR400_INTR);
val 27 dev/pcmcia/if_malovar.h #define MALO_WRITE_1(sc, reg, val) \
val 28 dev/pcmcia/if_malovar.h bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
val 29 dev/pcmcia/if_malovar.h #define MALO_WRITE_2(sc, reg, val) \
val 30 dev/pcmcia/if_malovar.h bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
val 406 dev/pcmcia/if_ray.c #define REG_WRITE(sc, off, val) \
val 408 dev/pcmcia/if_ray.c ((sc)->sc_ccroff + (off)), (val))
val 427 dev/pcmcia/if_ray.c #define SRAM_WRITE_1(sc, off, val) \
val 428 dev/pcmcia/if_ray.c bus_space_write_1((sc)->sc_memt, (sc)->sc_memh, (off), (val))
val 88 dev/pcmcia/pcmcia.c pcmcia_ccr_write(pf, ccr, val)
val 91 dev/pcmcia/pcmcia.c int val;
val 96 dev/pcmcia/pcmcia.c pf->pf_ccr_offset + ccr, val);
val 881 dev/raidframe/rf_driver.c rf_set_debug_option(char *name, long val)
val 887 dev/raidframe/rf_driver.c *(p->ptr) = val;
val 888 dev/raidframe/rf_driver.c printf("[Set debug variable %s to %ld]\n", name, val);
val 902 dev/raidframe/rf_driver.c long val;
val 914 dev/raidframe/rf_driver.c val = rf_htoi(val_p + 2);
val 916 dev/raidframe/rf_driver.c val = rf_atoi(val_p);
val 918 dev/raidframe/rf_driver.c rf_set_debug_option(name_p, val);
val 46 dev/raidframe/rf_geniq.c lsfr_shift(unsigned val, unsigned poly)
val 50 dev/raidframe/rf_geniq.c unsigned high = (val >> 4) & 1;
val 56 dev/raidframe/rf_geniq.c bit = (val >> (i - 1)) & 1;
val 74 dev/raidframe/rf_geniq.c unsigned int val;
val 113 dev/raidframe/rf_geniq.c val = j;
val 115 dev/raidframe/rf_geniq.c val = lsfr_shift(val, 5);
val 116 dev/raidframe/rf_geniq.c rf_qfor[i][j] = val;
val 117 dev/raidframe/rf_geniq.c printf("%d, ", val);
val 50 dev/raidframe/rf_hist.h RF_Hist_t val; \
val 51 dev/raidframe/rf_hist.h val = ((RF_Hist_t)(_val_)) / 1000; \
val 52 dev/raidframe/rf_hist.h if (val >= RF_HIST_MAX_VAL) \
val 55 dev/raidframe/rf_hist.h _hist_[(val - RF_HIST_MIN_VAL) / RF_HIST_RESOLUTION]++; \
val 387 dev/raidframe/rf_states.c int val;
val 395 dev/raidframe/rf_states.c val = rf_ForceOrBlockRecon(raidPtr,
val 399 dev/raidframe/rf_states.c if (val == 0) {
val 125 dev/raidframe/rf_utils.c int val = 0, negate = 0;
val 132 dev/raidframe/rf_utils.c val = 10 * val + (*p - '0');
val 133 dev/raidframe/rf_utils.c return ((negate) ? -val : val);
val 139 dev/raidframe/rf_utils.c int val = 0;
val 141 dev/raidframe/rf_utils.c val = 16 * val + HC2INT(*p);
val 142 dev/raidframe/rf_utils.c return (val);
val 708 dev/rnd.c enqueue_randomness(int state, int val)
val 726 dev/rnd.c val += state << 13;
val 789 dev/rnd.c nbits = 8 * sizeof(val) - 1;
val 801 dev/rnd.c rep->re_val = val;
val 1301 dev/sbus/be.c int val = 0, i;
val 1316 dev/sbus/be.c val |= (be_tcvr_read_bit(sc, phy) << i);
val 1322 dev/sbus/be.c return (val);
val 1326 dev/sbus/be.c be_mii_writereg(struct device *self, int phy, int reg, int val)
val 1344 dev/sbus/be.c be_tcvr_write_bit(sc, phy, (val >> i) & 1);
val 94 dev/sbus/bwtwo.c #define FBC_WRITE(sc, reg, val) \
val 95 dev/sbus/bwtwo.c bus_space_write_1((sc)->sc_bustag, (sc)->sc_ctrl_regs, (reg), (val))
val 314 dev/sbus/cgsixreg.h #define BT_WRITE(sc, reg, val) \
val 315 dev/sbus/cgsixreg.h bus_space_write_4((sc)->sc_bustag, (sc)->sc_bt_regs, (reg), (val))
val 75 dev/sbus/cgthree.c #define BT_WRITE(sc, reg, val) \
val 76 dev/sbus/cgthree.c bus_space_write_4((sc)->sc_bustag, (sc)->sc_ctrl_regs, (reg), (val))
val 116 dev/sbus/cgthree.c #define FBC_WRITE(sc, reg, val) \
val 117 dev/sbus/cgthree.c bus_space_write_1((sc)->sc_bustag, (sc)->sc_ctrl_regs, (reg), (val))
val 99 dev/sbus/if_le.c le_sbus_wrcsr(struct am7990_softc *sc, u_int16_t port, u_int16_t val)
val 106 dev/sbus/if_le.c bus_space_write_2(lesc->sc_bustag, lesc->sc_reg, LEREG1_RDP, val);
val 101 dev/sbus/if_le_lebuffer.c le_lebuffer_wrcsr(struct am7990_softc *sc, u_int16_t port, u_int16_t val)
val 108 dev/sbus/if_le_lebuffer.c bus_space_write_2(lesc->sc_bustag, lesc->sc_reg, LEREG1_RDP, val);
val 113 dev/sbus/if_le_ledma.c le_ledma_wrcsr(struct am7990_softc *sc, u_int16_t port, u_int16_t val)
val 120 dev/sbus/if_le_ledma.c bus_space_write_2(lesc->sc_bustag, lesc->sc_reg, LEREG1_RDP, val);
val 362 dev/sbus/isp_sbus.c isp_sbus_wr_reg(struct ispsoftc *isp, int regoff, u_int16_t val)
val 367 dev/sbus/isp_sbus.c bus_space_write_2(sbc->sbus_bustag, sbc->sbus_reg, offset, val);
val 1003 dev/sbus/spif.c stty_write_ccr(sc, val)
val 1005 dev/sbus/spif.c u_int8_t val;
val 1013 dev/sbus/spif.c STC_WRITE(sc, STC_CCR, val);
val 36 dev/sdmmc/sbt.c #define CSR_WRITE_1(sc, reg, val) sdmmc_io_write_1((sc)->sc_sf, (reg), (val))
val 66 dev/sdmmc/sdhc.c #define HWRITE1(hp, reg, val) \
val 67 dev/sdmmc/sdhc.c bus_space_write_1((hp)->iot, (hp)->ioh, (reg), (val))
val 68 dev/sdmmc/sdhc.c #define HWRITE2(hp, reg, val) \
val 69 dev/sdmmc/sdhc.c bus_space_write_2((hp)->iot, (hp)->ioh, (reg), (val))
val 70 dev/sdmmc/sdhc.c #define HWRITE4(hp, reg, val) \
val 71 dev/sdmmc/sdhc.c bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val))
val 112 dev/tc/asc.c asc_write_reg(sc, reg, val)
val 115 dev/tc/asc.c u_char val;
val 120 dev/tc/asc.c reg * sizeof(u_int32_t), val);
val 381 dev/tc/tcds.c tcds_intrnull(val)
val 382 dev/tc/tcds.c void *val;
val 386 dev/tc/tcds.c (u_long)val);
val 279 dev/usb/if_aue.c uByte val = 0;
val 290 dev/usb/if_aue.c err = usbd_do_request(sc->aue_udev, &req, &val);
val 298 dev/usb/if_aue.c return (val);
val 306 dev/usb/if_aue.c uWord val;
val 317 dev/usb/if_aue.c err = usbd_do_request(sc->aue_udev, &req, &val);
val 325 dev/usb/if_aue.c return (UGETW(val));
val 333 dev/usb/if_aue.c uByte val;
val 338 dev/usb/if_aue.c val = aval;
val 341 dev/usb/if_aue.c USETW(req.wValue, val);
val 345 dev/usb/if_aue.c err = usbd_do_request(sc->aue_udev, &req, &val);
val 361 dev/usb/if_aue.c uWord val;
val 366 dev/usb/if_aue.c USETW(val, aval);
val 373 dev/usb/if_aue.c err = usbd_do_request(sc->aue_udev, &req, &val);
val 448 dev/usb/if_aue.c u_int16_t val;
val 488 dev/usb/if_aue.c val = aue_csr_read_2(sc, AUE_PHY_DATA);
val 491 dev/usb/if_aue.c sc->aue_dev.dv_xname, __func__, phy, reg, val));
val 494 dev/usb/if_aue.c return (val);
val 238 dev/usb/if_axe.c axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf)
val 251 dev/usb/if_axe.c USETW(req.wValue, val);
val 268 dev/usb/if_axe.c uWord val;
val 292 dev/usb/if_axe.c USETW(val, 0);
val 296 dev/usb/if_axe.c err = axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, val);
val 305 dev/usb/if_axe.c if (UGETW(val))
val 308 dev/usb/if_axe.c return (UGETW(val));
val 312 dev/usb/if_axe.c axe_miibus_writereg(struct device *dev, int phy, int reg, int val)
val 321 dev/usb/if_axe.c USETW(uval, val);
val 340 dev/usb/if_axe.c int val, err;
val 343 dev/usb/if_axe.c val = AXE_MEDIA_FULL_DUPLEX;
val 345 dev/usb/if_axe.c val = 0;
val 348 dev/usb/if_axe.c val |= (AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC);
val 352 dev/usb/if_axe.c val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK;
val 355 dev/usb/if_axe.c val |= AXE_178_MEDIA_100TX;
val 363 dev/usb/if_axe.c DPRINTF(("axe_miibus_statchg: val=0x%x\n", val));
val 364 dev/usb/if_axe.c err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL);
val 168 dev/usb/if_cue.c u_int8_t val = 0;
val 179 dev/usb/if_cue.c err = usbd_do_request(sc->cue_udev, &req, &val);
val 188 dev/usb/if_cue.c sc->cue_dev.dv_xname, reg, val));
val 190 dev/usb/if_cue.c return (val);
val 198 dev/usb/if_cue.c uWord val;
val 209 dev/usb/if_cue.c err = usbd_do_request(sc->cue_udev, &req, &val);
val 212 dev/usb/if_cue.c sc->cue_dev.dv_xname, reg, UGETW(val)));
val 220 dev/usb/if_cue.c return (UGETW(val));
val 224 dev/usb/if_cue.c cue_csr_write_1(struct cue_softc *sc, int reg, int val)
val 233 dev/usb/if_cue.c sc->cue_dev.dv_xname, reg, val));
val 237 dev/usb/if_cue.c USETW(req.wValue, val);
val 261 dev/usb/if_cue.c uWord val;
val 270 dev/usb/if_cue.c USETW(val, aval);
val 273 dev/usb/if_cue.c USETW(req.wValue, val);
val 213 dev/usb/if_kue.c kue_ctl(struct kue_softc *sc, int rw, u_int8_t breq, u_int16_t val,
val 227 dev/usb/if_kue.c USETW(req.wValue, val);
val 171 dev/usb/if_ral.c uint16_t val;
val 178 dev/usb/if_ral.c uint8_t val;
val 1413 dev/usb/if_ral.c uint16_t val;
val 1421 dev/usb/if_ral.c error = usbd_do_request(sc->sc_udev, &req, &val);
val 1427 dev/usb/if_ral.c return letoh16(val);
val 1450 dev/usb/if_ral.c ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val)
val 1457 dev/usb/if_ral.c USETW(req.wValue, val);
val 1488 dev/usb/if_ral.c ural_bbp_write(struct ural_softc *sc, uint8_t reg, uint8_t val)
val 1502 dev/usb/if_ral.c tmp = reg << 8 | val;
val 1509 dev/usb/if_ral.c uint16_t val;
val 1512 dev/usb/if_ral.c val = RAL_BBP_WRITE | reg << 8;
val 1513 dev/usb/if_ral.c ural_write(sc, RAL_PHY_CSR7, val);
val 1527 dev/usb/if_ral.c ural_rf_write(struct ural_softc *sc, uint8_t reg, uint32_t val)
val 1541 dev/usb/if_ral.c tmp = RAL_RF_BUSY | RAL_RF_20BIT | (val & 0xfffff) << 2 | (reg & 0x3);
val 1546 dev/usb/if_ral.c sc->rf_regs[reg] = val;
val 1548 dev/usb/if_ral.c DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff));
val 1813 dev/usb/if_ral.c uint16_t val;
val 1816 dev/usb/if_ral.c ural_eeprom_read(sc, RAL_EEPROM_MACBBP, &val, 2);
val 1817 dev/usb/if_ral.c sc->macbbp_rev = letoh16(val);
val 1819 dev/usb/if_ral.c ural_eeprom_read(sc, RAL_EEPROM_CONFIG0, &val, 2);
val 1820 dev/usb/if_ral.c val = letoh16(val);
val 1821 dev/usb/if_ral.c sc->rf_rev = (val >> 11) & 0x7;
val 1822 dev/usb/if_ral.c sc->hw_radio = (val >> 10) & 0x1;
val 1823 dev/usb/if_ral.c sc->led_mode = (val >> 6) & 0x7;
val 1824 dev/usb/if_ral.c sc->rx_ant = (val >> 4) & 0x3;
val 1825 dev/usb/if_ral.c sc->tx_ant = (val >> 2) & 0x3;
val 1826 dev/usb/if_ral.c sc->nb_ant = val & 0x3;
val 1857 dev/usb/if_ral.c ural_bbp_write(sc, ural_def_bbp[i].reg, ural_def_bbp[i].val);
val 1864 dev/usb/if_ral.c ural_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);
val 1935 dev/usb/if_ral.c ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val);
val 114 dev/usb/if_ralvar.h uint8_t val;
val 189 dev/usb/if_rum.c uint32_t val;
val 196 dev/usb/if_rum.c uint8_t val;
val 1419 dev/usb/if_rum.c uint32_t val;
val 1421 dev/usb/if_rum.c rum_read_multi(sc, reg, &val, sizeof val);
val 1423 dev/usb/if_rum.c return letoh32(val);
val 1446 dev/usb/if_rum.c rum_write(struct rum_softc *sc, uint16_t reg, uint32_t val)
val 1448 dev/usb/if_rum.c uint32_t tmp = htole32(val);
val 1473 dev/usb/if_rum.c rum_bbp_write(struct rum_softc *sc, uint8_t reg, uint8_t val)
val 1487 dev/usb/if_rum.c tmp = RT2573_BBP_BUSY | (reg & 0x7f) << 8 | val;
val 1494 dev/usb/if_rum.c uint32_t val;
val 1506 dev/usb/if_rum.c val = RT2573_BBP_BUSY | RT2573_BBP_READ | reg << 8;
val 1507 dev/usb/if_rum.c rum_write(sc, RT2573_PHY_CSR3, val);
val 1510 dev/usb/if_rum.c val = rum_read(sc, RT2573_PHY_CSR3);
val 1511 dev/usb/if_rum.c if (!(val & RT2573_BBP_BUSY))
val 1512 dev/usb/if_rum.c return val & 0xff;
val 1521 dev/usb/if_rum.c rum_rf_write(struct rum_softc *sc, uint8_t reg, uint32_t val)
val 1535 dev/usb/if_rum.c tmp = RT2573_RF_BUSY | RT2573_RF_20BIT | (val & 0xfffff) << 2 |
val 1540 dev/usb/if_rum.c sc->rf_regs[reg] = val;
val 1542 dev/usb/if_rum.c DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 3, val & 0xfffff));
val 1843 dev/usb/if_rum.c uint16_t val;
val 1849 dev/usb/if_rum.c rum_eeprom_read(sc, RT2573_EEPROM_MACBBP, &val, 2);
val 1850 dev/usb/if_rum.c sc->macbbp_rev = letoh16(val);
val 1855 dev/usb/if_rum.c rum_eeprom_read(sc, RT2573_EEPROM_ANTENNA, &val, 2);
val 1856 dev/usb/if_rum.c val = letoh16(val);
val 1857 dev/usb/if_rum.c sc->rf_rev = (val >> 11) & 0x1f;
val 1858 dev/usb/if_rum.c sc->hw_radio = (val >> 10) & 0x1;
val 1859 dev/usb/if_rum.c sc->rx_ant = (val >> 4) & 0x3;
val 1860 dev/usb/if_rum.c sc->tx_ant = (val >> 2) & 0x3;
val 1861 dev/usb/if_rum.c sc->nb_ant = val & 0x3;
val 1865 dev/usb/if_rum.c rum_eeprom_read(sc, RT2573_EEPROM_CONFIG2, &val, 2);
val 1866 dev/usb/if_rum.c val = letoh16(val);
val 1867 dev/usb/if_rum.c sc->ext_5ghz_lna = (val >> 6) & 0x1;
val 1868 dev/usb/if_rum.c sc->ext_2ghz_lna = (val >> 4) & 0x1;
val 1873 dev/usb/if_rum.c rum_eeprom_read(sc, RT2573_EEPROM_RSSI_2GHZ_OFFSET, &val, 2);
val 1874 dev/usb/if_rum.c val = letoh16(val);
val 1875 dev/usb/if_rum.c if ((val & 0xff) != 0xff)
val 1876 dev/usb/if_rum.c sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */
val 1878 dev/usb/if_rum.c rum_eeprom_read(sc, RT2573_EEPROM_RSSI_5GHZ_OFFSET, &val, 2);
val 1879 dev/usb/if_rum.c val = letoh16(val);
val 1880 dev/usb/if_rum.c if ((val & 0xff) != 0xff)
val 1881 dev/usb/if_rum.c sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */
val 1886 dev/usb/if_rum.c rum_eeprom_read(sc, RT2573_EEPROM_FREQ_OFFSET, &val, 2);
val 1887 dev/usb/if_rum.c val = letoh16(val);
val 1888 dev/usb/if_rum.c if ((val & 0xff) != 0xff)
val 1889 dev/usb/if_rum.c sc->rffreq = val & 0xff;
val 1909 dev/usb/if_rum.c sc->bbp_prom[i].val));
val 1922 dev/usb/if_rum.c const uint8_t val = rum_bbp_read(sc, 0);
val 1923 dev/usb/if_rum.c if (val != 0 && val != 0xff)
val 1935 dev/usb/if_rum.c rum_bbp_write(sc, rum_def_bbp[i].reg, rum_def_bbp[i].val);
val 1941 dev/usb/if_rum.c rum_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);
val 1962 dev/usb/if_rum.c rum_write(sc, rum_def_mac[i].reg, rum_def_mac[i].val);
val 116 dev/usb/if_rumvar.h uint8_t val;
val 869 dev/usb/if_uath.c uint32_t val;
val 888 dev/usb/if_uath.c val = htobe32(1);
val 889 dev/usb/if_uath.c (void)uath_cmd_write(sc, UATH_CMD_2E, &val, sizeof val, 0);
val 911 dev/usb/if_uath.c val = htobe32(1);
val 912 dev/usb/if_uath.c (void)uath_cmd_write(sc, UATH_CMD_SET_STATE, &val, sizeof val,
val 1041 dev/usb/if_uath.c uath_write_reg(struct uath_softc *sc, uint32_t reg, uint32_t val)
val 1048 dev/usb/if_uath.c *(uint32_t *)write.data = htobe32(val);
val 1081 dev/usb/if_uath.c uath_read_reg(struct uath_softc *sc, uint32_t reg, uint32_t *val)
val 1094 dev/usb/if_uath.c *val = betoh32(*(uint32_t *)read.data);
val 1653 dev/usb/if_uath.c uint32_t reg, val;
val 1676 dev/usb/if_uath.c if ((error = uath_read_reg(sc, reg, &val)) != 0)
val 1678 dev/usb/if_uath.c DPRINTFN(2, ("reg 0x%02x=0x%08x\n", reg, val));
val 1840 dev/usb/if_uath.c uint32_t val;
val 1863 dev/usb/if_uath.c val = htobe32(0);
val 1864 dev/usb/if_uath.c error = uath_cmd_write(sc, UATH_CMD_SET_STATE, &val, sizeof val, 0);
val 1879 dev/usb/if_uath.c uint32_t val;
val 1885 dev/usb/if_uath.c val = htobe32(0);
val 1886 dev/usb/if_uath.c (void)uath_cmd_write(sc, UATH_CMD_02, &val, sizeof val, 0);
val 1915 dev/usb/if_uath.c error = uath_cmd_read(sc, UATH_CMD_07, 0, NULL, &val,
val 1922 dev/usb/if_uath.c DPRINTF(("command 07h return code: %x\n", betoh32(val)));
val 1949 dev/usb/if_uath.c val = htobe32(4);
val 1950 dev/usb/if_uath.c (void)uath_cmd_write(sc, UATH_CMD_27, &val, sizeof val, 0);
val 1951 dev/usb/if_uath.c (void)uath_cmd_write(sc, UATH_CMD_27, &val, sizeof val, 0);
val 1987 dev/usb/if_uath.c uint32_t val;
val 1998 dev/usb/if_uath.c val = htobe32(0);
val 1999 dev/usb/if_uath.c (void)uath_cmd_write(sc, UATH_CMD_SET_STATE, &val, sizeof val, 0);
val 2002 dev/usb/if_uath.c val = htobe32(0);
val 2003 dev/usb/if_uath.c (void)uath_cmd_write(sc, UATH_CMD_15, &val, sizeof val, 0);
val 565 dev/usb/if_udav.c u_int8_t val = 0;
val 576 dev/usb/if_udav.c return (udav_csr_read(sc, offset, &val, 1) ? 0 : val);
val 1536 dev/usb/if_udav.c u_int8_t val[2];
val 1577 dev/usb/if_udav.c udav_csr_read(sc, UDAV_EPDRL, val, 2);
val 1581 dev/usb/if_udav.c data16 = val[0] | (val[1] << 8);
val 1593 dev/usb/if_udav.c u_int8_t val[2];
val 1625 dev/usb/if_udav.c val[0] = data & 0xff;
val 1626 dev/usb/if_udav.c val[1] = (data >> 8) & 0xff;
val 1627 dev/usb/if_udav.c udav_csr_write(sc, UDAV_EPDRL, val, 2);
val 430 dev/usb/if_url.c u_int8_t val = 0;
val 438 dev/usb/if_url.c return (url_mem(sc, URL_CMD_READMEM, reg, &val, 1) ? 0 : val);
val 445 dev/usb/if_url.c uWord val;
val 453 dev/usb/if_url.c USETW(val, 0);
val 454 dev/usb/if_url.c return (url_mem(sc, URL_CMD_READMEM, reg, &val, 2) ? 0 : UGETW(val));
val 461 dev/usb/if_url.c u_int8_t val = aval;
val 469 dev/usb/if_url.c return (url_mem(sc, URL_CMD_WRITEMEM, reg, &val, 1) ? -1 : 0);
val 476 dev/usb/if_url.c uWord val;
val 481 dev/usb/if_url.c USETW(val, aval);
val 486 dev/usb/if_url.c return (url_mem(sc, URL_CMD_WRITEMEM, reg, &val, 2) ? -1 : 0);
val 493 dev/usb/if_url.c uDWord val;
val 498 dev/usb/if_url.c USETDW(val, aval);
val 503 dev/usb/if_url.c return (url_mem(sc, URL_CMD_WRITEMEM, reg, &val, 4) ? -1 : 0);
val 1424 dev/usb/if_url.c u_int16_t val;
val 1460 dev/usb/if_url.c val = 0;
val 1475 dev/usb/if_url.c val = 0;
val 1481 dev/usb/if_url.c val = url_csr_read_1(sc, reg);
val 1483 dev/usb/if_url.c val = url_csr_read_2(sc, reg);
val 1487 dev/usb/if_url.c sc->sc_dev.dv_xname, __func__, phy, reg, val));
val 1490 dev/usb/if_url.c return (val);
val 1583 dev/usb/if_url.c u_int16_t val;
val 1614 dev/usb/if_url.c val = url_csr_read_2(sc, URL_PHYDAT);
val 1617 dev/usb/if_url.c sc->sc_dev.dv_xname, __func__, phy, reg, val));
val 1620 dev/usb/if_url.c return (val);
val 799 dev/usb/if_wi_usb.c u_int16_t val = 0;
val 844 dev/usb/if_wi_usb.c val = PRIVACY_INVOKED;
val 855 dev/usb/if_wi_usb.c val |= EXCLUDE_UNENCRYPTED;
val 864 dev/usb/if_wi_usb.c val |= HOST_ENCRYPT;
val 867 dev/usb/if_wi_usb.c val |= HOST_ENCRYPT|HOST_DECRYPT;
val 870 dev/usb/if_wi_usb.c p2ltv.wi_val = htole16(val);
val 813 dev/usb/if_zyd.c zyd_read16(struct zyd_softc *sc, uint16_t reg, uint16_t *val)
val 822 dev/usb/if_zyd.c *val = letoh16(tmp.val);
val 827 dev/usb/if_zyd.c zyd_read32(struct zyd_softc *sc, uint16_t reg, uint32_t *val)
val 838 dev/usb/if_zyd.c *val = letoh16(tmp[0].val) << 16 | letoh16(tmp[1].val);
val 843 dev/usb/if_zyd.c zyd_write16(struct zyd_softc *sc, uint16_t reg, uint16_t val)
val 848 dev/usb/if_zyd.c pair.val = htole16(val);
val 854 dev/usb/if_zyd.c zyd_write32(struct zyd_softc *sc, uint16_t reg, uint32_t val)
val 859 dev/usb/if_zyd.c pair[0].val = htole16(val >> 16);
val 861 dev/usb/if_zyd.c pair[1].val = htole16(val & 0xffff);
val 867 dev/usb/if_zyd.c zyd_rfwrite(struct zyd_softc *sc, uint32_t val)
val 881 dev/usb/if_zyd.c if (val & (1 << (rf->width - 1 - i)))
val 921 dev/usb/if_zyd.c error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
val 974 dev/usb/if_zyd.c error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
val 999 dev/usb/if_zyd.c error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
val 1062 dev/usb/if_zyd.c error = zyd_write16(sc, phyini_1[i].reg, phyini_1[i].val);
val 1073 dev/usb/if_zyd.c error = zyd_write16(sc, phyini_2[i].reg, phyini_2[i].val);
val 1084 dev/usb/if_zyd.c error = zyd_write16(sc, phyini_3[i].reg, phyini_3[i].val);
val 1158 dev/usb/if_zyd.c error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
val 1227 dev/usb/if_zyd.c error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
val 1276 dev/usb/if_zyd.c error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
val 1323 dev/usb/if_zyd.c error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
val 1361 dev/usb/if_zyd.c error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
val 1408 dev/usb/if_zyd.c error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
val 1530 dev/usb/if_zyd.c if ((error = zyd_write16(sc, phyp->reg, phyp->val)) != 0)
val 1592 dev/usb/if_zyd.c uint16_t val;
val 1616 dev/usb/if_zyd.c (void)zyd_read16(sc, ZYD_EEPROM_PWR_CAL + i, &val);
val 1617 dev/usb/if_zyd.c sc->pwr_cal[i * 2] = val >> 8;
val 1618 dev/usb/if_zyd.c sc->pwr_cal[i * 2 + 1] = val & 0xff;
val 1620 dev/usb/if_zyd.c (void)zyd_read16(sc, ZYD_EEPROM_PWR_INT + i, &val);
val 1621 dev/usb/if_zyd.c sc->pwr_int[i * 2] = val >> 8;
val 1622 dev/usb/if_zyd.c sc->pwr_int[i * 2 + 1] = val & 0xff;
val 1624 dev/usb/if_zyd.c (void)zyd_read16(sc, ZYD_EEPROM_36M_CAL + i, &val);
val 1625 dev/usb/if_zyd.c sc->ofdm36_cal[i * 2] = val >> 8;
val 1626 dev/usb/if_zyd.c sc->ofdm36_cal[i * 2 + 1] = val & 0xff;
val 1628 dev/usb/if_zyd.c (void)zyd_read16(sc, ZYD_EEPROM_48M_CAL + i, &val);
val 1629 dev/usb/if_zyd.c sc->ofdm48_cal[i * 2] = val >> 8;
val 1630 dev/usb/if_zyd.c sc->ofdm48_cal[i * 2 + 1] = val & 0xff;
val 1632 dev/usb/if_zyd.c (void)zyd_read16(sc, ZYD_EEPROM_54M_CAL + i, &val);
val 1633 dev/usb/if_zyd.c sc->ofdm54_cal[i * 2] = val >> 8;
val 1634 dev/usb/if_zyd.c sc->ofdm54_cal[i * 2 + 1] = val & 0xff;
val 1057 dev/usb/if_zydreg.h uint16_t val;
val 1094 dev/usb/if_zydreg.h uint8_t val;
val 1099 dev/usb/if_zydreg.h uint32_t val;
val 346 dev/usb/moscom.c int val;
val 350 dev/usb/moscom.c val = onoff ? MOSCOM_MCR_DTR : 0;
val 353 dev/usb/moscom.c val = onoff ? MOSCOM_MCR_RTS : 0;
val 356 dev/usb/moscom.c val = sc->sc_lcr;
val 358 dev/usb/moscom.c val |= MOSCOM_LCR_BREAK;
val 359 dev/usb/moscom.c moscom_cmd(sc, MOSCOM_LCR, val);
val 365 dev/usb/moscom.c moscom_cmd(sc, MOSCOM_MCR, val);
val 441 dev/usb/moscom.c moscom_cmd(struct moscom_softc *sc, int reg, int val)
val 448 dev/usb/moscom.c USETW(req.wValue, val + MOSCOM_UART_REG);
val 2218 dev/usb/uaudio.c int val;
val 2238 dev/usb/uaudio.c val = data[0];
val 2241 dev/usb/uaudio.c val = data[0] | (data[1] << 8);
val 2247 dev/usb/uaudio.c DPRINTFN(2,("uaudio_get: val=%d\n", val));
val 2248 dev/usb/uaudio.c return (val);
val 2253 dev/usb/uaudio.c int wIndex, int len, int val)
val 2269 dev/usb/uaudio.c data[0] = val;
val 2272 dev/usb/uaudio.c data[0] = val;
val 2273 dev/usb/uaudio.c data[1] = val >> 8;
val 2280 dev/usb/uaudio.c type, which, wValue, wIndex, len, val & 0xffff));
val 2289 dev/usb/uaudio.c uaudio_signext(int type, int val)
val 2293 dev/usb/uaudio.c val = (int16_t)val;
val 2295 dev/usb/uaudio.c val = (int8_t)val;
val 2297 dev/usb/uaudio.c return (val);
val 2301 dev/usb/uaudio.c uaudio_value2bsd(struct mixerctl *mc, int val)
val 2304 dev/usb/uaudio.c mc->type, val, mc->minval, mc->maxval));
val 2306 dev/usb/uaudio.c val = (val != 0);
val 2308 dev/usb/uaudio.c if (val < mc->minval || val > mc->maxval)
val 2309 dev/usb/uaudio.c val = mc->minval;
val 2311 dev/usb/uaudio.c val = ((uaudio_signext(mc->type, val) - mc->minval) * 255
val 2313 dev/usb/uaudio.c DPRINTFN(5, ("val'=%d\n", val));
val 2314 dev/usb/uaudio.c return (val);
val 2318 dev/usb/uaudio.c uaudio_bsd2value(struct mixerctl *mc, int val)
val 2321 dev/usb/uaudio.c mc->type, val, mc->minval, mc->maxval));
val 2323 dev/usb/uaudio.c val = (val != 0);
val 2325 dev/usb/uaudio.c if (val < mc->minval || val > mc->maxval)
val 2326 dev/usb/uaudio.c val = mc->minval;
val 2328 dev/usb/uaudio.c val = (val + mc->delta/2) * mc->mul / 255 + mc->minval;
val 2329 dev/usb/uaudio.c DPRINTFN(5, ("val'=%d\n", val));
val 2330 dev/usb/uaudio.c return (val);
val 2337 dev/usb/uaudio.c int val;
val 2340 dev/usb/uaudio.c val = uaudio_get(sc, which, UT_READ_CLASS_INTERFACE, mc->wValue[chan],
val 2342 dev/usb/uaudio.c return (uaudio_value2bsd(mc, val));
val 2347 dev/usb/uaudio.c int chan, int val)
val 2349 dev/usb/uaudio.c val = uaudio_bsd2value(mc, val);
val 2351 dev/usb/uaudio.c mc->wIndex, MIX_SIZE(mc->type), val);
val 2359 dev/usb/uaudio.c int i, n, vals[MIX_MAX_CHAN], val;
val 2388 dev/usb/uaudio.c for (val = 0, i = 0; i < mc->nchan; i++)
val 2389 dev/usb/uaudio.c val += vals[i];
val 2390 dev/usb/uaudio.c vals[0] = val / mc->nchan;
val 393 dev/usb/ueagle.c ueagle_request(struct ueagle_softc *sc, uint16_t val, uint16_t index,
val 401 dev/usb/ueagle.c USETW(req.wValue, val);
val 470 dev/usb/umct.c u_int val;
val 475 dev/usb/umct.c case 300: val = 0x01; break;
val 476 dev/usb/umct.c case 600: val = 0x02; break;
val 477 dev/usb/umct.c case 1200: val = 0x03; break;
val 478 dev/usb/umct.c case 2400: val = 0x04; break;
val 479 dev/usb/umct.c case 4800: val = 0x06; break;
val 480 dev/usb/umct.c case 9600: val = 0x08; break;
val 481 dev/usb/umct.c case 19200: val = 0x09; break;
val 482 dev/usb/umct.c case 38400: val = 0x0a; break;
val 483 dev/usb/umct.c case 57600: val = 0x0b; break;
val 484 dev/usb/umct.c case 115200: val = 0x0c; break;
val 485 dev/usb/umct.c default: val = -1; break;
val 488 dev/usb/umct.c val = UMCT_BAUD_RATE(rate);
val 490 dev/usb/umct.c USETDW(arate, val);
val 375 isofs/cd9660/cd9660_vfsops.c mp->mnt_stat.f_fsid.val[0] = (long)dev;
val 376 isofs/cd9660/cd9660_vfsops.c mp->mnt_stat.f_fsid.val[1] = mp->mnt_vfc->vfc_typenum;
val 256 isofs/udf/udf_vfsops.c mp->mnt_stat.f_fsid.val[0] = devvp->v_rdev;
val 257 isofs/udf/udf_vfsops.c mp->mnt_stat.f_fsid.val[1] = makefstype(MOUNT_UDF);
val 120 kern/kern_event.c #define KN_HASH(val, mask) (((val) ^ (val >> 8)) & (mask))
val 1479 kern/kern_sig.c initsiginfo(siginfo_t *si, int sig, u_long code, int type, union sigval val)
val 1486 kern/kern_sig.c si->si_value = val;
val 1493 kern/kern_sig.c si->si_addr = val.sival_ptr;
val 696 kern/kern_sysctl.c unsigned int oval = *valp, val = *valp;
val 702 kern/kern_sysctl.c if ((error = sysctl_int(oldp, oldlenp, newp, newlen, &val)))
val 704 kern/kern_sysctl.c if (val > oval)
val 706 kern/kern_sysctl.c *(unsigned int *)valp = val;
val 735 kern/kern_sysctl.c sysctl_rdint(void *oldp, size_t *oldlenp, void *newp, int val)
val 745 kern/kern_sysctl.c error = copyout((caddr_t)&val, oldp, sizeof(int));
val 789 kern/kern_sysctl.c sysctl_rdquad(void *oldp, size_t *oldlenp, void *newp, int64_t val)
val 799 kern/kern_sysctl.c error = copyout((caddr_t)&val, oldp, sizeof(int64_t));
val 1477 kern/subr_pool.c #define PRWORD(ovflw, fmt, width, fixed, val) do { \
val 1481 kern/subr_pool.c (val)) - (width); \
val 176 kern/subr_userconf.c userconf_hist_int(int val)
val 178 kern/subr_userconf.c snprintf(userconf_histbuf, sizeof userconf_histbuf, " %d",val);
val 198 kern/subr_userconf.c userconf_pnum(int val)
val 200 kern/subr_userconf.c if (val > -2 && val < 16) {
val 201 kern/subr_userconf.c printf("%d",val);
val 207 kern/subr_userconf.c printf("0%o",val);
val 210 kern/subr_userconf.c printf("%d",val);
val 214 kern/subr_userconf.c printf("0x%x",val);
val 309 kern/subr_userconf.c userconf_number(char *c, int *val)
val 347 kern/subr_userconf.c *val = neg ? - num : num;
val 387 kern/subr_userconf.c userconf_attr(char *cmd, int *val)
val 410 kern/subr_userconf.c *val = attr;
val 416 kern/subr_userconf.c userconf_modify(char *item, int *val)
val 425 kern/subr_userconf.c userconf_pnum(*val);
val 435 kern/subr_userconf.c *val = a;
val 761 kern/subr_userconf.c userconf_common_attr_val(short attr, int *val, char routine)
val 776 kern/subr_userconf.c if (val == NULL) {
val 780 kern/subr_userconf.c if (*val == *l) {
val 970 kern/subr_userconf.c userconf_add_read(char *prompt, char field, char *dev, int len, int *val)
val 977 kern/subr_userconf.c *val = -1;
val 998 kern/subr_userconf.c *val = a;
val 1020 kern/subr_userconf.c int val, max_unit, star_unit, orig;
val 1045 kern/subr_userconf.c 'a', dev, len, &val);
val 1047 kern/subr_userconf.c if (val != -1) {
val 1048 kern/subr_userconf.c orig = val;
val 1049 kern/subr_userconf.c new = cfdata[val];
val 1053 kern/subr_userconf.c 'i', dev, len, &val);
val 1056 kern/subr_userconf.c if (val != -1) {
val 1062 kern/subr_userconf.c userconf_hist_int(val);
val 1066 kern/subr_userconf.c for (i = userconf_maxdev; val <= i; i--)
val 1068 kern/subr_userconf.c cfdata[val] = new;
val 1072 kern/subr_userconf.c if (pv[i] != -1 && pv[i] >= val)
val 1078 kern/subr_userconf.c if (cfroots[i] != -1 && cfroots[i] >= val)
val 1151 kern/subr_userconf.c userconf_pdev(val);
val 358 kern/sysv_sem.c semaptr->sem_base[semnum].semval = arg->val;
val 821 kern/sysv_sem.c int error, val;
val 844 kern/sysv_sem.c val = seminfo.semmni;
val 845 kern/sysv_sem.c if ((error = sysctl_int(oldp, oldlenp, newp, newlen, &val)) ||
val 846 kern/sysv_sem.c val == seminfo.semmni)
val 849 kern/sysv_sem.c if (val < seminfo.semmni || val > 0xffff)
val 853 kern/sysv_sem.c sema_new = malloc(val * sizeof(struct semid_ds *),
val 858 kern/sysv_sem.c (val - seminfo.semmni) * sizeof(struct semid_ds *));
val 859 kern/sysv_sem.c newseqs = malloc(val * sizeof(unsigned short), M_SEM, M_WAITOK);
val 863 kern/sysv_sem.c (val - seminfo.semmni) * sizeof(unsigned short));
val 868 kern/sysv_sem.c seminfo.semmni = val;
val 871 kern/sysv_sem.c val = seminfo.semmns;
val 872 kern/sysv_sem.c if ((error = sysctl_int(oldp, oldlenp, newp, newlen, &val)) ||
val 873 kern/sysv_sem.c val == seminfo.semmns)
val 875 kern/sysv_sem.c if (val < seminfo.semmns || val > 0xffff)
val 877 kern/sysv_sem.c seminfo.semmns = val;
val 880 kern/sysv_sem.c val = seminfo.semmnu;
val 881 kern/sysv_sem.c if ((error = sysctl_int(oldp, oldlenp, newp, newlen, &val)) ||
val 882 kern/sysv_sem.c val == seminfo.semmnu)
val 884 kern/sysv_sem.c if (val < seminfo.semmnu)
val 886 kern/sysv_sem.c seminfo.semmnu = val;
val 889 kern/sysv_sem.c val = seminfo.semmsl;
val 890 kern/sysv_sem.c if ((error = sysctl_int(oldp, oldlenp, newp, newlen, &val)) ||
val 891 kern/sysv_sem.c val == seminfo.semmsl)
val 893 kern/sysv_sem.c if (val < seminfo.semmsl || val > 0xffff)
val 895 kern/sysv_sem.c seminfo.semmsl = val;
val 898 kern/sysv_sem.c val = seminfo.semopm;
val 899 kern/sysv_sem.c if ((error = sysctl_int(oldp, oldlenp, newp, newlen, &val)) ||
val 900 kern/sysv_sem.c val == seminfo.semopm)
val 902 kern/sysv_sem.c if (val <= 0)
val 904 kern/sysv_sem.c seminfo.semopm = val;
val 557 kern/sysv_shm.c int error, val;
val 585 kern/sysv_shm.c val = shminfo.shmmin;
val 586 kern/sysv_shm.c if ((error = sysctl_int(oldp, oldlenp, newp, newlen, &val)) ||
val 587 kern/sysv_shm.c val == shminfo.shmmin)
val 589 kern/sysv_shm.c if (val <= 0)
val 591 kern/sysv_shm.c shminfo.shmmin = val;
val 594 kern/sysv_shm.c val = shminfo.shmmni;
val 595 kern/sysv_shm.c if ((error = sysctl_int(oldp, oldlenp, newp, newlen, &val)) ||
val 596 kern/sysv_shm.c val == shminfo.shmmni)
val 599 kern/sysv_shm.c if (val < shminfo.shmmni || val > 0xffff)
val 603 kern/sysv_shm.c newsegs = malloc(val * sizeof(struct shmid_ds *),
val 608 kern/sysv_shm.c (val - shminfo.shmmni) * sizeof(struct shmid_ds *));
val 611 kern/sysv_shm.c newseqs = malloc(val * sizeof(unsigned short), M_SHM, M_WAITOK);
val 615 kern/sysv_shm.c (val - shminfo.shmmni) * sizeof(unsigned short));
val 618 kern/sysv_shm.c shminfo.shmmni = val;
val 621 kern/sysv_shm.c val = shminfo.shmseg;
val 622 kern/sysv_shm.c if ((error = sysctl_int(oldp, oldlenp, newp, newlen, &val)) ||
val 623 kern/sysv_shm.c val == shminfo.shmseg)
val 625 kern/sysv_shm.c if (val <= 0)
val 627 kern/sysv_shm.c shminfo.shmseg = val;
val 630 kern/sysv_shm.c val = shminfo.shmall;
val 631 kern/sysv_shm.c if ((error = sysctl_int(oldp, oldlenp, newp, newlen, &val)) ||
val 632 kern/sysv_shm.c val == shminfo.shmall)
val 634 kern/sysv_shm.c if (val < shminfo.shmall)
val 636 kern/sysv_shm.c shminfo.shmall = val;
val 1062 kern/uipc_socket.c short val;
val 1073 kern/uipc_socket.c val = tv->tv_sec * hz + tv->tv_usec / tick;
val 1074 kern/uipc_socket.c if (val == 0 && tv->tv_usec != 0)
val 1075 kern/uipc_socket.c val = 1;
val 1080 kern/uipc_socket.c so->so_snd.sb_timeo = val;
val 1083 kern/uipc_socket.c so->so_rcv.sb_timeo = val;
val 1169 kern/uipc_socket.c int val = (optname == SO_SNDTIMEO ?
val 1173 kern/uipc_socket.c mtod(m, struct timeval *)->tv_sec = val / hz;
val 1175 kern/uipc_socket.c (val % hz) * tick;
val 815 kern/uipc_syscalls.c if (SCARG(uap, val)) {
val 828 kern/uipc_syscalls.c error = copyin(SCARG(uap, val), mtod(m, caddr_t),
val 863 kern/uipc_syscalls.c if (SCARG(uap, val)) {
val 871 kern/uipc_syscalls.c SCARG(uap, name), &m)) == 0 && SCARG(uap, val) && valsize &&
val 875 kern/uipc_syscalls.c error = copyout(mtod(m, caddr_t), SCARG(uap, val), valsize);
val 252 kern/vfs_subr.c if (mp->mnt_stat.f_fsid.val[0] == fsid->val[0] &&
val 253 kern/vfs_subr.c mp->mnt_stat.f_fsid.val[1] == fsid->val[1]) {
val 274 kern/vfs_subr.c mp->mnt_stat.f_fsid.val[0] = makedev(nblkdev + mtype, 0);
val 275 kern/vfs_subr.c mp->mnt_stat.f_fsid.val[1] = mtype;
val 278 kern/vfs_subr.c tfsid.val[0] = makedev(nblkdev + mtype, xxxfs_mntid);
val 279 kern/vfs_subr.c tfsid.val[1] = mtype;
val 282 kern/vfs_subr.c tfsid.val[0]++;
val 286 kern/vfs_subr.c mp->mnt_stat.f_fsid.val[0] = tfsid.val[0];
val 2257 kern/vfs_subr.c mp->mnt_stat.f_fsid.val[0], mp->mnt_stat.f_fsid.val[1],
val 327 lib/libsa/net.c u_long val;
val 339 lib/libsa/net.c val = 0;
val 342 lib/libsa/net.c val = (val * 10) + (c - '0');
val 355 lib/libsa/net.c if (pp >= parts + 3 || val > 0xff)
val 357 lib/libsa/net.c *pp++ = val, cp++;
val 378 lib/libsa/net.c if (val > 0xffffff)
val 380 lib/libsa/net.c val |= parts[0] << 24;
val 384 lib/libsa/net.c if (val > 0xffff)
val 386 lib/libsa/net.c val |= (parts[0] << 24) | (parts[1] << 16);
val 390 lib/libsa/net.c if (val > 0xff)
val 392 lib/libsa/net.c val |= (parts[0] << 24) | (parts[1] << 16) | (parts[2] << 8);
val 396 lib/libsa/net.c return (htonl(val));
val 96 lib/libsa/netif.c int val;
val 131 lib/libsa/netif.c val = netif_match(&cur_if, machdep_hint);
val 134 lib/libsa/netif.c printf(" [%d -> %d]", s, val);
val 136 lib/libsa/netif.c if (val > best_val) {
val 137 lib/libsa/netif.c best_val = val;
val 408 lib/libz/infback.c if (this.val < 16) {
val 411 lib/libz/infback.c state->lens[state->have++] = this.val;
val 414 lib/libz/infback.c if (this.val == 16) {
val 426 lib/libz/infback.c else if (this.val == 17) {
val 498 lib/libz/infback.c this = state->lencode[last.val +
val 506 lib/libz/infback.c state->length = (unsigned)this.val;
val 510 lib/libz/infback.c Tracevv((stderr, this.val >= 0x20 && this.val < 0x7f ?
val 512 lib/libz/infback.c "inflate: literal 0x%02x\n", this.val));
val 552 lib/libz/infback.c this = state->distcode[last.val +
val 565 lib/libz/infback.c state->offset = (unsigned)this.val;
val 135 lib/libz/inffast.c Tracevv((stderr, this.val >= 0x20 && this.val < 0x7f ?
val 137 lib/libz/inffast.c "inflate: literal 0x%02x\n", this.val));
val 138 lib/libz/inffast.c PUP(out) = (unsigned char)(this.val);
val 141 lib/libz/inffast.c len = (unsigned)(this.val);
val 166 lib/libz/inffast.c dist = (unsigned)(this.val);
val 267 lib/libz/inffast.c this = dcode[this.val + (hold & ((1U << op) - 1))];
val 281 lib/libz/inffast.c this = lcode[this.val + (hold & ((1U << op) - 1))];
val 291 lib/libz/inflate.c state.lencode[low].val);
val 302 lib/libz/inflate.c state.distcode[low].val);
val 927 lib/libz/inflate.c if (this.val < 16) {
val 930 lib/libz/inflate.c state->lens[state->have++] = this.val;
val 933 lib/libz/inflate.c if (this.val == 16) {
val 949 lib/libz/inflate.c else if (this.val == 17) {
val 1027 lib/libz/inflate.c this = state->lencode[last.val +
val 1035 lib/libz/inflate.c state->length = (unsigned)this.val;
val 1037 lib/libz/inflate.c Tracevv((stderr, this.val >= 0x20 && this.val < 0x7f ?
val 1039 lib/libz/inflate.c "inflate: literal 0x%02x\n", this.val));
val 1076 lib/libz/inflate.c this = state->distcode[last.val +
val 1093 lib/libz/inflate.c state->offset = (unsigned)this.val;
val 121 lib/libz/inftrees.c this.val = (unsigned short)0;
val 222 lib/libz/inftrees.c this.val = work[sym];
val 226 lib/libz/inftrees.c this.val = base[work[sym]];
val 230 lib/libz/inftrees.c this.val = 0;
val 288 lib/libz/inftrees.c (*table)[low].val = (unsigned short)(next - *table);
val 301 lib/libz/inftrees.c this.val = (unsigned short)0;
val 28 lib/libz/inftrees.h unsigned short val; /* offset in table or code value */
val 516 miscfs/portal/portal_vnops.c vap->va_fsid = vp->v_mount->mnt_stat.f_fsid.val[0];
val 539 msdosfs/msdosfs_vfsops.c mp->mnt_stat.f_fsid.val[0] = (long)dev;
val 540 msdosfs/msdosfs_vfsops.c mp->mnt_stat.f_fsid.val[1] = mp->mnt_vfc->vfc_typenum;
val 2140 net/bridgestp.c int r = 0, err = 0, val;
val 2179 net/bridgestp.c val = ifbp->ifbrp_prio;
val 2180 net/bridgestp.c if (val < 0 || val > BSTP_MAX_PRIORITY) {
val 2186 net/bridgestp.c val -= val % 4096;
val 2187 net/bridgestp.c bs->bs_bridge_priority = val;
val 2194 net/bridgestp.c val = ifbp->ifbrp_maxage;
val 2197 net/bridgestp.c val *= BSTP_TICK_VAL;
val 2199 net/bridgestp.c if (val < BSTP_MIN_MAX_AGE || val > BSTP_MAX_MAX_AGE) {
val 2203 net/bridgestp.c bs->bs_bridge_max_age = val;
val 2210 net/bridgestp.c val = ifbp->ifbrp_hellotime;
val 2213 net/bridgestp.c val *= BSTP_TICK_VAL;
val 2220 net/bridgestp.c if (val < BSTP_MIN_HELLO_TIME || val > BSTP_MAX_HELLO_TIME) {
val 2224 net/bridgestp.c bs->bs_bridge_htime = val;
val 2231 net/bridgestp.c val = ifbp->ifbrp_fwddelay;
val 2234 net/bridgestp.c val *= BSTP_TICK_VAL;
val 2236 net/bridgestp.c if (val < BSTP_MIN_FORWARD_DELAY ||
val 2237 net/bridgestp.c val > BSTP_MAX_FORWARD_DELAY) {
val 2241 net/bridgestp.c bs->bs_bridge_fdelay = val;
val 2245 net/bridgestp.c val = ifbp->ifbrp_txhc;
val 2247 net/bridgestp.c if (val < BSTP_MIN_HOLD_COUNT || val > BSTP_MAX_HOLD_COUNT) {
val 2251 net/bridgestp.c bs->bs_txholdcount = val;
val 2256 net/bridgestp.c val = ifbr->ifbr_priority;
val 2257 net/bridgestp.c if (val < 0 || val > BSTP_MAX_PORT_PRIORITY)
val 2261 net/bridgestp.c val -= val % 16;
val 2262 net/bridgestp.c bp->bp_priority = val;
val 2266 net/bridgestp.c val = ifbr->ifbr_path_cost;
val 2267 net/bridgestp.c if (val > BSTP_MAX_PATH_COST) {
val 2271 net/bridgestp.c if (val == 0) { /* use auto */
val 2275 net/bridgestp.c bp->bp_path_cost = val;
val 2281 net/bridgestp.c val = ifbp->ifbrp_proto;
val 2284 net/bridgestp.c switch (val) {
val 2287 net/bridgestp.c bs->bs_protover = val;
val 1663 net/zlib.c int val = value;\
val 1664 net/zlib.c s->bi_buf |= (val << s->bi_valid);\
val 1666 net/zlib.c s->bi_buf = (ush)val >> (Buf_size - s->bi_valid);\
val 417 netbt/l2cap_signal.c l2cap_cfg_opt_val_t val;
val 485 netbt/l2cap_signal.c m_copydata(m, 0, L2CAP_OPT_MTU_SIZE, (caddr_t)&val);
val 486 netbt/l2cap_signal.c val.mtu = letoh16(val.mtu);
val 494 netbt/l2cap_signal.c if (val.mtu < L2CAP_MTU_MINIMUM) {
val 501 netbt/l2cap_signal.c val.mtu = htole16(L2CAP_MTU_MINIMUM);
val 502 netbt/l2cap_signal.c memcpy(buf + len, &val, L2CAP_OPT_MTU_SIZE);
val 505 netbt/l2cap_signal.c chan->lc_omtu = val.mtu;
val 582 netbt/l2cap_signal.c l2cap_cfg_opt_val_t val;
val 675 netbt/l2cap_signal.c m_copydata(m, 0, L2CAP_OPT_MTU_SIZE, (caddr_t)&val);
val 676 netbt/l2cap_signal.c chan->lc_imtu = letoh16(val.mtu);
val 1023 netbt/l2cap_signal.c l2cap_cfg_opt_val_t *val;
val 1044 netbt/l2cap_signal.c val = (l2cap_cfg_opt_val_t *)(opt + 1);
val 1045 netbt/l2cap_signal.c val->mtu = htole16(chan->lc_imtu);
val 1056 netbt/l2cap_signal.c val = (l2cap_cfg_opt_val_t *)(opt + 1);
val 1057 netbt/l2cap_signal.c val->flush_timo = htole16(chan->lc_flush);
val 277 netinet/ip6.h #define IP6_EXTHDR_GET(val, typ, m, off, len) \
val 282 netinet/ip6.h (val) = (typ)(mtod((m), caddr_t) + (off)); \
val 288 netinet/ip6.h (val) = (typ)(mtod(t, caddr_t) + tmp); \
val 290 netinet/ip6.h (val) = (typ)NULL; \
val 296 netinet/ip6.h #define IP6_EXTHDR_GET0(val, typ, m, off, len) \
val 300 netinet/ip6.h (val) = (typ)mtod((m), caddr_t); \
val 306 netinet/ip6.h (val) = (typ)mtod(t, caddr_t); \
val 308 netinet/ip6.h (val) = (typ)NULL; \
val 1203 netinet/tcp_subr.c tcp_rndiss_encrypt(val)
val 1204 netinet/tcp_subr.c u_int16_t val;
val 1210 netinet/tcp_subr.c val ^= ((u_int16_t)tcp_rndiss_sbox[(val^sum) & 0x7f]) << 7;
val 1211 netinet/tcp_subr.c val = ((val & 0xff) << 7) | (val >> 8);
val 1214 netinet/tcp_subr.c return val;
val 1202 nfs/nfs_subs.c vap->va_fsid = vp->v_mount->mnt_stat.f_fsid.val[0];
val 97 ntfs/ntfs_ihash.c u_long oldmask, mask, val;
val 110 ntfs/ntfs_ihash.c val = NTNOHASH(ip->i_dev, ip->i_number);
val 111 ntfs/ntfs_ihash.c LIST_INSERT_HEAD(&hash[val], ip, i_hash);
val 678 ntfs/ntfs_vfsops.c mp->mnt_stat.f_fsid.val[0] = dev2udev(dev);
val 679 ntfs/ntfs_vfsops.c mp->mnt_stat.f_fsid.val[1] = mp->mnt_vfc->vfc_typenum;
val 681 ntfs/ntfs_vfsops.c mp->mnt_stat.f_fsid.val[0] = dev;
val 682 ntfs/ntfs_vfsops.c mp->mnt_stat.f_fsid.val[1] = makefstype(MOUNT_NTFS);
val 360 scsi/scsiconf.h static __inline void _lto2b(u_int32_t val, u_int8_t *bytes);
val 361 scsi/scsiconf.h static __inline void _lto3b(u_int32_t val, u_int8_t *bytes);
val 362 scsi/scsiconf.h static __inline void _lto4b(u_int32_t val, u_int8_t *bytes);
val 363 scsi/scsiconf.h static __inline void _lto8b(u_int64_t val, u_int8_t *bytes);
val 370 scsi/scsiconf.h static __inline void _lto2l(u_int32_t val, u_int8_t *bytes);
val 371 scsi/scsiconf.h static __inline void _lto3l(u_int32_t val, u_int8_t *bytes);
val 372 scsi/scsiconf.h static __inline void _lto4l(u_int32_t val, u_int8_t *bytes);
val 378 scsi/scsiconf.h _lto2b(val, bytes)
val 379 scsi/scsiconf.h u_int32_t val;
val 383 scsi/scsiconf.h bytes[0] = (val >> 8) & 0xff;
val 384 scsi/scsiconf.h bytes[1] = val & 0xff;
val 388 scsi/scsiconf.h _lto3b(val, bytes)
val 389 scsi/scsiconf.h u_int32_t val;
val 393 scsi/scsiconf.h bytes[0] = (val >> 16) & 0xff;
val 394 scsi/scsiconf.h bytes[1] = (val >> 8) & 0xff;
val 395 scsi/scsiconf.h bytes[2] = val & 0xff;
val 399 scsi/scsiconf.h _lto4b(val, bytes)
val 400 scsi/scsiconf.h u_int32_t val;
val 404 scsi/scsiconf.h bytes[0] = (val >> 24) & 0xff;
val 405 scsi/scsiconf.h bytes[1] = (val >> 16) & 0xff;
val 406 scsi/scsiconf.h bytes[2] = (val >> 8) & 0xff;
val 407 scsi/scsiconf.h bytes[3] = val & 0xff;
val 411 scsi/scsiconf.h _lto8b(val, bytes)
val 412 scsi/scsiconf.h u_int64_t val;
val 416 scsi/scsiconf.h bytes[0] = (val >> 56) & 0xff;
val 417 scsi/scsiconf.h bytes[1] = (val >> 48) & 0xff;
val 418 scsi/scsiconf.h bytes[2] = (val >> 40) & 0xff;
val 419 scsi/scsiconf.h bytes[3] = (val >> 32) & 0xff;
val 420 scsi/scsiconf.h bytes[4] = (val >> 24) & 0xff;
val 421 scsi/scsiconf.h bytes[5] = (val >> 16) & 0xff;
val 422 scsi/scsiconf.h bytes[6] = (val >> 8) & 0xff;
val 423 scsi/scsiconf.h bytes[7] = val & 0xff;
val 489 scsi/scsiconf.h _lto2l(val, bytes)
val 490 scsi/scsiconf.h u_int32_t val;
val 494 scsi/scsiconf.h bytes[0] = val & 0xff;
val 495 scsi/scsiconf.h bytes[1] = (val >> 8) & 0xff;
val 499 scsi/scsiconf.h _lto3l(val, bytes)
val 500 scsi/scsiconf.h u_int32_t val;
val 504 scsi/scsiconf.h bytes[0] = val & 0xff;
val 505 scsi/scsiconf.h bytes[1] = (val >> 8) & 0xff;
val 506 scsi/scsiconf.h bytes[2] = (val >> 16) & 0xff;
val 510 scsi/scsiconf.h _lto4l(val, bytes)
val 511 scsi/scsiconf.h u_int32_t val;
val 515 scsi/scsiconf.h bytes[0] = val & 0xff;
val 516 scsi/scsiconf.h bytes[1] = (val >> 8) & 0xff;
val 517 scsi/scsiconf.h bytes[2] = (val >> 16) & 0xff;
val 518 scsi/scsiconf.h bytes[3] = (val >> 24) & 0xff;
val 45 sys/mount.h typedef struct { int32_t val[2]; } fsid_t; /* file system id type */
val 71 sys/reboot.h #define B_ADAPTOR(val) (((val) >> B_ADAPTORSHIFT) & B_ADAPTORMASK)
val 74 sys/reboot.h #define B_CONTROLLER(val) (((val)>>B_CONTROLLERSHIFT) & B_CONTROLLERMASK)
val 77 sys/reboot.h #define B_UNIT(val) (((val) >> B_UNITSHIFT) & B_UNITMASK)
val 80 sys/reboot.h #define B_PARTITION(val) (((val) >> B_PARTITIONSHIFT) & B_PARTITIONMASK)
val 83 sys/reboot.h #define B_TYPE(val) (((val) >> B_TYPESHIFT) & B_TYPEMASK)
val 110 sys/sem.h int val; /* value for SETVAL */
val 165 sys/signalvar.h union sigval val);
val 181 sys/signalvar.h int type, union sigval val);
val 473 sys/syscallargs.h syscallarg(const void *) val;
val 531 sys/syscallargs.h syscallarg(void *) val;
val 84 sys/termios.h #define CCEQ(val, c) (c == val ? val != _POSIX_VDISABLE : 0)
val 147 sys/tree.h name##_SPLAY_MIN_MAX(struct name *head, int val) \
val 149 sys/tree.h name##_SPLAY_MINMAX(head, val); \
val 648 sys/tree.h name##_RB_MINMAX(struct name *head, int val) \
val 654 sys/tree.h if (val < 0) \
val 55 ufs/ext2fs/ext2fs_subr.c int32_t val[2];
val 61 ufs/ext2fs/ext2fs_subr.c tmp.val[_QUAD_HIGHWORD] = (h); \
val 68 ufs/ext2fs/ext2fs_subr.c tmp.val[_QUAD_LOWWORD] = (l); \
val 577 ufs/ext2fs/ext2fs_vfsops.c mp->mnt_stat.f_fsid.val[0] = (long)dev;
val 578 ufs/ext2fs/ext2fs_vfsops.c mp->mnt_stat.f_fsid.val[1] = mp->mnt_vfc->vfc_typenum;
val 841 ufs/ffs/ffs_vfsops.c mp->mnt_stat.f_fsid.val[0] = (long)dev;
val 844 ufs/ffs/ffs_vfsops.c mp->mnt_stat.f_fsid.val[1] = fs->fs_id[1];
val 846 ufs/ffs/ffs_vfsops.c mp->mnt_stat.f_fsid.val[1] = mp->mnt_vfc->vfc_typenum;
val 56 ufs/ufs/ufs_dirhash.c #define WRAPINCR(val, limit) (((val) + 1 == (limit)) ? 0 : ((val) + 1))
val 57 ufs/ufs/ufs_dirhash.c #define WRAPDECR(val, limit) (((val) == 0) ? ((limit) - 1) : ((val) - 1))
val 83 ufs/ufs/ufs_vnops.c int32_t val[2];
val 89 ufs/ufs/ufs_vnops.c tmp.val[_QUAD_HIGHWORD] = (h); \
val 95 ufs/ufs/ufs_vnops.c tmp.val[_QUAD_LOWWORD] = (l); \
val 133 uvm/uvm_param.h void *val;
val 165 xfs/xfs_vfsops-common.c mp->mnt_stat.f_fsid.val[0] = dev;
val 166 xfs/xfs_vfsops-common.c mp->mnt_stat.f_fsid.val[1] = MOUNT_NNPFS;