1 /* $OpenBSD: if_tlreg.h,v 1.9 2005/12/17 07:31:27 miod Exp $ */
2
3 /*
4 * Copyright (c) 1997, 1998
5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 * $FreeBSD: src/sys/pci/if_tlreg.h,v 1.17 2001/02/09 06:11:21 bmilekic Exp $
35 */
36
37
38 struct tl_type {
39 u_int16_t tl_vid;
40 u_int16_t tl_did;
41 char *tl_name;
42 };
43
44 /*
45 * ThunderLAN TX/RX list format. The TX and RX lists are pretty much
46 * identical: the list begins with a 32-bit forward pointer which points
47 * at the next list in the chain, followed by 16 bits for the total
48 * frame size, and a 16 bit status field. This is followed by a series
49 * of 10 32-bit data count/data address pairs that point to the fragments
50 * that make up the complete frame.
51 */
52
53 #define TL_MAXFRAGS 10
54 #define TL_RX_LIST_CNT 20
55 #define TL_TX_LIST_CNT 64
56 #define TL_MIN_FRAMELEN 128
57
58 struct tl_frag {
59 u_int32_t tlist_dcnt;
60 u_int32_t tlist_dadr;
61 };
62
63 struct tl_list {
64 u_int32_t tlist_fptr; /* phys address of next list */
65 u_int16_t tlist_cstat; /* status word */
66 u_int16_t tlist_frsize; /* size of data in frame */
67 struct tl_frag tl_frag[TL_MAXFRAGS];
68 };
69
70 /*
71 * This is a special case of an RX list. By setting the One_Frag
72 * bit in the NETCONFIG register, the driver can force the ThunderLAN
73 * chip to use only one fragment when DMAing RX frames.
74 */
75
76 struct tl_list_onefrag {
77 u_int32_t tlist_fptr;
78 u_int16_t tlist_cstat;
79 u_int16_t tlist_frsize;
80 struct tl_frag tl_frag;
81 };
82
83 struct tl_list_data {
84 struct tl_list_onefrag tl_rx_list[TL_RX_LIST_CNT];
85 struct tl_list tl_tx_list[TL_TX_LIST_CNT];
86 unsigned char tl_pad[TL_MIN_FRAMELEN];
87 };
88
89 struct tl_chain {
90 struct tl_list *tl_ptr;
91 struct mbuf *tl_mbuf;
92 struct tl_chain *tl_next;
93 };
94
95 struct tl_chain_onefrag {
96 struct tl_list_onefrag *tl_ptr;
97 struct mbuf *tl_mbuf;
98 struct tl_chain_onefrag *tl_next;
99 };
100
101 struct tl_chain_data {
102 struct tl_chain_onefrag tl_rx_chain[TL_RX_LIST_CNT];
103 struct tl_chain tl_tx_chain[TL_TX_LIST_CNT];
104
105 struct tl_chain_onefrag *tl_rx_head;
106 struct tl_chain_onefrag *tl_rx_tail;
107
108 struct tl_chain *tl_tx_head;
109 struct tl_chain *tl_tx_tail;
110 struct tl_chain *tl_tx_free;
111 };
112
113 struct tl_products {
114 u_int16_t tp_vend;
115 u_int16_t tp_prod;
116 u_int32_t tp_tlphymedia;
117 };
118
119 struct tl_softc {
120 struct device sc_dev; /* generic device structure */
121 void * sc_ih; /* interrupt handler cookie */
122 struct arpcom arpcom; /* interface info */
123 struct ifmedia ifmedia; /* media info */
124 struct timeout tl_stats_tmo, tl_wait_tmo;
125 bus_space_handle_t tl_bhandle;
126 bus_space_tag_t tl_btag;
127 bus_dma_tag_t sc_dmat;
128 struct tl_type *tl_dinfo; /* ThunderLAN adapter info */
129 struct tl_type *tl_pinfo; /* PHY info struct */
130 int tl_if_flags;
131 u_int8_t tl_ctlr; /* chip number */
132 u_int8_t tl_eeaddr;
133 struct tl_list_data *tl_ldata; /* TX/RX lists and mbufs */
134 struct tl_chain_data tl_cdata;
135 u_int8_t tl_txeoc;
136 u_int8_t tl_bitrate;
137 struct mii_data sc_mii;
138 const struct tl_products *tl_product;
139 };
140
141 /*
142 * Transmit interrupt threshold.
143 */
144 #define TX_THR 0x00000004
145
146 /*
147 * General constants that are fun to know.
148 *
149 * The ThunderLAN controller is made by Texas Instruments. The
150 * manual indicates that if the EEPROM checksum fails, the PCI
151 * vendor and device ID registers will be loaded with TI-specific
152 * values.
153 */
154 #define TI_VENDORID 0x104C
155 #define TI_DEVICEID_THUNDERLAN 0x0500
156
157 /*
158 * These are the PCI vendor and device IDs for Compaq ethernet
159 * adapters based on the ThunderLAN controller.
160 */
161 #define COMPAQ_VENDORID 0x0E11
162 #define COMPAQ_DEVICEID_NETEL_10_100 0xAE32
163 #define COMPAQ_DEVICEID_NETEL_UNKNOWN 0xAE33
164 #define COMPAQ_DEVICEID_NETEL_10 0xAE34
165 #define COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED 0xAE35
166 #define COMPAQ_DEVICEID_NETEL_10_100_DUAL 0xAE40
167 #define COMPAQ_DEVICEID_NETEL_10_100_PROLIANT 0xAE43
168 #define COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED 0xB011
169 #define COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX 0xB012
170 #define COMPAQ_DEVICEID_NETEL_10_100_TX_UTP 0xB030
171 #define COMPAQ_DEVICEID_NETFLEX_3P 0xF130
172 #define COMPAQ_DEVICEID_NETFLEX_3P_BNC 0xF150
173
174 /*
175 * These are the PCI vendor and device IDs for Olicom
176 * adapters based on the ThunderLAN controller.
177 */
178 #define OLICOM_VENDORID 0x108D
179 #define OLICOM_DEVICEID_OC2183 0x0013
180 #define OLICOM_DEVICEID_OC2325 0x0012
181 #define OLICOM_DEVICEID_OC2326 0x0014
182
183 /*
184 * PCI low memory base and low I/O base
185 */
186 #define TL_PCI_LOIO 0x10
187 #define TL_PCI_LOMEM 0x14
188
189 /*
190 * PCI latency timer (it's actually 0x0D, but we want a value
191 * that's longword aligned).
192 */
193 #define TL_PCI_LATENCY_TIMER 0x0C
194
195 #define TL_DIO_ADDR_INC 0x8000 /* Increment addr on each read */
196 #define TL_DIO_RAM_SEL 0x4000 /* RAM address select */
197 #define TL_DIO_ADDR_MASK 0x3FFF /* address bits mask */
198
199 /*
200 * Interrupt types
201 */
202 #define TL_INTR_INVALID 0x0
203 #define TL_INTR_TXEOF 0x1
204 #define TL_INTR_STATOFLOW 0x2
205 #define TL_INTR_RXEOF 0x3
206 #define TL_INTR_DUMMY 0x4
207 #define TL_INTR_TXEOC 0x5
208 #define TL_INTR_ADCHK 0x6
209 #define TL_INTR_RXEOC 0x7
210
211 #define TL_INT_MASK 0x001C
212 #define TL_VEC_MASK 0x1FE0
213 /*
214 * Host command register bits
215 */
216 #define TL_CMD_GO 0x80000000
217 #define TL_CMD_STOP 0x40000000
218 #define TL_CMD_ACK 0x20000000
219 #define TL_CMD_CHSEL7 0x10000000
220 #define TL_CMD_CHSEL6 0x08000000
221 #define TL_CMD_CHSEL5 0x04000000
222 #define TL_CMD_CHSEL4 0x02000000
223 #define TL_CMD_CHSEL3 0x01000000
224 #define TL_CMD_CHSEL2 0x00800000
225 #define TL_CMD_CHSEL1 0x00400000
226 #define TL_CMD_CHSEL0 0x00200000
227 #define TL_CMD_EOC 0x00100000
228 #define TL_CMD_RT 0x00080000
229 #define TL_CMD_NES 0x00040000
230 #define TL_CMD_ZERO0 0x00020000
231 #define TL_CMD_ZERO1 0x00010000
232 #define TL_CMD_ADRST 0x00008000
233 #define TL_CMD_LDTMR 0x00004000
234 #define TL_CMD_LDTHR 0x00002000
235 #define TL_CMD_REQINT 0x00001000
236 #define TL_CMD_INTSOFF 0x00000800
237 #define TL_CMD_INTSON 0x00000400
238 #define TL_CMD_RSVD0 0x00000200
239 #define TL_CMD_RSVD1 0x00000100
240 #define TL_CMD_ACK7 0x00000080
241 #define TL_CMD_ACK6 0x00000040
242 #define TL_CMD_ACK5 0x00000020
243 #define TL_CMD_ACK4 0x00000010
244 #define TL_CMD_ACK3 0x00000008
245 #define TL_CMD_ACK2 0x00000004
246 #define TL_CMD_ACK1 0x00000002
247 #define TL_CMD_ACK0 0x00000001
248
249 #define TL_CMD_CHSEL_MASK 0x01FE0000
250 #define TL_CMD_ACK_MASK 0xFF
251
252 /*
253 * EEPROM address where station address resides.
254 */
255 #define TL_EEPROM_EADDR 0x83
256 #define TL_EEPROM_EADDR2 0x99
257 #define TL_EEPROM_EADDR3 0xAF
258 #define TL_EEPROM_EADDR_OC 0xF8 /* Olicom cards use a different
259 address than Compaqs. */
260 /*
261 * ThunderLAN host command register offsets.
262 * (Can be accessed either by IO ports or memory map.)
263 */
264 #define TL_HOSTCMD 0x00
265 #define TL_CH_PARM 0x04
266 #define TL_DIO_ADDR 0x08
267 #define TL_HOST_INT 0x0A
268 #define TL_DIO_DATA 0x0C
269
270 /*
271 * ThunderLAN internal registers
272 */
273 #define TL_NETCMD 0x00
274 #define TL_NETSIO 0x01
275 #define TL_NETSTS 0x02
276 #define TL_NETMASK 0x03
277
278 #define TL_NETCONFIG 0x04
279 #define TL_MANTEST 0x06
280
281 #define TL_VENID_LSB 0x08
282 #define TL_VENID_MSB 0x09
283 #define TL_DEVID_LSB 0x0A
284 #define TL_DEVID_MSB 0x0B
285
286 #define TL_REVISION 0x0C
287 #define TL_SUBCLASS 0x0D
288 #define TL_MINLAT 0x0E
289 #define TL_MAXLAT 0x0F
290
291 #define TL_AREG0_B5 0x10
292 #define TL_AREG0_B4 0x11
293 #define TL_AREG0_B3 0x12
294 #define TL_AREG0_B2 0x13
295
296 #define TL_AREG0_B1 0x14
297 #define TL_AREG0_B0 0x15
298 #define TL_AREG1_B5 0x16
299 #define TL_AREG1_B4 0x17
300
301 #define TL_AREG1_B3 0x18
302 #define TL_AREG1_B2 0x19
303 #define TL_AREG1_B1 0x1A
304 #define TL_AREG1_B0 0x1B
305
306 #define TL_AREG2_B5 0x1C
307 #define TL_AREG2_B4 0x1D
308 #define TL_AREG2_B3 0x1E
309 #define TL_AREG2_B2 0x1F
310
311 #define TL_AREG2_B1 0x20
312 #define TL_AREG2_B0 0x21
313 #define TL_AREG3_B5 0x22
314 #define TL_AREG3_B4 0x23
315
316 #define TL_AREG3_B3 0x24
317 #define TL_AREG3_B2 0x25
318 #define TL_AREG3_B1 0x26
319 #define TL_AREG3_B0 0x27
320
321 #define TL_HASH1 0x28
322 #define TL_HASH2 0x2C
323 #define TL_TXGOODFRAMES 0x30
324 #define TL_TXUNDERRUN 0x33
325 #define TL_RXGOODFRAMES 0x34
326 #define TL_RXOVERRUN 0x37
327 #define TL_DEFEREDTX 0x38
328 #define TL_CRCERROR 0x3A
329 #define TL_CODEERROR 0x3B
330 #define TL_MULTICOLTX 0x3C
331 #define TL_SINGLECOLTX 0x3E
332 #define TL_EXCESSIVECOL 0x40
333 #define TL_LATECOL 0x41
334 #define TL_CARRIERLOSS 0x42
335 #define TL_ACOMMIT 0x43
336 #define TL_LDREG 0x44
337 #define TL_BSIZEREG 0x45
338 #define TL_MAXRX 0x46
339
340 /*
341 * ThunderLAN SIO register bits
342 */
343 #define TL_SIO_MINTEN 0x80
344 #define TL_SIO_ECLOK 0x40
345 #define TL_SIO_ETXEN 0x20
346 #define TL_SIO_EDATA 0x10
347 #define TL_SIO_NMRST 0x08
348 #define TL_SIO_MCLK 0x04
349 #define TL_SIO_MTXEN 0x02
350 #define TL_SIO_MDATA 0x01
351
352 /*
353 * Thunderlan NETCONFIG bits
354 */
355 #define TL_CFG_RCLKTEST 0x8000
356 #define TL_CFG_TCLKTEST 0x4000
357 #define TL_CFG_BITRATE 0x2000
358 #define TL_CFG_RXCRC 0x1000
359 #define TL_CFG_PEF 0x0800
360 #define TL_CFG_ONEFRAG 0x0400
361 #define TL_CFG_ONECHAN 0x0200
362 #define TL_CFG_MTEST 0x0100
363 #define TL_CFG_PHYEN 0x0080
364 #define TL_CFG_MACSEL6 0x0040
365 #define TL_CFG_MACSEL5 0x0020
366 #define TL_CFG_MACSEL4 0x0010
367 #define TL_CFG_MACSEL3 0x0008
368 #define TL_CFG_MACSEL2 0x0004
369 #define TL_CFG_MACSEL1 0x0002
370 #define TL_CFG_MACSEL0 0x0001
371
372 /*
373 * ThunderLAN NETSTS bits
374 */
375 #define TL_STS_MIRQ 0x80
376 #define TL_STS_HBEAT 0x40
377 #define TL_STS_TXSTOP 0x20
378 #define TL_STS_RXSTOP 0x10
379
380 /*
381 * ThunderLAN NETCMD bits
382 */
383 #define TL_CMD_NRESET 0x80
384 #define TL_CMD_NWRAP 0x40
385 #define TL_CMD_CSF 0x20
386 #define TL_CMD_CAF 0x10
387 #define TL_CMD_NOBRX 0x08
388 #define TL_CMD_DUPLEX 0x04
389 #define TL_CMD_TRFRAM 0x02
390 #define TL_CMD_TXPACE 0x01
391
392 /*
393 * ThunderLAN NETMASK bits
394 */
395 #define TL_MASK_MASK7 0x80
396 #define TL_MASK_MASK6 0x40
397 #define TL_MASK_MASK5 0x20
398 #define TL_MASK_MASK4 0x10
399
400 /*
401 * MII frame format
402 */
403 #ifdef ANSI_DOESNT_ALLOW_BITFIELDS
404 struct tl_mii_frame {
405 u_int16_t mii_stdelim:2,
406 mii_opcode:2,
407 mii_phyaddr:5,
408 mii_regaddr:5,
409 mii_turnaround:2;
410 u_int16_t mii_data;
411 };
412 #else
413 struct tl_mii_frame {
414 u_int8_t mii_stdelim;
415 u_int8_t mii_opcode;
416 u_int8_t mii_phyaddr;
417 u_int8_t mii_regaddr;
418 u_int8_t mii_turnaround;
419 u_int16_t mii_data;
420 };
421 #endif
422 /*
423 * MII constants
424 */
425 #define TL_MII_STARTDELIM 0x01
426 #define TL_MII_READOP 0x02
427 #define TL_MII_WRITEOP 0x01
428 #define TL_MII_TURNAROUND 0x02
429
430 #define TL_LAST_FRAG 0x80000000
431 #define TL_CSTAT_UNUSED 0x8000
432 #define TL_CSTAT_FRAMECMP 0x4000
433 #define TL_CSTAT_READY 0x3000
434 #define TL_CSTAT_UNUSED13 0x2000
435 #define TL_CSTAT_UNUSED12 0x1000
436 #define TL_CSTAT_EOC 0x0800
437 #define TL_CSTAT_RXERROR 0x0400
438 #define TL_CSTAT_PASSCRC 0x0200
439 #define TL_CSTAT_DPRIO 0x0100
440
441 #define TL_FRAME_MASK 0x00FFFFFF
442 #define tl_tx_goodframes(x) (x.tl_txstat & TL_FRAME_MASK)
443 #define tl_tx_underrun(x) ((x.tl_txstat & ~TL_FRAME_MASK) >> 24)
444 #define tl_rx_goodframes(x) (x.tl_rxstat & TL_FRAME_MASK)
445 #define tl_rx_overrun(x) ((x.tl_rxstat & ~TL_FRAME_MASK) >> 24)
446
447 struct tl_stats {
448 u_int32_t tl_txstat;
449 u_int32_t tl_rxstat;
450 u_int16_t tl_deferred;
451 u_int8_t tl_crc_errors;
452 u_int8_t tl_code_errors;
453 u_int16_t tl_tx_multi_collision;
454 u_int16_t tl_tx_single_collision;
455 u_int8_t tl_excessive_collision;
456 u_int8_t tl_late_collision;
457 u_int8_t tl_carrier_loss;
458 u_int8_t acommit;
459 };
460
461 /*
462 * ACOMMIT register bits. These are used only when a bitrate
463 * PHY is selected ('bitrate' bit in netconfig register is set).
464 */
465 #define TL_AC_MTXER 0x01 /* reserved */
466 #define TL_AC_MTXD1 0x02 /* 0 == 10baseT 1 == AUI */
467 #define TL_AC_MTXD2 0x04 /* loopback disable */
468 #define TL_AC_MTXD3 0x08 /* full duplex disable */
469
470 #define TL_AC_TXTHRESH 0xF0
471 #define TL_AC_TXTHRESH_16LONG 0x00
472 #define TL_AC_TXTHRESH_32LONG 0x10
473 #define TL_AC_TXTHRESH_64LONG 0x20
474 #define TL_AC_TXTHRESH_128LONG 0x30
475 #define TL_AC_TXTHRESH_256LONG 0x40
476 #define TL_AC_TXTHRESH_WHOLEPKT 0x50
477
478 /*
479 * PCI burst size register (TL_BSIZEREG).
480 */
481 #define TL_RXBURST 0x0F
482 #define TL_TXBURST 0xF0
483
484 #define TL_RXBURST_4LONG 0x00
485 #define TL_RXBURST_8LONG 0x01
486 #define TL_RXBURST_16LONG 0x02
487 #define TL_RXBURST_32LONG 0x03
488 #define TL_RXBURST_64LONG 0x04
489 #define TL_RXBURST_128LONG 0x05
490
491 #define TL_TXBURST_4LONG 0x00
492 #define TL_TXBURST_8LONG 0x10
493 #define TL_TXBURST_16LONG 0x20
494 #define TL_TXBURST_32LONG 0x30
495 #define TL_TXBURST_64LONG 0x40
496 #define TL_TXBURST_128LONG 0x50
497
498 /*
499 * register space access macros
500 */
501 #define CSR_WRITE_4(sc, reg, val) \
502 bus_space_write_4(sc->tl_btag, sc->tl_bhandle, reg, val)
503 #define CSR_WRITE_2(sc, reg, val) \
504 bus_space_write_2(sc->tl_btag, sc->tl_bhandle, reg, val)
505 #define CSR_WRITE_1(sc, reg, val) \
506 bus_space_write_1(sc->tl_btag, sc->tl_bhandle, reg, val)
507
508 #define CSR_READ_4(sc, reg) \
509 bus_space_read_4(sc->tl_btag, sc->tl_bhandle, reg)
510 #define CSR_READ_2(sc, reg) \
511 bus_space_read_2(sc->tl_btag, sc->tl_bhandle, reg)
512 #define CSR_READ_1(sc, reg) \
513 bus_space_read_1(sc->tl_btag, sc->tl_bhandle, reg)
514
515 #define CMD_PUT(sc, x) CSR_WRITE_4(sc, TL_HOSTCMD, x)
516 #define CMD_SET(sc, x) \
517 CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) | (x))
518 #define CMD_CLR(sc, x) \
519 CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) & ~(x))
520
521 /*
522 * ThunderLAN adapters typically have a serial EEPROM containing
523 * configuration information. The main reason we're interested in
524 * it is because it also contains the adapters's station address.
525 *
526 * Access to the EEPROM is a bit goofy since it is a serial device:
527 * you have to do reads and writes one bit at a time. The state of
528 * the DATA bit can only change while the CLOCK line is held low.
529 * Transactions work basically like this:
530 *
531 * 1) Send the EEPROM_START sequence to prepare the EEPROM for
532 * accepting commands. This pulls the clock high, sets
533 * the data bit to 0, enables transmission to the EEPROM,
534 * pulls the data bit up to 1, then pulls the clock low.
535 * The idea is to do a 0 to 1 transition of the data bit
536 * while the clock pin is held high.
537 *
538 * 2) To write a bit to the EEPROM, set the TXENABLE bit, then
539 * set the EDATA bit to send a 1 or clear it to send a 0.
540 * Finally, set and then clear ECLOK. Strobing the clock
541 * transmits the bit. After 8 bits have been written, the
542 * EEPROM should respond with an ACK, which should be read.
543 *
544 * 3) To read a bit from the EEPROM, clear the TXENABLE bit,
545 * then set ECLOK. The bit can then be read by reading EDATA.
546 * ECLOCK should then be cleared again. This can be repeated
547 * 8 times to read a whole byte, after which the
548 *
549 * 4) We need to send the address byte to the EEPROM. For this
550 * we have to send the write control byte to the EEPROM to
551 * tell it to accept data. The byte is 0xA0. The EEPROM should
552 * ack this. The address byte can be send after that.
553 *
554 * 5) Now we have to tell the EEPROM to send us data. For that we
555 * have to transmit the read control byte, which is 0xA1. This
556 * byte should also be acked. We can then read the data bits
557 * from the EEPROM.
558 *
559 * 6) When we're all finished, send the EEPROM_STOP sequence.
560 *
561 * Note that we use the ThunderLAN's NetSio register to access the
562 * EEPROM, however there is an alternate method. There is a PCI NVRAM
563 * register at PCI offset 0xB4 which can also be used with minor changes.
564 * The difference is that access to PCI registers via pci_conf_read()
565 * and pci_conf_write() is done using programmed I/O, which we want to
566 * avoid.
567 */
568
569 /*
570 * Note that EEPROM_START leaves transmission enabled.
571 */
572 #define EEPROM_START \
573 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock pin high */\
574 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Set DATA bit to 1 */ \
575 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Enable xmit to write bit */\
576 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Pull DATA bit to 0 again */\
577 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock low again */
578
579 /*
580 * EEPROM_STOP ends access to the EEPROM and clears the ETXEN bit so
581 * that no further data can be written to the EEPROM I/O pin.
582 */
583 #define EEPROM_STOP \
584 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Disable xmit */ \
585 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Pull DATA to 0 */ \
586 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock high */ \
587 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Enable xmit */ \
588 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Toggle DATA to 1 */ \
589 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Disable xmit. */ \
590 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock low again */
591
592 /*
593 * Microchip Technology 24Cxx EEPROM control bytes
594 */
595 #define EEPROM_CTL_READ 0xA1 /* 0101 0001 */
596 #define EEPROM_CTL_WRITE 0xA0 /* 0101 0000 */
597
598 #ifdef __alpha__
599 #undef vtophys
600 #define vtophys(va) alpha_XXX_dmamap((vaddr_t)va)
601 #endif