CSR_READ_1 1476 dev/ic/acx.c *val = CSR_READ_1(sc, ACXREG_EEPROM_DATA);
CSR_READ_1 1503 dev/ic/acx.c *val = CSR_READ_1(sc, ACXREG_PHY_DATA);
CSR_READ_1 201 dev/ic/fxp.c while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
CSR_READ_1 818 dev/ic/fxp.c statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
CSR_READ_1 826 dev/ic/fxp.c while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
CSR_READ_1 1019 dev/ic/fxp.c if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
CSR_READ_1 1741 dev/ic/fxp.c while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) != FXP_SCB_CUS_IDLE);
CSR_READ_1 202 dev/ic/re.c CSR_READ_1(sc, RL_EECMD) | x)
CSR_READ_1 206 dev/ic/re.c CSR_READ_1(sc, RL_EECMD) & ~x)
CSR_READ_1 289 dev/ic/re.c if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
CSR_READ_1 335 dev/ic/re.c rval = CSR_READ_1(sc, RL_GMEDIASTAT);
CSR_READ_1 427 dev/ic/re.c rval = CSR_READ_1(sc, RL_MEDIASTAT);
CSR_READ_1 604 dev/ic/re.c if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
CSR_READ_1 1932 dev/ic/re.c CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD);
CSR_READ_1 167 dev/ic/rtl81x9.c CSR_READ_1(sc, RL_EECMD) | x)
CSR_READ_1 171 dev/ic/rtl81x9.c CSR_READ_1(sc, RL_EECMD) & ~x)
CSR_READ_1 228 dev/ic/rtl81x9.c if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
CSR_READ_1 272 dev/ic/rtl81x9.c CSR_READ_1(sc, RL_MII) | x)
CSR_READ_1 276 dev/ic/rtl81x9.c CSR_READ_1(sc, RL_MII) & ~x)
CSR_READ_1 529 dev/ic/rtl81x9.c if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
CSR_READ_1 613 dev/ic/rtl81x9.c while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
CSR_READ_1 1400 dev/ic/rtl81x9.c return (CSR_READ_1(sc, RL_MEDIASTAT));
CSR_READ_1 789 dev/ic/rtl81x9reg.h CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))
CSR_READ_1 792 dev/ic/rtl81x9reg.h CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))
CSR_READ_1 488 dev/ic/xl.c (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
CSR_READ_1 573 dev/ic/xl.c rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
CSR_READ_1 606 dev/ic/xl.c rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
CSR_READ_1 652 dev/ic/xl.c rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
CSR_READ_1 785 dev/ic/xl.c (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
CSR_READ_1 1430 dev/ic/xl.c while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
CSR_READ_1 1577 dev/ic/xl.c *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
CSR_READ_1 1592 dev/ic/xl.c CSR_READ_1(sc, XL_W4_BADSSD);
CSR_READ_1 2019 dev/ic/xl.c rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
CSR_READ_1 2029 dev/ic/xl.c rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
CSR_READ_1 2100 dev/ic/xl.c macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
CSR_READ_1 2221 dev/ic/xl.c if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
CSR_READ_1 2230 dev/ic/xl.c if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
CSR_READ_1 122 dev/pci/if_ipw.c return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA);
CSR_READ_1 1979 dev/pci/if_ipw.c *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3));
CSR_READ_1 133 dev/pci/if_iwi.c return CSR_READ_1(sc, IWI_CSR_INDIRECT_DATA);
CSR_READ_1 667 dev/pci/if_lge.c if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0)
CSR_READ_1 996 dev/pci/if_lge.c txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT);
CSR_READ_1 1175 dev/pci/if_lge.c if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0)
CSR_READ_1 235 dev/pci/if_msk.c return CSR_READ_1(sc, reg);
CSR_READ_1 865 dev/pci/if_msk.c DPRINTFN(2, ("mskc_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR)));
CSR_READ_1 226 dev/pci/if_sk.c return CSR_READ_1(sc, reg);
CSR_READ_1 136 dev/pci/if_ste.c CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x)
CSR_READ_1 139 dev/pci/if_ste.c CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x)
CSR_READ_1 724 dev/pci/if_ste.c while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) &
CSR_READ_1 799 dev/pci/if_ste.c ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS)
CSR_READ_1 800 dev/pci/if_ste.c + CSR_READ_1(sc, STE_MULTI_COLLS)
CSR_READ_1 801 dev/pci/if_ste.c + CSR_READ_1(sc, STE_SINGLE_COLLS);
CSR_READ_1 377 dev/pci/if_stge.c sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) &
CSR_READ_1 1686 dev/pci/if_stge.c return (CSR_READ_1(sc, STGE_PhyCtrl));
CSR_READ_1 311 dev/pci/if_tl.c return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)));
CSR_READ_1 368 dev/pci/if_tl.c f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
CSR_READ_1 383 dev/pci/if_tl.c f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
CSR_READ_1 211 dev/pci/if_vge.c if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE)
CSR_READ_1 253 dev/pci/if_vge.c dest[i] = CSR_READ_1(sc, VGE_PAR0 + i);
CSR_READ_1 266 dev/pci/if_vge.c if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)
CSR_READ_1 286 dev/pci/if_vge.c if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)
CSR_READ_1 303 dev/pci/if_vge.c if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0)
CSR_READ_1 318 dev/pci/if_vge.c if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F))
CSR_READ_1 334 dev/pci/if_vge.c if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0)
CSR_READ_1 355 dev/pci/if_vge.c if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F))
CSR_READ_1 373 dev/pci/if_vge.c if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0)
CSR_READ_1 440 dev/pci/if_vge.c if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0)
CSR_READ_1 542 dev/pci/if_vge.c if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0)
CSR_READ_1 558 dev/pci/if_vge.c if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0)
CSR_READ_1 113 dev/pci/if_vgevar.h CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
CSR_READ_1 120 dev/pci/if_vgevar.h CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
CSR_READ_1 156 dev/pci/if_vr.c CSR_READ_1(sc, reg) | (x))
CSR_READ_1 160 dev/pci/if_vr.c CSR_READ_1(sc, reg) & ~(x))
CSR_READ_1 180 dev/pci/if_vr.c CSR_READ_1(sc, VR_MIICMD) | (x))
CSR_READ_1 184 dev/pci/if_vr.c CSR_READ_1(sc, VR_MIICMD) & ~(x))
CSR_READ_1 328 dev/pci/if_vr.c CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
CSR_READ_1 336 dev/pci/if_vr.c if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0)
CSR_READ_1 408 dev/pci/if_vr.c CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
CSR_READ_1 418 dev/pci/if_vr.c if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0)
CSR_READ_1 502 dev/pci/if_vr.c rxfilt = CSR_READ_1(sc, VR_RXCFG);
CSR_READ_1 727 dev/pci/if_vr.c sc->arpcom.ac_enaddr[i] = CSR_READ_1(sc, VR_PAR0 + i);
CSR_READ_1 316 dev/sdmmc/sbt.c status = CSR_READ_1(sc, SBT_REG_ISTAT);