root/dev/pci/if_vge.c

DEFINITIONS

1. vge_eeprom_getword
2. vge_read_eeprom
3. vge_miipoll_stop
4. vge_miipoll_start
5. vge_miibus_readreg
6. vge_miibus_writereg
7. vge_cam_clear
8. vge_cam_set
9. vge_setmulti
10. vge_reset
11. vge_probe
12. vge_allocmem
13. vge_attach
14. vge_newbuf
15. vge_tx_list_init
16. vge_rx_list_init
17. vge_rxeof
18. vge_txeof
19. vge_tick
20. vge_intr
21. vge_encap
22. vge_start
23. vge_init
24. vge_ifmedia_upd
25. vge_ifmedia_sts
26. vge_miibus_statchg
27. vge_ioctl
28. vge_watchdog
29. vge_stop

    1 /*      $OpenBSD: if_vge.c,v 1.33 2007/05/01 11:28:06 canacar Exp $     */
    2 /*      $FreeBSD: if_vge.c,v 1.3 2004/09/11 22:13:25 wpaul Exp $        */
    3 /*
    4  * Copyright (c) 2004
    5  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. All advertising materials mentioning features or use of this software
   16  *    must display the following acknowledgement:
   17  *      This product includes software developed by Bill Paul.
   18  * 4. Neither the name of the author nor the names of any co-contributors
   19  *    may be used to endorse or promote products derived from this software
   20  *    without specific prior written permission.
   21  *
   22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   32  * THE POSSIBILITY OF SUCH DAMAGE.
   33  */
   35 /*
   36  * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver.
   37  *
   38  * Written by Bill Paul <wpaul@windriver.com>
   39  * Senior Networking Software Engineer
   40  * Wind River Systems
   41  *
   42  * Ported to OpenBSD by Peter Valchev <pvalchev@openbsd.org>
   43  */
   45 /*
   46  * The VIA Networking VT6122 is a 32bit, 33/66MHz PCI device that
   47  * combines a tri-speed ethernet MAC and PHY, with the following
   48  * features:
   49  *
   50  *      o Jumbo frame support up to 16K
   51  *      o Transmit and receive flow control
   52  *      o IPv4 checksum offload
   53  *      o VLAN tag insertion and stripping
   54  *      o TCP large send
   55  *      o 64-bit multicast hash table filter
   56  *      o 64 entry CAM filter
   57  *      o 16K RX FIFO and 48K TX FIFO memory
   58  *      o Interrupt moderation
   59  *
   60  * The VT6122 supports up to four transmit DMA queues. The descriptors
   61  * in the transmit ring can address up to 7 data fragments; frames which
   62  * span more than 7 data buffers must be coalesced, but in general the
   63  * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments
   64  * long. The receive descriptors address only a single buffer.
   65  *
   66  * There are two peculiar design issues with the VT6122. One is that
   67  * receive data buffers must be aligned on a 32-bit boundary. This is
   68  * not a problem where the VT6122 is used as a LOM device in x86-based
   69  * systems, but on architectures that generate unaligned access traps, we
   70  * have to do some copying.
   71  *
   72  * The other issue has to do with the way 64-bit addresses are handled.
   73  * The DMA descriptors only allow you to specify 48 bits of addressing
   74  * information. The remaining 16 bits are specified using one of the
   75  * I/O registers. If you only have a 32-bit system, then this isn't
   76  * an issue, but if you have a 64-bit system and more than 4GB of
   77  * memory, you must have to make sure your network data buffers reside
   78  * in the same 48-bit 'segment.'
   79  *
   80  * Special thanks to Ryan Fu at VIA Networking for providing documentation
   81  * and sample NICs for testing.
   82  */
   84 #include "bpfilter.h"
   85 #include "vlan.h"
   87 #include <sys/param.h>
   88 #include <sys/endian.h>
   89 #include <sys/systm.h>
   90 #include <sys/sockio.h>
   91 #include <sys/mbuf.h>
   92 #include <sys/malloc.h>
   93 #include <sys/kernel.h>
   94 #include <sys/device.h>
   95 #include <sys/timeout.h>
   96 #include <sys/socket.h>
   98 #include <net/if.h>
   99 #include <net/if_dl.h>
  100 #include <net/if_media.h>
  102 #ifdef INET
  103 #include <netinet/in.h>
  104 #include <netinet/in_systm.h>
  105 #include <netinet/in_var.h>
  106 #include <netinet/ip.h>
  107 #include <netinet/if_ether.h>
  108 #endif
  110 #if NVLAN > 0
  111 #include <net/if_types.h>
  112 #include <net/if_vlan_var.h>
  113 #endif
  115 #if NBPFILTER > 0
  116 #include <net/bpf.h>
  117 #endif
  119 #include <dev/mii/mii.h>
  120 #include <dev/mii/miivar.h>
  122 #include <dev/pci/pcireg.h>
  123 #include <dev/pci/pcivar.h>
  124 #include <dev/pci/pcidevs.h>
  126 #include <dev/pci/if_vgereg.h>
  127 #include <dev/pci/if_vgevar.h>
  129 int vge_probe           (struct device *, void *, void *);
  130 void vge_attach         (struct device *, struct device *, void *);
  132 int vge_encap           (struct vge_softc *, struct mbuf *, int);
  134 int vge_allocmem                (struct vge_softc *);
  135 int vge_newbuf          (struct vge_softc *, int, struct mbuf *);
  136 int vge_rx_list_init    (struct vge_softc *);
  137 int vge_tx_list_init    (struct vge_softc *);
  138 void vge_rxeof          (struct vge_softc *);
  139 void vge_txeof          (struct vge_softc *);
  140 int vge_intr            (void *);
  141 void vge_tick           (void *);
  142 void vge_start          (struct ifnet *);
  143 int vge_ioctl           (struct ifnet *, u_long, caddr_t);
  144 int vge_init            (struct ifnet *);
  145 void vge_stop           (struct vge_softc *);
  146 void vge_watchdog       (struct ifnet *);
  147 int vge_ifmedia_upd     (struct ifnet *);
  148 void vge_ifmedia_sts    (struct ifnet *, struct ifmediareq *);
  150 #ifdef VGE_EEPROM
  151 void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *);
  152 #endif
  153 void vge_read_eeprom    (struct vge_softc *, caddr_t, int, int, int);
  155 void vge_miipoll_start  (struct vge_softc *);
  156 void vge_miipoll_stop   (struct vge_softc *);
  157 int vge_miibus_readreg  (struct device *, int, int);
  158 void vge_miibus_writereg (struct device *, int, int, int);
  159 void vge_miibus_statchg (struct device *);
  161 void vge_cam_clear      (struct vge_softc *);
  162 int vge_cam_set         (struct vge_softc *, uint8_t *);
  163 void vge_setmulti       (struct vge_softc *);
  164 void vge_reset          (struct vge_softc *);
  166 struct cfattach vge_ca = {
  167         sizeof(struct vge_softc), vge_probe, vge_attach
  168 };
  170 struct cfdriver vge_cd = {
  171         0, "vge", DV_IFNET
  172 };
  174 #define VGE_PCI_LOIO             0x10
  175 #define VGE_PCI_LOMEM            0x14
  177 int vge_debug = 0;
  178 #define DPRINTF(x)      if (vge_debug) printf x
  179 #define DPRINTFN(n, x)  if (vge_debug >= (n)) printf x
  181 const struct pci_matchid vge_devices[] = {
  182         { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT612x },
  183 };
  185 #ifdef VGE_EEPROM
  186 /*
  187  * Read a word of data stored in the EEPROM at address 'addr.'
  188  */
  189 void
vge_eeprom_getword(struct vge_softc *sc, int addr, u_int16_t *dest)
  191 {
  192         int                     i;
u_int16_t               word = 0;
  195         /*
  196          * Enter EEPROM embedded programming mode. In order to
  197          * access the EEPROM at all, we first have to set the
  198          * EELOAD bit in the CHIPCFG2 register.
  199          */
CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD);
CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/);
  203         /* Select the address of the word we want to read */
CSR_WRITE_1(sc, VGE_EEADDR, addr);
  206         /* Issue read command */
CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD);
  209         /* Wait for the done bit to be set. */
  210         for (i = 0; i < VGE_TIMEOUT; i++) {
  211                 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE)
  212                         break;
  213         }
  215         if (i == VGE_TIMEOUT) {
printf("%s: EEPROM read timed out\n", sc->vge_dev.dv_xname);
  217                 *dest = 0;
  218                 return;
  219         }
  221         /* Read the result */
word = CSR_READ_2(sc, VGE_EERDDAT);
  224         /* Turn off EEPROM access mode. */
CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/);
CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD);
  228         *dest = word;
  229 }
  230 #endif
  232 /*
  233  * Read a sequence of words from the EEPROM.
  234  */
  235 void
vge_read_eeprom(struct vge_softc *sc, caddr_t dest, int off, int cnt,
  237     int swap)
  238 {
  239         int                     i;
  240 #ifdef VGE_EEPROM
u_int16_t               word = 0, *ptr;
  243         for (i = 0; i < cnt; i++) {
vge_eeprom_getword(sc, off + i, &word);
ptr = (u_int16_t *)(dest + (i * 2));
  246                 if (swap)
  247                         *ptr = ntohs(word);
  248                 else
  249                         *ptr = word;
  250         }
  251 #else
  252         for (i = 0; i < ETHER_ADDR_LEN; i++)
dest[i] = CSR_READ_1(sc, VGE_PAR0 + i);
  254 #endif
  255 }
  257 void
vge_miipoll_stop(struct vge_softc *sc)
  259 {
  260         int                     i;
CSR_WRITE_1(sc, VGE_MIICMD, 0);
  264         for (i = 0; i < VGE_TIMEOUT; i++) {
DELAY(1);
  266                 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)
  267                         break;
  268         }
  270         if (i == VGE_TIMEOUT)
printf("%s: failed to idle MII autopoll\n", sc->vge_dev.dv_xname);
  272 }
  274 void
vge_miipoll_start(struct vge_softc *sc)
  276 {
  277         int                     i;
  279         /* First, make sure we're idle. */
CSR_WRITE_1(sc, VGE_MIICMD, 0);
CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL);
  284         for (i = 0; i < VGE_TIMEOUT; i++) {
DELAY(1);
  286                 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)
  287                         break;
  288         }
  290         if (i == VGE_TIMEOUT) {
printf("%s: failed to idle MII autopoll\n", sc->vge_dev.dv_xname);
  292                 return;
  293         }
  295         /* Now enable auto poll mode. */
CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO);
  299         /* And make sure it started. */
  301         for (i = 0; i < VGE_TIMEOUT; i++) {
DELAY(1);
  303                 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0)
  304                         break;
  305         }
  307         if (i == VGE_TIMEOUT)
printf("%s: failed to start MII autopoll\n", sc->vge_dev.dv_xname);
  309 }
  311 int
vge_miibus_readreg(struct device *dev, int phy, int reg)
  313 {
  314         struct vge_softc        *sc = (struct vge_softc *)dev;
  315         int                     i, s;
u_int16_t               rval = 0;
  318         if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F))
  319                 return(0);
s = splnet();
vge_miipoll_stop(sc);
  325         /* Specify the register we want to read. */
CSR_WRITE_1(sc, VGE_MIIADDR, reg);
  328         /* Issue read command. */
CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD);
  331         /* Wait for the read command bit to self-clear. */
  332         for (i = 0; i < VGE_TIMEOUT; i++) {
DELAY(1);
  334                 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0)
  335                         break;
  336         }
  338         if (i == VGE_TIMEOUT)
printf("%s: MII read timed out\n", sc->vge_dev.dv_xname);
  340         else
rval = CSR_READ_2(sc, VGE_MIIDATA);
vge_miipoll_start(sc);
splx(s);
  346         return (rval);
  347 }
  349 void
vge_miibus_writereg(struct device *dev, int phy, int reg, int data)
  351 {
  352         struct vge_softc        *sc = (struct vge_softc *)dev;
  353         int                     i, s;
  355         if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F))
  356                 return;
s = splnet();
vge_miipoll_stop(sc);
  361         /* Specify the register we want to write. */
CSR_WRITE_1(sc, VGE_MIIADDR, reg);
  364         /* Specify the data we want to write. */
CSR_WRITE_2(sc, VGE_MIIDATA, data);
  367         /* Issue write command. */
CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD);
  370         /* Wait for the write command bit to self-clear. */
  371         for (i = 0; i < VGE_TIMEOUT; i++) {
DELAY(1);
  373                 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0)
  374                         break;
  375         }
  377         if (i == VGE_TIMEOUT) {
printf("%s: MII write timed out\n", sc->vge_dev.dv_xname);
  379         }
vge_miipoll_start(sc);
splx(s);
  383 }
  385 void
vge_cam_clear(struct vge_softc *sc)
  387 {
  388         int                     i;
  390         /*
  391          * Turn off all the mask bits. This tells the chip
  392          * that none of the entries in the CAM filter are valid.
  393          * desired entries will be enabled as we fill the filter in.
  394          */
CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK);
CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE);
  399         for (i = 0; i < 8; i++)
CSR_WRITE_1(sc, VGE_CAM0 + i, 0);
  402         /* Clear the VLAN filter too. */
CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0);
  405         for (i = 0; i < 8; i++)
CSR_WRITE_1(sc, VGE_CAM0 + i, 0);
CSR_WRITE_1(sc, VGE_CAMADDR, 0);
CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
sc->vge_camidx = 0;
  413 }
  415 int
vge_cam_set(struct vge_softc *sc, uint8_t *addr)
  417 {
  418         int                     i, error = 0;
  420         if (sc->vge_camidx == VGE_CAM_MAXADDRS)
  421                 return(ENOSPC);
  423         /* Select the CAM data page. */
CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA);
  427         /* Set the filter entry we want to update and enable writing. */
CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx);
  430         /* Write the address to the CAM registers */
  431         for (i = 0; i < ETHER_ADDR_LEN; i++)
CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]);
  434         /* Issue a write command. */
CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE);
  437         /* Wake for it to clear. */
  438         for (i = 0; i < VGE_TIMEOUT; i++) {
DELAY(1);
  440                 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0)
  441                         break;
  442         }
  444         if (i == VGE_TIMEOUT) {
printf("%s: setting CAM filter failed\n", sc->vge_dev.dv_xname);
error = EIO;
  447                 goto fail;
  448         }
  450         /* Select the CAM mask page. */
CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK);
  454         /* Set the mask bit that enables this filter. */
CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8),
  456             1<<(sc->vge_camidx & 7));
sc->vge_camidx++;
fail:
  461         /* Turn off access to CAM. */
CSR_WRITE_1(sc, VGE_CAMADDR, 0);
CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
  466         return (error);
  467 }
  469 /*
  470  * Program the multicast filter. We use the 64-entry CAM filter
  471  * for perfect filtering. If there's more than 64 multicast addresses,
  472  * we use the hash filter instead.
  473  */
  474 void
vge_setmulti(struct vge_softc *sc)
  476 {
  477         struct arpcom           *ac = &sc->arpcom;
  478         struct ifnet            *ifp = &ac->ac_if;
  479         struct ether_multi      *enm;
  480         struct ether_multistep  step;
  481         int                     error;
u_int32_t               h = 0, hashes[2] = { 0, 0 };
  484         /* First, zot all the multicast entries. */
vge_cam_clear(sc);
CSR_WRITE_4(sc, VGE_MAR0, 0);
CSR_WRITE_4(sc, VGE_MAR1, 0);
ifp->if_flags &= ~IFF_ALLMULTI;
  490         /*
  491          * If the user wants allmulti or promisc mode, enable reception
  492          * of all multicast frames.
  493          */
  494         if (ifp->if_flags & IFF_PROMISC) {
allmulti:
CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF);
CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF);
ifp->if_flags |= IFF_ALLMULTI;
  499                 return;
  500         }
  502         /* Now program new ones */
ETHER_FIRST_MULTI(step, ac, enm);
  504         while (enm != NULL) {
  505                 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN))
  506                         goto allmulti;
error = vge_cam_set(sc, enm->enm_addrlo);
  509                 if (error)
  510                         break;
ETHER_NEXT_MULTI(step, enm);
  513         }
  515         /* If there were too many addresses, use the hash filter. */
  516         if (error) {
vge_cam_clear(sc);
ETHER_FIRST_MULTI(step, ac, enm);
  520                 while (enm != NULL) {
h = ether_crc32_be(enm->enm_addrlo,
ETHER_ADDR_LEN) >> 26;
hashes[h >> 5] |= 1 << (h & 0x1f);
ETHER_NEXT_MULTI(step, enm);
  526                 }
CSR_WRITE_4(sc, VGE_MAR0, hashes[0]);
CSR_WRITE_4(sc, VGE_MAR1, hashes[1]);
  530         }
  531 }
  533 void
vge_reset(struct vge_softc *sc)
  535 {
  536         int                     i;
CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET);
  540         for (i = 0; i < VGE_TIMEOUT; i++) {
DELAY(5);
  542                 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0)
  543                         break;
  544         }
  546         if (i == VGE_TIMEOUT) {
printf("%s: soft reset timed out", sc->vge_dev.dv_xname);
CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE);
DELAY(2000);
  550         }
DELAY(5000);
CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD);
  556         for (i = 0; i < VGE_TIMEOUT; i++) {
DELAY(5);
  558                 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0)
  559                         break;
  560         }
  562         if (i == VGE_TIMEOUT) {
printf("%s: EEPROM reload timed out\n", sc->vge_dev.dv_xname);
  564                 return;
  565         }
CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI);
  568 }
  570 /*
  571  * Probe for a VIA gigabit chip. Check the PCI vendor and device
  572  * IDs against our list and return a device name if we find a match.
  573  */
  574 int
vge_probe(struct device *dev, void *match, void *aux)
  576 {
  577         return (pci_matchbyid((struct pci_attach_args *)aux, vge_devices,
  578             sizeof(vge_devices)/sizeof(vge_devices[0])));
  579 }
  581 /*
  582  * Allocate memory for RX/TX rings
  583  */
  584 int
vge_allocmem(struct vge_softc *sc)
  586 {
  587         int                     nseg, rseg;
  588         int                     i, error;
nseg = 32;
  592         /* Allocate DMA'able memory for the TX ring */
error = bus_dmamap_create(sc->sc_dmat, VGE_TX_LIST_SZ, 1,
VGE_TX_LIST_SZ, 0, BUS_DMA_ALLOCNOW,
  596             &sc->vge_ldata.vge_tx_list_map);
  597         if (error)
  598                 return (ENOMEM);
error = bus_dmamem_alloc(sc->sc_dmat, VGE_TX_LIST_SZ,
ETHER_ALIGN, 0,
  601             &sc->vge_ldata.vge_tx_listseg, 1, &rseg, BUS_DMA_NOWAIT);
  602         if (error) {
printf("%s: can't alloc TX list\n", sc->vge_dev.dv_xname);
  604                 return (ENOMEM);
  605         }
  607         /* Load the map for the TX ring. */
error = bus_dmamem_map(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg,
  609              1, VGE_TX_LIST_SZ,
  610              (caddr_t *)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT);
memset(sc->vge_ldata.vge_tx_list, 0, VGE_TX_LIST_SZ);
  612         if (error) {
printf("%s: can't map TX dma buffers\n",
sc->vge_dev.dv_xname);
bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, rseg);
  616                 return (ENOMEM);
  617         }
error = bus_dmamap_load(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map,
sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ, NULL, BUS_DMA_NOWAIT);
  621         if (error) {
printf("%s: can't load TX dma map\n", sc->vge_dev.dv_xname);
bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map);
bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_tx_list,
VGE_TX_LIST_SZ);
bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, rseg);
  627                 return (ENOMEM);
  628         }
  630         /* Create DMA maps for TX buffers */
  632         for (i = 0; i < VGE_TX_DESC_CNT; i++) {
error = bus_dmamap_create(sc->sc_dmat, MCLBYTES * nseg, nseg,
MCLBYTES, 0, BUS_DMA_ALLOCNOW,
  635                     &sc->vge_ldata.vge_tx_dmamap[i]);
  636                 if (error) {
printf("%s: can't create DMA map for TX\n",
sc->vge_dev.dv_xname);
  639                         return (ENOMEM);
  640                 }
  641         }
  643         /* Allocate DMA'able memory for the RX ring */
error = bus_dmamap_create(sc->sc_dmat, VGE_RX_LIST_SZ, 1,
VGE_RX_LIST_SZ, 0, BUS_DMA_ALLOCNOW,
  647             &sc->vge_ldata.vge_rx_list_map);
  648         if (error)
  649                 return (ENOMEM);
error = bus_dmamem_alloc(sc->sc_dmat, VGE_RX_LIST_SZ, VGE_RING_ALIGN,
  651             0, &sc->vge_ldata.vge_rx_listseg, 1, &rseg, BUS_DMA_NOWAIT);
  652         if (error) {
printf("%s: can't alloc RX list\n", sc->vge_dev.dv_xname);
  654                 return (ENOMEM);
  655         }
  657         /* Load the map for the RX ring. */
error = bus_dmamem_map(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg,
  660              1, VGE_RX_LIST_SZ,
  661              (caddr_t *)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT);
memset(sc->vge_ldata.vge_rx_list, 0, VGE_RX_LIST_SZ);
  663         if (error) {
printf("%s: can't map RX dma buffers\n",
sc->vge_dev.dv_xname);
bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, rseg);
  667                 return (ENOMEM);
  668         }
error = bus_dmamap_load(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map,
sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ, NULL, BUS_DMA_NOWAIT);
  671         if (error) {
printf("%s: can't load RX dma map\n", sc->vge_dev.dv_xname);
bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map);
bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_rx_list,
VGE_RX_LIST_SZ);
bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, rseg);
  677                 return (ENOMEM);
  678         }
  680         /* Create DMA maps for RX buffers */
  682         for (i = 0; i < VGE_RX_DESC_CNT; i++) {
error = bus_dmamap_create(sc->sc_dmat, MCLBYTES * nseg, nseg,
MCLBYTES, 0, BUS_DMA_ALLOCNOW,
  685                     &sc->vge_ldata.vge_rx_dmamap[i]);
  686                 if (error) {
printf("%s: can't create DMA map for RX\n",
sc->vge_dev.dv_xname);
  689                         return (ENOMEM);
  690                 }
  691         }
  693         return (0);
  694 }
  696 /*
  697  * Attach the interface. Allocate softc structures, do ifmedia
  698  * setup and ethernet/BPF attach.
  699  */
  700 void
vge_attach(struct device *parent, struct device *self, void *aux)
  702 {
u_char                  eaddr[ETHER_ADDR_LEN];
u_int16_t               as[3];
  705         struct vge_softc        *sc = (struct vge_softc *)self;
  706         struct pci_attach_args  *pa = aux;
pci_chipset_tag_t       pc = pa->pa_pc;
pci_intr_handle_t       ih;
  709         const char              *intrstr = NULL;
  710         struct ifnet            *ifp;
  711         int                     error = 0, i;
bus_size_t              iosize;
  714         /*
  715          * Map control/status registers.
  716          */
  717         if (pci_mapreg_map(pa, VGE_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0,
  718             &sc->vge_btag, &sc->vge_bhandle, NULL, &iosize, 0)) {
  719                 if (pci_mapreg_map(pa, VGE_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0,
  720                     &sc->vge_btag, &sc->vge_bhandle, NULL, &iosize, 0)) {
printf(": can't map mem or i/o space\n");
  722                         return;
  723                 }
  724         }
  726         /* Allocate interrupt */
  727         if (pci_intr_map(pa, &ih)) {
printf(": couldn't map interrupt\n");
  729                 return;
  730         }
intrstr = pci_intr_string(pc, ih);
sc->vge_intrhand = pci_intr_establish(pc, ih, IPL_NET, vge_intr, sc,
sc->vge_dev.dv_xname);
  734         if (sc->vge_intrhand == NULL) {
printf(": couldn't establish interrupt");
  736                 if (intrstr != NULL)
printf(" at %s", intrstr);
  738                 return;
  739         }
printf(": %s", intrstr);
sc->sc_dmat = pa->pa_dmat;
  744         /* Reset the adapter. */
vge_reset(sc);
  747         /*
  748          * Get station address from the EEPROM.
  749          */
vge_read_eeprom(sc, (caddr_t)as, VGE_EE_EADDR, 3, 0);
  751         for (i = 0; i < 3; i++) {
eaddr[(i * 2) + 0] = as[i] & 0xff;
eaddr[(i * 2) + 1] = as[i] >> 8;
  754         }
bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
printf(", address %s\n",
ether_sprintf(sc->arpcom.ac_enaddr));
error = vge_allocmem(sc);
  763         if (error)
  764                 return;
ifp = &sc->arpcom.ac_if;
ifp->if_softc = sc;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_ioctl = vge_ioctl;
ifp->if_start = vge_start;
ifp->if_watchdog = vge_watchdog;
ifp->if_init = vge_init;
ifp->if_baudrate = 1000000000;
  774 #ifdef VGE_JUMBO
ifp->if_hardmtu = VGE_JUMBO_MTU;
  776 #endif
IFQ_SET_MAXLEN(&ifp->if_snd, VGE_IFQ_MAXLEN);
IFQ_SET_READY(&ifp->if_snd);
ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_CSUM_IPv4 |
IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4;
  783 #ifdef VGE_VLAN
ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
  785 #endif
  787         /* Set interface name */
strlcpy(ifp->if_xname, sc->vge_dev.dv_xname, IFNAMSIZ);
  790         /* Do MII setup */
sc->sc_mii.mii_ifp = ifp;
sc->sc_mii.mii_readreg = vge_miibus_readreg;
sc->sc_mii.mii_writereg = vge_miibus_writereg;
sc->sc_mii.mii_statchg = vge_miibus_statchg;
ifmedia_init(&sc->sc_mii.mii_media, 0,
vge_ifmedia_upd, vge_ifmedia_sts);
mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
MII_OFFSET_ANY, 0);
  799         if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
printf("%s: no PHY found!\n", sc->vge_dev.dv_xname);
ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL,
  802                     0, NULL);
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL);
  804         } else
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
timeout_set(&sc->timer_handle, vge_tick, sc);
  809         /*
  810          * Call MI attach routine.
  811          */
if_attach(ifp);
ether_ifattach(ifp);
  814 }
  816 int
vge_newbuf(struct vge_softc *sc, int idx, struct mbuf *m)
  818 {
  819         struct mbuf             *m_new = NULL;
  820         struct vge_rx_desc      *r;
bus_dmamap_t            rxmap = sc->vge_ldata.vge_rx_dmamap[idx];
  822         int                     i;
  824         if (m == NULL) {
  825                 /* Allocate a new mbuf */
MGETHDR(m_new, M_DONTWAIT, MT_DATA);
  827                 if (m_new == NULL)
  828                         return (ENOBUFS);
  830                 /* Allocate a cluster */
MCLGET(m_new, M_DONTWAIT);
  832                 if (!(m_new->m_flags & M_EXT)) {
m_freem(m_new);
  834                         return (ENOBUFS);
  835                 }
  836         } else
m_new->m_data = m_new->m_ext.ext_buf;
m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
  840         /* Fix-up alignment so payload is doubleword-aligned */
  841         /* XXX m_adj(m_new, ETHER_ALIGN); */
  843         if (bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m_new, BUS_DMA_NOWAIT))
  844                 return (ENOBUFS);
  846         if (rxmap->dm_nsegs > 1)
  847                 goto out;
  849         /* Map the segments into RX descriptors */
r = &sc->vge_ldata.vge_rx_list[idx];
  852         if (letoh32(r->vge_sts) & VGE_RDSTS_OWN) {
printf("%s: tried to map a busy RX descriptor\n",
sc->vge_dev.dv_xname);
  855                 goto out;
  856         }
r->vge_buflen = htole16(VGE_BUFLEN(rxmap->dm_segs[0].ds_len) | VGE_RXDESC_I);
r->vge_addrlo = htole32(VGE_ADDR_LO(rxmap->dm_segs[0].ds_addr));
r->vge_addrhi = htole16(VGE_ADDR_HI(rxmap->dm_segs[0].ds_addr) & 0xFFFF);
r->vge_sts = htole32(0);
r->vge_ctl = htole32(0);
  863         /*
  864          * Note: the manual fails to document the fact that for
  865          * proper operation, the driver needs to replenish the RX
  866          * DMA ring 4 descriptors at a time (rather than one at a
  867          * time, like most chips). We can allocate the new buffers
  868          * but we should not set the OWN bits until we're ready
  869          * to hand back 4 of them in one shot.
  870          */
  871 #define VGE_RXCHUNK 4
sc->vge_rx_consumed++;
  873         if (sc->vge_rx_consumed == VGE_RXCHUNK) {
  874                 for (i = idx; i != idx - sc->vge_rx_consumed; i--)
sc->vge_ldata.vge_rx_list[i].vge_sts |=
htole32(VGE_RDSTS_OWN);
sc->vge_rx_consumed = 0;
  878         }
sc->vge_ldata.vge_rx_mbuf[idx] = m_new;
bus_dmamap_sync(sc->sc_dmat, rxmap, 0,
rxmap->dm_mapsize, BUS_DMASYNC_PREREAD);
  885         return (0);
out:
DPRINTF(("vge_newbuf: out of memory\n"));
  888         if (m_new != NULL)
m_freem(m_new);
  890         return (ENOMEM);
  891 }
  893 int
vge_tx_list_init(struct vge_softc *sc)
  895 {
bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ);
bzero ((char *)&sc->vge_ldata.vge_tx_mbuf,
  898             (VGE_TX_DESC_CNT * sizeof(struct mbuf *)));
bus_dmamap_sync(sc->sc_dmat,
sc->vge_ldata.vge_tx_list_map, 0,
sc->vge_ldata.vge_tx_list_map->dm_mapsize,
BUS_DMASYNC_PREWRITE);
sc->vge_ldata.vge_tx_prodidx = 0;
sc->vge_ldata.vge_tx_considx = 0;
sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT;
  908         return (0);
  909 }
  911 /* Init RX descriptors and allocate mbufs with vge_newbuf()
  912  * A ring is used, and last descriptor points to first. */
  913 int
vge_rx_list_init(struct vge_softc *sc)
  915 {
  916         int                     i;
bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ);
bzero ((char *)&sc->vge_ldata.vge_rx_mbuf,
  920             (VGE_RX_DESC_CNT * sizeof(struct mbuf *)));
sc->vge_rx_consumed = 0;
  924         for (i = 0; i < VGE_RX_DESC_CNT; i++) {
  925                 if (vge_newbuf(sc, i, NULL) == ENOBUFS)
  926                         return (ENOBUFS);
  927         }
  929         /* Flush the RX descriptors */
bus_dmamap_sync(sc->sc_dmat,
sc->vge_ldata.vge_rx_list_map,
  933             0, sc->vge_ldata.vge_rx_list_map->dm_mapsize,
BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
sc->vge_ldata.vge_rx_prodidx = 0;
sc->vge_rx_consumed = 0;
sc->vge_head = sc->vge_tail = NULL;
  940         return (0);
  941 }
  943 /*
  944  * RX handler. We support the reception of jumbo frames that have
  945  * been fragmented across multiple 2K mbuf cluster buffers.
  946  */
  947 void
vge_rxeof(struct vge_softc *sc)
  949 {
  950         struct mbuf             *m;
  951         struct ifnet            *ifp;
  952         int                     i, total_len;
  953         int                     lim = 0;
  954         struct vge_rx_desc      *cur_rx;
u_int32_t               rxstat, rxctl;
ifp = &sc->arpcom.ac_if;
i = sc->vge_ldata.vge_rx_prodidx;
  960         /* Invalidate the descriptor memory */
bus_dmamap_sync(sc->sc_dmat,
sc->vge_ldata.vge_rx_list_map,
  964             0, sc->vge_ldata.vge_rx_list_map->dm_mapsize,
BUS_DMASYNC_POSTREAD);
  967         while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) {
  968                 struct mbuf *m0 = NULL;
cur_rx = &sc->vge_ldata.vge_rx_list[i];
m = sc->vge_ldata.vge_rx_mbuf[i];
total_len = VGE_RXBYTES(cur_rx);
rxstat = letoh32(cur_rx->vge_sts);
rxctl = letoh32(cur_rx->vge_ctl);
  976                 /* Invalidate the RX mbuf and unload its map */
bus_dmamap_sync(sc->sc_dmat,
sc->vge_ldata.vge_rx_dmamap[i],
  980                     0, sc->vge_ldata.vge_rx_dmamap[i]->dm_mapsize,
BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->sc_dmat,
sc->vge_ldata.vge_rx_dmamap[i]);
  985                 /*
  986                  * If the 'start of frame' bit is set, this indicates
  987                  * either the first fragment in a multi-fragment receive,
  988                  * or an intermediate fragment. Either way, we want to
  989                  * accumulate the buffers.
  990                  */
  991                 if (rxstat & VGE_RXPKT_SOF) {
DPRINTF(("vge_rxeof: SOF\n"));
m->m_len = MCLBYTES;
  994                         if (sc->vge_head == NULL)
sc->vge_head = sc->vge_tail = m;
  996                         else {
m->m_flags &= ~M_PKTHDR;
sc->vge_tail->m_next = m;
sc->vge_tail = m;
 1000                         }
vge_newbuf(sc, i, NULL);
VGE_RX_DESC_INC(i);
 1003                         continue;
 1004                 }
 1006                 /*
 1007                  * Bad/error frames will have the RXOK bit cleared.
 1008                  * However, there's one error case we want to allow:
 1009                  * if a VLAN tagged frame arrives and the chip can't
 1010                  * match it against the CAM filter, it considers this
 1011                  * a 'VLAN CAM filter miss' and clears the 'RXOK' bit.
 1012                  * We don't want to drop the frame though: our VLAN
 1013                  * filtering is done in software.
 1014                  */
 1015                 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM)
 1016                     && !(rxstat & VGE_RDSTS_CSUMERR)) {
ifp->if_ierrors++;
 1018                         /*
 1019                          * If this is part of a multi-fragment packet,
 1020                          * discard all the pieces.
 1021                          */
 1022                         if (sc->vge_head != NULL) {
m_freem(sc->vge_head);
sc->vge_head = sc->vge_tail = NULL;
 1025                         }
vge_newbuf(sc, i, m);
VGE_RX_DESC_INC(i);
 1028                         continue;
 1029                 }
 1031                 /*
 1032                  * If allocating a replacement mbuf fails,
 1033                  * reload the current one.
 1034                  */
 1036                 if (vge_newbuf(sc, i, NULL) == ENOBUFS) {
 1037                         if (sc->vge_head != NULL) {
m_freem(sc->vge_head);
sc->vge_head = sc->vge_tail = NULL;
 1040                         }
m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
total_len - ETHER_CRC_LEN + ETHER_ALIGN,
 1044                             0, ifp, NULL);
vge_newbuf(sc, i, m);
 1046                         if (m0 == NULL) {
ifp->if_ierrors++;
 1048                                 continue;
 1049                         }
m_adj(m0, ETHER_ALIGN);
m = m0;
VGE_RX_DESC_INC(i);
 1054                         continue;
 1055                 }
VGE_RX_DESC_INC(i);
 1059                 if (sc->vge_head != NULL) {
m->m_len = total_len % MCLBYTES;
 1061                         /*
 1062                          * Special case: if there's 4 bytes or less
 1063                          * in this buffer, the mbuf can be discarded:
 1064                          * the last 4 bytes is the CRC, which we don't
 1065                          * care about anyway.
 1066                          */
 1067                         if (m->m_len <= ETHER_CRC_LEN) {
sc->vge_tail->m_len -=
 1069                                     (ETHER_CRC_LEN - m->m_len);
m_freem(m);
 1071                         } else {
m->m_len -= ETHER_CRC_LEN;
m->m_flags &= ~M_PKTHDR;
sc->vge_tail->m_next = m;
 1075                         }
m = sc->vge_head;
sc->vge_head = sc->vge_tail = NULL;
m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
 1079                 } else
m->m_pkthdr.len = m->m_len =
 1081                             (total_len - ETHER_CRC_LEN);
 1083 #ifdef __STRICT_ALIGNMENT
bcopy(m->m_data, m->m_data + ETHER_ALIGN,
total_len);
m->m_data += ETHER_ALIGN;
 1087 #endif
ifp->if_ipackets++;
m->m_pkthdr.rcvif = ifp;
 1091                 /* Do RX checksumming */
 1093                 /* Check IP header checksum */
 1094                 if ((rxctl & VGE_RDCTL_IPPKT) &&
 1095                     (rxctl & VGE_RDCTL_IPCSUMOK))
m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK;
 1098                 /* Check TCP/UDP checksum */
 1099                 if ((rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT)) &&
 1100                     (rxctl & VGE_RDCTL_PROTOCSUMOK))
m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK;
 1103 #if NBPFILTER > 0
 1104                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN);
 1106 #endif
ether_input_mbuf(ifp, m);
lim++;
 1110                 if (lim == VGE_RX_DESC_CNT)
 1111                         break;
 1112         }
 1114         /* Flush the RX DMA ring */
bus_dmamap_sync(sc->sc_dmat,
sc->vge_ldata.vge_rx_list_map,
 1117             0, sc->vge_ldata.vge_rx_list_map->dm_mapsize,
BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
sc->vge_ldata.vge_rx_prodidx = i;
CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim);
 1122 }
 1124 void
vge_txeof(struct vge_softc *sc)
 1126 {
 1127         struct ifnet            *ifp;
u_int32_t               txstat;
 1129         int                     idx;
ifp = &sc->arpcom.ac_if;
idx = sc->vge_ldata.vge_tx_considx;
 1134         /* Invalidate the TX descriptor list */
bus_dmamap_sync(sc->sc_dmat,
sc->vge_ldata.vge_tx_list_map,
 1138             0, sc->vge_ldata.vge_tx_list_map->dm_mapsize,
BUS_DMASYNC_POSTREAD);
 1141         /* Transmitted frames can be now free'd from the TX list */
 1142         while (idx != sc->vge_ldata.vge_tx_prodidx) {
txstat = letoh32(sc->vge_ldata.vge_tx_list[idx].vge_sts);
 1144                 if (txstat & VGE_TDSTS_OWN)
 1145                         break;
m_freem(sc->vge_ldata.vge_tx_mbuf[idx]);
sc->vge_ldata.vge_tx_mbuf[idx] = NULL;
bus_dmamap_unload(sc->sc_dmat,
sc->vge_ldata.vge_tx_dmamap[idx]);
 1151                 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL))
ifp->if_collisions++;
 1153                 if (txstat & VGE_TDSTS_TXERR)
ifp->if_oerrors++;
 1155                 else
ifp->if_opackets++;
sc->vge_ldata.vge_tx_free++;
VGE_TX_DESC_INC(idx);
 1160         }
 1162         /* No changes made to the TX ring, so no flush needed */
 1164         if (idx != sc->vge_ldata.vge_tx_considx) {
sc->vge_ldata.vge_tx_considx = idx;
ifp->if_flags &= ~IFF_OACTIVE;
ifp->if_timer = 0;
 1168         }
 1170         /*
 1171          * If not all descriptors have been released reaped yet,
 1172          * reload the timer so that we will eventually get another
 1173          * interrupt that will cause us to re-enter this routine.
 1174          * This is done in case the transmitter has gone idle.
 1175          */
 1176         if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT)
CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE);
 1178 }
 1180 void
vge_tick(void *xsc)
 1182 {
 1183         struct vge_softc        *sc = xsc;
 1184         struct ifnet            *ifp = &sc->arpcom.ac_if;
 1185         struct mii_data         *mii = &sc->sc_mii;
 1186         int s;
s = splnet();
mii_tick(mii);
 1192         if (sc->vge_link) {
 1193                 if (!(mii->mii_media_status & IFM_ACTIVE)) {
sc->vge_link = 0;
ifp->if_link_state = LINK_STATE_DOWN;
if_link_state_change(ifp);
 1197                 }
 1198         } else {
 1199                 if (mii->mii_media_status & IFM_ACTIVE &&
IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
sc->vge_link = 1;
 1202                         if (mii->mii_media_status & IFM_FDX)
ifp->if_link_state = LINK_STATE_FULL_DUPLEX;
 1204                         else if (mii->mii_media_status & IFM_HDX)
ifp->if_link_state = LINK_STATE_HALF_DUPLEX;
 1206                         else
ifp->if_link_state = LINK_STATE_UP;
if_link_state_change(ifp);
 1209                         if (!IFQ_IS_EMPTY(&ifp->if_snd))
vge_start(ifp);
 1211                 }
 1212         }
timeout_add(&sc->timer_handle, hz);
splx(s);
 1215 }
 1217 int
vge_intr(void *arg)
 1219 {
 1220         struct vge_softc        *sc = arg;
 1221         struct ifnet            *ifp;
u_int32_t               status;
 1223         int                     claimed = 0;
ifp = &sc->arpcom.ac_if;
 1227         if (!(ifp->if_flags & IFF_UP))
 1228                 return 0;
 1230         /* Disable interrupts */
CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);
 1233         for (;;) {
status = CSR_READ_4(sc, VGE_ISR);
DPRINTFN(3, ("vge_intr: status=%#x\n", status));
 1237                 /* If the card has gone away the read returns 0xffffffff. */
 1238                 if (status == 0xFFFFFFFF)
 1239                         break;
 1241                 if (status) {
CSR_WRITE_4(sc, VGE_ISR, status);
 1243                 }
 1245                 if ((status & VGE_INTRS) == 0)
 1246                         break;
claimed = 1;
 1250                 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO))
vge_rxeof(sc);
 1253                 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) {
DPRINTFN(2, ("vge_intr: RX error, recovering\n"));
vge_rxeof(sc);
CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);
CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);
 1258                 }
 1260                 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0))
vge_txeof(sc);
 1263                 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) {
DPRINTFN(2, ("DMA_STALL\n"));
vge_init(ifp);
 1266                 }
 1268                 if (status & VGE_ISR_LINKSTS) {
timeout_del(&sc->timer_handle);
vge_tick(sc);
 1271                 }
 1272         }
 1274         /* Re-enable interrupts */
CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);
 1277         if (!IFQ_IS_EMPTY(&ifp->if_snd))
vge_start(ifp);
 1280         return (claimed);
 1281 }
 1283 /*
 1284  * Encapsulate an mbuf chain into the TX ring by combining it w/
 1285  * the descriptors.
 1286  */
 1287 int
vge_encap(struct vge_softc *sc, struct mbuf *m_head, int idx)
 1289 {
 1290         struct ifnet            *ifp = &sc->arpcom.ac_if;
bus_dmamap_t            txmap;
 1292         struct vge_tx_desc      *d = NULL;
 1293         struct vge_tx_frag      *f;
 1294         struct mbuf             *mnew = NULL;
 1295         int                     error, frag;
u_int32_t               vge_flags;
 1297 #if NVLAN > 0
 1298         struct ifvlan           *ifv = NULL;
 1300         if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
m_head->m_pkthdr.rcvif != NULL)
ifv = m_head->m_pkthdr.rcvif->if_softc;
 1303 #endif
vge_flags = 0;
 1307         if (m_head->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT)
vge_flags |= VGE_TDCTL_IPCSUM;
 1309         if (m_head->m_pkthdr.csum_flags & M_TCPV4_CSUM_OUT)
vge_flags |= VGE_TDCTL_TCPCSUM;
 1311         if (m_head->m_pkthdr.csum_flags & M_UDPV4_CSUM_OUT)
vge_flags |= VGE_TDCTL_UDPCSUM;
txmap = sc->vge_ldata.vge_tx_dmamap[idx];
repack:
error = bus_dmamap_load_mbuf(sc->sc_dmat, txmap,
m_head, BUS_DMA_NOWAIT);
 1318         if (error) {
printf("%s: can't map mbuf (error %d)\n",
sc->vge_dev.dv_xname, error);
 1321                 return (ENOBUFS);
 1322         }
d = &sc->vge_ldata.vge_tx_list[idx];
 1325         /* If owned by chip, fail */
 1326         if (letoh32(d->vge_sts) & VGE_TDSTS_OWN)
 1327                 return (ENOBUFS);
 1329         for (frag = 0; frag < txmap->dm_nsegs; frag++) {
 1330                 /* Check if we have used all 7 fragments. */
 1331                 if (frag == VGE_TX_FRAGS)
 1332                         break;
f = &d->vge_frag[frag];
f->vge_buflen = htole16(VGE_BUFLEN(txmap->dm_segs[frag].ds_len));
f->vge_addrlo = htole32(VGE_ADDR_LO(txmap->dm_segs[frag].ds_addr));
f->vge_addrhi = htole16(VGE_ADDR_HI(txmap->dm_segs[frag].ds_addr) & 0xFFFF);
 1337         }
 1339         /*
 1340          * We used up all 7 fragments!  Now what we have to do is
 1341          * copy the data into a mbuf cluster and map that.
 1342          */
 1343         if (frag == VGE_TX_FRAGS) {
MGETHDR(mnew, M_DONTWAIT, MT_DATA);
 1345                 if (mnew == NULL)
 1346                         return (ENOBUFS);
 1348                 if (m_head->m_pkthdr.len > MHLEN) {
MCLGET(mnew, M_DONTWAIT);
 1350                         if (!(mnew->m_flags & M_EXT)) {
m_freem(mnew);
 1352                                 return (ENOBUFS);
 1353                         }
 1354                 }
m_copydata(m_head, 0, m_head->m_pkthdr.len,
mtod(mnew, caddr_t));
mnew->m_pkthdr.len = mnew->m_len = m_head->m_pkthdr.len;
IFQ_DEQUEUE(&ifp->if_snd, m_head);
m_freem(m_head);
m_head = mnew;
 1361                 goto repack;
 1362         }
 1364         /* This chip does not do auto-padding */
 1365         if (m_head->m_pkthdr.len < VGE_MIN_FRAMELEN) {
f = &d->vge_frag[frag];
f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN -
m_head->m_pkthdr.len));
f->vge_addrlo = htole32(VGE_ADDR_LO(txmap->dm_segs[0].ds_addr));
f->vge_addrhi = htole16(VGE_ADDR_HI(txmap->dm_segs[0].ds_addr) & 0xFFFF);
m_head->m_pkthdr.len = VGE_MIN_FRAMELEN;
frag++;
 1374         }
 1375         /* For some reason, we need to tell the card fragment + 1 */
frag++;
bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize,
BUS_DMASYNC_PREWRITE);
d->vge_sts = htole32(m_head->m_pkthdr.len << 16);
d->vge_ctl = htole32(vge_flags|(frag << 28) | VGE_TD_LS_NORM);
 1384         if (m_head->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN)
d->vge_ctl |= htole32(VGE_TDCTL_JUMBO);
sc->vge_ldata.vge_tx_dmamap[idx] = txmap;
sc->vge_ldata.vge_tx_mbuf[idx] = m_head;
sc->vge_ldata.vge_tx_free--;
sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN);
 1392         /*
 1393          * Set up hardware VLAN tagging.
 1394          */
 1395 #if NVLAN > 0
 1396         if (ifv != NULL) {
sc->vge_ldata.vge_tx_list[idx].vge_ctl |=
htole32(htons(ifv->ifv_tag) | VGE_TDCTL_VTAG);
 1399         }
 1400 #endif
idx++;
 1403         if (mnew == NULL) {
 1404                 /* if mbuf is coalesced, it is already dequeued */
IFQ_DEQUEUE(&ifp->if_snd, m_head);
 1406         }
 1407         return (0);
 1408 }
 1410 /*
 1411  * Main transmit routine.
 1412  */
 1413 void
vge_start(struct ifnet *ifp)
 1415 {
 1416         struct vge_softc        *sc;
 1417         struct mbuf             *m_head = NULL;
 1418         int                     idx, pidx = 0;
sc = ifp->if_softc;
 1422         if (!sc->vge_link || ifp->if_flags & IFF_OACTIVE)
 1423                 return;
 1425         if (IFQ_IS_EMPTY(&ifp->if_snd))
 1426                 return;
idx = sc->vge_ldata.vge_tx_prodidx;
pidx = idx - 1;
 1431         if (pidx < 0)
pidx = VGE_TX_DESC_CNT - 1;
 1434         while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) {
IFQ_POLL(&ifp->if_snd, m_head);
 1436                 if (m_head == NULL)
 1437                         break;
 1439                 /*
 1440                  * If there's a BPF listener, bounce a copy of this frame
 1441                  * to him.
 1442                  */
 1443 #if NBPFILTER > 0
 1444                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT);
 1446 #endif
 1448                 if (vge_encap(sc, m_head, idx)) {
ifp->if_flags |= IFF_OACTIVE;
 1450                         break;
 1451                 }
sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |=
htole16(VGE_TXDESC_Q);
pidx = idx;
VGE_TX_DESC_INC(idx);
 1458         }
 1460         if (idx == sc->vge_ldata.vge_tx_prodidx) {
 1461                 return;
 1462         }
 1464         /* Flush the TX descriptors */
bus_dmamap_sync(sc->sc_dmat,
sc->vge_ldata.vge_tx_list_map,
 1468             0, sc->vge_ldata.vge_tx_list_map->dm_mapsize,
BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
 1471         /* Issue a transmit command. */
CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0);
sc->vge_ldata.vge_tx_prodidx = idx;
 1476         /*
 1477          * Use the countdown timer for interrupt moderation.
 1478          * 'TX done' interrupts are disabled. Instead, we reset the
 1479          * countdown timer, which will begin counting until it hits
 1480          * the value in the SSTIMER register, and then trigger an
 1481          * interrupt. Each time we set the TIMER0_ENABLE bit, the
 1482          * the timer count is reloaded. Only when the transmitter
 1483          * is idle will the timer hit 0 and an interrupt fire.
 1484          */
CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE);
 1487         /*
 1488          * Set a timeout in case the chip goes out to lunch.
 1489          */
ifp->if_timer = 5;
 1491 }
 1493 int
vge_init(struct ifnet *ifp)
 1495 {
 1496         struct vge_softc        *sc = ifp->if_softc;
 1497         int                     i;
 1499         /*
 1500          * Cancel pending I/O and free all RX/TX buffers.
 1501          */
vge_stop(sc);
vge_reset(sc);
 1505         /* Initialize RX descriptors list */
 1506         if (vge_rx_list_init(sc) == ENOBUFS) {
printf("%s: init failed: no memory for RX buffers\n",
sc->vge_dev.dv_xname);
vge_stop(sc);
 1510                 return (ENOBUFS);
 1511         }
 1512         /* Initialize TX descriptors */
 1513         if (vge_tx_list_init(sc) == ENOBUFS) {
printf("%s: init failed: no memory for TX buffers\n",
sc->vge_dev.dv_xname);
vge_stop(sc);
 1517                 return (ENOBUFS);
 1518         }
 1520         /* Set our station address */
 1521         for (i = 0; i < ETHER_ADDR_LEN; i++)
CSR_WRITE_1(sc, VGE_PAR0 + i, sc->arpcom.ac_enaddr[i]);
 1524         /*
 1525          * Set receive FIFO threshold. Also allow transmission and
 1526          * reception of VLAN tagged frames.
 1527          */
CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT);
CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2);
 1531         /* Set DMA burst length */
CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN);
CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128);
CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK);
 1537         /* Set collision backoff algorithm */
CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM|
VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT);
CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET);
 1542         /* Disable LPSEL field in priority resolution */
CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS);
 1545         /*
 1546          * Load the addresses of the DMA queues into the chip.
 1547          * Note that we only use one transmit queue.
 1548          */
CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0,
VGE_ADDR_LO(sc->vge_ldata.vge_tx_listseg.ds_addr));
CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1);
CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO,
VGE_ADDR_LO(sc->vge_ldata.vge_rx_listseg.ds_addr));
CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1);
CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT);
 1559         /* Enable and wake up the RX descriptor queue */
CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);
CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);
 1563         /* Enable the TX descriptor queue */
CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0);
 1566         /* Set up the receive filter -- allow large frames for VLANs. */
CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT);
 1569         /* If we want promiscuous mode, set the allframes bit. */
 1570         if (ifp->if_flags & IFF_PROMISC) {
CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC);
 1572         }
 1574         /* Set capture broadcast bit to capture broadcast frames. */
 1575         if (ifp->if_flags & IFF_BROADCAST) {
CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST);
 1577         }
 1579         /* Set multicast bit to capture multicast frames. */
 1580         if (ifp->if_flags & IFF_MULTICAST) {
CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST);
 1582         }
 1584         /* Init the cam filter. */
vge_cam_clear(sc);
 1587         /* Init the multicast filter. */
vge_setmulti(sc);
 1590         /* Enable flow control */
CSR_WRITE_1(sc, VGE_CRS2, 0x8B);
 1594         /* Enable jumbo frame reception (if desired) */
 1596         /* Start the MAC. */
CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP);
CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL);
CSR_WRITE_1(sc, VGE_CRS0,
VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START);
 1602         /*
 1603          * Configure one-shot timer for microsecond
 1604          * resulution and load it for 500 usecs.
 1605          */
CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES);
CSR_WRITE_2(sc, VGE_SSTIMER, 400);
 1609         /*
 1610          * Configure interrupt moderation for receive. Enable
 1611          * the holdoff counter and load it, and set the RX
 1612          * suppression count to the number of descriptors we
 1613          * want to allow before triggering an interrupt.
 1614          * The holdoff timer is in units of 20 usecs.
 1615          */
 1617 #ifdef notyet
CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE);
 1619         /* Select the interrupt holdoff timer page. */
CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF);
CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */
 1624         /* Enable use of the holdoff timer. */
CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF);
CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD);
 1628         /* Select the RX suppression threshold page. */
CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR);
CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */
 1633         /* Restore the page select bits. */
CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
 1636 #endif
 1638         /*
 1639          * Enable interrupts.
 1640          */
CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS);
CSR_WRITE_4(sc, VGE_ISR, 0);
CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);
 1645         /* Restore BMCR state */
mii_mediachg(&sc->sc_mii);
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
sc->vge_if_flags = 0;
sc->vge_link = 0;
 1654         if (!timeout_pending(&sc->timer_handle))
timeout_add(&sc->timer_handle, hz);
 1657         return (0);
 1658 }
 1660 /*
 1661  * Set media options.
 1662  */
 1663 int
vge_ifmedia_upd(struct ifnet *ifp)
 1665 {
 1666         struct vge_softc *sc = ifp->if_softc;
 1668         return (mii_mediachg(&sc->sc_mii));
 1669 }
 1671 /*
 1672  * Report current media status.
 1673  */
 1674 void
vge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
 1676 {
 1677         struct vge_softc *sc = ifp->if_softc;
mii_pollstat(&sc->sc_mii);
ifmr->ifm_active = sc->sc_mii.mii_media_active;
ifmr->ifm_status = sc->sc_mii.mii_media_status;
 1682 }
 1684 void
vge_miibus_statchg(struct device *dev)
 1686 {
 1687         struct vge_softc        *sc = (struct vge_softc *)dev;
 1688         struct mii_data         *mii;
 1689         struct ifmedia_entry    *ife;
mii = &sc->sc_mii;
ife = mii->mii_media.ifm_cur;
 1694         /*
 1695          * If the user manually selects a media mode, we need to turn
 1696          * on the forced MAC mode bit in the DIAGCTL register. If the
 1697          * user happens to choose a full duplex mode, we also need to
 1698          * set the 'force full duplex' bit. This applies only to
 1699          * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC
 1700          * mode is disabled, and in 1000baseT mode, full duplex is
 1701          * always implied, so we turn on the forced mode bit but leave
 1702          * the FDX bit cleared.
 1703          */
 1705         switch (IFM_SUBTYPE(ife->ifm_media)) {
 1706         case IFM_AUTO:
CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
 1709                 break;
 1710         case IFM_1000_T:
CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
 1713                 break;
 1714         case IFM_100_TX:
 1715         case IFM_10_T:
CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
 1717                 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
 1719                 } else {
CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
 1721                 }
 1722                 break;
 1723         default:
printf("%s: unknown media type: %x\n",
sc->vge_dev.dv_xname, IFM_SUBTYPE(ife->ifm_media));
 1726                 break;
 1727         }
 1728 }
 1730 int
vge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
 1732 {
 1733         struct vge_softc        *sc = ifp->if_softc;
 1734         struct ifreq            *ifr = (struct ifreq *) data;
 1735         struct ifaddr           *ifa = (struct ifaddr *) data;
 1736         int                     s, error = 0;
s = splnet();
 1740         if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) {
splx(s);
 1742                 return (error);
 1743         }
 1745         switch (command) {
 1746         case SIOCSIFADDR:
ifp->if_flags |= IFF_UP;
 1748                 switch (ifa->ifa_addr->sa_family) {
 1749 #ifdef INET
 1750                 case AF_INET:
vge_init(ifp);
arp_ifinit(&sc->arpcom, ifa);
 1753                         break;
 1754 #endif
 1755                 default:
vge_init(ifp);
 1757                         break;
 1758                 }
 1759                 break;
 1760         case SIOCSIFMTU:
 1761                 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ifp->if_hardmtu)
error = EINVAL;
 1763                 else if (ifp->if_mtu != ifr->ifr_mtu)
ifp->if_mtu = ifr->ifr_mtu;
 1765                 break;
 1766         case SIOCSIFFLAGS:
 1767                 if (ifp->if_flags & IFF_UP) {
 1768                         if (ifp->if_flags & IFF_RUNNING &&
ifp->if_flags & IFF_PROMISC &&
 1770                             !(sc->vge_if_flags & IFF_PROMISC)) {
CSR_SETBIT_1(sc, VGE_RXCTL,
VGE_RXCTL_RX_PROMISC);
vge_setmulti(sc);
 1774                         } else if (ifp->if_flags & IFF_RUNNING &&
 1775                             !(ifp->if_flags & IFF_PROMISC) &&
sc->vge_if_flags & IFF_PROMISC) {
CSR_CLRBIT_1(sc, VGE_RXCTL,
VGE_RXCTL_RX_PROMISC);
vge_setmulti(sc);
 1780                         } else
vge_init(ifp);
 1782                 } else {
 1783                         if (ifp->if_flags & IFF_RUNNING)
vge_stop(sc);
 1785                 }
sc->vge_if_flags = ifp->if_flags;
 1787                 break;
 1788         case SIOCADDMULTI:
 1789         case SIOCDELMULTI:
error = (command == SIOCADDMULTI) ?
ether_addmulti(ifr, &sc->arpcom) :
ether_delmulti(ifr, &sc->arpcom);
 1794                 if (error == ENETRESET) {
 1795                         if (ifp->if_flags & IFF_RUNNING)
vge_setmulti(sc);
error = 0;
 1798                 }
 1799                 break;
 1800         case SIOCGIFMEDIA:
 1801         case SIOCSIFMEDIA:
error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command);
 1803                 break;
 1804         default:
error = ENOTTY;
 1806                 break;
 1807         }
splx(s);
 1810         return (error);
 1811 }
 1813 void
vge_watchdog(struct ifnet *ifp)
 1815 {
 1816         struct vge_softc *sc = ifp->if_softc;
 1817         int s;
s = splnet();
printf("%s: watchdog timeout\n", sc->vge_dev.dv_xname);
ifp->if_oerrors++;
vge_txeof(sc);
vge_rxeof(sc);
vge_init(ifp);
splx(s);
 1829 }
 1831 /*
 1832  * Stop the adapter and free any mbufs allocated to the
 1833  * RX and TX lists.
 1834  */
 1835 void
vge_stop(struct vge_softc *sc)
 1837 {
 1838         int                     i;
 1839         struct ifnet            *ifp;
ifp = &sc->arpcom.ac_if;
ifp->if_timer = 0;
 1843         if (timeout_pending(&sc->timer_handle))
timeout_del(&sc->timer_handle);
ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);
CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP);
CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF);
CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF);
CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF);
CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0);
 1855         if (sc->vge_head != NULL) {
m_freem(sc->vge_head);
sc->vge_head = sc->vge_tail = NULL;
 1858         }
 1860         /* Free the TX list buffers. */
 1861         for (i = 0; i < VGE_TX_DESC_CNT; i++) {
 1862                 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) {
bus_dmamap_unload(sc->sc_dmat,
sc->vge_ldata.vge_tx_dmamap[i]);
m_freem(sc->vge_ldata.vge_tx_mbuf[i]);
sc->vge_ldata.vge_tx_mbuf[i] = NULL;
 1867                 }
 1868         }
 1870         /* Free the RX list buffers. */
 1871         for (i = 0; i < VGE_RX_DESC_CNT; i++) {
 1872                 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) {
bus_dmamap_unload(sc->sc_dmat,
sc->vge_ldata.vge_rx_dmamap[i]);
m_freem(sc->vge_ldata.vge_rx_mbuf[i]);
sc->vge_ldata.vge_rx_mbuf[i] = NULL;
 1877                 }
 1878         }
 1879 }