h 199 arch/i386/i386/bios.c bios32_header_t h = (bios32_header_t)va;
h 203 arch/i386/i386/bios.c if (h->signature != BIOS32_SIGNATURE)
h 207 arch/i386/i386/bios.c for (cksum = 0, i = h->length * 16; i--; cksum += va[i])
h 212 arch/i386/i386/bios.c if (h->entry <= BIOS32_START || h->entry >= BIOS32_END)
h 216 arch/i386/i386/bios.c bios32_entry.offset = (u_int32_t)ISA_HOLE_VADDR(h->entry);
h 217 arch/i386/i386/bios.c printf(", BIOS32 rev. %d @ 0x%lx", h->rev, h->entry);
h 124 arch/i386/include/bus.h #define bus_space_read_1(t, h, o) \
h 125 arch/i386/include/bus.h ((t) == I386_BUS_SPACE_IO ? (inb((h) + (o))) : \
h 126 arch/i386/include/bus.h (*(volatile u_int8_t *)((h) + (o))))
h 128 arch/i386/include/bus.h #define bus_space_read_2(t, h, o) \
h 129 arch/i386/include/bus.h ((t) == I386_BUS_SPACE_IO ? (inw((h) + (o))) : \
h 130 arch/i386/include/bus.h (*(volatile u_int16_t *)((h) + (o))))
h 132 arch/i386/include/bus.h #define bus_space_read_4(t, h, o) \
h 133 arch/i386/include/bus.h ((t) == I386_BUS_SPACE_IO ? (inl((h) + (o))) : \
h 134 arch/i386/include/bus.h (*(volatile u_int32_t *)((h) + (o))))
h 137 arch/i386/include/bus.h #define bus_space_read_8(t, h, o) !!! bus_space_read_8 unimplemented !!!
h 149 arch/i386/include/bus.h #define bus_space_read_multi_1(t, h, o, a, cnt) do { \
h 151 arch/i386/include/bus.h insb((h) + (o), (a), (cnt)); \
h 158 arch/i386/include/bus.h "+D" (_addr), "+c" (_cnt) : "r" ((h) + (o)) : \
h 163 arch/i386/include/bus.h #define bus_space_read_multi_2(t, h, o, a, cnt) do { \
h 165 arch/i386/include/bus.h insw((h) + (o), (a), (cnt)); \
h 172 arch/i386/include/bus.h "+D" (_addr), "+c" (_cnt) : "r" ((h) + (o)) : \
h 177 arch/i386/include/bus.h #define bus_space_read_multi_4(t, h, o, a, cnt) do { \
h 179 arch/i386/include/bus.h insl((h) + (o), (a), (cnt)); \
h 186 arch/i386/include/bus.h "+D" (_addr), "+c" (_cnt) : "r" ((h) + (o)) : \
h 206 arch/i386/include/bus.h #define bus_space_read_raw_multi_2(t, h, o, a, c) \
h 207 arch/i386/include/bus.h bus_space_read_multi_2((t), (h), (o), (u_int16_t *)(a), (c) >> 1)
h 208 arch/i386/include/bus.h #define bus_space_read_raw_multi_4(t, h, o, a, c) \
h 209 arch/i386/include/bus.h bus_space_read_multi_4((t), (h), (o), (u_int32_t *)(a), (c) >> 2)
h 226 arch/i386/include/bus.h #define bus_space_read_region_1(t, h, o, a, cnt) do { \
h 227 arch/i386/include/bus.h int _cnt = (cnt); void *_addr = (a); int _port = (h)+(o); \
h 241 arch/i386/include/bus.h #define bus_space_read_region_2(t, h, o, a, cnt) do { \
h 242 arch/i386/include/bus.h int _cnt = (cnt); void *_addr = (a); int _port = (h)+(o); \
h 256 arch/i386/include/bus.h #define bus_space_read_region_4(t, h, o, a, cnt) do { \
h 257 arch/i386/include/bus.h int _cnt = (cnt); void *_addr = (a); int _port = (h)+(o); \
h 287 arch/i386/include/bus.h #define bus_space_read_raw_region_2(t, h, o, a, c) \
h 288 arch/i386/include/bus.h bus_space_read_region_2((t), (h), (o), (u_int16_t *)(a), (c) >> 1)
h 289 arch/i386/include/bus.h #define bus_space_read_raw_region_4(t, h, o, a, c) \
h 290 arch/i386/include/bus.h bus_space_read_region_4((t), (h), (o), (u_int32_t *)(a), (c) >> 2)
h 306 arch/i386/include/bus.h #define bus_space_write_1(t, h, o, v) do { \
h 308 arch/i386/include/bus.h outb((h) + (o), (v)); \
h 310 arch/i386/include/bus.h ((void)(*(volatile u_int8_t *)((h) + (o)) = (v))); \
h 313 arch/i386/include/bus.h #define bus_space_write_2(t, h, o, v) do { \
h 315 arch/i386/include/bus.h outw((h) + (o), (v)); \
h 317 arch/i386/include/bus.h ((void)(*(volatile u_int16_t *)((h) + (o)) = (v))); \
h 320 arch/i386/include/bus.h #define bus_space_write_4(t, h, o, v) do { \
h 322 arch/i386/include/bus.h outl((h) + (o), (v)); \
h 324 arch/i386/include/bus.h ((void)(*(volatile u_int32_t *)((h) + (o)) = (v))); \
h 340 arch/i386/include/bus.h #define bus_space_write_multi_1(t, h, o, a, cnt) do { \
h 342 arch/i386/include/bus.h outsb((h) + (o), (a), (cnt)); \
h 349 arch/i386/include/bus.h "+S" (_addr), "+c" (_cnt) : "r" ((h) + (o)) : \
h 354 arch/i386/include/bus.h #define bus_space_write_multi_2(t, h, o, a, cnt) do { \
h 356 arch/i386/include/bus.h outsw((h) + (o), (a), (cnt)); \
h 363 arch/i386/include/bus.h "+S" (_addr), "+c" (_cnt) : "r" ((h) + (o)) : \
h 368 arch/i386/include/bus.h #define bus_space_write_multi_4(t, h, o, a, cnt) do { \
h 370 arch/i386/include/bus.h outsl((h) + (o), (a), (cnt)); \
h 377 arch/i386/include/bus.h "+S" (_addr), "+c" (_cnt) : "r" ((h) + (o)) : \
h 383 arch/i386/include/bus.h #define bus_space_write_multi_8(t, h, o, a, c) \
h 398 arch/i386/include/bus.h #define bus_space_write_raw_multi_2(t, h, o, a, c) \
h 399 arch/i386/include/bus.h bus_space_write_multi_2((t), (h), (o), (const u_int16_t *)(a), (c) >> 1)
h 400 arch/i386/include/bus.h #define bus_space_write_raw_multi_4(t, h, o, a, c) \
h 401 arch/i386/include/bus.h bus_space_write_multi_4((t), (h), (o), (const u_int32_t *)(a), (c) >> 2)
h 417 arch/i386/include/bus.h #define bus_space_write_region_1(t, h, o, a, cnt) do { \
h 418 arch/i386/include/bus.h int _port = (h)+(o); const void *_addr=(a); int _cnt=(cnt); \
h 432 arch/i386/include/bus.h #define bus_space_write_region_2(t, h, o, a, cnt) do { \
h 433 arch/i386/include/bus.h int _port = (h)+(o); const void *_addr=(a); int _cnt=(cnt); \
h 447 arch/i386/include/bus.h #define bus_space_write_region_4(t, h, o, a, cnt) do { \
h 448 arch/i386/include/bus.h int _port = (h)+(o); const void *_addr=(a); int _cnt=(cnt); \
h 479 arch/i386/include/bus.h #define bus_space_write_raw_region_2(t, h, o, a, c) \
h 480 arch/i386/include/bus.h bus_space_write_region_2((t), (h), (o), (const u_int16_t *)(a), (c) >> 1)
h 481 arch/i386/include/bus.h #define bus_space_write_raw_region_4(t, h, o, a, c) \
h 482 arch/i386/include/bus.h bus_space_write_region_4((t), (h), (o), (const u_int32_t *)(a), (c) >> 2)
h 498 arch/i386/include/bus.h #define bus_space_set_multi_1(t, h, o, v, cnt) do { \
h 505 arch/i386/include/bus.h "+c" (_cnt) : "d" ((h) + (o)), "a" ((v)) : \
h 512 arch/i386/include/bus.h "+c" (_cnt) : "D" ((h) + (o)), "a" ((v)) : \
h 517 arch/i386/include/bus.h #define bus_space_set_multi_2(t, h, o, v, cnt) do { \
h 524 arch/i386/include/bus.h "+c" (_cnt) : "d" ((h) + (o)), "a" ((v)) : \
h 531 arch/i386/include/bus.h "+c" (_cnt) : "D" ((h) + (o)), "a" ((v)) : \
h 536 arch/i386/include/bus.h #define bus_space_set_multi_4(t, h, o, v, cnt) do { \
h 543 arch/i386/include/bus.h "+c" (_cnt) : "d" ((h) + (o)), "a" ((v)) : \
h 550 arch/i386/include/bus.h "+c" (_cnt) : "D" ((h) + (o)), "a" ((v)) : \
h 569 arch/i386/include/bus.h #define bus_space_set_region_1(t, h, o, v, cnt) do { \
h 570 arch/i386/include/bus.h int _port = (h)+(o); int _cnt = (cnt); \
h 588 arch/i386/include/bus.h #define bus_space_set_region_2(t, h, o, v, cnt) do { \
h 589 arch/i386/include/bus.h int _port = (h)+(o); int _cnt = (cnt); \
h 607 arch/i386/include/bus.h #define bus_space_set_region_4(t, h, o, v, cnt) do { \
h 608 arch/i386/include/bus.h int _port = (h)+(o); int _cnt = (cnt); \
h 727 arch/i386/include/bus.h #define bus_space_barrier(t, h, o, l, f) \
h 728 arch/i386/include/bus.h ((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f)))
h 128 arch/i386/pci/pcibiosvar.h #define pciintr_icu_getclink(t, h, link, pirqp) \
h 129 arch/i386/pci/pcibiosvar.h (*(t)->pi_getclink)((h), (link), (pirqp))
h 130 arch/i386/pci/pcibiosvar.h #define pciintr_icu_get_intr(t, h, pirq, irqp) \
h 131 arch/i386/pci/pcibiosvar.h (*(t)->pi_get_intr)((h), (pirq), (irqp))
h 132 arch/i386/pci/pcibiosvar.h #define pciintr_icu_set_intr(t, h, pirq, irq) \
h 133 arch/i386/pci/pcibiosvar.h (*(t)->pi_set_intr)((h), (pirq), (irq))
h 134 arch/i386/pci/pcibiosvar.h #define pciintr_icu_get_trigger(t, h, irq, triggerp) \
h 135 arch/i386/pci/pcibiosvar.h (*(t)->pi_get_trigger)((h), (irq), (triggerp))
h 136 arch/i386/pci/pcibiosvar.h #define pciintr_icu_set_trigger(t, h, irq, trigger) \
h 137 arch/i386/pci/pcibiosvar.h (*(t)->pi_set_trigger)((h), (irq), (trigger))
h 285 crypto/sha2.c #define ROUND256_0_TO_15(a,b,c,d,e,f,g,h) do { \
h 289 crypto/sha2.c T1 = (h) + Sigma1_256((e)) + Ch((e), (f), (g)) + K256[j] + W256[j]; \
h 291 crypto/sha2.c (h) = T1 + Sigma0_256((a)) + Maj((a), (b), (c)); \
h 295 crypto/sha2.c #define ROUND256(a,b,c,d,e,f,g,h) do { \
h 300 crypto/sha2.c T1 = (h) + Sigma1_256((e)) + Ch((e), (f), (g)) + K256[j] + \
h 303 crypto/sha2.c (h) = T1 + Sigma0_256((a)) + Maj((a), (b), (c)); \
h 310 crypto/sha2.c u_int32_t a, b, c, d, e, f, g, h, s0, s1;
h 324 crypto/sha2.c h = context->state[7];
h 329 crypto/sha2.c ROUND256_0_TO_15(a,b,c,d,e,f,g,h);
h 330 crypto/sha2.c ROUND256_0_TO_15(h,a,b,c,d,e,f,g);
h 331 crypto/sha2.c ROUND256_0_TO_15(g,h,a,b,c,d,e,f);
h 332 crypto/sha2.c ROUND256_0_TO_15(f,g,h,a,b,c,d,e);
h 333 crypto/sha2.c ROUND256_0_TO_15(e,f,g,h,a,b,c,d);
h 334 crypto/sha2.c ROUND256_0_TO_15(d,e,f,g,h,a,b,c);
h 335 crypto/sha2.c ROUND256_0_TO_15(c,d,e,f,g,h,a,b);
h 336 crypto/sha2.c ROUND256_0_TO_15(b,c,d,e,f,g,h,a);
h 341 crypto/sha2.c ROUND256(a,b,c,d,e,f,g,h);
h 342 crypto/sha2.c ROUND256(h,a,b,c,d,e,f,g);
h 343 crypto/sha2.c ROUND256(g,h,a,b,c,d,e,f);
h 344 crypto/sha2.c ROUND256(f,g,h,a,b,c,d,e);
h 345 crypto/sha2.c ROUND256(e,f,g,h,a,b,c,d);
h 346 crypto/sha2.c ROUND256(d,e,f,g,h,a,b,c);
h 347 crypto/sha2.c ROUND256(c,d,e,f,g,h,a,b);
h 348 crypto/sha2.c ROUND256(b,c,d,e,f,g,h,a);
h 359 crypto/sha2.c context->state[7] += h;
h 362 crypto/sha2.c a = b = c = d = e = f = g = h = T1 = 0;
h 370 crypto/sha2.c u_int32_t a, b, c, d, e, f, g, h, s0, s1;
h 384 crypto/sha2.c h = context->state[7];
h 392 crypto/sha2.c T1 = h + Sigma1_256(e) + Ch(e, f, g) + K256[j] + W256[j];
h 394 crypto/sha2.c h = g;
h 414 crypto/sha2.c T1 = h + Sigma1_256(e) + Ch(e, f, g) + K256[j] +
h 417 crypto/sha2.c h = g;
h 437 crypto/sha2.c context->state[7] += h;
h 440 crypto/sha2.c a = b = c = d = e = f = g = h = T1 = T2 = 0;
h 569 crypto/sha2.c #define ROUND512_0_TO_15(a,b,c,d,e,f,g,h) do { \
h 575 crypto/sha2.c T1 = (h) + Sigma1_512((e)) + Ch((e), (f), (g)) + K512[j] + W512[j]; \
h 577 crypto/sha2.c (h) = T1 + Sigma0_512((a)) + Maj((a), (b), (c)); \
h 582 crypto/sha2.c #define ROUND512(a,b,c,d,e,f,g,h) do { \
h 587 crypto/sha2.c T1 = (h) + Sigma1_512((e)) + Ch((e), (f), (g)) + K512[j] + \
h 590 crypto/sha2.c (h) = T1 + Sigma0_512((a)) + Maj((a), (b), (c)); \
h 597 crypto/sha2.c u_int64_t a, b, c, d, e, f, g, h, s0, s1;
h 609 crypto/sha2.c h = context->state[7];
h 613 crypto/sha2.c ROUND512_0_TO_15(a,b,c,d,e,f,g,h);
h 614 crypto/sha2.c ROUND512_0_TO_15(h,a,b,c,d,e,f,g);
h 615 crypto/sha2.c ROUND512_0_TO_15(g,h,a,b,c,d,e,f);
h 616 crypto/sha2.c ROUND512_0_TO_15(f,g,h,a,b,c,d,e);
h 617 crypto/sha2.c ROUND512_0_TO_15(e,f,g,h,a,b,c,d);
h 618 crypto/sha2.c ROUND512_0_TO_15(d,e,f,g,h,a,b,c);
h 619 crypto/sha2.c ROUND512_0_TO_15(c,d,e,f,g,h,a,b);
h 620 crypto/sha2.c ROUND512_0_TO_15(b,c,d,e,f,g,h,a);
h 625 crypto/sha2.c ROUND512(a,b,c,d,e,f,g,h);
h 626 crypto/sha2.c ROUND512(h,a,b,c,d,e,f,g);
h 627 crypto/sha2.c ROUND512(g,h,a,b,c,d,e,f);
h 628 crypto/sha2.c ROUND512(f,g,h,a,b,c,d,e);
h 629 crypto/sha2.c ROUND512(e,f,g,h,a,b,c,d);
h 630 crypto/sha2.c ROUND512(d,e,f,g,h,a,b,c);
h 631 crypto/sha2.c ROUND512(c,d,e,f,g,h,a,b);
h 632 crypto/sha2.c ROUND512(b,c,d,e,f,g,h,a);
h 643 crypto/sha2.c context->state[7] += h;
h 646 crypto/sha2.c a = b = c = d = e = f = g = h = T1 = 0;
h 654 crypto/sha2.c u_int64_t a, b, c, d, e, f, g, h, s0, s1;
h 666 crypto/sha2.c h = context->state[7];
h 676 crypto/sha2.c T1 = h + Sigma1_512(e) + Ch(e, f, g) + K512[j] + W512[j];
h 678 crypto/sha2.c h = g;
h 698 crypto/sha2.c T1 = h + Sigma1_512(e) + Ch(e, f, g) + K512[j] +
h 701 crypto/sha2.c h = g;
h 721 crypto/sha2.c context->state[7] += h;
h 724 crypto/sha2.c a = b = c = d = e = f = g = h = T1 = T2 = 0;
h 232 dev/bluetooth/btkbd.c struct hid_item h;
h 238 dev/bluetooth/btkbd.c while (hid_get_item(d, &h)) {
h 239 dev/bluetooth/btkbd.c if (h.kind != hid_input || (h.flags & HIO_CONST) ||
h 240 dev/bluetooth/btkbd.c HID_GET_USAGE_PAGE(h.usage) != HUP_KEYBOARD ||
h 241 dev/bluetooth/btkbd.c h.report_ID != id)
h 244 dev/bluetooth/btkbd.c if (h.flags & HIO_VARIABLE) {
h 245 dev/bluetooth/btkbd.c if (h.loc.size != 1)
h 250 dev/bluetooth/btkbd.c sc->sc_modloc[imod] = h.loc;
h 252 dev/bluetooth/btkbd.c sc->sc_mods[imod].key = HID_GET_USAGE(h.usage);
h 258 dev/bluetooth/btkbd.c if (h.loc.size != 8)
h 261 dev/bluetooth/btkbd.c if (h.loc.count > MAXKEYCODE)
h 264 dev/bluetooth/btkbd.c if (h.loc.pos % 8 != 0)
h 270 dev/bluetooth/btkbd.c sc->sc_keycodeloc = h.loc;
h 271 dev/bluetooth/btkbd.c sc->sc_nkeycode = h.loc.count;
h 116 dev/cardbus/puc_cardbus.c &sc->sc_bar_mappings[i].t, &sc->sc_bar_mappings[i].h,
h 183 dev/cardbus/puc_cardbus.c sc->sc_bar_mappings[i].t, sc->sc_bar_mappings[i].h,
h 294 dev/ic/am79c930.c bus_space_handle_t h = sc->sc_memh;
h 298 dev/ic/am79c930.c bus_space_write_2(t, h, off, val);
h 300 dev/ic/am79c930.c bus_space_write_1(t, h, off, val & 0xff);
h 301 dev/ic/am79c930.c bus_space_write_1(t, h, off+1, (val >> 8) & 0xff);
h 311 dev/ic/am79c930.c bus_space_handle_t h = sc->sc_memh;
h 315 dev/ic/am79c930.c bus_space_write_4(t, h, off, val);
h 317 dev/ic/am79c930.c bus_space_write_1(t, h, off, val & 0xff);
h 318 dev/ic/am79c930.c bus_space_write_1(t, h, off+1, (val >> 8) & 0xff);
h 319 dev/ic/am79c930.c bus_space_write_1(t, h, off+2, (val >> 16) & 0xff);
h 320 dev/ic/am79c930.c bus_space_write_1(t, h, off+3, (val >> 24) & 0xff);
h 927 dev/ic/dc.c u_int32_t h, *sp;
h 971 dev/ic/dc.c h = dc_crc_le(sc, enm->enm_addrlo);
h 972 dev/ic/dc.c sp[h >> 4] |= htole32(1 << (h & 0xF));
h 978 dev/ic/dc.c h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr);
h 979 dev/ic/dc.c sp[h >> 4] |= htole32(1 << (h & 0xF));
h 1020 dev/ic/dc.c int h = 0;
h 1062 dev/ic/dc.c h = dc_crc_le(sc, enm->enm_addrlo);
h 1064 dev/ic/dc.c h = dc_crc_be(enm->enm_addrlo);
h 1065 dev/ic/dc.c if (h < 32)
h 1066 dev/ic/dc.c hashes[0] |= (1 << h);
h 1068 dev/ic/dc.c hashes[1] |= (1 << (h - 32));
h 1084 dev/ic/dc.c int h = 0;
h 1133 dev/ic/dc.c h = dc_crc_be(enm->enm_addrlo);
h 1134 dev/ic/dc.c if (h < 32)
h 1135 dev/ic/dc.c hashes[0] |= (1 << h);
h 1137 dev/ic/dc.c hashes[1] |= (1 << (h - 32));
h 1155 dev/ic/dc.c u_int32_t h, *sp;
h 1191 dev/ic/dc.c h = dc_crc_le(sc, enm->enm_addrlo);
h 1192 dev/ic/dc.c sp[h >> 4] |= htole32(1 << (h & 0xF));
h 1197 dev/ic/dc.c h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr);
h 1198 dev/ic/dc.c sp[h >> 4] |= htole32(1 << (h & 0xF));
h 147 dev/ic/dp8390var.h #define NIC_GET(t, h, reg) bus_space_read_1(t, h, \
h 149 dev/ic/dp8390var.h #define NIC_PUT(t, h, reg, val) bus_space_write_1(t, h, \
h 151 dev/ic/dp8390var.h #define NIC_BARRIER(t, h) bus_space_barrier(t, h, 0, 0x10, \
h 413 dev/ic/gem.c gem_bitwait(struct gem_softc *sc, bus_space_handle_t h, int r,
h 420 dev/ic/gem.c reg = bus_space_read_4(sc->sc_bustag, h, r);
h 432 dev/ic/gem.c bus_space_handle_t h = sc->sc_h2;
h 441 dev/ic/gem.c bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX);
h 442 dev/ic/gem.c if (!gem_bitwait(sc, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0))
h 521 dev/ic/gem.c bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2;
h 528 dev/ic/gem.c bus_space_write_4(t, h, GEM_RX_CONFIG, 0);
h 530 dev/ic/gem.c if (!gem_bitwait(sc, h, GEM_RX_CONFIG, 1, 0))
h 553 dev/ic/gem.c bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2;
h 560 dev/ic/gem.c bus_space_write_4(t, h, GEM_TX_CONFIG, 0);
h 562 dev/ic/gem.c if (!gem_bitwait(sc, h, GEM_TX_CONFIG, 1, 0))
h 585 dev/ic/gem.c bus_space_handle_t h = sc->sc_h1;
h 589 dev/ic/gem.c cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
h 591 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg);
h 594 dev/ic/gem.c return (gem_bitwait(sc, h, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0));
h 604 dev/ic/gem.c bus_space_handle_t h = sc->sc_h1;
h 608 dev/ic/gem.c cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG);
h 610 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg);
h 613 dev/ic/gem.c return (gem_bitwait(sc, h, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0));
h 699 dev/ic/gem.c bus_space_handle_t h = sc->sc_h1;
h 733 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, v);
h 739 dev/ic/gem.c bus_space_write_4(t, h, GEM_TX_RING_PTR_HI,
h 741 dev/ic/gem.c bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0));
h 743 dev/ic/gem.c bus_space_write_4(t, h, GEM_RX_RING_PTR_HI,
h 745 dev/ic/gem.c bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
h 748 dev/ic/gem.c bus_space_write_4(t, h, GEM_INTMASK,
h 755 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_RX_MASK,
h 757 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */
h 758 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */
h 764 dev/ic/gem.c bus_space_write_4(t, h, GEM_TX_CONFIG,
h 767 dev/ic/gem.c bus_space_write_4(t, h, GEM_TX_KICK, 0);
h 775 dev/ic/gem.c bus_space_write_4(t, h, GEM_RX_CONFIG,
h 783 dev/ic/gem.c bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH,
h 786 dev/ic/gem.c bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6);
h 792 dev/ic/gem.c v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
h 794 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v);
h 804 dev/ic/gem.c bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4);
h 821 dev/ic/gem.c bus_space_handle_t h = sc->sc_h1;
h 829 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_IPG0, 0);
h 830 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_IPG1, 8);
h 831 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_IPG2, 4);
h 833 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN);
h 836 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, v);
h 838 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7);
h 839 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4);
h 840 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10);
h 842 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088);
h 843 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED,
h 847 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_ADDR3, 0);
h 848 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_ADDR4, 0);
h 849 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_ADDR5, 0);
h 851 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001);
h 852 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200);
h 853 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180);
h 856 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0);
h 857 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0);
h 858 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0);
h 860 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0);
h 861 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0);
h 867 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0);
h 868 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0);
h 869 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0);
h 870 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0);
h 871 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0);
h 872 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0);
h 873 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0);
h 874 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0);
h 875 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0);
h 876 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0);
h 877 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0);
h 880 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0);
h 885 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_ADDR0,
h 887 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_ADDR1,
h 889 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_ADDR2,
h 896 dev/ic/gem.c sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG);
h 903 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v);
h 914 dev/ic/gem.c bus_space_handle_t h = sc->sc_h1;
h 995 dev/ic/gem.c bus_space_write_4(t, h, GEM_RX_KICK, i);
h 998 dev/ic/gem.c sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION)));
h 1525 dev/ic/gem.c bus_space_handle_t h = sc->sc_h1;
h 1530 dev/ic/gem.c v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
h 1594 dev/ic/gem.c bus_space_write_4(t, h,
h 1600 dev/ic/gem.c bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v);
h 762 dev/ic/hme.c } h;
h 815 dev/ic/hme.c ph.h.len = htons(ntohs(ip->ip_len) - hlen);
h 816 dev/ic/hme.c ph.h.ttl = 0;
h 817 dev/ic/hme.c ph.h.proto = ip->ip_p;
h 818 dev/ic/hme.c ph.h.src = ip->ip_src.s_addr;
h 819 dev/ic/hme.c ph.h.dst = ip->ip_dst.s_addr;
h 134 dev/ic/i82365.c pcic_vendor(h)
h 135 dev/ic/i82365.c struct pcic_handle *h;
h 144 dev/ic/i82365.c pcic_write(h, PCIC_CIRRUS_CHIP_INFO, 0);
h 145 dev/ic/i82365.c reg = pcic_read(h, -1);
h 149 dev/ic/i82365.c reg = pcic_read(h, -1);
h 158 dev/ic/i82365.c reg = pcic_read(h, PCIC_IDENT);
h 175 dev/ic/i82365.c pcic_write(h, 0x0e, -1);
h 176 dev/ic/i82365.c pcic_write(h, 0x37, -1);
h 178 dev/ic/i82365.c reg = pcic_read(h, PCIC_VG468_MISC);
h 180 dev/ic/i82365.c pcic_write(h, PCIC_VG468_MISC, reg);
h 182 dev/ic/i82365.c reg = pcic_read(h, PCIC_IDENT);
h 190 dev/ic/i82365.c reg = pcic_read(h, PCIC_VG468_MISC);
h 192 dev/ic/i82365.c pcic_write(h, PCIC_VG468_MISC, reg);
h 352 dev/ic/i82365.c pcic_attach_socket(h)
h 353 dev/ic/i82365.c struct pcic_handle *h;
h 356 dev/ic/i82365.c struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent);
h 360 dev/ic/i82365.c h->shutdown = 0;
h 361 dev/ic/i82365.c h->memalloc = 0;
h 362 dev/ic/i82365.c h->ioalloc = 0;
h 363 dev/ic/i82365.c h->ih_irq = 0;
h 369 dev/ic/i82365.c paa.pch = (pcmcia_chipset_handle_t) h;
h 373 dev/ic/i82365.c h->pcmcia = config_found_sm(&sc->dev, &paa, pcic_print,
h 378 dev/ic/i82365.c if (h->pcmcia)
h 379 dev/ic/i82365.c pcic_init_socket(h);
h 381 dev/ic/i82365.c h->flags &= ~PCIC_FLAG_SOCKETP;
h 388 dev/ic/i82365.c struct pcic_handle *h = arg;
h 391 dev/ic/i82365.c switch (h->sock) {
h 408 dev/ic/i82365.c if (kthread_create(pcic_event_thread, h, &h->event_thread,
h 409 dev/ic/i82365.c "%s,%s", h->ph_parent->dv_xname, cs)) {
h 411 dev/ic/i82365.c h->ph_parent->dv_xname, h->sock);
h 420 dev/ic/i82365.c struct pcic_handle *h = arg;
h 423 dev/ic/i82365.c struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent);
h 425 dev/ic/i82365.c while (h->shutdown == 0) {
h 427 dev/ic/i82365.c if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) {
h 429 dev/ic/i82365.c (void) tsleep(&h->events, PWAIT, "pcicev", 0);
h 437 dev/ic/i82365.c pcic_event_process(h, pe);
h 440 dev/ic/i82365.c h->event_thread = NULL;
h 449 dev/ic/i82365.c pcic_event_process(h, pe)
h 450 dev/ic/i82365.c struct pcic_handle *h;
h 456 dev/ic/i82365.c SIMPLEQ_REMOVE_HEAD(&h->events, pe_q);
h 465 dev/ic/i82365.c if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL)
h 472 dev/ic/i82365.c SIMPLEQ_REMOVE_HEAD(&h->events, pe_q);
h 474 dev/ic/i82365.c SIMPLEQ_REMOVE_HEAD(&h->events, pe_q);
h 480 dev/ic/i82365.c DPRINTF(("%s: insertion event\n", h->ph_parent->dv_xname));
h 481 dev/ic/i82365.c pcic_attach_card(h);
h 489 dev/ic/i82365.c if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL)
h 496 dev/ic/i82365.c SIMPLEQ_REMOVE_HEAD(&h->events, pe_q);
h 498 dev/ic/i82365.c SIMPLEQ_REMOVE_HEAD(&h->events, pe_q);
h 504 dev/ic/i82365.c DPRINTF(("%s: removal event\n", h->ph_parent->dv_xname));
h 505 dev/ic/i82365.c pcic_detach_card(h, DETACH_FORCE);
h 515 dev/ic/i82365.c pcic_init_socket(h)
h 516 dev/ic/i82365.c struct pcic_handle *h;
h 519 dev/ic/i82365.c struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent);
h 525 dev/ic/i82365.c if (h->event_thread != NULL)
h 528 dev/ic/i82365.c kthread_create_deferred(pcic_create_event_thread, h);
h 532 dev/ic/i82365.c pcic_write(h, PCIC_CSC_INTR, (sc->irq << PCIC_CSC_INTR_IRQ_SHIFT) |
h 534 dev/ic/i82365.c pcic_write(h, PCIC_INTR, 0);
h 535 dev/ic/i82365.c pcic_read(h, PCIC_CSC);
h 539 dev/ic/i82365.c if ((h->vendor == PCIC_VENDOR_CIRRUS_PD6710) ||
h 540 dev/ic/i82365.c (h->vendor == PCIC_VENDOR_CIRRUS_PD672X)) {
h 541 dev/ic/i82365.c reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_2);
h 544 dev/ic/i82365.c h->ph_parent->dv_xname, h->sock));
h 546 dev/ic/i82365.c pcic_write(h, PCIC_CIRRUS_MISC_CTL_2, reg);
h 551 dev/ic/i82365.c reg = pcic_read(h, PCIC_IF_STATUS);
h 555 dev/ic/i82365.c pcic_attach_card(h);
h 556 dev/ic/i82365.c h->laststate = PCIC_LASTSTATE_PRESENT;
h 558 dev/ic/i82365.c h->laststate = PCIC_LASTSTATE_EMPTY;
h 568 dev/ic/i82365.c struct pcic_handle *h = (struct pcic_handle *) paa->pch;
h 570 dev/ic/i82365.c switch (h->sock) {
h 628 dev/ic/i82365.c struct pcic_handle *h = (struct pcic_handle *) paa->pch;
h 634 dev/ic/i82365.c switch (h->sock) {
h 693 dev/ic/i82365.c pcic_intr_socket(h)
h 694 dev/ic/i82365.c struct pcic_handle *h;
h 698 dev/ic/i82365.c cscreg = pcic_read(h, PCIC_CSC);
h 707 dev/ic/i82365.c DPRINTF(("%s: %02x GPI\n", h->ph_parent->dv_xname, h->sock));
h 712 dev/ic/i82365.c statreg = pcic_read(h, PCIC_IF_STATUS);
h 714 dev/ic/i82365.c DPRINTF(("%s: %02x CD %x\n", h->ph_parent->dv_xname, h->sock,
h 719 dev/ic/i82365.c if (h->laststate != PCIC_LASTSTATE_PRESENT) {
h 721 dev/ic/i82365.c h->ph_parent->dv_xname));
h 722 dev/ic/i82365.c pcic_queue_event(h, PCIC_EVENT_INSERTION);
h 724 dev/ic/i82365.c h->laststate = PCIC_LASTSTATE_PRESENT;
h 726 dev/ic/i82365.c if (h->laststate == PCIC_LASTSTATE_PRESENT) {
h 729 dev/ic/i82365.c h->ph_parent->dv_xname));
h 730 dev/ic/i82365.c pcic_deactivate_card(h);
h 733 dev/ic/i82365.c h->ph_parent->dv_xname));
h 734 dev/ic/i82365.c pcic_queue_event(h, PCIC_EVENT_REMOVAL);
h 736 dev/ic/i82365.c h->laststate =
h 742 dev/ic/i82365.c DPRINTF(("%s: %02x READY\n", h->ph_parent->dv_xname, h->sock));
h 746 dev/ic/i82365.c DPRINTF(("%s: %02x BATTWARN\n", h->ph_parent->dv_xname,
h 747 dev/ic/i82365.c h->sock));
h 750 dev/ic/i82365.c DPRINTF(("%s: %02x BATTDEAD\n", h->ph_parent->dv_xname,
h 751 dev/ic/i82365.c h->sock));
h 757 dev/ic/i82365.c pcic_queue_event(h, event)
h 758 dev/ic/i82365.c struct pcic_handle *h;
h 770 dev/ic/i82365.c SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q);
h 772 dev/ic/i82365.c wakeup(&h->events);
h 776 dev/ic/i82365.c pcic_attach_card(h)
h 777 dev/ic/i82365.c struct pcic_handle *h;
h 779 dev/ic/i82365.c if (h->flags & PCIC_FLAG_CARDP)
h 783 dev/ic/i82365.c pcmcia_card_attach(h->pcmcia);
h 785 dev/ic/i82365.c h->flags |= PCIC_FLAG_CARDP;
h 789 dev/ic/i82365.c pcic_detach_card(h, flags)
h 790 dev/ic/i82365.c struct pcic_handle *h;
h 794 dev/ic/i82365.c if (h->flags & PCIC_FLAG_CARDP) {
h 795 dev/ic/i82365.c h->flags &= ~PCIC_FLAG_CARDP;
h 798 dev/ic/i82365.c pcmcia_card_detach(h->pcmcia, flags);
h 805 dev/ic/i82365.c pcic_deactivate_card(h)
h 806 dev/ic/i82365.c struct pcic_handle *h;
h 808 dev/ic/i82365.c struct device *dev = (struct device *)h->pcmcia;
h 816 dev/ic/i82365.c pcmcia_card_deactivate(h->pcmcia);
h 819 dev/ic/i82365.c pcic_write(h, PCIC_PWRCTL, 0);
h 822 dev/ic/i82365.c pcic_write(h, PCIC_INTR, 0);
h 836 dev/ic/i82365.c struct pcic_handle *h = (struct pcic_handle *)arg;
h 837 dev/ic/i82365.c struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent;
h 845 dev/ic/i82365.c pcic_intr_socket(h);
h 847 dev/ic/i82365.c while ((pe = SIMPLEQ_FIRST(&h->events)))
h 848 dev/ic/i82365.c pcic_event_process(h, pe);
h 860 dev/ic/i82365.c struct pcic_handle *h = (struct pcic_handle *) pch;
h 865 dev/ic/i82365.c struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent);
h 910 dev/ic/i82365.c struct pcic_handle *h = (struct pcic_handle *) pch;
h 911 dev/ic/i82365.c struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent);
h 973 dev/ic/i82365.c pcic_chip_do_mem_map(h, win)
h 974 dev/ic/i82365.c struct pcic_handle *h;
h 978 dev/ic/i82365.c int kind = h->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK;
h 980 dev/ic/i82365.c (h->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8
h 983 dev/ic/i82365.c pcic_write(h, mem_map_index[win].sysmem_start_lsb,
h 984 dev/ic/i82365.c (h->mem[win].addr >> PCIC_SYSMEM_ADDRX_SHIFT) & 0xff);
h 985 dev/ic/i82365.c pcic_write(h, mem_map_index[win].sysmem_start_msb,
h 986 dev/ic/i82365.c ((h->mem[win].addr >> (PCIC_SYSMEM_ADDRX_SHIFT + 8)) &
h 990 dev/ic/i82365.c pcic_write(h, mem_map_index[win].sysmem_stop_lsb,
h 991 dev/ic/i82365.c ((h->mem[win].addr + h->mem[win].size) >>
h 993 dev/ic/i82365.c pcic_write(h, mem_map_index[win].sysmem_stop_msb,
h 994 dev/ic/i82365.c (((h->mem[win].addr + h->mem[win].size) >>
h 999 dev/ic/i82365.c pcic_write(h, mem_map_index[win].cardmem_lsb,
h 1000 dev/ic/i82365.c (h->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff);
h 1001 dev/ic/i82365.c pcic_write(h, mem_map_index[win].cardmem_msb,
h 1002 dev/ic/i82365.c ((h->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) &
h 1007 dev/ic/i82365.c reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);
h 1009 dev/ic/i82365.c pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
h 1015 dev/ic/i82365.c r1 = pcic_read(h, mem_map_index[win].sysmem_start_msb);
h 1016 dev/ic/i82365.c r2 = pcic_read(h, mem_map_index[win].sysmem_start_lsb);
h 1017 dev/ic/i82365.c r3 = pcic_read(h, mem_map_index[win].sysmem_stop_msb);
h 1018 dev/ic/i82365.c r4 = pcic_read(h, mem_map_index[win].sysmem_stop_lsb);
h 1019 dev/ic/i82365.c r5 = pcic_read(h, mem_map_index[win].cardmem_msb);
h 1020 dev/ic/i82365.c r6 = pcic_read(h, mem_map_index[win].cardmem_lsb);
h 1038 dev/ic/i82365.c struct pcic_handle *h = (struct pcic_handle *) pch;
h 1042 dev/ic/i82365.c struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent);
h 1047 dev/ic/i82365.c if ((h->memalloc & (1 << i)) == 0) {
h 1049 dev/ic/i82365.c h->memalloc |= (1 << i);
h 1088 dev/ic/i82365.c h->mem[win].addr = busaddr;
h 1089 dev/ic/i82365.c h->mem[win].size = size;
h 1090 dev/ic/i82365.c h->mem[win].offset = card_offset;
h 1091 dev/ic/i82365.c h->mem[win].kind = kind;
h 1093 dev/ic/i82365.c pcic_chip_do_mem_map(h, win);
h 1103 dev/ic/i82365.c struct pcic_handle *h = (struct pcic_handle *) pch;
h 1109 dev/ic/i82365.c reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);
h 1111 dev/ic/i82365.c pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
h 1113 dev/ic/i82365.c h->memalloc &= ~(1 << window);
h 1124 dev/ic/i82365.c struct pcic_handle *h = (struct pcic_handle *) pch;
h 1129 dev/ic/i82365.c struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent);
h 1265 dev/ic/i82365.c pcic_chip_do_io_map(h, win)
h 1266 dev/ic/i82365.c struct pcic_handle *h;
h 1272 dev/ic/i82365.c win, (long) h->io[win].addr, (long) h->io[win].size,
h 1273 dev/ic/i82365.c h->io[win].width * 8));
h 1275 dev/ic/i82365.c pcic_write(h, io_map_index[win].start_lsb, h->io[win].addr & 0xff);
h 1276 dev/ic/i82365.c pcic_write(h, io_map_index[win].start_msb,
h 1277 dev/ic/i82365.c (h->io[win].addr >> 8) & 0xff);
h 1279 dev/ic/i82365.c pcic_write(h, io_map_index[win].stop_lsb,
h 1280 dev/ic/i82365.c (h->io[win].addr + h->io[win].size - 1) & 0xff);
h 1281 dev/ic/i82365.c pcic_write(h, io_map_index[win].stop_msb,
h 1282 dev/ic/i82365.c ((h->io[win].addr + h->io[win].size - 1) >> 8) & 0xff);
h 1284 dev/ic/i82365.c reg = pcic_read(h, PCIC_IOCTL);
h 1286 dev/ic/i82365.c reg |= io_map_index[win].ioctlbits[h->io[win].width];
h 1287 dev/ic/i82365.c pcic_write(h, PCIC_IOCTL, reg);
h 1289 dev/ic/i82365.c reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);
h 1291 dev/ic/i82365.c pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
h 1303 dev/ic/i82365.c struct pcic_handle *h = (struct pcic_handle *) pch;
h 1309 dev/ic/i82365.c struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent);
h 1315 dev/ic/i82365.c if ((h->ioalloc & (1 << i)) == 0) {
h 1317 dev/ic/i82365.c h->ioalloc |= (1 << i);
h 1335 dev/ic/i82365.c h->io[win].addr = ioaddr;
h 1336 dev/ic/i82365.c h->io[win].size = size;
h 1337 dev/ic/i82365.c h->io[win].width = width;
h 1339 dev/ic/i82365.c pcic_chip_do_io_map(h, win);
h 1349 dev/ic/i82365.c struct pcic_handle *h = (struct pcic_handle *) pch;
h 1355 dev/ic/i82365.c reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);
h 1357 dev/ic/i82365.c pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
h 1359 dev/ic/i82365.c h->ioalloc &= ~(1 << window);
h 1363 dev/ic/i82365.c pcic_wait_ready(h)
h 1364 dev/ic/i82365.c struct pcic_handle *h;
h 1369 dev/ic/i82365.c if (pcic_read(h, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY)
h 1380 dev/ic/i82365.c pcic_read(h, PCIC_IF_STATUS));
h 1388 dev/ic/i82365.c struct pcic_handle *h = (struct pcic_handle *) pch;
h 1395 dev/ic/i82365.c pcic_write(h, PCIC_PWRCTL, 0);
h 1403 dev/ic/i82365.c if (h->vendor == PCIC_VENDOR_VADEM_VG469) {
h 1404 dev/ic/i82365.c reg = pcic_read(h, PCIC_VG469_VSELECT);
h 1406 dev/ic/i82365.c pcic_write(h, PCIC_VG469_VSELECT, reg);
h 1411 dev/ic/i82365.c pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_DISABLE_RESETDRV
h 1423 dev/ic/i82365.c pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_DISABLE_RESETDRV |
h 1425 dev/ic/i82365.c pcic_write(h, PCIC_INTR, 0);
h 1434 dev/ic/i82365.c pcic_write(h, PCIC_INTR, PCIC_INTR_RESET);
h 1443 dev/ic/i82365.c reg = pcic_read(h, PCIC_IF_STATUS);
h 1449 dev/ic/i82365.c pcic_wait_ready(h);
h 1453 dev/ic/i82365.c pcic_write(h, PCIC_ADDRWIN_ENABLE, 0);
h 1457 dev/ic/i82365.c cardtype = pcmcia_card_gettype(h->pcmcia);
h 1459 dev/ic/i82365.c reg = pcic_read(h, PCIC_INTR);
h 1464 dev/ic/i82365.c reg |= h->ih_irq;
h 1465 dev/ic/i82365.c pcic_write(h, PCIC_INTR, reg);
h 1468 dev/ic/i82365.c h->ph_parent->dv_xname, h->sock,
h 1474 dev/ic/i82365.c if (h->memalloc & (1 << win))
h 1475 dev/ic/i82365.c pcic_chip_do_mem_map(h, win);
h 1478 dev/ic/i82365.c if (h->ioalloc & (1 << win))
h 1479 dev/ic/i82365.c pcic_chip_do_io_map(h, win);
h 1486 dev/ic/i82365.c struct pcic_handle *h = (struct pcic_handle *) pch;
h 1492 dev/ic/i82365.c pcic_write(h, PCIC_PWRCTL, 0);
h 1501 dev/ic/i82365.c st_pcic_read(h, idx)
h 1502 dev/ic/i82365.c struct pcic_handle *h;
h 1506 dev/ic/i82365.c bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX,
h 1507 dev/ic/i82365.c h->sock + idx);
h 1508 dev/ic/i82365.c return bus_space_read_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA);
h 1512 dev/ic/i82365.c st_pcic_write(h, idx, data)
h 1513 dev/ic/i82365.c struct pcic_handle *h;
h 1518 dev/ic/i82365.c bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX,
h 1519 dev/ic/i82365.c h->sock + idx);
h 1521 dev/ic/i82365.c bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA,
h 182 dev/ic/i82365var.h #define pcic_read(h, idx) \
h 183 dev/ic/i82365var.h (*(h)->ph_read)((h), (idx))
h 185 dev/ic/i82365var.h #define pcic_write(h, idx, data) \
h 186 dev/ic/i82365var.h (*(h)->ph_write)((h), (idx), (data))
h 19 dev/ic/midwayreg.h #define bus_space_read_4(t, h, o) ((void) t, \
h 20 dev/ic/midwayreg.h (*(volatile u_int32_t *)((h) + (o))))
h 21 dev/ic/midwayreg.h #define bus_space_write_4(t, h, o, v) \
h 22 dev/ic/midwayreg.h ((void) t, ((void)(*(volatile u_int32_t *)((h) + (o)) = (v))))
h 307 dev/ic/pdqreg.h #define PDQ_BITFIELD12(a, b, c, d, e, f, g, h, i, j, k, l) \
h 308 dev/ic/pdqreg.h l, k, j, i, h, g, f, e, d, c, b, a
h 314 dev/ic/pdqreg.h #define PDQ_BITFIELD12(a, b, c, d, e, f, g, h, i, j, k, l) \
h 315 dev/ic/pdqreg.h a, b, c, d, e, f, g, h, i, j, k, l
h 510 dev/ic/re.c int h = 0;
h 544 dev/ic/re.c h = (ether_crc32_be(enm->enm_addrlo,
h 546 dev/ic/re.c if (h < 32)
h 547 dev/ic/re.c hashes[0] |= (1 << h);
h 549 dev/ic/re.c hashes[1] |= (1 << (h - 32));
h 467 dev/ic/rtl81x9.c int h = 0;
h 500 dev/ic/rtl81x9.c h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26;
h 501 dev/ic/rtl81x9.c if (h < 32)
h 502 dev/ic/rtl81x9.c hashes[0] |= (1 << h);
h 504 dev/ic/rtl81x9.c hashes[1] |= (1 << (h - 32));
h 704 dev/ic/sti.c sti_bmove(scr, x1, y1, x2, y2, h, w, f)
h 706 dev/ic/sti.c int x1, y1, x2, y2, h, w;
h 738 dev/ic/sti.c a.in.height = h;
h 413 dev/ic/tcic2.c tcic_attach_socket(h)
h 414 dev/ic/tcic2.c struct tcic_handle *h;
h 420 dev/ic/tcic2.c h->shutdown = 0;
h 421 dev/ic/tcic2.c h->memalloc = 0;
h 422 dev/ic/tcic2.c h->ioalloc = 0;
h 423 dev/ic/tcic2.c h->ih_irq = 0;
h 428 dev/ic/tcic2.c paa.pct = (pcmcia_chipset_tag_t) h->sc->pct;
h 429 dev/ic/tcic2.c paa.pch = (pcmcia_chipset_handle_t) h;
h 430 dev/ic/tcic2.c paa.iobase = h->sc->iobase;
h 431 dev/ic/tcic2.c paa.iosize = h->sc->iosize;
h 433 dev/ic/tcic2.c h->pcmcia = config_found_sm(&h->sc->dev, &paa, tcic_print,
h 438 dev/ic/tcic2.c if (h->pcmcia)
h 439 dev/ic/tcic2.c tcic_init_socket(h);
h 441 dev/ic/tcic2.c h->flags &= ~TCIC_FLAG_SOCKETP;
h 448 dev/ic/tcic2.c struct tcic_handle *h = arg;
h 451 dev/ic/tcic2.c switch (h->sock) {
h 462 dev/ic/tcic2.c if (kthread_create(tcic_event_thread, h, &h->event_thread,
h 463 dev/ic/tcic2.c "%s,%s", h->sc->dev.dv_xname, cs)) {
h 465 dev/ic/tcic2.c h->sc->dev.dv_xname, h->sock);
h 474 dev/ic/tcic2.c struct tcic_handle *h = arg;
h 478 dev/ic/tcic2.c while (h->shutdown == 0) {
h 480 dev/ic/tcic2.c if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) {
h 482 dev/ic/tcic2.c (void) tsleep(&h->events, PWAIT, "tcicev", 0);
h 485 dev/ic/tcic2.c SIMPLEQ_REMOVE_HEAD(&h->events, pe_q);
h 490 dev/ic/tcic2.c DPRINTF(("%s: insertion event\n", h->sc->dev.dv_xname));
h 491 dev/ic/tcic2.c tcic_attach_card(h);
h 495 dev/ic/tcic2.c DPRINTF(("%s: removal event\n", h->sc->dev.dv_xname));
h 496 dev/ic/tcic2.c tcic_detach_card(h, DETACH_FORCE);
h 506 dev/ic/tcic2.c h->event_thread = NULL;
h 509 dev/ic/tcic2.c wakeup(h->sc);
h 516 dev/ic/tcic2.c tcic_init_socket(h)
h 517 dev/ic/tcic2.c struct tcic_handle *h;
h 522 dev/ic/tcic2.c tcic_sel_sock(h);
h 525 dev/ic/tcic2.c reg = tcic_read_ind_2(h, TCIC_IR_SCF2_N(h->sock));
h 526 dev/ic/tcic2.c tcic_write_ind_2(h, TCIC_IR_SCF2_N(h->sock), reg & ~TCIC_SCF2_MCD);
h 529 dev/ic/tcic2.c reg = tcic_read_2(h, TCIC_R_IENA);
h 530 dev/ic/tcic2.c tcic_write_2(h, TCIC_R_IENA, reg |= TCIC_IENA_CDCHG);
h 533 dev/ic/tcic2.c h->sstat = reg = tcic_read_1(h, TCIC_R_SSTAT) & TCIC_SSTAT_STAT_MASK;
h 535 dev/ic/tcic2.c tcic_attach_card(h);
h 547 dev/ic/tcic2.c struct tcic_handle *h = (struct tcic_handle *) paa->pch;
h 549 dev/ic/tcic2.c switch (h->sock) {
h 585 dev/ic/tcic2.c struct tcic_handle *h = (struct tcic_handle *) paa->pch;
h 591 dev/ic/tcic2.c switch (h->sock) {
h 621 dev/ic/tcic2.c tcic_intr_socket(h)
h 622 dev/ic/tcic2.c struct tcic_handle *h;
h 627 dev/ic/tcic2.c tcic_sel_sock(h);
h 628 dev/ic/tcic2.c icsr = tcic_read_1(h, TCIC_R_ICSR);
h 630 dev/ic/tcic2.c DPRINTF(("%s: %d icsr: 0x%02x \n", h->sc->dev.dv_xname, h->sock, icsr));
h 634 dev/ic/tcic2.c DPRINTF(("%s: %02x PROGTIME\n", h->sc->dev.dv_xname, h->sock));
h 638 dev/ic/tcic2.c DPRINTF(("%s: %02x ILOCK\n", h->sc->dev.dv_xname, h->sock));
h 642 dev/ic/tcic2.c DPRINTF(("%s: %02x ERR\n", h->sc->dev.dv_xname, h->sock));
h 649 dev/ic/tcic2.c sstat = tcic_read_aux_1(h->sc->iot, h->sc->ioh,
h 651 dev/ic/tcic2.c delta = h->sstat ^ sstat;
h 652 dev/ic/tcic2.c h->sstat = sstat;
h 657 dev/ic/tcic2.c DPRINTF(("%s: %02x CDCHG %x\n", h->sc->dev.dv_xname, h->sock,
h 667 dev/ic/tcic2.c if (!(h->flags & TCIC_FLAG_CARDP)) {
h 669 dev/ic/tcic2.c h->sc->dev.dv_xname));
h 670 dev/ic/tcic2.c tcic_queue_event(h, TCIC_EVENT_INSERTION);
h 673 dev/ic/tcic2.c if (h->flags & TCIC_FLAG_CARDP) {
h 676 dev/ic/tcic2.c h->sc->dev.dv_xname));
h 677 dev/ic/tcic2.c tcic_deactivate_card(h);
h 680 dev/ic/tcic2.c h->sc->dev.dv_xname));
h 681 dev/ic/tcic2.c tcic_queue_event(h, TCIC_EVENT_REMOVAL);
h 686 dev/ic/tcic2.c DPRINTF(("%s: %02x READY\n", h->sc->dev.dv_xname, h->sock));
h 690 dev/ic/tcic2.c DPRINTF(("%s: %02x LBAT1\n", h->sc->dev.dv_xname, h->sock));
h 693 dev/ic/tcic2.c DPRINTF(("%s: %02x LBAT2\n", h->sc->dev.dv_xname, h->sock));
h 696 dev/ic/tcic2.c DPRINTF(("%s: %02x WP\n", h->sc->dev.dv_xname, h->sock));
h 703 dev/ic/tcic2.c tcic_queue_event(h, event)
h 704 dev/ic/tcic2.c struct tcic_handle *h;
h 716 dev/ic/tcic2.c SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q);
h 718 dev/ic/tcic2.c wakeup(&h->events);
h 721 dev/ic/tcic2.c tcic_attach_card(h)
h 722 dev/ic/tcic2.c struct tcic_handle *h;
h 726 dev/ic/tcic2.c if (h->flags & TCIC_FLAG_CARDP)
h 731 dev/ic/tcic2.c pcmcia_card_attach(h->pcmcia);
h 733 dev/ic/tcic2.c h->flags |= TCIC_FLAG_CARDP;
h 737 dev/ic/tcic2.c tcic_detach_card(h, flags)
h 738 dev/ic/tcic2.c struct tcic_handle *h;
h 743 dev/ic/tcic2.c if (!(h->flags & TCIC_FLAG_CARDP))
h 746 dev/ic/tcic2.c h->flags &= ~TCIC_FLAG_CARDP;
h 750 dev/ic/tcic2.c pcmcia_card_detach(h->pcmcia, flags);
h 755 dev/ic/tcic2.c tcic_deactivate_card(h)
h 756 dev/ic/tcic2.c struct tcic_handle *h;
h 760 dev/ic/tcic2.c if (!(h->flags & TCIC_FLAG_CARDP))
h 764 dev/ic/tcic2.c pcmcia_card_deactivate(h->pcmcia);
h 766 dev/ic/tcic2.c tcic_sel_sock(h);
h 771 dev/ic/tcic2.c tcic_write_1(h, TCIC_R_PWR, 0);
h 776 dev/ic/tcic2.c reg = TCIC_IR_SCF1_N(h->sock);
h 777 dev/ic/tcic2.c val = tcic_read_ind_2(h, reg);
h 778 dev/ic/tcic2.c tcic_write_ind_2(h, reg, (val & ~TCIC_SCF1_IRQ_MASK)|TCIC_SCF1_IRQOFF);
h 779 dev/ic/tcic2.c reg = TCIC_IR_SCF2_N(h->sock);
h 780 dev/ic/tcic2.c val = tcic_read_ind_2(h, reg);
h 781 dev/ic/tcic2.c tcic_write_ind_2(h, reg,
h 793 dev/ic/tcic2.c struct tcic_handle *h = (struct tcic_handle *) pch;
h 823 dev/ic/tcic2.c if ((h->sc->subregionmask & (mask << i)) == (mask << i)) {
h 824 dev/ic/tcic2.c if (bus_space_subregion(h->sc->memt, h->sc->memh,
h 829 dev/ic/tcic2.c addr = h->sc->membase + (i * TCIC_MEM_PAGESIZE);
h 830 dev/ic/tcic2.c h->sc->subregionmask &= ~(mhandle);
h 841 dev/ic/tcic2.c pcmhp->memt = h->sc->memt;
h 857 dev/ic/tcic2.c struct tcic_handle *h = (struct tcic_handle *) pch;
h 859 dev/ic/tcic2.c h->sc->subregionmask |= pcmhp->mhandle;
h 863 dev/ic/tcic2.c tcic_chip_do_mem_map(h, win)
h 864 dev/ic/tcic2.c struct tcic_handle *h;
h 869 dev/ic/tcic2.c int kind = h->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK;
h 870 dev/ic/tcic2.c int mem8 = (h->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8;
h 872 dev/ic/tcic2.c win, (u_long)h->mem[win].addr, (u_long)h->mem[win].size,
h 873 dev/ic/tcic2.c (u_long)h->mem[win].offset));
h 878 dev/ic/tcic2.c hwwin = (win << 1) + h->sock;
h 881 dev/ic/tcic2.c tcic_write_ind_2(h, TCIC_WR_MEXT_N(hwwin), 0);
h 884 dev/ic/tcic2.c if (h->mem[win].size2 <= 1) {
h 885 dev/ic/tcic2.c reg = ((h->mem[win].addr >> TCIC_MEM_SHIFT) &
h 888 dev/ic/tcic2.c reg = ((h->mem[win].addr >> TCIC_MEM_SHIFT) &
h 889 dev/ic/tcic2.c TCIC_MBASE_ADDR_MASK) | (h->mem[win].size2 >> 1);
h 891 dev/ic/tcic2.c tcic_write_ind_2(h, TCIC_WR_MBASE_N(hwwin), reg);
h 895 dev/ic/tcic2.c reg = ((h->mem[win].offset >> TCIC_MEM_SHIFT) & TCIC_MMAP_ADDR_MASK);
h 899 dev/ic/tcic2.c tcic_write_ind_2(h, TCIC_WR_MMAP_N(hwwin), reg);
h 904 dev/ic/tcic2.c reg = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin)) & TCIC_MCTL_WSCNT_MASK;
h 907 dev/ic/tcic2.c reg |= (h->sock << TCIC_MCTL_SS_SHIFT) & TCIC_MCTL_SS_MASK;
h 909 dev/ic/tcic2.c wscnt = tcic_ns2wscnt(h->mem[win].speed);
h 913 dev/ic/tcic2.c if (h->sc->chipid == TCIC_CHIPID_DB86082_1) {
h 919 dev/ic/tcic2.c reg2 = tcic_read_ind_2(h, TCIC_WR_MCTL_N(7-hwwin));
h 922 dev/ic/tcic2.c tcic_write_ind_2(h, TCIC_WR_MCTL_N(7-hwwin), reg2);
h 926 dev/ic/tcic2.c tcic_write_ind_2(h, TCIC_WR_MCTL_N(hwwin), reg);
h 932 dev/ic/tcic2.c r1 = tcic_read_ind_2(h, TCIC_WR_MBASE_N(hwwin));
h 933 dev/ic/tcic2.c r2 = tcic_read_ind_2(h, TCIC_WR_MMAP_N(hwwin));
h 934 dev/ic/tcic2.c r3 = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin));
h 953 dev/ic/tcic2.c struct tcic_handle *h = (struct tcic_handle *) pch;
h 959 dev/ic/tcic2.c for (i = 0; i < h->memwins; i++) {
h 960 dev/ic/tcic2.c if ((h->memalloc & (1 << i)) == 0) {
h 962 dev/ic/tcic2.c h->memalloc |= (1 << i);
h 974 dev/ic/tcic2.c if (h->sc->memt != pcmhp->memt)
h 1005 dev/ic/tcic2.c h->mem[win].addr = busaddr;
h 1006 dev/ic/tcic2.c h->mem[win].size = size;
h 1007 dev/ic/tcic2.c h->mem[win].size2 = tcic_log2((u_int)pcmhp->realsize) - TCIC_MEM_SHIFT;
h 1008 dev/ic/tcic2.c h->mem[win].offset = card_offset;
h 1009 dev/ic/tcic2.c h->mem[win].kind = kind;
h 1011 dev/ic/tcic2.c tcic_chip_do_mem_map(h, win);
h 1021 dev/ic/tcic2.c struct tcic_handle *h = (struct tcic_handle *) pch;
h 1024 dev/ic/tcic2.c if (window >= h->memwins)
h 1027 dev/ic/tcic2.c hwwin = (window << 1) + h->sock;
h 1028 dev/ic/tcic2.c reg = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin));
h 1030 dev/ic/tcic2.c tcic_write_ind_2(h, TCIC_WR_MCTL_N(hwwin), reg);
h 1032 dev/ic/tcic2.c h->memalloc &= ~(1 << window);
h 1043 dev/ic/tcic2.c struct tcic_handle *h = (struct tcic_handle *) pch;
h 1074 dev/ic/tcic2.c iot = h->sc->iot;
h 1084 dev/ic/tcic2.c if (bus_space_alloc(iot, h->sc->iobase,
h 1085 dev/ic/tcic2.c h->sc->iobase + h->sc->iosize, size, align, 0, 0,
h 1120 dev/ic/tcic2.c tcic_chip_do_io_map(h, win)
h 1121 dev/ic/tcic2.c struct tcic_handle *h;
h 1127 dev/ic/tcic2.c win, (long) h->io[win].addr, (long) h->io[win].size,
h 1128 dev/ic/tcic2.c h->io[win].width * 8));
h 1134 dev/ic/tcic2.c hwwin = (win << 1) + h->sock;
h 1138 dev/ic/tcic2.c size2 = tcic_log2((u_int)h->io[win].size);
h 1142 dev/ic/tcic2.c wbase = h->io[win].addr;
h 1146 dev/ic/tcic2.c wbase = h->io[win].addr | (1 << (size2 - 1));
h 1148 dev/ic/tcic2.c tcic_write_ind_2(h, TCIC_WR_IBASE_N(hwwin), wbase);
h 1152 dev/ic/tcic2.c reg |= (h->sock << TCIC_ICTL_SS_SHIFT) & TCIC_ICTL_SS_MASK;
h 1153 dev/ic/tcic2.c reg |= iotiny | tcic_iowidth_map[h->io[win].width];
h 1154 dev/ic/tcic2.c if (h->sc->chipid != TCIC_CHIPID_DB86082_1)
h 1157 dev/ic/tcic2.c wscnt = tcic_ns2wscnt(h->io[win].speed);
h 1162 dev/ic/tcic2.c tcic_write_ind_2(h, TCIC_WR_ICTL_N(hwwin), reg);
h 1168 dev/ic/tcic2.c r1 = tcic_read_ind_2(h, TCIC_WR_IBASE_N(hwwin));
h 1169 dev/ic/tcic2.c r2 = tcic_read_ind_2(h, TCIC_WR_ICTL_N(hwwin));
h 1186 dev/ic/tcic2.c struct tcic_handle *h = (struct tcic_handle *) pch;
h 1197 dev/ic/tcic2.c if ((h->ioalloc & (1 << i)) == 0) {
h 1199 dev/ic/tcic2.c h->ioalloc |= (1 << i);
h 1211 dev/ic/tcic2.c if (h->sc->iot != pcihp->iot)
h 1223 dev/ic/tcic2.c h->io[win].addr = ioaddr;
h 1224 dev/ic/tcic2.c h->io[win].size = size;
h 1225 dev/ic/tcic2.c h->io[win].width = width;
h 1227 dev/ic/tcic2.c tcic_chip_do_io_map(h, win);
h 1237 dev/ic/tcic2.c struct tcic_handle *h = (struct tcic_handle *) pch;
h 1243 dev/ic/tcic2.c hwwin = (window << 1) + h->sock;
h 1244 dev/ic/tcic2.c reg = tcic_read_ind_2(h, TCIC_WR_ICTL_N(hwwin));
h 1246 dev/ic/tcic2.c tcic_write_ind_2(h, TCIC_WR_ICTL_N(hwwin), reg);
h 1248 dev/ic/tcic2.c h->ioalloc &= ~(1 << window);
h 1255 dev/ic/tcic2.c struct tcic_handle *h = (struct tcic_handle *) pch;
h 1258 dev/ic/tcic2.c tcic_sel_sock(h);
h 1265 dev/ic/tcic2.c tcic_write_1(h, TCIC_R_PWR, 0);
h 1266 dev/ic/tcic2.c reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK);
h 1269 dev/ic/tcic2.c tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg);
h 1270 dev/ic/tcic2.c tcic_write_1(h, TCIC_R_SCTRL, 0); /* clear TCIC_SCTRL_ENA */
h 1275 dev/ic/tcic2.c reg = TCIC_PWR_VCC_N(h->sock) | TCIC_PWR_VPP_N(h->sock) | h->sc->pwrena;
h 1276 dev/ic/tcic2.c if (h->sc->pwrena) /* this is a '84 type chip */
h 1278 dev/ic/tcic2.c tcic_write_1(h, TCIC_R_PWR, reg);
h 1282 dev/ic/tcic2.c reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK);
h 1284 dev/ic/tcic2.c tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg);
h 1287 dev/ic/tcic2.c tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg);
h 1289 dev/ic/tcic2.c tcic_write_1(h, TCIC_R_SCTRL, TCIC_SCTRL_ENA);
h 1293 dev/ic/tcic2.c reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK);
h 1295 dev/ic/tcic2.c tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg);
h 1301 dev/ic/tcic2.c tcic_wait_ready(h);
h 1307 dev/ic/tcic2.c for (win = 0; win < h->memwins; win++) {
h 1308 dev/ic/tcic2.c tcic_write_ind_2(h, TCIC_WR_MBASE_N((win<<1)+h->sock), 0);
h 1312 dev/ic/tcic2.c tcic_write_ind_2(h, TCIC_WR_IBASE_N((win<<1)+h->sock), 0);
h 1317 dev/ic/tcic2.c cardtype = pcmcia_card_gettype(h->pcmcia);
h 1320 dev/ic/tcic2.c reg = tcic_read_ind_2(h, TCIC_IR_SCF1_N(h->sock));
h 1327 dev/ic/tcic2.c reg |= tcic_irqmap[h->ih_irq]; /* enable interrupts */
h 1329 dev/ic/tcic2.c tcic_write_ind_2(h, TCIC_IR_SCF1_N(h->sock), reg);
h 1332 dev/ic/tcic2.c h->sc->dev.dv_xname, h->sock,
h 1337 dev/ic/tcic2.c for (win = 0; win < h->memwins; win++)
h 1338 dev/ic/tcic2.c if (h->memalloc & (1 << win))
h 1339 dev/ic/tcic2.c tcic_chip_do_mem_map(h, win);
h 1342 dev/ic/tcic2.c if (h->ioalloc & (1 << win))
h 1343 dev/ic/tcic2.c tcic_chip_do_io_map(h, win);
h 1350 dev/ic/tcic2.c struct tcic_handle *h = (struct tcic_handle *) pch;
h 1355 dev/ic/tcic2.c tcic_sel_sock(h);
h 1358 dev/ic/tcic2.c val = tcic_read_ind_2(h, TCIC_IR_SCF1_N(h->sock));
h 1360 dev/ic/tcic2.c tcic_write_ind_2(h, TCIC_IR_SCF1_N(h->sock), val);
h 1363 dev/ic/tcic2.c tcic_write_1(h, TCIC_R_SCTRL, 0);
h 1364 dev/ic/tcic2.c val = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK);
h 1366 dev/ic/tcic2.c tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, val);
h 1369 dev/ic/tcic2.c tcic_write_1(h, TCIC_R_PWR, 0);
h 188 dev/ic/tcic2var.h tcic_read_1(h, reg)
h 189 dev/ic/tcic2var.h struct tcic_handle *h;
h 192 dev/ic/tcic2var.h return (bus_space_read_1(h->sc->iot, h->sc->ioh, reg));
h 197 dev/ic/tcic2var.h tcic_read_2(h, reg)
h 198 dev/ic/tcic2var.h struct tcic_handle *h;
h 201 dev/ic/tcic2var.h return (bus_space_read_2(h->sc->iot, h->sc->ioh, reg));
h 206 dev/ic/tcic2var.h tcic_read_4(h, reg)
h 207 dev/ic/tcic2var.h struct tcic_handle *h;
h 211 dev/ic/tcic2var.h val = bus_space_read_2(h->sc->iot, h->sc->ioh, reg);
h 212 dev/ic/tcic2var.h val |= bus_space_read_2(h->sc->iot, h->sc->ioh, reg+2) << 16;
h 218 dev/ic/tcic2var.h tcic_write_1(h, reg, data)
h 219 dev/ic/tcic2var.h struct tcic_handle *h;
h 223 dev/ic/tcic2var.h bus_space_write_1(h->sc->iot, h->sc->ioh, reg, (data));
h 228 dev/ic/tcic2var.h tcic_write_2(h, reg, data)
h 229 dev/ic/tcic2var.h struct tcic_handle *h;
h 233 dev/ic/tcic2var.h bus_space_write_2(h->sc->iot, h->sc->ioh, reg, (data));
h 238 dev/ic/tcic2var.h tcic_write_4(h, reg, data)
h 239 dev/ic/tcic2var.h struct tcic_handle *h;
h 243 dev/ic/tcic2var.h bus_space_write_2(h->sc->iot, h->sc->ioh, reg, (data));
h 244 dev/ic/tcic2var.h bus_space_write_2(h->sc->iot, h->sc->ioh, reg+2, (data)>>16);
h 249 dev/ic/tcic2var.h tcic_read_ind_2(h, reg)
h 250 dev/ic/tcic2var.h struct tcic_handle *h;
h 254 dev/ic/tcic2var.h r_addr = tcic_read_4(h, TCIC_R_ADDR);
h 255 dev/ic/tcic2var.h tcic_write_4(h, TCIC_R_ADDR, reg|TCIC_ADDR_INDREG);
h 256 dev/ic/tcic2var.h val = bus_space_read_2(h->sc->iot, h->sc->ioh, TCIC_R_DATA);
h 257 dev/ic/tcic2var.h tcic_write_4(h, TCIC_R_ADDR, r_addr);
h 263 dev/ic/tcic2var.h tcic_write_ind_2(h, reg, data)
h 264 dev/ic/tcic2var.h struct tcic_handle *h;
h 269 dev/ic/tcic2var.h r_addr = tcic_read_4(h, TCIC_R_ADDR);
h 270 dev/ic/tcic2var.h tcic_write_4(h, TCIC_R_ADDR, reg|TCIC_ADDR_INDREG);
h 271 dev/ic/tcic2var.h bus_space_write_2(h->sc->iot, h->sc->ioh, TCIC_R_DATA, (data));
h 272 dev/ic/tcic2var.h tcic_write_4(h, TCIC_R_ADDR, r_addr);
h 277 dev/ic/tcic2var.h tcic_sel_sock(h)
h 278 dev/ic/tcic2var.h struct tcic_handle *h;
h 281 dev/ic/tcic2var.h r_addr = tcic_read_2(h, TCIC_R_ADDR2);
h 282 dev/ic/tcic2var.h tcic_write_2(h, TCIC_R_ADDR2,
h 283 dev/ic/tcic2var.h (h->sock<<TCIC_ADDR2_SS_SHFT)|(r_addr & ~TCIC_ADDR2_SS_MASK));
h 288 dev/ic/tcic2var.h tcic_wait_ready(h)
h 289 dev/ic/tcic2var.h struct tcic_handle *h;
h 295 dev/ic/tcic2var.h if (tcic_read_1(h, TCIC_R_SSTAT) & TCIC_SSTAT_RDY)
h 168 dev/ic/twereg.h #define TWE_UNITHOST(u, h) (((u) & 0xf) | ((h) << 4))
h 596 dev/ic/xl.c int h = 0, i;
h 628 dev/ic/xl.c h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) &
h 630 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h);
h 105 dev/isa/ess.c #define EREAD1(t, h, a) (uuu=bus_space_read_1(t, h, a),printf("EREAD %02x=%02x\n", ((int)h&0xfff)+a, uuu),uuu)
h 106 dev/isa/ess.c #define EWRITE1(t, h, a, d) (printf("EWRITE %02x=%02x\n", ((int)h & 0xfff)+a, d), bus_space_write_1(t, h, a, d))
h 108 dev/isa/ess.c #define EREAD1(t, h, a) bus_space_read_1(t, h, a)
h 109 dev/isa/ess.c #define EWRITE1(t, h, a, d) bus_space_write_1(t, h, a, d)
h 84 dev/isa/ess_isapnp.c sc->sc_ioh = ia->ipa_io[0].h;
h 161 dev/isa/gus_isapnp.c sc->sc_ioh1 = ipa->ipa_io[0].h; /* p2xr */
h 162 dev/isa/gus_isapnp.c sc->sc_ioh2 = ipa->ipa_io[1].h; /* p3xr */
h 163 dev/isa/gus_isapnp.c sc->sc_ioh3 = ipa->ipa_io[2].h; /* codec/mixer */
h 159 dev/isa/i82365_isa.c struct pcic_handle *h;
h 219 dev/isa/i82365_isa.c h = &sc->handle[i];
h 220 dev/isa/i82365_isa.c if (h->flags & PCIC_FLAG_SOCKETP) {
h 221 dev/isa/i82365_isa.c pcic_write(h, PCIC_CSC_INTR,
h 224 dev/isa/i82365_isa.c powerhook_establish(pcic_power, h);
h 108 dev/isa/i82365_isapnp.c struct pcic_handle *h;
h 135 dev/isa/i82365_isapnp.c ioh = ipa->ipa_io[0].h;
h 197 dev/isa/i82365_isapnp.c h = &sc->handle[i];
h 198 dev/isa/i82365_isapnp.c if (h->flags & PCIC_FLAG_SOCKETP) {
h 199 dev/isa/i82365_isapnp.c pcic_write(h, PCIC_CSC_INTR,
h 202 dev/isa/i82365_isapnp.c powerhook_establish(pcic_power, h);
h 193 dev/isa/i82365_isasubr.c struct pcic_handle *h = (struct pcic_handle *)pch;
h 194 dev/isa/i82365_isasubr.c struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent);
h 209 dev/isa/i82365_isasubr.c h->ih_irq = irq;
h 210 dev/isa/i82365_isasubr.c reg = pcic_read(h, PCIC_INTR);
h 212 dev/isa/i82365_isasubr.c pcic_write(h, PCIC_INTR, reg | irq);
h 215 dev/isa/i82365_isasubr.c h->pcmcia->dv_xname);
h 223 dev/isa/i82365_isasubr.c struct pcic_handle *h = (struct pcic_handle *) pch;
h 224 dev/isa/i82365_isasubr.c struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent);
h 228 dev/isa/i82365_isasubr.c h->ih_irq = 0;
h 232 dev/isa/i82365_isasubr.c reg = pcic_read(h, PCIC_INTR);
h 234 dev/isa/i82365_isasubr.c pcic_write(h, PCIC_INTR, reg);
h 242 dev/isa/i82365_isasubr.c struct pcic_handle *h = (struct pcic_handle *)pch;
h 248 dev/isa/i82365_isasubr.c snprintf(irqstr, sizeof(irqstr), "irq %d", h->ih_irq);
h 74 dev/isa/if_an_isapnp.c sc->sc_ioh = ia->ipa_io[0].h;
h 167 dev/isa/if_ef_isapnp.c sc->sc_ioh = ioh = ia->ipa_io[0].h;
h 118 dev/isa/if_ep_isapnp.c sc->sc_ioh = ioh = ia->ipa_io[0].h;
h 93 dev/isa/if_le_isapnp.c lesc->sc_ioh = ioh = ia->ipa_io[0].h;
h 120 dev/isa/if_ne_isapnp.c nich = ipa->ipa_io[0].h;
h 202 dev/isa/isapnp.c bus_space_unmap(t, r->h, r->length);
h 203 dev/isa/isapnp.c r->h = NULL;
h 220 dev/isa/isapnp.c r->h = NULL;
h 223 dev/isa/isapnp.c error = bus_space_map(t, r->base, r->length, 0, &r->h);
h 213 dev/isa/isavar.h bus_space_handle_t h;
h 294 dev/isa/isavar.h #define ia_ioh ipa_io[0].h
h 300 dev/isa/isavar.h #define ia_memh ipa_mem[0].h
h 62 dev/isa/mpu_isapnp.c sc->sc_mpu.ioh = ipa->ipa_io[0].h;
h 66 dev/isa/rt_isapnp.c sc->lm.ioh = ia->ipa_io[0].h; /* ia_ioh */
h 98 dev/isa/sb_isapnp.c sc->sc_ioh = ia->ipa_io[0].h;
h 117 dev/isa/sb_isapnp.c sc->sc_mpu_sc.ioh = ia->ipa_io[1].h;
h 319 dev/isa/tcic2_isa.c struct tcic_handle *h = (struct tcic_handle *) pch;
h 329 dev/isa/tcic2_isa.c DPRINTF(("%s: tcic_isa_chip_intr_establish\n", h->sc->dev.dv_xname));
h 339 dev/isa/tcic2_isa.c if (isa_intr_alloc(h->sc->intr_est,
h 340 dev/isa/tcic2_isa.c h->sc->validirqs & tcic_isa_intr_alloc_mask, ist, &irq))
h 342 dev/isa/tcic2_isa.c if ((ih = isa_intr_establish(h->sc->intr_est, irq, ist, ipl,
h 343 dev/isa/tcic2_isa.c fct, arg, h->pcmcia->dv_xname)) == NULL)
h 346 dev/isa/tcic2_isa.c DPRINTF(("%s: intr established\n", h->sc->dev.dv_xname));
h 348 dev/isa/tcic2_isa.c h->ih_irq = irq;
h 350 dev/isa/tcic2_isa.c reg = TCIC_IR_SCF1_N(h->sock);
h 351 dev/isa/tcic2_isa.c val = (tcic_read_ind_2(h, reg) & (~TCIC_SCF1_IRQ_MASK)) | irqmap[irq];
h 352 dev/isa/tcic2_isa.c tcic_write_ind_2(h, reg, val);
h 363 dev/isa/tcic2_isa.c struct tcic_handle *h = (struct tcic_handle *) pch;
h 366 dev/isa/tcic2_isa.c DPRINTF(("%s: tcic_isa_chip_intr_disestablish\n", h->sc->dev.dv_xname));
h 368 dev/isa/tcic2_isa.c h->ih_irq = 0;
h 370 dev/isa/tcic2_isa.c reg = TCIC_IR_SCF1_N(h->sock);
h 371 dev/isa/tcic2_isa.c val = tcic_read_ind_2(h, reg);
h 373 dev/isa/tcic2_isa.c tcic_write_ind_2(h, reg, val);
h 375 dev/isa/tcic2_isa.c isa_intr_disestablish(h->sc->intr_est, ih);
h 383 dev/isa/tcic2_isa.c struct tcic_handle *h = (struct tcic_handle *) pch;
h 389 dev/isa/tcic2_isa.c snprintf(irqstr, sizeof(irqstr), "irq %d", h->ih_irq);
h 114 dev/isa/wdc_isapnp.c sc->wdc_channel.cmd_ioh = ipa->ipa_io[0].h;
h 115 dev/isa/wdc_isapnp.c sc->wdc_channel.ctl_ioh = ipa->ipa_io[1].h;
h 117 dev/isa/wdc_isapnp.c sc->wdc_channel.cmd_ioh = ipa->ipa_io[1].h;
h 118 dev/isa/wdc_isapnp.c sc->wdc_channel.ctl_ioh = ipa->ipa_io[0].h;
h 105 dev/isa/wss_isapnp.c sc->sc_ioh = ipa->ipa_io[0].h;
h 101 dev/isa/ym_isapnp.c sc->sc_ioh = ia->ipa_io[1].h;
h 108 dev/isa/ym_isapnp.c sc->sc_controlioh = ia->ipa_io[4].h;
h 119 dev/isa/ym_isapnp.c sc->sc_mpu_sc.ioh = ia->ipa_io[3].h;
h 673 dev/microcode/siop/ncr53cxxx.c struct patchlist *p, **h;
h 675 dev/microcode/siop/ncr53cxxx.c h = &patches;
h 676 dev/microcode/siop/ncr53cxxx.c while(*h)
h 677 dev/microcode/siop/ncr53cxxx.c h = &(*h)->next;
h 679 dev/microcode/siop/ncr53cxxx.c *h = p;
h 1068 dev/pci/emuxki.c chan->fxsend.g.level = chan->fxsend.h.level =
h 1080 dev/pci/emuxki.c chan->fxsend.h.dest = 0x7;
h 1166 dev/pci/emuxki.c chan->fxsend.h.level = fxsend->h.level;
h 1170 dev/pci/emuxki.c chan->fxsend.h.dest = fxsend->h.dest;
h 1207 dev/pci/emuxki.c (chan->fxsend.h.dest << 24) |
h 1215 dev/pci/emuxki.c (chan->fxsend.h.level));
h 1559 dev/pci/emuxki.c fxsend.h.dest = 0x7;
h 1564 dev/pci/emuxki.c fxsend.f.level = fxsend.h.level = 0x00;
h 1570 dev/pci/emuxki.c fxsend.f.level = fxsend.h.level = 0xc0;
h 98 dev/pci/emuxkivar.h } a, b, c, d, e, f, g, h;
h 110 dev/pci/i82365_pci.c struct pcic_handle *h;
h 196 dev/pci/i82365_pci.c h = &sc->handle[i];
h 197 dev/pci/i82365_pci.c if (h->flags & PCIC_FLAG_SOCKETP) {
h 198 dev/pci/i82365_pci.c pcic_write(h, PCIC_CSC_INTR,
h 201 dev/pci/i82365_pci.c powerhook_establish(pcic_power, h);
h 1070 dev/pci/if_bge.c u_int32_t h, rxmode;
h 1085 dev/pci/if_bge.c h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
h 1086 dev/pci/if_bge.c setbit(hashes, h & 0x7F);
h 4781 dev/pci/if_bnx.c int h, i;
h 4825 dev/pci/if_bnx.c h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) &
h 4827 dev/pci/if_bnx.c hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
h 647 dev/pci/if_cas.c cas_bitwait(struct cas_softc *sc, bus_space_handle_t h, int r,
h 654 dev/pci/if_cas.c reg = bus_space_read_4(sc->sc_memt, h, r);
h 666 dev/pci/if_cas.c bus_space_handle_t h = sc->sc_memh;
h 675 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_RESET, CAS_RESET_RX|CAS_RESET_TX);
h 676 dev/pci/if_cas.c if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0))
h 745 dev/pci/if_cas.c bus_space_handle_t h = sc->sc_memh;
h 752 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_RX_CONFIG, 0);
h 754 dev/pci/if_cas.c if (!cas_bitwait(sc, h, CAS_RX_CONFIG, 1, 0))
h 760 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_RESET, CAS_RESET_RX);
h 762 dev/pci/if_cas.c if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX, 0)) {
h 777 dev/pci/if_cas.c bus_space_handle_t h = sc->sc_memh;
h 784 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_TX_CONFIG, 0);
h 786 dev/pci/if_cas.c if (!cas_bitwait(sc, h, CAS_TX_CONFIG, 1, 0))
h 792 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_RESET, CAS_RESET_TX);
h 794 dev/pci/if_cas.c if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_TX, 0)) {
h 809 dev/pci/if_cas.c bus_space_handle_t h = sc->sc_memh;
h 813 dev/pci/if_cas.c cfg = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG);
h 815 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, cfg);
h 818 dev/pci/if_cas.c return (cas_bitwait(sc, h, CAS_MAC_RX_CONFIG, CAS_MAC_RX_ENABLE, 0));
h 828 dev/pci/if_cas.c bus_space_handle_t h = sc->sc_memh;
h 832 dev/pci/if_cas.c cfg = bus_space_read_4(t, h, CAS_MAC_TX_CONFIG);
h 834 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_TX_CONFIG, cfg);
h 837 dev/pci/if_cas.c return (cas_bitwait(sc, h, CAS_MAC_TX_CONFIG, CAS_MAC_TX_ENABLE, 0));
h 936 dev/pci/if_cas.c bus_space_handle_t h = sc->sc_memh;
h 966 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v);
h 973 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_TX_RING_PTR_HI,
h 975 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_TX_RING_PTR_LO, CAS_CDTXADDR(sc, 0));
h 978 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI,
h 980 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO, CAS_CDRXADDR(sc, 0));
h 983 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_RX_CRING_PTR_HI,
h 985 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_RX_CRING_PTR_LO, CAS_CDRXCADDR(sc, 0));
h 988 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_INTMASK,
h 996 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_RX_MASK,
h 998 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_TX_MASK, CAS_MAC_TX_XMIT_DONE);
h 999 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_CONTROL_MASK, 0); /* XXXX */
h 1005 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_TX_CONFIG,
h 1007 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_TX_KICK, 0);
h 1018 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_RX_CONFIG,
h 1025 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_RX_PAUSE_THRESH,
h 1028 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_RX_BLANKING, (6<<12)|6);
h 1034 dev/pci/if_cas.c v = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG);
h 1036 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, v);
h 1041 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_RX_KICK, CAS_NRXDESC-4);
h 1058 dev/pci/if_cas.c bus_space_handle_t h = sc->sc_memh;
h 1066 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_IPG0, 0);
h 1067 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_IPG1, 8);
h 1068 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_IPG2, 4);
h 1070 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN);
h 1073 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v);
h 1075 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_PREAMBLE_LEN, 0x7);
h 1076 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_JAM_SIZE, 0x4);
h 1077 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_ATTEMPT_LIMIT, 0x10);
h 1079 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_CONTROL_TYPE, 0x8088);
h 1080 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_RANDOM_SEED,
h 1085 dev/pci/if_cas.c bus_space_write_4(t, h, r, 0);
h 1088 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_ADDR42, 0x0001);
h 1089 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_ADDR43, 0xc200);
h 1090 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_ADDR44, 0x0180);
h 1093 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER0, 0);
h 1094 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER1, 0);
h 1095 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER2, 0);
h 1097 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK1_2, 0);
h 1098 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK0, 0);
h 1102 dev/pci/if_cas.c bus_space_write_4(t, h, r, 0);
h 1108 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_NORM_COLL_CNT, 0);
h 1109 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_FIRST_COLL_CNT, 0);
h 1110 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_EXCESS_COLL_CNT, 0);
h 1111 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_LATE_COLL_CNT, 0);
h 1112 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_DEFER_TMR_CNT, 0);
h 1113 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_PEAK_ATTEMPTS, 0);
h 1114 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_RX_FRAME_COUNT, 0);
h 1115 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_RX_LEN_ERR_CNT, 0);
h 1116 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_RX_ALIGN_ERR, 0);
h 1117 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_RX_CRC_ERR_CNT, 0);
h 1118 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_RX_CODE_VIOL, 0);
h 1121 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_SEND_PAUSE_CMD, 0);
h 1126 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_ADDR0,
h 1128 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_ADDR1,
h 1130 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_ADDR2,
h 1142 dev/pci/if_cas.c bus_space_handle_t h = sc->sc_memh;
h 1254 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_RX_COMP_TAIL, sc->sc_rxptr);
h 1257 dev/pci/if_cas.c sc->sc_rxptr, bus_space_read_4(t, h, CAS_RX_COMPLETION)));
h 1271 dev/pci/if_cas.c bus_space_handle_t h = sc->sc_memh;
h 1276 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_RX_KICK, sc->sc_rxdptr);
h 1760 dev/pci/if_cas.c bus_space_handle_t h = sc->sc_memh;
h 1765 dev/pci/if_cas.c v = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG);
h 1829 dev/pci/if_cas.c bus_space_write_4(t, h,
h 1835 dev/pci/if_cas.c bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, v);
h 325 dev/pci/if_lge.c u_int32_t h = 0, hashes[2] = { 0, 0 };
h 348 dev/pci/if_lge.c h = (ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26) &
h 350 dev/pci/if_lge.c if (h < 32)
h 351 dev/pci/if_lge.c hashes[0] |= (1 << h);
h 353 dev/pci/if_lge.c hashes[1] |= (1 << (h - 32));
h 370 dev/pci/if_msk.c int h;
h 396 dev/pci/if_msk.c h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) &
h 398 dev/pci/if_msk.c if (h < 32)
h 399 dev/pci/if_msk.c hashes[0] |= (1 << h);
h 401 dev/pci/if_msk.c hashes[1] |= (1 << (h - 32));
h 614 dev/pci/if_nge.c u_int32_t h = 0, i, filtsave;
h 655 dev/pci/if_nge.c h = (ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 21) &
h 657 dev/pci/if_nge.c index = (h >> 4) & 0x7F;
h 658 dev/pci/if_nge.c bit = h & 0xF;
h 721 dev/pci/if_sis.c u_int32_t h = 0, i, filtsave;
h 759 dev/pci/if_sis.c h = sis_mchash(sc, enm->enm_addrlo);
h 760 dev/pci/if_sis.c index = h >> 3;
h 761 dev/pci/if_sis.c bit = h & 0x1F;
h 779 dev/pci/if_sis.c u_int32_t h, i, n, ctl;
h 814 dev/pci/if_sis.c h = sis_mchash(sc, enm->enm_addrlo);
h 815 dev/pci/if_sis.c hashes[h >> 4] |= 1 << (h & 0xf);
h 435 dev/pci/if_sk.c int h, i;
h 487 dev/pci/if_sk.c h = sk_xmac_hash(enm->enm_addrlo);
h 493 dev/pci/if_sk.c h = sk_yukon_hash(enm->enm_addrlo);
h 496 dev/pci/if_sk.c if (h < 32)
h 497 dev/pci/if_sk.c hashes[0] |= (1 << h);
h 499 dev/pci/if_sk.c hashes[1] |= (1 << (h - 32));
h 512 dev/pci/if_ste.c int h = 0;
h 536 dev/pci/if_ste.c h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 0x3F;
h 537 dev/pci/if_ste.c if (h < 32)
h 538 dev/pci/if_ste.c hashes[0] |= (1 << h);
h 540 dev/pci/if_ste.c hashes[1] |= (1 << (h - 32));
h 868 dev/pci/if_tl.c int h;
h 882 dev/pci/if_tl.c h = tl_calchash(enm->enm_addrlo);
h 883 dev/pci/if_tl.c hashes[h/32] |= (1 << (h % 32));
h 893 dev/pci/if_tl.c h = 0;
h 895 dev/pci/if_tl.c h++;
h 898 dev/pci/if_tl.c if (h) {
h 482 dev/pci/if_vge.c u_int32_t h = 0, hashes[2] = { 0, 0 };
h 521 dev/pci/if_vge.c h = ether_crc32_be(enm->enm_addrlo,
h 523 dev/pci/if_vge.c hashes[h >> 5] |= 1 << (h & 0x1f);
h 492 dev/pci/if_vr.c int h = 0;
h 524 dev/pci/if_vr.c h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26;
h 525 dev/pci/if_vr.c if (h < 32)
h 526 dev/pci/if_vr.c hashes[0] |= (1 << h);
h 528 dev/pci/if_vr.c hashes[1] |= (1 << (h - 32));
h 532 dev/pci/if_wb.c int h = 0;
h 564 dev/pci/if_wb.c h = ~(ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26);
h 565 dev/pci/if_wb.c if (h < 32)
h 566 dev/pci/if_wb.c hashes[0] |= (1 << h);
h 568 dev/pci/if_wb.c hashes[1] |= (1 << (h - 32));
h 340 dev/pci/if_xgereg.h #define RXD_MKCTL3(h,bs3,bs4) \
h 341 dev/pci/if_xgereg.h (((uint64_t)(h) << 32) | ((uint64_t)(bs3) << 16) | (uint64_t)(bs4))
h 193 dev/pci/puc.c 0, &sc->sc_bar_mappings[i].t, &sc->sc_bar_mappings[i].h,
h 272 dev/pci/puc.c sc->sc_bar_mappings[bar].h, sc->sc_desc->ports[i].offset,
h 274 dev/pci/puc.c &paa->h)) {
h 285 dev/pci/puc.c (long)paa->t, (long)paa->h);
h 79 dev/pci/pucvar.h bus_space_handle_t h;
h 103 dev/pci/pucvar.h bus_space_handle_t h;
h 1030 dev/pci/tga.c tga_rop(dst, dx, dy, w, h, src, sx, sy)
h 1032 dev/pci/tga.c int dx, dy, w, h;
h 1045 dev/pci/tga.c h += sy;
h 1050 dev/pci/tga.c if (sy + h > src->ri_emuheight)
h 1051 dev/pci/tga.c h = src->ri_emuheight - sy;
h 1062 dev/pci/tga.c h += dy;
h 1068 dev/pci/tga.c if (dy + h > dst->ri_emuheight)
h 1069 dev/pci/tga.c h = dst->ri_emuheight - dy;
h 1070 dev/pci/tga.c if (w <= 0 || h <= 0)
h 1073 dev/pci/tga.c return tga_rop_vtov(dst, dx, dy, w, h, src, sx, sy);
h 1084 dev/pci/tga.c tga_rop_vtov(dst, dx, dy, w, h, src, sx, sy)
h 1086 dev/pci/tga.c int dx, dy, w, h;
h 1113 dev/pci/tga.c yend = h;
h 1116 dev/pci/tga.c ystart = h;
h 268 dev/pcmcia/cfxga.c struct pcmcia_mem_handle h;
h 290 dev/pcmcia/cfxga.c rc = pcmcia_mem_alloc(pf, CFXGA_MEM_RANGE, &h);
h 295 dev/pcmcia/cfxga.c &h, &ptr, &win);
h 299 dev/pcmcia/cfxga.c id = (bus_space_read_1(h.memt, h.memh, ptr + CFREG_REV) &
h 304 dev/pcmcia/cfxga.c pcmcia_mem_free(pa->pf, &h);
h 118 dev/puc/com_puc.c sc->sc_ioh = pa->h;
h 86 dev/puc/lpt_puc.c sc->sc_ioh = aa->h;
h 113 dev/raidframe/rf_layout.c #define RF_NU(a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p)
h 115 dev/raidframe/rf_layout.c #define RF_NU(a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p) a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p
h 350 dev/raidframe/rf_nwayxor.c unsigned long *h = (unsigned long *) src_rbs[6]->buffer;
h 356 dev/raidframe/rf_nwayxor.c *dst++ ^= *b++ ^ *c++ ^ *d++ ^ *e++ ^ *f++ ^ *g++ ^ *h++;
h 366 dev/raidframe/rf_nwayxor.c XOR_AND_LOAD_NEXT(h);
h 370 dev/raidframe/rf_nwayxor.c *dst++ ^= *b++ ^ *c++ ^ *d++ ^ *e++ ^ *f++ ^ *g++ ^ *h++;
h 389 dev/raidframe/rf_nwayxor.c unsigned long *h = (unsigned long *) src_rbs[6]->buffer;
h 396 dev/raidframe/rf_nwayxor.c *dst++ ^= *b++ ^ *c++ ^ *d++ ^ *e++ ^ *f++ ^ *g++ ^ *h++ ^ *i++;
h 406 dev/raidframe/rf_nwayxor.c XOR_AND_LOAD_NEXT(h);
h 411 dev/raidframe/rf_nwayxor.c *dst++ ^= *b++ ^ *c++ ^ *d++ ^ *e++ ^ *f++ ^ *g++ ^ *h++ ^ *i++;
h 431 dev/raidframe/rf_nwayxor.c unsigned long *h = (unsigned long *) src_rbs[6]->buffer;
h 440 dev/raidframe/rf_nwayxor.c *f++ ^ *g++ ^ *h++ ^ *i++ ^ *j++;
h 450 dev/raidframe/rf_nwayxor.c XOR_AND_LOAD_NEXT(h);
h 457 dev/raidframe/rf_nwayxor.c *f++ ^ *g++ ^ *h++ ^ *i++ ^ *j++;
h 100 dev/raidframe/rf_stripelocks.c #define Dprintf8(s,a,b,c,d,e,f,g,h) \
h 105 dev/raidframe/rf_stripelocks.c (void *)((unsigned long)h))
h 196 dev/sbus/bpp.c bus_space_handle_t h = sc->sc_regs;
h 200 dev/sbus/bpp.c hw->hw_hcr = bus_space_read_2(sc->sc_bustag, h, L64854_REG_HCR);
h 201 dev/sbus/bpp.c hw->hw_ocr = bus_space_read_2(sc->sc_bustag, h, L64854_REG_OCR);
h 202 dev/sbus/bpp.c hw->hw_tcr = bus_space_read_1(sc->sc_bustag, h, L64854_REG_TCR);
h 203 dev/sbus/bpp.c hw->hw_or = bus_space_read_1(sc->sc_bustag, h, L64854_REG_OR);
h 219 dev/sbus/bpp.c bus_space_handle_t h = sc->sc_lsi64854.sc_regs;
h 221 dev/sbus/bpp.c bus_space_write_2(t, h, L64854_REG_HCR, hw->hw_hcr);
h 222 dev/sbus/bpp.c bus_space_write_2(t, h, L64854_REG_OCR, hw->hw_ocr);
h 223 dev/sbus/bpp.c bus_space_write_1(t, h, L64854_REG_TCR, hw->hw_tcr);
h 224 dev/sbus/bpp.c bus_space_write_1(t, h, L64854_REG_OR, hw->hw_or);
h 227 dev/sbus/bpp.c irq = bus_space_read_2(t, h, L64854_REG_ICR);
h 230 dev/sbus/bpp.c bus_space_write_2(t, h, L64854_REG_ICR, irq);
h 1757 dev/sbus/magma.c mbpp_hztoms(int h)
h 1759 dev/sbus/magma.c int m = h;
h 1769 dev/sbus/magma.c int h = m;
h 1771 dev/sbus/magma.c if (h > 0) {
h 1772 dev/sbus/magma.c h = h * hz / 1000;
h 1773 dev/sbus/magma.c if (h == 0)
h 1774 dev/sbus/magma.c h = 1000 / hz;
h 1776 dev/sbus/magma.c return (h);
h 147 dev/sbus/stp4020.c stp4020_rd_sockctl(h, idx)
h 148 dev/sbus/stp4020.c struct stp4020_socket *h;
h 151 dev/sbus/stp4020.c int o = ((STP4020_SOCKREGS_SIZE * (h->sock)) + idx);
h 152 dev/sbus/stp4020.c return (bus_space_read_2(h->tag, h->regs, o));
h 156 dev/sbus/stp4020.c stp4020_wr_sockctl(h, idx, v)
h 157 dev/sbus/stp4020.c struct stp4020_socket *h;
h 161 dev/sbus/stp4020.c int o = (STP4020_SOCKREGS_SIZE * (h->sock)) + idx;
h 162 dev/sbus/stp4020.c bus_space_write_2(h->tag, h->regs, o, v);
h 166 dev/sbus/stp4020.c stp4020_rd_winctl(h, win, idx)
h 167 dev/sbus/stp4020.c struct stp4020_socket *h;
h 171 dev/sbus/stp4020.c int o = (STP4020_SOCKREGS_SIZE * (h->sock)) +
h 173 dev/sbus/stp4020.c return (bus_space_read_2(h->tag, h->regs, o));
h 177 dev/sbus/stp4020.c stp4020_wr_winctl(h, win, idx, v)
h 178 dev/sbus/stp4020.c struct stp4020_socket *h;
h 183 dev/sbus/stp4020.c int o = (STP4020_SOCKREGS_SIZE * (h->sock)) +
h 185 dev/sbus/stp4020.c bus_space_write_2(h->tag, h->regs, o, v);
h 195 dev/sbus/stp4020.c struct stp4020_socket *h = paa->pch;
h 197 dev/sbus/stp4020.c printf(" socket %d", h->sock);
h 223 dev/sbus/stp4020.c struct stp4020_socket *h = &sc->sc_socks[i];
h 224 dev/sbus/stp4020.c h->sock = i;
h 225 dev/sbus/stp4020.c h->sc = sc;
h 228 dev/sbus/stp4020.c stp4020_dump_regs(h);
h 230 dev/sbus/stp4020.c stp4020_attach_socket(h, clockfreq);
h 235 dev/sbus/stp4020.c stp4020_attach_socket(h, speed)
h 236 dev/sbus/stp4020.c struct stp4020_socket *h;
h 243 dev/sbus/stp4020.c stp4020_map_window(h, STP_WIN_ATTR, speed);
h 244 dev/sbus/stp4020.c stp4020_map_window(h, STP_WIN_MEM, speed);
h 245 dev/sbus/stp4020.c stp4020_map_window(h, STP_WIN_IO, speed);
h 249 dev/sbus/stp4020.c paa.pct = (pcmcia_chipset_tag_t)h->sc->sc_pct;
h 250 dev/sbus/stp4020.c paa.pch = (pcmcia_chipset_handle_t)h;
h 254 dev/sbus/stp4020.c h->pcmcia = config_found(&h->sc->sc_dev, &paa, stp4020print);
h 256 dev/sbus/stp4020.c if (h->pcmcia == NULL)
h 267 dev/sbus/stp4020.c stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0);
h 268 dev/sbus/stp4020.c stp4020_wr_sockctl(h, STP4020_ICR0_IDX, 0);
h 269 dev/sbus/stp4020.c stp4020_wr_sockctl(h, STP4020_ISR1_IDX, 0x3fff);
h 270 dev/sbus/stp4020.c stp4020_wr_sockctl(h, STP4020_ISR0_IDX, 0x3fff);
h 277 dev/sbus/stp4020.c stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v);
h 280 dev/sbus/stp4020.c v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX);
h 281 dev/sbus/stp4020.c h->sense = v & (STP4020_ISR0_CD1ST | STP4020_ISR0_CD2ST);
h 282 dev/sbus/stp4020.c if (h->sense != 0) {
h 283 dev/sbus/stp4020.c h->flags |= STP4020_SOCKET_BUSY;
h 284 dev/sbus/stp4020.c pcmcia_card_attach(h->pcmcia);
h 317 dev/sbus/stp4020.c struct stp4020_socket *h;
h 337 dev/sbus/stp4020.c h = &sc->sc_socks[socket];
h 340 dev/sbus/stp4020.c sense = stp4020_rd_sockctl(h, STP4020_ISR0_IDX) &
h 343 dev/sbus/stp4020.c if (sense > h->sense) {
h 348 dev/sbus/stp4020.c h->sense = sense;
h 349 dev/sbus/stp4020.c if ((h->flags & STP4020_SOCKET_BUSY) == 0) {
h 350 dev/sbus/stp4020.c h->flags |= STP4020_SOCKET_BUSY;
h 351 dev/sbus/stp4020.c pcmcia_card_attach(h->pcmcia);
h 353 dev/sbus/stp4020.c } else if (sense < h->sense) {
h 358 dev/sbus/stp4020.c h->sense = sense;
h 359 dev/sbus/stp4020.c if (h->flags & STP4020_SOCKET_BUSY) {
h 360 dev/sbus/stp4020.c h->flags &= ~STP4020_SOCKET_BUSY;
h 361 dev/sbus/stp4020.c pcmcia_card_detach(h->pcmcia, DETACH_FORCE);
h 391 dev/sbus/stp4020.c struct stp4020_socket *h;
h 394 dev/sbus/stp4020.c h = &sc->sc_socks[i];
h 397 dev/sbus/stp4020.c v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX);
h 407 dev/sbus/stp4020.c stp4020_wr_sockctl(h, STP4020_ISR0_IDX,
h 426 dev/sbus/stp4020.c if (sense != h->sense)
h 434 dev/sbus/stp4020.c h->sock));
h 440 dev/sbus/stp4020.c h->sock));
h 446 dev/sbus/stp4020.c h->sock));
h 452 dev/sbus/stp4020.c h->sock));
h 458 dev/sbus/stp4020.c h->sock));
h 464 dev/sbus/stp4020.c h->sock));
h 472 dev/sbus/stp4020.c if ((h->flags & STP4020_SOCKET_ENABLING) &&
h 491 dev/sbus/stp4020.c struct stp4020_socket *h;
h 494 dev/sbus/stp4020.c h = &sc->sc_socks[i];
h 495 dev/sbus/stp4020.c v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX);
h 503 dev/sbus/stp4020.c stp4020_wr_sockctl(h, STP4020_ISR0_IDX, v);
h 506 dev/sbus/stp4020.c if ((h->flags & STP4020_SOCKET_BUSY) == 0) {
h 508 dev/sbus/stp4020.c h->sock);
h 512 dev/sbus/stp4020.c if (h->intrhandler != NULL) {
h 519 dev/sbus/stp4020.c splassert(h->ipl);
h 520 dev/sbus/stp4020.c (*h->intrhandler)(h->intrarg);
h 554 dev/sbus/stp4020.c stp4020_map_window(struct stp4020_socket *h, int win, int speed)
h 584 dev/sbus/stp4020.c stp4020_wr_winctl(h, win, STP4020_WCR0_IDX, v);
h 585 dev/sbus/stp4020.c stp4020_wr_winctl(h, win, STP4020_WCR1_IDX,
h 595 dev/sbus/stp4020.c struct stp4020_socket *h = (struct stp4020_socket *)pch;
h 598 dev/sbus/stp4020.c pcmhp->memt = h->wintag;
h 624 dev/sbus/stp4020.c struct stp4020_socket *h = (struct stp4020_socket *)pch;
h 627 dev/sbus/stp4020.c pcmhp->memt = h->wintag;
h 628 dev/sbus/stp4020.c bus_space_subregion(h->wintag, h->windows[win].winaddr,
h 653 dev/sbus/stp4020.c struct stp4020_socket *h = (struct stp4020_socket *)pch;
h 655 dev/sbus/stp4020.c pcihp->iot = h->wintag;
h 656 dev/sbus/stp4020.c pcihp->ioh = h->windows[STP_WIN_IO].winaddr;
h 677 dev/sbus/stp4020.c struct stp4020_socket *h = (struct stp4020_socket *)pch;
h 679 dev/sbus/stp4020.c pcihp->iot = h->wintag;
h 680 dev/sbus/stp4020.c bus_space_subregion(h->wintag, h->windows[STP_WIN_IO].winaddr,
h 697 dev/sbus/stp4020.c struct stp4020_socket *h = (struct stp4020_socket *)pch;
h 700 dev/sbus/stp4020.c h->flags |= STP4020_SOCKET_ENABLING;
h 705 dev/sbus/stp4020.c stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0);
h 715 dev/sbus/stp4020.c stp4020_wr_sockctl(h, STP4020_ICR1_IDX, v);
h 727 dev/sbus/stp4020.c stp4020_wr_sockctl(h, STP4020_ICR1_IDX, v);
h 732 dev/sbus/stp4020.c stp4020_wr_sockctl(h, STP4020_ICR0_IDX,
h 733 dev/sbus/stp4020.c stp4020_rd_sockctl(h, STP4020_ICR0_IDX) | STP4020_ICR0_RESET);
h 735 dev/sbus/stp4020.c stp4020_wr_sockctl(h, STP4020_ICR0_IDX,
h 736 dev/sbus/stp4020.c stp4020_rd_sockctl(h, STP4020_ICR0_IDX) & ~STP4020_ICR0_RESET);
h 743 dev/sbus/stp4020.c v = stp4020_rd_sockctl(h, STP4020_ISR0_IDX);
h 746 dev/sbus/stp4020.c h->flags &= ~STP4020_SOCKET_ENABLING;
h 758 dev/sbus/stp4020.c h->flags &= ~STP4020_SOCKET_ENABLING;
h 762 dev/sbus/stp4020.c v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX);
h 769 dev/sbus/stp4020.c if (pcmcia_card_gettype(h->pcmcia) == PCMCIA_IFTYPE_IO) {
h 774 dev/sbus/stp4020.c h->sc->sc_dev.dv_xname));
h 780 dev/sbus/stp4020.c h->sc->sc_dev.dv_xname));
h 782 dev/sbus/stp4020.c stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v);
h 784 dev/sbus/stp4020.c h->flags &= ~STP4020_SOCKET_ENABLING;
h 791 dev/sbus/stp4020.c struct stp4020_socket *h = (struct stp4020_socket *)pch;
h 797 dev/sbus/stp4020.c v = stp4020_rd_sockctl(h, STP4020_ICR0_IDX);
h 800 dev/sbus/stp4020.c stp4020_wr_sockctl(h, STP4020_ICR0_IDX, v);
h 803 dev/sbus/stp4020.c stp4020_wr_sockctl(h, STP4020_ICR1_IDX, 0);
h 820 dev/sbus/stp4020.c struct stp4020_socket *h = (struct stp4020_socket *)pch;
h 822 dev/sbus/stp4020.c h->intrhandler = handler;
h 823 dev/sbus/stp4020.c h->intrarg = arg;
h 824 dev/sbus/stp4020.c h->ipl = ipl;
h 825 dev/sbus/stp4020.c return (h);
h 833 dev/sbus/stp4020.c struct stp4020_socket *h = (struct stp4020_socket *)pch;
h 835 dev/sbus/stp4020.c h->intrhandler = NULL;
h 836 dev/sbus/stp4020.c h->intrarg = NULL;
h 877 dev/sbus/stp4020.c stp4020_dump_regs(h)
h 878 dev/sbus/stp4020.c struct stp4020_socket *h;
h 884 dev/sbus/stp4020.c "\tICR0=%b\n\tICR1=%b\n\tISR0=%b\n\tISR1=%x\n", h->sock,
h 885 dev/sbus/stp4020.c stp4020_rd_sockctl(h, STP4020_ICR0_IDX), STP4020_ICR0_BITS,
h 886 dev/sbus/stp4020.c stp4020_rd_sockctl(h, STP4020_ICR1_IDX), STP4020_ICR1_BITS,
h 887 dev/sbus/stp4020.c stp4020_rd_sockctl(h, STP4020_ISR0_IDX), STP4020_ISR0_IOBITS,
h 888 dev/sbus/stp4020.c stp4020_rd_sockctl(h, STP4020_ISR1_IDX));
h 617 dev/sbus/zx.c zx_fillrect(struct rasops_info *ri, int x, int y, int w, int h, long attr,
h 633 dev/sbus/zx.c h = ri->ri_font->fontheight * h - 1;
h 640 dev/sbus/zx.c SETREG(zc->zc_extent, ZX_COORDS(w, h));
h 646 dev/sbus/zx.c int h)
h 662 dev/sbus/zx.c h = h * ri->ri_font->fontheight - 1;
h 667 dev/sbus/zx.c sy += h;
h 669 dev/sbus/zx.c dy += h;
h 677 dev/sbus/zx.c SETREG(zc->zc_extent, ZX_COORDS(w, h) | dir);
h 122 dev/usb/hid.c hid_get_item(struct hid_data *s, struct hid_item *h)
h 141 dev/usb/hid.c *h = *c;
h 143 dev/usb/hid.c h->next = NULL;
h 233 dev/usb/hid.c *h = *c;
h 234 dev/usb/hid.c h->next = NULL;
h 249 dev/usb/hid.c *h = *c;
h 259 dev/usb/hid.c *h = *c;
h 381 dev/usb/hid.c struct hid_item h;
h 384 dev/usb/hid.c h.report_ID = 0;
h 387 dev/usb/hid.c for (d = hid_start_parse(buf, len, k); hid_get_item(d, &h); ) {
h 390 dev/usb/hid.c h.kind, h.report_ID, h.loc.pos, h.loc.size,
h 391 dev/usb/hid.c h.loc.count));
h 392 dev/usb/hid.c if (h.report_ID == id && h.kind == k) {
h 394 dev/usb/hid.c lo = h.loc.pos;
h 401 dev/usb/hid.c hi = h.loc.pos + h.loc.size * h.loc.count;
h 414 dev/usb/hid.c struct hid_item h;
h 416 dev/usb/hid.c h.report_ID = 0;
h 418 dev/usb/hid.c for (d = hid_start_parse(desc, size, k); hid_get_item(d, &h); ) {
h 420 dev/usb/hid.c h.usage, h.kind, h.report_ID, h.flags));
h 421 dev/usb/hid.c if (h.kind == k && !(h.flags & HIO_CONST) &&
h 422 dev/usb/hid.c h.usage == u && h.report_ID == id) {
h 424 dev/usb/hid.c *loc = h.loc;
h 426 dev/usb/hid.c *flags = h.flags;
h 91 dev/usb/hid.h int hid_get_item(struct hid_data *s, struct hid_item *h);
h 1662 dev/usb/if_atu.c struct atu_rx_hdr *h;
h 1720 dev/usb/if_atu.c h = (struct atu_rx_hdr *)c->atu_buf;
h 1721 dev/usb/if_atu.c len = UGETW(h->length) - 4; /* XXX magic number */
h 1750 dev/usb/if_atu.c rr->rr_rssi = h->rssi;
h 1771 dev/usb/if_atu.c ieee80211_input(ifp, m, ni, h->rssi, UGETDW(h->rx_time));
h 1851 dev/usb/if_atu.c struct atu_tx_hdr *h;
h 1895 dev/usb/if_atu.c h = (struct atu_tx_hdr *)c->atu_buf;
h 1896 dev/usb/if_atu.c memset(h, 0, ATU_TX_HDRLEN);
h 1897 dev/usb/if_atu.c USETW(h->length, len);
h 1898 dev/usb/if_atu.c h->tx_rate = 4; /* XXX rate = auto */
h 1903 dev/usb/if_atu.c h->padding = pad;
h 594 dev/usb/if_aue.c u_int32_t h = 0, i;
h 620 dev/usb/if_aue.c h = aue_crc(enm->enm_addrlo);
h 621 dev/usb/if_aue.c AUE_SETBIT(sc, AUE_MAR + (h >> 3), 1 << (h & 0x7));
h 411 dev/usb/if_axe.c u_int32_t h = 0;
h 439 dev/usb/if_axe.c h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26;
h 440 dev/usb/if_axe.c hashtbl[h / 8] |= 1 << (h % 8);
h 351 dev/usb/if_cue.c u_int32_t h, i;
h 379 dev/usb/if_cue.c h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) &
h 381 dev/usb/if_cue.c sc->cue_mctab[h >> 3] |= 1 << (h & 0x7);
h 392 dev/usb/if_cue.c h = ether_crc32_le(etherbroadcastaddr, ETHER_ADDR_LEN) &
h 394 dev/usb/if_cue.c sc->cue_mctab[h >> 3] |= 1 << (h & 0x7);
h 759 dev/usb/if_udav.c int h = 0;
h 791 dev/usb/if_udav.c h = UDAV_CALCHASH(enm->enm_addrlo);
h 792 dev/usb/if_udav.c hashes[h>>3] |= 1 << (h & 0x7);
h 1113 dev/usb/if_udav.c struct udav_rx_hdr *h;
h 1144 dev/usb/if_udav.c h = (struct udav_rx_hdr *)c->udav_buf;
h 1145 dev/usb/if_udav.c total_len = UGETW(h->length) - ETHER_CRC_LEN;
h 1147 dev/usb/if_udav.c DPRINTF(("%s: RX Status: 0x%02x\n", h->pktstat));
h 1149 dev/usb/if_udav.c if (h->pktstat & UDAV_RSR_LCS) {
h 1155 dev/usb/if_udav.c h->pktstat & UDAV_RSR_ERR) {
h 640 dev/usb/if_url.c int h = 0;
h 672 dev/usb/if_url.c h = url_calchash(enm->enm_addrlo);
h 673 dev/usb/if_url.c if (h < 32)
h 674 dev/usb/if_url.c hashes[0] |= (1 << h);
h 676 dev/usb/if_url.c hashes[1] |= (1 << (h -32));
h 1829 dev/usb/ohci.c int h = HASH(std->physaddr);
h 1833 dev/usb/ohci.c LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext);
h 1848 dev/usb/ohci.c int h = HASH(a);
h 1851 dev/usb/ohci.c for (std = LIST_FIRST(&sc->sc_hash_tds[h]);
h 1863 dev/usb/ohci.c int h = HASH(sitd->physaddr);
h 1870 dev/usb/ohci.c LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext);
h 1888 dev/usb/ohci.c int h = HASH(a);
h 1891 dev/usb/ohci.c for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]);
h 109 dev/usb/uaudio.c #define MAKE(h,l) (((h) << 8) | (l))
h 922 dev/usb/ubt.c usbd_private_handle h, usbd_status status)
h 924 dev/usb/ubt.c struct hci_unit *unit = h;
h 1019 dev/usb/ubt.c usbd_private_handle h, usbd_status status)
h 1021 dev/usb/ubt.c struct hci_unit *unit = h;
h 1152 dev/usb/ubt.c usbd_private_handle h, usbd_status status)
h 1154 dev/usb/ubt.c struct ubt_isoc_xfer *isoc = h;
h 1227 dev/usb/ubt.c ubt_recv_event(usbd_xfer_handle xfer, usbd_private_handle h, usbd_status status)
h 1229 dev/usb/ubt.c struct ubt_softc *sc = h;
h 1300 dev/usb/ubt.c usbd_private_handle h, usbd_status status)
h 1302 dev/usb/ubt.c struct ubt_softc *sc = h;
h 1390 dev/usb/ubt.c usbd_private_handle h, usbd_status status)
h 1392 dev/usb/ubt.c struct ubt_isoc_xfer *isoc = h;
h 318 dev/usb/uhidev.c struct hid_item h;
h 322 dev/usb/uhidev.c h.report_ID = 0;
h 323 dev/usb/uhidev.c for (d = hid_start_parse(buf, len, hid_none); hid_get_item(d, &h); )
h 324 dev/usb/uhidev.c if (h.report_ID > maxid)
h 325 dev/usb/uhidev.c maxid = h.report_ID;
h 901 dev/usb/ukbd.c struct hid_item h;
h 910 dev/usb/ukbd.c while (hid_get_item(d, &h)) {
h 913 dev/usb/ukbd.c if (h.kind != hid_input || (h.flags & HIO_CONST) ||
h 914 dev/usb/ukbd.c HID_GET_USAGE_PAGE(h.usage) != HUP_KEYBOARD ||
h 915 dev/usb/ukbd.c h.report_ID != sc->sc_hdev.sc_report_id)
h 919 dev/usb/ukbd.c h.usage, h.flags, h.loc.pos, h.loc.size, h.loc.count));
h 920 dev/usb/ukbd.c if (h.flags & HIO_VARIABLE) {
h 921 dev/usb/ukbd.c if (h.loc.size != 1)
h 925 dev/usb/ukbd.c sc->sc_modloc[imod] = h.loc;
h 927 dev/usb/ukbd.c sc->sc_mods[imod].key = HID_GET_USAGE(h.usage);
h 933 dev/usb/ukbd.c if (h.loc.size != 8)
h 935 dev/usb/ukbd.c if (h.loc.count > MAXKEYCODE)
h 937 dev/usb/ukbd.c if (h.loc.pos % 8 != 0)
h 941 dev/usb/ukbd.c sc->sc_keycodeloc = h.loc;
h 942 dev/usb/ukbd.c sc->sc_nkeycode = h.loc.count;
h 71 dev/usb/usb.h #define USETW2(w,h,l) ((w)[0] = (u_int8_t)(l), (w)[1] = (u_int8_t)(h))
h 107 dev/usb/usb_port.h #define usb_callout_init(h) timeout_set(&(h), NULL, NULL)
h 108 dev/usb/usb_port.h #define usb_callout(h, t, f, d) \
h 110 dev/usb/usb_port.h timeout_del(&(h)); \
h 111 dev/usb/usb_port.h timeout_set(&(h), (f), (d)); \
h 112 dev/usb/usb_port.h timeout_add(&(h), (t)); \
h 114 dev/usb/usb_port.h #define usb_callout_pending(h) timeout_pending(&(h))
h 115 dev/usb/usb_port.h #define usb_uncallout(h, f, d) timeout_del(&(h))
h 128 isofs/cd9660/cd9660_rrip.c (ISO_RRIP_SLINK_COMPONENT *)((char *)p + isonum_711(p->h.length));
h 262 isofs/cd9660/cd9660_rrip.c wlen = isonum_711(p->h.length) - 5;
h 325 isofs/cd9660/cd9660_rrip.c return (*p->h.type == 'C' ? ISO_SUSP_CLINK : ISO_SUSP_PLINK);
h 47 isofs/cd9660/cd9660_rrip.h ISO_SUSP_HEADER h;
h 55 isofs/cd9660/cd9660_rrip.h ISO_SUSP_HEADER h;
h 75 isofs/cd9660/cd9660_rrip.h ISO_SUSP_HEADER h;
h 81 isofs/cd9660/cd9660_rrip.h ISO_SUSP_HEADER h;
h 86 isofs/cd9660/cd9660_rrip.h ISO_SUSP_HEADER h;
h 91 isofs/cd9660/cd9660_rrip.h ISO_SUSP_HEADER h;
h 96 isofs/cd9660/cd9660_rrip.h ISO_SUSP_HEADER h;
h 110 isofs/cd9660/cd9660_rrip.h ISO_SUSP_HEADER h;
h 116 isofs/cd9660/cd9660_rrip.h ISO_SUSP_HEADER h;
h 121 isofs/cd9660/cd9660_rrip.h ISO_SUSP_HEADER h;
h 129 isofs/cd9660/cd9660_rrip.h ISO_SUSP_HEADER h;
h 135 isofs/cd9660/cd9660_rrip.h ISO_SUSP_HEADER h;
h 1000 kern/subr_pool.c #define pool_put(h, v) _pool_put((h), (v), __FILE__, __LINE__)
h 2031 kern/tty.c #define CLAMP(x, h, l) ((x) > h ? h : ((x) < l) ? l : (x))
h 121 lib/libsa/bootparam.c n_long h[RPC_HEADER_WORDS];
h 125 lib/libsa/bootparam.c n_long h[RPC_HEADER_WORDS];
h 232 lib/libsa/bootparam.c n_long h[RPC_HEADER_WORDS];
h 236 lib/libsa/bootparam.c n_long h[RPC_HEADER_WORDS];
h 118 lib/libsa/nfs.c n_long h[RPC_HEADER_WORDS];
h 122 lib/libsa/nfs.c n_long h[RPC_HEADER_WORDS];
h 180 lib/libsa/nfs.c n_long h[RPC_HEADER_WORDS];
h 184 lib/libsa/nfs.c n_long h[RPC_HEADER_WORDS];
h 231 lib/libsa/nfs.c n_long h[RPC_HEADER_WORDS];
h 235 lib/libsa/nfs.c n_long h[RPC_HEADER_WORDS];
h 277 lib/libsa/nfs.c n_long h[RPC_HEADER_WORDS];
h 281 lib/libsa/nfs.c n_long h[RPC_HEADER_WORDS];
h 371 lib/libsa/rpc.c n_long h[RPC_HEADER_WORDS];
h 375 lib/libsa/rpc.c n_long h[RPC_HEADER_WORDS];
h 125 lib/libsa/stand.h #define btochs(b,c,h,s,nh,ns) \
h 127 lib/libsa/stand.h h = ((b) % ((nh) * (ns))) / (ns); \
h 153 lib/libsa/tftp.c tftp_makereq(struct tftp_handle *h)
h 169 lib/libsa/tftp.c l = strlen(h->path);
h 170 lib/libsa/tftp.c bcopy(h->path, wtail, l + 1);
h 175 lib/libsa/tftp.c t = &h->lastdata.t;
h 178 lib/libsa/tftp.c h->iodesc->myport = htons(tftpport + (getsecs() & 0x3ff));
h 179 lib/libsa/tftp.c h->iodesc->destport = htons(IPPORT_TFTP);
h 180 lib/libsa/tftp.c h->iodesc->xid = 1; /* expected block */
h 182 lib/libsa/tftp.c res = sendrecv(h->iodesc, sendudp, &wbuf.t, wtail - (char *) &wbuf.t,
h 188 lib/libsa/tftp.c h->currblock = 1;
h 189 lib/libsa/tftp.c h->validsize = res;
h 190 lib/libsa/tftp.c h->islastblock = 0;
h 192 lib/libsa/tftp.c h->islastblock = 1; /* very short file */
h 198 lib/libsa/tftp.c tftp_getnextblock(struct tftp_handle *h)
h 211 lib/libsa/tftp.c wbuf.t.th_block = htons((u_short) h->currblock);
h 214 lib/libsa/tftp.c t = &h->lastdata.t;
h 216 lib/libsa/tftp.c h->iodesc->xid = h->currblock + 1; /* expected block */
h 218 lib/libsa/tftp.c res = sendrecv(h->iodesc, sendudp, &wbuf.t, wtail - (char *) &wbuf.t,
h 224 lib/libsa/tftp.c h->currblock++;
h 225 lib/libsa/tftp.c h->validsize = res;
h 227 lib/libsa/tftp.c h->islastblock = 1; /* EOF */
h 233 lib/libsa/tftp.c tftp_terminate(struct tftp_handle *h)
h 243 lib/libsa/tftp.c if (h->islastblock) {
h 245 lib/libsa/tftp.c wbuf.t.th_block = htons((u_short) h->currblock);
h 252 lib/libsa/tftp.c (void) sendudp(h->iodesc, &wbuf.t, wtail - (char *) &wbuf.t);
h 1683 net/if_bridge.c u_int32_t h;
h 1686 net/if_bridge.c h = bridge_hash(sc, ea);
h 1687 net/if_bridge.c p = LIST_FIRST(&sc->sc_rts[h]);
h 1688 net/if_bridge.c if (p == LIST_END(&sc->sc_rts[h])) {
h 1705 net/if_bridge.c LIST_INSERT_HEAD(&sc->sc_rts[h], p, brt_next);
h 1750 net/if_bridge.c if (p == LIST_END(&sc->sc_rts[h])) {
h 1770 net/if_bridge.c } while (p != LIST_END(&sc->sc_rts[h]));
h 1782 net/if_bridge.c u_int32_t h;
h 1785 net/if_bridge.c h = bridge_hash(sc, ea);
h 1786 net/if_bridge.c LIST_FOREACH(p, &sc->sc_rts[h], brt_next) {
h 1982 net/if_bridge.c int h;
h 1985 net/if_bridge.c h = bridge_hash(sc, ea);
h 1986 net/if_bridge.c LIST_FOREACH(p, &sc->sc_rts[h], brt_next) {
h 2122 net/if_bridge.c bridge_filterrule(struct brl_head *h, struct ether_header *eh, struct mbuf *m)
h 2127 net/if_bridge.c SIMPLEQ_FOREACH(n, h, brl_next) {
h 75 net/if_pflog.h #define PFLOG_PACKET(i,x,a,b,c,d,e,f,g,h) pflog_packet(i,a,b,c,d,e,f,g,h)
h 77 net/if_pflog.h #define PFLOG_PACKET(i,x,a,b,c,d,e,f,g,h) ((void)0)
h 1023 net/if_pfsync.c struct pfsync_header *h;
h 1077 net/if_pfsync.c h = mtod(m, struct pfsync_header *);
h 1078 net/if_pfsync.c h->version = PFSYNC_VERSION;
h 1079 net/if_pfsync.c h->af = 0;
h 1080 net/if_pfsync.c h->count = 0;
h 1081 net/if_pfsync.c h->action = action;
h 1083 net/if_pfsync.c bcopy(&pf_status.pf_chksum, &h->pf_chksum,
h 1086 net/if_pfsync.c *sp = (void *)((char *)h + PFSYNC_HDRLEN);
h 1099 net/if_pfsync.c struct pfsync_header *h, *h_net;
h 1138 net/if_pfsync.c h = mtod(sc->sc_mbuf, struct pfsync_header *);
h 1140 net/if_pfsync.c h = mtod(sc->sc_mbuf, struct pfsync_header *);
h 1141 net/if_pfsync.c if (h->action != action) {
h 1148 net/if_pfsync.c h = mtod(sc->sc_mbuf, struct pfsync_header *);
h 1156 net/if_pfsync.c (void *)((char *)h + PFSYNC_HDRLEN);
h 1158 net/if_pfsync.c for (i = 0; i < h->count; i++) {
h 1182 net/if_pfsync.c h->count++;
h 1286 net/if_pfsync.c if (h->count == sc->sc_maxcount ||
h 1299 net/if_pfsync.c struct pfsync_header *h;
h 1312 net/if_pfsync.c h = mtod(sc->sc_mbuf, struct pfsync_header *);
h 1314 net/if_pfsync.c h = mtod(sc->sc_mbuf, struct pfsync_header *);
h 1315 net/if_pfsync.c if (h->action != PFSYNC_ACT_UREQ) {
h 1320 net/if_pfsync.c h = mtod(sc->sc_mbuf, struct pfsync_header *);
h 1327 net/if_pfsync.c h->count++;
h 1335 net/if_pfsync.c if (h->count == sc->sc_maxcount)
h 1648 net/if_pfsync.c struct pfsync_header *h;
h 1674 net/if_pfsync.c h = mtod(sc->sc_mbuf_tdb, struct pfsync_header *);
h 1676 net/if_pfsync.c h = mtod(sc->sc_mbuf_tdb, struct pfsync_header *);
h 1677 net/if_pfsync.c if (h->action != PFSYNC_ACT_TDB_UPD) {
h 1689 net/if_pfsync.c h = mtod(sc->sc_mbuf_tdb, struct pfsync_header *);
h 1696 net/if_pfsync.c (void *)((char *)h + PFSYNC_HDRLEN);
h 1698 net/if_pfsync.c for (i = 0; !pt && i < h->count; i++) {
h 1716 net/if_pfsync.c h->count++;
h 1745 net/if_pfsync.c if (h->count == sc->sc_maxcount ||
h 237 net/if_spppsubr.c int (*RCR)(struct sppp *sp, struct lcp_header *h, int len);
h 238 net/if_spppsubr.c void (*RCN_rej)(struct sppp *sp, struct lcp_header *h, int len);
h 239 net/if_spppsubr.c void (*RCN_nak)(struct sppp *sp, struct lcp_header *h, int len);
h 317 net/if_spppsubr.c HIDE int sppp_lcp_RCR(struct sppp *sp, struct lcp_header *h, int len);
h 318 net/if_spppsubr.c HIDE void sppp_lcp_RCN_rej(struct sppp *sp, struct lcp_header *h, int len);
h 319 net/if_spppsubr.c HIDE void sppp_lcp_RCN_nak(struct sppp *sp, struct lcp_header *h, int len);
h 334 net/if_spppsubr.c HIDE int sppp_ipcp_RCR(struct sppp *sp, struct lcp_header *h, int len);
h 335 net/if_spppsubr.c HIDE void sppp_ipcp_RCN_rej(struct sppp *sp, struct lcp_header *h, int len);
h 336 net/if_spppsubr.c HIDE void sppp_ipcp_RCN_nak(struct sppp *sp, struct lcp_header *h, int len);
h 443 net/if_spppsubr.c struct ppp_header *h, ht;
h 476 net/if_spppsubr.c h = &ht;
h 479 net/if_spppsubr.c h = mtod (m, struct ppp_header*);
h 496 net/if_spppsubr.c switch (h->address) {
h 498 net/if_spppsubr.c if (h->control != PPP_UI)
h 506 net/if_spppsubr.c h->address, h->control, ntohs(h->protocol));
h 509 net/if_spppsubr.c switch (ntohs (h->protocol)) {
h 513 net/if_spppsubr.c ++sp->pp_seq, 2, &h->protocol);
h 519 net/if_spppsubr.c h->address, h->control, ntohs(h->protocol));
h 561 net/if_spppsubr.c h->address, h->control, ntohs(h->protocol));
h 564 net/if_spppsubr.c switch (ntohs (h->protocol)) {
h 587 net/if_spppsubr.c h->address, h->control, ntohs(h->protocol));
h 619 net/if_spppsubr.c struct ppp_header *h;
h 714 net/if_spppsubr.c h = mtod (m, struct ppp_header*);
h 716 net/if_spppsubr.c h->address = CISCO_UNICAST; /* unicast address */
h 717 net/if_spppsubr.c h->control = 0;
h 719 net/if_spppsubr.c h->address = PPP_ALLSTATIONS; /* broadcast address */
h 720 net/if_spppsubr.c h->control = PPP_UI; /* Unnumbered Info */
h 765 net/if_spppsubr.c h->protocol = protocol;
h 1050 net/if_spppsubr.c struct cisco_packet *h;
h 1060 net/if_spppsubr.c h = mtod (m, struct cisco_packet*);
h 1066 net/if_spppsubr.c ntohl(h->type), h->par1, h->par2, (u_int)h->rel,
h 1067 net/if_spppsubr.c (u_int)h->time0, (u_int)h->time1);
h 1068 net/if_spppsubr.c switch (ntohl (h->type)) {
h 1072 net/if_spppsubr.c SPP_ARGS(ifp), ntohl(h->type));
h 1079 net/if_spppsubr.c sp->pp_rseq = ntohl (h->par1);
h 1125 net/if_spppsubr.c struct ppp_header *h;
h 1138 net/if_spppsubr.c h = mtod (m, struct ppp_header*);
h 1139 net/if_spppsubr.c h->address = CISCO_MULTICAST;
h 1140 net/if_spppsubr.c h->control = 0;
h 1141 net/if_spppsubr.c h->protocol = htons (CISCO_KEEPALIVE);
h 1143 net/if_spppsubr.c ch = (struct cisco_packet*) (h + 1);
h 1183 net/if_spppsubr.c struct ppp_header *h;
h 1202 net/if_spppsubr.c h = mtod (m, struct ppp_header*);
h 1203 net/if_spppsubr.c h->address = PPP_ALLSTATIONS; /* broadcast address */
h 1204 net/if_spppsubr.c h->control = PPP_UI; /* Unnumbered Info */
h 1205 net/if_spppsubr.c h->protocol = htons (proto); /* Link Control Protocol */
h 1206 net/if_spppsubr.c lh = (struct lcp_header*) (h + 1);
h 1245 net/if_spppsubr.c struct lcp_header *h;
h 1258 net/if_spppsubr.c h = mtod (m, struct lcp_header*);
h 1264 net/if_spppsubr.c sppp_cp_type_name (h->type), h->ident, ntohs (h->len));
h 1266 net/if_spppsubr.c sppp_print_bytes ((u_char*) (h+1), len-4);
h 1269 net/if_spppsubr.c if (len > ntohs (h->len))
h 1270 net/if_spppsubr.c len = ntohs (h->len);
h 1271 net/if_spppsubr.c p = (u_char *)(h + 1);
h 1272 net/if_spppsubr.c switch (h->type) {
h 1288 net/if_spppsubr.c sppp_cp_send(sp, cp->proto, TERM_ACK, h->ident,
h 1292 net/if_spppsubr.c rv = (cp->RCR)(sp, h, len);
h 1334 net/if_spppsubr.c if (h->ident != sp->confid[cp->protoidx]) {
h 1338 net/if_spppsubr.c h->ident, sp->confid[cp->protoidx]);
h 1345 net/if_spppsubr.c sppp_cp_send(sp, cp->proto, TERM_ACK, h->ident, 0, 0);
h 1381 net/if_spppsubr.c if (h->ident != sp->confid[cp->protoidx]) {
h 1385 net/if_spppsubr.c h->ident, sp->confid[cp->protoidx]);
h 1389 net/if_spppsubr.c if (h->type == CONF_NAK)
h 1390 net/if_spppsubr.c (cp->RCN_nak)(sp, h, len);
h 1392 net/if_spppsubr.c (cp->RCN_rej)(sp, h, len);
h 1397 net/if_spppsubr.c sppp_cp_send(sp, cp->proto, TERM_ACK, h->ident, 0, 0);
h 1441 net/if_spppsubr.c sppp_cp_send(sp, cp->proto, TERM_ACK, h->ident, 0, 0);
h 1495 net/if_spppsubr.c sppp_cp_type_name(h->type), ntohs(*((u_short *)p)));
h 1558 net/if_spppsubr.c sppp_cp_send (sp, PPP_LCP, ECHO_REPLY, h->ident, len-4, h+1);
h 1563 net/if_spppsubr.c if (h->ident != sp->lcp.echoid) {
h 1589 net/if_spppsubr.c SPP_ARGS(ifp), cp->name, h->type);
h 1591 net/if_spppsubr.c m->m_pkthdr.len, h);
h 2004 net/if_spppsubr.c sppp_lcp_RCR(struct sppp *sp, struct lcp_header *h, int len)
h 2023 net/if_spppsubr.c p = (void*) (h+1);
h 2088 net/if_spppsubr.c sppp_cp_send(sp, PPP_LCP, CONF_REJ, h->ident, rlen, buf);
h 2101 net/if_spppsubr.c p = (void*) (h+1);
h 2186 net/if_spppsubr.c sppp_cp_send(sp, PPP_LCP, CONF_REJ, h->ident, rlen, buf);
h 2190 net/if_spppsubr.c sppp_cp_send(sp, PPP_LCP, CONF_NAK, h->ident, rlen, buf);
h 2199 net/if_spppsubr.c h->ident, origlen, h+1);
h 2212 net/if_spppsubr.c sppp_lcp_RCN_rej(struct sppp *sp, struct lcp_header *h, int len)
h 2223 net/if_spppsubr.c p = (void*) (h+1);
h 2272 net/if_spppsubr.c sppp_lcp_RCN_nak(struct sppp *sp, struct lcp_header *h, int len)
h 2284 net/if_spppsubr.c p = (void*) (h+1);
h 2581 net/if_spppsubr.c sppp_ipcp_RCR(struct sppp *sp, struct lcp_header *h, int len)
h 2602 net/if_spppsubr.c p = (void*) (h+1);
h 2643 net/if_spppsubr.c sppp_cp_send(sp, PPP_IPCP, CONF_REJ, h->ident, rlen, buf);
h 2656 net/if_spppsubr.c p = (void*) (h+1);
h 2740 net/if_spppsubr.c sppp_cp_send (sp, PPP_IPCP, CONF_NAK, h->ident, rlen, buf);
h 2745 net/if_spppsubr.c h->ident, origlen, h+1);
h 2758 net/if_spppsubr.c sppp_ipcp_RCN_rej(struct sppp *sp, struct lcp_header *h, int len)
h 2770 net/if_spppsubr.c p = (void*) (h+1);
h 2800 net/if_spppsubr.c sppp_ipcp_RCN_nak(struct sppp *sp, struct lcp_header *h, int len)
h 2813 net/if_spppsubr.c p = (void*) (h+1);
h 3067 net/if_spppsubr.c struct lcp_header *h;
h 3081 net/if_spppsubr.c h = mtod (m, struct lcp_header*);
h 3082 net/if_spppsubr.c if (len > ntohs (h->len))
h 3083 net/if_spppsubr.c len = ntohs (h->len);
h 3085 net/if_spppsubr.c switch (h->type) {
h 3088 net/if_spppsubr.c value = 1 + (u_char*)(h+1);
h 3098 net/if_spppsubr.c sppp_auth_type_name(PPP_CHAP, h->type),
h 3099 net/if_spppsubr.c h->ident, ntohs(h->len));
h 3101 net/if_spppsubr.c sppp_print_bytes((u_char*) (h+1), len-4);
h 3111 net/if_spppsubr.c sppp_auth_type_name(PPP_CHAP, h->type), h->ident,
h 3112 net/if_spppsubr.c ntohs(h->len));
h 3121 net/if_spppsubr.c MD5Update(&ctx, &h->ident, 1);
h 3128 net/if_spppsubr.c sppp_auth_send(&chap, sp, CHAP_RESPONSE, h->ident,
h 3142 net/if_spppsubr.c sppp_print_string((char*)(h + 1), len - 4);
h 3169 net/if_spppsubr.c sppp_print_string((char*)(h + 1), len - 4);
h 3180 net/if_spppsubr.c value = 1 + (u_char*)(h+1);
h 3190 net/if_spppsubr.c sppp_auth_type_name(PPP_CHAP, h->type),
h 3191 net/if_spppsubr.c h->ident, ntohs(h->len));
h 3193 net/if_spppsubr.c sppp_print_bytes((u_char*)(h+1), len-4);
h 3198 net/if_spppsubr.c if (h->ident != sp->confid[IDX_CHAP]) {
h 3204 net/if_spppsubr.c h->ident, sp->confid[IDX_CHAP]);
h 3222 net/if_spppsubr.c sppp_auth_type_name(PPP_CHAP, h->type),
h 3223 net/if_spppsubr.c h->ident, ntohs (h->len));
h 3240 net/if_spppsubr.c MD5Update(&ctx, &h->ident, 1);
h 3252 net/if_spppsubr.c sppp_auth_send(&chap, sp, CHAP_FAILURE, h->ident,
h 3261 net/if_spppsubr.c sppp_auth_send(&chap, sp, CHAP_SUCCESS, h->ident,
h 3277 net/if_spppsubr.c h->type, h->ident, ntohs(h->len));
h 3279 net/if_spppsubr.c sppp_print_bytes((u_char*)(h+1), len-4);
h 3477 net/if_spppsubr.c struct lcp_header *h;
h 3490 net/if_spppsubr.c h = mtod (m, struct lcp_header*);
h 3491 net/if_spppsubr.c if (len > ntohs (h->len))
h 3492 net/if_spppsubr.c len = ntohs (h->len);
h 3493 net/if_spppsubr.c switch (h->type) {
h 3496 net/if_spppsubr.c name = 1 + (u_char*)(h+1);
h 3505 net/if_spppsubr.c sppp_auth_type_name(PPP_PAP, h->type),
h 3506 net/if_spppsubr.c h->ident, ntohs(h->len));
h 3508 net/if_spppsubr.c sppp_print_bytes((u_char*)(h+1), len-4);
h 3518 net/if_spppsubr.c sppp_auth_type_name(PPP_PAP, h->type),
h 3519 net/if_spppsubr.c h->ident, ntohs(h->len));
h 3531 net/if_spppsubr.c sppp_auth_send(&pap, sp, PAP_NAK, h->ident,
h 3542 net/if_spppsubr.c sppp_auth_send(&pap, sp, PAP_ACK, h->ident,
h 3559 net/if_spppsubr.c name_len = *((char *)h);
h 3562 net/if_spppsubr.c sppp_print_string((char*)(h+1), name_len);
h 3588 net/if_spppsubr.c name_len = *((char *)h);
h 3591 net/if_spppsubr.c sppp_print_string((char*)(h+1), name_len);
h 3606 net/if_spppsubr.c h->type, h->ident, ntohs(h->len));
h 3608 net/if_spppsubr.c sppp_print_bytes((u_char*)(h+1), len-4);
h 3789 net/if_spppsubr.c struct ppp_header *h;
h 3809 net/if_spppsubr.c h = mtod (m, struct ppp_header*);
h 3810 net/if_spppsubr.c h->address = PPP_ALLSTATIONS; /* broadcast address */
h 3811 net/if_spppsubr.c h->control = PPP_UI; /* Unnumbered Info */
h 3812 net/if_spppsubr.c h->protocol = htons(cp->proto);
h 3814 net/if_spppsubr.c lh = (struct lcp_header*)(h + 1);
h 1566 net/pf.c struct ip *h;
h 1617 net/pf.c h = mtod(m, struct ip *);
h 1620 net/pf.c h->ip_p = IPPROTO_TCP;
h 1621 net/pf.c h->ip_len = htons(tlen);
h 1622 net/pf.c h->ip_src.s_addr = saddr->v4.s_addr;
h 1623 net/pf.c h->ip_dst.s_addr = daddr->v4.s_addr;
h 1625 net/pf.c th = (struct tcphdr *)((caddr_t)h + sizeof(struct ip));
h 1667 net/pf.c h->ip_v = 4;
h 1668 net/pf.c h->ip_hl = sizeof(*h) >> 2;
h 1669 net/pf.c h->ip_tos = IPTOS_LOWDELAY;
h 1670 net/pf.c h->ip_len = htons(len);
h 1671 net/pf.c h->ip_off = htons(ip_mtudisc ? IP_DF : 0);
h 1672 net/pf.c h->ip_ttl = ttl ? ttl : ip_defttl;
h 1673 net/pf.c h->ip_sum = 0;
h 2841 net/pf.c struct pfi_kif *kif, struct mbuf *m, int off, void *h,
h 3119 net/pf.c PFLOG_PACKET(kif, h, m, af, direction, reason, r->log ? r : nr,
h 3206 net/pf.c struct ip *h = mtod(m, struct ip *);
h 3209 net/pf.c ntohs(h->ip_len) - off, IPPROTO_TCP, AF_INET))
h 3498 net/pf.c struct mbuf *m, void *h, struct pf_pdesc *pd, struct pf_rule **am,
h 3560 net/pf.c PFLOG_PACKET(kif, h, m, af, direction, reason, r, a, ruleset,
h 3576 net/pf.c struct mbuf *m, int off, void *h, struct pf_pdesc *pd,
h 4035 net/pf.c struct mbuf *m, int off, void *h, struct pf_pdesc *pd)
h 4096 net/pf.c struct mbuf *m, int off, void *h, struct pf_pdesc *pd, u_short *reason)
h 4775 net/pf.c struct ip *h = mtod(m, struct ip *);
h 4776 net/pf.c u_int16_t fragoff = (ntohs(h->ip_off) & IP_OFFMASK) << 3;
h 4788 net/pf.c ntohs(h->ip_len) < off + len) {
h 4798 net/pf.c struct ip6_hdr *h = mtod(m, struct ip6_hdr *);
h 4801 net/pf.c (ntohs(h->ip6_plen) + sizeof(struct ip6_hdr)) <
h 5349 net/pf.c struct ip *h;
h 5379 net/pf.c if (m->m_pkthdr.len < (int)sizeof(*h)) {
h 5395 net/pf.c h = mtod(m, struct ip *);
h 5397 net/pf.c off = h->ip_hl << 2;
h 5398 net/pf.c if (off < (int)sizeof(*h)) {
h 5405 net/pf.c pd.src = (struct pf_addr *)&h->ip_src;
h 5406 net/pf.c pd.dst = (struct pf_addr *)&h->ip_dst;
h 5408 net/pf.c pd.ip_sum = &h->ip_sum;
h 5409 net/pf.c pd.proto = h->ip_p;
h 5411 net/pf.c pd.tos = h->ip_tos;
h 5412 net/pf.c pd.tot_len = ntohs(h->ip_len);
h 5416 net/pf.c if (h->ip_off & htons(IP_MF | IP_OFFMASK)) {
h 5417 net/pf.c action = pf_test_fragment(&r, dir, kif, m, h,
h 5422 net/pf.c switch (h->ip_p) {
h 5436 net/pf.c action = pf_normalize_tcp(dir, kif, m, 0, off, h, &pd);
h 5439 net/pf.c action = pf_test_state_tcp(&s, dir, kif, m, off, h, &pd,
h 5450 net/pf.c m, off, h, &pd, &a, &ruleset, &ipintrq);
h 5470 net/pf.c action = pf_test_state_udp(&s, dir, kif, m, off, h, &pd);
h 5480 net/pf.c m, off, h, &pd, &a, &ruleset, &ipintrq);
h 5493 net/pf.c action = pf_test_state_icmp(&s, dir, kif, m, off, h, &pd,
h 5504 net/pf.c m, off, h, &pd, &a, &ruleset, &ipintrq);
h 5518 net/pf.c action = pf_test_rule(&r, &s, dir, kif, m, off, h,
h 5524 net/pf.c if (action == PF_PASS && h->ip_hl > 5 &&
h 5543 net/pf.c m->m_pkthdr.pf.hdr = h;
h 5567 net/pf.c PFLOG_PACKET(kif, h, m, AF_INET, dir, reason, lr, a, ruleset,
h 5658 net/pf.c struct ip6_hdr *h;
h 5688 net/pf.c if (m->m_pkthdr.len < (int)sizeof(*h)) {
h 5704 net/pf.c h = mtod(m, struct ip6_hdr *);
h 5711 net/pf.c if (htons(h->ip6_plen) == 0) {
h 5718 net/pf.c pd.src = (struct pf_addr *)&h->ip6_src;
h 5719 net/pf.c pd.dst = (struct pf_addr *)&h->ip6_dst;
h 5724 net/pf.c pd.tot_len = ntohs(h->ip6_plen) + sizeof(struct ip6_hdr);
h 5727 net/pf.c off = ((caddr_t)h - m->m_data) + sizeof(struct ip6_hdr);
h 5728 net/pf.c pd.proto = h->ip6_nxt;
h 5732 net/pf.c action = pf_test_fragment(&r, dir, kif, m, h,
h 5811 net/pf.c action = pf_normalize_tcp(dir, kif, m, 0, off, h, &pd);
h 5814 net/pf.c action = pf_test_state_tcp(&s, dir, kif, m, off, h, &pd,
h 5825 net/pf.c m, off, h, &pd, &a, &ruleset, &ip6intrq);
h 5845 net/pf.c action = pf_test_state_udp(&s, dir, kif, m, off, h, &pd);
h 5855 net/pf.c m, off, h, &pd, &a, &ruleset, &ip6intrq);
h 5869 net/pf.c m, off, h, &pd, &reason);
h 5879 net/pf.c m, off, h, &pd, &a, &ruleset, &ip6intrq);
h 5893 net/pf.c action = pf_test_rule(&r, &s, dir, kif, m, off, h,
h 5924 net/pf.c m->m_pkthdr.pf.hdr = h;
h 5943 net/pf.c PFLOG_PACKET(kif, h, m, AF_INET6, dir, reason, lr, a, ruleset,
h 520 net/pf_norm.c pf_fragcache(struct mbuf **m0, struct ip *h, struct pf_fragment **frag, int mff,
h 525 net/pf_norm.c int ip_len = ntohs(h->ip_len) - (h->ip_hl << 2);
h 526 net/pf_norm.c u_int16_t off = ntohs(h->ip_off) << 3;
h 553 net/pf_norm.c (*frag)->fr_src = h->ip_src;
h 554 net/pf_norm.c (*frag)->fr_dst = h->ip_dst;
h 555 net/pf_norm.c (*frag)->fr_p = h->ip_p;
h 556 net/pf_norm.c (*frag)->fr_id = h->ip_id;
h 567 net/pf_norm.c DPFPRINTF(("fragcache[%d]: new %d-%d\n", h->ip_id, off, max));
h 592 net/pf_norm.c h->ip_id, frp->fr_off, frp->fr_end, off, max));
h 598 net/pf_norm.c h->ip_id, frp->fr_off, frp->fr_end, off, max));
h 609 net/pf_norm.c h->ip_id, precut, frp->fr_off, frp->fr_end, off,
h 625 net/pf_norm.c *m0 = m_copym2(m, 0, h->ip_hl << 2, M_NOWAIT);
h 629 net/pf_norm.c m_adj(m, precut + (h->ip_hl << 2));
h 641 net/pf_norm.c h = mtod(m, struct ip *);
h 645 net/pf_norm.c ntohs(h->ip_len) - precut);
h 646 net/pf_norm.c h->ip_off = htons(ntohs(h->ip_off) +
h 648 net/pf_norm.c h->ip_len = htons(ntohs(h->ip_len) - precut);
h 656 net/pf_norm.c h->ip_id, -precut, frp->fr_off, frp->fr_end, off,
h 678 net/pf_norm.c h->ip_id, off, max, fra->fr_off, fra->fr_end));
h 684 net/pf_norm.c h->ip_id, aftercut, off, max, fra->fr_off,
h 700 net/pf_norm.c h = mtod(m, struct ip *);
h 702 net/pf_norm.c ntohs(h->ip_len) - aftercut);
h 703 net/pf_norm.c h->ip_len = htons(ntohs(h->ip_len) - aftercut);
h 710 net/pf_norm.c h->ip_id, -aftercut, off, max, fra->fr_off,
h 730 net/pf_norm.c h->ip_id, cur->fr_off, cur->fr_end, off,
h 743 net/pf_norm.c h->ip_id, frp->fr_off, frp->fr_end, off,
h 779 net/pf_norm.c DPFPRINTF(("fragcache[%d]: done 0-%d\n", h->ip_id,
h 807 net/pf_norm.c h->ip_id));
h 823 net/pf_norm.c struct ip *h = mtod(m, struct ip *);
h 824 net/pf_norm.c int mff = (ntohs(h->ip_off) & IP_MF);
h 825 net/pf_norm.c int hlen = h->ip_hl << 2;
h 826 net/pf_norm.c u_int16_t fragoff = (ntohs(h->ip_off) & IP_OFFMASK) << 3;
h 840 net/pf_norm.c else if (r->proto && r->proto != h->ip_p)
h 843 net/pf_norm.c (struct pf_addr *)&h->ip_src.s_addr, AF_INET,
h 847 net/pf_norm.c (struct pf_addr *)&h->ip_dst.s_addr, AF_INET,
h 865 net/pf_norm.c if (hlen > ntohs(h->ip_len))
h 869 net/pf_norm.c if (r->rule_flag & PFRULE_NODF && h->ip_off & htons(IP_DF)) {
h 870 net/pf_norm.c u_int16_t ip_off = h->ip_off;
h 872 net/pf_norm.c h->ip_off &= htons(~IP_DF);
h 873 net/pf_norm.c h->ip_sum = pf_cksum_fixup(h->ip_sum, ip_off, h->ip_off, 0);
h 884 net/pf_norm.c if (h->ip_off & htons(IP_DF)) {
h 889 net/pf_norm.c ip_len = ntohs(h->ip_len) - hlen;
h 890 net/pf_norm.c ip_off = (ntohs(h->ip_off) & IP_OFFMASK) << 3;
h 908 net/pf_norm.c frag = pf_find_fragment(h, &pf_frag_tree);
h 922 net/pf_norm.c frent->fr_ip = h;
h 926 net/pf_norm.c DPFPRINTF(("reass frag %d @ %d-%d\n", h->ip_id, fragoff, max));
h 935 net/pf_norm.c h = mtod(m, struct ip *);
h 949 net/pf_norm.c frag = pf_find_fragment(h, &pf_cache_tree);
h 959 net/pf_norm.c *m0 = m = pf_fragcache(m0, h, &frag, mff,
h 977 net/pf_norm.c if (h->ip_off & ~htons(IP_DF)) {
h 978 net/pf_norm.c u_int16_t ip_off = h->ip_off;
h 980 net/pf_norm.c h->ip_off &= htons(IP_DF);
h 981 net/pf_norm.c h->ip_sum = pf_cksum_fixup(h->ip_sum, ip_off, h->ip_off, 0);
h 985 net/pf_norm.c if (r->min_ttl && h->ip_ttl < r->min_ttl) {
h 986 net/pf_norm.c u_int16_t ip_ttl = h->ip_ttl;
h 988 net/pf_norm.c h->ip_ttl = r->min_ttl;
h 989 net/pf_norm.c h->ip_sum = pf_cksum_fixup(h->ip_sum, ip_ttl, h->ip_ttl, 0);
h 993 net/pf_norm.c u_int16_t ip_id = h->ip_id;
h 995 net/pf_norm.c h->ip_id = ip_randomid();
h 996 net/pf_norm.c h->ip_sum = pf_cksum_fixup(h->ip_sum, ip_id, h->ip_id, 0);
h 1005 net/pf_norm.c if (r->min_ttl && h->ip_ttl < r->min_ttl) {
h 1006 net/pf_norm.c u_int16_t ip_ttl = h->ip_ttl;
h 1008 net/pf_norm.c h->ip_ttl = r->min_ttl;
h 1009 net/pf_norm.c h->ip_sum = pf_cksum_fixup(h->ip_sum, ip_ttl, h->ip_ttl, 0);
h 1018 net/pf_norm.c PFLOG_PACKET(kif, h, m, AF_INET, dir, *reason, r, NULL, NULL, pd);
h 1024 net/pf_norm.c PFLOG_PACKET(kif, h, m, AF_INET, dir, *reason, r, NULL, NULL, pd);
h 1036 net/pf_norm.c PFLOG_PACKET(kif, h, m, AF_INET, dir, *reason, r, NULL, NULL, pd);
h 1048 net/pf_norm.c struct ip6_hdr *h = mtod(m, struct ip6_hdr *);
h 1071 net/pf_norm.c else if (r->proto && r->proto != h->ip6_nxt)
h 1075 net/pf_norm.c (struct pf_addr *)&h->ip6_src, AF_INET6,
h 1079 net/pf_norm.c (struct pf_addr *)&h->ip6_dst, AF_INET6,
h 1098 net/pf_norm.c proto = h->ip6_nxt;
h 1139 net/pf_norm.c if (h->ip6_plen != 0)
h 1170 net/pf_norm.c if (ntohs(h->ip6_plen) == 0)
h 1173 net/pf_norm.c plen = ntohs(h->ip6_plen);
h 1180 net/pf_norm.c if (r->min_ttl && h->ip6_hlim < r->min_ttl)
h 1181 net/pf_norm.c h->ip6_hlim = r->min_ttl;
h 1186 net/pf_norm.c if (ntohs(h->ip6_plen) == 0 || jumbolen)
h 1188 net/pf_norm.c plen = ntohs(h->ip6_plen);
h 1203 net/pf_norm.c PFLOG_PACKET(kif, h, m, AF_INET6, dir, *reason, r, NULL, NULL, pd);
h 1209 net/pf_norm.c PFLOG_PACKET(kif, h, m, AF_INET6, dir, *reason, r, NULL, NULL, pd);
h 1215 net/pf_norm.c PFLOG_PACKET(kif, h, m, AF_INET6, dir, *reason, r, NULL, NULL, pd);
h 1222 net/pf_norm.c int off, void *h, struct pf_pdesc *pd)
h 1331 net/pf_norm.c PFLOG_PACKET(kif, h, m, AF_INET, dir, reason, r, NULL, NULL, pd);
h 1353 net/pf_norm.c struct ip *h = mtod(m, struct ip *);
h 1354 net/pf_norm.c src->scrub->pfss_ttl = h->ip_ttl;
h 1360 net/pf_norm.c struct ip6_hdr *h = mtod(m, struct ip6_hdr *);
h 1361 net/pf_norm.c src->scrub->pfss_ttl = h->ip6_hlim;
h 1453 net/pf_norm.c struct ip *h = mtod(m, struct ip *);
h 1454 net/pf_norm.c if (h->ip_ttl > src->scrub->pfss_ttl)
h 1455 net/pf_norm.c src->scrub->pfss_ttl = h->ip_ttl;
h 1456 net/pf_norm.c h->ip_ttl = src->scrub->pfss_ttl;
h 1464 net/pf_norm.c struct ip6_hdr *h = mtod(m, struct ip6_hdr *);
h 1465 net/pf_norm.c if (h->ip6_hlim > src->scrub->pfss_ttl)
h 1466 net/pf_norm.c src->scrub->pfss_ttl = h->ip6_hlim;
h 1467 net/pf_norm.c h->ip6_hlim = src->scrub->pfss_ttl;
h 895 net/radix.c rn_walktree(struct radix_node_head *h, int (*f)(struct radix_node *, void *),
h 900 net/radix.c struct radix_node *rn = h->rnh_treetop;
h 567 net/zlib.c #define UPDATE_HASH(s,h,c) (h = (((h)<<s->hash_shift) ^ (c)) & s->hash_mask)
h 1870 net/zlib.c int h; /* heap index */
h 1884 net/zlib.c for (h = s->heap_max+1; h < HEAP_SIZE; h++) {
h 1885 net/zlib.c n = s->heap[h];
h 1926 net/zlib.c m = s->heap[--h];
h 3421 net/zlib.c inflate_huft *h;
h 3426 net/zlib.c h = s->sub.trees.tb + ((uInt)b & inflate_mask[t]);
h 3427 net/zlib.c t = h->word.what.Bits;
h 3428 net/zlib.c c = h->more.Base;
h 3729 net/zlib.c int h; /* table level */
h 3809 net/zlib.c h = -1; /* no tables yet--level -1 */
h 3825 net/zlib.c h++;
h 3848 net/zlib.c if (h)
h 3858 net/zlib.c u[h] = ++q; /* table starts after link */
h 3861 net/zlib.c if (h)
h 3863 net/zlib.c x[h] = i; /* save pattern for backing up */
h 3868 net/zlib.c u[h-1][j] = r; /* connect to last table */
h 3898 net/zlib.c while ((i & ((1 << w) - 1)) != x[h])
h 3900 net/zlib.c h--; /* don't need to update q */
h 372 netbt/hci.h #define HCI_CON_HANDLE(h) ((h) & 0x0fff)
h 373 netbt/hci.h #define HCI_PB_FLAG(h) (((h) & 0x3000) >> 12)
h 374 netbt/hci.h #define HCI_BC_FLAG(h) (((h) & 0xc000) >> 14)
h 375 netbt/hci.h #define HCI_MK_CON_HANDLE(h, pb, bc) \
h 376 netbt/hci.h (((h) & 0x0fff) | (((pb) & 3) << 12) | (((bc) & 3) << 14))
h 264 netinet6/ip6_mroute.h #define MF6CHASHMOD(h) ((h) & (MF6CTBLSIZ - 1))
h 266 netinet6/ip6_mroute.h #define MF6CHASHMOD(h) ((h) % MF6CTBLSIZ)
h 215 sys/pool.h #define pool_get(h, f) _pool_get((h), (f), __FILE__, __LINE__)
h 216 sys/pool.h #define pool_put(h, v) _pool_put((h), (v), __FILE__, __LINE__)
h 217 sys/pool.h #define pool_reclaim(h) _pool_reclaim((h), __FILE__, __LINE__)
h 58 ufs/ext2fs/ext2fs_subr.c #define SETHIGH(q, h) { \
h 61 ufs/ext2fs/ext2fs_subr.c tmp.val[_QUAD_HIGHWORD] = (h); \
h 159 ufs/ffs/ffs_subr.c ffs_isblock(struct fs *fs, unsigned char *cp, daddr_t h)
h 166 ufs/ffs/ffs_subr.c return (cp[h] == 0xff);
h 168 ufs/ffs/ffs_subr.c mask = 0x0f << ((h & 0x1) << 2);
h 169 ufs/ffs/ffs_subr.c return ((cp[h >> 1] & mask) == mask);
h 171 ufs/ffs/ffs_subr.c mask = 0x03 << ((h & 0x3) << 1);
h 172 ufs/ffs/ffs_subr.c return ((cp[h >> 2] & mask) == mask);
h 174 ufs/ffs/ffs_subr.c mask = 0x01 << (h & 0x7);
h 175 ufs/ffs/ffs_subr.c return ((cp[h >> 3] & mask) == mask);
h 183 ufs/ffs/ffs_subr.c ffs_clrblock(struct fs *fs, u_char *cp, daddr_t h)
h 189 ufs/ffs/ffs_subr.c cp[h] = 0;
h 192 ufs/ffs/ffs_subr.c cp[h >> 1] &= ~(0x0f << ((h & 0x1) << 2));
h 195 ufs/ffs/ffs_subr.c cp[h >> 2] &= ~(0x03 << ((h & 0x3) << 1));
h 198 ufs/ffs/ffs_subr.c cp[h >> 3] &= ~(0x01 << (h & 0x7));
h 207 ufs/ffs/ffs_subr.c ffs_setblock(struct fs *fs, unsigned char *cp, daddr_t h)
h 213 ufs/ffs/ffs_subr.c cp[h] = 0xff;
h 216 ufs/ffs/ffs_subr.c cp[h >> 1] |= (0x0f << ((h & 0x1) << 2));
h 219 ufs/ffs/ffs_subr.c cp[h >> 2] |= (0x03 << ((h & 0x3) << 1));
h 222 ufs/ffs/ffs_subr.c cp[h >> 3] |= (0x01 << (h & 0x7));
h 231 ufs/ffs/ffs_subr.c ffs_isfreeblock(struct fs *fs, unsigned char *cp, daddr_t h)
h 237 ufs/ffs/ffs_subr.c return (cp[h] == 0);
h 239 ufs/ffs/ffs_subr.c return ((cp[h >> 1] & (0x0f << ((h & 0x1) << 2))) == 0);
h 241 ufs/ffs/ffs_subr.c return ((cp[h >> 2] & (0x03 << ((h & 0x3) << 1))) == 0);
h 243 ufs/ffs/ffs_subr.c return ((cp[h >> 3] & (0x01 << (h & 0x7))) == 0);
h 86 ufs/ufs/ufs_vnops.c #define SETHIGH(q, h) { \
h 89 ufs/ufs/ufs_vnops.c tmp.val[_QUAD_HIGHWORD] = (h); \
h 80 xfs/xfs_node.c struct nh_node_list *h;
h 83 xfs/xfs_node.c h = &head->nh_nodelist[xfs_hash(handlep)];
h 85 xfs/xfs_node.c NNPQUEUE_FOREACH(nn, h, nn_hash) {
h 100 xfs/xfs_node.c struct nh_node_list *h;
h 102 xfs/xfs_node.c h = &head->nh_nodelist[xfs_hash(&node->handle)];
h 103 xfs/xfs_node.c NNPQUEUE_REMOVE(node, h, nn_hash);
h 113 xfs/xfs_node.c struct nh_node_list *h;
h 115 xfs/xfs_node.c h = &head->nh_nodelist[xfs_hash(&node->handle)];
h 116 xfs/xfs_node.c NNPQUEUE_INSERT_HEAD(h, node, nn_hash);