root/dev/ic/tcic2var.h

INCLUDED FROM

DEFINITIONS

1. tcic_read_1
2. tcic_read_2
3. tcic_read_4
4. tcic_write_1
5. tcic_write_2
6. tcic_write_4
7. tcic_read_ind_2
8. tcic_write_ind_2
9. tcic_sel_sock
10. tcic_wait_ready
11. tcic_read_aux_1
12. tcic_read_aux_2
13. tcic_write_aux_1
14. tcic_write_aux_2

    1 /*      $OpenBSD: tcic2var.h,v 1.4 2005/11/23 11:39:37 mickey Exp $     */
    2 /*      $NetBSD: tcic2var.h,v 1.1 1999/03/23 20:04:14 bad Exp $ */
    4 /*
    5  * Copyright (c) 1998, 1999 Christoph Badura.  All rights reserved.
    6  * Copyright (c) 1997 Marc Horowitz.  All rights reserved.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  * 3. All advertising materials mentioning features or use of this software
   17  *    must display the following acknowledgement:
   18  *      This product includes software developed by Marc Horowitz.
   19  * 4. The name of the author may not be used to endorse or promote products
   20  *    derived from this software without specific prior written permission.
   21  *
   22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   24  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   25  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   28  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   29  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   32  */
   34 #ifndef _TCIC2VAR_H
   35 #define _TCIC2VAR_H
   37 #include <sys/device.h>
   39 #include <dev/pcmcia/pcmciareg.h>
   40 #include <dev/pcmcia/pcmciachip.h>
   42 #include <dev/ic/tcic2reg.h>
   44 struct proc;
   46 struct tcic_event {
SIMPLEQ_ENTRY(tcic_event) pe_q;
   48         int pe_type;
   49 };
   51 /* pe_type */
   52 #define TCIC_EVENT_INSERTION    0
   53 #define TCIC_EVENT_REMOVAL      1
   56 struct tcic_handle {
   57         struct tcic_softc *sc;
   58         int     sock;                           /* socket number */
   59         int     flags;
   60         int     sstat;                          /* last value of R_SSTAT */
   61         int     memalloc;
   62         int     memwins;
   63         struct {
bus_addr_t      addr;
bus_size_t      size;
   66                 int             size2;          /* size as 2^n scaled by 4K */
   67                 long            offset;
   68                 int             speed;          /* in ns */
   69                 int             kind;
   70         } mem[TCIC_MAX_MEM_WINS];
   71         int     ioalloc;
   72         struct {
bus_addr_t      addr;
bus_size_t      size;
   75                 int             width;
   76                 int             speed;          /* in ns */
   77         } io[TCIC_IO_WINS];
   78         int     ih_irq;
   79         struct device *pcmcia;
   81         int shutdown;
   82         struct proc *event_thread;
SIMPLEQ_HEAD(, tcic_event) events;
   84 };
   86 #define TCIC_FLAG_SOCKETP       0x0001
   87 #define TCIC_FLAG_CARDP         0x0002
   89 /*
   90  * This is sort of arbitrary.  It merely needs to be "enough". It can be
   91  * overridden in the conf file, anyway.
   92  */
   94 #define TCIC_MEM_PAGES  4
   95 #define TCIC_MEMSIZE    TCIC_MEM_PAGES*TCIC_MEM_PAGESIZE
   97 #define TCIC_NSLOTS     2
   99 struct tcic_softc {
  100         struct device dev;
bus_space_tag_t memt;
bus_space_handle_t memh;
bus_space_tag_t iot;
bus_space_handle_t ioh;
  107         int     chipid;
  108         int     validirqs;
  109         int     pwrena;         /* holds TCIC_PWR_ENA on'084 and successors */
  111         /* XXX isa_chipset_tag_t, pci_chipset_tag_t, etc. */
  112         void    *intr_est;
pcmcia_chipset_tag_t pct;
  116         /* this needs to be large enough to hold TCIC_MEM_PAGES bits */
  117         int     subregionmask;
  119         /* used by memory window mapping functions */
bus_addr_t membase;
  121         int     memsize2;               /* int(log2(memsize)) */
  123         /*
  124          * used by io window mapping functions.  These can actually overlap
  125          * with another tcic, since the underlying extent mapper will deal
  126          * with individual allocations.  This is here to deal with the fact
  127          * that different busses have different real widths (different pc
  128          * hardware seems to use 10 or 12 bits for the I/O bus).
  129          */
bus_addr_t iobase;
bus_size_t iosize;
  133         int     irq;
  134         void    *ih;
  136         struct tcic_handle handle[TCIC_NSLOTS];
  137 };
  139 int     tcic_log2(u_int);
  140 int     tcic_ns2wscnt(int);
  142 int     tcic_check_reserved_bits(bus_space_tag_t, bus_space_handle_t);
  143 int     tcic_chipid(bus_space_tag_t, bus_space_handle_t);
  144 int     tcic_chipid_known(int);
  145 char    *tcic_chipid_to_string(int);
  146 int     tcic_validirqs(int);
  148 void    tcic_attach(struct tcic_softc *);
  149 void    tcic_attach_sockets(struct tcic_softc *);
  150 int     tcic_intr(void *arg);
  152 static __inline__ int tcic_read_1(struct tcic_handle *, int);
  153 static __inline__ int tcic_read_2(struct tcic_handle *, int);
  154 static __inline__ int tcic_read_4(struct tcic_handle *, int);
  155 static __inline__ void tcic_write_1(struct tcic_handle *, int, int);
  156 static __inline__ void tcic_write_2(struct tcic_handle *, int, int);
  157 static __inline__ void tcic_write_4(struct tcic_handle *, int, int);
  158 static __inline__ int tcic_read_ind_2(struct tcic_handle *, int);
  159 static __inline__ void tcic_write_ind_2(struct tcic_handle *, int, int);
  160 static __inline__ void tcic_sel_sock(struct tcic_handle *);
  161 static __inline__ void tcic_wait_ready(struct tcic_handle *);
  162 static __inline__ int tcic_read_aux_1(bus_space_tag_t, bus_space_handle_t, int, int);
  163 static __inline__ int tcic_read_aux_2(bus_space_tag_t, bus_space_handle_t, int);
  164 static __inline__ void tcic_write_aux_1(bus_space_tag_t, bus_space_handle_t, int, int, int);
  165 static __inline__ void tcic_write_aux_2(bus_space_tag_t, bus_space_handle_t, int, int);
  167 int     tcic_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t,
  168             struct pcmcia_mem_handle *);
  169 void    tcic_chip_mem_free(pcmcia_chipset_handle_t,
  170             struct pcmcia_mem_handle *);
  171 int     tcic_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t,
bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *);
  173 void    tcic_chip_mem_unmap(pcmcia_chipset_handle_t, int);
  175 int     tcic_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t,
bus_size_t, bus_size_t, struct pcmcia_io_handle *);
  177 void    tcic_chip_io_free(pcmcia_chipset_handle_t,
  178             struct pcmcia_io_handle *);
  179 int     tcic_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t,
bus_size_t, struct pcmcia_io_handle *, int *);
  181 void    tcic_chip_io_unmap(pcmcia_chipset_handle_t, int);
  183 void    tcic_chip_socket_enable(pcmcia_chipset_handle_t);
  184 void    tcic_chip_socket_disable(pcmcia_chipset_handle_t);
  186 static __inline__ int tcic_read_1(struct tcic_handle *, int);
  187 static __inline__ int
tcic_read_1(h, reg)
  189         struct tcic_handle *h;
  190         int reg;
  191 {
  192         return (bus_space_read_1(h->sc->iot, h->sc->ioh, reg));
  193 }
  195 static __inline__ int tcic_read_2(struct tcic_handle *, int);
  196 static __inline__ int
tcic_read_2(h, reg)
  198         struct tcic_handle *h;
  199         int reg;
  200 {
  201         return (bus_space_read_2(h->sc->iot, h->sc->ioh, reg));
  202 }
  204 static __inline__ int tcic_read_4(struct tcic_handle *, int);
  205 static __inline__ int
tcic_read_4(h, reg)
  207         struct tcic_handle *h;
  208         int reg;
  209 {
  210         int val;
val = bus_space_read_2(h->sc->iot, h->sc->ioh, reg);
val |= bus_space_read_2(h->sc->iot, h->sc->ioh, reg+2) << 16;
  213         return val;
  214 }
  216 static __inline__ void tcic_write_1(struct tcic_handle *, int, int);
  217 static __inline__ void
tcic_write_1(h, reg, data)
  219         struct tcic_handle *h;
  220         int reg;
  221         int data;
  222 {
bus_space_write_1(h->sc->iot, h->sc->ioh, reg, (data));
  224 }
  226 static __inline__ void tcic_write_2(struct tcic_handle *, int, int);
  227 static __inline__ void
tcic_write_2(h, reg, data)
  229         struct tcic_handle *h;
  230         int reg;
  231         int data;
  232 {
bus_space_write_2(h->sc->iot, h->sc->ioh, reg, (data));
  234 }
  236 static __inline__ void tcic_write_4(struct tcic_handle *, int, int);
  237 static __inline__ void
tcic_write_4(h, reg, data)
  239         struct tcic_handle *h;
  240         int reg;
  241         int data;
  242 {
bus_space_write_2(h->sc->iot, h->sc->ioh, reg, (data));
bus_space_write_2(h->sc->iot, h->sc->ioh, reg+2, (data)>>16);
  245 }
  247 static __inline__ int tcic_read_ind_2(struct tcic_handle *, int);
  248 static __inline__ int
tcic_read_ind_2(h, reg)
  250         struct tcic_handle *h;
  251         int reg;
  252 {
  253         int r_addr, val;
r_addr = tcic_read_4(h, TCIC_R_ADDR);
tcic_write_4(h, TCIC_R_ADDR, reg|TCIC_ADDR_INDREG);
val = bus_space_read_2(h->sc->iot, h->sc->ioh, TCIC_R_DATA);
tcic_write_4(h, TCIC_R_ADDR, r_addr);
  258         return val;
  259 }
  261 static __inline__ void tcic_write_ind_2(struct tcic_handle *, int, int);
  262 static __inline__ void
tcic_write_ind_2(h, reg, data)
  264         struct tcic_handle *h;
  265         int reg;
  266         int data;
  267 {
  268         int r_addr;
r_addr = tcic_read_4(h, TCIC_R_ADDR);
tcic_write_4(h, TCIC_R_ADDR, reg|TCIC_ADDR_INDREG);
bus_space_write_2(h->sc->iot, h->sc->ioh, TCIC_R_DATA, (data));
tcic_write_4(h, TCIC_R_ADDR, r_addr);
  273 }
  275 static __inline__ void tcic_sel_sock(struct tcic_handle *);
  276 static __inline__ void
tcic_sel_sock(h)
  278         struct tcic_handle *h;
  279 {
  280         int r_addr;
r_addr = tcic_read_2(h, TCIC_R_ADDR2);
tcic_write_2(h, TCIC_R_ADDR2,
  283             (h->sock<<TCIC_ADDR2_SS_SHFT)|(r_addr & ~TCIC_ADDR2_SS_MASK));
  284 }
  286 static __inline__ void tcic_wait_ready(struct tcic_handle *);
  287 static __inline__ void
tcic_wait_ready(h)
  289         struct tcic_handle *h;
  290 {
  291         int i;
  293         /* XXX appropriate socket must have been selected already. */
  294         for (i = 0; i < 10000; i++) {
  295                 if (tcic_read_1(h, TCIC_R_SSTAT) & TCIC_SSTAT_RDY)
  296                         return;
delay(500);
  298         }
  300 #ifdef DIAGNOSTIC
printf("tcic_wait_ready ready never happened\n");
  302 #endif
  303 }
  305 static __inline__ int tcic_read_aux_1(bus_space_tag_t, bus_space_handle_t, int, int);
  306 static __inline__ int
tcic_read_aux_1(iot, ioh, auxreg, reg)
bus_space_tag_t iot;
bus_space_handle_t ioh;
  310         int auxreg, reg;
  311 {
  312         int mode, val;
mode = bus_space_read_1(iot, ioh, TCIC_R_MODE);
bus_space_write_1(iot, ioh, TCIC_R_MODE, (mode & ~TCIC_AR_MASK)|auxreg);
val = bus_space_read_1(iot, ioh, reg);
  316         return val;
  317 }
  319 static __inline__ int tcic_read_aux_2(bus_space_tag_t, bus_space_handle_t, int);
  320 static __inline__ int
tcic_read_aux_2(iot, ioh, auxreg)
bus_space_tag_t iot;
bus_space_handle_t ioh;
  324         int auxreg;
  325 {
  326         int mode, val;
mode = bus_space_read_1(iot, ioh, TCIC_R_MODE);
bus_space_write_1(iot, ioh, TCIC_R_MODE, (mode & ~TCIC_AR_MASK)|auxreg);
val = bus_space_read_2(iot, ioh, TCIC_R_AUX);
  330         return val;
  331 }
  333 static __inline__ void tcic_write_aux_1(bus_space_tag_t, bus_space_handle_t, int, int, int);
  334 static __inline__ void
tcic_write_aux_1(iot, ioh, auxreg, reg, val)
bus_space_tag_t iot;
bus_space_handle_t ioh;
  338         int auxreg, reg, val;
  339 {
  340         int mode;
mode = bus_space_read_1(iot, ioh, TCIC_R_MODE);
bus_space_write_1(iot, ioh, TCIC_R_MODE, (mode & ~TCIC_AR_MASK)|auxreg);
bus_space_write_1(iot, ioh, reg, val);
  344 }
  346 static __inline__ void tcic_write_aux_2(bus_space_tag_t, bus_space_handle_t, int, int);
  347 static __inline__ void
tcic_write_aux_2(iot, ioh, auxreg, val)
bus_space_tag_t iot;
bus_space_handle_t ioh;
  351         int auxreg, val;
  352 {
  353         int mode;
mode = bus_space_read_1(iot, ioh, TCIC_R_MODE);
bus_space_write_1(iot, ioh, TCIC_R_MODE, (mode & ~TCIC_AR_MASK)|auxreg);
bus_space_write_2(iot, ioh, TCIC_R_AUX, val);
  357 }
  359 #endif  /* _TCIC2VAR_H */