root/dev/ic/tcic2.c

DEFINITIONS

1. tcic_check_reserved_bits
2. tcic_chipid
3. tcic_chipid_known
4. tcic_chipid_to_string
5. tcic_validirqs
6. tcic_attach
7. tcic_attach_sockets
8. tcic_attach_socket
9. tcic_create_event_thread
10. tcic_event_thread
11. tcic_init_socket
12. tcic_submatch
13. tcic_print
14. tcic_intr
15. tcic_intr_socket
16. tcic_queue_event
17. tcic_attach_card
18. tcic_detach_card
19. tcic_deactivate_card
20. tcic_chip_mem_alloc
21. tcic_chip_mem_free
22. tcic_chip_do_mem_map
23. tcic_chip_mem_map
24. tcic_chip_mem_unmap
25. tcic_chip_io_alloc
26. tcic_chip_io_free
27. tcic_chip_do_io_map
28. tcic_chip_io_map
29. tcic_chip_io_unmap
30. tcic_chip_socket_enable
31. tcic_chip_socket_disable
32. tcic_ns2wscnt
33. tcic_log2

    1 /*      $OpenBSD: tcic2.c,v 1.7 2005/11/23 11:39:37 mickey Exp $        */
    2 /*      $NetBSD: tcic2.c,v 1.3 2000/01/13 09:38:17 joda Exp $   */
    4 #undef  TCICDEBUG
    6 /*
    7  * Copyright (c) 1998, 1999 Christoph Badura.  All rights reserved.
    8  * Copyright (c) 1997 Marc Horowitz.  All rights reserved.
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  * 3. All advertising materials mentioning features or use of this software
   19  *    must display the following acknowledgement:
   20  *      This product includes software developed by Marc Horowitz.
   21  * 4. The name of the author may not be used to endorse or promote products
   22  *    derived from this software without specific prior written permission.
   23  *
   24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   25  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   26  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   27  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   28  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   29  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   30  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   31  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   32  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   33  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   34  */
   36 #include <sys/types.h>
   37 #include <sys/param.h>
   38 #include <sys/systm.h>
   39 #include <sys/device.h>
   40 #include <sys/extent.h>
   41 #include <sys/malloc.h>
   42 #include <sys/kthread.h>
   44 #include <uvm/uvm_extern.h>
   46 #include <machine/bus.h>
   47 #include <machine/intr.h>
   49 #include <dev/pcmcia/pcmciareg.h>
   50 #include <dev/pcmcia/pcmciavar.h>
   52 #include <dev/ic/tcic2reg.h>
   53 #include <dev/ic/tcic2var.h>
   55 #ifdef TCICDEBUG
   56 int     tcic_debug = 1;
   57 #define DPRINTF(arg) if (tcic_debug) printf arg;
   58 #else
   59 #define DPRINTF(arg)
   60 #endif
   62 /*
   63  * Individual drivers will allocate their own memory and io regions. Memory
   64  * regions must be a multiple of 4k, aligned on a 4k boundary.
   65  */
   67 #define TCIC_MEM_ALIGN  TCIC_MEM_PAGESIZE
   69 void    tcic_attach_socket(struct tcic_handle *);
   70 void    tcic_init_socket(struct tcic_handle *);
   72 int     tcic_submatch(struct device *, void *, void *);
   73 int     tcic_print(void *arg, const char *pnp);
   74 int     tcic_intr_socket(struct tcic_handle *);
   76 void    tcic_attach_card(struct tcic_handle *);
   77 void    tcic_detach_card(struct tcic_handle *, int);
   78 void    tcic_deactivate_card(struct tcic_handle *);
   80 void    tcic_chip_do_mem_map(struct tcic_handle *, int);
   81 void    tcic_chip_do_io_map(struct tcic_handle *, int);
   83 void    tcic_create_event_thread(void *);
   84 void    tcic_event_thread(void *);
   86 void    tcic_queue_event(struct tcic_handle *, int);
   88 struct cfdriver tcic_cd = {
NULL, "tcic", DV_DULL
   90 };
   92 /* Map between irq numbers and internal representation */
   93 #if 1
   94 int tcic_irqmap[] =
   95     { 0, 0, 0, 3, 4, 5, 6, 7, 0, 0, 10, 1, 0, 0, 14, 0 };
   96 int tcic_valid_irqs = 0x4cf8;
   97 #else
   98 int tcic_irqmap[] =     /* irqs 9 and 6 switched, some ISA cards */
   99     { 0, 0, 0, 3, 4, 5, 0, 7, 0, 6, 10, 1, 0, 0, 14, 0 };
  100 int tcic_valid_irqs = 0x4eb8;
  101 #endif
  103 int tcic_mem_speed = 250;       /* memory access time in nanoseconds */
  104 int tcic_io_speed = 165;        /* io access time in nanoseconds */
  106 /*
  107  * Check various reserved and otherwise in their value restricted bits.
  108  */
  109 int
tcic_check_reserved_bits(iot, ioh)
bus_space_tag_t iot;
bus_space_handle_t ioh;
  113 {
  114         int val, auxreg;
DPRINTF(("tcic: chkrsvd 1\n"));
  117         /* R_ADDR bit 30:28 have a restricted range. */
val = (bus_space_read_2(iot, ioh, TCIC_R_ADDR2) & TCIC_SS_MASK)
  119             >> TCIC_SS_SHIFT;
  120         if (val > 1)
  121                 return 0;
DPRINTF(("tcic: chkrsvd 2\n"));
  124         /* R_SCTRL bits 6,2,1 are reserved. */
val = bus_space_read_1(iot, ioh, TCIC_R_SCTRL);
  126         if (val & TCIC_SCTRL_RSVD)
  127                 return 0;
DPRINTF(("tcic: chkrsvd 3\n"));
  130         /* R_ICSR bit 2 must be same as bit 3. */
val = bus_space_read_1(iot, ioh, TCIC_R_ICSR);
  132         if (((val >> 1) & 1) != ((val >> 2) & 1))
  133                 return 0;
DPRINTF(("tcic: chkrsvd 4\n"));
  136         /* R_IENA bits 7,2 are reserved. */
val = bus_space_read_1(iot, ioh, TCIC_R_IENA);
  138         if (val & TCIC_IENA_RSVD)
  139                 return 0;
DPRINTF(("tcic: chkrsvd 5\n"));
  142         /* Some aux registers have reserved bits. */
  143         /* Which are we looking at? */
auxreg = bus_space_read_1(iot, ioh, TCIC_R_MODE)
  145             & TCIC_AR_MASK;
val = bus_space_read_2(iot, ioh, TCIC_R_AUX);
DPRINTF(("tcic: auxreg 0x%02x val 0x%04x\n", auxreg, val));
  148         switch (auxreg) {
  149         case TCIC_AR_SYSCFG:
  150                 if (INVALID_AR_SYSCFG(val))
  151                         return 0;
  152                 break;
  153         case TCIC_AR_ILOCK:
  154                 if (INVALID_AR_ILOCK(val))
  155                         return 0;
  156                 break;
  157         case TCIC_AR_TEST:
  158                 if (INVALID_AR_TEST(val))
  159                         return 0;
  160                 break;
  161         }
DPRINTF(("tcic: chkrsvd 6\n"));
  164         /* XXX fails if pcmcia bios is enabled. */
  165         /* Various bits set or not depending if in RESET mode. */
val = bus_space_read_1(iot, ioh, TCIC_R_SCTRL);
  167         if (val & TCIC_SCTRL_RESET) {
DPRINTF(("tcic: chkrsvd 7\n"));
  169                 /* Address bits must be 0 */
val = bus_space_read_2(iot, ioh, TCIC_R_ADDR);
  171                 if (val != 0)
  172                         return 0;
val = bus_space_read_2(iot, ioh, TCIC_R_ADDR2);
  174                 if (val != 0)
  175                         return 0;
DPRINTF(("tcic: chkrsvd 8\n"));
  177                 /* EDC bits must be 0 */
val = bus_space_read_2(iot, ioh, TCIC_R_EDC);
  179                 if (val != 0)
  180                         return 0;
  181                 /* We're OK, so take it out of reset. XXX -chb */
bus_space_write_1(iot, ioh, TCIC_R_SCTRL, 0);
  183         }
  184         else {  /* not in RESET mode */
  185                 int omode;
  186                 int val1, val2;
DPRINTF(("tcic: chkrsvd 9\n"));
  188                 /* Programming timers must have expired. */
val = bus_space_read_1(iot, ioh, TCIC_R_SSTAT);
  190                 if ((val & (TCIC_SSTAT_6US|TCIC_SSTAT_10US|TCIC_SSTAT_PROGTIME))
  191                     != (TCIC_SSTAT_6US|TCIC_SSTAT_10US|TCIC_SSTAT_PROGTIME))
  192                         return 0;
DPRINTF(("tcic: chkrsvd 10\n"));
  194                 /*
  195                  * EDC bits should change on read from data space
  196                  * as long as either EDC or the data are nonzero.
  197                  */
  198                  if ((bus_space_read_2(iot, ioh, TCIC_R_ADDR2)
  199                      & TCIC_ADDR2_INDREG) != 0) {
val1 = bus_space_read_2(iot, ioh, TCIC_R_EDC);
val2 = bus_space_read_2(iot, ioh, TCIC_R_DATA);
  202                         if (val1 | val2) {
val1 = bus_space_read_2(iot, ioh, TCIC_R_EDC);
  204                                 if (val1 == val2)
  205                                         return 0;
  206                         }
  207                 }
DPRINTF(("tcic: chkrsvd 11\n"));
  209                 /* XXX what does this check? -chb */
omode = bus_space_read_1(iot, ioh, TCIC_R_MODE);
val1 = omode ^ TCIC_AR_MASK;
bus_space_write_1(iot, ioh, TCIC_R_MODE, val1);
val2 = bus_space_read_1(iot, ioh, TCIC_R_MODE);
bus_space_write_1(iot, ioh, TCIC_R_MODE, omode);
  215                 if ( val1 != val2)
  216                         return 0;
  217         }
  218         /* All tests passed */
  219         return 1;
  220 }
  222 /*
  223  * Read chip ID from AR_ILOCK in test mode.
  224  */
  225 int
tcic_chipid(iot, ioh)
bus_space_tag_t iot;
bus_space_handle_t ioh;
  229 {
  230         unsigned id, otest;
otest = tcic_read_aux_2(iot, ioh, TCIC_AR_TEST);
tcic_write_aux_2(iot, ioh, TCIC_AR_TEST, TCIC_TEST_DIAG);
id = tcic_read_aux_2(iot, ioh, TCIC_AR_ILOCK);
tcic_write_aux_2(iot, ioh, TCIC_AR_TEST, otest);
id &= TCIC_ILOCKTEST_ID_MASK;
id >>= TCIC_ILOCKTEST_ID_SHFT;
  239         /* clear up IRQs inside tcic. XXX -chb */
  240         while (bus_space_read_1(iot, ioh, TCIC_R_ICSR))
bus_space_write_1(iot, ioh, TCIC_R_ICSR, TCIC_ICSR_JAM);
  243         return id;
  244 }
  245 /*
  246  * Indicate whether the driver can handle the chip.
  247  */
  248 int
tcic_chipid_known(id)
  250         int id;
  251 {
  252         /* XXX only know how to handle DB86082 -chb */
  253         switch (id) {
  254         case TCIC_CHIPID_DB86082_1:
  255         case TCIC_CHIPID_DB86082A:
  256         case TCIC_CHIPID_DB86082B_ES:
  257         case TCIC_CHIPID_DB86082B:
  258         case TCIC_CHIPID_DB86084_1:
  259         case TCIC_CHIPID_DB86084A:
  260         case TCIC_CHIPID_DB86184_1:
  261         case TCIC_CHIPID_DB86072_1_ES:
  262         case TCIC_CHIPID_DB86072_1:
  263                 return 1;
  264         }
  266         return 0;
  267 }
  269 char *
tcic_chipid_to_string(id)
  271         int id;
  272 {
  273         switch (id) {
  274         case TCIC_CHIPID_DB86082_1:
  275                 return ("Databook DB86082");
  276         case TCIC_CHIPID_DB86082A:
  277                 return ("Databook DB86082A");
  278         case TCIC_CHIPID_DB86082B_ES:
  279                 return ("Databook DB86082B-es");
  280         case TCIC_CHIPID_DB86082B:
  281                 return ("Databook DB86082B");
  282         case TCIC_CHIPID_DB86084_1:
  283                 return ("Databook DB86084");
  284         case TCIC_CHIPID_DB86084A:
  285                 return ("Databook DB86084A");
  286         case TCIC_CHIPID_DB86184_1:
  287                 return ("Databook DB86184");
  288         case TCIC_CHIPID_DB86072_1_ES:
  289                 return ("Databook DB86072-es");
  290         case TCIC_CHIPID_DB86072_1:
  291                 return ("Databook DB86072");
  292         }
  294         return ("Unknown controller");
  295 }
  296 /*
  297  * Return bitmask of IRQs that the chip can handle.
  298  * XXX should be table driven.
  299  */
  300 int
tcic_validirqs(chipid)
  302         int chipid;
  303 {
  304         switch (chipid) {
  305         case TCIC_CHIPID_DB86082_1:
  306         case TCIC_CHIPID_DB86082A:
  307         case TCIC_CHIPID_DB86082B_ES:
  308         case TCIC_CHIPID_DB86082B:
  309         case TCIC_CHIPID_DB86084_1:
  310         case TCIC_CHIPID_DB86084A:
  311         case TCIC_CHIPID_DB86184_1:
  312         case TCIC_CHIPID_DB86072_1_ES:
  313         case TCIC_CHIPID_DB86072_1:
  314                 return tcic_valid_irqs;
  315         }
  316         return 0;
  317 }
  319 void
tcic_attach(sc)
  321         struct tcic_softc *sc;
  322 {
  323         int i, reg;
  325         /* set more chipset-dependent parameters in the softc. */
  326         switch (sc->chipid) {
  327         case TCIC_CHIPID_DB86084_1:
  328         case TCIC_CHIPID_DB86084A:
  329         case TCIC_CHIPID_DB86184_1:
sc->pwrena = TCIC_PWR_ENA;
  331                 break;
  332         default:
sc->pwrena = 0;
  334                 break;
  335         }
  337         /* set up global config registers */
reg = TCIC_WAIT_SYNC | TCIC_WAIT_CCLK | TCIC_WAIT_RISING;
reg |= (tcic_ns2wscnt(250) & TCIC_WAIT_COUNT_MASK);
tcic_write_aux_1(sc->iot, sc->ioh, TCIC_AR_WCTL, TCIC_R_WCTL_WAIT, reg);
reg = TCIC_SYSCFG_MPSEL_RI | TCIC_SYSCFG_MCSFULL;
tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, reg);
reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_ILOCK);
reg |= TCIC_ILOCK_HOLD_CCLK;
tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_ILOCK, reg);
  347         /* the TCIC has two sockets */
  348         /* XXX should i check for actual presence of sockets? -chb */
  349         for (i = 0; i < TCIC_NSLOTS; i++) {
sc->handle[i].sc = sc;
sc->handle[i].sock = i;
sc->handle[i].flags = TCIC_FLAG_SOCKETP;
sc->handle[i].memwins
  354                     = sc->chipid == TCIC_CHIPID_DB86082_1 ?  4 : 5;
  355         }
  357         /* establish the interrupt */
reg = tcic_read_1(&sc->handle[0], TCIC_R_IENA);
tcic_write_1(&sc->handle[0], TCIC_R_IENA,
  360             (reg & ~TCIC_IENA_CFG_MASK) | TCIC_IENA_CFG_HIGH);
reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG);
tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG,
  363             (reg & ~TCIC_SYSCFG_IRQ_MASK) | tcic_irqmap[sc->irq]);
  365         /* XXX block interrupts? */
  367         for (i = 0; i < TCIC_NSLOTS; i++) {
  368                 /* XXX make more clear what happens here -chb */
tcic_sel_sock(&sc->handle[i]);
tcic_write_ind_2(&sc->handle[i], TCIC_IR_SCF1_N(i), 0);
tcic_write_ind_2(&sc->handle[i], TCIC_IR_SCF2_N(i), 
  372                     (TCIC_SCF2_MCD|TCIC_SCF2_MWP|TCIC_SCF2_MRDY
  373 #if 1           /* XXX explain byte routing issue */
  374                     |TCIC_SCF2_MLBAT2|TCIC_SCF2_MLBAT1|TCIC_SCF2_IDBR));
  375 #else
  376                     |TCIC_SCF2_MLBAT2|TCIC_SCF2_MLBAT1));
  377 #endif
tcic_write_1(&sc->handle[i], TCIC_R_MODE, 0);
reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG);
reg &= ~TCIC_SYSCFG_AUTOBUSY;
tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, reg);
SIMPLEQ_INIT(&sc->handle[i].events);
  383         }
  385         if ((sc->handle[0].flags & TCIC_FLAG_SOCKETP) ||
  386             (sc->handle[1].flags & TCIC_FLAG_SOCKETP)) {
printf("%s: %s has ", sc->dev.dv_xname,
tcic_chipid_to_string(sc->chipid));
  390                 if ((sc->handle[0].flags & TCIC_FLAG_SOCKETP) &&
  391                     (sc->handle[1].flags & TCIC_FLAG_SOCKETP))
printf("sockets A and B\n");
  393                 else if (sc->handle[0].flags & TCIC_FLAG_SOCKETP)
printf("socket A only\n");
  395                 else
printf("socket B only\n");
  398         }
  399 }
  401 void
tcic_attach_sockets(sc)
  403         struct tcic_softc *sc;
  404 {
  405         int i;
  407         for (i = 0; i < TCIC_NSLOTS; i++)
  408                 if (sc->handle[i].flags & TCIC_FLAG_SOCKETP)
tcic_attach_socket(&sc->handle[i]);
  410 }
  412 void
tcic_attach_socket(h)
  414         struct tcic_handle *h;
  415 {
  416         struct pcmciabus_attach_args paa;
  418         /* initialize the rest of the handle */
h->shutdown = 0;
h->memalloc = 0;
h->ioalloc = 0;
h->ih_irq = 0;
  425         /* now, config one pcmcia device per socket */
paa.paa_busname = "pcmcia";
paa.pct = (pcmcia_chipset_tag_t) h->sc->pct;
paa.pch = (pcmcia_chipset_handle_t) h;
paa.iobase = h->sc->iobase;
paa.iosize = h->sc->iosize;
h->pcmcia = config_found_sm(&h->sc->dev, &paa, tcic_print,
tcic_submatch);
  436         /* if there's actually a pcmcia device attached, initialize the slot */
  438         if (h->pcmcia)
tcic_init_socket(h);
  440         else
h->flags &= ~TCIC_FLAG_SOCKETP;
  442 }
  444 void
tcic_create_event_thread(arg)
  446         void *arg;
  447 {
  448         struct tcic_handle *h = arg;
  449         const char *cs;
  451         switch (h->sock) {
  452         case 0:
cs = "0";
  454                 break;
  455         case 1:
cs = "1";
  457                 break;
  458         default:
panic("tcic_create_event_thread: unknown tcic socket");
  460         }
  462         if (kthread_create(tcic_event_thread, h, &h->event_thread,
  463             "%s,%s", h->sc->dev.dv_xname, cs)) {
printf("%s: unable to create event thread for sock 0x%02x\n",
h->sc->dev.dv_xname, h->sock);
panic("tcic_create_event_thread");
  467         }
  468 }
  470 void
tcic_event_thread(arg)
  472         void *arg;
  473 {
  474         struct tcic_handle *h = arg;
  475         struct tcic_event *pe;
  476         int s;
  478         while (h->shutdown == 0) {
s = splhigh();
  480                 if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) {
splx(s);
  482                         (void) tsleep(&h->events, PWAIT, "tcicev", 0);
  483                         continue;
  484                 }
SIMPLEQ_REMOVE_HEAD(&h->events, pe_q);
splx(s);
  488                 switch (pe->pe_type) {
  489                 case TCIC_EVENT_INSERTION:
DPRINTF(("%s: insertion event\n", h->sc->dev.dv_xname));
tcic_attach_card(h);
  492                         break;
  494                 case TCIC_EVENT_REMOVAL:
DPRINTF(("%s: removal event\n", h->sc->dev.dv_xname));
tcic_detach_card(h, DETACH_FORCE);
  497                         break;
  499                 default:
panic("tcic_event_thread: unknown event %d",
pe->pe_type);
  502                 }
free(pe, M_TEMP);
  504         }
h->event_thread = NULL;
  508         /* In case parent is waiting for us to exit. */
wakeup(h->sc);
kthread_exit(0);
  512 }
  515 void
tcic_init_socket(h)
  517         struct tcic_handle *h;
  518 {
  519         int reg;
  521         /* select this socket's config registers */
tcic_sel_sock(h);
  524         /* set up the socket to interrupt on card detect */
reg = tcic_read_ind_2(h, TCIC_IR_SCF2_N(h->sock));
tcic_write_ind_2(h, TCIC_IR_SCF2_N(h->sock), reg & ~TCIC_SCF2_MCD);
  528         /* enable CD irq in R_IENA */
reg = tcic_read_2(h, TCIC_R_IENA);
tcic_write_2(h, TCIC_R_IENA, reg |= TCIC_IENA_CDCHG);
  532         /* if there's a card there, then attach it. also save sstat */
h->sstat = reg = tcic_read_1(h, TCIC_R_SSTAT) & TCIC_SSTAT_STAT_MASK;
  534         if (reg & TCIC_SSTAT_CD)
tcic_attach_card(h);
  536 }
  538 int
tcic_submatch(parent, match, aux)
  540         struct device *parent;
  541         void *match;
  542         void *aux;
  543 {
  544         struct cfdata *cf = match;
  546         struct pcmciabus_attach_args *paa = aux;
  547         struct tcic_handle *h = (struct tcic_handle *) paa->pch;
  549         switch (h->sock) {
  550         case 0:
  551                 if (cf->cf_loc[0 /* PCMCIABUSCF_CONTROLLER */] !=
  552                     -1 /* PCMCIABUSCF_CONTROLLER_DEFAULT */ &&
cf->cf_loc[0 /* PCMCIABUSCF_CONTROLLER */] != 0)
  554                         return 0;
  555                 if (cf->cf_loc[1 /* PCMCIABUSCF_SOCKET */] !=
  556                     -1 /* PCMCIABUSCF_SOCKET_DEFAULT */ &&
cf->cf_loc[1 /* PCMCIABUSCF_SOCKET */] != 0)
  558                         return 0;
  560                 break;
  561         case 1:
  562                 if (cf->cf_loc[0 /* PCMCIABUSCF_CONTROLLER */] !=
  563                     -1 /* PCMCIABUSCF_CONTROLLER_DEFAULT */ &&
cf->cf_loc[0 /* PCMCIABUSCF_CONTROLLER */] != 0)
  565                         return 0;
  566                 if (cf->cf_loc[1 /* PCMCIABUSCF_SOCKET */] !=
  567                     -1 /* PCMCIABUSCF_SOCKET_DEFAULT */ &&
cf->cf_loc[1 /* PCMCIABUSCF_SOCKET */] != 1)
  569                         return 0;
  571                 break;
  572         default:
panic("unknown tcic socket");
  574         }
  576         return ((*cf->cf_attach->ca_match)(parent, cf, aux));
  577 }
  579 int
tcic_print(arg, pnp)
  581         void *arg;
  582         const char *pnp;
  583 {
  584         struct pcmciabus_attach_args *paa = arg;
  585         struct tcic_handle *h = (struct tcic_handle *) paa->pch;
  587         /* Only "pcmcia"s can attach to "tcic"s... easy. */
  588         if (pnp)
printf("pcmcia at %s", pnp);
  591         switch (h->sock) {
  592         case 0:
printf(" socket 0");
  594                 break;
  595         case 1:
printf(" socket 1");
  597                 break;
  598         default:
panic("unknown tcic socket");
  600         }
  601         return (UNCONF);
  602 }
  604 int
tcic_intr(arg)
  606         void *arg;
  607 {
  608         struct tcic_softc *sc = arg;
  609         int i, ret = 0;
DPRINTF(("%s: intr\n", sc->dev.dv_xname));
  613         for (i = 0; i < TCIC_NSLOTS; i++)
  614                 if (sc->handle[i].flags & TCIC_FLAG_SOCKETP)
ret += tcic_intr_socket(&sc->handle[i]);
  617         return (ret ? 1 : 0);
  618 }
  620 int
tcic_intr_socket(h)
  622         struct tcic_handle *h;
  623 {
  624         int icsr, rv;
rv = 0;
tcic_sel_sock(h);
icsr = tcic_read_1(h, TCIC_R_ICSR);
DPRINTF(("%s: %d icsr: 0x%02x \n", h->sc->dev.dv_xname, h->sock, icsr));
  632         /* XXX or should the next three be handled in tcic_intr? -chb */
  633         if (icsr & TCIC_ICSR_PROGTIME) {
DPRINTF(("%s: %02x PROGTIME\n", h->sc->dev.dv_xname, h->sock));
rv = 1;
  636         }
  637         if (icsr & TCIC_ICSR_ILOCK) {
DPRINTF(("%s: %02x ILOCK\n", h->sc->dev.dv_xname, h->sock));
rv = 1;
  640         }
  641         if (icsr & TCIC_ICSR_ERR) {
DPRINTF(("%s: %02x ERR\n", h->sc->dev.dv_xname, h->sock));
rv = 1;
  644         }
  645         if (icsr & TCIC_ICSR_CDCHG) {
  646                 int sstat, delta;
  648                 /* compute what changed since last interrupt */
sstat = tcic_read_aux_1(h->sc->iot, h->sc->ioh,
TCIC_AR_WCTL, TCIC_R_WCTL_XCSR) & TCIC_XCSR_STAT_MASK;
delta = h->sstat ^ sstat;
h->sstat = sstat;
  654                 if (delta)
rv = 1;
DPRINTF(("%s: %02x CDCHG %x\n", h->sc->dev.dv_xname, h->sock,
delta));
  660                 /*
  661                  * XXX This should probably schedule something to happen
  662                  * after the interrupt handler completes
  663                  */
  665                 if (delta & TCIC_SSTAT_CD) {
  666                         if (sstat & TCIC_SSTAT_CD) {
  667                                 if (!(h->flags & TCIC_FLAG_CARDP)) {
DPRINTF(("%s: enqueing INSERTION event\n",
h->sc->dev.dv_xname));
tcic_queue_event(h, TCIC_EVENT_INSERTION);
  671                                 }
  672                         } else {
  673                                 if (h->flags & TCIC_FLAG_CARDP) {
  674                                         /* Deactivate the card now. */
DPRINTF(("%s: deactivating card\n",
h->sc->dev.dv_xname));
tcic_deactivate_card(h);
DPRINTF(("%s: enqueing REMOVAL event\n",
h->sc->dev.dv_xname));
tcic_queue_event(h, TCIC_EVENT_REMOVAL);
  682                                 }
  683                         }
  684                 }
  685                 if (delta & TCIC_SSTAT_RDY) {
DPRINTF(("%s: %02x READY\n", h->sc->dev.dv_xname, h->sock));
  687                         /* shouldn't happen */
  688                 }
  689                 if (delta & TCIC_SSTAT_LBAT1) {
DPRINTF(("%s: %02x LBAT1\n", h->sc->dev.dv_xname, h->sock));
  691                 }
  692                 if (delta & TCIC_SSTAT_LBAT2) {
DPRINTF(("%s: %02x LBAT2\n", h->sc->dev.dv_xname, h->sock));
  694                 }
  695                 if (delta & TCIC_SSTAT_WP) {
DPRINTF(("%s: %02x WP\n", h->sc->dev.dv_xname, h->sock));
  697                 }
  698         }
  699         return rv;
  700 }
  702 void
tcic_queue_event(h, event)
  704         struct tcic_handle *h;
  705         int event;
  706 {
  707         struct tcic_event *pe;
  708         int s;
pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT);
  711         if (pe == NULL)
panic("tcic_queue_event: can't allocate event");
pe->pe_type = event;
s = splhigh();
SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q);
splx(s);
wakeup(&h->events);
  719 }
  720 void
tcic_attach_card(h)
  722         struct tcic_handle *h;
  723 {
DPRINTF(("tcic_attach_card\n"));
  726         if (h->flags & TCIC_FLAG_CARDP)
panic("tcic_attach_card: already attached");
  729         /* call the MI attach function */
pcmcia_card_attach(h->pcmcia);
h->flags |= TCIC_FLAG_CARDP;
  734 }
  736 void
tcic_detach_card(h, flags)
  738         struct tcic_handle *h;
  739         int flags;              /* DETACH_* */
  740 {
DPRINTF(("tcic_detach_card\n"));
  743         if (!(h->flags & TCIC_FLAG_CARDP))
panic("tcic_detach_card: already detached");
h->flags &= ~TCIC_FLAG_CARDP;
  748         /* call the MI detach function */
pcmcia_card_detach(h->pcmcia, flags);
  752 }
  754 void
tcic_deactivate_card(h)
  756         struct tcic_handle *h;
  757 {
  758         int val, reg;
  760         if (!(h->flags & TCIC_FLAG_CARDP))
panic("tcic_deactivate_card: already detached");
  763         /* call the MI deactivate function */
pcmcia_card_deactivate(h->pcmcia);
tcic_sel_sock(h);
  768         /* XXX disable card detect resume and configuration reset??? */
  770         /* power down the socket */
tcic_write_1(h, TCIC_R_PWR, 0);
  773         /* reset the card XXX ? -chb */
  775         /* turn off irq's for this socket */
reg = TCIC_IR_SCF1_N(h->sock);
val = tcic_read_ind_2(h, reg);
tcic_write_ind_2(h, reg, (val & ~TCIC_SCF1_IRQ_MASK)|TCIC_SCF1_IRQOFF);
reg = TCIC_IR_SCF2_N(h->sock);
val = tcic_read_ind_2(h, reg);
tcic_write_ind_2(h, reg,
  782             (val | (TCIC_SCF2_MLBAT1|TCIC_SCF2_MLBAT2|TCIC_SCF2_MRDY
  783                 |TCIC_SCF2_MWP|TCIC_SCF2_MCD)));
  784 }
  786 /* XXX the following routine may need to be rewritten. -chb */
  787 int 
tcic_chip_mem_alloc(pch, size, pcmhp)
pcmcia_chipset_handle_t pch;
bus_size_t size;
  791         struct pcmcia_mem_handle *pcmhp;
  792 {
  793         struct tcic_handle *h = (struct tcic_handle *) pch;
bus_space_handle_t memh;
bus_addr_t addr;
bus_size_t sizepg;
  797         int i, mask, mhandle;
  799         /* out of sc->memh, allocate as many pages as necessary */
  801         /*
  802          * The TCIC can map memory only in sizes that are
  803          * powers of two, aligned at the natural boundary for the size.
  804          */
i = tcic_log2((u_int)size);
  806         if ((1<<i) < size)
i++;
sizepg = max(i, TCIC_MEM_SHIFT) - (TCIC_MEM_SHIFT-1);
DPRINTF(("tcic_chip_mem_alloc: size %ld sizepg %ld\n", size, sizepg));
  812         /* can't allocate that much anyway */
  813         if (sizepg > TCIC_MEM_PAGES)    /* XXX -chb */
  814                 return 1;
mask = (1 << sizepg) - 1;
addr = 0;               /* XXX gcc -Wuninitialized */
mhandle = 0;            /* XXX gcc -Wuninitialized */
  821         /* XXX i should be initialised to always lay on boundary. -chb */
  822         for (i = 0; i < (TCIC_MEM_PAGES + 1 - sizepg); i += sizepg) {
  823                 if ((h->sc->subregionmask & (mask << i)) == (mask << i)) {
  824                         if (bus_space_subregion(h->sc->memt, h->sc->memh,
i * TCIC_MEM_PAGESIZE,
sizepg * TCIC_MEM_PAGESIZE, &memh))
  827                                 return (1);
mhandle = mask << i;
addr = h->sc->membase + (i * TCIC_MEM_PAGESIZE);
h->sc->subregionmask &= ~(mhandle);
  831                         break;
  832                 }
  833         }
  835         if (i == (TCIC_MEM_PAGES + 1 - sizepg))
  836                 return (1);
DPRINTF(("tcic_chip_mem_alloc bus addr 0x%lx+0x%lx\n", (u_long) addr,
  839                  (u_long) size));
pcmhp->memt = h->sc->memt;
pcmhp->memh = memh;
pcmhp->addr = addr;
pcmhp->size = size;
pcmhp->mhandle = mhandle;
pcmhp->realsize = sizepg * TCIC_MEM_PAGESIZE;
  848         return (0);
  849 }
  851 /* XXX the following routine may need to be rewritten. -chb */
  852 void 
tcic_chip_mem_free(pch, pcmhp)
pcmcia_chipset_handle_t pch;
  855         struct pcmcia_mem_handle *pcmhp;
  856 {
  857         struct tcic_handle *h = (struct tcic_handle *) pch;
h->sc->subregionmask |= pcmhp->mhandle;
  860 }
  862 void 
tcic_chip_do_mem_map(h, win)
  864         struct tcic_handle *h;
  865         int win;
  866 {
  867         int reg, hwwin, wscnt;
  869         int kind = h->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK;
  870         int mem8 = (h->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8;
DPRINTF(("tcic_chip_do_mem_map window %d: 0x%lx+0x%lx 0x%lx\n",
win, (u_long)h->mem[win].addr, (u_long)h->mem[win].size,
  873                 (u_long)h->mem[win].offset));
  874         /*
  875          * the even windows are used for socket 0,
  876          * the odd ones for socket 1.
  877          */
hwwin = (win << 1) + h->sock;
  880         /* the WR_MEXT register is MBZ */
tcic_write_ind_2(h, TCIC_WR_MEXT_N(hwwin), 0);
  883         /* set the host base address and window size */
  884         if (h->mem[win].size2 <= 1) {
reg = ((h->mem[win].addr >> TCIC_MEM_SHIFT) &
TCIC_MBASE_ADDR_MASK) | TCIC_MBASE_4K;
  887         } else {
reg = ((h->mem[win].addr >> TCIC_MEM_SHIFT) &
TCIC_MBASE_ADDR_MASK) | (h->mem[win].size2 >> 1);
  890         }
tcic_write_ind_2(h, TCIC_WR_MBASE_N(hwwin), reg);
  893         /* set the card address and address space */
reg = 0;
reg = ((h->mem[win].offset >> TCIC_MEM_SHIFT) & TCIC_MMAP_ADDR_MASK);
reg |= (kind == PCMCIA_MEM_ATTR) ? TCIC_MMAP_ATTR : 0;
DPRINTF(("tcic_chip_do_map_mem window %d(%d) mmap 0x%04x\n",
win, hwwin, reg));
tcic_write_ind_2(h, TCIC_WR_MMAP_N(hwwin), reg);
  901         /* set the MCTL register */
  902         /* must save WSCNT field in case this is a DB86082 rev 0 */
  903         /* XXX why can't I do the following two in one statement? */
reg = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin)) & TCIC_MCTL_WSCNT_MASK;
reg |= TCIC_MCTL_ENA|TCIC_MCTL_QUIET;
reg |= mem8 ? TCIC_MCTL_B8 : 0;
reg |= (h->sock << TCIC_MCTL_SS_SHIFT) & TCIC_MCTL_SS_MASK;
  908 #ifdef notyet   /* XXX must get speed from CIS somehow. -chb */
wscnt = tcic_ns2wscnt(h->mem[win].speed);
  910 #else
wscnt = tcic_ns2wscnt(tcic_mem_speed);  /*  300 is "save" default for CIS memory */
  912 #endif
  913         if (h->sc->chipid == TCIC_CHIPID_DB86082_1) {
  914                 /*
  915                  * this chip has the wait state count in window
  916                  * register 7 - hwwin.
  917                  */
  918                 int reg2;
reg2 = tcic_read_ind_2(h, TCIC_WR_MCTL_N(7-hwwin));
reg2 &= ~TCIC_MCTL_WSCNT_MASK;
reg2 |= wscnt & TCIC_MCTL_WSCNT_MASK;
tcic_write_ind_2(h, TCIC_WR_MCTL_N(7-hwwin), reg2);
  923         } else {
reg |= wscnt & TCIC_MCTL_WSCNT_MASK;
  925         }
tcic_write_ind_2(h, TCIC_WR_MCTL_N(hwwin), reg);
  928 #ifdef TCICDEBUG
  929         {
  930                 int r1, r2, r3;
r1 = tcic_read_ind_2(h, TCIC_WR_MBASE_N(hwwin));
r2 = tcic_read_ind_2(h, TCIC_WR_MMAP_N(hwwin));
r3 = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin));
DPRINTF(("tcic_chip_do_mem_map window %d(%d): %04x %04x %04x\n",
win, hwwin, r1, r2, r3));
  938         }
  939 #endif
  940 }
  942 /* XXX needs work */
  943 int 
tcic_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp)
pcmcia_chipset_handle_t pch;
  946         int kind;
bus_addr_t card_addr;
bus_size_t size;
  949         struct pcmcia_mem_handle *pcmhp;
bus_size_t *offsetp;
  951         int *windowp;
  952 {
  953         struct tcic_handle *h = (struct tcic_handle *) pch;
bus_addr_t busaddr;
  955         long card_offset;
  956         int i, win;
win = -1;
  959         for (i = 0; i < h->memwins; i++) {
  960                 if ((h->memalloc & (1 << i)) == 0) {
win = i;
h->memalloc |= (1 << i);
  963                         break;
  964                 }
  965         }
  967         if (win == -1)
  968                 return (1);
  970         *windowp = win;
  972         /* XXX this is pretty gross */
  974         if (h->sc->memt != pcmhp->memt)
panic("tcic_chip_mem_map memt is bogus");
busaddr = pcmhp->addr;
  979         /*
  980          * compute the address offset to the pcmcia address space for the
  981          * tcic.  this is intentionally signed.  The masks and shifts below
  982          * will cause TRT to happen in the tcic registers.  Deal with making
  983          * sure the address is aligned, and return the alignment offset.
  984          */
  986         *offsetp = card_addr % TCIC_MEM_ALIGN;
card_addr -= *offsetp;
DPRINTF(("tcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr "
  990             "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size,
  991             (u_long) card_addr));
  993         /* XXX we can't use size. -chb */
  994         /*
  995          * include the offset in the size, and decrement size by one, since
  996          * the hw wants start/stop
  997          */
size += *offsetp - 1;
card_offset = (((long) card_addr) - ((long) busaddr));
DPRINTF(("tcic_chip_mem_map window %d card_offset 0x%lx\n",
win, (u_long)card_offset));
h->mem[win].addr = busaddr;
h->mem[win].size = size;
h->mem[win].size2 = tcic_log2((u_int)pcmhp->realsize) - TCIC_MEM_SHIFT;
h->mem[win].offset = card_offset;
h->mem[win].kind = kind;
tcic_chip_do_mem_map(h, win);
 1013         return (0);
 1014 }
 1016 void 
tcic_chip_mem_unmap(pch, window)
pcmcia_chipset_handle_t pch;
 1019         int window;
 1020 {
 1021         struct tcic_handle *h = (struct tcic_handle *) pch;
 1022         int reg, hwwin;
 1024         if (window >= h->memwins)
panic("tcic_chip_mem_unmap: window out of range");
hwwin = (window << 1) + h->sock;
reg = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin));
reg &= ~TCIC_MCTL_ENA;
tcic_write_ind_2(h, TCIC_WR_MCTL_N(hwwin), reg);
h->memalloc &= ~(1 << window);
 1033 }
 1035 int 
tcic_chip_io_alloc(pch, start, size, align, pcihp)
pcmcia_chipset_handle_t pch;
bus_addr_t start;
bus_size_t size;
bus_size_t align;
 1041         struct pcmcia_io_handle *pcihp;
 1042 {
 1043         struct tcic_handle *h = (struct tcic_handle *) pch;
bus_space_tag_t iot;
bus_space_handle_t ioh;
bus_addr_t ioaddr;
 1047         int size2, flags = 0;
 1049         /*
 1050          * Allocate some arbitrary I/O space.
 1051          */
DPRINTF(("tcic_chip_io_alloc req 0x%lx %ld %ld\n",
 1054             (u_long) start, (u_long) size, (u_long) align));
 1055         /*
 1056          * The TCIC can map I/O space only in sizes that are
 1057          * powers of two, aligned at the natural boundary for the size.
 1058          */
size2 = tcic_log2((u_int)size);
 1060         if ((1 << size2) < size)
size2++;
 1062         /* can't allocate that much anyway */
 1063         if (size2 > 16) /* XXX 64K -chb */
 1064                 return 1;
 1065         if (align) {
 1066                 if ((1 << size2) != align)
 1067                         return 1;       /* not suitably  aligned */
 1068         } else {
align = 1 << size2;     /* no alignment given, make it natural */
 1070         }
 1071         if (start & (align - 1))
 1072                 return 1;       /* not suitably aligned */
iot = h->sc->iot;
 1076         if (start) {
ioaddr = start;
 1078                 if (bus_space_map(iot, start, size, 0, &ioh))
 1079                         return (1);
DPRINTF(("tcic_chip_io_alloc map port %lx+%lx\n",
 1081                     (u_long) ioaddr, (u_long) size));
 1082         } else {
flags |= PCMCIA_IO_ALLOCATED;
 1084                 if (bus_space_alloc(iot, h->sc->iobase,
h->sc->iobase + h->sc->iosize, size, align, 0, 0,
 1086                     &ioaddr, &ioh))
 1087                         return (1);
DPRINTF(("tcic_chip_io_alloc alloc port %lx+%lx\n",
 1089                     (u_long) ioaddr, (u_long) size));
 1090         }
pcihp->iot = iot;
pcihp->ioh = ioh;
pcihp->addr = ioaddr;
pcihp->size = size;
pcihp->flags = flags;
 1098         return (0);
 1099 }
 1101 void 
tcic_chip_io_free(pch, pcihp)
pcmcia_chipset_handle_t pch;
 1104         struct pcmcia_io_handle *pcihp;
 1105 {
bus_space_tag_t iot = pcihp->iot;
bus_space_handle_t ioh = pcihp->ioh;
bus_size_t size = pcihp->size;
 1110         if (pcihp->flags & PCMCIA_IO_ALLOCATED)
bus_space_free(iot, ioh, size);
 1112         else
bus_space_unmap(iot, ioh, size);
 1114 }
 1116 static int tcic_iowidth_map[] =
 1117     { TCIC_ICTL_AUTOSZ, TCIC_ICTL_B8, TCIC_ICTL_B16 };
 1119 void 
tcic_chip_do_io_map(h, win)
 1121         struct tcic_handle *h;
 1122         int win;
 1123 {
 1124         int reg, size2, iotiny, wbase, hwwin, wscnt;
DPRINTF(("tcic_chip_do_io_map win %d addr %lx size %lx width %d\n",
win, (long) h->io[win].addr, (long) h->io[win].size,
h->io[win].width * 8));
 1130         /*
 1131          * the even windows are used for socket 0,
 1132          * the odd ones for socket 1.
 1133          */
hwwin = (win << 1) + h->sock;
 1136         /* set the WR_BASE register */
 1137         /* XXX what if size isn't power of 2? -chb */
size2 = tcic_log2((u_int)h->io[win].size);
DPRINTF(("tcic_chip_do_io_map win %d size2 %d\n", win, size2));
 1140         if (size2 < 1) {
iotiny = TCIC_ICTL_TINY;
wbase = h->io[win].addr;
 1143         } else {
iotiny = 0;
 1145                 /* XXX we should do better -chb */
wbase = h->io[win].addr | (1 << (size2 - 1));
 1147         }
tcic_write_ind_2(h, TCIC_WR_IBASE_N(hwwin), wbase);
 1150         /* set the WR_ICTL register */
reg = TCIC_ICTL_ENA | TCIC_ICTL_QUIET;
reg |= (h->sock << TCIC_ICTL_SS_SHIFT) & TCIC_ICTL_SS_MASK;
reg |= iotiny | tcic_iowidth_map[h->io[win].width];
 1154         if (h->sc->chipid != TCIC_CHIPID_DB86082_1)
reg |= TCIC_ICTL_PASS16;
 1156 #ifdef notyet   /* XXX must get speed from CIS somehow. -chb */
wscnt = tcic_ns2wscnt(h->io[win].speed);
 1158 #else
wscnt = tcic_ns2wscnt(tcic_io_speed);   /* linux uses 0 as default */
 1160 #endif
reg |= wscnt & TCIC_ICTL_WSCNT_MASK;
tcic_write_ind_2(h, TCIC_WR_ICTL_N(hwwin), reg);
 1164 #ifdef TCICDEBUG
 1165         {
 1166                 int r1, r2;
r1 = tcic_read_ind_2(h, TCIC_WR_IBASE_N(hwwin));
r2 = tcic_read_ind_2(h, TCIC_WR_ICTL_N(hwwin));
DPRINTF(("tcic_chip_do_io_map window %d(%d): %04x %04x\n",
win, hwwin, r1, r2));
 1173         }
 1174 #endif
 1175 }
 1177 int 
tcic_chip_io_map(pch, width, offset, size, pcihp, windowp)
pcmcia_chipset_handle_t pch;
 1180         int width;
bus_addr_t offset;
bus_size_t size;
 1183         struct pcmcia_io_handle *pcihp;
 1184         int *windowp;
 1185 {
 1186         struct tcic_handle *h = (struct tcic_handle *) pch;
bus_addr_t ioaddr = pcihp->addr + offset;
 1188         int i, win;
 1189 #ifdef TCICDEBUG
 1190         static char *width_names[] = { "auto", "io8", "io16" };
 1191 #endif
 1193         /* XXX Sanity check offset/size. */
win = -1;
 1196         for (i = 0; i < TCIC_IO_WINS; i++) {
 1197                 if ((h->ioalloc & (1 << i)) == 0) {
win = i;
h->ioalloc |= (1 << i);
 1200                         break;
 1201                 }
 1202         }
 1204         if (win == -1)
 1205                 return (1);
 1207         *windowp = win;
 1209         /* XXX this is pretty gross */
 1211         if (h->sc->iot != pcihp->iot)
panic("tcic_chip_io_map iot is bogus");
DPRINTF(("tcic_chip_io_map window %d %s port %lx+%lx\n",
win, width_names[width], (u_long) ioaddr, (u_long) size));
 1217         /* XXX wtf is this doing here? */
printf(" port 0x%lx", (u_long) ioaddr);
 1220         if (size > 1)
printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1);
h->io[win].addr = ioaddr;
h->io[win].size = size;
h->io[win].width = width;
tcic_chip_do_io_map(h, win);
 1229         return (0);
 1230 }
 1232 void 
tcic_chip_io_unmap(pch, window)
pcmcia_chipset_handle_t pch;
 1235         int window;
 1236 {
 1237         struct tcic_handle *h = (struct tcic_handle *) pch;
 1238         int reg, hwwin;
 1240         if (window >= TCIC_IO_WINS)
panic("tcic_chip_io_unmap: window out of range");
hwwin = (window << 1) + h->sock;
reg = tcic_read_ind_2(h, TCIC_WR_ICTL_N(hwwin));
reg &= ~TCIC_ICTL_ENA;
tcic_write_ind_2(h, TCIC_WR_ICTL_N(hwwin), reg);
h->ioalloc &= ~(1 << window);
 1249 }
 1251 void
tcic_chip_socket_enable(pch)
pcmcia_chipset_handle_t pch;
 1254 {
 1255         struct tcic_handle *h = (struct tcic_handle *) pch;
 1256         int cardtype, reg, win;
tcic_sel_sock(h);
 1260         /*
 1261          * power down the socket to reset it.
 1262          * put card reset into high-z, put chip outputs to card into high-z
 1263          */
tcic_write_1(h, TCIC_R_PWR, 0);
reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK);
reg |= TCIC_ILOCK_CWAIT;
reg &= ~(TCIC_ILOCK_CRESET|TCIC_ILOCK_CRESENA);
tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg);
tcic_write_1(h, TCIC_R_SCTRL, 0);       /* clear TCIC_SCTRL_ENA */
 1272         /* power up the socket */
 1274         /* turn on VCC, turn of VPP */
reg = TCIC_PWR_VCC_N(h->sock) | TCIC_PWR_VPP_N(h->sock) | h->sc->pwrena;
 1276         if (h->sc->pwrena)              /* this is a '84 type chip */
reg |= TCIC_PWR_VCC5V;
tcic_write_1(h, TCIC_R_PWR, reg);
delay(10000);
 1281         /* enable reset and wiggle it to reset the card */
reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK);
reg |= TCIC_ILOCK_CRESENA;
tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg);
 1285         /* XXX need bus_space_barrier here */
reg |= TCIC_ILOCK_CRESET;
tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg);
 1288         /* enable card signals */
tcic_write_1(h, TCIC_R_SCTRL, TCIC_SCTRL_ENA);
delay(10);      /* wait 10 us */
 1292         /* clear the reset flag */
reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK);
reg &= ~(TCIC_ILOCK_CRESET);
tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg);
 1297         /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */
delay(20000);
 1300         /* wait for the chip to finish initializing */
tcic_wait_ready(h);
 1303         /* WWW */
 1304         /* zero out the address windows */
 1306         /* writing to WR_MBASE_N disables the window */
 1307         for (win = 0; win < h->memwins; win++) {
tcic_write_ind_2(h, TCIC_WR_MBASE_N((win<<1)+h->sock), 0);
 1309         }
 1310         /* writing to WR_IBASE_N disables the window */
 1311         for (win = 0; win < TCIC_IO_WINS; win++) {
tcic_write_ind_2(h, TCIC_WR_IBASE_N((win<<1)+h->sock), 0);
 1313         }
 1315         /* set the card type */
cardtype = pcmcia_card_gettype(h->pcmcia);
 1319 #if 0
reg = tcic_read_ind_2(h, TCIC_IR_SCF1_N(h->sock));
reg &= ~TCIC_SCF1_IRQ_MASK;
 1322 #else
reg = 0;
 1324 #endif
reg |= ((cardtype == PCMCIA_IFTYPE_IO) ?
TCIC_SCF1_IOSTS : 0);
reg |= tcic_irqmap[h->ih_irq];          /* enable interrupts */
reg &= ~TCIC_SCF1_IRQOD;
tcic_write_ind_2(h, TCIC_IR_SCF1_N(h->sock), reg);
DPRINTF(("%s: tcic_chip_socket_enable %d cardtype %s 0x%02x\n",
h->sc->dev.dv_xname, h->sock,
 1333             ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg));
 1335         /* reinstall all the memory and io mappings */
 1337         for (win = 0; win < h->memwins; win++)
 1338                 if (h->memalloc & (1 << win))
tcic_chip_do_mem_map(h, win);
 1341         for (win = 0; win < TCIC_IO_WINS; win++)
 1342                 if (h->ioalloc & (1 << win))
tcic_chip_do_io_map(h, win);
 1344 }
 1346 void
tcic_chip_socket_disable(pch)
pcmcia_chipset_handle_t pch;
 1349 {
 1350         struct tcic_handle *h = (struct tcic_handle *) pch;
 1351         int val;
DPRINTF(("tcic_chip_socket_disable\n"));
tcic_sel_sock(h);
 1357         /* disable interrupts */
val = tcic_read_ind_2(h, TCIC_IR_SCF1_N(h->sock));
val &= TCIC_SCF1_IRQ_MASK;
tcic_write_ind_2(h, TCIC_IR_SCF1_N(h->sock), val);
 1362         /* disable the output signals */
tcic_write_1(h, TCIC_R_SCTRL, 0);
val = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK);
val &= ~TCIC_ILOCK_CRESENA;
tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, val);
 1368         /* power down the socket */
tcic_write_1(h, TCIC_R_PWR, 0);
 1370 }
 1372 /*
 1373  * XXX The following is Linux driver but doesn't match the table
 1374  * in the manual.
 1375  */
 1376 int
tcic_ns2wscnt(ns)
 1378         int ns;
 1379 {
 1380         if (ns < 14) {
 1381                 return 0;
 1382         } else {
 1383                 return (2*(ns-14))/70;  /* XXX assumes 14.31818 MHz clock. */
 1384         }
 1385 }
 1387 int
tcic_log2(val)
u_int val;
 1390 {
 1391         int i, l2;
l2 = i = 0;
 1394         while (val) {
 1395                 if (val & 1)
l2 = i;
i++;
val >>= 1;
 1399         }
 1400         return l2;
 1401 }