val1              943 dev/ic/if_wi.c wi_cmd_io(struct wi_softc *sc, int cmd, int val0, int val1, int val2)
val1              960 dev/ic/if_wi.c 	CSR_WRITE_2(sc, WI_PARAM1, val1);
val1              148 dev/ic/if_wivar.h 	int (*f_cmd)(struct wi_softc *sc, int cmd, int val0, int val1,
val1              186 dev/ic/tcic2.c 		int val1, val2;
val1              200 dev/ic/tcic2.c 			val1 = bus_space_read_2(iot, ioh, TCIC_R_EDC);
val1              202 dev/ic/tcic2.c 			if (val1 | val2) {
val1              203 dev/ic/tcic2.c 				val1 = bus_space_read_2(iot, ioh, TCIC_R_EDC);
val1              204 dev/ic/tcic2.c 				if (val1 == val2)
val1              211 dev/ic/tcic2.c 		val1 = omode ^ TCIC_AR_MASK;
val1              212 dev/ic/tcic2.c 		bus_space_write_1(iot, ioh, TCIC_R_MODE, val1);
val1              215 dev/ic/tcic2.c 		if ( val1 != val2)
val1             1162 dev/pci/if_bnx.c 	u_int32_t		val1;
val1             1177 dev/pci/if_bnx.c 		val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE);
val1             1178 dev/pci/if_bnx.c 		val1 &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL;
val1             1180 dev/pci/if_bnx.c 		REG_WR(sc, BNX_EMAC_MDIO_MODE, val1);
val1             1186 dev/pci/if_bnx.c 	val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val |
val1             1189 dev/pci/if_bnx.c 	REG_WR(sc, BNX_EMAC_MDIO_COMM, val1);
val1             1194 dev/pci/if_bnx.c 		val1 = REG_RD(sc, BNX_EMAC_MDIO_COMM);
val1             1195 dev/pci/if_bnx.c 		if (!(val1 & BNX_EMAC_MDIO_COMM_START_BUSY)) {
val1             1201 dev/pci/if_bnx.c 	if (val1 & BNX_EMAC_MDIO_COMM_START_BUSY) {
val1             1207 dev/pci/if_bnx.c 		val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE);
val1             1208 dev/pci/if_bnx.c 		val1 |= BNX_EMAC_MDIO_MODE_AUTO_POLL;
val1             1210 dev/pci/if_bnx.c 		REG_WR(sc, BNX_EMAC_MDIO_MODE, val1);
val1             5761 dev/pci/if_bnx.c 	u_int32_t		val1;
val1             5771 dev/pci/if_bnx.c 	val1 = REG_RD(sc, BNX_MISC_ENABLE_STATUS_BITS);
val1             5773 dev/pci/if_bnx.c 	    val1, BNX_MISC_ENABLE_STATUS_BITS);
val1             5775 dev/pci/if_bnx.c 	val1 = REG_RD(sc, BNX_DMA_STATUS);
val1             5776 dev/pci/if_bnx.c 	BNX_PRINTF(sc, "0x%08X : (0x%04X) dma_status\n", val1, BNX_DMA_STATUS);
val1             5778 dev/pci/if_bnx.c 	val1 = REG_RD(sc, BNX_CTX_STATUS);
val1             5779 dev/pci/if_bnx.c 	BNX_PRINTF(sc, "0x%08X : (0x%04X) ctx_status\n", val1, BNX_CTX_STATUS);
val1             5781 dev/pci/if_bnx.c 	val1 = REG_RD(sc, BNX_EMAC_STATUS);
val1             5782 dev/pci/if_bnx.c 	BNX_PRINTF(sc, "0x%08X : (0x%04X) emac_status\n", val1,
val1             5785 dev/pci/if_bnx.c 	val1 = REG_RD(sc, BNX_RPM_STATUS);
val1             5786 dev/pci/if_bnx.c 	BNX_PRINTF(sc, "0x%08X : (0x%04X) rpm_status\n", val1, BNX_RPM_STATUS);
val1             5788 dev/pci/if_bnx.c 	val1 = REG_RD(sc, BNX_TBDR_STATUS);
val1             5789 dev/pci/if_bnx.c 	BNX_PRINTF(sc, "0x%08X : (0x%04X) tbdr_status\n", val1,
val1             5792 dev/pci/if_bnx.c 	val1 = REG_RD(sc, BNX_TDMA_STATUS);
val1             5793 dev/pci/if_bnx.c 	BNX_PRINTF(sc, "0x%08X : (0x%04X) tdma_status\n", val1,
val1             5796 dev/pci/if_bnx.c 	val1 = REG_RD(sc, BNX_HC_STATUS);
val1             5797 dev/pci/if_bnx.c 	BNX_PRINTF(sc, "0x%08X : (0x%04X) hc_status\n", val1, BNX_HC_STATUS);
val1              746 dev/pci/isp_pci.c 	u_int16_t val0, val1;
val1              751 dev/pci/isp_pci.c 		val1 = BXR2(pcs, IspVirt2Off(isp, off));
val1              752 dev/pci/isp_pci.c 	} while (val0 != val1 && ++i < 1000);
val1              753 dev/pci/isp_pci.c 	if (val0 != val1) {
val1              576 dev/usb/if_wi_usb.c wi_cmd_usb(struct wi_softc *wsc, int cmd, int val0, int val1, int val2)
val1              585 dev/usb/if_wi_usb.c 	    sc->wi_usb_dev.dv_xname, __func__, cmd, val0, val1, val2));
val1              632 dev/usb/if_wi_usb.c 	pcmd->param1  = htole16(val1);
val1              147 dev/usb/if_wi_usb.h int wi_cmd_usb(struct wi_softc *sc, int cmd, int val0, int val1, int val2);