root/dev/pci/tga.c

DEFINITIONS

1. tgamatch
2. tga_getdevconfig
3. tgaattach
4. tga_config_interrupts
5. tga_ioctl
6. tga_sched_update
7. tga_intr
8. tga_mmap
9. tga_alloc_screen
10. tga_free_screen
11. tga_show_screen
12. tga_cnattach
13. tga_burner
14. tga_blank
15. tga_unblank
16. tga_builtin_set_cursor
17. tga_builtin_get_cursor
18. tga_builtin_set_curpos
19. tga_builtin_get_curpos
20. tga_builtin_get_curmax
21. tga_copycols
22. tga_copyrows
23. tga_rop
24. tga_rop_vtov
25. tga_putchar
26. tga_eraserows
27. tga_erasecols
28. tga_ramdac_wr
29. tga2_ramdac_wr
30. tga_bt463_rd
31. tga_bt463_wr
32. tga_ramdac_rd
33. tga2_ramdac_rd
34. tga2_init
35. tga2_ics9110_wr
36. tga_getmonitor
37. tga_getdotclock

    1 /* $OpenBSD: tga.c,v 1.29 2006/12/17 22:18:16 miod Exp $ */
    2 /* $NetBSD: tga.c,v 1.40 2002/03/13 15:05:18 ad Exp $ */
    4 /*
    5  * Copyright (c) 1995, 1996 Carnegie-Mellon University.
    6  * All rights reserved.
    7  *
    8  * Author: Chris G. Demetriou
    9  * 
   10  * Permission to use, copy, modify and distribute this software and
   11  * its documentation is hereby granted, provided that both the copyright
   12  * notice and this permission notice appear in all copies of the
   13  * software, derivative works or modified versions, and any portions
   14  * thereof, and that both notices appear in supporting documentation.
   15  * 
   16  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 
   17  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 
   18  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
   19  * 
   20  * Carnegie Mellon requests users of this software to return to
   21  *
   22  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
   23  *  School of Computer Science
   24  *  Carnegie Mellon University
   25  *  Pittsburgh PA 15213-3890
   26  *
   27  * any improvements or extensions that they make and grant Carnegie the
   28  * rights to redistribute these changes.
   29  */
   31 #include <sys/param.h>
   32 #include <sys/systm.h>
   33 #include <sys/kernel.h>
   34 #include <sys/device.h>
   35 #include <sys/conf.h>
   36 #include <sys/malloc.h>
   37 #include <sys/buf.h>
   38 #include <sys/ioctl.h>
   40 #include <machine/bus.h>
   41 #include <machine/intr.h>
   43 #include <dev/pci/pcireg.h>
   44 #include <dev/pci/pcivar.h>
   45 #include <dev/pci/pcidevs.h>
   46 #include <dev/pci/tgareg.h>
   47 #include <dev/pci/tgavar.h>
   48 #include <dev/ic/bt485reg.h>
   49 #include <dev/ic/bt485var.h>
   50 #include <dev/ic/bt463reg.h>
   51 #include <dev/ic/bt463var.h>
   52 #include <dev/ic/ibm561var.h>
   54 #include <dev/wscons/wsconsio.h>
   55 #include <dev/rasops/rasops.h>
   56 #include <dev/wsfont/wsfont.h>
   58 #if defined(__alpha__) || defined(__mips__)
   59 #include <uvm/uvm_extern.h>
   60 #endif
   62 #ifdef __alpha__
   63 #include <machine/pte.h>
   64 #endif
   65 #ifdef __mips__
   66 #include <mips/pte.h>
   67 #endif
   69 int     tgamatch(struct device *, struct cfdata *, void *);
   70 void    tgaattach(struct device *, struct device *, void *);
   71 int     tgaprint(void *, const char *);
   73 struct cfdriver tga_cd = {
NULL, "tga", DV_DULL
   75 };
   77 struct cfattach tga_ca = {
   78         sizeof(struct tga_softc), (cfmatch_t)tgamatch, tgaattach,
   79 };
   81 int     tga_identify(struct tga_devconfig *);
   82 const struct tga_conf *tga_getconf(int);
   83 void    tga_getdevconfig(bus_space_tag_t memt, pci_chipset_tag_t pc,
pcitag_t tag, struct tga_devconfig *dc);
   85 unsigned tga_getdotclock(struct tga_devconfig *dc);
   87 struct tga_devconfig tga_console_dc;
   89 int     tga_ioctl(void *, u_long, caddr_t, int, struct proc *);
paddr_t tga_mmap(void *, off_t, int);
   91 void    tga_copyrows(void *, int, int, int);
   92 void    tga_copycols(void *, int, int, int, int);
   93 int     tga_alloc_screen(void *, const struct wsscreen_descr *,
   94             void **, int *, int *, long *);
   95 void    tga_free_screen(void *, void *);
   96 int     tga_show_screen(void *, void *, int,
   97                            void (*) (void *, int, int), void *);
   98 void    tga_burner(void *, u_int, u_int);
   99 int     tga_rop(struct rasops_info *, int, int, int, int,
  100         struct rasops_info *, int, int);
  101 int     tga_rop_vtov(struct rasops_info *, int, int, int,
  102         int, struct rasops_info *, int, int );
  103 void    tga_putchar(void *c, int row, int col, u_int uc, long attr);
  104 void    tga_eraserows(void *, int, int, long);
  105 void    tga_erasecols(void *, int, int, int, long);
  106 void    tga2_init(struct tga_devconfig *);
  108 void    tga_config_interrupts(struct device *);
  110 /* RAMDAC interface functions */
  111 int      tga_sched_update(void *, void (*)(void *));
  112 void     tga_ramdac_wr(void *, u_int, u_int8_t);
u_int8_t tga_ramdac_rd(void *, u_int);
  114 void     tga_bt463_wr(void *, u_int, u_int8_t);
u_int8_t tga_bt463_rd(void *, u_int);
  116 void     tga2_ramdac_wr(void *, u_int, u_int8_t);
u_int8_t tga2_ramdac_rd(void *, u_int);
  119 /* Interrupt handler */
  120 int     tga_intr(void *);
  122 /* The NULL entries will get filled in by rasops_init().
  123  * XXX and the non-NULL ones will be overwritten; reset after calling it.
  124  */
  125 struct wsdisplay_emulops tga_emulops = {
NULL,
NULL,
tga_putchar,
tga_copycols,
tga_erasecols,
tga_copyrows,
tga_eraserows,
NULL,
NULL
  135 };
  137 struct wsscreen_descr tga_stdscreen = {
  138         "std",
  139         0, 0,   /* will be filled in -- XXX shouldn't, it's global */
  140         &tga_emulops,
  141         0, 0,
WSSCREEN_UNDERLINE | WSSCREEN_HILIT |
WSSCREEN_WSCOLORS | WSSCREEN_REVERSE
  144 };
  146 const struct wsscreen_descr *_tga_scrlist[] = {
  147         &tga_stdscreen,
  148         /* XXX other formats, graphics screen? */
  149 };
  151 struct wsscreen_list tga_screenlist = {
  152         sizeof(_tga_scrlist) / sizeof(struct wsscreen_descr *), _tga_scrlist
  153 };
  155 struct wsdisplay_accessops tga_accessops = {
tga_ioctl,
tga_mmap,
tga_alloc_screen,
tga_free_screen,
tga_show_screen,
NULL,                   /* load_font */
NULL,                   /* scrollback */
NULL,                   /* getchar */
tga_burner,
  165 };
  167 void    tga_blank(struct tga_devconfig *);
  168 void    tga_unblank(struct tga_devconfig *);
  170 #ifdef TGA_DEBUG
  171 #define DPRINTF(...)      printf (__VA_ARGS__)
  172 #define DPRINTFN(n, ...)   if (tgadebug > (n)) printf (__VA_ARGS__)
  173 int tgadebug = 0;
  174 #else
  175 #define DPRINTF(...)
  176 #define DPRINTFN(n,...)
  177 #endif
  179 const struct pci_matchid tga_devices[] = {
  180         { PCI_VENDOR_DEC, PCI_PRODUCT_DEC_21030 },
  181         { PCI_VENDOR_DEC, PCI_PRODUCT_DEC_PBXGB },
  182 };
  184 int
tgamatch(parent, match, aux)
  186         struct device *parent;
  187         struct cfdata *match;
  188         void *aux;
  189 {
  190         if (pci_matchbyid((struct pci_attach_args *)aux, tga_devices,
  191             sizeof(tga_devices) / sizeof(tga_devices[0])))
  192                 return (10);    /* need to return more than vga_pci here! */
  194         return (0);
  195 }
  197 void
tga_getdevconfig(memt, pc, tag, dc)
bus_space_tag_t memt;
pci_chipset_tag_t pc;
pcitag_t tag;
  202         struct tga_devconfig *dc;
  203 {
  204         const struct tga_conf *tgac;
  205         struct rasops_info *rip;
  206         int cookie;
bus_size_t pcisize;
  208         int i;
dc->dc_memt = memt;
dc->dc_pcitag = tag;
DPRINTF("tga_getdevconfig: Getting map info\n");
  215         /* XXX magic number */
  216         if (pci_mapreg_info(pc, tag, 0x10,
PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT,
  218             &dc->dc_pcipaddr, &pcisize, NULL))
  219                 return;
DPRINTF("tga_getdevconfig: preparing to map\n");
  222 #ifdef __OpenBSD__
  223         if (bus_space_map(memt, dc->dc_pcipaddr, pcisize, 1, &dc->dc_memh))
  224                 return;
dc->dc_vaddr = dc->dc_memh;
  226 #else
  227         if (bus_space_map(memt, dc->dc_pcipaddr, pcisize,
BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR, &dc->dc_memh))
  229                 return;
dc->dc_vaddr = (vaddr_t) bus_space_vaddr(memt, dc->dc_memh);
  231 #endif
DPRINTF("tga_getdevconfig: mapped\n");
  234 #ifdef __alpha__
dc->dc_paddr = ALPHA_K0SEG_TO_PHYS(dc->dc_vaddr);       /* XXX */
  236 #endif
  237 #ifdef arc
bus_space_paddr(memt, dc->dc_memh, &dc->dc_paddr);
  239 #endif
DPRINTF("tga_getdevconfig: allocating subregion\n");
bus_space_subregion(dc->dc_memt, dc->dc_memh, 
TGA_MEM_CREGS, TGA_CREGS_SIZE,
  243                             &dc->dc_regs);
DPRINTF("tga_getdevconfig: going to identify\n");
dc->dc_tga_type = tga_identify(dc);
DPRINTF("tga_getdevconfig: preparing to get config\n");
tgac = dc->dc_tgaconf = tga_getconf(dc->dc_tga_type);
  250         if (tgac == NULL)
  251                 return;
  253 #if 0
  254         /* XXX on the Alpha, pcisize = 4 * cspace_size. */
  255         if (tgac->tgac_cspace_size != pcisize)                  /* sanity */
panic("tga_getdevconfig: memory size mismatch?");
  257 #endif
DPRINTF("tga_getdevconfig: get revno\n");
  260         switch (TGARREG(dc, TGA_REG_GREV) & 0xff) {
  261         case 0x01:
  262         case 0x02:
  263         case 0x03:
  264         case 0x04:
dc->dc_tga2 = 0;
  266                 break;
  267         case 0x20:
  268         case 0x21:
  269         case 0x22:
dc->dc_tga2 = 1;
  271                 break;
  272         default:
panic("tga_getdevconfig: TGA Revision not recognized");
  274         }
  276         if (dc->dc_tga2) {
tga2_init(dc);
  278         }
i = TGARREG(dc, TGA_REG_VHCR) & 0x1ff;
DPRINTF("tga_getdevconfig: TGA_REG_VHCR & 0x1ff = %d\n", i);
  282         switch (i) {            /* XXX */
  283         case 0:
dc->dc_wid = 8192;
  285                 break;
  287         case 1:
dc->dc_wid = 8196;
  289                 break;
  291         default:
dc->dc_wid = (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) * 4; /* XXX */
  293                 break;
  294         }
DPRINTF("tga_getdevconfig: dc->dc_wid = %d\n", dc->dc_wid);
  297         /*
  298          * XXX XXX Turning off "odd" shouldn't be necessary,
  299          * XXX XXX but I can't make X work with the weird size.
  300          */
DPRINTF("tga_getdevconfig: beginning magic incantation\n");
  302         if ((TGARREG(dc, TGA_REG_VHCR) & 0x00000001) != 0 &&    /* XXX */
  303             (TGARREG(dc, TGA_REG_VHCR) & 0x80000000) != 0) {    /* XXX */
TGAWREG(dc, TGA_REG_VHCR,
  305                     (TGARREG(dc, TGA_REG_VHCR) & ~0x80000001));
dc->dc_wid -= 4;
  307         }
dc->dc_rowbytes = dc->dc_wid * (dc->dc_tgaconf->tgac_phys_depth / 8);
dc->dc_ht = (TGARREG(dc, TGA_REG_VVCR) & 0x7ff);        /* XXX */
DPRINTF("tga_getdevconfig: rowbytes = %d, tgac_phys_depth = %d\n"
  312                 "                  dc_wid = %d, dc_ht = %d\n",
dc->dc_rowbytes, dc->dc_tgaconf->tgac_phys_depth,
dc->dc_wid, dc->dc_ht);
  316         /* XXX this seems to be what DEC does */
DPRINTF("tga_getdevconfig: more magic\n");
TGAWREG(dc, TGA_REG_CCBR, 0);
TGAWREG(dc, TGA_REG_VVBR, 1);
dc->dc_videobase = dc->dc_vaddr + tgac->tgac_dbuf[0] +
  321             1 * tgac->tgac_vvbr_units;
dc->dc_blanked = 1;
tga_unblank(dc);
DPRINTF("tga_getdevconfig: dc_videobase = 0x%016llx\n"
  326                 "                  dc_vaddr = 0x%016llx\n"
  327                 "                  tgac_dbuf[0] = %d\n"
  328                 "                  tgac_vvbr_units = %d\n",
dc->dc_videobase, dc->dc_vaddr, tgac->tgac_dbuf[0],
tgac->tgac_vvbr_units);
  332         /*
  333          * Set all bits in the pixel mask, to enable writes to all pixels.
  334          * It seems that the console firmware clears some of them
  335          * under some circumstances, which causes cute vertical stripes.
  336          */
DPRINTF("tga_getdevconfig: set pixel mask\n");
TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff);
  340         /* clear the screen */
DPRINTF("tga_getdevconfig: clear screen\n");
  342         for (i = 0; i < dc->dc_ht * dc->dc_rowbytes; i += sizeof(u_int32_t))
  343                 *(u_int32_t *)(dc->dc_videobase + i) = 0;
DPRINTF("tga_getdevconfig: raster ops\n");
  346         /* Initialize rasops descriptor */
rip = &dc->dc_rinfo;
rip->ri_flg = RI_CENTER;
rip->ri_depth = tgac->tgac_phys_depth;
rip->ri_bits = (void *)dc->dc_videobase;
rip->ri_width = dc->dc_wid;
rip->ri_height = dc->dc_ht;
rip->ri_stride = dc->dc_rowbytes;
rip->ri_hw = dc;
  356         if (tgac->tgac_phys_depth == 32) {
rip->ri_rnum = 8;
rip->ri_gnum = 8;
rip->ri_bnum = 8;
rip->ri_rpos = 16;
rip->ri_gpos = 8;
rip->ri_bpos = 0;
  363         }
DPRINTF("tga_getdevconfig: wsfont_init\n");
wsfont_init();
  367         if (rip->ri_width > 80*12) 
  368                 /* High res screen, choose a big font */
cookie = wsfont_find(NULL, 12, 0, 0);
  370         else 
  371                 /*  lower res, choose a 8 pixel wide font */
cookie = wsfont_find(NULL, 8, 0, 0);
  373         if (cookie <= 0)
cookie = wsfont_find(NULL, 0, 0, 0);
  375         if (cookie <= 0) {
printf("tga: no appropriate fonts.\n");
  377                 return;
  378         }
  380         /* the accelerated tga_putchar() needs LSbit left */
  381         if (wsfont_lock(cookie, &rip->ri_font,
WSDISPLAY_FONTORDER_R2L, WSDISPLAY_FONTORDER_L2R) <= 0) {
printf("tga: couldn't lock font\n");
  384                 return;
  385         }
rip->ri_wsfcookie = cookie;
  387         /* fill screen size */
rasops_init(rip, rip->ri_height / rip->ri_font->fontheight,
rip->ri_width / rip->ri_font->fontwidth); 
  391         /* add our accelerated functions */
  392         /* XXX shouldn't have to do this; rasops should leave non-NULL 
  393          * XXX entries alone.
  394          */
rip->ri_ops.copyrows = tga_copyrows;
rip->ri_ops.eraserows = tga_eraserows;
rip->ri_ops.erasecols = tga_erasecols;
rip->ri_ops.copycols = tga_copycols;
rip->ri_ops.putchar = tga_putchar;      
tga_stdscreen.nrows = rip->ri_rows;
tga_stdscreen.ncols = rip->ri_cols;
tga_stdscreen.textops = &rip->ri_ops;
tga_stdscreen.capabilities = rip->ri_caps;
dc->dc_intrenabled = 0;
  407 }
  409 void
tgaattach(parent, self, aux)
  411         struct device *parent, *self;
  412         void *aux;
  413 {
  414         struct pci_attach_args *pa = aux;
  415         struct tga_softc *sc = (struct tga_softc *)self;
  416         struct wsemuldisplaydev_attach_args aa;
pci_intr_handle_t intrh;
  418         const char *intrstr;
u_int8_t rev;
  420         int console;
  422 #if defined(__alpha__) || defined(arc)
console = (pa->pa_tag == tga_console_dc.dc_pcitag);
  424 #else
console = 0;
  426 #endif
  427         if (console) {
sc->sc_dc = &tga_console_dc;
sc->nscreens = 1;
  430         } else {
sc->sc_dc = (struct tga_devconfig *)
malloc(sizeof(struct tga_devconfig), M_DEVBUF, M_NOWAIT);
  433                 if (sc->sc_dc == NULL)
  434                         return;
bzero(sc->sc_dc, sizeof(struct tga_devconfig));
tga_getdevconfig(pa->pa_memt, pa->pa_pc, pa->pa_tag,
sc->sc_dc);
  438         }
  439         if (sc->sc_dc->dc_vaddr == NULL) {
printf(": couldn't map memory space; punt!\n");
  441                 return;
  442         }
  444         /* XXX say what's going on. */
intrstr = NULL;
  446         if (pci_intr_map(pa, &intrh)) {
printf(": couldn't map interrupt");
  448                 return;
  449         }
intrstr = pci_intr_string(pa->pa_pc, intrh);
sc->sc_intr = pci_intr_establish(pa->pa_pc, intrh, IPL_TTY, tga_intr,
sc->sc_dc, sc->sc_dev.dv_xname);
  453         if (sc->sc_intr == NULL) {
printf(": couldn't establish interrupt");
  455                 if (intrstr != NULL)
printf("at %s", intrstr);
printf("\n");
  458                 return;
  459         }
rev = PCI_REVISION(pa->pa_class);
  462         switch (rev) {
  463         case 0x1:
  464         case 0x2:
  465         case 0x3:
printf(": DC21030 step %c", 'A' + rev - 1);
  467                 break;
  468         case 0x20:
printf(": TGA2 abstract software model");
  470                 break;
  471         case 0x21:
  472         case 0x22:
printf(": TGA2 pass %d", rev - 0x20);
  474                 break;
  476         default:
printf("unknown stepping (0x%x)", rev);
  478                 break;
  479         }
printf(", ");
  482         /*
  483          * Get RAMDAC function vectors and call the RAMDAC functions
  484          * to allocate its private storage and pass that back to us.
  485          */
DPRINTF("tgaattach: Get RAMDAC functions\n");
sc->sc_dc->dc_ramdac_funcs = sc->sc_dc->dc_tgaconf->ramdac_funcs();
  489         if (!sc->sc_dc->dc_tga2) {
DPRINTF("tgaattach: !sc->sc_dc->dc_tga2\n");
DPRINTF("tgaattach: sc->sc_dc->dc_tgaconf->ramdac_funcs %s "
  492                     "bt485_funcs\n",
  493                     (sc->sc_dc->dc_tgaconf->ramdac_funcs == bt485_funcs)
  494                     ? "==" : "!=");
  495             if (sc->sc_dc->dc_tgaconf->ramdac_funcs == bt485_funcs) 
sc->sc_dc->dc_ramdac_cookie = 
sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc,
tga_sched_update, tga_ramdac_wr, tga_ramdac_rd);
  499                 else
sc->sc_dc->dc_ramdac_cookie = 
sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc,
tga_sched_update, tga_bt463_wr, tga_bt463_rd);
  503         } else {
DPRINTF("tgaattach: sc->sc_dc->dc_tga2\n");
sc->sc_dc->dc_ramdac_cookie = 
sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 
tga_sched_update, tga2_ramdac_wr, tga2_ramdac_rd);
  509                 /* XXX this is a bit of a hack, setting the dotclock here */
  510                 if (sc->sc_dc->dc_tgaconf->ramdac_funcs != bt485_funcs)
  511                         (*sc->sc_dc->dc_ramdac_funcs->ramdac_set_dotclock)
  512                                 (sc->sc_dc->dc_ramdac_cookie,
tga_getdotclock(sc->sc_dc));
  514         }
DPRINTF("tgaattach: sc->sc_dc->dc_ramdac_cookie = 0x%016llx\n",
sc->sc_dc->dc_ramdac_cookie);
  517         /*
  518          * Initialize the RAMDAC.  Initialization includes disabling
  519          * cursor, setting a sane colormap, etc.
  520          */
DPRINTF("tgaattach: Initializing RAMDAC.\n");
  522         (*sc->sc_dc->dc_ramdac_funcs->ramdac_init)(sc->sc_dc->dc_ramdac_cookie);
TGAWREG(sc->sc_dc, TGA_REG_SISR, 0x00000001); /* XXX */
  525         if (sc->sc_dc->dc_tgaconf == NULL) {
printf("unknown board configuration\n");
  527                 return;
  528         }
printf("board type %s\n", sc->sc_dc->dc_tgaconf->tgac_name);
printf("%s: %d x %d, %dbpp, %s RAMDAC\n", sc->sc_dev.dv_xname,
sc->sc_dc->dc_wid, sc->sc_dc->dc_ht,
sc->sc_dc->dc_tgaconf->tgac_phys_depth,
sc->sc_dc->dc_ramdac_funcs->ramdac_name);
  535         if (intrstr != NULL)
printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname,
intrstr);
aa.console = console;
aa.scrdata = &tga_screenlist;
aa.accessops = &tga_accessops;
aa.accesscookie = sc;
aa.defaultscreens = 0;
config_found(self, &aa, wsemuldisplaydevprint);
  547 #ifdef __NetBSD__
config_interrupts(self, tga_config_interrupts);
  549 #else
tga_config_interrupts(self);
  551 #endif
  552 }
  554 void 
tga_config_interrupts (d)
  556         struct device *d;
  557 {
  558         struct tga_softc *sc = (struct tga_softc *)d;
sc->sc_dc->dc_intrenabled = 1;
  560 }
  563 int
tga_ioctl(v, cmd, data, flag, p)
  565         void *v;
u_long cmd;
caddr_t data;
  568         int flag;
  569         struct proc *p;
  570 {
  571         struct tga_softc *sc = v;
  572         struct tga_devconfig *dc = sc->sc_dc;
  573         struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs;
  574         struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie;
  576         switch (cmd) {
  577         case WSDISPLAYIO_GTYPE:
  578                 *(u_int *)data = WSDISPLAY_TYPE_TGA;
  579                 break;
  581         case WSDISPLAYIO_SMODE:
sc->sc_mode = *(u_int *)data;
  583                 switch (sc->sc_mode) {
  584                 case WSDISPLAYIO_MODE_DUMBFB:
  585                         /* in dump fb mode start the framebuffer at 0 */
TGAWREG(dc, TGA_REG_VVBR, 0);
  587                         break;
  588                 default:
  589                         /* XXX it this useful, except for not breaking Xtga? */
TGAWREG(dc, TGA_REG_VVBR, 1);
  591                         break;                  
  592                 }
  593                 break;
  595         case WSDISPLAYIO_GINFO:
  596 #define wsd_fbip ((struct wsdisplay_fbinfo *)data)
wsd_fbip->height = sc->sc_dc->dc_ht;
wsd_fbip->width = sc->sc_dc->dc_wid;
wsd_fbip->depth = sc->sc_dc->dc_tgaconf->tgac_phys_depth;
wsd_fbip->cmsize = 1024;                /* XXX ??? */
  601 #undef wsd_fbip
  602                 break;
  604         case WSDISPLAYIO_LINEBYTES:
  605                 *(u_int *)data = sc->sc_dc->dc_rowbytes;
  606                 break;
  608         case WSDISPLAYIO_GETCMAP:
  609                 return (*dcrf->ramdac_get_cmap)(dcrc,
  610                     (struct wsdisplay_cmap *)data);
  611         case WSDISPLAYIO_PUTCMAP:
  612                 return (*dcrf->ramdac_set_cmap)(dcrc,
  613                     (struct wsdisplay_cmap *)data);
  615         case WSDISPLAYIO_SVIDEO:
  616         case WSDISPLAYIO_GVIDEO:
  617                 break;
  619         case WSDISPLAYIO_GCURPOS:
  620                 return (*dcrf->ramdac_get_curpos)(dcrc,
  621                     (struct wsdisplay_curpos *)data);
  623         case WSDISPLAYIO_SCURPOS:
  624                 return (*dcrf->ramdac_set_curpos)(dcrc,
  625                     (struct wsdisplay_curpos *)data);
  627         case WSDISPLAYIO_GCURMAX:
  628                 return (*dcrf->ramdac_get_curmax)(dcrc,
  629                     (struct wsdisplay_curpos *)data);
  631         case WSDISPLAYIO_GCURSOR:
  632                 return (*dcrf->ramdac_get_cursor)(dcrc,
  633                     (struct wsdisplay_cursor *)data);
  635         case WSDISPLAYIO_SCURSOR:
  636                 return (*dcrf->ramdac_set_cursor)(dcrc,
  637                     (struct wsdisplay_cursor *)data);
  639         default:
  640                 return (-1);
  641         }
  643         return (0);
  644 }
  646 int
tga_sched_update(v, f)
  648         void    *v;
  649         void    (*f)(void *);
  650 {
  651         struct tga_devconfig *dc = v;
  653         if (dc->dc_intrenabled) {
  654                 /* Arrange for f to be called at the next end-of-frame interrupt */
dc->dc_ramdac_intr = f;
TGAWREG(dc, TGA_REG_SISR, 0x00010000);
  657         } else {
  658                 /* Spin until the end-of-frame, then call f */
TGAWREG(dc, TGA_REG_SISR, 0x00010001);
TGAREGWB(dc, TGA_REG_SISR, 1);
  661                 while ((TGARREG(dc, TGA_REG_SISR) & 0x00000001) == 0)
  662                         ;
f(dc->dc_ramdac_cookie);
TGAWREG(dc, TGA_REG_SISR, 0x00000001);
TGAREGWB(dc, TGA_REG_SISR, 1);
  666         }
  668         return 0;
  669 }
  671 int
tga_intr(v)
  673         void *v;
  674 {
  675         struct tga_devconfig *dc = v;
  676         struct ramdac_cookie *dcrc= dc->dc_ramdac_cookie;
u_int32_t reg;
reg = TGARREG(dc, TGA_REG_SISR);
  681         if (( reg & 0x00010001) != 0x00010001) {
  682                 /* Odd. We never set any of the other interrupt enables. */
  683                 if ((reg & 0x1f) != 0) {
  684                         /* Clear the mysterious pending interrupts. */
TGAWREG(dc, TGA_REG_SISR, (reg & 0x1f));
TGAREGWB(dc, TGA_REG_SISR, 1);
  687                         /* This was our interrupt, even if we're puzzled as to why
  688                          * we got it.  Don't make the interrupt handler think it
  689                          * was a stray.  
  690                          */
  691                         return -1;
  692                 } else {
  693                         return 0;
  694                 }
  695         }
  696         /* if we have something to do, do it */
  697         if (dc->dc_ramdac_intr) {
dc->dc_ramdac_intr(dcrc);
dc->dc_ramdac_intr = NULL;
  700         }
TGAWREG(dc, TGA_REG_SISR, 0x00000001);
TGAREGWB(dc, TGA_REG_SISR, 1);
  703         return (1);
  704 }
paddr_t
tga_mmap(v, offset, prot)
  708         void *v;
off_t offset;
  710         int prot;
  711 {
  712         struct tga_softc *sc = v;
  713         struct tga_devconfig *dc = sc->sc_dc;
  715         if (offset >= dc->dc_tgaconf->tgac_cspace_size || offset < 0)
  716                 return -1;
  718         if (sc->sc_mode == WSDISPLAYIO_MODE_DUMBFB) {
  719                 /* 
  720                  * The framebuffer starts at the upper half of tga mem
  721                  */
offset += dc->dc_tgaconf->tgac_cspace_size / 2;
  723         }
  724 #if defined(__alpha__) || defined(__mips__)
  725         return atop(sc->sc_dc->dc_paddr + offset);
  726 #else
  727         return (-1);
  728 #endif
  729 }
  731 int
tga_alloc_screen(v, type, cookiep, curxp, curyp, attrp)
  733         void *v;
  734         const struct wsscreen_descr *type;
  735         void **cookiep;
  736         int *curxp, *curyp;
  737         long *attrp;
  738 {
  739         struct tga_softc *sc = v;
  740         long defattr;
  742         if (sc->nscreens > 0)
  743                 return (ENOMEM);
  745         *cookiep = &sc->sc_dc->dc_rinfo; /* one and only for now */
  746         *curxp = 0;
  747         *curyp = 0;
sc->sc_dc->dc_rinfo.ri_ops.alloc_attr(&sc->sc_dc->dc_rinfo, 
  749                 0, 0, 0, &defattr);
  750         *attrp = defattr;
sc->nscreens++;
  752         return (0);
  753 }
  755 void
tga_free_screen(v, cookie)
  757         void *v;
  758         void *cookie;
  759 {
  760         struct tga_softc *sc = v;
  762         if (sc->sc_dc == &tga_console_dc)
panic("tga_free_screen: console");
sc->nscreens--;
  766 }
  768 int
tga_show_screen(v, cookie, waitok, cb, cbarg)
  770         void *v;
  771         void *cookie;
  772         int waitok;
  773         void (*cb)(void *, int, int);
  774         void *cbarg;
  775 {
  777         return (0);
  778 }
  780 int
tga_cnattach(iot, memt, pc, bus, device, function)
bus_space_tag_t iot, memt;
pci_chipset_tag_t pc;
  784         int bus, device, function;
  785 {
  786         struct tga_devconfig *dcp = &tga_console_dc;
  787         long defattr;
tga_getdevconfig(memt, pc,
pci_make_tag(pc, bus, device, function), dcp);
  792         /* sanity checks */
  793         if (dcp->dc_vaddr == NULL)
panic("tga_console(%d, %d): couldn't map memory space",
device, function);
  796         if (dcp->dc_tgaconf == NULL)
panic("tga_console(%d, %d): unknown board configuration",
device, function);
  800         /*
  801          * Initialize the RAMDAC but DO NOT allocate any private storage.
  802          * Initialization includes disabling cursor, setting a sane
  803          * colormap, etc.  It will be reinitialized in tgaattach().
  804          */
  805         if (dcp->dc_tga2) {
  806                 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs)
bt485_cninit(dcp, tga_sched_update, tga2_ramdac_wr,
tga2_ramdac_rd);
  809                 else
ibm561_cninit(dcp, tga_sched_update, tga2_ramdac_wr,
tga2_ramdac_rd, tga_getdotclock(dcp));
  812         } else {
  813                 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs)
bt485_cninit(dcp, tga_sched_update, tga_ramdac_wr,
tga_ramdac_rd);
  816                 else {
bt463_cninit(dcp, tga_sched_update, tga_bt463_wr,
tga_bt463_rd);
  819                 }
  820         }
dcp->dc_rinfo.ri_ops.alloc_attr(&dcp->dc_rinfo, 0, 0, 0, &defattr);
wsdisplay_cnattach(&tga_stdscreen, &dcp->dc_rinfo, 0, 0, defattr);
  824         return(0);
  825 }
  827 /*
  828  * Functions to blank and unblank the display.
  829  */
  830 void
tga_burner(v, on, flags)
  832         void *v;
u_int on, flags;
  834 {
  835         struct tga_softc *sc = v;
  837         if (on) {
tga_unblank(sc->sc_dc);
  839         } else {
tga_blank(sc->sc_dc);
  841         }
  842 }
  844 void
tga_blank(dc)
  846         struct tga_devconfig *dc;
  847 {
  849         if (!dc->dc_blanked) {
dc->dc_blanked = 1;
  851                 /* XXX */
TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | VVR_BLANK);
  853         }
  854 }
  856 void
tga_unblank(dc)
  858         struct tga_devconfig *dc;
  859 {
  861         if (dc->dc_blanked) {
dc->dc_blanked = 0;
  863                 /* XXX */
TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~VVR_BLANK);
  865         }
  866 }
  868 /*
  869  * Functions to manipulate the built-in cursor handing hardware.
  870  */
  871 int
tga_builtin_set_cursor(dc, cursorp)
  873         struct tga_devconfig *dc;
  874         struct wsdisplay_cursor *cursorp;
  875 {
  876         struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs;
  877         struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie;
u_int count, v;
  879         int error;
v = cursorp->which;
  882         if (v & WSDISPLAY_CURSOR_DOCMAP) {
error = dcrf->ramdac_check_curcmap(dcrc, cursorp);
  884                 if (error)
  885                         return (error);
  886         }
  887         if (v & WSDISPLAY_CURSOR_DOSHAPE) {
  888                 if ((u_int)cursorp->size.x != 64 ||
  889                     (u_int)cursorp->size.y > 64)
  890                         return (EINVAL);
  891         }
  892         if (v & WSDISPLAY_CURSOR_DOHOT)         /* not supported */
  893                 return EINVAL;
  895         /* parameters are OK; do it */
  896         if (v & WSDISPLAY_CURSOR_DOCUR) {
  897                 if (cursorp->enable)
  898                         /* XXX */
TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 0x04);
  900                 else
  901                         /* XXX */
TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~0x04);
  903         }
  904         if (v & WSDISPLAY_CURSOR_DOPOS) {
TGAWREG(dc, TGA_REG_CXYR, 
  906                     ((cursorp->pos.y & 0xfff) << 12) | (cursorp->pos.x & 0xfff));
  907         }
  908         if (v & WSDISPLAY_CURSOR_DOCMAP) {
  909                 /* can't fail. */
dcrf->ramdac_set_curcmap(dcrc, cursorp);
  911         }
  912         if (v & WSDISPLAY_CURSOR_DOSHAPE) {
  913                 /* The cursor is 2 bits deep, and there is no mask */
count = (cursorp->size.y * 64 * 2) / NBBY;
TGAWREG(dc, TGA_REG_CCBR,
  916                     (TGARREG(dc, TGA_REG_CCBR) & ~0xfc00) | (cursorp->size.y << 10));
  917                 if ((error = copyin(cursorp->image,(char *)(dc->dc_vaddr +
  918                     (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), count)) != 0)
  919                         return (error);
  920         }
  921         return (0);
  922 }
  924 int
tga_builtin_get_cursor(dc, cursorp)
  926         struct tga_devconfig *dc;
  927         struct wsdisplay_cursor *cursorp;
  928 {
  929         struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs;
  930         struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie;
  931         int error;
u_int count;
cursorp->which = WSDISPLAY_CURSOR_DOALL &
  935             ~(WSDISPLAY_CURSOR_DOHOT | WSDISPLAY_CURSOR_DOCMAP);
cursorp->enable = (TGARREG(dc, TGA_REG_VVVR) & 0x04) != 0;
cursorp->pos.x = TGARREG(dc, TGA_REG_CXYR) & 0xfff;
cursorp->pos.y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff;
cursorp->size.x = 64;
cursorp->size.y = (TGARREG(dc, TGA_REG_CCBR) >> 10) & 0x3f;
  942         if (cursorp->image != NULL) {
count = (cursorp->size.y * 64 * 2) / NBBY;
error = copyout((char *)(dc->dc_vaddr +
  945                       (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)),
cursorp->image, count);
  947                 if (error)
  948                         return (error);
  949                 /* No mask */
  950         }
error = dcrf->ramdac_get_curcmap(dcrc, cursorp);
  952         return (error);
  953 }
  955 int
tga_builtin_set_curpos(dc, curposp)
  957         struct tga_devconfig *dc;
  958         struct wsdisplay_curpos *curposp;
  959 {
TGAWREG(dc, TGA_REG_CXYR,
  962             ((curposp->y & 0xfff) << 12) | (curposp->x & 0xfff));
  963         return (0);
  964 }
  966 int
tga_builtin_get_curpos(dc, curposp)
  968         struct tga_devconfig *dc;
  969         struct wsdisplay_curpos *curposp;
  970 {
curposp->x = TGARREG(dc, TGA_REG_CXYR) & 0xfff;
curposp->y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff;
  974         return (0);
  975 }
  977 int
tga_builtin_get_curmax(dc, curposp)
  979         struct tga_devconfig *dc;
  980         struct wsdisplay_curpos *curposp;
  981 {
curposp->x = curposp->y = 64;
  984         return (0);
  985 }
  987 /*
  988  * Copy columns (characters) in a row (line).
  989  */
  990 void
tga_copycols(id, row, srccol, dstcol, ncols)
  992         void *id;
  993         int row, srccol, dstcol, ncols;
  994 {
  995         struct rasops_info *ri = id;
  996         int y, srcx, dstx, nx;
y = ri->ri_font->fontheight * row;
srcx = ri->ri_font->fontwidth * srccol;
dstx = ri->ri_font->fontwidth * dstcol;
nx = ri->ri_font->fontwidth * ncols;
tga_rop(ri, dstx, y, nx, ri->ri_font->fontheight, ri, srcx, y);
 1004 }
 1006 /*
 1007  * Copy rows (lines).
 1008  */
 1009 void
tga_copyrows(id, srcrow, dstrow, nrows)
 1011         void *id;
 1012         int srcrow, dstrow, nrows;
 1013 {
 1014         struct rasops_info *ri = id;
 1015         int srcy, dsty, ny;
srcy = ri->ri_font->fontheight * srcrow;
dsty = ri->ri_font->fontheight * dstrow;
ny = ri->ri_font->fontheight * nrows;
tga_rop(ri, 0, dsty, ri->ri_emuwidth, ny, ri, 0, srcy);
 1022 }
 1024 /*
 1025  *  Generic TGA raster op.
 1026  *   This covers all possible raster ops, and
 1027  *   clips the sizes and all of that.
 1028  */
 1029 int
tga_rop(dst, dx, dy, w, h, src, sx, sy)
 1031         struct rasops_info *dst;
 1032         int dx, dy, w, h;
 1033         struct rasops_info *src;
 1034         int sx, sy;
 1035 {
 1036         if (dst == NULL || src == NULL)
 1037                 return -1;
 1039         /* Clip against src */
 1040         if (sx < 0) {
w += sx;
sx = 0;
 1043         }
 1044         if (sy < 0) {
h += sy;
sy = 0;
 1047         }
 1048         if (sx + w > src->ri_emuwidth)
w = src->ri_emuwidth - sx;
 1050         if (sy + h > src->ri_emuheight)
h = src->ri_emuheight - sy;
 1053         /* Clip against dst.  We modify src regardless of using it,
 1054          * since it really doesn't matter.
 1055          */
 1056         if (dx < 0) {
w += dx;
sx -= dx;
dx = 0;
 1060         }
 1061         if (dy < 0) {
h += dy;
sy -= dy;
dy = 0;
 1065         }
 1066         if (dx + w > dst->ri_emuwidth)
w = dst->ri_emuwidth - dx;
 1068         if (dy + h > dst->ri_emuheight)
h = dst->ri_emuheight - dy;
 1070         if (w <= 0 || h <= 0)
 1071                 return 0;       /* Vacuously true; */
 1073         return tga_rop_vtov(dst, dx, dy, w, h, src, sx, sy);
 1074 }
 1078 /*
 1079  * Video to Video raster ops.
 1080  * This function deals with all raster ops that have a src and dst
 1081  * that are on the card.
 1082  */
 1083 int
tga_rop_vtov(dst, dx, dy, w, h, src, sx, sy)
 1085         struct rasops_info *dst;
 1086         int dx, dy, w, h;
 1087         struct rasops_info *src;
 1088         int sx, sy;
 1089 {
 1090         struct tga_devconfig *dc = (struct tga_devconfig *)dst->ri_hw;
 1091         int srcb, dstb, tga_srcb, tga_dstb;
 1092         int x, y, wb;
 1093         int xstart, xend, xdir;
 1094         int ystart, yend, ydir, yinc;
 1095         int xleft, lastx, lastleft;
 1096         int offset = 1 * dc->dc_tgaconf->tgac_vvbr_units;
 1098         /*
 1099          * I don't yet want to deal with unaligned guys, really.  And we don't
 1100          * deal with copies from one card to another.
 1101          */
 1102         if (dx % 8 != 0 || sx % 8 != 0 || src != dst) {
 1103                 /* XXX Punt! */
 1104                 /* XXX should never happen, since it's only being used to
 1105                  * XXX copy 8-pixel-wide characters.
 1106                  */
 1107                 return -1;
 1108         }
wb = w * (dst->ri_depth / 8);
 1111         if (sy >= dy) {
ystart = 0;
yend = h;
ydir = 1;
 1115         } else {
ystart = h;
yend = 0;
ydir = -1;
 1119         }
 1120         if (sx >= dx) {      /* moving to the left */
xstart = 0;
xend = w * (dst->ri_depth / 8) - 4;
xdir = 1;
 1124         } else {             /* moving to the right */
xstart = wb - ( wb >= 4*64 ? 4*64 : wb >= 64 ? 64 : 4 );
xend = 0;
xdir = -1;
 1128         }
 1129 #define XINC4   4
 1130 #define XINC64  64
 1131 #define XINC256 (64*4)
yinc = ydir * dst->ri_stride;
ystart *= dst->ri_stride;
yend *= dst->ri_stride;
srcb = sy * src->ri_stride + sx * (src->ri_depth/8);
dstb = dy * dst->ri_stride + dx * (dst->ri_depth/8);
tga_srcb = offset + (sy + src->ri_yorigin) * src->ri_stride + 
 1139                 (sx + src->ri_xorigin) * (src->ri_depth/8);
tga_dstb = offset + (dy + dst->ri_yorigin) * dst->ri_stride + 
 1141                 (dx + dst->ri_xorigin) * (dst->ri_depth/8);
TGAWALREG(dc, TGA_REG_GMOR, 3, 0x0007); /* Copy mode */
TGAWALREG(dc, TGA_REG_GOPR, 3, 0x0003); /* SRC */
 1146         /*
 1147          * we have 3 sizes of pixels to move in X direction:
 1148          * 4 * 64   (unrolled TGA ops)
 1149          *     64   (single TGA op)
 1150          *      4   (CPU, using long word)
 1151          */
 1153         if (xdir == 1) {   /* move to the left */
 1155                 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) {
 1157                         /* 4*64 byte chunks */
 1158                         for (xleft = wb, x = xstart;
x <= xend && xleft >= 4*64;
x += XINC256, xleft -= XINC256) {
 1162                                 /* XXX XXX Eight writes to different addresses should fill 
 1163                                  * XXX XXX up the write buffers on 21064 and 21164 chips,
 1164                                  * XXX XXX but later CPUs might have larger write buffers which
 1165                                  * XXX XXX require further unrolling of this loop, or the
 1166                                  * XXX XXX insertion of memory barriers.
 1167                                  */
TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64);
TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64);
TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x + 1 * 64);
TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x + 1 * 64);
TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x + 2 * 64);
TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x + 2 * 64);
TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x + 3 * 64);
TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x + 3 * 64);
 1176                         }
 1178                         /* 64 byte chunks */
 1179                         for ( ; x <= xend && xleft >= 64;
x += XINC64, xleft -= XINC64) {
TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64);
TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64);
 1183                         }
lastx = x; lastleft = xleft;  /* remember for CPU loop */
 1186                 }
TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */
TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */
 1190                 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) {
 1191                         /* 4 byte granularity */
 1192                         for (x = lastx, xleft = lastleft;
x <= xend && xleft >= 4;
x += XINC4, xleft -= XINC4) {
 1195                                 *(uint32_t *)(dst->ri_bits + dstb + y + x) =
 1196                                         *(uint32_t *)(dst->ri_bits + srcb + y + x);
 1197                         }
 1198                 }
 1199         }
 1200         else {    /* above move to the left, below move to the right */
 1202                 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) {
 1204                         /* 4*64 byte chunks */
 1205                         for (xleft = wb, x = xstart;
x >= xend && xleft >= 4*64;
x -= XINC256, xleft -= XINC256) {
 1209                                 /* XXX XXX Eight writes to different addresses should fill 
 1210                                  * XXX XXX up the write buffers on 21064 and 21164 chips,
 1211                                  * XXX XXX but later CPUs might have larger write buffers which
 1212                                  * XXX XXX require further unrolling of this loop, or the
 1213                                  * XXX XXX insertion of memory barriers.
 1214                                  */
TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 3 * 64);
TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 3 * 64);
TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x + 2 * 64);
TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x + 2 * 64);
TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x + 1 * 64);
TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x + 1 * 64);
TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x + 0 * 64);
TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x + 0 * 64);
 1223                         }
 1225                         if (xleft) x += XINC256 - XINC64;
 1227                         /* 64 byte chunks */
 1228                         for ( ; x >= xend && xleft >= 64;
x -= XINC64, xleft -= XINC64) {
TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64);
TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64);
 1232                         }
 1233                         if (xleft) x += XINC64 - XINC4;
lastx = x; lastleft = xleft;  /* remember for CPU loop */
 1235                 }
TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */
TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */
 1239                 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) {
 1240                         /* 4 byte granularity */
 1241                         for (x = lastx, xleft = lastleft;
x >= xend && xleft >= 4;
x -= XINC4, xleft -= XINC4) {
 1244                                 *(uint32_t *)(dst->ri_bits + dstb + y + x) =
 1245                                         *(uint32_t *)(dst->ri_bits + srcb + y + x);
 1246                         }
 1247                 }
 1248         }
 1249         return 0;
 1250 }
 1253 void
tga_putchar(c, row, col, uc, attr)
 1255         void *c;
 1256         int row, col;
u_int uc;
 1258         long attr;
 1259 {
 1260         struct rasops_info *ri = c;
 1261         struct tga_devconfig *dc = ri->ri_hw;
 1262         int fs, height, width;
 1263         int fg, bg, ul;
u_char *fr;
int32_t *rp;
rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale);
height = ri->ri_font->fontheight;
width = ri->ri_font->fontwidth;
uc -= ri->ri_font->firstchar;
fr = (u_char *)ri->ri_font->data + uc * ri->ri_fontscale;
fs = ri->ri_font->stride;
 1276         /* Set foreground and background color. XXX memoize this somehow?
 1277          * The rasops code has already expanded the color entry to 32 bits
 1278          * for us, even for 8-bit displays, so we don't have to do anything.
 1279          */
ri->ri_ops.unpack_attr(c, attr, &fg, &bg, &ul);
TGAWREG(dc, TGA_REG_GFGR, ri->ri_devcmap[fg]);
TGAWREG(dc, TGA_REG_GBGR, ri->ri_devcmap[bg]);
 1284         /* Set raster operation to "copy"... */
 1285         if (ri->ri_depth == 8)
TGAWREG(dc, TGA_REG_GOPR, 0x3);
 1287         else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */
TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8));
 1290         /* Set which pixels we're drawing (of a possible 32). */
TGAWREG(dc, TGA_REG_GPXR_P, (1 << width) - 1);
 1293         /* Set drawing mode to opaque stipple. */
TGAWREG(dc, TGA_REG_GMOR, 0x1);
 1296         /* Insert write barrier before actually sending data */
 1297         /* XXX Abuses the fact that there is only one write barrier on Alphas */
TGAREGWB(dc, TGA_REG_GMOR, 1);
 1300         while (height--) {
 1301                 /* The actual stipple write */
 1302                 *rp = fr[0] | (fr[1] << 8) | (fr[2] << 16) | (fr[3] << 24); 
fr += fs;
rp = (int32_t *)((caddr_t)rp + ri->ri_stride);
 1306         }
 1308         /* Do underline */
 1309         if (ul) {
rp = (int32_t *)((caddr_t)rp - (ri->ri_stride << 1));
 1311                 *rp = 0xffffffff;
 1312         }
 1314         /* Set grapics mode back to normal. */
TGAWREG(dc, TGA_REG_GMOR, 0);
TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff);
 1317 }
 1319 void
tga_eraserows(c, row, num, attr)
 1321         void *c;
 1322         int row, num;
 1323         long attr;
 1324 {
 1325         struct rasops_info *ri = c;
 1326         struct tga_devconfig *dc = ri->ri_hw;
int32_t color, lines, pixels;
 1328         int fg, bg;
int32_t *rp;
ri->ri_ops.unpack_attr(c, attr, &fg, &bg, NULL);
color = ri->ri_devcmap[bg];
rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale);
lines = num * ri->ri_font->fontheight;
pixels = ri->ri_emuwidth - 1;
 1337         /* Set fill color in block-color registers */
TGAWREG(dc, TGA_REG_GBCR0, color);
TGAWREG(dc, TGA_REG_GBCR1, color);
 1340         if (ri->ri_depth != 8) {
TGAWREG(dc, TGA_REG_GBCR2, color);
TGAWREG(dc, TGA_REG_GBCR3, color);
TGAWREG(dc, TGA_REG_GBCR4, color);
TGAWREG(dc, TGA_REG_GBCR5, color);
TGAWREG(dc, TGA_REG_GBCR6, color);
TGAWREG(dc, TGA_REG_GBCR7, color);
 1347         }
 1349         /* Set raster operation to "copy"... */
 1350         if (ri->ri_depth == 8)
TGAWREG(dc, TGA_REG_GOPR, 0x3);
 1352         else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */
TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8));
 1355         /* Set which pixels we're drawing (of a possible 32). */
TGAWREG(dc, TGA_REG_GDAR, 0xffffffff);
 1358         /* Set drawing mode to block fill. */
TGAWREG(dc, TGA_REG_GMOR, 0x2d);
 1361         /* Insert write barrier before actually sending data */
 1362         /* XXX Abuses the fact that there is only one write barrier on Alphas */
TGAREGWB(dc, TGA_REG_GMOR, 1);
 1365         while (lines--) {
 1366                 *rp = pixels;
rp = (int32_t *)((caddr_t)rp + ri->ri_stride);
 1368         }
 1370         /* Set grapics mode back to normal. */
TGAWREG(dc, TGA_REG_GMOR, 0);
 1373 }
 1375 void
tga_erasecols (c, row, col, num, attr)
 1377         void *c;
 1378         int row, col, num;
 1379         long attr;
 1380 {
 1381         struct rasops_info *ri = c;
 1382         struct tga_devconfig *dc = ri->ri_hw;
int32_t color, lines, pixels;
 1384         int fg, bg;
int32_t *rp;
ri->ri_ops.unpack_attr(c, attr, &fg, &bg, NULL);
color = ri->ri_devcmap[bg];
rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale);
lines = ri->ri_font->fontheight;
pixels = (num * ri->ri_font->fontwidth) - 1;
 1393         /* Set fill color in block-color registers */
TGAWREG(dc, TGA_REG_GBCR0, color);
TGAWREG(dc, TGA_REG_GBCR1, color);
 1396         if (ri->ri_depth != 8) {
TGAWREG(dc, TGA_REG_GBCR2, color);
TGAWREG(dc, TGA_REG_GBCR3, color);
TGAWREG(dc, TGA_REG_GBCR4, color);
TGAWREG(dc, TGA_REG_GBCR5, color);
TGAWREG(dc, TGA_REG_GBCR6, color);
TGAWREG(dc, TGA_REG_GBCR7, color);
 1403         }
 1405         /* Set raster operation to "copy"... */
 1406         if (ri->ri_depth == 8)
TGAWREG(dc, TGA_REG_GOPR, 0x3);
 1408         else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */
TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8));
 1411         /* Set which pixels we're drawing (of a possible 32). */
TGAWREG(dc, TGA_REG_GDAR, 0xffffffff);
 1414         /* Set drawing mode to block fill. */
TGAWREG(dc, TGA_REG_GMOR, 0x2d);
 1417         /* Insert write barrier before actually sending data */
 1418         /* XXX Abuses the fact that there is only one write barrier on Alphas */
TGAREGWB(dc, TGA_REG_GMOR, 1);
 1421         while (lines--) {
 1422                 *rp = pixels;
rp = (int32_t *)((caddr_t)rp + ri->ri_stride);
 1424         }
 1426         /* Set grapics mode back to normal. */
TGAWREG(dc, TGA_REG_GMOR, 0);
 1428 }
 1431 void
tga_ramdac_wr(v, btreg, val)
 1433         void *v;
u_int btreg;
u_int8_t val;
 1436 {
 1437         struct tga_devconfig *dc = v;
 1439         if (btreg > BT485_REG_MAX)
panic("tga_ramdac_wr: reg %d out of range", btreg);
TGAWREG(dc, TGA_REG_EPDR, (btreg << 9) | (0 << 8 ) | val); /* XXX */
TGAREGWB(dc, TGA_REG_EPDR, 1);
 1444 }
 1446 void
tga2_ramdac_wr(v, btreg, val)
 1448         void *v;
u_int btreg;
u_int8_t val;
 1451 {
 1452         struct tga_devconfig *dc = v;
bus_space_handle_t ramdac;
 1455         if (btreg > BT485_REG_MAX)
panic("tga_ramdac_wr: reg %d out of range", btreg);
bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 
 1459                 (0xe << 12) + (btreg << 8), 4, &ramdac);
bus_space_write_4(dc->dc_memt, ramdac, 0, val & 0xff);
bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_WRITE);
 1462 }
u_int8_t
tga_bt463_rd(v, btreg)
 1466         void *v;
u_int btreg;
 1468 {
 1469         struct tga_devconfig *dc = v;
tga_reg_t rdval;
 1472         /* 
 1473          * Strobe CE# (high->low->high) since status and data are latched on 
 1474          * the falling and rising edges (repsectively) of this active-low signal.
 1475          */
TGAREGWB(dc, TGA_REG_EPSR, 1);
TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1);
TGAREGWB(dc, TGA_REG_EPSR, 1);
TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 0);
TGAREGRB(dc, TGA_REG_EPSR, 1);
rdval = TGARREG(dc, TGA_REG_EPDR);
TGAREGWB(dc, TGA_REG_EPSR, 1);
TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1);
 1488         return (rdval >> 16) & 0xff;
 1489 }
 1491 void
tga_bt463_wr(v, btreg, val)
 1493         void *v;
u_int btreg;
u_int8_t val;
 1496 {
 1497         struct tga_devconfig *dc = v;
 1499         /* 
 1500          * In spite of the 21030 documentation, to set the MPU bus bits for
 1501          * a write, you set them in the upper bits of EPDR, not EPSR.
 1502          */
 1504         /* 
 1505          * Strobe CE# (high->low->high) since status and data are latched on
 1506          * the falling and rising edges of this active-low signal.
 1507          */
TGAREGWB(dc, TGA_REG_EPDR, 1);
TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val);
TGAREGWB(dc, TGA_REG_EPDR, 1);
TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x000 | val);
TGAREGWB(dc, TGA_REG_EPDR, 1);
TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val);
 1516 }
u_int8_t
tga_ramdac_rd(v, btreg)
 1520         void *v;
u_int btreg;
 1522 {
 1523         struct tga_devconfig *dc = v;
tga_reg_t rdval;
 1526         if (btreg > BT485_REG_MAX)
panic("tga_ramdac_rd: reg %d out of range", btreg);
TGAWREG(dc, TGA_REG_EPSR, (btreg << 1) | 0x1); /* XXX */
TGAREGWB(dc, TGA_REG_EPSR, 1);
rdval = TGARREG(dc, TGA_REG_EPDR);
 1533         return (rdval >> 16) & 0xff;                            /* XXX */
 1534 }
u_int8_t
tga2_ramdac_rd(v, btreg)
 1538         void *v;
u_int btreg;
 1540 {
 1541         struct tga_devconfig *dc = v;
bus_space_handle_t ramdac;
u_int8_t retval;
 1545         if (btreg > BT485_REG_MAX)
panic("tga_ramdac_rd: reg %d out of range", btreg);
bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 
 1549                 (0xe << 12) + (btreg << 8), 4, &ramdac);
retval = bus_space_read_4(dc->dc_memt, ramdac, 0) & 0xff;
bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_READ);
 1552         return retval;
 1553 }
 1555 #include <dev/ic/decmonitors.c>
 1556 void tga2_ics9110_wr(
 1557         struct tga_devconfig *dc,
 1558         int dotclock
 1559 );
 1561 struct monitor *tga_getmonitor(struct tga_devconfig *dc);
 1563 void
tga2_init(dc)
 1565         struct tga_devconfig *dc;
 1566 {
 1567         struct  monitor *m = tga_getmonitor(dc);
 1570         /* Deal with the dot clocks.
 1571          */
 1572         if (dc->dc_tga_type == TGA_TYPE_POWERSTORM_4D20) {
 1573                 /* Set this up as a reference clock for the
 1574                  * ibm561's PLL.
 1575                  */
tga2_ics9110_wr(dc, 14300000);
 1577                 /* XXX Can't set up the dotclock properly, until such time
 1578                  * as the RAMDAC is configured.
 1579                  */
 1580         } else {
 1581                 /* otherwise the ics9110 is our clock. */
tga2_ics9110_wr(dc, m->dotclock);
 1583         }
 1584 #if 0
TGAWREG(dc, TGA_REG_VHCR, 
 1586              ((m->hbp / 4) << 21) |
 1587              ((m->hsync / 4) << 14) |
 1588             (((m->hfp - 4) / 4) << 9) |
 1589              ((m->cols + 4) / 4));
 1590 #else
TGAWREG(dc, TGA_REG_VHCR, 
 1592              ((m->hbp / 4) << 21) |
 1593              ((m->hsync / 4) << 14) |
 1594             (((m->hfp) / 4) << 9) |
 1595              ((m->cols) / 4));
 1596 #endif
TGAWREG(dc, TGA_REG_VVCR, 
 1598             (m->vbp << 22) |
 1599             (m->vsync << 16) |
 1600             (m->vfp << 11) |
 1601             (m->rows));
TGAWREG(dc, TGA_REG_VVBR, 1);
TGAREGRWB(dc, TGA_REG_VHCR, 3);
TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 1);
TGAREGRWB(dc, TGA_REG_VVVR, 1);
TGAWREG(dc, TGA_REG_GPMR, 0xffffffff);
TGAREGRWB(dc, TGA_REG_GPMR, 1);
 1608 }
 1610 void
tga2_ics9110_wr(dc, dotclock)
 1612         struct tga_devconfig *dc;
 1613         int dotclock;
 1614 {
bus_space_handle_t clock;
u_int32_t valU;
 1617         int N, M, R, V, X;
 1618         int i;
 1620         switch (dotclock) {
 1621         case 130808000:
N = 0x40; M = 0x7; V = 0x0; X = 0x1; R = 0x1; break;
 1623         case 119840000:
N = 0x2d; M = 0x2b; V = 0x1; X = 0x1; R = 0x1; break;
 1625         case 108180000:
N = 0x11; M = 0x9; V = 0x1; X = 0x1; R = 0x2; break;
 1627         case 103994000:
N = 0x6d; M = 0xf; V = 0x0; X = 0x1; R = 0x1; break;
 1629         case 175000000:
N = 0x5F; M = 0x3E; V = 0x1; X = 0x1; R = 0x1; break;
 1631         case  75000000:
N = 0x6e; M = 0x15; V = 0x0; X = 0x1; R = 0x1; break;
 1633         case  74000000:
N = 0x2a; M = 0x41; V = 0x1; X = 0x1; R = 0x1; break;
 1635         case  69000000:
N = 0x35; M = 0xb; V = 0x0; X = 0x1; R = 0x1; break;
 1637         case  65000000:
N = 0x6d; M = 0x0c; V = 0x0; X = 0x1; R = 0x2; break;
 1639         case  50000000:
N = 0x37; M = 0x3f; V = 0x1; X = 0x1; R = 0x2; break;
 1641         case  40000000:
N = 0x5f; M = 0x11; V = 0x0; X = 0x1; R = 0x2; break;
 1643         case  31500000:
N = 0x16; M = 0x05; V = 0x0; X = 0x1; R = 0x2; break;
 1645         case  25175000:
N = 0x66; M = 0x1d; V = 0x0; X = 0x1; R = 0x2; break;
 1647         case 135000000:
N = 0x42; M = 0x07; V = 0x0; X = 0x1; R = 0x1; break;
 1649         case 110000000:
N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break;
 1651         case 202500000:
N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break;
 1653        case  14300000:         /* this one is just a ref clock */
N = 0x03; M = 0x03; V = 0x1; X = 0x1; R = 0x3; break;
 1655         default:
panic("unrecognized clock rate %d", dotclock);
 1657         }
 1659         /* XXX -- hard coded, bad */
valU  = N | ( M << 7 ) | (V << 14);
valU |= (X << 15) | (R << 17);
valU |= 0x17 << 19;
bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV +
TGA2_MEM_CLOCK + (0xe << 12), 4, &clock); /* XXX */
 1667         for (i = 24; i > 0; i--) {
u_int32_t writeval;
writeval = valU & 0x1;
 1671                 if (i == 1)  
writeval |= 0x2; 
valU >>= 1;
bus_space_write_4(dc->dc_memt, clock, 0, writeval);
bus_space_barrier(dc->dc_memt, clock, 0, 4, BUS_SPACE_BARRIER_WRITE);
 1676         }       
bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV +
TGA2_MEM_CLOCK + (0xe << 12) + (0x1 << 11) + (0x1 << 11), 4,
 1679                 &clock); /* XXX */
bus_space_write_4(dc->dc_memt, clock, 0, 0x0);
bus_space_barrier(dc->dc_memt, clock, 0, 0, BUS_SPACE_BARRIER_WRITE);
 1682 }
 1684 struct monitor *
tga_getmonitor(dc)
 1686        struct tga_devconfig *dc;
 1687 {
 1688        return &decmonitors[(~TGARREG(dc, TGA_REG_GREV) >> 16) & 0x0f];
 1689 }
 1691 unsigned
tga_getdotclock(dc)
 1693        struct tga_devconfig *dc;
 1694 {
 1695        return tga_getmonitor(dc)->dotclock;
 1696 }