dc 107 arch/i386/stand/libsa/diskprobe.c const char *dc = (const char *)((0x40 << 4) + 0x75);
dc 110 arch/i386/stand/libsa/diskprobe.c for (i = 0x80; i < (0x80 + *dc); i++) {
dc 508 dev/isa/ega.c struct ega_config *dc;
dc 516 dev/isa/ega.c dc = &ega_console_dc;
dc 520 dev/isa/ega.c dc = malloc(sizeof(struct ega_config),
dc 524 dev/isa/ega.c ega_init(dc, ia->ia_iot, ia->ia_memt, 0);
dc 527 dev/isa/ega.c ega_init(dc, ia->ia_iot, ia->ia_memt, 1);
dc 531 dev/isa/ega.c sc->sc_dc = dc;
dc 536 dev/isa/ega.c aa.accesscookie = dc;
dc 174 dev/isa/pcdisplay.c pcdisplay_init(dc, iot, memt, mono)
dc 175 dev/isa/pcdisplay.c struct pcdisplay_config *dc;
dc 179 dev/isa/pcdisplay.c struct pcdisplay_handle *ph = &dc->dc_ph;
dc 184 dev/isa/pcdisplay.c dc->mono = mono;
dc 196 dev/isa/pcdisplay.c dc->pcs.hdl = ph;
dc 197 dev/isa/pcdisplay.c dc->pcs.type = &pcdisplay_scr;
dc 198 dev/isa/pcdisplay.c dc->pcs.active = 1;
dc 199 dev/isa/pcdisplay.c dc->pcs.mem = NULL;
dc 208 dev/isa/pcdisplay.c dc->pcs.dispoffset = 0;
dc 209 dev/isa/pcdisplay.c dc->pcs.visibleoffset = 0;
dc 211 dev/isa/pcdisplay.c dc->pcs.vc_crow = cpos / pcdisplay_scr.ncols;
dc 212 dev/isa/pcdisplay.c dc->pcs.vc_ccol = cpos % pcdisplay_scr.ncols;
dc 213 dev/isa/pcdisplay.c pcdisplay_cursor_init(&dc->pcs, 1);
dc 263 dev/isa/pcdisplay.c struct pcdisplay_config *dc;
dc 271 dev/isa/pcdisplay.c dc = &pcdisplay_console_dc;
dc 275 dev/isa/pcdisplay.c dc = malloc(sizeof(struct pcdisplay_config),
dc 279 dev/isa/pcdisplay.c pcdisplay_init(dc, ia->ia_iot, ia->ia_memt, 0);
dc 282 dev/isa/pcdisplay.c pcdisplay_init(dc, ia->ia_iot, ia->ia_memt, 1);
dc 286 dev/isa/pcdisplay.c sc->sc_dc = dc;
dc 2910 dev/pci/if_em.c sc->stats.dc += E1000_READ_REG(&sc->hw, DC);
dc 3011 dev/pci/if_em.c (long long)sc->stats.dc);
dc 1307 dev/pci/if_em_hw.h uint64_t dc;
dc 1974 dev/pci/if_ixgb.c sc->stats.dc += IXGB_READ_REG(&sc->hw, DC);
dc 2085 dev/pci/if_ixgb.c (long long)sc->stats.dc);
dc 804 dev/pci/ixgb_hw.h uint64_t dc;
dc 84 dev/pci/tga.c pcitag_t tag, struct tga_devconfig *dc);
dc 85 dev/pci/tga.c unsigned tga_getdotclock(struct tga_devconfig *dc);
dc 198 dev/pci/tga.c tga_getdevconfig(memt, pc, tag, dc)
dc 202 dev/pci/tga.c struct tga_devconfig *dc;
dc 210 dev/pci/tga.c dc->dc_memt = memt;
dc 212 dev/pci/tga.c dc->dc_pcitag = tag;
dc 218 dev/pci/tga.c &dc->dc_pcipaddr, &pcisize, NULL))
dc 223 dev/pci/tga.c if (bus_space_map(memt, dc->dc_pcipaddr, pcisize, 1, &dc->dc_memh))
dc 225 dev/pci/tga.c dc->dc_vaddr = dc->dc_memh;
dc 227 dev/pci/tga.c if (bus_space_map(memt, dc->dc_pcipaddr, pcisize,
dc 228 dev/pci/tga.c BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR, &dc->dc_memh))
dc 230 dev/pci/tga.c dc->dc_vaddr = (vaddr_t) bus_space_vaddr(memt, dc->dc_memh);
dc 235 dev/pci/tga.c dc->dc_paddr = ALPHA_K0SEG_TO_PHYS(dc->dc_vaddr); /* XXX */
dc 238 dev/pci/tga.c bus_space_paddr(memt, dc->dc_memh, &dc->dc_paddr);
dc 241 dev/pci/tga.c bus_space_subregion(dc->dc_memt, dc->dc_memh,
dc 243 dev/pci/tga.c &dc->dc_regs);
dc 246 dev/pci/tga.c dc->dc_tga_type = tga_identify(dc);
dc 249 dev/pci/tga.c tgac = dc->dc_tgaconf = tga_getconf(dc->dc_tga_type);
dc 260 dev/pci/tga.c switch (TGARREG(dc, TGA_REG_GREV) & 0xff) {
dc 265 dev/pci/tga.c dc->dc_tga2 = 0;
dc 270 dev/pci/tga.c dc->dc_tga2 = 1;
dc 276 dev/pci/tga.c if (dc->dc_tga2) {
dc 277 dev/pci/tga.c tga2_init(dc);
dc 280 dev/pci/tga.c i = TGARREG(dc, TGA_REG_VHCR) & 0x1ff;
dc 284 dev/pci/tga.c dc->dc_wid = 8192;
dc 288 dev/pci/tga.c dc->dc_wid = 8196;
dc 292 dev/pci/tga.c dc->dc_wid = (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) * 4; /* XXX */
dc 296 dev/pci/tga.c DPRINTF("tga_getdevconfig: dc->dc_wid = %d\n", dc->dc_wid);
dc 302 dev/pci/tga.c if ((TGARREG(dc, TGA_REG_VHCR) & 0x00000001) != 0 && /* XXX */
dc 303 dev/pci/tga.c (TGARREG(dc, TGA_REG_VHCR) & 0x80000000) != 0) { /* XXX */
dc 304 dev/pci/tga.c TGAWREG(dc, TGA_REG_VHCR,
dc 305 dev/pci/tga.c (TGARREG(dc, TGA_REG_VHCR) & ~0x80000001));
dc 306 dev/pci/tga.c dc->dc_wid -= 4;
dc 309 dev/pci/tga.c dc->dc_rowbytes = dc->dc_wid * (dc->dc_tgaconf->tgac_phys_depth / 8);
dc 310 dev/pci/tga.c dc->dc_ht = (TGARREG(dc, TGA_REG_VVCR) & 0x7ff); /* XXX */
dc 313 dev/pci/tga.c dc->dc_rowbytes, dc->dc_tgaconf->tgac_phys_depth,
dc 314 dev/pci/tga.c dc->dc_wid, dc->dc_ht);
dc 318 dev/pci/tga.c TGAWREG(dc, TGA_REG_CCBR, 0);
dc 319 dev/pci/tga.c TGAWREG(dc, TGA_REG_VVBR, 1);
dc 320 dev/pci/tga.c dc->dc_videobase = dc->dc_vaddr + tgac->tgac_dbuf[0] +
dc 322 dev/pci/tga.c dc->dc_blanked = 1;
dc 323 dev/pci/tga.c tga_unblank(dc);
dc 329 dev/pci/tga.c dc->dc_videobase, dc->dc_vaddr, tgac->tgac_dbuf[0],
dc 338 dev/pci/tga.c TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff);
dc 342 dev/pci/tga.c for (i = 0; i < dc->dc_ht * dc->dc_rowbytes; i += sizeof(u_int32_t))
dc 343 dev/pci/tga.c *(u_int32_t *)(dc->dc_videobase + i) = 0;
dc 347 dev/pci/tga.c rip = &dc->dc_rinfo;
dc 350 dev/pci/tga.c rip->ri_bits = (void *)dc->dc_videobase;
dc 351 dev/pci/tga.c rip->ri_width = dc->dc_wid;
dc 352 dev/pci/tga.c rip->ri_height = dc->dc_ht;
dc 353 dev/pci/tga.c rip->ri_stride = dc->dc_rowbytes;
dc 354 dev/pci/tga.c rip->ri_hw = dc;
dc 406 dev/pci/tga.c dc->dc_intrenabled = 0;
dc 572 dev/pci/tga.c struct tga_devconfig *dc = sc->sc_dc;
dc 573 dev/pci/tga.c struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs;
dc 574 dev/pci/tga.c struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie;
dc 586 dev/pci/tga.c TGAWREG(dc, TGA_REG_VVBR, 0);
dc 590 dev/pci/tga.c TGAWREG(dc, TGA_REG_VVBR, 1);
dc 651 dev/pci/tga.c struct tga_devconfig *dc = v;
dc 653 dev/pci/tga.c if (dc->dc_intrenabled) {
dc 655 dev/pci/tga.c dc->dc_ramdac_intr = f;
dc 656 dev/pci/tga.c TGAWREG(dc, TGA_REG_SISR, 0x00010000);
dc 659 dev/pci/tga.c TGAWREG(dc, TGA_REG_SISR, 0x00010001);
dc 660 dev/pci/tga.c TGAREGWB(dc, TGA_REG_SISR, 1);
dc 661 dev/pci/tga.c while ((TGARREG(dc, TGA_REG_SISR) & 0x00000001) == 0)
dc 663 dev/pci/tga.c f(dc->dc_ramdac_cookie);
dc 664 dev/pci/tga.c TGAWREG(dc, TGA_REG_SISR, 0x00000001);
dc 665 dev/pci/tga.c TGAREGWB(dc, TGA_REG_SISR, 1);
dc 675 dev/pci/tga.c struct tga_devconfig *dc = v;
dc 676 dev/pci/tga.c struct ramdac_cookie *dcrc= dc->dc_ramdac_cookie;
dc 680 dev/pci/tga.c reg = TGARREG(dc, TGA_REG_SISR);
dc 685 dev/pci/tga.c TGAWREG(dc, TGA_REG_SISR, (reg & 0x1f));
dc 686 dev/pci/tga.c TGAREGWB(dc, TGA_REG_SISR, 1);
dc 697 dev/pci/tga.c if (dc->dc_ramdac_intr) {
dc 698 dev/pci/tga.c dc->dc_ramdac_intr(dcrc);
dc 699 dev/pci/tga.c dc->dc_ramdac_intr = NULL;
dc 701 dev/pci/tga.c TGAWREG(dc, TGA_REG_SISR, 0x00000001);
dc 702 dev/pci/tga.c TGAREGWB(dc, TGA_REG_SISR, 1);
dc 713 dev/pci/tga.c struct tga_devconfig *dc = sc->sc_dc;
dc 715 dev/pci/tga.c if (offset >= dc->dc_tgaconf->tgac_cspace_size || offset < 0)
dc 722 dev/pci/tga.c offset += dc->dc_tgaconf->tgac_cspace_size / 2;
dc 845 dev/pci/tga.c tga_blank(dc)
dc 846 dev/pci/tga.c struct tga_devconfig *dc;
dc 849 dev/pci/tga.c if (!dc->dc_blanked) {
dc 850 dev/pci/tga.c dc->dc_blanked = 1;
dc 852 dev/pci/tga.c TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | VVR_BLANK);
dc 857 dev/pci/tga.c tga_unblank(dc)
dc 858 dev/pci/tga.c struct tga_devconfig *dc;
dc 861 dev/pci/tga.c if (dc->dc_blanked) {
dc 862 dev/pci/tga.c dc->dc_blanked = 0;
dc 864 dev/pci/tga.c TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~VVR_BLANK);
dc 872 dev/pci/tga.c tga_builtin_set_cursor(dc, cursorp)
dc 873 dev/pci/tga.c struct tga_devconfig *dc;
dc 876 dev/pci/tga.c struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs;
dc 877 dev/pci/tga.c struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie;
dc 899 dev/pci/tga.c TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 0x04);
dc 902 dev/pci/tga.c TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~0x04);
dc 905 dev/pci/tga.c TGAWREG(dc, TGA_REG_CXYR,
dc 915 dev/pci/tga.c TGAWREG(dc, TGA_REG_CCBR,
dc 916 dev/pci/tga.c (TGARREG(dc, TGA_REG_CCBR) & ~0xfc00) | (cursorp->size.y << 10));
dc 917 dev/pci/tga.c if ((error = copyin(cursorp->image,(char *)(dc->dc_vaddr +
dc 918 dev/pci/tga.c (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), count)) != 0)
dc 925 dev/pci/tga.c tga_builtin_get_cursor(dc, cursorp)
dc 926 dev/pci/tga.c struct tga_devconfig *dc;
dc 929 dev/pci/tga.c struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs;
dc 930 dev/pci/tga.c struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie;
dc 936 dev/pci/tga.c cursorp->enable = (TGARREG(dc, TGA_REG_VVVR) & 0x04) != 0;
dc 937 dev/pci/tga.c cursorp->pos.x = TGARREG(dc, TGA_REG_CXYR) & 0xfff;
dc 938 dev/pci/tga.c cursorp->pos.y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff;
dc 940 dev/pci/tga.c cursorp->size.y = (TGARREG(dc, TGA_REG_CCBR) >> 10) & 0x3f;
dc 944 dev/pci/tga.c error = copyout((char *)(dc->dc_vaddr +
dc 945 dev/pci/tga.c (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)),
dc 956 dev/pci/tga.c tga_builtin_set_curpos(dc, curposp)
dc 957 dev/pci/tga.c struct tga_devconfig *dc;
dc 961 dev/pci/tga.c TGAWREG(dc, TGA_REG_CXYR,
dc 967 dev/pci/tga.c tga_builtin_get_curpos(dc, curposp)
dc 968 dev/pci/tga.c struct tga_devconfig *dc;
dc 972 dev/pci/tga.c curposp->x = TGARREG(dc, TGA_REG_CXYR) & 0xfff;
dc 973 dev/pci/tga.c curposp->y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff;
dc 978 dev/pci/tga.c tga_builtin_get_curmax(dc, curposp)
dc 979 dev/pci/tga.c struct tga_devconfig *dc;
dc 1090 dev/pci/tga.c struct tga_devconfig *dc = (struct tga_devconfig *)dst->ri_hw;
dc 1096 dev/pci/tga.c int offset = 1 * dc->dc_tgaconf->tgac_vvbr_units;
dc 1143 dev/pci/tga.c TGAWALREG(dc, TGA_REG_GMOR, 3, 0x0007); /* Copy mode */
dc 1144 dev/pci/tga.c TGAWALREG(dc, TGA_REG_GOPR, 3, 0x0003); /* SRC */
dc 1168 dev/pci/tga.c TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64);
dc 1169 dev/pci/tga.c TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64);
dc 1170 dev/pci/tga.c TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x + 1 * 64);
dc 1171 dev/pci/tga.c TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x + 1 * 64);
dc 1172 dev/pci/tga.c TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x + 2 * 64);
dc 1173 dev/pci/tga.c TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x + 2 * 64);
dc 1174 dev/pci/tga.c TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x + 3 * 64);
dc 1175 dev/pci/tga.c TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x + 3 * 64);
dc 1181 dev/pci/tga.c TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64);
dc 1182 dev/pci/tga.c TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64);
dc 1187 dev/pci/tga.c TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */
dc 1188 dev/pci/tga.c TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */
dc 1215 dev/pci/tga.c TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 3 * 64);
dc 1216 dev/pci/tga.c TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 3 * 64);
dc 1217 dev/pci/tga.c TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x + 2 * 64);
dc 1218 dev/pci/tga.c TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x + 2 * 64);
dc 1219 dev/pci/tga.c TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x + 1 * 64);
dc 1220 dev/pci/tga.c TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x + 1 * 64);
dc 1221 dev/pci/tga.c TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x + 0 * 64);
dc 1222 dev/pci/tga.c TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x + 0 * 64);
dc 1230 dev/pci/tga.c TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64);
dc 1231 dev/pci/tga.c TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64);
dc 1236 dev/pci/tga.c TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */
dc 1237 dev/pci/tga.c TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */
dc 1261 dev/pci/tga.c struct tga_devconfig *dc = ri->ri_hw;
dc 1281 dev/pci/tga.c TGAWREG(dc, TGA_REG_GFGR, ri->ri_devcmap[fg]);
dc 1282 dev/pci/tga.c TGAWREG(dc, TGA_REG_GBGR, ri->ri_devcmap[bg]);
dc 1286 dev/pci/tga.c TGAWREG(dc, TGA_REG_GOPR, 0x3);
dc 1288 dev/pci/tga.c TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8));
dc 1291 dev/pci/tga.c TGAWREG(dc, TGA_REG_GPXR_P, (1 << width) - 1);
dc 1294 dev/pci/tga.c TGAWREG(dc, TGA_REG_GMOR, 0x1);
dc 1298 dev/pci/tga.c TGAREGWB(dc, TGA_REG_GMOR, 1);
dc 1315 dev/pci/tga.c TGAWREG(dc, TGA_REG_GMOR, 0);
dc 1316 dev/pci/tga.c TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff);
dc 1326 dev/pci/tga.c struct tga_devconfig *dc = ri->ri_hw;
dc 1338 dev/pci/tga.c TGAWREG(dc, TGA_REG_GBCR0, color);
dc 1339 dev/pci/tga.c TGAWREG(dc, TGA_REG_GBCR1, color);
dc 1341 dev/pci/tga.c TGAWREG(dc, TGA_REG_GBCR2, color);
dc 1342 dev/pci/tga.c TGAWREG(dc, TGA_REG_GBCR3, color);
dc 1343 dev/pci/tga.c TGAWREG(dc, TGA_REG_GBCR4, color);
dc 1344 dev/pci/tga.c TGAWREG(dc, TGA_REG_GBCR5, color);
dc 1345 dev/pci/tga.c TGAWREG(dc, TGA_REG_GBCR6, color);
dc 1346 dev/pci/tga.c TGAWREG(dc, TGA_REG_GBCR7, color);
dc 1351 dev/pci/tga.c TGAWREG(dc, TGA_REG_GOPR, 0x3);
dc 1353 dev/pci/tga.c TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8));
dc 1356 dev/pci/tga.c TGAWREG(dc, TGA_REG_GDAR, 0xffffffff);
dc 1359 dev/pci/tga.c TGAWREG(dc, TGA_REG_GMOR, 0x2d);
dc 1363 dev/pci/tga.c TGAREGWB(dc, TGA_REG_GMOR, 1);
dc 1371 dev/pci/tga.c TGAWREG(dc, TGA_REG_GMOR, 0);
dc 1382 dev/pci/tga.c struct tga_devconfig *dc = ri->ri_hw;
dc 1394 dev/pci/tga.c TGAWREG(dc, TGA_REG_GBCR0, color);
dc 1395 dev/pci/tga.c TGAWREG(dc, TGA_REG_GBCR1, color);
dc 1397 dev/pci/tga.c TGAWREG(dc, TGA_REG_GBCR2, color);
dc 1398 dev/pci/tga.c TGAWREG(dc, TGA_REG_GBCR3, color);
dc 1399 dev/pci/tga.c TGAWREG(dc, TGA_REG_GBCR4, color);
dc 1400 dev/pci/tga.c TGAWREG(dc, TGA_REG_GBCR5, color);
dc 1401 dev/pci/tga.c TGAWREG(dc, TGA_REG_GBCR6, color);
dc 1402 dev/pci/tga.c TGAWREG(dc, TGA_REG_GBCR7, color);
dc 1407 dev/pci/tga.c TGAWREG(dc, TGA_REG_GOPR, 0x3);
dc 1409 dev/pci/tga.c TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8));
dc 1412 dev/pci/tga.c TGAWREG(dc, TGA_REG_GDAR, 0xffffffff);
dc 1415 dev/pci/tga.c TGAWREG(dc, TGA_REG_GMOR, 0x2d);
dc 1419 dev/pci/tga.c TGAREGWB(dc, TGA_REG_GMOR, 1);
dc 1427 dev/pci/tga.c TGAWREG(dc, TGA_REG_GMOR, 0);
dc 1437 dev/pci/tga.c struct tga_devconfig *dc = v;
dc 1442 dev/pci/tga.c TGAWREG(dc, TGA_REG_EPDR, (btreg << 9) | (0 << 8 ) | val); /* XXX */
dc 1443 dev/pci/tga.c TGAREGWB(dc, TGA_REG_EPDR, 1);
dc 1452 dev/pci/tga.c struct tga_devconfig *dc = v;
dc 1458 dev/pci/tga.c bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC +
dc 1460 dev/pci/tga.c bus_space_write_4(dc->dc_memt, ramdac, 0, val & 0xff);
dc 1461 dev/pci/tga.c bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_WRITE);
dc 1469 dev/pci/tga.c struct tga_devconfig *dc = v;
dc 1477 dev/pci/tga.c TGAREGWB(dc, TGA_REG_EPSR, 1);
dc 1478 dev/pci/tga.c TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1);
dc 1479 dev/pci/tga.c TGAREGWB(dc, TGA_REG_EPSR, 1);
dc 1480 dev/pci/tga.c TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 0);
dc 1482 dev/pci/tga.c TGAREGRB(dc, TGA_REG_EPSR, 1);
dc 1484 dev/pci/tga.c rdval = TGARREG(dc, TGA_REG_EPDR);
dc 1485 dev/pci/tga.c TGAREGWB(dc, TGA_REG_EPSR, 1);
dc 1486 dev/pci/tga.c TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1);
dc 1497 dev/pci/tga.c struct tga_devconfig *dc = v;
dc 1509 dev/pci/tga.c TGAREGWB(dc, TGA_REG_EPDR, 1);
dc 1510 dev/pci/tga.c TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val);
dc 1511 dev/pci/tga.c TGAREGWB(dc, TGA_REG_EPDR, 1);
dc 1512 dev/pci/tga.c TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x000 | val);
dc 1513 dev/pci/tga.c TGAREGWB(dc, TGA_REG_EPDR, 1);
dc 1514 dev/pci/tga.c TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val);
dc 1523 dev/pci/tga.c struct tga_devconfig *dc = v;
dc 1529 dev/pci/tga.c TGAWREG(dc, TGA_REG_EPSR, (btreg << 1) | 0x1); /* XXX */
dc 1530 dev/pci/tga.c TGAREGWB(dc, TGA_REG_EPSR, 1);
dc 1532 dev/pci/tga.c rdval = TGARREG(dc, TGA_REG_EPDR);
dc 1541 dev/pci/tga.c struct tga_devconfig *dc = v;
dc 1548 dev/pci/tga.c bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC +
dc 1550 dev/pci/tga.c retval = bus_space_read_4(dc->dc_memt, ramdac, 0) & 0xff;
dc 1551 dev/pci/tga.c bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_READ);
dc 1557 dev/pci/tga.c struct tga_devconfig *dc,
dc 1561 dev/pci/tga.c struct monitor *tga_getmonitor(struct tga_devconfig *dc);
dc 1564 dev/pci/tga.c tga2_init(dc)
dc 1565 dev/pci/tga.c struct tga_devconfig *dc;
dc 1567 dev/pci/tga.c struct monitor *m = tga_getmonitor(dc);
dc 1572 dev/pci/tga.c if (dc->dc_tga_type == TGA_TYPE_POWERSTORM_4D20) {
dc 1576 dev/pci/tga.c tga2_ics9110_wr(dc, 14300000);
dc 1582 dev/pci/tga.c tga2_ics9110_wr(dc, m->dotclock);
dc 1585 dev/pci/tga.c TGAWREG(dc, TGA_REG_VHCR,
dc 1591 dev/pci/tga.c TGAWREG(dc, TGA_REG_VHCR,
dc 1597 dev/pci/tga.c TGAWREG(dc, TGA_REG_VVCR,
dc 1602 dev/pci/tga.c TGAWREG(dc, TGA_REG_VVBR, 1);
dc 1603 dev/pci/tga.c TGAREGRWB(dc, TGA_REG_VHCR, 3);
dc 1604 dev/pci/tga.c TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 1);
dc 1605 dev/pci/tga.c TGAREGRWB(dc, TGA_REG_VVVR, 1);
dc 1606 dev/pci/tga.c TGAWREG(dc, TGA_REG_GPMR, 0xffffffff);
dc 1607 dev/pci/tga.c TGAREGRWB(dc, TGA_REG_GPMR, 1);
dc 1611 dev/pci/tga.c tga2_ics9110_wr(dc, dotclock)
dc 1612 dev/pci/tga.c struct tga_devconfig *dc;
dc 1664 dev/pci/tga.c bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV +
dc 1674 dev/pci/tga.c bus_space_write_4(dc->dc_memt, clock, 0, writeval);
dc 1675 dev/pci/tga.c bus_space_barrier(dc->dc_memt, clock, 0, 4, BUS_SPACE_BARRIER_WRITE);
dc 1677 dev/pci/tga.c bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV +
dc 1680 dev/pci/tga.c bus_space_write_4(dc->dc_memt, clock, 0, 0x0);
dc 1681 dev/pci/tga.c bus_space_barrier(dc->dc_memt, clock, 0, 0, BUS_SPACE_BARRIER_WRITE);
dc 1685 dev/pci/tga.c tga_getmonitor(dc)
dc 1686 dev/pci/tga.c struct tga_devconfig *dc;
dc 1688 dev/pci/tga.c return &decmonitors[(~TGARREG(dc, TGA_REG_GREV) >> 16) & 0x0f];
dc 1692 dev/pci/tga.c tga_getdotclock(dc)
dc 1693 dev/pci/tga.c struct tga_devconfig *dc;
dc 1695 dev/pci/tga.c return tga_getmonitor(dc)->dotclock;
dc 135 dev/pci/tga_conf.c tga_identify(dc)
dc 136 dev/pci/tga_conf.c struct tga_devconfig *dc;
dc 144 dev/pci/tga_conf.c gder = TGARREG(dc, TGA_REG_GDER);
dc 145 dev/pci/tga_conf.c grev = TGARREG(dc, TGA_REG_GREV);
dc 140 dev/pci/tgavar.h #define TGARREG(dc,reg) (bus_space_read_4((dc)->dc_memt, (dc)->dc_regs, \
dc 144 dev/pci/tgavar.h #define TGAWREG(dc,reg,val) bus_space_write_4((dc)->dc_memt, (dc)->dc_regs, \
dc 148 dev/pci/tgavar.h #define TGAWALREG(dc,reg,alias,val) bus_space_write_4( \
dc 149 dev/pci/tgavar.h (dc)->dc_memt, (dc)->dc_regs, \
dc 154 dev/pci/tgavar.h #define TGAREGWB(dc,reg, nregs) bus_space_barrier( \
dc 155 dev/pci/tgavar.h (dc)->dc_memt, (dc)->dc_regs, \
dc 159 dev/pci/tgavar.h #define TGAREGRB(dc,reg, nregs) bus_space_barrier( \
dc 160 dev/pci/tgavar.h (dc)->dc_memt, (dc)->dc_regs, \
dc 164 dev/pci/tgavar.h #define TGAREGRWB(dc,reg, nregs) bus_space_barrier( \
dc 165 dev/pci/tgavar.h (dc)->dc_memt, (dc)->dc_regs, \
dc 2054 dev/wscons/wsdisplay.c struct wsscreen_internal *dc;
dc 2065 dev/wscons/wsdisplay.c dc = &wsdisplay_console_conf;
dc 2069 dev/wscons/wsdisplay.c (*dc->wsemul->output)(dc->wsemulcookie, &c, 1, 1);
dc 337 dev/wscons/wsemul_vt100.c u_int *ct, dc;
dc 356 dev/wscons/wsemul_vt100.c dc = (ct ? ct[c] : c);
dc 362 dev/wscons/wsemul_vt100.c edp->ccol << edp->dw, dc,
dc 651 kern/subr_autoconf.c struct deferred_config *dc;
dc 657 kern/subr_autoconf.c for (dc = TAILQ_FIRST(&deferred_config_queue); dc != NULL;
dc 658 kern/subr_autoconf.c dc = TAILQ_NEXT(dc, dc_queue)) {
dc 659 kern/subr_autoconf.c if (dc->dc_dev == dev)
dc 664 kern/subr_autoconf.c if ((dc = malloc(sizeof(*dc), M_DEVBUF, M_NOWAIT)) == NULL)
dc 667 kern/subr_autoconf.c dc->dc_dev = dev;
dc 668 kern/subr_autoconf.c dc->dc_func = func;
dc 669 kern/subr_autoconf.c TAILQ_INSERT_TAIL(&deferred_config_queue, dc, dc_queue);
dc 679 kern/subr_autoconf.c struct deferred_config *dc, *ndc;
dc 681 kern/subr_autoconf.c for (dc = TAILQ_FIRST(&deferred_config_queue);
dc 682 kern/subr_autoconf.c dc != NULL; dc = ndc) {
dc 683 kern/subr_autoconf.c ndc = TAILQ_NEXT(dc, dc_queue);
dc 684 kern/subr_autoconf.c if (dc->dc_dev->dv_parent == parent) {
dc 685 kern/subr_autoconf.c TAILQ_REMOVE(&deferred_config_queue, dc, dc_queue);
dc 686 kern/subr_autoconf.c (*dc->dc_func)(dc->dc_dev);
dc 687 kern/subr_autoconf.c free(dc, M_DEVBUF);