root/dev/pci/if_ixgb.c

DEFINITIONS

1. ixgb_probe
2. ixgb_attach
3. ixgb_power
4. ixgb_shutdown
5. ixgb_start
6. ixgb_ioctl
7. ixgb_watchdog
8. ixgb_init
9. ixgb_intr
10. ixgb_media_status
11. ixgb_media_change
12. ixgb_encap
13. ixgb_set_promisc
14. ixgb_set_multi
15. ixgb_local_timer
16. ixgb_update_link_status
17. ixgb_stop
18. ixgb_identify_hardware
19. ixgb_allocate_pci_resources
20. ixgb_free_pci_resources
21. ixgb_hardware_init
22. ixgb_setup_interface
23. ixgb_dma_malloc
24. ixgb_dma_free
25. ixgb_allocate_transmit_structures
26. ixgb_setup_transmit_structures
27. ixgb_initialize_transmit_unit
28. ixgb_free_transmit_structures
29. ixgb_transmit_checksum_setup
30. ixgb_txeof
31. ixgb_get_buf
32. ixgb_allocate_receive_structures
33. ixgb_setup_receive_structures
34. ixgb_initialize_receive_unit
35. ixgb_free_receive_structures
36. ixgb_rxeof
37. ixgb_receive_checksum
38. ixgb_enable_intr
39. ixgb_disable_intr
40. ixgb_write_pci_cfg
41. ixgb_update_stats_counters
42. ixgb_print_hw_stats

    1 /**************************************************************************
    2 
    3 Copyright (c) 2001-2005, Intel Corporation
    4 All rights reserved.
    5 
    6 Redistribution and use in source and binary forms, with or without
    7 modification, are permitted provided that the following conditions are met:
    8 
    9  1. Redistributions of source code must retain the above copyright notice,
   10     this list of conditions and the following disclaimer.
   11 
   12  2. Redistributions in binary form must reproduce the above copyright
   13     notice, this list of conditions and the following disclaimer in the
   14     documentation and/or other materials provided with the distribution.
   15 
   16  3. Neither the name of the Intel Corporation nor the names of its
   17     contributors may be used to endorse or promote products derived from
   18     this software without specific prior written permission.
   19 
   20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
   24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   30 POSSIBILITY OF SUCH DAMAGE.
   31 
   32 ***************************************************************************/
   34 /* $OpenBSD: if_ixgb.c,v 1.36 2006/12/04 14:35:20 reyk Exp $ */
   36 #include <dev/pci/if_ixgb.h>
   38 /*********************************************************************
   39  *  Set this to one to display debug statistics
   40  *********************************************************************/
   41 int             ixgb_display_debug_stats = 0;
   43 /*********************************************************************
   44  *  Driver version
   45  *********************************************************************/
   47 char ixgb_driver_version[] = "6.1.0";
   49 /*********************************************************************
   50  *  PCI Device ID Table
   51  *********************************************************************/
   53 const struct pci_matchid ixgb_devices[] = {
   54         { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82597EX },
   55         { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82597EX_SR },
   56         { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82597EX_LR },
   57         { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82597EX_CX4 },
   58 };
   60 /*********************************************************************
   61  *  Function prototypes
   62  *********************************************************************/
   63 int  ixgb_probe(struct device *, void *, void *);
   64 void ixgb_attach(struct device *, struct device *, void *);
   65 void ixgb_shutdown(void *);
   66 int  ixgb_intr(void *);
   67 void ixgb_power(int, void *);
   68 void ixgb_start(struct ifnet *);
   69 int  ixgb_ioctl(struct ifnet *, u_long, caddr_t);
   70 void ixgb_watchdog(struct ifnet *);
   71 void ixgb_init(void *);
   72 void ixgb_stop(void *);
   73 void ixgb_media_status(struct ifnet *, struct ifmediareq *);
   74 int  ixgb_media_change(struct ifnet *);
   75 void ixgb_identify_hardware(struct ixgb_softc *);
   76 int  ixgb_allocate_pci_resources(struct ixgb_softc *);
   77 void ixgb_free_pci_resources(struct ixgb_softc *);
   78 void ixgb_local_timer(void *);
   79 int  ixgb_hardware_init(struct ixgb_softc *);
   80 void ixgb_setup_interface(struct ixgb_softc *);
   81 int  ixgb_setup_transmit_structures(struct ixgb_softc *);
   82 void ixgb_initialize_transmit_unit(struct ixgb_softc *);
   83 int  ixgb_setup_receive_structures(struct ixgb_softc *);
   84 void ixgb_initialize_receive_unit(struct ixgb_softc *);
   85 void ixgb_enable_intr(struct ixgb_softc *);
   86 void ixgb_disable_intr(struct ixgb_softc *);
   87 void ixgb_free_transmit_structures(struct ixgb_softc *);
   88 void ixgb_free_receive_structures(struct ixgb_softc *);
   89 void ixgb_update_stats_counters(struct ixgb_softc *);
   90 void ixgb_txeof(struct ixgb_softc *);
   91 int  ixgb_allocate_receive_structures(struct ixgb_softc *);
   92 int  ixgb_allocate_transmit_structures(struct ixgb_softc *);
   93 void ixgb_rxeof(struct ixgb_softc *, int);
   94 void
ixgb_receive_checksum(struct ixgb_softc *,
   96                       struct ixgb_rx_desc * rx_desc,
   97                       struct mbuf *);
   98 void
ixgb_transmit_checksum_setup(struct ixgb_softc *,
  100                              struct mbuf *,
u_int8_t *);
  102 void ixgb_set_promisc(struct ixgb_softc *);
  103 void ixgb_set_multi(struct ixgb_softc *);
  104 void ixgb_print_hw_stats(struct ixgb_softc *);
  105 void ixgb_update_link_status(struct ixgb_softc *);
  106 int
ixgb_get_buf(struct ixgb_softc *, int i,
  108              struct mbuf *);
  109 int  ixgb_encap(struct ixgb_softc *, struct mbuf *);
  110 int
ixgb_dma_malloc(struct ixgb_softc *, bus_size_t,
  112                 struct ixgb_dma_alloc *, int);
  113 void ixgb_dma_free(struct ixgb_softc *, struct ixgb_dma_alloc *);
  115 /*********************************************************************
  116  *  OpenBSD Device Interface Entry Points
  117  *********************************************************************/
  119 struct cfattach ixgb_ca = {
  120         sizeof(struct ixgb_softc), ixgb_probe, ixgb_attach
  121 };
  123 struct cfdriver ixgb_cd = {
  124         0, "ixgb", DV_IFNET
  125 };
  127 /* some defines for controlling descriptor fetches in h/w */
  128 #define RXDCTL_PTHRESH_DEFAULT 0        /* chip considers prefech below this */
  129 #define RXDCTL_HTHRESH_DEFAULT 0        /* chip will only prefetch if tail is
  130                                          * pushed this many descriptors from
  131                                          * head */
  132 #define RXDCTL_WTHRESH_DEFAULT 0        /* chip writes back at this many or RXT0 */
  135 /*********************************************************************
  136  *  Device identification routine
  137  *
  138  *  ixgb_probe determines if the driver should be loaded on
  139  *  adapter based on PCI vendor/device id of the adapter.
  140  *
  141  *  return 0 on no match, positive on match
  142  *********************************************************************/
  144 int
ixgb_probe(struct device *parent, void *match, void *aux)
  146 {
INIT_DEBUGOUT("ixgb_probe: begin");
  149         return (pci_matchbyid((struct pci_attach_args *)aux, ixgb_devices,
  150             sizeof(ixgb_devices)/sizeof(ixgb_devices[0])));
  151 }
  153 /*********************************************************************
  154  *  Device initialization routine
  155  *
  156  *  The attach entry point is called when the driver is being loaded.
  157  *  This routine identifies the type of hardware, allocates all resources
  158  *  and initializes the hardware.
  159  *
  160  *********************************************************************/
  162 void
ixgb_attach(struct device *parent, struct device *self, void *aux)
  164 {
  165         struct pci_attach_args *pa = aux;
  166         struct ixgb_softc *sc;
  167         int             tsize, rsize;
INIT_DEBUGOUT("ixgb_attach: begin");
sc = (struct ixgb_softc *)self;
sc->osdep.ixgb_pa = *pa;
timeout_set(&sc->timer_handle, ixgb_local_timer, sc);
  176         /* Determine hardware revision */
ixgb_identify_hardware(sc);
  179         /* Parameters (to be read from user) */
sc->num_tx_desc = IXGB_MAX_TXD;
sc->num_rx_desc = IXGB_MAX_RXD;
sc->tx_int_delay = TIDV;
sc->rx_int_delay = RDTR;
sc->rx_buffer_len = IXGB_RXBUFFER_2048;
  186         /*
  187          * These parameters control the automatic generation(Tx) and
  188          * response(Rx) to Ethernet PAUSE frames.
  189          */
sc->hw.fc.high_water = FCRTH;
sc->hw.fc.low_water = FCRTL;
sc->hw.fc.pause_time = FCPAUSE;
sc->hw.fc.send_xon = TRUE;
sc->hw.fc.type = FLOW_CONTROL;
  196         /* Set the max frame size assuming standard ethernet sized frames */
sc->hw.max_frame_size = IXGB_MAX_JUMBO_FRAME_SIZE;
  199         if (ixgb_allocate_pci_resources(sc)) {
printf("%s: Allocation of PCI resources failed\n",
sc->sc_dv.dv_xname);
  202                 goto err_pci;
  203         }
tsize = IXGB_ROUNDUP(sc->num_tx_desc * sizeof(struct ixgb_tx_desc),
IXGB_MAX_TXD * sizeof(struct ixgb_tx_desc));
tsize = IXGB_ROUNDUP(tsize, PAGE_SIZE);
  209         /* Allocate Transmit Descriptor ring */
  210         if (ixgb_dma_malloc(sc, tsize, &sc->txdma, BUS_DMA_NOWAIT)) {
printf("%s: Unable to allocate TxDescriptor memory\n",
sc->sc_dv.dv_xname);
  213                 goto err_tx_desc;
  214         }
sc->tx_desc_base = (struct ixgb_tx_desc *) sc->txdma.dma_vaddr;
rsize = IXGB_ROUNDUP(sc->num_rx_desc * sizeof(struct ixgb_rx_desc),
IXGB_MAX_RXD * sizeof(struct ixgb_rx_desc));
rsize = IXGB_ROUNDUP(rsize, PAGE_SIZE);
  221         /* Allocate Receive Descriptor ring */
  222         if (ixgb_dma_malloc(sc, rsize, &sc->rxdma, BUS_DMA_NOWAIT)) {
printf("%s: Unable to allocate rx_desc memory\n",
sc->sc_dv.dv_xname);
  225                 goto err_rx_desc;
  226         }
sc->rx_desc_base = (struct ixgb_rx_desc *) sc->rxdma.dma_vaddr;
  229         /* Initialize the hardware */
  230         if (ixgb_hardware_init(sc)) {
printf("%s: Unable to initialize the hardware\n",
sc->sc_dv.dv_xname);
  233                 goto err_hw_init;
  234         }
  236         /* Setup OS specific network interface */
ixgb_setup_interface(sc);
  239         /* Initialize statistics */
ixgb_clear_hw_cntrs(&sc->hw);
ixgb_update_stats_counters(sc);
ixgb_update_link_status(sc);
printf(", address %s\n", ether_sprintf(sc->interface_data.ac_enaddr));
INIT_DEBUGOUT("ixgb_attach: end");
sc->sc_powerhook = powerhook_establish(ixgb_power, sc);
sc->sc_shutdownhook = shutdownhook_establish(ixgb_shutdown, sc);
  249         return;
err_hw_init:
ixgb_dma_free(sc, &sc->rxdma);
err_rx_desc:
ixgb_dma_free(sc, &sc->txdma);
err_tx_desc:
err_pci:
ixgb_free_pci_resources(sc);
  258 }
  260 void
ixgb_power(int why, void *arg)
  262 {
  263         struct ixgb_softc *sc = (struct ixgb_softc *)arg;
  264         struct ifnet *ifp;
  266         if (why == PWR_RESUME) {
ifp = &sc->interface_data.ac_if;
  268                 if (ifp->if_flags & IFF_UP)
ixgb_init(sc);
  270         }
  271 }
  273 /*********************************************************************
  274  *
  275  *  Shutdown entry point
  276  *
  277  **********************************************************************/ 
  279 void
ixgb_shutdown(void *arg)
  281 {
  282         struct ixgb_softc *sc = arg;
ixgb_stop(sc);
  285 }
  287 /*********************************************************************
  288  *  Transmit entry point
  289  *
  290  *  ixgb_start is called by the stack to initiate a transmit.
  291  *  The driver will remain in this routine as long as there are
  292  *  packets to transmit and transmit resources are available.
  293  *  In case resources are not available stack is notified and
  294  *  the packet is requeued.
  295  **********************************************************************/
  297 void
ixgb_start(struct ifnet *ifp)
  299 {
  300         struct mbuf    *m_head;
  301         struct ixgb_softc *sc = ifp->if_softc;
  303         if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
  304                 return;
  306         if (!sc->link_active)
  307                 return;
  309         for (;;) {
IFQ_POLL(&ifp->if_snd, m_head);
  312                 if (m_head == NULL)
  313                         break;
  315                 if (ixgb_encap(sc, m_head)) {
ifp->if_flags |= IFF_OACTIVE;
  317                         break;
  318                 }
IFQ_DEQUEUE(&ifp->if_snd, m_head);
  322 #if NBPFILTER > 0
  323                 /* Send a copy of the frame to the BPF listener */
  324                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT);
  326 #endif
  328                 /* Set timeout in case hardware has problems transmitting */
ifp->if_timer = IXGB_TX_TIMEOUT;
  330         }
  331 }
  333 /*********************************************************************
  334  *  Ioctl entry point
  335  *
  336  *  ixgb_ioctl is called when the user wants to configure the
  337  *  interface.
  338  *
  339  *  return 0 on success, positive on failure
  340  **********************************************************************/
  342 int
ixgb_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
  344 {
  345         int             s, error = 0;
  346         struct ifreq   *ifr = (struct ifreq *) data;
  347         struct ifaddr  *ifa = (struct ifaddr *)data;
  348         struct ixgb_softc *sc = ifp->if_softc;
s = splnet();
  352         if ((error = ether_ioctl(ifp, &sc->interface_data, command, data)) > 0) {
splx(s);
  354                 return (error);
  355         }
  357         switch (command) {
  358         case SIOCSIFADDR:
IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFADDR (Set Interface "
  360                                "Addr)");
ifp->if_flags |= IFF_UP;
  362                 if (!(ifp->if_flags & IFF_RUNNING))
ixgb_init(sc);
  364 #ifdef INET
  365                 if (ifa->ifa_addr->sa_family == AF_INET)
arp_ifinit(&sc->interface_data, ifa);
  367 #endif /* INET */
  368                 break;
  369         case SIOCSIFMTU:
IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
  371                 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ifp->if_hardmtu)
error = EINVAL;
  373                 else if (ifp->if_mtu != ifr->ifr_mtu)
ifp->if_mtu = ifr->ifr_mtu;
  375                 break;
  376         case SIOCSIFFLAGS:
IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFFLAGS (Set Interface Flags)");
  378                 if (ifp->if_flags & IFF_UP) {
  379                         /*
  380                          * If only the PROMISC or ALLMULTI flag changes, then
  381                          * don't do a full re-init of the chip, just update
  382                          * the Rx filter.
  383                          */
  384                         if ((ifp->if_flags & IFF_RUNNING) &&
  385                             ((ifp->if_flags ^ sc->if_flags) &
  386                              (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
ixgb_set_promisc(sc);
  388                         } else {
  389                                 if (!(ifp->if_flags & IFF_RUNNING))
ixgb_init(sc);
  391                         }
  392                 } else {
  393                         if (ifp->if_flags & IFF_RUNNING)
ixgb_stop(sc);
  395                 }
sc->if_flags = ifp->if_flags;
  397                 break;
  398         case SIOCADDMULTI:
  399         case SIOCDELMULTI:
IOCTL_DEBUGOUT("ioctl rcv'd: SIOC(ADD|DEL)MULTI");
error = (command == SIOCADDMULTI)
  402                         ? ether_addmulti(ifr, &sc->interface_data)
  403                         : ether_delmulti(ifr, &sc->interface_data);
  405                 if (error == ENETRESET) {
  406                         if (ifp->if_flags & IFF_RUNNING) {
ixgb_disable_intr(sc);
ixgb_set_multi(sc);
ixgb_enable_intr(sc);
  410                         }
error = 0;
  412                 }
  413                 break;
  414         case SIOCSIFMEDIA:
  415         case SIOCGIFMEDIA:
IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFMEDIA (Get/Set Interface Media)");
error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
  418                 break;
  419         default:
IOCTL_DEBUGOUT1("ioctl received: UNKNOWN (0x%X)\n", (int)command);
error = ENOTTY;
  422         }
splx(s);
  425         return (error);
  426 }
  428 /*********************************************************************
  429  *  Watchdog entry point
  430  *
  431  *  This routine is called whenever hardware quits transmitting.
  432  *
  433  **********************************************************************/
  435 void
ixgb_watchdog(struct ifnet * ifp)
  437 {
  438         struct ixgb_softc *sc = ifp->if_softc;
  440         /*
  441          * If we are in this routine because of pause frames, then don't
  442          * reset the hardware.
  443          */
  444         if (IXGB_READ_REG(&sc->hw, STATUS) & IXGB_STATUS_TXOFF) {
ifp->if_timer = IXGB_TX_TIMEOUT;
  446                 return;
  447         }
printf("%s: watchdog timeout -- resetting\n", sc->sc_dv.dv_xname);
ixgb_init(sc);
sc->watchdog_events++;
  454 }
  456 /*********************************************************************
  457  *  Init entry point
  458  *
  459  *  This routine is used in two ways. It is used by the stack as
  460  *  init entry point in network interface structure. It is also used
  461  *  by the driver as a hw/sw initialization routine to get to a
  462  *  consistent state.
  463  *
  464  **********************************************************************/
  466 void
ixgb_init(void *arg)
  468 {
  469         struct ixgb_softc *sc = arg;
  470         struct ifnet   *ifp = &sc->interface_data.ac_if;
uint32_t temp_reg;
  472         int s;
INIT_DEBUGOUT("ixgb_init: begin");
s = splnet();
ixgb_stop(sc);
  480         /* Get the latest mac address, User can use a LAA */
bcopy(sc->interface_data.ac_enaddr, sc->hw.curr_mac_addr,
IXGB_ETH_LENGTH_OF_ADDRESS);
  484         /* Initialize the hardware */
  485         if (ixgb_hardware_init(sc)) {
printf("%s: Unable to initialize the hardware\n",
sc->sc_dv.dv_xname);
splx(s);
  489                 return;
  490         }
  492         /* Prepare transmit descriptors and buffers */
  493         if (ixgb_setup_transmit_structures(sc)) {
printf("%s: Could not setup transmit structures\n",
sc->sc_dv.dv_xname);
ixgb_stop(sc);
splx(s);
  498                 return;
  499         }
ixgb_initialize_transmit_unit(sc);
  502         /* Setup Multicast table */
ixgb_set_multi(sc);
  505         /* Prepare receive descriptors and buffers */
  506         if (ixgb_setup_receive_structures(sc)) {
printf("%s: Could not setup receive structures\n",
sc->sc_dv.dv_xname);
ixgb_stop(sc);
splx(s);
  511                 return;
  512         }
ixgb_initialize_receive_unit(sc);
  515         /* Don't lose promiscuous settings */
ixgb_set_promisc(sc);
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
  521         /* Enable jumbo frames */
IXGB_WRITE_REG(&sc->hw, MFRMS,
sc->hw.max_frame_size << IXGB_MFRMS_SHIFT);
temp_reg = IXGB_READ_REG(&sc->hw, CTRL0);
temp_reg |= IXGB_CTRL0_JFE;
IXGB_WRITE_REG(&sc->hw, CTRL0, temp_reg);
timeout_add(&sc->timer_handle, hz);
ixgb_clear_hw_cntrs(&sc->hw);
ixgb_enable_intr(sc);
splx(s);
  533 }
  535 /*********************************************************************
  536  *
  537  *  Interrupt Service routine
  538  *
  539  **********************************************************************/
  541 int
ixgb_intr(void *arg)
  543 {
  544         struct ixgb_softc *sc = arg;
  545         struct ifnet    *ifp;
u_int32_t       reg_icr;
boolean_t       rxdmt0 = FALSE;
  548         int claimed = 0;
ifp = &sc->interface_data.ac_if;
  552         for (;;) {
reg_icr = IXGB_READ_REG(&sc->hw, ICR);
  554                 if (reg_icr == 0)
  555                         break;
claimed = 1;
  559                 if (reg_icr & IXGB_INT_RXDMT0)
rxdmt0 = TRUE;
  562                 if (ifp->if_flags & IFF_RUNNING) {
ixgb_rxeof(sc, -1);
ixgb_txeof(sc);
  565                 }
  567                 /* Link status change */
  568                 if (reg_icr & (IXGB_INT_RXSEQ | IXGB_INT_LSC)) {
timeout_del(&sc->timer_handle);
ixgb_check_for_link(&sc->hw);
ixgb_update_link_status(sc);
timeout_add(&sc->timer_handle, hz);
  573                 }
  575                 if (rxdmt0 && sc->raidc) {
IXGB_WRITE_REG(&sc->hw, IMC, IXGB_INT_RXDMT0);
IXGB_WRITE_REG(&sc->hw, IMS, IXGB_INT_RXDMT0);
  578                 }
  579         }
  581         if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd))
ixgb_start(ifp);
  584         return (claimed);
  585 }
  588 /*********************************************************************
  589  *
  590  *  Media Ioctl callback
  591  *
  592  *  This routine is called whenever the user queries the status of
  593  *  the interface using ifconfig.
  594  *
  595  **********************************************************************/
  596 void
ixgb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
  598 {
  599         struct ixgb_softc *sc = ifp->if_softc;
INIT_DEBUGOUT("ixgb_media_status: begin");
ixgb_check_for_link(&sc->hw);
ixgb_update_link_status(sc);
ifmr->ifm_status = IFM_AVALID;
ifmr->ifm_active = IFM_ETHER;
  609         if (!sc->hw.link_up) {
ifmr->ifm_active |= IFM_NONE;
  611                 return;
  612         }
ifmr->ifm_status |= IFM_ACTIVE;
  615         if ((sc->hw.phy_type == ixgb_phy_type_g6104) ||
  616             (sc->hw.phy_type == ixgb_phy_type_txn17401))
ifmr->ifm_active |= IFM_10G_LR | IFM_FDX;
  618         else
ifmr->ifm_active |= IFM_10G_SR | IFM_FDX;
  621         return;
  622 }
  624 /*********************************************************************
  625  *
  626  *  Media Ioctl callback
  627  *
  628  *  This routine is called when the user changes speed/duplex using
  629  *  media/mediopt option with ifconfig.
  630  *
  631  **********************************************************************/
  632 int
ixgb_media_change(struct ifnet * ifp)
  634 {
  635         struct ixgb_softc *sc = ifp->if_softc;
  636         struct ifmedia *ifm = &sc->media;
INIT_DEBUGOUT("ixgb_media_change: begin");
  640         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
  641                 return (EINVAL);
  643         return (0);
  644 }
  646 /*********************************************************************
  647  *
  648  *  This routine maps the mbufs to tx descriptors.
  649  *
  650  *  return 0 on success, positive on failure
  651  **********************************************************************/
  653 int
ixgb_encap(struct ixgb_softc *sc, struct mbuf *m_head)
  655 {
u_int8_t        txd_popts;
  657         int             i, j, error = 0;
bus_dmamap_t    map;
  660         struct ixgb_buffer *tx_buffer;
  661         struct ixgb_tx_desc *current_tx_desc = NULL;
  663         /*
  664          * Force a cleanup if number of TX descriptors available hits the
  665          * threshold
  666          */
  667         if (sc->num_tx_desc_avail <= IXGB_TX_CLEANUP_THRESHOLD) {
ixgb_txeof(sc);
  669                 /* Now do we at least have a minimal? */
  670                 if (sc->num_tx_desc_avail <= IXGB_TX_CLEANUP_THRESHOLD) {
sc->no_tx_desc_avail1++;
  672                         return (ENOBUFS);
  673                 }
  674         }
  676         /*
  677          * Map the packet for DMA.
  678          */
tx_buffer = &sc->tx_buffer_area[sc->next_avail_tx_desc];
map = tx_buffer->map;
error = bus_dmamap_load_mbuf(sc->txtag, map,
m_head, BUS_DMA_NOWAIT);
  684         if (error != 0) {
sc->no_tx_dma_setup++;
  686                 return (error);
  687         }
IXGB_KASSERT(map->dm_nsegs != 0, ("ixgb_encap: empty packet"));
  690         if (map->dm_nsegs > sc->num_tx_desc_avail)
  691                 goto fail;
  693 #ifdef IXGB_CSUM_OFFLOAD
ixgb_transmit_checksum_setup(sc, m_head, &txd_popts);
  695 #else
txd_popts = 0;
  697 #endif
i = sc->next_avail_tx_desc;
  700         for (j = 0; j < map->dm_nsegs; j++) {
tx_buffer = &sc->tx_buffer_area[i];
current_tx_desc = &sc->tx_desc_base[i];
current_tx_desc->buff_addr = htole64(map->dm_segs[j].ds_addr);
current_tx_desc->cmd_type_len = htole32((sc->txd_cmd | map->dm_segs[j].ds_len));
current_tx_desc->popts = txd_popts;
  707                 if (++i == sc->num_tx_desc)
i = 0;
tx_buffer->m_head = NULL;
  711         }
sc->num_tx_desc_avail -= map->dm_nsegs;
sc->next_avail_tx_desc = i;
tx_buffer->m_head = m_head;
bus_dmamap_sync(sc->txtag, map, 0, map->dm_mapsize,
BUS_DMASYNC_PREWRITE);
  720         /*
  721          * Last Descriptor of Packet needs End Of Packet (EOP)
  722          */
current_tx_desc->cmd_type_len |= htole32(IXGB_TX_DESC_CMD_EOP);
  725         /*
  726          * Advance the Transmit Descriptor Tail (Tdt), this tells the E1000
  727          * that this frame is available to transmit.
  728          */
bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 0,
sc->txdma.dma_map->dm_mapsize,
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
IXGB_WRITE_REG(&sc->hw, TDT, i);
  734         return (0);
fail:
sc->no_tx_desc_avail2++;
bus_dmamap_unload(sc->txtag, map);
  739         return (ENOBUFS);
  740 }
  742 void
ixgb_set_promisc(struct ixgb_softc *sc)
  744 {
u_int32_t       reg_rctl;
  747         struct ifnet   *ifp = &sc->interface_data.ac_if;
reg_rctl = IXGB_READ_REG(&sc->hw, RCTL);
  751         if (ifp->if_flags & IFF_PROMISC) {
reg_rctl |= (IXGB_RCTL_UPE | IXGB_RCTL_MPE);
  753         } else if (ifp->if_flags & IFF_ALLMULTI) {
reg_rctl |= IXGB_RCTL_MPE;
reg_rctl &= ~IXGB_RCTL_UPE;
  756         } else {
reg_rctl &= ~(IXGB_RCTL_UPE | IXGB_RCTL_MPE);
  758         }
IXGB_WRITE_REG(&sc->hw, RCTL, reg_rctl);
  760 }
  762 /*********************************************************************
  763  *  Multicast Update
  764  *
  765  *  This routine is called whenever multicast address list is updated.
  766  *
  767  **********************************************************************/
  769 void
ixgb_set_multi(struct ixgb_softc *sc)
  771 {
u_int32_t       reg_rctl = 0;
u_int8_t        mta[MAX_NUM_MULTICAST_ADDRESSES * IXGB_ETH_LENGTH_OF_ADDRESS];
  774         int             mcnt = 0;
  775         struct ifnet   *ifp = &sc->interface_data.ac_if;
  776         struct arpcom *ac = &sc->interface_data;
  777         struct ether_multi *enm;
  778         struct ether_multistep step;
IOCTL_DEBUGOUT("ixgb_set_multi: begin");
ETHER_FIRST_MULTI(step, ac, enm);
  783         while (enm != NULL) {
  784                 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
ifp->if_flags |= IFF_ALLMULTI;
mcnt = MAX_NUM_MULTICAST_ADDRESSES;
  787                 }
  788                 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
  789                         break;
bcopy(enm->enm_addrlo, &mta[mcnt*IXGB_ETH_LENGTH_OF_ADDRESS],
IXGB_ETH_LENGTH_OF_ADDRESS);
mcnt++;
ETHER_NEXT_MULTI(step, enm);
  794         }
  796         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
reg_rctl = IXGB_READ_REG(&sc->hw, RCTL);
reg_rctl |= IXGB_RCTL_MPE;
IXGB_WRITE_REG(&sc->hw, RCTL, reg_rctl);
  800         } else
ixgb_mc_addr_list_update(&sc->hw, mta, mcnt, 0);
  802 }
  805 /*********************************************************************
  806  *  Timer routine
  807  *
  808  *  This routine checks for link status and updates statistics.
  809  *
  810  **********************************************************************/
  812 void
ixgb_local_timer(void *arg)
  814 {
  815         struct ifnet   *ifp;
  816         struct ixgb_softc *sc = arg;
  817         int s;
ifp = &sc->interface_data.ac_if;
s = splnet();
ixgb_check_for_link(&sc->hw);
ixgb_update_link_status(sc);
ixgb_update_stats_counters(sc);
  826         if (ixgb_display_debug_stats && ifp->if_flags & IFF_RUNNING)
ixgb_print_hw_stats(sc);
timeout_add(&sc->timer_handle, hz);
splx(s);
  832 }
  834 void
ixgb_update_link_status(struct ixgb_softc *sc)
  836 {
  837         struct ifnet *ifp = &sc->interface_data.ac_if;
  839         if (sc->hw.link_up) {
  840                 if (!sc->link_active) {
ifp->if_baudrate = 1000000000;
sc->link_active = 1;
ifp->if_link_state = LINK_STATE_FULL_DUPLEX;
if_link_state_change(ifp);
  845                 }
  846         } else {
  847                 if (sc->link_active) {
ifp->if_baudrate = 0;
sc->link_active = 0;
ifp->if_link_state = LINK_STATE_DOWN;
if_link_state_change(ifp);
  852                 }
  853         }
  854 }
  856 /*********************************************************************
  857  *
  858  *  This routine disables all traffic on the adapter by issuing a
  859  *  global reset on the MAC and deallocates TX/RX buffers.
  860  *
  861  **********************************************************************/
  863 void
ixgb_stop(void *arg)
  865 {
  866         struct ifnet   *ifp;
  867         struct ixgb_softc *sc = arg;
ifp = &sc->interface_data.ac_if;
INIT_DEBUGOUT("ixgb_stop: begin\n");
ixgb_disable_intr(sc);
sc->hw.adapter_stopped = FALSE;
ixgb_adapter_stop(&sc->hw);
timeout_del(&sc->timer_handle);
  876         /* Tell the stack that the interface is no longer active */
ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
ixgb_free_transmit_structures(sc);
ixgb_free_receive_structures(sc);
  881 }
  884 /*********************************************************************
  885  *
  886  *  Determine hardware revision.
  887  *
  888  **********************************************************************/
  889 void
ixgb_identify_hardware(struct ixgb_softc *sc)
  891 {
u_int32_t       reg;
  893         struct pci_attach_args *pa = &sc->osdep.ixgb_pa;
  895         /* Make sure our PCI config space has the necessary stuff set */
sc->hw.pci_cmd_word = pci_conf_read(pa->pa_pc, pa->pa_tag,
PCI_COMMAND_STATUS_REG);
  899         /* Save off the information about this board */
sc->hw.vendor_id = PCI_VENDOR(pa->pa_id);
sc->hw.device_id = PCI_PRODUCT(pa->pa_id);
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG);
sc->hw.revision_id = PCI_REVISION(reg);
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
sc->hw.subsystem_vendor_id = PCI_VENDOR(reg);
sc->hw.subsystem_id = PCI_PRODUCT(reg);
  910         /* Set MacType, etc. based on this PCI info */
  911         switch (sc->hw.device_id) {
  912         case IXGB_DEVICE_ID_82597EX:
  913         case IXGB_DEVICE_ID_82597EX_SR:
  914         case IXGB_DEVICE_ID_82597EX_LR:
  915         case IXGB_DEVICE_ID_82597EX_CX4:
sc->hw.mac_type = ixgb_82597;
  917                 break;
  918         default:
INIT_DEBUGOUT1("Unknown device if 0x%x", sc->hw.device_id);
printf("%s: unsupported device id 0x%x\n",
sc->sc_dv.dv_xname, sc->hw.device_id);
  922         }
  923 }
  925 int
ixgb_allocate_pci_resources(struct ixgb_softc *sc)
  928 {
  929         int val;
pci_intr_handle_t       ih;
  931         const char              *intrstr = NULL;
  932         struct pci_attach_args *pa =  &sc->osdep.ixgb_pa;
pci_chipset_tag_t       pc = pa->pa_pc;
val = pci_conf_read(pa->pa_pc, pa->pa_tag, IXGB_MMBA);
  936         if (PCI_MAPREG_TYPE(val) != PCI_MAPREG_TYPE_MEM) {
printf(": mmba is not mem space\n");
  938                 return (ENXIO);
  939         }
  940         if (pci_mapreg_map(pa, IXGB_MMBA, PCI_MAPREG_MEM_TYPE(val), 0,
  941             &sc->osdep.mem_bus_space_tag, &sc->osdep.mem_bus_space_handle,
  942             &sc->osdep.ixgb_membase, &sc->osdep.ixgb_memsize, 0)) {
printf(": cannot find mem space\n");
  944                 return (ENXIO);
  945         }
  947         if (pci_intr_map(pa, &ih)) {
printf(": couldn't map interrupt\n");
  949                 return (ENXIO);
  950         }
sc->hw.back = &sc->osdep;
intrstr = pci_intr_string(pc, ih);
sc->sc_intrhand = pci_intr_establish(pc, ih, IPL_NET, ixgb_intr, sc,
sc->sc_dv.dv_xname);
  957         if (sc->sc_intrhand == NULL) {
printf(": couldn't establish interrupt");
  959                 if (intrstr != NULL)
printf(" at %s", intrstr);
printf("\n");
  962                 return (ENXIO);
  963         }
printf(": %s", intrstr);
  966         return (0);
  967 }
  969 void
ixgb_free_pci_resources(struct ixgb_softc *sc)
  971 {
  972         struct pci_attach_args *pa = &sc->osdep.ixgb_pa;
pci_chipset_tag_t       pc = pa->pa_pc;
  975         if (sc->sc_intrhand)
pci_intr_disestablish(pc, sc->sc_intrhand);
sc->sc_intrhand = 0;
  979         if (sc->osdep.ixgb_membase)
bus_space_unmap(sc->osdep.mem_bus_space_tag, sc->osdep.mem_bus_space_handle,
sc->osdep.ixgb_memsize);
sc->osdep.ixgb_membase = 0;
  983 }
  985 /*********************************************************************
  986  *
  987  *  Initialize the hardware to a configuration as specified by the
  988  *  adapter structure. The controller is reset, the EEPROM is
  989  *  verified, the MAC address is set, then the shared initialization
  990  *  routines are called.
  991  *
  992  **********************************************************************/
  993 int
ixgb_hardware_init(struct ixgb_softc *sc)
  995 {
  996         /* Issue a global reset */
sc->hw.adapter_stopped = FALSE;
ixgb_adapter_stop(&sc->hw);
 1000         /* Make sure we have a good EEPROM before we read from it */
 1001         if (!ixgb_validate_eeprom_checksum(&sc->hw)) {
printf("%s: The EEPROM Checksum Is Not Valid\n",
sc->sc_dv.dv_xname);
 1004                 return (EIO);
 1005         }
 1006         if (!ixgb_init_hw(&sc->hw)) {
printf("%s: Hardware Initialization Failed",
sc->sc_dv.dv_xname);
 1009                 return (EIO);
 1010         }
bcopy(sc->hw.curr_mac_addr, sc->interface_data.ac_enaddr,
IXGB_ETH_LENGTH_OF_ADDRESS);
 1014         return (0);
 1015 }
 1017 /*********************************************************************
 1018  *
 1019  *  Setup networking device structure and register an interface.
 1020  *
 1021  **********************************************************************/
 1022 void
ixgb_setup_interface(struct ixgb_softc *sc)
 1024 {
 1025         struct ifnet   *ifp;
INIT_DEBUGOUT("ixgb_setup_interface: begin");
ifp = &sc->interface_data.ac_if;
strlcpy(ifp->if_xname, sc->sc_dv.dv_xname, IFNAMSIZ);
ifp->if_softc = sc;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_ioctl = ixgb_ioctl;
ifp->if_start = ixgb_start;
ifp->if_watchdog = ixgb_watchdog;
ifp->if_hardmtu =
IXGB_MAX_JUMBO_FRAME_SIZE - ETHER_HDR_LEN - ETHER_CRC_LEN;
IFQ_SET_MAXLEN(&ifp->if_snd, sc->num_tx_desc - 1);
IFQ_SET_READY(&ifp->if_snd);
ifp->if_capabilities = IFCAP_VLAN_MTU;
 1043 #ifdef IXGB_CSUM_OFFLOAD
ifp->if_capabilities |= IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4;
 1045 #endif
 1047         /*
 1048          * Specify the media types supported by this adapter and register
 1049          * callbacks to update media and link information
 1050          */
ifmedia_init(&sc->media, IFM_IMASK, ixgb_media_change,
ixgb_media_status);
 1053         if ((sc->hw.phy_type == ixgb_phy_type_g6104) ||
 1054             (sc->hw.phy_type == ixgb_phy_type_txn17401)) {
ifmedia_add(&sc->media, IFM_ETHER | IFM_10G_LR |
IFM_FDX, 0, NULL);
 1057         } else {
ifmedia_add(&sc->media, IFM_ETHER | IFM_10G_SR |
IFM_FDX, 0, NULL);
 1060         }
ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
if_attach(ifp);
ether_ifattach(ifp);
 1066 }
 1068 /********************************************************************
 1069  * Manage DMA'able memory.
 1070  *******************************************************************/
 1071 int
ixgb_dma_malloc(struct ixgb_softc *sc, bus_size_t size,
 1073                 struct ixgb_dma_alloc * dma, int mapflags)
 1074 {
 1075         int r;
dma->dma_tag = sc->osdep.ixgb_pa.pa_dmat;
r = bus_dmamap_create(dma->dma_tag, size, 1,
size, 0, BUS_DMA_NOWAIT, &dma->dma_map);
 1080         if (r != 0) {
printf("%s: ixgb_dma_malloc: bus_dmamap_create failed; "
 1082                         "error %u\n", sc->sc_dv.dv_xname, r);
 1083                 goto fail_0;
 1084         }
r = bus_dmamem_alloc(dma->dma_tag, size, PAGE_SIZE, 0, &dma->dma_seg,
 1087             1, &dma->dma_nseg, BUS_DMA_NOWAIT);
 1088         if (r != 0) {
printf("%s: ixgb_dma_malloc: bus_dmammem_alloc failed; "
 1090                         "size %lu, error %d\n", sc->sc_dv.dv_xname,
 1091                         (unsigned long)size, r);
 1092                 goto fail_1;
 1093         }
r = bus_dmamem_map(dma->dma_tag, &dma->dma_seg, dma->dma_nseg, size,
 1096             &dma->dma_vaddr, BUS_DMA_NOWAIT);
 1097         if (r != 0) {
printf("%s: ixgb_dma_malloc: bus_dmammem_map failed; "
 1099                         "size %lu, error %d\n", sc->sc_dv.dv_xname,
 1100                         (unsigned long)size, r);
 1101                 goto fail_2;
 1102         }
r = bus_dmamap_load(sc->osdep.ixgb_pa.pa_dmat, dma->dma_map,
dma->dma_vaddr,
size,
NULL,
mapflags | BUS_DMA_NOWAIT);
 1109         if (r != 0) {
printf("%s: ixgb_dma_malloc: bus_dmamap_load failed; "
 1111                         "error %u\n", sc->sc_dv.dv_xname, r);
 1112                 goto fail_3;
 1113         }
dma->dma_size = size;
 1116         return (0);
fail_3: 
bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size);
fail_2: 
bus_dmamem_free(dma->dma_tag, &dma->dma_seg, dma->dma_nseg);
fail_1: 
bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
fail_0: 
dma->dma_map = NULL;
dma->dma_tag = NULL;
 1128         return (r);
 1129 }
 1131 void
ixgb_dma_free(struct ixgb_softc *sc, struct ixgb_dma_alloc *dma)
 1133 {
 1134         if (dma->dma_tag == NULL)
 1135                 return;
 1137         if (dma->dma_map != NULL) {
bus_dmamap_sync(dma->dma_tag, dma->dma_map, 0,
dma->dma_map->dm_mapsize,
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(dma->dma_tag, dma->dma_map);
bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, dma->dma_size);
bus_dmamem_free(dma->dma_tag, &dma->dma_seg, dma->dma_nseg);
bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
 1145         }
 1146 }
 1148 /*********************************************************************
 1149  *
 1150  *  Allocate memory for tx_buffer structures. The tx_buffer stores all
 1151  *  the information needed to transmit a packet on the wire.
 1152  *
 1153  **********************************************************************/
 1154 int
ixgb_allocate_transmit_structures(struct ixgb_softc *sc)
 1156 {
 1157         if (!(sc->tx_buffer_area =
 1158               (struct ixgb_buffer *) malloc(sizeof(struct ixgb_buffer) *
sc->num_tx_desc, M_DEVBUF,
M_NOWAIT))) {
printf("%s: Unable to allocate tx_buffer memory\n",
sc->sc_dv.dv_xname);
 1163                 return (ENOMEM);
 1164         }
bzero(sc->tx_buffer_area,
 1166               sizeof(struct ixgb_buffer) * sc->num_tx_desc);
 1168         return (0);
 1169 }
 1171 /*********************************************************************
 1172  *
 1173  *  Allocate and initialize transmit structures.
 1174  *
 1175  **********************************************************************/
 1176 int
ixgb_setup_transmit_structures(struct ixgb_softc *sc)
 1178 {
 1179         struct  ixgb_buffer *tx_buffer;
 1180         int error, i;
 1182         if ((error = ixgb_allocate_transmit_structures(sc)) != 0)
 1183                 goto fail;
bzero((void *)sc->tx_desc_base,
 1186               (sizeof(struct ixgb_tx_desc)) * sc->num_tx_desc);
sc->txtag = sc->osdep.ixgb_pa.pa_dmat;
tx_buffer = sc->tx_buffer_area;
 1191         for (i = 0; i < sc->num_tx_desc; i++) {
error = bus_dmamap_create(sc->txtag, IXGB_MAX_JUMBO_FRAME_SIZE,
IXGB_MAX_SCATTER, IXGB_MAX_JUMBO_FRAME_SIZE, 0,
BUS_DMA_NOWAIT, &tx_buffer->map);
 1195                 if (error != 0) {
printf("%s: Unable to create TX DMA map\n",
sc->sc_dv.dv_xname);
 1198                         goto fail;
 1199                 }
tx_buffer++;
 1201         }
sc->next_avail_tx_desc = 0;
sc->oldest_used_tx_desc = 0;
 1206         /* Set number of descriptors available */
sc->num_tx_desc_avail = sc->num_tx_desc;
 1209         /* Set checksum context */
sc->active_checksum_context = OFFLOAD_NONE;
bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 0,
sc->txdma.dma_size, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 1214         return (0);
fail:
ixgb_free_transmit_structures(sc);
 1218         return (error);
 1219 }
 1221 /*********************************************************************
 1222  *
 1223  *  Enable transmit unit.
 1224  *
 1225  **********************************************************************/
 1226 void
ixgb_initialize_transmit_unit(struct ixgb_softc *sc)
 1228 {
u_int32_t       reg_tctl;
u_int64_t       bus_addr;
 1232         /* Setup the Base and Length of the Tx Descriptor Ring */
bus_addr = sc->txdma.dma_map->dm_segs[0].ds_addr;
IXGB_WRITE_REG(&sc->hw, TDBAL, (u_int32_t)bus_addr);
IXGB_WRITE_REG(&sc->hw, TDBAH, (u_int32_t)(bus_addr >> 32));
IXGB_WRITE_REG(&sc->hw, TDLEN,
sc->num_tx_desc *
 1238                        sizeof(struct ixgb_tx_desc));
 1240         /* Setup the HW Tx Head and Tail descriptor pointers */
IXGB_WRITE_REG(&sc->hw, TDH, 0);
IXGB_WRITE_REG(&sc->hw, TDT, 0);
HW_DEBUGOUT2("Base = %x, Length = %x\n",
IXGB_READ_REG(&sc->hw, TDBAL),
IXGB_READ_REG(&sc->hw, TDLEN));
IXGB_WRITE_REG(&sc->hw, TIDV, sc->tx_int_delay);
 1250         /* Program the Transmit Control Register */
reg_tctl = IXGB_READ_REG(&sc->hw, TCTL);
reg_tctl = IXGB_TCTL_TCE | IXGB_TCTL_TXEN | IXGB_TCTL_TPDE;
IXGB_WRITE_REG(&sc->hw, TCTL, reg_tctl);
 1255         /* Setup Transmit Descriptor Settings for this adapter */
sc->txd_cmd = IXGB_TX_DESC_TYPE | IXGB_TX_DESC_CMD_RS;
 1258         if (sc->tx_int_delay > 0)
sc->txd_cmd |= IXGB_TX_DESC_CMD_IDE;
 1260 }
 1262 /*********************************************************************
 1263  *
 1264  *  Free all transmit related data structures.
 1265  *
 1266  **********************************************************************/
 1267 void
ixgb_free_transmit_structures(struct ixgb_softc *sc)
 1269 {
 1270         struct ixgb_buffer *tx_buffer;
 1271         int             i;
INIT_DEBUGOUT("free_transmit_structures: begin");
 1275         if (sc->tx_buffer_area != NULL) {
tx_buffer = sc->tx_buffer_area;
 1277                 for (i = 0; i < sc->num_tx_desc; i++, tx_buffer++) {
 1278                         if (tx_buffer->map != NULL &&
tx_buffer->map->dm_nsegs > 0) {
bus_dmamap_sync(sc->txtag, tx_buffer->map,
 1281                                     0, tx_buffer->map->dm_mapsize,
BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->txtag,
tx_buffer->map);
 1285                         }
 1287                         if (tx_buffer->m_head != NULL) {
m_freem(tx_buffer->m_head);
tx_buffer->m_head = NULL;
 1290                         }
 1291                         if (tx_buffer->map != NULL) {
bus_dmamap_destroy(sc->txtag,
tx_buffer->map);
tx_buffer->map = NULL;
 1295                         }
 1296                 }
 1297         }
 1298         if (sc->tx_buffer_area != NULL) {
free(sc->tx_buffer_area, M_DEVBUF);
sc->tx_buffer_area = NULL;
 1301         }
 1302         if (sc->txtag != NULL) {
sc->txtag = NULL;
 1304         }
 1305 }
 1307 /*********************************************************************
 1308  *
 1309  *  The offload context needs to be set when we transfer the first
 1310  *  packet of a particular protocol (TCP/UDP). We change the
 1311  *  context only if the protocol type changes.
 1312  *
 1313  **********************************************************************/
 1314 void
ixgb_transmit_checksum_setup(struct ixgb_softc *sc,
 1316                              struct mbuf *mp,
u_int8_t *txd_popts)
 1318 {
 1319         struct ixgb_context_desc *TXD;
 1320         struct ixgb_buffer *tx_buffer;
 1321         int             curr_txd;
 1323         if (mp->m_pkthdr.csum_flags) {
 1325                 if (mp->m_pkthdr.csum_flags & M_TCPV4_CSUM_OUT) {
 1326                         *txd_popts = IXGB_TX_DESC_POPTS_TXSM;
 1327                         if (sc->active_checksum_context == OFFLOAD_TCP_IP)
 1328                                 return;
 1329                         else
sc->active_checksum_context = OFFLOAD_TCP_IP;
 1332                 } else if (mp->m_pkthdr.csum_flags & M_UDPV4_CSUM_OUT) {
 1333                         *txd_popts = IXGB_TX_DESC_POPTS_TXSM;
 1334                         if (sc->active_checksum_context == OFFLOAD_UDP_IP)
 1335                                 return;
 1336                         else
sc->active_checksum_context = OFFLOAD_UDP_IP;
 1338                 } else {
 1339                         *txd_popts = 0;
 1340                         return;
 1341                 }
 1342         } else {
 1343                 *txd_popts = 0;
 1344                 return;
 1345         }
 1347         /*
 1348          * If we reach this point, the checksum offload context needs to be
 1349          * reset.
 1350          */
curr_txd = sc->next_avail_tx_desc;
tx_buffer = &sc->tx_buffer_area[curr_txd];
TXD = (struct ixgb_context_desc *) & sc->tx_desc_base[curr_txd];
TXD->tucss = ENET_HEADER_SIZE + sizeof(struct ip);
TXD->tucse = 0;
TXD->mss = 0;
 1360         if (sc->active_checksum_context == OFFLOAD_TCP_IP) {
TXD->tucso =
ENET_HEADER_SIZE + sizeof(struct ip) +
offsetof(struct tcphdr, th_sum);
 1364         } else if (sc->active_checksum_context == OFFLOAD_UDP_IP) {
TXD->tucso =
ENET_HEADER_SIZE + sizeof(struct ip) +
offsetof(struct udphdr, uh_sum);
 1368         }
TXD->cmd_type_len = htole32(IXGB_CONTEXT_DESC_CMD_TCP |
IXGB_TX_DESC_CMD_RS | IXGB_CONTEXT_DESC_CMD_IDE);
tx_buffer->m_head = NULL;
 1374         if (++curr_txd == sc->num_tx_desc)
curr_txd = 0;
sc->num_tx_desc_avail--;
sc->next_avail_tx_desc = curr_txd;
 1379 }
 1381 /**********************************************************************
 1382  *
 1383  *  Examine each tx_buffer in the used queue. If the hardware is done
 1384  *  processing the packet then free associated resources. The
 1385  *  tx_buffer is put back on the free queue.
 1386  *
 1387  **********************************************************************/
 1388 void
ixgb_txeof(struct ixgb_softc *sc)
 1390 {
 1391         int             i, num_avail;
 1392         struct ixgb_buffer *tx_buffer;
 1393         struct ixgb_tx_desc *tx_desc;
 1394         struct ifnet    *ifp = &sc->interface_data.ac_if;
 1396         if (sc->num_tx_desc_avail == sc->num_tx_desc)
 1397                 return;
num_avail = sc->num_tx_desc_avail;
i = sc->oldest_used_tx_desc;
tx_buffer = &sc->tx_buffer_area[i];
tx_desc = &sc->tx_desc_base[i];
bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 0,
sc->txdma.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD);
 1407         while (tx_desc->status & IXGB_TX_DESC_STATUS_DD) {
tx_desc->status = 0;
num_avail++;
 1412                 if (tx_buffer->m_head != NULL) {
ifp->if_opackets++;
 1415                         if (tx_buffer->map->dm_nsegs > 0) {
bus_dmamap_sync(sc->txtag, tx_buffer->map,
 1417                                     0, tx_buffer->map->dm_mapsize,
BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->txtag, tx_buffer->map);
 1420                         }
m_freem(tx_buffer->m_head);
tx_buffer->m_head = NULL;
 1424                 }
 1425                 if (++i == sc->num_tx_desc)
i = 0;
tx_buffer = &sc->tx_buffer_area[i];
tx_desc = &sc->tx_desc_base[i];
 1430         }
bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 0,
sc->txdma.dma_map->dm_mapsize,
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
sc->oldest_used_tx_desc = i;
 1437         /*
 1438          * If we have enough room, clear IFF_OACTIVE to tell the stack that
 1439          * it is OK to send packets. If there are no pending descriptors,
 1440          * clear the timeout. Otherwise, if some descriptors have been freed,
 1441          * restart the timeout.
 1442          */
 1443         if (num_avail > IXGB_TX_CLEANUP_THRESHOLD) {
ifp->if_flags &= ~IFF_OACTIVE;
 1445                 /* All clean, turn off the timer */
 1446                 if (num_avail == sc->num_tx_desc)
ifp->if_timer = 0;
 1448                 /* Some cleaned, reset the timer */
 1449                 else if (num_avail != sc->num_tx_desc_avail)
ifp->if_timer = IXGB_TX_TIMEOUT;
 1451         }
sc->num_tx_desc_avail = num_avail;
 1453 }
 1456 /*********************************************************************
 1457  *
 1458  *  Get a buffer from system mbuf buffer pool.
 1459  *
 1460  **********************************************************************/
 1461 int
ixgb_get_buf(struct ixgb_softc *sc, int i,
 1463              struct mbuf *nmp)
 1464 {
 1465         struct mbuf *mp = nmp;
 1466         struct ixgb_buffer *rx_buffer;
 1467         struct ifnet   *ifp;
 1468         int             error;
ifp = &sc->interface_data.ac_if;
 1472         if (mp == NULL) {
MGETHDR(mp, M_DONTWAIT, MT_DATA);
 1474                 if (mp == NULL) {
sc->mbuf_alloc_failed++;
 1476                         return (ENOBUFS);
 1477                 }
MCLGET(mp, M_DONTWAIT);
 1479                 if ((mp->m_flags & M_EXT) == 0) {
m_freem(mp);
sc->mbuf_cluster_failed++;
 1482                         return (ENOBUFS);
 1483                 }
mp->m_len = mp->m_pkthdr.len = MCLBYTES;
 1485         } else {
mp->m_len = mp->m_pkthdr.len = MCLBYTES;
mp->m_data = mp->m_ext.ext_buf;
mp->m_next = NULL;
 1489         }
 1491         if (sc->hw.max_frame_size <= (MCLBYTES - ETHER_ALIGN))
m_adj(mp, ETHER_ALIGN);
rx_buffer = &sc->rx_buffer_area[i];
 1496         /*
 1497          * Using memory from the mbuf cluster pool, invoke the bus_dma
 1498          * machinery to arrange the memory mapping.
 1499          */
error = bus_dmamap_load_mbuf(sc->rxtag, rx_buffer->map,
mp, BUS_DMA_NOWAIT);
 1502         if (error) {
m_free(mp);
 1504                 return (error);
 1505         }
rx_buffer->m_head = mp;
sc->rx_desc_base[i].buff_addr = htole64(rx_buffer->map->dm_segs[0].ds_addr);
bus_dmamap_sync(sc->rxtag, rx_buffer->map, 0,
rx_buffer->map->dm_mapsize, BUS_DMASYNC_PREREAD);
 1511         return (0);
 1512 }
 1514 /*********************************************************************
 1515  *
 1516  *  Allocate memory for rx_buffer structures. Since we use one
 1517  *  rx_buffer per received packet, the maximum number of rx_buffer's
 1518  *  that we'll need is equal to the number of receive descriptors
 1519  *  that we've allocated.
 1520  *
 1521  **********************************************************************/
 1522 int
ixgb_allocate_receive_structures(struct ixgb_softc *sc)
 1524 {
 1525         int             i, error;
 1526         struct ixgb_buffer *rx_buffer;
 1528         if (!(sc->rx_buffer_area =
 1529               (struct ixgb_buffer *) malloc(sizeof(struct ixgb_buffer) *
sc->num_rx_desc, M_DEVBUF,
M_NOWAIT))) {
printf("%s: Unable to allocate rx_buffer memory\n",
sc->sc_dv.dv_xname);
 1534                 return (ENOMEM);
 1535         }
bzero(sc->rx_buffer_area,
 1538               sizeof(struct ixgb_buffer) * sc->num_rx_desc);
sc->rxtag = sc->osdep.ixgb_pa.pa_dmat;
rx_buffer = sc->rx_buffer_area;
 1543         for (i = 0; i < sc->num_rx_desc; i++, rx_buffer++) {
error = bus_dmamap_create(sc->rxtag, MCLBYTES, 1,
MCLBYTES, 0, BUS_DMA_NOWAIT,
 1546                                           &rx_buffer->map);
 1547                 if (error != 0) {
printf("%s: ixgb_allocate_receive_structures: "
 1549                                "bus_dmamap_create failed; error %u\n",
sc->sc_dv.dv_xname, error);
 1551                         goto fail;
 1552                 }
 1553         }
 1555         for (i = 0; i < sc->num_rx_desc; i++) {
error = ixgb_get_buf(sc, i, NULL);
 1557                 if (error != 0)
 1558                         goto fail;
 1559         }
bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 0,
sc->rxdma.dma_map->dm_mapsize,
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 1564         return (0);
fail:
ixgb_free_receive_structures(sc);
 1568         return (error);
 1569 }
 1571 /*********************************************************************
 1572  *
 1573  *  Allocate and initialize receive structures.
 1574  *
 1575  **********************************************************************/
 1576 int
ixgb_setup_receive_structures(struct ixgb_softc *sc)
 1578 {
bzero((void *)sc->rx_desc_base,
 1580               (sizeof(struct ixgb_rx_desc)) * sc->num_rx_desc);
 1582         if (ixgb_allocate_receive_structures(sc))
 1583                 return (ENOMEM);
 1585         /* Setup our descriptor pointers */
sc->next_rx_desc_to_check = 0;
sc->next_rx_desc_to_use = 0;
 1588         return (0);
 1589 }
 1591 /*********************************************************************
 1592  *
 1593  *  Enable receive unit.
 1594  *
 1595  **********************************************************************/
 1596 void
ixgb_initialize_receive_unit(struct ixgb_softc *sc)
 1598 {
u_int32_t       reg_rctl;
u_int32_t       reg_rxcsum;
u_int32_t       reg_rxdctl;
 1602         struct ifnet   *ifp;
u_int64_t       bus_addr;
ifp = &sc->interface_data.ac_if;
 1607         /*
 1608          * Make sure receives are disabled while setting up the descriptor
 1609          * ring
 1610          */
reg_rctl = IXGB_READ_REG(&sc->hw, RCTL);
IXGB_WRITE_REG(&sc->hw, RCTL, reg_rctl & ~IXGB_RCTL_RXEN);
 1614         /* Set the Receive Delay Timer Register */
IXGB_WRITE_REG(&sc->hw, RDTR,
sc->rx_int_delay);
 1618         /* Setup the Base and Length of the Rx Descriptor Ring */
bus_addr = sc->rxdma.dma_map->dm_segs[0].ds_addr;
IXGB_WRITE_REG(&sc->hw, RDBAL, (u_int32_t)bus_addr);
IXGB_WRITE_REG(&sc->hw, RDBAH, (u_int32_t)(bus_addr >> 32));
IXGB_WRITE_REG(&sc->hw, RDLEN, sc->num_rx_desc *
 1623                        sizeof(struct ixgb_rx_desc));
 1625         /* Setup the HW Rx Head and Tail Descriptor Pointers */
IXGB_WRITE_REG(&sc->hw, RDH, 0);
IXGB_WRITE_REG(&sc->hw, RDT, sc->num_rx_desc - 1);
reg_rxdctl = RXDCTL_WTHRESH_DEFAULT << IXGB_RXDCTL_WTHRESH_SHIFT
 1631                 | RXDCTL_HTHRESH_DEFAULT << IXGB_RXDCTL_HTHRESH_SHIFT
 1632                 | RXDCTL_PTHRESH_DEFAULT << IXGB_RXDCTL_PTHRESH_SHIFT;
IXGB_WRITE_REG(&sc->hw, RXDCTL, reg_rxdctl);
sc->raidc = 1;
 1636         if (sc->raidc) {
uint32_t        raidc;
uint8_t         poll_threshold;
 1639 #define IXGB_RAIDC_POLL_DEFAULT 120
poll_threshold = ((sc->num_rx_desc - 1) >> 3);
poll_threshold >>= 1;
poll_threshold &= 0x3F;
raidc = IXGB_RAIDC_EN | IXGB_RAIDC_RXT_GATE |
 1645                         (IXGB_RAIDC_POLL_DEFAULT << IXGB_RAIDC_POLL_SHIFT) |
 1646                         (sc->rx_int_delay << IXGB_RAIDC_DELAY_SHIFT) |
poll_threshold;
IXGB_WRITE_REG(&sc->hw, RAIDC, raidc);
 1649         }
 1651         /* Enable Receive Checksum Offload for TCP and UDP ? */
reg_rxcsum = IXGB_READ_REG(&sc->hw, RXCSUM);
reg_rxcsum |= IXGB_RXCSUM_TUOFL;
IXGB_WRITE_REG(&sc->hw, RXCSUM, reg_rxcsum);
 1656         /* Setup the Receive Control Register */
reg_rctl = IXGB_READ_REG(&sc->hw, RCTL);
reg_rctl &= ~(3 << IXGB_RCTL_MO_SHIFT);
reg_rctl |= IXGB_RCTL_BAM | IXGB_RCTL_RDMTS_1_2 | IXGB_RCTL_SECRC |
IXGB_RCTL_CFF |
 1661                 (sc->hw.mc_filter_type << IXGB_RCTL_MO_SHIFT);
 1663         switch (sc->rx_buffer_len) {
 1664         default:
 1665         case IXGB_RXBUFFER_2048:
reg_rctl |= IXGB_RCTL_BSIZE_2048;
 1667                 break;
 1668         case IXGB_RXBUFFER_4096:
reg_rctl |= IXGB_RCTL_BSIZE_4096;
 1670                 break;
 1671         case IXGB_RXBUFFER_8192:
reg_rctl |= IXGB_RCTL_BSIZE_8192;
 1673                 break;
 1674         case IXGB_RXBUFFER_16384:
reg_rctl |= IXGB_RCTL_BSIZE_16384;
 1676                 break;
 1677         }
reg_rctl |= IXGB_RCTL_RXEN;
 1681         /* Enable Receives */
IXGB_WRITE_REG(&sc->hw, RCTL, reg_rctl);
 1683 }
 1685 /*********************************************************************
 1686  *
 1687  *  Free receive related data structures.
 1688  *
 1689  **********************************************************************/
 1690 void
ixgb_free_receive_structures(struct ixgb_softc *sc)
 1692 {
 1693         struct ixgb_buffer *rx_buffer;
 1694         int             i;
INIT_DEBUGOUT("free_receive_structures: begin");
 1698         if (sc->rx_buffer_area != NULL) {
rx_buffer = sc->rx_buffer_area;
 1700                 for (i = 0; i < sc->num_rx_desc; i++, rx_buffer++) {
 1701                         if (rx_buffer->map != NULL &&
rx_buffer->map->dm_nsegs > 0) {
bus_dmamap_sync(sc->rxtag, rx_buffer->map,
 1704                                     0, rx_buffer->map->dm_mapsize,
BUS_DMASYNC_POSTREAD);
bus_dmamap_unload(sc->rxtag,
rx_buffer->map);
 1708                         }
 1709                         if (rx_buffer->m_head != NULL) {
m_freem(rx_buffer->m_head);
rx_buffer->m_head = NULL;
 1712                         }
 1713                         if (rx_buffer->map != NULL) {
bus_dmamap_destroy(sc->rxtag,
rx_buffer->map);
rx_buffer->map = NULL;
 1717                         }
 1718                 }
 1719         }
 1720         if (sc->rx_buffer_area != NULL) {
free(sc->rx_buffer_area, M_DEVBUF);
sc->rx_buffer_area = NULL;
 1723         }
 1724         if (sc->rxtag != NULL)
sc->rxtag = NULL;
 1726 }
 1728 /*********************************************************************
 1729  *
 1730  *  This routine executes in interrupt context. It replenishes
 1731  *  the mbufs in the descriptor and sends data which has been
 1732  *  dma'ed into host memory to upper layer.
 1733  *
 1734  *  We loop at most count times if count is > 0, or until done if
 1735  *  count < 0.
 1736  *
 1737  *********************************************************************/
 1738 void
ixgb_rxeof(struct ixgb_softc *sc, int count)
 1740 {
 1741         struct ifnet   *ifp;
 1742         struct mbuf    *mp;
 1743         int             eop = 0;
 1744         int             len;
u_int8_t        accept_frame = 0;
 1746         int             i;
 1747         int             next_to_use = 0;
 1748         int             eop_desc;
 1750         /* Pointer to the receive descriptor being examined. */
 1751         struct ixgb_rx_desc *current_desc;
ifp = &sc->interface_data.ac_if;
i = sc->next_rx_desc_to_check;
next_to_use = sc->next_rx_desc_to_use;
eop_desc = sc->next_rx_desc_to_check;
current_desc = &sc->rx_desc_base[i];
bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 0,
sc->rxdma.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD);
 1761         if (!((current_desc->status) & IXGB_RX_DESC_STATUS_DD))
 1762                 return;
 1764         while ((current_desc->status & IXGB_RX_DESC_STATUS_DD) &&
 1765                     (count != 0) &&
 1766                     (ifp->if_flags & IFF_RUNNING)) {
mp = sc->rx_buffer_area[i].m_head;
bus_dmamap_sync(sc->rxtag, sc->rx_buffer_area[i].map,
 1770                     0, sc->rx_buffer_area[i].map->dm_mapsize,
BUS_DMASYNC_POSTREAD);
bus_dmamap_unload(sc->rxtag, sc->rx_buffer_area[i].map);
accept_frame = 1;
 1775                 if (current_desc->status & IXGB_RX_DESC_STATUS_EOP) {
count--;
eop = 1;
 1778                 } else {
eop = 0;
 1780                 }
len = current_desc->length;
 1783                 if (current_desc->errors & (IXGB_RX_DESC_ERRORS_CE |
IXGB_RX_DESC_ERRORS_SE | IXGB_RX_DESC_ERRORS_P |
IXGB_RX_DESC_ERRORS_RXE))
accept_frame = 0;
 1787                 if (accept_frame) {
 1789                         /* Assign correct length to the current fragment */
mp->m_len = len;
 1792                         if (sc->fmp == NULL) {
mp->m_pkthdr.len = len;
sc->fmp = mp;   /* Store the first mbuf */
sc->lmp = mp;
 1796                         } else {
 1797                                 /* Chain mbuf's together */
mp->m_flags &= ~M_PKTHDR;
sc->lmp->m_next = mp;
sc->lmp = sc->lmp->m_next;
sc->fmp->m_pkthdr.len += len;
 1802                         }
 1804                         if (eop) {
eop_desc = i;
sc->fmp->m_pkthdr.rcvif = ifp;
ifp->if_ipackets++;
 1809 #if NBPFILTER > 0
 1810                                 /*
 1811                                  * Handle BPF listeners. Let the BPF
 1812                                  * user see the packet.
 1813                                  */
 1814                                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, sc->fmp,
BPF_DIRECTION_IN);
 1817 #endif
ixgb_receive_checksum(sc, current_desc,
sc->fmp);
ether_input_mbuf(ifp, sc->fmp);
sc->fmp = NULL;
sc->lmp = NULL;
 1824                         }
sc->rx_buffer_area[i].m_head = NULL;
 1826                 } else {
sc->dropped_pkts++;
 1828                         if (sc->fmp != NULL)
m_freem(sc->fmp);
sc->fmp = NULL;
sc->lmp = NULL;
 1832                 }
 1834                 /* Zero out the receive descriptors status  */
current_desc->status = 0;
bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 0,
sc->rxdma.dma_map->dm_mapsize,
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 1840                 /* Advance our pointers to the next descriptor */
 1841                 if (++i == sc->num_rx_desc) {
i = 0;
current_desc = sc->rx_desc_base;
 1844                 } else
current_desc++;
 1846         }
sc->next_rx_desc_to_check = i;
 1849         if (--i < 0)
i = (sc->num_rx_desc - 1);
 1852         /*
 1853          * 82597EX: Workaround for redundent write back in receive descriptor ring (causes
 1854          * memory corruption). Avoid using and re-submitting the most recently received RX
 1855          * descriptor back to hardware.
 1856          *
 1857          * if(Last written back descriptor == EOP bit set descriptor)
 1858          *      then avoid re-submitting the most recently received RX descriptor 
 1859          *      back to hardware.
 1860          * if(Last written back descriptor != EOP bit set descriptor)
 1861          *      then avoid re-submitting the most recently received RX descriptors
 1862          *      till last EOP bit set descriptor. 
 1863          */
 1864         if (eop_desc != i) {
 1865                 if (++eop_desc == sc->num_rx_desc)
eop_desc = 0;
i = eop_desc;
 1868         } 
 1869         /* Replenish the descriptors with new mbufs till last EOP bit set descriptor */
 1870         while (next_to_use != i) {
current_desc = &sc->rx_desc_base[next_to_use];
 1872                 if ((current_desc->errors & (IXGB_RX_DESC_ERRORS_CE |
IXGB_RX_DESC_ERRORS_SE | IXGB_RX_DESC_ERRORS_P |
IXGB_RX_DESC_ERRORS_RXE))) {
mp = sc->rx_buffer_area[next_to_use].m_head;
ixgb_get_buf(sc, next_to_use, mp);
 1877                 } else {
 1878                         if (ixgb_get_buf(sc, next_to_use, NULL) == ENOBUFS)
 1879                                 break;
 1880                 }
 1881                 /* Advance our pointers to the next descriptor */
 1882                 if (++next_to_use == sc->num_rx_desc) 
next_to_use = 0;
 1884         }
sc->next_rx_desc_to_use = next_to_use;
 1886         if (--next_to_use < 0)
next_to_use = (sc->num_rx_desc - 1);
 1888         /* Advance the IXGB's Receive Queue #0  "Tail Pointer" */
IXGB_WRITE_REG(&sc->hw, RDT, next_to_use);
 1890 }
 1892 /*********************************************************************
 1893  *
 1894  *  Verify that the hardware indicated that the checksum is valid.
 1895  *  Inform the stack about the status of checksum so that stack
 1896  *  doesn't spend time verifying the checksum.
 1897  *
 1898  *********************************************************************/
 1899 void
ixgb_receive_checksum(struct ixgb_softc *sc,
 1901                       struct ixgb_rx_desc *rx_desc,
 1902                       struct mbuf *mp)
 1903 {
 1904         if (rx_desc->status & IXGB_RX_DESC_STATUS_IXSM) {
mp->m_pkthdr.csum_flags = 0;
 1906                 return;
 1907         }
 1909         if (rx_desc->status & IXGB_RX_DESC_STATUS_IPCS) {
 1910                 /* Did it pass? */
 1911                 if (!(rx_desc->errors & IXGB_RX_DESC_ERRORS_IPE)) {
 1912                         /* IP Checksum Good */
mp->m_pkthdr.csum_flags = M_IPV4_CSUM_IN_OK;
 1915                 } else {
mp->m_pkthdr.csum_flags = 0;
 1917                 }
 1918         }
 1919         if (rx_desc->status & IXGB_RX_DESC_STATUS_TCPCS) {
 1920                 /* Did it pass? */
 1921                 if (!(rx_desc->errors & IXGB_RX_DESC_ERRORS_TCPE)) {
mp->m_pkthdr.csum_flags |=
M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK;
 1924                 }
 1925         }
 1926 }
 1928 void
ixgb_enable_intr(struct ixgb_softc *sc)
 1930 {
IXGB_WRITE_REG(&sc->hw, IMS, (IXGB_INT_RXT0 | IXGB_INT_TXDW |
IXGB_INT_RXDMT0 | IXGB_INT_LSC | IXGB_INT_RXO));
 1933 }
 1935 void
ixgb_disable_intr(struct ixgb_softc *sc)
 1937 {
IXGB_WRITE_REG(&sc->hw, IMC, ~0);
 1939 }
 1941 void
ixgb_write_pci_cfg(struct ixgb_hw *hw,
uint32_t reg,
uint16_t *value)
 1945 {
 1946         struct pci_attach_args *pa = &((struct ixgb_osdep *)hw->back)->ixgb_pa;
pci_chipset_tag_t pc = pa->pa_pc;
 1948         /* Should we do read/mask/write...?  16 vs 32 bit!!! */
pci_conf_write(pc, pa->pa_tag, reg, *value);
 1950 }
 1952 /**********************************************************************
 1953  *
 1954  *  Update the board statistics counters.
 1955  *
 1956  **********************************************************************/
 1957 void
ixgb_update_stats_counters(struct ixgb_softc *sc)
 1959 {
 1960         struct ifnet   *ifp;
sc->stats.crcerrs += IXGB_READ_REG(&sc->hw, CRCERRS);
sc->stats.gprcl += IXGB_READ_REG(&sc->hw, GPRCL);
sc->stats.gprch += IXGB_READ_REG(&sc->hw, GPRCH);
sc->stats.gorcl += IXGB_READ_REG(&sc->hw, GORCL);
sc->stats.gorch += IXGB_READ_REG(&sc->hw, GORCH);
sc->stats.bprcl += IXGB_READ_REG(&sc->hw, BPRCL);
sc->stats.bprch += IXGB_READ_REG(&sc->hw, BPRCH);
sc->stats.mprcl += IXGB_READ_REG(&sc->hw, MPRCL);
sc->stats.mprch += IXGB_READ_REG(&sc->hw, MPRCH);
sc->stats.roc += IXGB_READ_REG(&sc->hw, ROC);
sc->stats.mpc += IXGB_READ_REG(&sc->hw, MPC);
sc->stats.dc += IXGB_READ_REG(&sc->hw, DC);
sc->stats.rlec += IXGB_READ_REG(&sc->hw, RLEC);
sc->stats.xonrxc += IXGB_READ_REG(&sc->hw, XONRXC);
sc->stats.xontxc += IXGB_READ_REG(&sc->hw, XONTXC);
sc->stats.xoffrxc += IXGB_READ_REG(&sc->hw, XOFFRXC);
sc->stats.xofftxc += IXGB_READ_REG(&sc->hw, XOFFTXC);
sc->stats.gptcl += IXGB_READ_REG(&sc->hw, GPTCL);
sc->stats.gptch += IXGB_READ_REG(&sc->hw, GPTCH);
sc->stats.gotcl += IXGB_READ_REG(&sc->hw, GOTCL);
sc->stats.gotch += IXGB_READ_REG(&sc->hw, GOTCH);
sc->stats.ruc += IXGB_READ_REG(&sc->hw, RUC);
sc->stats.rfc += IXGB_READ_REG(&sc->hw, RFC);
sc->stats.rjc += IXGB_READ_REG(&sc->hw, RJC);
sc->stats.torl += IXGB_READ_REG(&sc->hw, TORL);
sc->stats.torh += IXGB_READ_REG(&sc->hw, TORH);
sc->stats.totl += IXGB_READ_REG(&sc->hw, TOTL);
sc->stats.toth += IXGB_READ_REG(&sc->hw, TOTH);
sc->stats.tprl += IXGB_READ_REG(&sc->hw, TPRL);
sc->stats.tprh += IXGB_READ_REG(&sc->hw, TPRH);
sc->stats.tptl += IXGB_READ_REG(&sc->hw, TPTL);
sc->stats.tpth += IXGB_READ_REG(&sc->hw, TPTH);
sc->stats.plt64c += IXGB_READ_REG(&sc->hw, PLT64C);
sc->stats.mptcl += IXGB_READ_REG(&sc->hw, MPTCL);
sc->stats.mptch += IXGB_READ_REG(&sc->hw, MPTCH);
sc->stats.bptcl += IXGB_READ_REG(&sc->hw, BPTCL);
sc->stats.bptch += IXGB_READ_REG(&sc->hw, BPTCH);
sc->stats.uprcl += IXGB_READ_REG(&sc->hw, UPRCL);
sc->stats.uprch += IXGB_READ_REG(&sc->hw, UPRCH);
sc->stats.vprcl += IXGB_READ_REG(&sc->hw, VPRCL);
sc->stats.vprch += IXGB_READ_REG(&sc->hw, VPRCH);
sc->stats.jprcl += IXGB_READ_REG(&sc->hw, JPRCL);
sc->stats.jprch += IXGB_READ_REG(&sc->hw, JPRCH);
sc->stats.rnbc += IXGB_READ_REG(&sc->hw, RNBC);
sc->stats.icbc += IXGB_READ_REG(&sc->hw, ICBC);
sc->stats.ecbc += IXGB_READ_REG(&sc->hw, ECBC);
sc->stats.uptcl += IXGB_READ_REG(&sc->hw, UPTCL);
sc->stats.uptch += IXGB_READ_REG(&sc->hw, UPTCH);
sc->stats.vptcl += IXGB_READ_REG(&sc->hw, VPTCL);
sc->stats.vptch += IXGB_READ_REG(&sc->hw, VPTCH);
sc->stats.jptcl += IXGB_READ_REG(&sc->hw, JPTCL);
sc->stats.jptch += IXGB_READ_REG(&sc->hw, JPTCH);
sc->stats.tsctc += IXGB_READ_REG(&sc->hw, TSCTC);
sc->stats.tsctfc += IXGB_READ_REG(&sc->hw, TSCTFC);
sc->stats.ibic += IXGB_READ_REG(&sc->hw, IBIC);
sc->stats.lfc += IXGB_READ_REG(&sc->hw, LFC);
sc->stats.pfrc += IXGB_READ_REG(&sc->hw, PFRC);
sc->stats.pftc += IXGB_READ_REG(&sc->hw, PFTC);
sc->stats.mcfrc += IXGB_READ_REG(&sc->hw, MCFRC);
ifp = &sc->interface_data.ac_if;
 2026         /* Fill out the OS statistics structure */
ifp->if_collisions = 0;
 2029         /* Rx Errors */
ifp->if_ierrors =
sc->dropped_pkts +
sc->stats.crcerrs +
sc->stats.rnbc +
sc->stats.mpc +
sc->stats.rlec;
 2037         /* Tx Errors */
ifp->if_oerrors =
sc->watchdog_events;
 2040 }
 2042 /**********************************************************************
 2043  *
 2044  *  This routine is called only when ixgb_display_debug_stats is enabled.
 2045  *  This routine provides a way to take a look at important statistics
 2046  *  maintained by the driver and hardware.
 2047  *
 2048  **********************************************************************/
 2049 void
ixgb_print_hw_stats(struct ixgb_softc *sc)
 2051 {
 2052         char            buf_speed[100], buf_type[100];
ixgb_bus_speed  bus_speed;
ixgb_bus_type   bus_type;
 2055         const char * const unit = sc->sc_dv.dv_xname;
bus_speed = sc->hw.bus.speed;
bus_type = sc->hw.bus.type;
snprintf(buf_speed, sizeof(buf_speed),
bus_speed == ixgb_bus_speed_33 ? "33MHz" :
bus_speed == ixgb_bus_speed_66 ? "66MHz" :
bus_speed == ixgb_bus_speed_100 ? "100MHz" :
bus_speed == ixgb_bus_speed_133 ? "133MHz" :
 2064                 "UNKNOWN");
printf("%s: PCI_Bus_Speed = %s\n", unit,
buf_speed);
snprintf(buf_type, sizeof(buf_type),
bus_type == ixgb_bus_type_pci ? "PCI" :
bus_type == ixgb_bus_type_pcix ? "PCI-X" :
 2071                 "UNKNOWN");
printf("%s: PCI_Bus_Type = %s\n", unit,
buf_type);
printf("%s: Tx Descriptors not Avail1 = %ld\n", unit,
sc->no_tx_desc_avail1);
printf("%s: Tx Descriptors not Avail2 = %ld\n", unit,
sc->no_tx_desc_avail2);
printf("%s: Std Mbuf Failed = %ld\n", unit,
sc->mbuf_alloc_failed);
printf("%s: Std Cluster Failed = %ld\n", unit,
sc->mbuf_cluster_failed);
printf("%s: Defer count = %lld\n", unit,
 2085                 (long long)sc->stats.dc);
printf("%s: Missed Packets = %lld\n", unit,
 2087                 (long long)sc->stats.mpc);
printf("%s: Receive No Buffers = %lld\n", unit,
 2089                 (long long)sc->stats.rnbc);
printf("%s: Receive length errors = %lld\n", unit,
 2091                 (long long)sc->stats.rlec);
printf("%s: Crc errors = %lld\n", unit,
 2093                 (long long)sc->stats.crcerrs);
printf("%s: Driver dropped packets = %ld\n", unit,
sc->dropped_pkts);
printf("%s: XON Rcvd = %lld\n", unit,
 2098                 (long long)sc->stats.xonrxc);
printf("%s: XON Xmtd = %lld\n", unit,
 2100                 (long long)sc->stats.xontxc);
printf("%s: XOFF Rcvd = %lld\n", unit,
 2102                 (long long)sc->stats.xoffrxc);
printf("%s: XOFF Xmtd = %lld\n", unit,
 2104                 (long long)sc->stats.xofftxc);
printf("%s: Good Packets Rcvd = %lld\n", unit,
 2107                 (long long)sc->stats.gprcl);
printf("%s: Good Packets Xmtd = %lld\n", unit,
 2109                 (long long)sc->stats.gptcl);
printf("%s: Jumbo frames recvd = %lld\n", unit,
 2112                 (long long)sc->stats.jprcl);
printf("%s: Jumbo frames Xmtd = %lld\n", unit,
 2114                 (long long)sc->stats.jptcl);
 2115 }