1 /*******************************************************************************
2
3 Copyright (c) 2001-2005, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 *******************************************************************************/
33
34 /* $OpenBSD: ixgb_hw.c,v 1.2 2006/06/22 04:50:31 brad Exp $ */
35
36 /* ixgb_hw.c
37 * Shared functions for accessing and configuring the adapter
38 */
39
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/sockio.h>
43 #include <sys/mbuf.h>
44 #include <sys/malloc.h>
45 #include <sys/kernel.h>
46 #include <sys/device.h>
47 #include <sys/socket.h>
48
49 #include <net/if.h>
50 #include <net/if_dl.h>
51 #include <net/if_media.h>
52
53 #ifdef INET
54 #include <netinet/in.h>
55 #include <netinet/in_systm.h>
56 #include <netinet/in_var.h>
57 #include <netinet/ip.h>
58 #include <netinet/if_ether.h>
59 #endif
60
61 #include <uvm/uvm_extern.h>
62
63 #include <dev/pci/pcireg.h>
64 #include <dev/pci/pcivar.h>
65 #include <dev/pci/pcidevs.h>
66
67 #include <dev/pci/ixgb_hw.h>
68 #include <dev/pci/ixgb_ids.h>
69
70 /* Local function prototypes */
71
72 static uint32_t ixgb_hash_mc_addr(struct ixgb_hw *hw, uint8_t *mc_addr);
73
74 static void ixgb_mta_set(struct ixgb_hw *hw, uint32_t hash_value);
75
76 static void ixgb_get_bus_info(struct ixgb_hw *hw);
77
78 static boolean_t ixgb_link_reset(struct ixgb_hw *hw);
79
80 static void ixgb_optics_reset(struct ixgb_hw *hw);
81
82 static ixgb_phy_type ixgb_identify_phy(struct ixgb_hw *hw);
83
84 uint32_t ixgb_mac_reset(struct ixgb_hw *hw);
85
86 uint32_t
87 ixgb_mac_reset(struct ixgb_hw *hw)
88 {
89 uint32_t ctrl_reg;
90
91 ctrl_reg = IXGB_CTRL0_RST |
92 IXGB_CTRL0_SDP3_DIR | /* All pins are Output=1 */
93 IXGB_CTRL0_SDP2_DIR |
94 IXGB_CTRL0_SDP1_DIR |
95 IXGB_CTRL0_SDP0_DIR |
96 IXGB_CTRL0_SDP3 | /* Initial value 1101 */
97 IXGB_CTRL0_SDP2 |
98 IXGB_CTRL0_SDP0;
99
100 #ifdef HP_ZX1
101 /* Workaround for 82597EX reset errata */
102 IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg);
103 #else
104 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
105 #endif
106
107 /* Delay a few ms just to allow the reset to complete */
108 msec_delay(IXGB_DELAY_AFTER_RESET);
109 ctrl_reg = IXGB_READ_REG(hw, CTRL0);
110 #ifdef DBG
111 /* Make sure the self-clearing global reset bit did self clear */
112 ASSERT(!(ctrl_reg & IXGB_CTRL0_RST));
113 #endif
114
115 if(hw->phy_type == ixgb_phy_type_txn17401) {
116 ixgb_optics_reset(hw);
117 }
118
119 return ctrl_reg;
120 }
121
122 /******************************************************************************
123 * Reset the transmit and receive units; mask and clear all interrupts.
124 *
125 * hw - Struct containing variables accessed by shared code
126 *****************************************************************************/
127 boolean_t
128 ixgb_adapter_stop(struct ixgb_hw *hw)
129 {
130 uint32_t ctrl_reg;
131 uint32_t icr_reg;
132
133 DEBUGFUNC("ixgb_adapter_stop");
134
135 /* If we are stopped or resetting exit gracefully and wait to be
136 * started again before accessing the hardware. */
137 if(hw->adapter_stopped) {
138 DEBUGOUT("Exiting because the adapter is already stopped!!!\n");
139 return FALSE;
140 }
141
142 /* Set the Adapter Stopped flag so other driver functions stop touching
143 * the Hardware. */
144 hw->adapter_stopped = TRUE;
145
146 /* Clear interrupt mask to stop board from generating interrupts */
147 DEBUGOUT("Masking off all interrupts\n");
148 IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF);
149
150 /* Disable the Transmit and Receive units. Then delay to allow any
151 * pending transactions to complete before we hit the MAC with the
152 * global reset. */
153 IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN);
154 IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN);
155 msec_delay(IXGB_DELAY_BEFORE_RESET);
156
157 /* Issue a global reset to the MAC. This will reset the chip's
158 * transmit, receive, DMA, and link units. It will not effect the
159 * current PCI configuration. The global reset bit is self- clearing,
160 * and should clear within a microsecond. */
161 DEBUGOUT("Issuing a global reset to MAC\n");
162
163 ctrl_reg = ixgb_mac_reset(hw);
164
165 /* Clear interrupt mask to stop board from generating interrupts */
166 DEBUGOUT("Masking off all interrupts\n");
167 IXGB_WRITE_REG(hw, IMC, 0xffffffff);
168
169 /* Clear any pending interrupt events. */
170 icr_reg = IXGB_READ_REG(hw, ICR);
171
172 return (ctrl_reg & IXGB_CTRL0_RST);
173 }
174
175 /******************************************************************************
176 * Identifies the vendor of the optics module on the adapter. The SR adapters
177 * support two different types of XPAK optics, so it is necessary to determine
178 * which optics are present before applying any optics-specific workarounds.
179 *
180 * hw - Struct containing variables accessed by shared code.
181 *
182 * Returns: the vendor of the XPAK optics module.
183 *****************************************************************************/
184 static ixgb_xpak_vendor
185 ixgb_identify_xpak_vendor(struct ixgb_hw *hw)
186 {
187 uint32_t i;
188 uint16_t vendor_name[5];
189 ixgb_xpak_vendor xpak_vendor;
190
191 DEBUGFUNC("ixgb_identify_xpak_vendor");
192
193 /* Read the first few bytes of the vendor string from the XPAK NVR
194 * registers. These are standard XENPAK/XPAK registers, so all XPAK
195 * devices should implement them. */
196 for(i = 0; i < 5; i++) {
197 vendor_name[i] =
198 ixgb_read_phy_reg(hw, MDIO_PMA_PMD_XPAK_VENDOR_NAME + i,
199 IXGB_PHY_ADDRESS, MDIO_PMA_PMD_DID);
200 }
201
202 /* Determine the actual vendor */
203 if (vendor_name[0] == 'I' &&
204 vendor_name[1] == 'N' &&
205 vendor_name[2] == 'T' &&
206 vendor_name[3] == 'E' &&
207 vendor_name[4] == 'L') {
208 xpak_vendor = ixgb_xpak_vendor_intel;
209 }
210 else {
211 xpak_vendor = ixgb_xpak_vendor_infineon;
212 }
213 return (xpak_vendor);
214 }
215
216 /******************************************************************************
217 * Determine the physical layer module on the adapter.
218 *
219 * hw - Struct containing variables accessed by shared code. The device_id
220 * field must be (correctly) populated before calling this routine.
221 *
222 * Returns: the phy type of the adapter.
223 *****************************************************************************/
224 static ixgb_phy_type
225 ixgb_identify_phy(struct ixgb_hw *hw)
226 {
227 ixgb_phy_type phy_type;
228 ixgb_xpak_vendor xpak_vendor;
229
230 DEBUGFUNC("ixgb_identify_phy");
231
232 /* Infer the transceiver/phy type from the device id */
233 switch(hw->device_id) {
234 case IXGB_DEVICE_ID_82597EX:
235 DEBUGOUT("Identified TXN17401 optics\n");
236 phy_type = ixgb_phy_type_txn17401;
237 break;
238
239 case IXGB_DEVICE_ID_82597EX_SR:
240 /* The SR adapters carry two different types of XPAK optics
241 * modules; read the vendor identifier to determine the exact
242 * type of optics. */
243 xpak_vendor = ixgb_identify_xpak_vendor(hw);
244 if(xpak_vendor == ixgb_xpak_vendor_intel) {
245 DEBUGOUT("Identified TXN17201 optics\n");
246 phy_type = ixgb_phy_type_txn17201;
247 } else {
248 DEBUGOUT("Identified G6005 optics\n");
249 phy_type = ixgb_phy_type_g6005;
250 }
251 break;
252
253 case IXGB_DEVICE_ID_82597EX_LR:
254 DEBUGOUT("Identified G6104 optics\n");
255 phy_type = ixgb_phy_type_g6104;
256 break;
257
258 case IXGB_DEVICE_ID_82597EX_CX4:
259 DEBUGOUT("Identified CX4\n");
260 xpak_vendor = ixgb_identify_xpak_vendor(hw);
261 if(xpak_vendor == ixgb_xpak_vendor_intel) {
262 DEBUGOUT("Identified TXN17201 optics\n");
263 phy_type = ixgb_phy_type_txn17201;
264 } else {
265 DEBUGOUT("Identified G6005 optics\n");
266 phy_type = ixgb_phy_type_g6005;
267 }
268 break;
269
270 default:
271 DEBUGOUT("Unknown physical layer module\n");
272 phy_type = ixgb_phy_type_unknown;
273 break;
274 }
275
276 return (phy_type);
277 }
278
279 /******************************************************************************
280 * Performs basic configuration of the adapter.
281 *
282 * hw - Struct containing variables accessed by shared code
283 *
284 * Resets the controller.
285 * Reads and validates the EEPROM.
286 * Initializes the receive address registers.
287 * Initializes the multicast table.
288 * Clears all on-chip counters.
289 * Calls routine to setup flow control settings.
290 * Leaves the transmit and receive units disabled and uninitialized.
291 *
292 * Returns:
293 * TRUE if successful,
294 * FALSE if unrecoverable problems were encountered.
295 *****************************************************************************/
296 boolean_t
297 ixgb_init_hw(struct ixgb_hw *hw)
298 {
299 uint32_t i;
300 uint32_t ctrl_reg;
301 boolean_t status;
302
303 DEBUGFUNC("ixgb_init_hw");
304
305 /* Issue a global reset to the MAC. This will reset the chip's
306 * transmit, receive, DMA, and link units. It will not effect the
307 * current PCI configuration. The global reset bit is self- clearing,
308 * and should clear within a microsecond. */
309 DEBUGOUT("Issuing a global reset to MAC\n");
310
311 ctrl_reg = ixgb_mac_reset(hw);
312
313 DEBUGOUT("Issuing an EE reset to MAC\n");
314 #ifdef HP_ZX1
315 /* Workaround for 82597EX reset errata */
316 IXGB_WRITE_REG_IO(hw, CTRL1, IXGB_CTRL1_EE_RST);
317 #else
318 IXGB_WRITE_REG(hw, CTRL1, IXGB_CTRL1_EE_RST);
319 #endif
320
321 /* Delay a few ms just to allow the reset to complete */
322 msec_delay(IXGB_DELAY_AFTER_EE_RESET);
323
324 if(ixgb_get_eeprom_data(hw) == FALSE) {
325 return (FALSE);
326 }
327
328 /* Use the device id to determine the type of phy/transceiver. */
329 hw->device_id = ixgb_get_ee_device_id(hw);
330 hw->phy_type = ixgb_identify_phy(hw);
331
332 /* Setup the receive addresses. Receive Address Registers (RARs 0 -
333 * 15). */
334 ixgb_init_rx_addrs(hw);
335
336 /*
337 * Check that a valid MAC address has been set.
338 * If it is not valid, we fail hardware init.
339 */
340 if(!mac_addr_valid(hw->curr_mac_addr)) {
341 DEBUGOUT("MAC address invalid after ixgb_init_rx_addrs\n");
342 return (FALSE);
343 }
344
345 /* tell the routines in this file they can access hardware again */
346 hw->adapter_stopped = FALSE;
347
348 /* Fill in the bus_info structure */
349 ixgb_get_bus_info(hw);
350
351 /* Zero out the Multicast HASH table */
352 DEBUGOUT("Zeroing the MTA\n");
353 for(i = 0; i < IXGB_MC_TBL_SIZE; i++)
354 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
355
356 /* Zero out the VLAN Filter Table Array */
357 ixgb_clear_vfta(hw);
358
359 /* Zero all of the hardware counters */
360 ixgb_clear_hw_cntrs(hw);
361
362 /* Call a subroutine to setup flow control. */
363 status = ixgb_setup_fc(hw);
364
365 /* 82597EX errata: Call check-for-link in case lane deskew is locked */
366 ixgb_check_for_link(hw);
367
368 return (status);
369 }
370
371 /******************************************************************************
372 * Initializes receive address filters.
373 *
374 * hw - Struct containing variables accessed by shared code
375 *
376 * Places the MAC address in receive address register 0 and clears the rest
377 * of the receive addresss registers. Clears the multicast table. Assumes
378 * the receiver is in reset when the routine is called.
379 *****************************************************************************/
380 void
381 ixgb_init_rx_addrs(struct ixgb_hw *hw)
382 {
383 uint32_t i;
384
385 DEBUGFUNC("ixgb_init_rx_addrs");
386
387 /*
388 * If the current mac address is valid, assume it is a software override
389 * to the permanent address.
390 * Otherwise, use the permanent address from the eeprom.
391 */
392 if(!mac_addr_valid(hw->curr_mac_addr)) {
393
394 /* Get the MAC address from the eeprom for later reference */
395 ixgb_get_ee_mac_addr(hw, hw->curr_mac_addr);
396
397 DEBUGOUT3(" Keeping Permanent MAC Addr =%.2X %.2X %.2X ",
398 hw->curr_mac_addr[0], hw->curr_mac_addr[1],
399 hw->curr_mac_addr[2]);
400 DEBUGOUT3("%.2X %.2X %.2X\n", hw->curr_mac_addr[3],
401 hw->curr_mac_addr[4], hw->curr_mac_addr[5]);
402 } else {
403
404 /* Setup the receive address. */
405 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
406 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
407 hw->curr_mac_addr[0], hw->curr_mac_addr[1],
408 hw->curr_mac_addr[2]);
409 DEBUGOUT3("%.2X %.2X %.2X\n", hw->curr_mac_addr[3],
410 hw->curr_mac_addr[4], hw->curr_mac_addr[5]);
411
412 ixgb_rar_set(hw, hw->curr_mac_addr, 0);
413 }
414
415 /* Zero out the other 15 receive addresses. */
416 DEBUGOUT("Clearing RAR[1-15]\n");
417 for(i = 1; i < IXGB_RAR_ENTRIES; i++) {
418 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
419 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
420 }
421
422 return;
423 }
424
425 /******************************************************************************
426 * Updates the MAC's list of multicast addresses.
427 *
428 * hw - Struct containing variables accessed by shared code
429 * mc_addr_list - the list of new multicast addresses
430 * mc_addr_count - number of addresses
431 * pad - number of bytes between addresses in the list
432 *
433 * The given list replaces any existing list. Clears the last 15 receive
434 * address registers and the multicast table. Uses receive address registers
435 * for the first 15 multicast addresses, and hashes the rest into the
436 * multicast table.
437 *****************************************************************************/
438 void
439 ixgb_mc_addr_list_update(struct ixgb_hw *hw, uint8_t *mc_addr_list,
440 uint32_t mc_addr_count, uint32_t pad)
441 {
442 uint32_t hash_value;
443 uint32_t i;
444 uint32_t rar_used_count = 1; /* RAR[0] is used for our MAC address */
445
446 DEBUGFUNC("ixgb_mc_addr_list_update");
447
448 /* Set the new number of MC addresses that we are being requested to
449 * use. */
450 hw->num_mc_addrs = mc_addr_count;
451
452 /* Clear RAR[1-15] */
453 DEBUGOUT(" Clearing RAR[1-15]\n");
454 for(i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) {
455 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
456 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
457 }
458
459 /* Clear the MTA */
460 DEBUGOUT(" Clearing MTA\n");
461 for(i = 0; i < IXGB_MC_TBL_SIZE; i++) {
462 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
463 }
464
465 /* Add the new addresses */
466 for(i = 0; i < mc_addr_count; i++) {
467 DEBUGOUT(" Adding the multicast addresses:\n");
468 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
469 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)],
470 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 1],
471 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 2],
472 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 3],
473 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 4],
474 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 5]);
475
476 /* Place this multicast address in the RAR if there is room, *
477 * else put it in the MTA */
478 if(rar_used_count < IXGB_RAR_ENTRIES) {
479 ixgb_rar_set(hw,
480 mc_addr_list +
481 (i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)),
482 rar_used_count);
483 DEBUGOUT1("Added a multicast address to RAR[%d]\n", i);
484 rar_used_count++;
485 } else {
486 hash_value =
487 ixgb_hash_mc_addr(hw,
488 mc_addr_list +
489 (i *
490 (IXGB_ETH_LENGTH_OF_ADDRESS +
491 pad)));
492
493 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
494
495 ixgb_mta_set(hw, hash_value);
496 }
497 }
498
499 DEBUGOUT("MC Update Complete\n");
500 return;
501 }
502
503 /******************************************************************************
504 * Hashes an address to determine its location in the multicast table
505 *
506 * hw - Struct containing variables accessed by shared code
507 * mc_addr - the multicast address to hash
508 *
509 * Returns:
510 * The hash value
511 *****************************************************************************/
512 static uint32_t
513 ixgb_hash_mc_addr(struct ixgb_hw *hw, uint8_t *mc_addr)
514 {
515 uint32_t hash_value = 0;
516
517 DEBUGFUNC("ixgb_hash_mc_addr");
518
519 /* The portion of the address that is used for the hash table is
520 * determined by the mc_filter_type setting. */
521 switch(hw->mc_filter_type) {
522 /* [0] [1] [2] [3] [4] [5] 01 AA 00 12 34 56 LSB MSB -
523 * According to H/W docs */
524 case 0:
525 /* [47:36] i.e. 0x563 for above example address */
526 hash_value =
527 ((mc_addr[4] >> 4) | (((uint16_t)mc_addr[5]) << 4));
528 break;
529 case 1: /* [46:35] i.e. 0xAC6 for above
530 * example address */
531 hash_value =
532 ((mc_addr[4] >> 3) | (((uint16_t)mc_addr[5]) << 5));
533 break;
534 case 2: /* [45:34] i.e. 0x5D8 for above
535 * example address */
536 hash_value =
537 ((mc_addr[4] >> 2) | (((uint16_t)mc_addr[5]) << 6));
538 break;
539 case 3: /* [43:32] i.e. 0x634 for above
540 * example address */
541 hash_value = ((mc_addr[4]) | (((uint16_t)mc_addr[5]) << 8));
542 break;
543 default:
544 /* Invalid mc_filter_type, what should we do? */
545 DEBUGOUT("MC filter type param set incorrectly\n");
546 ASSERT(0);
547 break;
548 }
549
550 hash_value &= 0xFFF;
551 return (hash_value);
552 }
553
554 /******************************************************************************
555 * Sets the bit in the multicast table corresponding to the hash value.
556 *
557 * hw - Struct containing variables accessed by shared code
558 * hash_value - Multicast address hash value
559 *****************************************************************************/
560 static void
561 ixgb_mta_set(struct ixgb_hw *hw, uint32_t hash_value)
562 {
563 uint32_t hash_bit, hash_reg;
564 uint32_t mta_reg;
565
566 /* The MTA is a register array of 128 32-bit registers. It is treated
567 * like an array of 4096 bits. We want to set bit
568 * BitArray[hash_value]. So we figure out what register the bit is in,
569 * read it, OR in the new bit, then write back the new value. The
570 * register is determined by the upper 7 bits of the hash value and the
571 * bit within that register are determined by the lower 5 bits of the
572 * value. */
573 hash_reg = (hash_value >> 5) & 0x7F;
574 hash_bit = hash_value & 0x1F;
575 mta_reg = IXGB_READ_REG_ARRAY(hw, MTA, hash_reg);
576 mta_reg |= (1 << hash_bit);
577 IXGB_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta_reg);
578 return;
579 }
580
581 /******************************************************************************
582 * Puts an ethernet address into a receive address register.
583 *
584 * hw - Struct containing variables accessed by shared code
585 * addr - Address to put into receive address register
586 * index - Receive address register to write
587 *****************************************************************************/
588 void
589 ixgb_rar_set(struct ixgb_hw *hw, uint8_t *addr, uint32_t index)
590 {
591 uint32_t rar_low, rar_high;
592
593 DEBUGFUNC("ixgb_rar_set");
594
595 /* HW expects these in little endian so we reverse the byte order from
596 * network order (big endian) to little endian */
597 rar_low = ((uint32_t)addr[0] |
598 ((uint32_t)addr[1] << 8) |
599 ((uint32_t)addr[2] << 16) |
600 ((uint32_t)addr[3] << 24));
601
602 rar_high = ((uint32_t)addr[4] |
603 ((uint32_t)addr[5] << 8) |
604 IXGB_RAH_AV);
605
606 IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
607 IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
608 return;
609 }
610
611 /******************************************************************************
612 * Writes a value to the specified offset in the VLAN filter table.
613 *
614 * hw - Struct containing variables accessed by shared code
615 * offset - Offset in VLAN filer table to write
616 * value - Value to write into VLAN filter table
617 *****************************************************************************/
618 void
619 ixgb_write_vfta(struct ixgb_hw *hw, uint32_t offset, uint32_t value)
620 {
621 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value);
622 return;
623 }
624
625 /******************************************************************************
626 * Clears the VLAN filer table
627 *
628 * hw - Struct containing variables accessed by shared code
629 *****************************************************************************/
630 void
631 ixgb_clear_vfta(struct ixgb_hw *hw)
632 {
633 uint32_t offset;
634
635 for(offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++)
636 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
637 return;
638 }
639
640 /******************************************************************************
641 * Configures the flow control settings based on SW configuration.
642 *
643 * hw - Struct containing variables accessed by shared code
644 *****************************************************************************/
645
646 boolean_t
647 ixgb_setup_fc(struct ixgb_hw *hw)
648 {
649 uint32_t ctrl_reg;
650 uint32_t pap_reg = 0; /* by default, assume no pause time */
651 boolean_t status = TRUE;
652
653 DEBUGFUNC("ixgb_setup_fc");
654
655 /* Get the current control reg 0 settings */
656 ctrl_reg = IXGB_READ_REG(hw, CTRL0);
657
658 /* Clear the Receive Pause Enable and Transmit Pause Enable bits */
659 ctrl_reg &= ~(IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
660
661 /* The possible values of the "flow_control" parameter are:
662 * 0: Flow control is completely disabled
663 * 1: Rx flow control is enabled (we can receive pause frames but not send
664 * pause frames).
665 * 2: Tx flow control is enabled (we can send pause frames but we do not
666 * support receiving pause frames)
667 * 3: Both Rx and TX flow control (symmetric) are enabled.
668 * other: Invalid. */
669 switch(hw->fc.type) {
670 case ixgb_fc_none: /* 0 */
671 /* Set CMDC bit to disable Rx Flow control */
672 ctrl_reg |= (IXGB_CTRL0_CMDC);
673 break;
674 case ixgb_fc_rx_pause: /* 1 */
675 /* RX Flow control is enabled, and TX Flow control is disabled. */
676 ctrl_reg |= (IXGB_CTRL0_RPE);
677 break;
678 case ixgb_fc_tx_pause: /* 2 */
679 /* TX Flow control is enabled, and RX Flow control is disabled,
680 * by a software over-ride. */
681 ctrl_reg |= (IXGB_CTRL0_TPE);
682 pap_reg = hw->fc.pause_time;
683 break;
684 case ixgb_fc_full: /* 3 */
685 /* Flow control (both RX and TX) is enabled by a software
686 * over-ride. */
687 ctrl_reg |= (IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
688 pap_reg = hw->fc.pause_time;
689 break;
690 default:
691 /* We should never get here. The value should be 0-3. */
692 DEBUGOUT("Flow control param set incorrectly\n");
693 ASSERT(0);
694 break;
695 }
696
697 /* Write the new settings */
698 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
699
700 if(pap_reg != 0) {
701 IXGB_WRITE_REG(hw, PAP, pap_reg);
702 }
703
704 /* Set the flow control receive threshold registers. Normally, these
705 * registers will be set to a default threshold that may be adjusted
706 * later by the driver's runtime code. However, if the ability to
707 * transmit pause frames in not enabled, then these registers will be
708 * set to 0. */
709 if(!(hw->fc.type & ixgb_fc_tx_pause)) {
710 IXGB_WRITE_REG(hw, FCRTL, 0);
711 IXGB_WRITE_REG(hw, FCRTH, 0);
712 } else {
713 /* We need to set up the Receive Threshold high and low water
714 * marks as well as (optionally) enabling the transmission of
715 * XON frames. */
716 if(hw->fc.send_xon) {
717 IXGB_WRITE_REG(hw, FCRTL,
718 (hw->fc.low_water | IXGB_FCRTL_XONE));
719 } else {
720 IXGB_WRITE_REG(hw, FCRTL, hw->fc.low_water);
721 }
722 IXGB_WRITE_REG(hw, FCRTH, hw->fc.high_water);
723 }
724 return (status);
725 }
726
727 /******************************************************************************
728 * Reads a word from a device over the Management Data Interface (MDI) bus.
729 * This interface is used to manage Physical layer devices.
730 *
731 * hw - Struct containing variables accessed by hw code
732 * reg_address - Offset of device register being read.
733 * phy_address - Address of device on MDI.
734 *
735 * Returns: Data word (16 bits) from MDI device.
736 *
737 * The 82597EX has support for several MDI access methods. This routine
738 * uses the new protocol MDI Single Command and Address Operation.
739 * This requires that first an address cycle command is sent, followed by a
740 * read command.
741 *****************************************************************************/
742 uint16_t
743 ixgb_read_phy_reg(struct ixgb_hw *hw, uint32_t reg_address,
744 uint32_t phy_address, uint32_t device_type)
745 {
746 uint32_t i;
747 uint32_t data;
748 uint32_t command = 0;
749
750 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
751 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
752 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
753
754 /* Setup and write the address cycle command */
755 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
756 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
757 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
758 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
759
760 IXGB_WRITE_REG(hw, MSCA, command);
761
762 /**************************************************************
763 ** Check every 10 usec to see if the address cycle completed
764 ** The COMMAND bit will clear when the operation is complete.
765 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
766 ** from the CPU Write to the Ready bit assertion.
767 **************************************************************/
768
769 for(i = 0; i < 10; i++) {
770 usec_delay(10);
771
772 command = IXGB_READ_REG(hw, MSCA);
773
774 if((command & IXGB_MSCA_MDI_COMMAND) == 0)
775 break;
776 }
777
778 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
779
780 /* Address cycle complete, setup and write the read command */
781 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
782 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
783 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
784 (IXGB_MSCA_READ | IXGB_MSCA_MDI_COMMAND));
785
786 IXGB_WRITE_REG(hw, MSCA, command);
787
788 /**************************************************************
789 ** Check every 10 usec to see if the read command completed
790 ** The COMMAND bit will clear when the operation is complete.
791 ** The read may take as long as 64 usecs (we'll wait 100 usecs max)
792 ** from the CPU Write to the Ready bit assertion.
793 **************************************************************/
794
795 for(i = 0; i < 10; i++) {
796 usec_delay(10);
797
798 command = IXGB_READ_REG(hw, MSCA);
799
800 if((command & IXGB_MSCA_MDI_COMMAND) == 0)
801 break;
802 }
803
804 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
805
806 /* Operation is complete, get the data from the MDIO Read/Write Data
807 * register and return. */
808 data = IXGB_READ_REG(hw, MSRWD);
809 data >>= IXGB_MSRWD_READ_DATA_SHIFT;
810 return ((uint16_t)data);
811 }
812
813 /******************************************************************************
814 * Writes a word to a device over the Management Data Interface (MDI) bus.
815 * This interface is used to manage Physical layer devices.
816 *
817 * hw - Struct containing variables accessed by hw code
818 * reg_address - Offset of device register being read.
819 * phy_address - Address of device on MDI.
820 * device_type - Also known as the Device ID or DID.
821 * data - 16-bit value to be written
822 *
823 * Returns: void.
824 *
825 * The 82597EX has support for several MDI access methods. This routine
826 * uses the new protocol MDI Single Command and Address Operation.
827 * This requires that first an address cycle command is sent, followed by a
828 * write command.
829 *****************************************************************************/
830 void
831 ixgb_write_phy_reg(struct ixgb_hw *hw, uint32_t reg_address,
832 uint32_t phy_address, uint32_t device_type, uint16_t data)
833 {
834 uint32_t i;
835 uint32_t command = 0;
836
837 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
838 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
839 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
840
841 /* Put the data in the MDIO Read/Write Data register */
842 IXGB_WRITE_REG(hw, MSRWD, (uint32_t)data);
843
844 /* Setup and write the address cycle command */
845 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
846 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
847 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
848 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
849
850 IXGB_WRITE_REG(hw, MSCA, command);
851
852 /**************************************************************
853 ** Check every 10 usec to see if the address cycle completed
854 ** The COMMAND bit will clear when the operation is complete.
855 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
856 ** from the CPU Write to the Ready bit assertion.
857 **************************************************************/
858
859 for(i = 0; i < 10; i++) {
860 usec_delay(10);
861
862 command = IXGB_READ_REG(hw, MSCA);
863
864 if((command & IXGB_MSCA_MDI_COMMAND) == 0)
865 break;
866 }
867
868 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
869
870 /* Address cycle complete, setup and write the write command */
871 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
872 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
873 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
874 (IXGB_MSCA_WRITE | IXGB_MSCA_MDI_COMMAND));
875
876 IXGB_WRITE_REG(hw, MSCA, command);
877
878 /**************************************************************
879 ** Check every 10 usec to see if the read command completed
880 ** The COMMAND bit will clear when the operation is complete.
881 ** The write may take as long as 64 usecs (we'll wait 100 usecs max)
882 ** from the CPU Write to the Ready bit assertion.
883 **************************************************************/
884
885 for(i = 0; i < 10; i++) {
886 usec_delay(10);
887
888 command = IXGB_READ_REG(hw, MSCA);
889
890 if((command & IXGB_MSCA_MDI_COMMAND) == 0)
891 break;
892 }
893
894 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
895
896 /* Operation is complete, return. */
897 }
898
899 /******************************************************************************
900 * Checks to see if the link status of the hardware has changed.
901 *
902 * hw - Struct containing variables accessed by hw code
903 *
904 * Called by any function that needs to check the link status of the adapter.
905 *****************************************************************************/
906 void
907 ixgb_check_for_link(struct ixgb_hw *hw)
908 {
909 uint32_t status_reg;
910 uint32_t xpcss_reg;
911
912 DEBUGFUNC("ixgb_check_for_link");
913
914 xpcss_reg = IXGB_READ_REG(hw, XPCSS);
915 status_reg = IXGB_READ_REG(hw, STATUS);
916
917 if((xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
918 (status_reg & IXGB_STATUS_LU)) {
919 hw->link_up = TRUE;
920 } else if(!(xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
921 (status_reg & IXGB_STATUS_LU)) {
922 DEBUGOUT("XPCSS Not Aligned while Status:LU is set.\n");
923 hw->link_up = ixgb_link_reset(hw);
924 } else {
925 /*
926 * 82597EX errata. Since the lane deskew problem may prevent
927 * link, reset the link before reporting link down.
928 */
929 hw->link_up = ixgb_link_reset(hw);
930 }
931 /* Anything else for 10 Gig?? */
932 }
933
934 /******************************************************************************
935 * Check for a bad link condition that may have occured.
936 * The indication is that the RFC / LFC registers may be incrementing
937 * continually. A full adapter reset is required to recover.
938 *
939 * hw - Struct containing variables accessed by hw code
940 *
941 * Called by any function that needs to check the link status of the adapter.
942 *****************************************************************************/
943 boolean_t
944 ixgb_check_for_bad_link(struct ixgb_hw *hw)
945 {
946 uint32_t newLFC, newRFC;
947 boolean_t bad_link_returncode = FALSE;
948
949 if(hw->phy_type == ixgb_phy_type_txn17401) {
950 newLFC = IXGB_READ_REG(hw, LFC);
951 newRFC = IXGB_READ_REG(hw, RFC);
952 if((hw->lastLFC + 250 < newLFC) || (hw->lastRFC + 250 < newRFC)) {
953 DEBUGOUT("BAD LINK! too many LFC/RFC since last check\n");
954 bad_link_returncode = TRUE;
955 }
956 hw->lastLFC = newLFC;
957 hw->lastRFC = newRFC;
958 }
959
960 return bad_link_returncode;
961 }
962
963 /******************************************************************************
964 * Clears all hardware statistics counters.
965 *
966 * hw - Struct containing variables accessed by shared code
967 *****************************************************************************/
968 void
969 ixgb_clear_hw_cntrs(struct ixgb_hw *hw)
970 {
971 volatile uint32_t temp_reg;
972
973 DEBUGFUNC("ixgb_clear_hw_cntrs");
974
975 /* if we are stopped or resetting exit gracefully */
976 if(hw->adapter_stopped) {
977 DEBUGOUT("Exiting because the adapter is stopped!!!\n");
978 return;
979 }
980
981 temp_reg = IXGB_READ_REG(hw, TPRL);
982 temp_reg = IXGB_READ_REG(hw, TPRH);
983 temp_reg = IXGB_READ_REG(hw, GPRCL);
984 temp_reg = IXGB_READ_REG(hw, GPRCH);
985 temp_reg = IXGB_READ_REG(hw, BPRCL);
986 temp_reg = IXGB_READ_REG(hw, BPRCH);
987 temp_reg = IXGB_READ_REG(hw, MPRCL);
988 temp_reg = IXGB_READ_REG(hw, MPRCH);
989 temp_reg = IXGB_READ_REG(hw, UPRCL);
990 temp_reg = IXGB_READ_REG(hw, UPRCH);
991 temp_reg = IXGB_READ_REG(hw, VPRCL);
992 temp_reg = IXGB_READ_REG(hw, VPRCH);
993 temp_reg = IXGB_READ_REG(hw, JPRCL);
994 temp_reg = IXGB_READ_REG(hw, JPRCH);
995 temp_reg = IXGB_READ_REG(hw, GORCL);
996 temp_reg = IXGB_READ_REG(hw, GORCH);
997 temp_reg = IXGB_READ_REG(hw, TORL);
998 temp_reg = IXGB_READ_REG(hw, TORH);
999 temp_reg = IXGB_READ_REG(hw, RNBC);
1000 temp_reg = IXGB_READ_REG(hw, RUC);
1001 temp_reg = IXGB_READ_REG(hw, ROC);
1002 temp_reg = IXGB_READ_REG(hw, RLEC);
1003 temp_reg = IXGB_READ_REG(hw, CRCERRS);
1004 temp_reg = IXGB_READ_REG(hw, ICBC);
1005 temp_reg = IXGB_READ_REG(hw, ECBC);
1006 temp_reg = IXGB_READ_REG(hw, MPC);
1007 temp_reg = IXGB_READ_REG(hw, TPTL);
1008 temp_reg = IXGB_READ_REG(hw, TPTH);
1009 temp_reg = IXGB_READ_REG(hw, GPTCL);
1010 temp_reg = IXGB_READ_REG(hw, GPTCH);
1011 temp_reg = IXGB_READ_REG(hw, BPTCL);
1012 temp_reg = IXGB_READ_REG(hw, BPTCH);
1013 temp_reg = IXGB_READ_REG(hw, MPTCL);
1014 temp_reg = IXGB_READ_REG(hw, MPTCH);
1015 temp_reg = IXGB_READ_REG(hw, UPTCL);
1016 temp_reg = IXGB_READ_REG(hw, UPTCH);
1017 temp_reg = IXGB_READ_REG(hw, VPTCL);
1018 temp_reg = IXGB_READ_REG(hw, VPTCH);
1019 temp_reg = IXGB_READ_REG(hw, JPTCL);
1020 temp_reg = IXGB_READ_REG(hw, JPTCH);
1021 temp_reg = IXGB_READ_REG(hw, GOTCL);
1022 temp_reg = IXGB_READ_REG(hw, GOTCH);
1023 temp_reg = IXGB_READ_REG(hw, TOTL);
1024 temp_reg = IXGB_READ_REG(hw, TOTH);
1025 temp_reg = IXGB_READ_REG(hw, DC);
1026 temp_reg = IXGB_READ_REG(hw, PLT64C);
1027 temp_reg = IXGB_READ_REG(hw, TSCTC);
1028 temp_reg = IXGB_READ_REG(hw, TSCTFC);
1029 temp_reg = IXGB_READ_REG(hw, IBIC);
1030 temp_reg = IXGB_READ_REG(hw, RFC);
1031 temp_reg = IXGB_READ_REG(hw, LFC);
1032 temp_reg = IXGB_READ_REG(hw, PFRC);
1033 temp_reg = IXGB_READ_REG(hw, PFTC);
1034 temp_reg = IXGB_READ_REG(hw, MCFRC);
1035 temp_reg = IXGB_READ_REG(hw, MCFTC);
1036 temp_reg = IXGB_READ_REG(hw, XONRXC);
1037 temp_reg = IXGB_READ_REG(hw, XONTXC);
1038 temp_reg = IXGB_READ_REG(hw, XOFFRXC);
1039 temp_reg = IXGB_READ_REG(hw, XOFFTXC);
1040 temp_reg = IXGB_READ_REG(hw, RJC);
1041 return;
1042 }
1043
1044 /******************************************************************************
1045 * Turns on the software controllable LED
1046 *
1047 * hw - Struct containing variables accessed by shared code
1048 *****************************************************************************/
1049 void
1050 ixgb_led_on(struct ixgb_hw *hw)
1051 {
1052 uint32_t ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
1053
1054 /* To turn on the LED, clear software-definable pin 0 (SDP0). */
1055 ctrl0_reg &= ~IXGB_CTRL0_SDP0;
1056 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
1057 return;
1058 }
1059
1060 /******************************************************************************
1061 * Turns off the software controllable LED
1062 *
1063 * hw - Struct containing variables accessed by shared code
1064 *****************************************************************************/
1065 void
1066 ixgb_led_off(struct ixgb_hw *hw)
1067 {
1068 uint32_t ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
1069
1070 /* To turn off the LED, set software-definable pin 0 (SDP0). */
1071 ctrl0_reg |= IXGB_CTRL0_SDP0;
1072 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
1073 return;
1074 }
1075
1076 /******************************************************************************
1077 * Gets the current PCI bus type, speed, and width of the hardware
1078 *
1079 * hw - Struct containing variables accessed by shared code
1080 *****************************************************************************/
1081 static void
1082 ixgb_get_bus_info(struct ixgb_hw *hw)
1083 {
1084 uint32_t status_reg;
1085
1086 status_reg = IXGB_READ_REG(hw, STATUS);
1087
1088 hw->bus.type =
1089 (status_reg & IXGB_STATUS_PCIX_MODE) ? ixgb_bus_type_pcix :
1090 ixgb_bus_type_pci;
1091
1092 if(hw->bus.type == ixgb_bus_type_pci) {
1093 hw->bus.speed =
1094 (status_reg & IXGB_STATUS_PCI_SPD) ? ixgb_bus_speed_66 :
1095 ixgb_bus_speed_33;
1096 } else {
1097 switch(status_reg & IXGB_STATUS_PCIX_SPD_MASK) {
1098 case IXGB_STATUS_PCIX_SPD_66:
1099 hw->bus.speed = ixgb_bus_speed_66;
1100 break;
1101 case IXGB_STATUS_PCIX_SPD_100:
1102 hw->bus.speed = ixgb_bus_speed_100;
1103 break;
1104 case IXGB_STATUS_PCIX_SPD_133:
1105 hw->bus.speed = ixgb_bus_speed_133;
1106 break;
1107 default:
1108 hw->bus.speed = ixgb_bus_speed_reserved;
1109 break;
1110 }
1111 }
1112
1113 hw->bus.width =
1114 (status_reg & IXGB_STATUS_BUS64) ? ixgb_bus_width_64 :
1115 ixgb_bus_width_32;
1116
1117 return;
1118 }
1119
1120 /******************************************************************************
1121 * Tests a MAC address to ensure it is a valid Individual Address
1122 *
1123 * mac_addr - pointer to MAC address.
1124 *
1125 *****************************************************************************/
1126 boolean_t
1127 mac_addr_valid(uint8_t *mac_addr)
1128 {
1129 boolean_t is_valid = TRUE;
1130
1131 DEBUGFUNC("mac_addr_valid");
1132
1133 /* Make sure it is not a multicast address */
1134 if(IS_MULTICAST(mac_addr)) {
1135 DEBUGOUT("MAC address is multicast\n");
1136 is_valid = FALSE;
1137 }
1138 /* Not a broadcast address */
1139 else if(IS_BROADCAST(mac_addr)) {
1140 DEBUGOUT("MAC address is broadcast\n");
1141 is_valid = FALSE;
1142 }
1143 /* Reject the zero address */
1144 else if (mac_addr[0] == 0 &&
1145 mac_addr[1] == 0 &&
1146 mac_addr[2] == 0 &&
1147 mac_addr[3] == 0 &&
1148 mac_addr[4] == 0 &&
1149 mac_addr[5] == 0) {
1150 DEBUGOUT("MAC address is all zeros\n");
1151 is_valid = FALSE;
1152 }
1153 return (is_valid);
1154 }
1155
1156 /******************************************************************************
1157 * Resets the 10GbE link. Waits the settle time and returns the state of
1158 * the link.
1159 *
1160 * hw - Struct containing variables accessed by shared code
1161 *****************************************************************************/
1162 boolean_t
1163 ixgb_link_reset(struct ixgb_hw *hw)
1164 {
1165 boolean_t link_status = FALSE;
1166 uint8_t wait_retries = MAX_RESET_ITERATIONS;
1167 uint8_t lrst_retries = MAX_RESET_ITERATIONS;
1168
1169 do {
1170 /* Reset the link */
1171 IXGB_WRITE_REG(hw, CTRL0,
1172 IXGB_READ_REG(hw, CTRL0) | IXGB_CTRL0_LRST);
1173
1174 /* Wait for link-up and lane re-alignment */
1175 do {
1176 usec_delay(IXGB_DELAY_USECS_AFTER_LINK_RESET);
1177 link_status =
1178 ((IXGB_READ_REG(hw, STATUS) & IXGB_STATUS_LU) &&
1179 (IXGB_READ_REG(hw, XPCSS) &
1180 IXGB_XPCSS_ALIGN_STATUS)) ? TRUE : FALSE;
1181 } while(!link_status && --wait_retries);
1182
1183 } while(!link_status && --lrst_retries);
1184
1185 return link_status;
1186 }
1187
1188 /******************************************************************************
1189 * Resets the 10GbE optics module.
1190 *
1191 * hw - Struct containing variables accessed by shared code
1192 *****************************************************************************/
1193 void
1194 ixgb_optics_reset(struct ixgb_hw *hw)
1195 {
1196 if(hw->phy_type == ixgb_phy_type_txn17401) {
1197 uint16_t mdio_reg;
1198
1199 ixgb_write_phy_reg(hw,
1200 MDIO_PMA_PMD_CR1,
1201 IXGB_PHY_ADDRESS,
1202 MDIO_PMA_PMD_DID,
1203 MDIO_PMA_PMD_CR1_RESET);
1204
1205 mdio_reg = ixgb_read_phy_reg(hw,
1206 MDIO_PMA_PMD_CR1,
1207 IXGB_PHY_ADDRESS,
1208 MDIO_PMA_PMD_DID);
1209 }
1210
1211 return;
1212 }