hw 531 dev/audio.c struct audio_hw_if *hw = sc->hw_if;
hw 539 dev/audio.c if (hw->round_buffersize)
hw 540 dev/audio.c bufsize = hw->round_buffersize(hdl, direction, bufsize);
hw 542 dev/audio.c if (hw->allocm)
hw 543 dev/audio.c r->start = hw->allocm(hdl, direction, r->bufsize, M_DEVBUF,
hw 822 dev/audio.c struct audio_hw_if *hw = sc->hw_if;
hw 827 dev/audio.c if (hw->init_input && (sc->sc_mode & AUMODE_RECORD)) {
hw 828 dev/audio.c error = hw->init_input(sc->hw_hdl, sc->sc_rr.start,
hw 836 dev/audio.c if (hw->init_output && (sc->sc_mode & AUMODE_PLAY)) {
hw 837 dev/audio.c error = hw->init_output(sc->hw_hdl, sc->sc_pr.start,
hw 1113 dev/audio.c struct audio_hw_if *hw = sc->hw_if;
hw 1139 dev/audio.c if (!sc->sc_pr.pause && !audio_drain(sc) && hw->drain)
hw 1140 dev/audio.c (void)hw->drain(sc->hw_hdl);
hw 1145 dev/audio.c hw->close(sc->hw_hdl);
hw 1296 dev/audio.c struct audio_hw_if *hw = sc->hw_if;
hw 1316 dev/audio.c if (hw->round_blocksize)
hw 1317 dev/audio.c bs = hw->round_blocksize(sc->hw_hdl, bs);
hw 1565 dev/audio.c struct audio_hw_if *hw = sc->hw_if;
hw 1684 dev/audio.c if (!error && hw->drain)
hw 1685 dev/audio.c error = hw->drain(sc->hw_hdl);
hw 1690 dev/audio.c error = hw->getdev(sc->hw_hdl, (audio_device_t *)addr);
hw 1697 dev/audio.c error = hw->query_encoding(sc->hw_hdl, (struct audio_encoding *)addr);
hw 1708 dev/audio.c if (hw->get_props(sc->hw_hdl) & AUDIO_PROP_FULLDUPLEX) {
hw 1709 dev/audio.c if (hw->setfd)
hw 1710 dev/audio.c error = hw->setfd(sc->hw_hdl, fd);
hw 1725 dev/audio.c *(int *)addr = hw->get_props(sc->hw_hdl);
hw 1794 dev/audio.c struct audio_hw_if *hw = sc->hw_if;
hw 1799 dev/audio.c if (!(hw->get_props(sc->hw_hdl) & AUDIO_PROP_MMAP) || !hw->mappage)
hw 1843 dev/audio.c return hw->mappage(sc->hw_hdl, cb->start, off, prot);
hw 1969 dev/audio.c struct audio_hw_if *hw = sc->hw_if;
hw 1990 dev/audio.c if (!hw->trigger_output)
hw 1991 dev/audio.c (void)hw->start_output(sc->hw_hdl, cb->outp,
hw 2052 dev/audio.c if (!hw->trigger_output) {
hw 2053 dev/audio.c error = hw->start_output(sc->hw_hdl, cb->outp, blksize,
hw 2082 dev/audio.c struct audio_hw_if *hw = sc->hw_if;
hw 2101 dev/audio.c if (!hw->trigger_input)
hw 2102 dev/audio.c (void)hw->start_input(sc->hw_hdl, cb->inp, blksize,
hw 2149 dev/audio.c if (!hw->trigger_input) {
hw 2150 dev/audio.c error = hw->start_input(sc->hw_hdl, cb->inp, blksize,
hw 2468 dev/audio.c struct audio_hw_if *hw = sc->hw_if;
hw 2477 dev/audio.c if (hw == 0) /* HW has not attached */
hw 2562 dev/audio.c int indep = hw->get_props(sc->hw_hdl) & AUDIO_PROP_INDEPENDENT;
hw 2569 dev/audio.c error = hw->set_params(sc->hw_hdl, setmode,
hw 2674 dev/audio.c if (hw->round_blocksize) {
hw 2675 dev/audio.c rbs = hw->round_blocksize(sc->hw_hdl, rbs);
hw 2676 dev/audio.c pbs = hw->round_blocksize(sc->hw_hdl, pbs);
hw 2691 dev/audio.c if (hw->commit_settings) {
hw 2692 dev/audio.c error = hw->commit_settings(sc->hw_hdl);
hw 2765 dev/audio.c struct audio_hw_if *hw = sc->hw_if;
hw 2767 dev/audio.c if (hw == 0) /* HW has not attached */
hw 2903 dev/audio.c struct audio_hw_if *hw = sc->hw_if;
hw 2925 dev/audio.c error = hw->getdev(sc->hw_hdl, (audio_device_t *)addr);
hw 2931 dev/audio.c error = hw->query_devinfo(sc->hw_hdl, (mixer_devinfo_t *)addr);
hw 2936 dev/audio.c error = hw->get_port(sc->hw_hdl, (mixer_ctrl_t *)addr);
hw 2943 dev/audio.c error = hw->set_port(sc->hw_hdl, (mixer_ctrl_t *)addr);
hw 2944 dev/audio.c if (!error && hw->commit_settings)
hw 2945 dev/audio.c error = hw->commit_settings(sc->hw_hdl);
hw 883 dev/ic/rt2560.c int hw;
hw 886 dev/ic/rt2560.c hw = (RAL_READ(sc, RT2560_SECCSR1) - sc->txq.physaddr) /
hw 889 dev/ic/rt2560.c for (; sc->txq.next_encrypt != hw;) {
hw 1081 dev/ic/rt2560.c int hw, error;
hw 1084 dev/ic/rt2560.c hw = (RAL_READ(sc, RT2560_SECCSR0) - sc->rxq.physaddr) /
hw 1087 dev/ic/rt2560.c for (; sc->rxq.cur_decrypt != hw;) {
hw 248 dev/pci/if_em.c sc->hw.autoneg = DO_AUTO_NEG;
hw 249 dev/pci/if_em.c sc->hw.wait_autoneg_complete = WAIT_FOR_AUTO_NEG_DEFAULT;
hw 250 dev/pci/if_em.c sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT;
hw 251 dev/pci/if_em.c sc->hw.tbi_compatibility_en = TRUE;
hw 254 dev/pci/if_em.c sc->hw.phy_init_script = 1;
hw 255 dev/pci/if_em.c sc->hw.phy_reset_disable = FALSE;
hw 258 dev/pci/if_em.c sc->hw.master_slave = em_ms_hw_default;
hw 260 dev/pci/if_em.c sc->hw.master_slave = EM_MASTER_SLAVE;
hw 267 dev/pci/if_em.c sc->hw.report_tx_early = 1;
hw 276 dev/pci/if_em.c em_init_eeprom_params(&sc->hw);
hw 282 dev/pci/if_em.c switch (sc->hw.mac_type) {
hw 291 dev/pci/if_em.c em_read_eeprom(&sc->hw, EEPROM_INIT_3GIO_3,
hw 294 dev/pci/if_em.c sc->hw.max_frame_size = ETHER_MAX_LEN;
hw 302 dev/pci/if_em.c sc->hw.max_frame_size = 9234;
hw 306 dev/pci/if_em.c sc->hw.max_frame_size = ETHER_MAX_LEN;
hw 309 dev/pci/if_em.c sc->hw.max_frame_size =
hw 313 dev/pci/if_em.c sc->hw.min_frame_size =
hw 316 dev/pci/if_em.c if (sc->hw.mac_type >= em_82544)
hw 352 dev/pci/if_em.c if (em_read_mac_addr(&sc->hw) < 0) {
hw 358 dev/pci/if_em.c if (!em_is_valid_ether_addr(sc->hw.mac_addr)) {
hw 363 dev/pci/if_em.c bcopy(sc->hw.mac_addr, sc->interface_data.ac_enaddr,
hw 370 dev/pci/if_em.c em_clear_hw_cntrs(&sc->hw);
hw 372 dev/pci/if_em.c sc->hw.get_link_status = 1;
hw 378 dev/pci/if_em.c if (em_check_phy_reset_block(&sc->hw))
hw 383 dev/pci/if_em.c em_get_bus_info(&sc->hw);
hw 384 dev/pci/if_em.c if (sc->hw.bus_type == em_bus_type_pcix &&
hw 385 dev/pci/if_em.c sc->hw.mac_type == em_82544)
hw 555 dev/pci/if_em.c if (sc->hw.mac_type == em_82542_rev2_0)
hw 564 dev/pci/if_em.c if (em_check_phy_reset_block(&sc->hw)) {
hw 597 dev/pci/if_em.c if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_TXOFF) {
hw 634 dev/pci/if_em.c if (sc->hw.mac_type >= em_82544)
hw 656 dev/pci/if_em.c switch (sc->hw.mac_type) {
hw 659 dev/pci/if_em.c if (sc->hw.max_frame_size > EM_RXBUFFER_8192)
hw 681 dev/pci/if_em.c if (sc->hw.max_frame_size > EM_RXBUFFER_8192)
hw 687 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, PBA, pba);
hw 690 dev/pci/if_em.c bcopy(sc->interface_data.ac_enaddr, sc->hw.mac_addr,
hw 732 dev/pci/if_em.c em_clear_hw_cntrs(&sc->hw);
hw 736 dev/pci/if_em.c sc->hw.phy_reset_disable = TRUE;
hw 757 dev/pci/if_em.c test_icr = reg_icr = E1000_READ_REG(&sc->hw, ICR);
hw 758 dev/pci/if_em.c if (sc->hw.mac_type >= em_82571)
hw 773 dev/pci/if_em.c sc->hw.get_link_status = 1;
hw 774 dev/pci/if_em.c em_check_for_link(&sc->hw);
hw 806 dev/pci/if_em.c em_check_for_link(&sc->hw);
hw 819 dev/pci/if_em.c if (sc->hw.media_type == em_media_type_fiber ||
hw 820 dev/pci/if_em.c sc->hw.media_type == em_media_type_internal_serdes) {
hw 821 dev/pci/if_em.c if (sc->hw.mac_type == em_82545)
hw 843 dev/pci/if_em.c em_read_phy_reg(&sc->hw, PHY_AUTONEG_ADV, &ar);
hw 844 dev/pci/if_em.c em_read_phy_reg(&sc->hw, PHY_LP_ABILITY, &lpar);
hw 858 dev/pci/if_em.c em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &gsr);
hw 886 dev/pci/if_em.c sc->hw.autoneg = DO_AUTO_NEG;
hw 887 dev/pci/if_em.c sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT;
hw 892 dev/pci/if_em.c sc->hw.autoneg = DO_AUTO_NEG;
hw 893 dev/pci/if_em.c sc->hw.autoneg_advertised = ADVERTISE_1000_FULL;
hw 896 dev/pci/if_em.c sc->hw.autoneg = FALSE;
hw 897 dev/pci/if_em.c sc->hw.autoneg_advertised = 0;
hw 899 dev/pci/if_em.c sc->hw.forced_speed_duplex = em_100_full;
hw 901 dev/pci/if_em.c sc->hw.forced_speed_duplex = em_100_half;
hw 904 dev/pci/if_em.c sc->hw.autoneg = FALSE;
hw 905 dev/pci/if_em.c sc->hw.autoneg_advertised = 0;
hw 907 dev/pci/if_em.c sc->hw.forced_speed_duplex = em_10_full;
hw 909 dev/pci/if_em.c sc->hw.forced_speed_duplex = em_10_half;
hw 919 dev/pci/if_em.c sc->hw.phy_reset_disable = FALSE;
hw 985 dev/pci/if_em.c if (sc->hw.mac_type >= em_82543)
hw 1080 dev/pci/if_em.c if (sc->hw.mac_type == em_82547 &&
hw 1084 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, TDT, i);
hw 1085 dev/pci/if_em.c if (sc->hw.mac_type == em_82547)
hw 1114 dev/pci/if_em.c hw_tdt = E1000_READ_REG(&sc->hw, TDT);
hw 1130 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, TDT, hw_tdt);
hw 1185 dev/pci/if_em.c if ((E1000_READ_REG(&sc->hw, TDT) ==
hw 1186 dev/pci/if_em.c E1000_READ_REG(&sc->hw, TDH)) &&
hw 1187 dev/pci/if_em.c (E1000_READ_REG(&sc->hw, TDFT) ==
hw 1188 dev/pci/if_em.c E1000_READ_REG(&sc->hw, TDFH)) &&
hw 1189 dev/pci/if_em.c (E1000_READ_REG(&sc->hw, TDFTS) ==
hw 1190 dev/pci/if_em.c E1000_READ_REG(&sc->hw, TDFHS)) &&
hw 1191 dev/pci/if_em.c (E1000_READ_REG(&sc->hw, TDFPC) == 0)) {
hw 1194 dev/pci/if_em.c tctl = E1000_READ_REG(&sc->hw, TCTL);
hw 1195 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, TCTL, tctl & ~E1000_TCTL_EN);
hw 1198 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, TDFT, sc->tx_head_addr);
hw 1199 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, TDFH, sc->tx_head_addr);
hw 1200 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, TDFTS, sc->tx_head_addr);
hw 1201 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, TDFHS, sc->tx_head_addr);
hw 1204 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, TCTL, tctl);
hw 1205 dev/pci/if_em.c E1000_WRITE_FLUSH(&sc->hw);
hw 1221 dev/pci/if_em.c reg_rctl = E1000_READ_REG(&sc->hw, RCTL);
hw 1231 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl);
hw 1254 dev/pci/if_em.c if (sc->hw.mac_type == em_82542_rev2_0) {
hw 1255 dev/pci/if_em.c reg_rctl = E1000_READ_REG(&sc->hw, RCTL);
hw 1256 dev/pci/if_em.c if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
hw 1257 dev/pci/if_em.c em_pci_clear_mwi(&sc->hw);
hw 1259 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl);
hw 1277 dev/pci/if_em.c reg_rctl = E1000_READ_REG(&sc->hw, RCTL);
hw 1279 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl);
hw 1281 dev/pci/if_em.c em_mc_addr_list_update(&sc->hw, mta, mcnt, 0, 1);
hw 1283 dev/pci/if_em.c if (sc->hw.mac_type == em_82542_rev2_0) {
hw 1284 dev/pci/if_em.c reg_rctl = E1000_READ_REG(&sc->hw, RCTL);
hw 1286 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl);
hw 1288 dev/pci/if_em.c if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
hw 1289 dev/pci/if_em.c em_pci_set_mwi(&sc->hw);
hw 1311 dev/pci/if_em.c em_check_for_link(&sc->hw);
hw 1328 dev/pci/if_em.c if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU) {
hw 1330 dev/pci/if_em.c em_get_speed_and_duplex(&sc->hw,
hw 1335 dev/pci/if_em.c ((sc->hw.mac_type == em_82571) ||
hw 1336 dev/pci/if_em.c (sc->hw.mac_type == em_82572))) {
hw 1339 dev/pci/if_em.c tarc0 = E1000_READ_REG(&sc->hw, TARC0);
hw 1341 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, TARC0, tarc0);
hw 1381 dev/pci/if_em.c em_reset_hw(&sc->hw);
hw 1404 dev/pci/if_em.c sc->hw.pci_cmd_word = pci_conf_read(pa->pa_pc, pa->pa_tag,
hw 1408 dev/pci/if_em.c sc->hw.vendor_id = PCI_VENDOR(pa->pa_id);
hw 1409 dev/pci/if_em.c sc->hw.device_id = PCI_PRODUCT(pa->pa_id);
hw 1412 dev/pci/if_em.c sc->hw.revision_id = PCI_REVISION(reg);
hw 1415 dev/pci/if_em.c sc->hw.subsystem_vendor_id = PCI_VENDOR(reg);
hw 1416 dev/pci/if_em.c sc->hw.subsystem_id = PCI_PRODUCT(reg);
hw 1419 dev/pci/if_em.c if (em_set_mac_type(&sc->hw))
hw 1422 dev/pci/if_em.c if (sc->hw.mac_type == em_82541 ||
hw 1423 dev/pci/if_em.c sc->hw.mac_type == em_82541_rev_2 ||
hw 1424 dev/pci/if_em.c sc->hw.mac_type == em_82547 ||
hw 1425 dev/pci/if_em.c sc->hw.mac_type == em_82547_rev_2)
hw 1426 dev/pci/if_em.c sc->hw.phy_init_script = TRUE;
hw 1450 dev/pci/if_em.c if (sc->hw.mac_type > em_82543) {
hw 1471 dev/pci/if_em.c sc->hw.io_base = 0;
hw 1475 dev/pci/if_em.c if (sc->hw.mac_type == em_ich8lan) {
hw 1495 dev/pci/if_em.c sc->hw.back = &sc->osdep;
hw 1553 dev/pci/if_em.c em_reset_hw(&sc->hw);
hw 1559 dev/pci/if_em.c if (em_validate_eeprom_checksum(&sc->hw) < 0) {
hw 1565 dev/pci/if_em.c if (em_validate_eeprom_checksum(&sc->hw) < 0) {
hw 1572 dev/pci/if_em.c if (em_read_part_num(&sc->hw, &(sc->part_num)) < 0) {
hw 1580 dev/pci/if_em.c (sc->hw.mac_type == em_82571 ||
hw 1581 dev/pci/if_em.c sc->hw.mac_type == em_82572)) {
hw 1585 dev/pci/if_em.c em_read_phy_reg(&sc->hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
hw 1587 dev/pci/if_em.c em_write_phy_reg(&sc->hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp);
hw 1604 dev/pci/if_em.c rx_buffer_size = ((E1000_READ_REG(&sc->hw, PBA) & 0xffff) << 10 );
hw 1606 dev/pci/if_em.c sc->hw.fc_high_water = rx_buffer_size -
hw 1607 dev/pci/if_em.c EM_ROUNDUP(sc->hw.max_frame_size, 1024);
hw 1608 dev/pci/if_em.c sc->hw.fc_low_water = sc->hw.fc_high_water - 1500;
hw 1609 dev/pci/if_em.c if (sc->hw.mac_type == em_80003es2lan)
hw 1610 dev/pci/if_em.c sc->hw.fc_pause_time = 0xFFFF;
hw 1612 dev/pci/if_em.c sc->hw.fc_pause_time = 1000;
hw 1613 dev/pci/if_em.c sc->hw.fc_send_xon = TRUE;
hw 1614 dev/pci/if_em.c sc->hw.fc = E1000_FC_FULL;
hw 1616 dev/pci/if_em.c if (em_init_hw(&sc->hw) < 0) {
hw 1622 dev/pci/if_em.c em_check_for_link(&sc->hw);
hw 1648 dev/pci/if_em.c sc->hw.max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN;
hw 1655 dev/pci/if_em.c if (sc->hw.mac_type >= em_82543)
hw 1665 dev/pci/if_em.c if (sc->hw.media_type == em_media_type_fiber ||
hw 1666 dev/pci/if_em.c sc->hw.media_type == em_media_type_internal_serdes) {
hw 1667 dev/pci/if_em.c if (sc->hw.mac_type == em_82545)
hw 1681 dev/pci/if_em.c if (sc->hw.phy_type != em_phy_ife) {
hw 1705 dev/pci/if_em.c if (sc->link_active || (sc->hw.phy_type != em_phy_igp) ||
hw 1706 dev/pci/if_em.c !sc->hw.autoneg || !(sc->hw.autoneg_advertised & ADVERTISE_1000_FULL))
hw 1712 dev/pci/if_em.c em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
hw 1715 dev/pci/if_em.c em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
hw 1717 dev/pci/if_em.c em_read_phy_reg(&sc->hw, PHY_1000T_CTRL,
hw 1721 dev/pci/if_em.c em_write_phy_reg(&sc->hw,
hw 1724 dev/pci/if_em.c if (sc->hw.autoneg &&
hw 1725 dev/pci/if_em.c !em_phy_setup_autoneg(&sc->hw) &&
hw 1726 dev/pci/if_em.c !em_read_phy_reg(&sc->hw, PHY_CTRL,
hw 1730 dev/pci/if_em.c em_write_phy_reg(&sc->hw,
hw 1738 dev/pci/if_em.c em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
hw 1740 dev/pci/if_em.c em_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
hw 1741 dev/pci/if_em.c if (sc->hw.autoneg &&
hw 1742 dev/pci/if_em.c !em_phy_setup_autoneg(&sc->hw) &&
hw 1743 dev/pci/if_em.c !em_read_phy_reg(&sc->hw, PHY_CTRL, &phy_tmp)) {
hw 1746 dev/pci/if_em.c em_write_phy_reg(&sc->hw, PHY_CTRL, phy_tmp);
hw 1924 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, TDLEN,
hw 1927 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, TDBAH, (u_int32_t)(bus_addr >> 32));
hw 1928 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, TDBAL, (u_int32_t)bus_addr);
hw 1931 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, TDT, 0);
hw 1932 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, TDH, 0);
hw 1935 dev/pci/if_em.c E1000_READ_REG(&sc->hw, TDBAL),
hw 1936 dev/pci/if_em.c E1000_READ_REG(&sc->hw, TDLEN));
hw 1939 dev/pci/if_em.c switch (sc->hw.mac_type) {
hw 1951 dev/pci/if_em.c if (sc->hw.media_type == em_media_type_fiber ||
hw 1952 dev/pci/if_em.c sc->hw.media_type == em_media_type_internal_serdes)
hw 1960 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, TIPG, reg_tipg);
hw 1961 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, TIDV, sc->tx_int_delay);
hw 1962 dev/pci/if_em.c if (sc->hw.mac_type >= em_82540)
hw 1963 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, TADV, sc->tx_abs_int_delay);
hw 1968 dev/pci/if_em.c if (sc->hw.mac_type >= em_82571)
hw 1975 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, TCTL, reg_tctl);
hw 2236 dev/pci/if_em.c if (sc->hw.max_frame_size <= (MCLBYTES - ETHER_ALIGN))
hw 2370 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, RCTL, 0);
hw 2373 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, RDTR,
hw 2376 dev/pci/if_em.c if (sc->hw.mac_type >= em_82540) {
hw 2377 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, RADV, sc->rx_abs_int_delay);
hw 2381 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, ITR, DEFAULT_ITR);
hw 2386 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, RDLEN, sc->num_rx_desc *
hw 2388 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, RDBAH, (u_int32_t)(bus_addr >> 32));
hw 2389 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, RDBAL, (u_int32_t)bus_addr);
hw 2394 dev/pci/if_em.c (sc->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
hw 2396 dev/pci/if_em.c if (sc->hw.tbi_compatibility_on == TRUE)
hw 2415 dev/pci/if_em.c if (sc->hw.max_frame_size != ETHER_MAX_LEN)
hw 2419 dev/pci/if_em.c if (sc->hw.mac_type >= em_82543) {
hw 2420 dev/pci/if_em.c reg_rxcsum = E1000_READ_REG(&sc->hw, RXCSUM);
hw 2422 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, RXCSUM, reg_rxcsum);
hw 2426 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl);
hw 2429 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, RDH, 0);
hw 2430 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, RDT, sc->num_rx_desc - 1);
hw 2552 dev/pci/if_em.c if (TBI_ACCEPT(&sc->hw, status, current_desc->errors,
hw 2554 dev/pci/if_em.c em_tbi_adjust_stats(&sc->hw,
hw 2557 dev/pci/if_em.c sc->hw.mac_addr);
hw 2580 dev/pci/if_em.c if (sc->hw.max_frame_size > (MCLBYTES - ETHER_ALIGN)) {
hw 2659 dev/pci/if_em.c if (sc->hw.max_frame_size <= (MCLBYTES - ETHER_ALIGN))
hw 2701 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, RDT, i);
hw 2716 dev/pci/if_em.c if ((sc->hw.mac_type < em_82543) ||
hw 2744 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, IMS, (IMS_ENABLE_MASK));
hw 2759 dev/pci/if_em.c if (sc->hw.mac_type == em_82542_rev2_0)
hw 2760 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, IMC, (0xffffffff & ~E1000_IMC_RXSEQ));
hw 2762 dev/pci/if_em.c E1000_WRITE_REG(&sc->hw, IMC, 0xffffffff);
hw 2777 dev/pci/if_em.c em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value)
hw 2779 dev/pci/if_em.c struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa;
hw 2786 dev/pci/if_em.c em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value)
hw 2788 dev/pci/if_em.c struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa;
hw 2794 dev/pci/if_em.c em_pci_set_mwi(struct em_hw *hw)
hw 2796 dev/pci/if_em.c struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa;
hw 2800 dev/pci/if_em.c (hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE));
hw 2804 dev/pci/if_em.c em_pci_clear_mwi(struct em_hw *hw)
hw 2806 dev/pci/if_em.c struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa;
hw 2810 dev/pci/if_em.c (hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE));
hw 2814 dev/pci/if_em.c em_read_pcie_cap_reg(struct em_hw *hw, uint32_t reg, uint16_t *value)
hw 2816 dev/pci/if_em.c struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa;
hw 2823 dev/pci/if_em.c em_read_pci_cfg(hw, reg + 0x12, value);
hw 2825 dev/pci/if_em.c em_read_pci_cfg(hw, reg + 0x8, &pectl);
hw 2827 dev/pci/if_em.c em_write_pci_cfg(hw, reg + 0x8, &pectl);
hw 2897 dev/pci/if_em.c if (sc->hw.media_type == em_media_type_copper ||
hw 2898 dev/pci/if_em.c (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU)) {
hw 2899 dev/pci/if_em.c sc->stats.symerrs += E1000_READ_REG(&sc->hw, SYMERRS);
hw 2900 dev/pci/if_em.c sc->stats.sec += E1000_READ_REG(&sc->hw, SEC);
hw 2902 dev/pci/if_em.c sc->stats.crcerrs += E1000_READ_REG(&sc->hw, CRCERRS);
hw 2903 dev/pci/if_em.c sc->stats.mpc += E1000_READ_REG(&sc->hw, MPC);
hw 2904 dev/pci/if_em.c sc->stats.scc += E1000_READ_REG(&sc->hw, SCC);
hw 2905 dev/pci/if_em.c sc->stats.ecol += E1000_READ_REG(&sc->hw, ECOL);
hw 2907 dev/pci/if_em.c sc->stats.mcc += E1000_READ_REG(&sc->hw, MCC);
hw 2908 dev/pci/if_em.c sc->stats.latecol += E1000_READ_REG(&sc->hw, LATECOL);
hw 2909 dev/pci/if_em.c sc->stats.colc += E1000_READ_REG(&sc->hw, COLC);
hw 2910 dev/pci/if_em.c sc->stats.dc += E1000_READ_REG(&sc->hw, DC);
hw 2911 dev/pci/if_em.c sc->stats.rlec += E1000_READ_REG(&sc->hw, RLEC);
hw 2912 dev/pci/if_em.c sc->stats.xonrxc += E1000_READ_REG(&sc->hw, XONRXC);
hw 2913 dev/pci/if_em.c sc->stats.xontxc += E1000_READ_REG(&sc->hw, XONTXC);
hw 2914 dev/pci/if_em.c sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, XOFFRXC);
hw 2915 dev/pci/if_em.c sc->stats.xofftxc += E1000_READ_REG(&sc->hw, XOFFTXC);
hw 2916 dev/pci/if_em.c sc->stats.fcruc += E1000_READ_REG(&sc->hw, FCRUC);
hw 2917 dev/pci/if_em.c sc->stats.prc64 += E1000_READ_REG(&sc->hw, PRC64);
hw 2918 dev/pci/if_em.c sc->stats.prc127 += E1000_READ_REG(&sc->hw, PRC127);
hw 2919 dev/pci/if_em.c sc->stats.prc255 += E1000_READ_REG(&sc->hw, PRC255);
hw 2920 dev/pci/if_em.c sc->stats.prc511 += E1000_READ_REG(&sc->hw, PRC511);
hw 2921 dev/pci/if_em.c sc->stats.prc1023 += E1000_READ_REG(&sc->hw, PRC1023);
hw 2922 dev/pci/if_em.c sc->stats.prc1522 += E1000_READ_REG(&sc->hw, PRC1522);
hw 2923 dev/pci/if_em.c sc->stats.gprc += E1000_READ_REG(&sc->hw, GPRC);
hw 2924 dev/pci/if_em.c sc->stats.bprc += E1000_READ_REG(&sc->hw, BPRC);
hw 2925 dev/pci/if_em.c sc->stats.mprc += E1000_READ_REG(&sc->hw, MPRC);
hw 2926 dev/pci/if_em.c sc->stats.gptc += E1000_READ_REG(&sc->hw, GPTC);
hw 2931 dev/pci/if_em.c sc->stats.gorcl += E1000_READ_REG(&sc->hw, GORCL);
hw 2932 dev/pci/if_em.c sc->stats.gorch += E1000_READ_REG(&sc->hw, GORCH);
hw 2933 dev/pci/if_em.c sc->stats.gotcl += E1000_READ_REG(&sc->hw, GOTCL);
hw 2934 dev/pci/if_em.c sc->stats.gotch += E1000_READ_REG(&sc->hw, GOTCH);
hw 2936 dev/pci/if_em.c sc->stats.rnbc += E1000_READ_REG(&sc->hw, RNBC);
hw 2937 dev/pci/if_em.c sc->stats.ruc += E1000_READ_REG(&sc->hw, RUC);
hw 2938 dev/pci/if_em.c sc->stats.rfc += E1000_READ_REG(&sc->hw, RFC);
hw 2939 dev/pci/if_em.c sc->stats.roc += E1000_READ_REG(&sc->hw, ROC);
hw 2940 dev/pci/if_em.c sc->stats.rjc += E1000_READ_REG(&sc->hw, RJC);
hw 2942 dev/pci/if_em.c sc->stats.torl += E1000_READ_REG(&sc->hw, TORL);
hw 2943 dev/pci/if_em.c sc->stats.torh += E1000_READ_REG(&sc->hw, TORH);
hw 2944 dev/pci/if_em.c sc->stats.totl += E1000_READ_REG(&sc->hw, TOTL);
hw 2945 dev/pci/if_em.c sc->stats.toth += E1000_READ_REG(&sc->hw, TOTH);
hw 2947 dev/pci/if_em.c sc->stats.tpr += E1000_READ_REG(&sc->hw, TPR);
hw 2948 dev/pci/if_em.c sc->stats.tpt += E1000_READ_REG(&sc->hw, TPT);
hw 2949 dev/pci/if_em.c sc->stats.ptc64 += E1000_READ_REG(&sc->hw, PTC64);
hw 2950 dev/pci/if_em.c sc->stats.ptc127 += E1000_READ_REG(&sc->hw, PTC127);
hw 2951 dev/pci/if_em.c sc->stats.ptc255 += E1000_READ_REG(&sc->hw, PTC255);
hw 2952 dev/pci/if_em.c sc->stats.ptc511 += E1000_READ_REG(&sc->hw, PTC511);
hw 2953 dev/pci/if_em.c sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, PTC1023);
hw 2954 dev/pci/if_em.c sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, PTC1522);
hw 2955 dev/pci/if_em.c sc->stats.mptc += E1000_READ_REG(&sc->hw, MPTC);
hw 2956 dev/pci/if_em.c sc->stats.bptc += E1000_READ_REG(&sc->hw, BPTC);
hw 2958 dev/pci/if_em.c if (sc->hw.mac_type >= em_82543) {
hw 2960 dev/pci/if_em.c E1000_READ_REG(&sc->hw, ALGNERRC);
hw 2962 dev/pci/if_em.c E1000_READ_REG(&sc->hw, RXERRC);
hw 2964 dev/pci/if_em.c E1000_READ_REG(&sc->hw, TNCRS);
hw 2966 dev/pci/if_em.c E1000_READ_REG(&sc->hw, CEXTERR);
hw 2968 dev/pci/if_em.c E1000_READ_REG(&sc->hw, TSCTC);
hw 2970 dev/pci/if_em.c E1000_READ_REG(&sc->hw, TSCTFC);
hw 317 dev/pci/if_em.h struct em_hw hw;
hw 76 dev/pci/if_em_hw.c static int32_t em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask);
hw 77 dev/pci/if_em_hw.c static void em_swfw_sync_release(struct em_hw *hw, uint16_t mask);
hw 78 dev/pci/if_em_hw.c static int32_t em_read_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *data);
hw 79 dev/pci/if_em_hw.c static int32_t em_write_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data);
hw 80 dev/pci/if_em_hw.c static int32_t em_get_software_semaphore(struct em_hw *hw);
hw 81 dev/pci/if_em_hw.c static void em_release_software_semaphore(struct em_hw *hw);
hw 83 dev/pci/if_em_hw.c static int32_t em_check_downshift(struct em_hw *hw);
hw 84 dev/pci/if_em_hw.c static void em_clear_vfta(struct em_hw *hw);
hw 85 dev/pci/if_em_hw.c static int32_t em_commit_shadow_ram(struct em_hw *hw);
hw 86 dev/pci/if_em_hw.c static int32_t em_config_dsp_after_link_change(struct em_hw *hw, boolean_t link_up);
hw 87 dev/pci/if_em_hw.c static int32_t em_config_fc_after_link_up(struct em_hw *hw);
hw 88 dev/pci/if_em_hw.c static int32_t em_detect_gig_phy(struct em_hw *hw);
hw 89 dev/pci/if_em_hw.c static int32_t em_erase_ich8_4k_segment(struct em_hw *hw, uint32_t bank);
hw 90 dev/pci/if_em_hw.c static int32_t em_get_auto_rd_done(struct em_hw *hw);
hw 91 dev/pci/if_em_hw.c static int32_t em_get_cable_length(struct em_hw *hw, uint16_t *min_length, uint16_t *max_length);
hw 92 dev/pci/if_em_hw.c static int32_t em_get_hw_eeprom_semaphore(struct em_hw *hw);
hw 93 dev/pci/if_em_hw.c static int32_t em_get_phy_cfg_done(struct em_hw *hw);
hw 94 dev/pci/if_em_hw.c static int32_t em_get_software_flag(struct em_hw *hw);
hw 95 dev/pci/if_em_hw.c static int32_t em_ich8_cycle_init(struct em_hw *hw);
hw 96 dev/pci/if_em_hw.c static int32_t em_ich8_flash_cycle(struct em_hw *hw, uint32_t timeout);
hw 97 dev/pci/if_em_hw.c static int32_t em_id_led_init(struct em_hw *hw);
hw 98 dev/pci/if_em_hw.c static int32_t em_init_lcd_from_nvm_config_region(struct em_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size);
hw 99 dev/pci/if_em_hw.c static int32_t em_init_lcd_from_nvm(struct em_hw *hw);
hw 100 dev/pci/if_em_hw.c static void em_init_rx_addrs(struct em_hw *hw);
hw 101 dev/pci/if_em_hw.c static void em_initialize_hardware_bits(struct em_hw *hw);
hw 102 dev/pci/if_em_hw.c static boolean_t em_is_onboard_nvm_eeprom(struct em_hw *hw);
hw 103 dev/pci/if_em_hw.c static int32_t em_kumeran_lock_loss_workaround(struct em_hw *hw);
hw 104 dev/pci/if_em_hw.c static int32_t em_mng_enable_host_if(struct em_hw *hw);
hw 105 dev/pci/if_em_hw.c static int32_t em_read_eeprom_eerd(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
hw 106 dev/pci/if_em_hw.c static int32_t em_write_eeprom_eewr(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
hw 107 dev/pci/if_em_hw.c static int32_t em_poll_eerd_eewr_done(struct em_hw *hw, int eerd);
hw 108 dev/pci/if_em_hw.c static void em_put_hw_eeprom_semaphore(struct em_hw *hw);
hw 109 dev/pci/if_em_hw.c static int32_t em_read_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t *data);
hw 110 dev/pci/if_em_hw.c static int32_t em_verify_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t byte);
hw 111 dev/pci/if_em_hw.c static int32_t em_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t byte);
hw 112 dev/pci/if_em_hw.c static int32_t em_read_ich8_word(struct em_hw *hw, uint32_t index, uint16_t *data);
hw 113 dev/pci/if_em_hw.c static int32_t em_read_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, uint16_t *data);
hw 114 dev/pci/if_em_hw.c static int32_t em_write_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, uint16_t data);
hw 115 dev/pci/if_em_hw.c static int32_t em_read_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
hw 116 dev/pci/if_em_hw.c static int32_t em_write_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
hw 117 dev/pci/if_em_hw.c static void em_release_software_flag(struct em_hw *hw);
hw 118 dev/pci/if_em_hw.c static int32_t em_set_d3_lplu_state(struct em_hw *hw, boolean_t active);
hw 119 dev/pci/if_em_hw.c static int32_t em_set_d0_lplu_state(struct em_hw *hw, boolean_t active);
hw 120 dev/pci/if_em_hw.c static int32_t em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop);
hw 121 dev/pci/if_em_hw.c static void em_set_pci_express_master_disable(struct em_hw *hw);
hw 122 dev/pci/if_em_hw.c static int32_t em_wait_autoneg(struct em_hw *hw);
hw 123 dev/pci/if_em_hw.c static void em_write_reg_io(struct em_hw *hw, uint32_t offset, uint32_t value);
hw 124 dev/pci/if_em_hw.c static int32_t em_set_phy_type(struct em_hw *hw);
hw 125 dev/pci/if_em_hw.c static void em_phy_init_script(struct em_hw *hw);
hw 126 dev/pci/if_em_hw.c static int32_t em_setup_copper_link(struct em_hw *hw);
hw 127 dev/pci/if_em_hw.c static int32_t em_setup_fiber_serdes_link(struct em_hw *hw);
hw 128 dev/pci/if_em_hw.c static int32_t em_adjust_serdes_amplitude(struct em_hw *hw);
hw 129 dev/pci/if_em_hw.c static int32_t em_phy_force_speed_duplex(struct em_hw *hw);
hw 130 dev/pci/if_em_hw.c static int32_t em_config_mac_to_phy(struct em_hw *hw);
hw 131 dev/pci/if_em_hw.c static void em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl);
hw 132 dev/pci/if_em_hw.c static void em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl);
hw 133 dev/pci/if_em_hw.c static void em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data,
hw 135 dev/pci/if_em_hw.c static uint16_t em_shift_in_mdi_bits(struct em_hw *hw);
hw 136 dev/pci/if_em_hw.c static int32_t em_phy_reset_dsp(struct em_hw *hw);
hw 137 dev/pci/if_em_hw.c static int32_t em_write_eeprom_spi(struct em_hw *hw, uint16_t offset,
hw 139 dev/pci/if_em_hw.c static int32_t em_write_eeprom_microwire(struct em_hw *hw,
hw 142 dev/pci/if_em_hw.c static int32_t em_spi_eeprom_ready(struct em_hw *hw);
hw 143 dev/pci/if_em_hw.c static void em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd);
hw 144 dev/pci/if_em_hw.c static void em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd);
hw 145 dev/pci/if_em_hw.c static void em_shift_out_ee_bits(struct em_hw *hw, uint16_t data,
hw 147 dev/pci/if_em_hw.c static int32_t em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr,
hw 149 dev/pci/if_em_hw.c static int32_t em_read_phy_reg_ex(struct em_hw *hw,uint32_t reg_addr,
hw 151 dev/pci/if_em_hw.c static uint16_t em_shift_in_ee_bits(struct em_hw *hw, uint16_t count);
hw 152 dev/pci/if_em_hw.c static int32_t em_acquire_eeprom(struct em_hw *hw);
hw 153 dev/pci/if_em_hw.c static void em_release_eeprom(struct em_hw *hw);
hw 154 dev/pci/if_em_hw.c static void em_standby_eeprom(struct em_hw *hw);
hw 155 dev/pci/if_em_hw.c static int32_t em_set_vco_speed(struct em_hw *hw);
hw 156 dev/pci/if_em_hw.c static int32_t em_polarity_reversal_workaround(struct em_hw *hw);
hw 157 dev/pci/if_em_hw.c static int32_t em_set_phy_mode(struct em_hw *hw);
hw 158 dev/pci/if_em_hw.c static int32_t em_host_if_read_cookie(struct em_hw *hw, uint8_t *buffer);
hw 160 dev/pci/if_em_hw.c static int32_t em_configure_kmrn_for_10_100(struct em_hw *hw,
hw 162 dev/pci/if_em_hw.c static int32_t em_configure_kmrn_for_1000(struct em_hw *hw);
hw 193 dev/pci/if_em_hw.c em_set_phy_type(struct em_hw *hw)
hw 197 dev/pci/if_em_hw.c if (hw->mac_type == em_undefined)
hw 200 dev/pci/if_em_hw.c switch (hw->phy_id) {
hw 205 dev/pci/if_em_hw.c hw->phy_type = em_phy_m88;
hw 208 dev/pci/if_em_hw.c if (hw->mac_type == em_82541 ||
hw 209 dev/pci/if_em_hw.c hw->mac_type == em_82541_rev_2 ||
hw 210 dev/pci/if_em_hw.c hw->mac_type == em_82547 ||
hw 211 dev/pci/if_em_hw.c hw->mac_type == em_82547_rev_2) {
hw 212 dev/pci/if_em_hw.c hw->phy_type = em_phy_igp;
hw 216 dev/pci/if_em_hw.c hw->phy_type = em_phy_igp_3;
hw 221 dev/pci/if_em_hw.c hw->phy_type = em_phy_ife;
hw 224 dev/pci/if_em_hw.c if (hw->mac_type == em_80003es2lan) {
hw 225 dev/pci/if_em_hw.c hw->phy_type = em_phy_gg82563;
hw 231 dev/pci/if_em_hw.c hw->phy_type = em_phy_undefined;
hw 244 dev/pci/if_em_hw.c em_phy_init_script(struct em_hw *hw)
hw 251 dev/pci/if_em_hw.c if (hw->phy_init_script) {
hw 256 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
hw 259 dev/pci/if_em_hw.c em_write_phy_reg(hw, 0x2F5B, 0x0003);
hw 263 dev/pci/if_em_hw.c em_write_phy_reg(hw,0x0000,0x0140);
hw 267 dev/pci/if_em_hw.c switch (hw->mac_type) {
hw 270 dev/pci/if_em_hw.c em_write_phy_reg(hw, 0x1F95, 0x0001);
hw 272 dev/pci/if_em_hw.c em_write_phy_reg(hw, 0x1F71, 0xBD21);
hw 274 dev/pci/if_em_hw.c em_write_phy_reg(hw, 0x1F79, 0x0018);
hw 276 dev/pci/if_em_hw.c em_write_phy_reg(hw, 0x1F30, 0x1600);
hw 278 dev/pci/if_em_hw.c em_write_phy_reg(hw, 0x1F31, 0x0014);
hw 280 dev/pci/if_em_hw.c em_write_phy_reg(hw, 0x1F32, 0x161C);
hw 282 dev/pci/if_em_hw.c em_write_phy_reg(hw, 0x1F94, 0x0003);
hw 284 dev/pci/if_em_hw.c em_write_phy_reg(hw, 0x1F96, 0x003F);
hw 286 dev/pci/if_em_hw.c em_write_phy_reg(hw, 0x2010, 0x0008);
hw 291 dev/pci/if_em_hw.c em_write_phy_reg(hw, 0x1F73, 0x0099);
hw 297 dev/pci/if_em_hw.c em_write_phy_reg(hw, 0x0000, 0x3300);
hw 302 dev/pci/if_em_hw.c em_write_phy_reg(hw, 0x2F5B, phy_saved_data);
hw 304 dev/pci/if_em_hw.c if (hw->mac_type == em_82547) {
hw 308 dev/pci/if_em_hw.c em_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
hw 311 dev/pci/if_em_hw.c em_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
hw 326 dev/pci/if_em_hw.c em_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
hw 327 dev/pci/if_em_hw.c em_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
hw 340 dev/pci/if_em_hw.c em_set_mac_type(struct em_hw *hw)
hw 344 dev/pci/if_em_hw.c switch (hw->device_id) {
hw 346 dev/pci/if_em_hw.c switch (hw->revision_id) {
hw 348 dev/pci/if_em_hw.c hw->mac_type = em_82542_rev2_0;
hw 351 dev/pci/if_em_hw.c hw->mac_type = em_82542_rev2_1;
hw 360 dev/pci/if_em_hw.c hw->mac_type = em_82543;
hw 366 dev/pci/if_em_hw.c hw->mac_type = em_82544;
hw 373 dev/pci/if_em_hw.c hw->mac_type = em_82540;
hw 377 dev/pci/if_em_hw.c hw->mac_type = em_82545;
hw 382 dev/pci/if_em_hw.c hw->mac_type = em_82545_rev_3;
hw 387 dev/pci/if_em_hw.c hw->mac_type = em_82546;
hw 396 dev/pci/if_em_hw.c hw->mac_type = em_82546_rev_3;
hw 401 dev/pci/if_em_hw.c hw->mac_type = em_82541;
hw 407 dev/pci/if_em_hw.c hw->mac_type = em_82541_rev_2;
hw 411 dev/pci/if_em_hw.c hw->mac_type = em_82547;
hw 414 dev/pci/if_em_hw.c hw->mac_type = em_82547_rev_2;
hw 424 dev/pci/if_em_hw.c hw->mac_type = em_82571;
hw 430 dev/pci/if_em_hw.c hw->mac_type = em_82572;
hw 439 dev/pci/if_em_hw.c hw->mac_type = em_82573;
hw 445 dev/pci/if_em_hw.c hw->mac_type = em_80003es2lan;
hw 454 dev/pci/if_em_hw.c hw->mac_type = em_ich8lan;
hw 461 dev/pci/if_em_hw.c switch (hw->mac_type) {
hw 463 dev/pci/if_em_hw.c hw->swfwhw_semaphore_present = TRUE;
hw 464 dev/pci/if_em_hw.c hw->asf_firmware_present = TRUE;
hw 467 dev/pci/if_em_hw.c hw->swfw_sync_present = TRUE;
hw 472 dev/pci/if_em_hw.c hw->eeprom_semaphore_present = TRUE;
hw 478 dev/pci/if_em_hw.c hw->asf_firmware_present = TRUE;
hw 493 dev/pci/if_em_hw.c em_set_media_type(struct em_hw *hw)
hw 499 dev/pci/if_em_hw.c if (hw->mac_type != em_82543) {
hw 501 dev/pci/if_em_hw.c hw->tbi_compatibility_en = FALSE;
hw 504 dev/pci/if_em_hw.c switch (hw->device_id) {
hw 510 dev/pci/if_em_hw.c hw->media_type = em_media_type_internal_serdes;
hw 513 dev/pci/if_em_hw.c switch (hw->mac_type) {
hw 516 dev/pci/if_em_hw.c hw->media_type = em_media_type_fiber;
hw 523 dev/pci/if_em_hw.c hw->media_type = em_media_type_copper;
hw 526 dev/pci/if_em_hw.c status = E1000_READ_REG(hw, STATUS);
hw 528 dev/pci/if_em_hw.c hw->media_type = em_media_type_fiber;
hw 530 dev/pci/if_em_hw.c hw->tbi_compatibility_en = FALSE;
hw 532 dev/pci/if_em_hw.c hw->media_type = em_media_type_copper;
hw 545 dev/pci/if_em_hw.c em_reset_hw(struct em_hw *hw)
hw 559 dev/pci/if_em_hw.c if (hw->mac_type == em_82542_rev2_0) {
hw 561 dev/pci/if_em_hw.c em_pci_clear_mwi(hw);
hw 564 dev/pci/if_em_hw.c if (hw->bus_type == em_bus_type_pci_express) {
hw 568 dev/pci/if_em_hw.c if (em_disable_pciex_master(hw) != E1000_SUCCESS) {
hw 575 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, IMC, 0xffffffff);
hw 581 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, RCTL, 0);
hw 582 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
hw 583 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 586 dev/pci/if_em_hw.c hw->tbi_compatibility_on = FALSE;
hw 593 dev/pci/if_em_hw.c ctrl = E1000_READ_REG(hw, CTRL);
hw 596 dev/pci/if_em_hw.c if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
hw 597 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
hw 603 dev/pci/if_em_hw.c if (hw->mac_type == em_82573) {
hw 606 dev/pci/if_em_hw.c extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
hw 610 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
hw 611 dev/pci/if_em_hw.c extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
hw 624 dev/pci/if_em_hw.c if (hw->mac_type == em_ich8lan) {
hw 626 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);
hw 628 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);
hw 638 dev/pci/if_em_hw.c switch (hw->mac_type) {
hw 647 dev/pci/if_em_hw.c E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
hw 652 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
hw 655 dev/pci/if_em_hw.c if (!hw->phy_reset_disable &&
hw 656 dev/pci/if_em_hw.c em_check_phy_reset_block(hw) == E1000_SUCCESS) {
hw 664 dev/pci/if_em_hw.c em_get_software_flag(hw);
hw 665 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
hw 669 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
hw 677 dev/pci/if_em_hw.c switch (hw->mac_type) {
hw 684 dev/pci/if_em_hw.c ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
hw 686 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
hw 687 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 699 dev/pci/if_em_hw.c if (em_is_onboard_nvm_eeprom(hw) == FALSE) {
hw 701 dev/pci/if_em_hw.c ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
hw 703 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
hw 704 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 709 dev/pci/if_em_hw.c ret_val = em_get_auto_rd_done(hw);
hw 716 dev/pci/if_em_hw.c if (hw->mac_type >= em_82540 && hw->mac_type <= em_82547_rev_2) {
hw 717 dev/pci/if_em_hw.c manc = E1000_READ_REG(hw, MANC);
hw 719 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, MANC, manc);
hw 722 dev/pci/if_em_hw.c if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
hw 723 dev/pci/if_em_hw.c em_phy_init_script(hw);
hw 726 dev/pci/if_em_hw.c led_ctrl = E1000_READ_REG(hw, LEDCTL);
hw 729 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
hw 734 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, IMC, 0xffffffff);
hw 737 dev/pci/if_em_hw.c icr = E1000_READ_REG(hw, ICR);
hw 740 dev/pci/if_em_hw.c if (hw->mac_type == em_82542_rev2_0) {
hw 741 dev/pci/if_em_hw.c if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
hw 742 dev/pci/if_em_hw.c em_pci_set_mwi(hw);
hw 745 dev/pci/if_em_hw.c if (hw->mac_type == em_ich8lan) {
hw 746 dev/pci/if_em_hw.c uint32_t kab = E1000_READ_REG(hw, KABGTXD);
hw 748 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, KABGTXD, kab);
hw 762 dev/pci/if_em_hw.c em_initialize_hardware_bits(struct em_hw *hw)
hw 764 dev/pci/if_em_hw.c if ((hw->mac_type >= em_82571) && (!hw->initialize_hw_bits_disable)) {
hw 771 dev/pci/if_em_hw.c reg_tarc0 = E1000_READ_REG(hw, TARC0);
hw 774 dev/pci/if_em_hw.c reg_txdctl = E1000_READ_REG(hw, TXDCTL);
hw 776 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
hw 778 dev/pci/if_em_hw.c reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
hw 780 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
hw 782 dev/pci/if_em_hw.c switch (hw->mac_type) {
hw 785 dev/pci/if_em_hw.c reg_tarc1 = E1000_READ_REG(hw, TARC1);
hw 786 dev/pci/if_em_hw.c reg_tctl = E1000_READ_REG(hw, TCTL);
hw 799 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, TARC1, reg_tarc1);
hw 802 dev/pci/if_em_hw.c reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
hw 803 dev/pci/if_em_hw.c reg_ctrl = E1000_READ_REG(hw, CTRL);
hw 809 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
hw 810 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, reg_ctrl);
hw 813 dev/pci/if_em_hw.c if ((hw->media_type == em_media_type_fiber) ||
hw 814 dev/pci/if_em_hw.c (hw->media_type == em_media_type_internal_serdes)) {
hw 818 dev/pci/if_em_hw.c reg_tctl = E1000_READ_REG(hw, TCTL);
hw 819 dev/pci/if_em_hw.c reg_tarc1 = E1000_READ_REG(hw, TARC1);
hw 825 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, TARC1, reg_tarc1);
hw 828 dev/pci/if_em_hw.c if ((hw->revision_id < 3) ||
hw 829 dev/pci/if_em_hw.c ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
hw 830 dev/pci/if_em_hw.c (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
hw 832 dev/pci/if_em_hw.c reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
hw 834 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
hw 838 dev/pci/if_em_hw.c reg_tarc1 = E1000_READ_REG(hw, TARC1);
hw 839 dev/pci/if_em_hw.c reg_tctl = E1000_READ_REG(hw, TCTL);
hw 848 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, TARC1, reg_tarc1);
hw 854 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, TARC0, reg_tarc0);
hw 870 dev/pci/if_em_hw.c em_init_hw(struct em_hw *hw)
hw 886 dev/pci/if_em_hw.c if ((hw->mac_type == em_ich8lan) &&
hw 887 dev/pci/if_em_hw.c ((hw->revision_id < 3) ||
hw 888 dev/pci/if_em_hw.c ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
hw 889 dev/pci/if_em_hw.c (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
hw 890 dev/pci/if_em_hw.c reg_data = E1000_READ_REG(hw, STATUS);
hw 892 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, STATUS, reg_data);
hw 896 dev/pci/if_em_hw.c ret_val = em_id_led_init(hw);
hw 903 dev/pci/if_em_hw.c em_set_media_type(hw);
hw 906 dev/pci/if_em_hw.c em_initialize_hardware_bits(hw);
hw 911 dev/pci/if_em_hw.c if (hw->mac_type != em_ich8lan) {
hw 912 dev/pci/if_em_hw.c if (hw->mac_type < em_82545_rev_3)
hw 913 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, VET, 0);
hw 914 dev/pci/if_em_hw.c em_clear_vfta(hw);
hw 918 dev/pci/if_em_hw.c if (hw->mac_type == em_82542_rev2_0) {
hw 920 dev/pci/if_em_hw.c em_pci_clear_mwi(hw);
hw 921 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
hw 922 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 929 dev/pci/if_em_hw.c em_init_rx_addrs(hw);
hw 932 dev/pci/if_em_hw.c if (hw->mac_type == em_82542_rev2_0) {
hw 933 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, RCTL, 0);
hw 934 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 936 dev/pci/if_em_hw.c if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
hw 937 dev/pci/if_em_hw.c em_pci_set_mwi(hw);
hw 943 dev/pci/if_em_hw.c if (hw->mac_type == em_ich8lan)
hw 946 dev/pci/if_em_hw.c E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
hw 949 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 957 dev/pci/if_em_hw.c if (hw->dma_fairness && hw->mac_type <= em_82543) {
hw 958 dev/pci/if_em_hw.c ctrl = E1000_READ_REG(hw, CTRL);
hw 959 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
hw 962 dev/pci/if_em_hw.c switch (hw->mac_type) {
hw 968 dev/pci/if_em_hw.c if (hw->bus_type == em_bus_type_pcix) {
hw 969 dev/pci/if_em_hw.c em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
hw 970 dev/pci/if_em_hw.c em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
hw 981 dev/pci/if_em_hw.c em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
hw 989 dev/pci/if_em_hw.c if (hw->mac_type == em_ich8lan)
hw 993 dev/pci/if_em_hw.c ret_val = em_setup_link(hw);
hw 996 dev/pci/if_em_hw.c if (hw->mac_type > em_82544) {
hw 997 dev/pci/if_em_hw.c ctrl = E1000_READ_REG(hw, TXDCTL);
hw 999 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, TXDCTL, ctrl);
hw 1002 dev/pci/if_em_hw.c if (hw->mac_type == em_82573) {
hw 1003 dev/pci/if_em_hw.c em_enable_tx_pkt_filtering(hw);
hw 1006 dev/pci/if_em_hw.c switch (hw->mac_type) {
hw 1011 dev/pci/if_em_hw.c reg_data = E1000_READ_REG(hw, TCTL);
hw 1013 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, TCTL, reg_data);
hw 1016 dev/pci/if_em_hw.c reg_data = E1000_READ_REG(hw, TCTL_EXT);
hw 1019 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
hw 1022 dev/pci/if_em_hw.c reg_data = E1000_READ_REG(hw, TIPG);
hw 1025 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, TIPG, reg_data);
hw 1027 dev/pci/if_em_hw.c reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
hw 1029 dev/pci/if_em_hw.c E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
hw 1034 dev/pci/if_em_hw.c ctrl = E1000_READ_REG(hw, TXDCTL1);
hw 1036 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, TXDCTL1, ctrl);
hw 1040 dev/pci/if_em_hw.c if (hw->mac_type == em_82573) {
hw 1041 dev/pci/if_em_hw.c uint32_t gcr = E1000_READ_REG(hw, GCR);
hw 1043 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, GCR, gcr);
hw 1051 dev/pci/if_em_hw.c em_clear_hw_cntrs(hw);
hw 1055 dev/pci/if_em_hw.c if (hw->mac_type == em_ich8lan)
hw 1056 dev/pci/if_em_hw.c em_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
hw 1058 dev/pci/if_em_hw.c if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
hw 1059 dev/pci/if_em_hw.c hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
hw 1060 dev/pci/if_em_hw.c ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
hw 1064 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
hw 1076 dev/pci/if_em_hw.c em_adjust_serdes_amplitude(struct em_hw *hw)
hw 1083 dev/pci/if_em_hw.c if (hw->media_type != em_media_type_internal_serdes)
hw 1086 dev/pci/if_em_hw.c switch (hw->mac_type) {
hw 1094 dev/pci/if_em_hw.c ret_val = em_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
hw 1102 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
hw 1122 dev/pci/if_em_hw.c em_setup_link(struct em_hw *hw)
hw 1132 dev/pci/if_em_hw.c if (em_check_phy_reset_block(hw))
hw 1143 dev/pci/if_em_hw.c if (hw->fc == E1000_FC_DEFAULT) {
hw 1144 dev/pci/if_em_hw.c switch (hw->mac_type) {
hw 1147 dev/pci/if_em_hw.c hw->fc = E1000_FC_FULL;
hw 1150 dev/pci/if_em_hw.c ret_val = em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
hw 1157 dev/pci/if_em_hw.c hw->fc = E1000_FC_NONE;
hw 1160 dev/pci/if_em_hw.c hw->fc = E1000_FC_TX_PAUSE;
hw 1162 dev/pci/if_em_hw.c hw->fc = E1000_FC_FULL;
hw 1171 dev/pci/if_em_hw.c if (hw->mac_type == em_82542_rev2_0)
hw 1172 dev/pci/if_em_hw.c hw->fc &= (~E1000_FC_TX_PAUSE);
hw 1174 dev/pci/if_em_hw.c if ((hw->mac_type < em_82543) && (hw->report_tx_early == 1))
hw 1175 dev/pci/if_em_hw.c hw->fc &= (~E1000_FC_RX_PAUSE);
hw 1177 dev/pci/if_em_hw.c hw->original_fc = hw->fc;
hw 1179 dev/pci/if_em_hw.c DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
hw 1188 dev/pci/if_em_hw.c if (hw->mac_type == em_82543) {
hw 1189 dev/pci/if_em_hw.c ret_val = em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
hw 1197 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
hw 1201 dev/pci/if_em_hw.c ret_val = (hw->media_type == em_media_type_copper) ?
hw 1202 dev/pci/if_em_hw.c em_setup_copper_link(hw) :
hw 1203 dev/pci/if_em_hw.c em_setup_fiber_serdes_link(hw);
hw 1213 dev/pci/if_em_hw.c if (hw->mac_type != em_ich8lan) {
hw 1214 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
hw 1215 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
hw 1216 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
hw 1219 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
hw 1227 dev/pci/if_em_hw.c if (!(hw->fc & E1000_FC_TX_PAUSE)) {
hw 1228 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, FCRTL, 0);
hw 1229 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, FCRTH, 0);
hw 1234 dev/pci/if_em_hw.c if (hw->fc_send_xon) {
hw 1235 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
hw 1236 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
hw 1238 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
hw 1239 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
hw 1255 dev/pci/if_em_hw.c em_setup_fiber_serdes_link(struct em_hw *hw)
hw 1271 dev/pci/if_em_hw.c if (hw->mac_type == em_82571 || hw->mac_type == em_82572)
hw 1272 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);
hw 1280 dev/pci/if_em_hw.c ctrl = E1000_READ_REG(hw, CTRL);
hw 1281 dev/pci/if_em_hw.c if (hw->media_type == em_media_type_fiber)
hw 1282 dev/pci/if_em_hw.c signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0;
hw 1284 dev/pci/if_em_hw.c ret_val = em_adjust_serdes_amplitude(hw);
hw 1292 dev/pci/if_em_hw.c ret_val = em_set_vco_speed(hw);
hw 1296 dev/pci/if_em_hw.c em_config_collision_dist(hw);
hw 1313 dev/pci/if_em_hw.c switch (hw->fc) {
hw 1351 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, TXCW, txcw);
hw 1352 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, ctrl);
hw 1353 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 1355 dev/pci/if_em_hw.c hw->txcw = txcw;
hw 1364 dev/pci/if_em_hw.c if (hw->media_type == em_media_type_internal_serdes ||
hw 1365 dev/pci/if_em_hw.c (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
hw 1369 dev/pci/if_em_hw.c status = E1000_READ_REG(hw, STATUS);
hw 1374 dev/pci/if_em_hw.c hw->autoneg_failed = 1;
hw 1380 dev/pci/if_em_hw.c ret_val = em_check_for_link(hw);
hw 1385 dev/pci/if_em_hw.c hw->autoneg_failed = 0;
hw 1387 dev/pci/if_em_hw.c hw->autoneg_failed = 0;
hw 1402 dev/pci/if_em_hw.c em_copper_link_preconfig(struct em_hw *hw)
hw 1410 dev/pci/if_em_hw.c ctrl = E1000_READ_REG(hw, CTRL);
hw 1415 dev/pci/if_em_hw.c if (hw->mac_type > em_82543) {
hw 1418 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, ctrl);
hw 1421 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, ctrl);
hw 1422 dev/pci/if_em_hw.c ret_val = em_phy_hw_reset(hw);
hw 1428 dev/pci/if_em_hw.c ret_val = em_detect_gig_phy(hw);
hw 1433 dev/pci/if_em_hw.c DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
hw 1436 dev/pci/if_em_hw.c ret_val = em_set_phy_mode(hw);
hw 1440 dev/pci/if_em_hw.c if ((hw->mac_type == em_82545_rev_3) ||
hw 1441 dev/pci/if_em_hw.c (hw->mac_type == em_82546_rev_3)) {
hw 1442 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
hw 1444 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
hw 1447 dev/pci/if_em_hw.c if (hw->mac_type <= em_82543 ||
hw 1448 dev/pci/if_em_hw.c hw->mac_type == em_82541 || hw->mac_type == em_82547 ||
hw 1449 dev/pci/if_em_hw.c hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2)
hw 1450 dev/pci/if_em_hw.c hw->phy_reset_disable = FALSE;
hw 1462 dev/pci/if_em_hw.c em_copper_link_igp_setup(struct em_hw *hw)
hw 1470 dev/pci/if_em_hw.c if (hw->phy_reset_disable)
hw 1473 dev/pci/if_em_hw.c ret_val = em_phy_reset(hw);
hw 1481 dev/pci/if_em_hw.c if (hw->mac_type != em_ich8lan) {
hw 1483 dev/pci/if_em_hw.c led_ctrl = E1000_READ_REG(hw, LEDCTL);
hw 1486 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
hw 1490 dev/pci/if_em_hw.c if (hw->phy_type == em_phy_igp) {
hw 1492 dev/pci/if_em_hw.c ret_val = em_set_d3_lplu_state(hw, FALSE);
hw 1500 dev/pci/if_em_hw.c ret_val = em_set_d0_lplu_state(hw, FALSE);
hw 1506 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
hw 1510 dev/pci/if_em_hw.c if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
hw 1511 dev/pci/if_em_hw.c hw->dsp_config_state = em_dsp_config_disabled;
hw 1514 dev/pci/if_em_hw.c hw->mdix = 1;
hw 1517 dev/pci/if_em_hw.c hw->dsp_config_state = em_dsp_config_enabled;
hw 1520 dev/pci/if_em_hw.c switch (hw->mdix) {
hw 1533 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
hw 1538 dev/pci/if_em_hw.c if (hw->autoneg) {
hw 1539 dev/pci/if_em_hw.c em_ms_type phy_ms_setting = hw->master_slave;
hw 1541 dev/pci/if_em_hw.c if (hw->ffe_config_state == em_ffe_config_active)
hw 1542 dev/pci/if_em_hw.c hw->ffe_config_state = em_ffe_config_enabled;
hw 1544 dev/pci/if_em_hw.c if (hw->dsp_config_state == em_dsp_config_activated)
hw 1545 dev/pci/if_em_hw.c hw->dsp_config_state = em_dsp_config_enabled;
hw 1550 dev/pci/if_em_hw.c if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
hw 1552 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
hw 1557 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
hw 1562 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
hw 1566 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
hw 1571 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
hw 1576 dev/pci/if_em_hw.c hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
hw 1596 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
hw 1610 dev/pci/if_em_hw.c em_copper_link_ggp_setup(struct em_hw *hw)
hw 1618 dev/pci/if_em_hw.c if (!hw->phy_reset_disable) {
hw 1621 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
hw 1630 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
hw 1642 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
hw 1648 dev/pci/if_em_hw.c switch (hw->mdix) {
hw 1668 dev/pci/if_em_hw.c if (hw->disable_polarity_correction == 1)
hw 1670 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
hw 1676 dev/pci/if_em_hw.c ret_val = em_phy_reset(hw);
hw 1683 dev/pci/if_em_hw.c if (hw->mac_type == em_80003es2lan) {
hw 1685 dev/pci/if_em_hw.c ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
hw 1691 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
hw 1696 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
hw 1701 dev/pci/if_em_hw.c reg_data = E1000_READ_REG(hw, CTRL_EXT);
hw 1703 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
hw 1705 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
hw 1714 dev/pci/if_em_hw.c if (em_check_mng_mode(hw) == FALSE) {
hw 1717 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
hw 1722 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
hw 1728 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
hw 1738 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
hw 1743 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
hw 1758 dev/pci/if_em_hw.c em_copper_link_mgp_setup(struct em_hw *hw)
hw 1765 dev/pci/if_em_hw.c if (hw->phy_reset_disable)
hw 1769 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
hw 1784 dev/pci/if_em_hw.c switch (hw->mdix) {
hw 1807 dev/pci/if_em_hw.c if (hw->disable_polarity_correction == 1)
hw 1809 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
hw 1813 dev/pci/if_em_hw.c if (hw->phy_revision < M88E1011_I_REV_4) {
hw 1817 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
hw 1823 dev/pci/if_em_hw.c if ((hw->phy_revision == E1000_REVISION_2) &&
hw 1824 dev/pci/if_em_hw.c (hw->phy_id == M88E1111_I_PHY_ID)) {
hw 1828 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw,
hw 1838 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw,
hw 1846 dev/pci/if_em_hw.c ret_val = em_phy_reset(hw);
hw 1862 dev/pci/if_em_hw.c em_copper_link_autoneg(struct em_hw *hw)
hw 1872 dev/pci/if_em_hw.c hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
hw 1877 dev/pci/if_em_hw.c if (hw->autoneg_advertised == 0)
hw 1878 dev/pci/if_em_hw.c hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
hw 1881 dev/pci/if_em_hw.c if (hw->phy_type == em_phy_ife)
hw 1882 dev/pci/if_em_hw.c hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
hw 1885 dev/pci/if_em_hw.c ret_val = em_phy_setup_autoneg(hw);
hw 1895 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data);
hw 1900 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data);
hw 1907 dev/pci/if_em_hw.c if (hw->wait_autoneg_complete) {
hw 1908 dev/pci/if_em_hw.c ret_val = em_wait_autoneg(hw);
hw 1915 dev/pci/if_em_hw.c hw->get_link_status = TRUE;
hw 1933 dev/pci/if_em_hw.c em_copper_link_postconfig(struct em_hw *hw)
hw 1938 dev/pci/if_em_hw.c if (hw->mac_type >= em_82544) {
hw 1939 dev/pci/if_em_hw.c em_config_collision_dist(hw);
hw 1941 dev/pci/if_em_hw.c ret_val = em_config_mac_to_phy(hw);
hw 1947 dev/pci/if_em_hw.c ret_val = em_config_fc_after_link_up(hw);
hw 1954 dev/pci/if_em_hw.c if (hw->phy_type == em_phy_igp) {
hw 1955 dev/pci/if_em_hw.c ret_val = em_config_dsp_after_link_change(hw, TRUE);
hw 1971 dev/pci/if_em_hw.c em_setup_copper_link(struct em_hw *hw)
hw 1980 dev/pci/if_em_hw.c switch (hw->mac_type) {
hw 1986 dev/pci/if_em_hw.c ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
hw 1989 dev/pci/if_em_hw.c ret_val = em_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data);
hw 1993 dev/pci/if_em_hw.c ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
hw 2001 dev/pci/if_em_hw.c ret_val = em_copper_link_preconfig(hw);
hw 2005 dev/pci/if_em_hw.c switch (hw->mac_type) {
hw 2010 dev/pci/if_em_hw.c ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
hw 2019 dev/pci/if_em_hw.c if (hw->phy_type == em_phy_igp ||
hw 2020 dev/pci/if_em_hw.c hw->phy_type == em_phy_igp_3 ||
hw 2021 dev/pci/if_em_hw.c hw->phy_type == em_phy_igp_2) {
hw 2022 dev/pci/if_em_hw.c ret_val = em_copper_link_igp_setup(hw);
hw 2025 dev/pci/if_em_hw.c } else if (hw->phy_type == em_phy_m88) {
hw 2026 dev/pci/if_em_hw.c ret_val = em_copper_link_mgp_setup(hw);
hw 2029 dev/pci/if_em_hw.c } else if (hw->phy_type == em_phy_gg82563) {
hw 2030 dev/pci/if_em_hw.c ret_val = em_copper_link_ggp_setup(hw);
hw 2035 dev/pci/if_em_hw.c if (hw->autoneg) {
hw 2038 dev/pci/if_em_hw.c ret_val = em_copper_link_autoneg(hw);
hw 2045 dev/pci/if_em_hw.c ret_val = em_phy_force_speed_duplex(hw);
hw 2056 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
hw 2059 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
hw 2065 dev/pci/if_em_hw.c ret_val = em_copper_link_postconfig(hw);
hw 2085 dev/pci/if_em_hw.c em_configure_kmrn_for_10_100(struct em_hw *hw, uint16_t duplex)
hw 2094 dev/pci/if_em_hw.c ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
hw 2100 dev/pci/if_em_hw.c tipg = E1000_READ_REG(hw, TIPG);
hw 2103 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, TIPG, tipg);
hw 2105 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
hw 2115 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
hw 2121 dev/pci/if_em_hw.c em_configure_kmrn_for_1000(struct em_hw *hw)
hw 2130 dev/pci/if_em_hw.c ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
hw 2136 dev/pci/if_em_hw.c tipg = E1000_READ_REG(hw, TIPG);
hw 2139 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, TIPG, tipg);
hw 2141 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
hw 2147 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
hw 2158 dev/pci/if_em_hw.c em_phy_setup_autoneg(struct em_hw *hw)
hw 2167 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
hw 2171 dev/pci/if_em_hw.c if (hw->phy_type != em_phy_ife) {
hw 2173 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
hw 2193 dev/pci/if_em_hw.c DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
hw 2196 dev/pci/if_em_hw.c if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
hw 2202 dev/pci/if_em_hw.c if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
hw 2208 dev/pci/if_em_hw.c if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
hw 2214 dev/pci/if_em_hw.c if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
hw 2220 dev/pci/if_em_hw.c if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
hw 2225 dev/pci/if_em_hw.c if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
hw 2228 dev/pci/if_em_hw.c if (hw->phy_type == em_phy_ife) {
hw 2249 dev/pci/if_em_hw.c switch (hw->fc) {
hw 2286 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
hw 2292 dev/pci/if_em_hw.c if (hw->phy_type != em_phy_ife) {
hw 2293 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
hw 2307 dev/pci/if_em_hw.c em_phy_force_speed_duplex(struct em_hw *hw)
hw 2319 dev/pci/if_em_hw.c hw->fc = E1000_FC_NONE;
hw 2321 dev/pci/if_em_hw.c DEBUGOUT1("hw->fc = %d\n", hw->fc);
hw 2324 dev/pci/if_em_hw.c ctrl = E1000_READ_REG(hw, CTRL);
hw 2334 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
hw 2343 dev/pci/if_em_hw.c if (hw->forced_speed_duplex == em_100_full ||
hw 2344 dev/pci/if_em_hw.c hw->forced_speed_duplex == em_10_full) {
hw 2361 dev/pci/if_em_hw.c if (hw->forced_speed_duplex == em_100_full ||
hw 2362 dev/pci/if_em_hw.c hw->forced_speed_duplex == em_100_half) {
hw 2376 dev/pci/if_em_hw.c em_config_collision_dist(hw);
hw 2379 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, ctrl);
hw 2381 dev/pci/if_em_hw.c if ((hw->phy_type == em_phy_m88) ||
hw 2382 dev/pci/if_em_hw.c (hw->phy_type == em_phy_gg82563)) {
hw 2383 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
hw 2391 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
hw 2400 dev/pci/if_em_hw.c } else if (hw->phy_type == em_phy_ife) {
hw 2401 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
hw 2408 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
hw 2415 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
hw 2422 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
hw 2428 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
hw 2441 dev/pci/if_em_hw.c if (hw->wait_autoneg_complete) {
hw 2451 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
hw 2455 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
hw 2463 dev/pci/if_em_hw.c ((hw->phy_type == em_phy_m88) ||
hw 2464 dev/pci/if_em_hw.c (hw->phy_type == em_phy_gg82563))) {
hw 2466 dev/pci/if_em_hw.c ret_val = em_phy_reset_dsp(hw);
hw 2479 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
hw 2483 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
hw 2489 dev/pci/if_em_hw.c if (hw->phy_type == em_phy_m88) {
hw 2494 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
hw 2499 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
hw 2506 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
hw 2511 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
hw 2515 dev/pci/if_em_hw.c if ((hw->mac_type == em_82544 || hw->mac_type == em_82543) &&
hw 2516 dev/pci/if_em_hw.c (!hw->autoneg) && (hw->forced_speed_duplex == em_10_full ||
hw 2517 dev/pci/if_em_hw.c hw->forced_speed_duplex == em_10_half)) {
hw 2518 dev/pci/if_em_hw.c ret_val = em_polarity_reversal_workaround(hw);
hw 2522 dev/pci/if_em_hw.c } else if (hw->phy_type == em_phy_gg82563) {
hw 2526 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
hw 2531 dev/pci/if_em_hw.c if ((hw->forced_speed_duplex == em_10_full) ||
hw 2532 dev/pci/if_em_hw.c (hw->forced_speed_duplex == em_10_half))
hw 2540 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
hw 2556 dev/pci/if_em_hw.c em_config_collision_dist(struct em_hw *hw)
hw 2562 dev/pci/if_em_hw.c if (hw->mac_type < em_82543)
hw 2567 dev/pci/if_em_hw.c tctl = E1000_READ_REG(hw, TCTL);
hw 2572 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, TCTL, tctl);
hw 2573 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 2586 dev/pci/if_em_hw.c em_config_mac_to_phy(struct em_hw *hw)
hw 2596 dev/pci/if_em_hw.c if (hw->mac_type >= em_82544)
hw 2602 dev/pci/if_em_hw.c ctrl = E1000_READ_REG(hw, CTRL);
hw 2609 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
hw 2618 dev/pci/if_em_hw.c em_config_collision_dist(hw);
hw 2629 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, ctrl);
hw 2645 dev/pci/if_em_hw.c em_force_mac_fc(struct em_hw *hw)
hw 2652 dev/pci/if_em_hw.c ctrl = E1000_READ_REG(hw, CTRL);
hw 2672 dev/pci/if_em_hw.c switch (hw->fc) {
hw 2693 dev/pci/if_em_hw.c if (hw->mac_type == em_82542_rev2_0)
hw 2696 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, ctrl);
hw 2712 dev/pci/if_em_hw.c em_config_fc_after_link_up(struct em_hw *hw)
hw 2727 dev/pci/if_em_hw.c if (((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed)) ||
hw 2728 dev/pci/if_em_hw.c ((hw->media_type == em_media_type_internal_serdes) &&
hw 2729 dev/pci/if_em_hw.c (hw->autoneg_failed)) ||
hw 2730 dev/pci/if_em_hw.c ((hw->media_type == em_media_type_copper) && (!hw->autoneg))) {
hw 2731 dev/pci/if_em_hw.c ret_val = em_force_mac_fc(hw);
hw 2743 dev/pci/if_em_hw.c if ((hw->media_type == em_media_type_copper) && hw->autoneg) {
hw 2748 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
hw 2751 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
hw 2762 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV,
hw 2766 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY,
hw 2813 dev/pci/if_em_hw.c if (hw->original_fc == E1000_FC_FULL) {
hw 2814 dev/pci/if_em_hw.c hw->fc = E1000_FC_FULL;
hw 2817 dev/pci/if_em_hw.c hw->fc = E1000_FC_RX_PAUSE;
hw 2833 dev/pci/if_em_hw.c hw->fc = E1000_FC_TX_PAUSE;
hw 2848 dev/pci/if_em_hw.c hw->fc = E1000_FC_RX_PAUSE;
hw 2871 dev/pci/if_em_hw.c else if ((hw->original_fc == E1000_FC_NONE||
hw 2872 dev/pci/if_em_hw.c hw->original_fc == E1000_FC_TX_PAUSE) ||
hw 2873 dev/pci/if_em_hw.c hw->fc_strict_ieee) {
hw 2874 dev/pci/if_em_hw.c hw->fc = E1000_FC_NONE;
hw 2877 dev/pci/if_em_hw.c hw->fc = E1000_FC_RX_PAUSE;
hw 2885 dev/pci/if_em_hw.c ret_val = em_get_speed_and_duplex(hw, &speed, &duplex);
hw 2892 dev/pci/if_em_hw.c hw->fc = E1000_FC_NONE;
hw 2897 dev/pci/if_em_hw.c ret_val = em_force_mac_fc(hw);
hw 2917 dev/pci/if_em_hw.c em_check_for_link(struct em_hw *hw)
hw 2930 dev/pci/if_em_hw.c ctrl = E1000_READ_REG(hw, CTRL);
hw 2931 dev/pci/if_em_hw.c status = E1000_READ_REG(hw, STATUS);
hw 2937 dev/pci/if_em_hw.c if ((hw->media_type == em_media_type_fiber) ||
hw 2938 dev/pci/if_em_hw.c (hw->media_type == em_media_type_internal_serdes)) {
hw 2939 dev/pci/if_em_hw.c rxcw = E1000_READ_REG(hw, RXCW);
hw 2941 dev/pci/if_em_hw.c if (hw->media_type == em_media_type_fiber) {
hw 2942 dev/pci/if_em_hw.c signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0;
hw 2944 dev/pci/if_em_hw.c hw->get_link_status = FALSE;
hw 2954 dev/pci/if_em_hw.c if ((hw->media_type == em_media_type_copper) && hw->get_link_status) {
hw 2960 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
hw 2963 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
hw 2968 dev/pci/if_em_hw.c hw->get_link_status = FALSE;
hw 2971 dev/pci/if_em_hw.c em_check_downshift(hw);
hw 2981 dev/pci/if_em_hw.c if ((hw->mac_type == em_82544 || hw->mac_type == em_82543) &&
hw 2982 dev/pci/if_em_hw.c (!hw->autoneg) &&
hw 2983 dev/pci/if_em_hw.c (hw->forced_speed_duplex == em_10_full ||
hw 2984 dev/pci/if_em_hw.c hw->forced_speed_duplex == em_10_half)) {
hw 2985 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, IMC, 0xffffffff);
hw 2986 dev/pci/if_em_hw.c ret_val = em_polarity_reversal_workaround(hw);
hw 2987 dev/pci/if_em_hw.c icr = E1000_READ_REG(hw, ICR);
hw 2988 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC));
hw 2989 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK);
hw 2994 dev/pci/if_em_hw.c em_config_dsp_after_link_change(hw, FALSE);
hw 3001 dev/pci/if_em_hw.c if (!hw->autoneg) return -E1000_ERR_CONFIG;
hw 3004 dev/pci/if_em_hw.c em_config_dsp_after_link_change(hw, TRUE);
hw 3014 dev/pci/if_em_hw.c if (hw->mac_type >= em_82544)
hw 3015 dev/pci/if_em_hw.c em_config_collision_dist(hw);
hw 3017 dev/pci/if_em_hw.c ret_val = em_config_mac_to_phy(hw);
hw 3028 dev/pci/if_em_hw.c ret_val = em_config_fc_after_link_up(hw);
hw 3041 dev/pci/if_em_hw.c if (hw->tbi_compatibility_en) {
hw 3043 dev/pci/if_em_hw.c ret_val = em_get_speed_and_duplex(hw, &speed, &duplex);
hw 3052 dev/pci/if_em_hw.c if (hw->tbi_compatibility_on) {
hw 3054 dev/pci/if_em_hw.c rctl = E1000_READ_REG(hw, RCTL);
hw 3056 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, RCTL, rctl);
hw 3057 dev/pci/if_em_hw.c hw->tbi_compatibility_on = FALSE;
hw 3065 dev/pci/if_em_hw.c if (!hw->tbi_compatibility_on) {
hw 3066 dev/pci/if_em_hw.c hw->tbi_compatibility_on = TRUE;
hw 3067 dev/pci/if_em_hw.c rctl = E1000_READ_REG(hw, RCTL);
hw 3069 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, RCTL, rctl);
hw 3081 dev/pci/if_em_hw.c else if ((((hw->media_type == em_media_type_fiber) &&
hw 3083 dev/pci/if_em_hw.c (hw->media_type == em_media_type_internal_serdes)) &&
hw 3086 dev/pci/if_em_hw.c if (hw->autoneg_failed == 0) {
hw 3087 dev/pci/if_em_hw.c hw->autoneg_failed = 1;
hw 3093 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
hw 3096 dev/pci/if_em_hw.c ctrl = E1000_READ_REG(hw, CTRL);
hw 3098 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, ctrl);
hw 3101 dev/pci/if_em_hw.c ret_val = em_config_fc_after_link_up(hw);
hw 3112 dev/pci/if_em_hw.c else if (((hw->media_type == em_media_type_fiber) ||
hw 3113 dev/pci/if_em_hw.c (hw->media_type == em_media_type_internal_serdes)) &&
hw 3116 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, TXCW, hw->txcw);
hw 3117 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
hw 3119 dev/pci/if_em_hw.c hw->serdes_link_down = FALSE;
hw 3124 dev/pci/if_em_hw.c else if ((hw->media_type == em_media_type_internal_serdes) &&
hw 3125 dev/pci/if_em_hw.c !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
hw 3128 dev/pci/if_em_hw.c if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
hw 3130 dev/pci/if_em_hw.c hw->serdes_link_down = FALSE;
hw 3134 dev/pci/if_em_hw.c hw->serdes_link_down = TRUE;
hw 3138 dev/pci/if_em_hw.c if ((hw->media_type == em_media_type_internal_serdes) &&
hw 3139 dev/pci/if_em_hw.c (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
hw 3140 dev/pci/if_em_hw.c hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
hw 3153 dev/pci/if_em_hw.c em_get_speed_and_duplex(struct em_hw *hw,
hw 3163 dev/pci/if_em_hw.c if (hw->mac_type >= em_82543) {
hw 3164 dev/pci/if_em_hw.c status = E1000_READ_REG(hw, STATUS);
hw 3193 dev/pci/if_em_hw.c if (hw->phy_type == em_phy_igp && hw->speed_downgraded) {
hw 3194 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
hw 3201 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
hw 3210 dev/pci/if_em_hw.c if ((hw->mac_type == em_80003es2lan) &&
hw 3211 dev/pci/if_em_hw.c (hw->media_type == em_media_type_copper)) {
hw 3213 dev/pci/if_em_hw.c ret_val = em_configure_kmrn_for_1000(hw);
hw 3215 dev/pci/if_em_hw.c ret_val = em_configure_kmrn_for_10_100(hw, *duplex);
hw 3220 dev/pci/if_em_hw.c if ((hw->phy_type == em_phy_igp_3) && (*speed == SPEED_1000)) {
hw 3221 dev/pci/if_em_hw.c ret_val = em_kumeran_lock_loss_workaround(hw);
hw 3235 dev/pci/if_em_hw.c em_wait_autoneg(struct em_hw *hw)
hw 3249 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
hw 3252 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
hw 3270 dev/pci/if_em_hw.c em_raise_mdi_clk(struct em_hw *hw,
hw 3276 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
hw 3277 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 3288 dev/pci/if_em_hw.c em_lower_mdi_clk(struct em_hw *hw,
hw 3294 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
hw 3295 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 3309 dev/pci/if_em_hw.c em_shift_out_mdi_bits(struct em_hw *hw,
hw 3323 dev/pci/if_em_hw.c ctrl = E1000_READ_REG(hw, CTRL);
hw 3339 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, ctrl);
hw 3340 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 3344 dev/pci/if_em_hw.c em_raise_mdi_clk(hw, &ctrl);
hw 3345 dev/pci/if_em_hw.c em_lower_mdi_clk(hw, &ctrl);
hw 3359 dev/pci/if_em_hw.c em_shift_in_mdi_bits(struct em_hw *hw)
hw 3372 dev/pci/if_em_hw.c ctrl = E1000_READ_REG(hw, CTRL);
hw 3378 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, ctrl);
hw 3379 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 3385 dev/pci/if_em_hw.c em_raise_mdi_clk(hw, &ctrl);
hw 3386 dev/pci/if_em_hw.c em_lower_mdi_clk(hw, &ctrl);
hw 3390 dev/pci/if_em_hw.c em_raise_mdi_clk(hw, &ctrl);
hw 3391 dev/pci/if_em_hw.c ctrl = E1000_READ_REG(hw, CTRL);
hw 3395 dev/pci/if_em_hw.c em_lower_mdi_clk(hw, &ctrl);
hw 3398 dev/pci/if_em_hw.c em_raise_mdi_clk(hw, &ctrl);
hw 3399 dev/pci/if_em_hw.c em_lower_mdi_clk(hw, &ctrl);
hw 3405 dev/pci/if_em_hw.c em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask)
hw 3414 dev/pci/if_em_hw.c if (hw->swfwhw_semaphore_present)
hw 3415 dev/pci/if_em_hw.c return em_get_software_flag(hw);
hw 3417 dev/pci/if_em_hw.c if (!hw->swfw_sync_present)
hw 3418 dev/pci/if_em_hw.c return em_get_hw_eeprom_semaphore(hw);
hw 3421 dev/pci/if_em_hw.c if (em_get_hw_eeprom_semaphore(hw))
hw 3424 dev/pci/if_em_hw.c swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
hw 3431 dev/pci/if_em_hw.c em_put_hw_eeprom_semaphore(hw);
hw 3442 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
hw 3444 dev/pci/if_em_hw.c em_put_hw_eeprom_semaphore(hw);
hw 3449 dev/pci/if_em_hw.c em_swfw_sync_release(struct em_hw *hw, uint16_t mask)
hw 3456 dev/pci/if_em_hw.c if (hw->swfwhw_semaphore_present) {
hw 3457 dev/pci/if_em_hw.c em_release_software_flag(hw);
hw 3461 dev/pci/if_em_hw.c if (!hw->swfw_sync_present) {
hw 3462 dev/pci/if_em_hw.c em_put_hw_eeprom_semaphore(hw);
hw 3468 dev/pci/if_em_hw.c while (em_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
hw 3471 dev/pci/if_em_hw.c swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
hw 3473 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
hw 3475 dev/pci/if_em_hw.c em_put_hw_eeprom_semaphore(hw);
hw 3485 dev/pci/if_em_hw.c em_read_phy_reg(struct em_hw *hw,
hw 3494 dev/pci/if_em_hw.c if ((hw->mac_type == em_80003es2lan) &&
hw 3495 dev/pci/if_em_hw.c (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
hw 3500 dev/pci/if_em_hw.c if (em_swfw_sync_acquire(hw, swfw))
hw 3503 dev/pci/if_em_hw.c if ((hw->phy_type == em_phy_igp ||
hw 3504 dev/pci/if_em_hw.c hw->phy_type == em_phy_igp_3 ||
hw 3505 dev/pci/if_em_hw.c hw->phy_type == em_phy_igp_2) &&
hw 3507 dev/pci/if_em_hw.c ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
hw 3510 dev/pci/if_em_hw.c em_swfw_sync_release(hw, swfw);
hw 3513 dev/pci/if_em_hw.c } else if (hw->phy_type == em_phy_gg82563) {
hw 3515 dev/pci/if_em_hw.c (hw->mac_type == em_80003es2lan)) {
hw 3518 dev/pci/if_em_hw.c ret_val = em_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
hw 3524 dev/pci/if_em_hw.c ret_val = em_write_phy_reg_ex(hw,
hw 3530 dev/pci/if_em_hw.c em_swfw_sync_release(hw, swfw);
hw 3536 dev/pci/if_em_hw.c ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
hw 3539 dev/pci/if_em_hw.c em_swfw_sync_release(hw, swfw);
hw 3544 dev/pci/if_em_hw.c em_read_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr,
hw 3558 dev/pci/if_em_hw.c if (hw->mac_type > em_82543) {
hw 3567 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, MDIC, mdic);
hw 3572 dev/pci/if_em_hw.c mdic = E1000_READ_REG(hw, MDIC);
hw 3589 dev/pci/if_em_hw.c em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
hw 3605 dev/pci/if_em_hw.c em_shift_out_mdi_bits(hw, mdic, 14);
hw 3611 dev/pci/if_em_hw.c *phy_data = em_shift_in_mdi_bits(hw);
hw 3624 dev/pci/if_em_hw.c em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr,
hw 3632 dev/pci/if_em_hw.c if ((hw->mac_type == em_80003es2lan) &&
hw 3633 dev/pci/if_em_hw.c (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
hw 3638 dev/pci/if_em_hw.c if (em_swfw_sync_acquire(hw, swfw))
hw 3641 dev/pci/if_em_hw.c if ((hw->phy_type == em_phy_igp ||
hw 3642 dev/pci/if_em_hw.c hw->phy_type == em_phy_igp_3 ||
hw 3643 dev/pci/if_em_hw.c hw->phy_type == em_phy_igp_2) &&
hw 3645 dev/pci/if_em_hw.c ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
hw 3648 dev/pci/if_em_hw.c em_swfw_sync_release(hw, swfw);
hw 3651 dev/pci/if_em_hw.c } else if (hw->phy_type == em_phy_gg82563) {
hw 3653 dev/pci/if_em_hw.c (hw->mac_type == em_80003es2lan)) {
hw 3656 dev/pci/if_em_hw.c ret_val = em_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
hw 3662 dev/pci/if_em_hw.c ret_val = em_write_phy_reg_ex(hw,
hw 3668 dev/pci/if_em_hw.c em_swfw_sync_release(hw, swfw);
hw 3674 dev/pci/if_em_hw.c ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
hw 3677 dev/pci/if_em_hw.c em_swfw_sync_release(hw, swfw);
hw 3682 dev/pci/if_em_hw.c em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr,
hw 3696 dev/pci/if_em_hw.c if (hw->mac_type > em_82543) {
hw 3706 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, MDIC, mdic);
hw 3711 dev/pci/if_em_hw.c mdic = E1000_READ_REG(hw, MDIC);
hw 3724 dev/pci/if_em_hw.c em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
hw 3737 dev/pci/if_em_hw.c em_shift_out_mdi_bits(hw, mdic, 32);
hw 3744 dev/pci/if_em_hw.c em_read_kmrn_reg(struct em_hw *hw,
hw 3752 dev/pci/if_em_hw.c if ((hw->mac_type == em_80003es2lan) &&
hw 3753 dev/pci/if_em_hw.c (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
hw 3758 dev/pci/if_em_hw.c if (em_swfw_sync_acquire(hw, swfw))
hw 3765 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
hw 3769 dev/pci/if_em_hw.c reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
hw 3772 dev/pci/if_em_hw.c em_swfw_sync_release(hw, swfw);
hw 3777 dev/pci/if_em_hw.c em_write_kmrn_reg(struct em_hw *hw,
hw 3785 dev/pci/if_em_hw.c if ((hw->mac_type == em_80003es2lan) &&
hw 3786 dev/pci/if_em_hw.c (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
hw 3791 dev/pci/if_em_hw.c if (em_swfw_sync_acquire(hw, swfw))
hw 3796 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
hw 3799 dev/pci/if_em_hw.c em_swfw_sync_release(hw, swfw);
hw 3809 dev/pci/if_em_hw.c em_phy_hw_reset(struct em_hw *hw)
hw 3820 dev/pci/if_em_hw.c ret_val = em_check_phy_reset_block(hw);
hw 3826 dev/pci/if_em_hw.c if (hw->mac_type > em_82543) {
hw 3827 dev/pci/if_em_hw.c if ((hw->mac_type == em_80003es2lan) &&
hw 3828 dev/pci/if_em_hw.c (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
hw 3833 dev/pci/if_em_hw.c if (em_swfw_sync_acquire(hw, swfw)) {
hw 3843 dev/pci/if_em_hw.c ctrl = E1000_READ_REG(hw, CTRL);
hw 3844 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
hw 3845 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 3847 dev/pci/if_em_hw.c if (hw->mac_type < em_82571)
hw 3852 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, ctrl);
hw 3853 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 3855 dev/pci/if_em_hw.c if (hw->mac_type >= em_82571)
hw 3857 dev/pci/if_em_hw.c em_swfw_sync_release(hw, swfw);
hw 3862 dev/pci/if_em_hw.c ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
hw 3865 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
hw 3866 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 3869 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
hw 3870 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 3874 dev/pci/if_em_hw.c if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
hw 3876 dev/pci/if_em_hw.c led_ctrl = E1000_READ_REG(hw, LEDCTL);
hw 3879 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
hw 3883 dev/pci/if_em_hw.c ret_val = em_get_phy_cfg_done(hw);
hw 3886 dev/pci/if_em_hw.c em_release_software_semaphore(hw);
hw 3888 dev/pci/if_em_hw.c if ((hw->mac_type == em_ich8lan) && (hw->phy_type == em_phy_igp_3))
hw 3889 dev/pci/if_em_hw.c ret_val = em_init_lcd_from_nvm(hw);
hw 3902 dev/pci/if_em_hw.c em_phy_reset(struct em_hw *hw)
hw 3911 dev/pci/if_em_hw.c ret_val = em_check_phy_reset_block(hw);
hw 3915 dev/pci/if_em_hw.c switch (hw->phy_type) {
hw 3920 dev/pci/if_em_hw.c ret_val = em_phy_hw_reset(hw);
hw 3925 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data);
hw 3930 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data);
hw 3938 dev/pci/if_em_hw.c if (hw->phy_type == em_phy_igp || hw->phy_type == em_phy_igp_2)
hw 3939 dev/pci/if_em_hw.c em_phy_init_script(hw);
hw 3959 dev/pci/if_em_hw.c em_kumeran_lock_loss_workaround(struct em_hw *hw)
hw 3966 dev/pci/if_em_hw.c if (hw->kmrn_lock_loss_workaround_disabled)
hw 3972 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
hw 3973 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
hw 3978 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
hw 3982 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
hw 3991 dev/pci/if_em_hw.c em_phy_hw_reset(hw);
hw 3995 dev/pci/if_em_hw.c reg = E1000_READ_REG(hw, PHY_CTRL);
hw 3996 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
hw 4012 dev/pci/if_em_hw.c em_detect_gig_phy(struct em_hw *hw)
hw 4020 dev/pci/if_em_hw.c if (hw->phy_id != 0)
hw 4026 dev/pci/if_em_hw.c if (hw->mac_type == em_82571 ||
hw 4027 dev/pci/if_em_hw.c hw->mac_type == em_82572) {
hw 4028 dev/pci/if_em_hw.c hw->phy_id = IGP01E1000_I_PHY_ID;
hw 4029 dev/pci/if_em_hw.c hw->phy_type = em_phy_igp_2;
hw 4039 dev/pci/if_em_hw.c if (hw->mac_type == em_80003es2lan)
hw 4040 dev/pci/if_em_hw.c hw->phy_type = em_phy_gg82563;
hw 4043 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_ID1, &phy_id_high);
hw 4047 dev/pci/if_em_hw.c hw->phy_id = (uint32_t) (phy_id_high << 16);
hw 4049 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_ID2, &phy_id_low);
hw 4053 dev/pci/if_em_hw.c hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
hw 4054 dev/pci/if_em_hw.c hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
hw 4056 dev/pci/if_em_hw.c switch (hw->mac_type) {
hw 4058 dev/pci/if_em_hw.c if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
hw 4061 dev/pci/if_em_hw.c if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
hw 4068 dev/pci/if_em_hw.c if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
hw 4074 dev/pci/if_em_hw.c if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
hw 4077 dev/pci/if_em_hw.c if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
hw 4080 dev/pci/if_em_hw.c if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
hw 4083 dev/pci/if_em_hw.c if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE;
hw 4084 dev/pci/if_em_hw.c if (hw->phy_id == IFE_E_PHY_ID) match = TRUE;
hw 4085 dev/pci/if_em_hw.c if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE;
hw 4086 dev/pci/if_em_hw.c if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE;
hw 4089 dev/pci/if_em_hw.c DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
hw 4092 dev/pci/if_em_hw.c phy_init_status = em_set_phy_type(hw);
hw 4095 dev/pci/if_em_hw.c DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
hw 4098 dev/pci/if_em_hw.c DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
hw 4108 dev/pci/if_em_hw.c em_phy_reset_dsp(struct em_hw *hw)
hw 4114 dev/pci/if_em_hw.c if (hw->phy_type != em_phy_gg82563) {
hw 4115 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, 29, 0x001d);
hw 4118 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, 30, 0x00c1);
hw 4120 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, 30, 0x0000);
hw 4136 dev/pci/if_em_hw.c em_init_eeprom_params(struct em_hw *hw)
hw 4138 dev/pci/if_em_hw.c struct em_eeprom_info *eeprom = &hw->eeprom;
hw 4139 dev/pci/if_em_hw.c uint32_t eecd = E1000_READ_REG(hw, EECD);
hw 4145 dev/pci/if_em_hw.c switch (hw->mac_type) {
hw 4234 dev/pci/if_em_hw.c if (em_is_onboard_nvm_eeprom(hw) == FALSE) {
hw 4241 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, EECD, eecd);
hw 4261 dev/pci/if_em_hw.c uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG);
hw 4270 dev/pci/if_em_hw.c if (hw->eeprom_shadow_ram != NULL) {
hw 4272 dev/pci/if_em_hw.c hw->eeprom_shadow_ram[i].modified = FALSE;
hw 4273 dev/pci/if_em_hw.c hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
hw 4277 dev/pci/if_em_hw.c hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
hw 4280 dev/pci/if_em_hw.c hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1;
hw 4281 dev/pci/if_em_hw.c hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
hw 4283 dev/pci/if_em_hw.c hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
hw 4285 dev/pci/if_em_hw.c hw->flash_bank_size /= 2 * sizeof(uint16_t);
hw 4297 dev/pci/if_em_hw.c if (hw->mac_type <= em_82547_rev_2) {
hw 4300 dev/pci/if_em_hw.c ret_val = em_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
hw 4326 dev/pci/if_em_hw.c em_raise_ee_clk(struct em_hw *hw,
hw 4333 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, EECD, *eecd);
hw 4334 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 4335 dev/pci/if_em_hw.c usec_delay(hw->eeprom.delay_usec);
hw 4345 dev/pci/if_em_hw.c em_lower_ee_clk(struct em_hw *hw,
hw 4352 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, EECD, *eecd);
hw 4353 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 4354 dev/pci/if_em_hw.c usec_delay(hw->eeprom.delay_usec);
hw 4365 dev/pci/if_em_hw.c em_shift_out_ee_bits(struct em_hw *hw,
hw 4369 dev/pci/if_em_hw.c struct em_eeprom_info *eeprom = &hw->eeprom;
hw 4378 dev/pci/if_em_hw.c eecd = E1000_READ_REG(hw, EECD);
hw 4395 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, EECD, eecd);
hw 4396 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 4400 dev/pci/if_em_hw.c em_raise_ee_clk(hw, &eecd);
hw 4401 dev/pci/if_em_hw.c em_lower_ee_clk(hw, &eecd);
hw 4409 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, EECD, eecd);
hw 4418 dev/pci/if_em_hw.c em_shift_in_ee_bits(struct em_hw *hw,
hw 4432 dev/pci/if_em_hw.c eecd = E1000_READ_REG(hw, EECD);
hw 4439 dev/pci/if_em_hw.c em_raise_ee_clk(hw, &eecd);
hw 4441 dev/pci/if_em_hw.c eecd = E1000_READ_REG(hw, EECD);
hw 4447 dev/pci/if_em_hw.c em_lower_ee_clk(hw, &eecd);
hw 4462 dev/pci/if_em_hw.c em_acquire_eeprom(struct em_hw *hw)
hw 4464 dev/pci/if_em_hw.c struct em_eeprom_info *eeprom = &hw->eeprom;
hw 4469 dev/pci/if_em_hw.c if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
hw 4471 dev/pci/if_em_hw.c eecd = E1000_READ_REG(hw, EECD);
hw 4473 dev/pci/if_em_hw.c if (hw->mac_type != em_82573) {
hw 4475 dev/pci/if_em_hw.c if (hw->mac_type > em_82544) {
hw 4477 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, EECD, eecd);
hw 4478 dev/pci/if_em_hw.c eecd = E1000_READ_REG(hw, EECD);
hw 4483 dev/pci/if_em_hw.c eecd = E1000_READ_REG(hw, EECD);
hw 4487 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, EECD, eecd);
hw 4489 dev/pci/if_em_hw.c em_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
hw 4500 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, EECD, eecd);
hw 4504 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, EECD, eecd);
hw 4508 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, EECD, eecd);
hw 4521 dev/pci/if_em_hw.c em_standby_eeprom(struct em_hw *hw)
hw 4523 dev/pci/if_em_hw.c struct em_eeprom_info *eeprom = &hw->eeprom;
hw 4526 dev/pci/if_em_hw.c eecd = E1000_READ_REG(hw, EECD);
hw 4530 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, EECD, eecd);
hw 4531 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 4536 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, EECD, eecd);
hw 4537 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 4542 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, EECD, eecd);
hw 4543 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 4548 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, EECD, eecd);
hw 4549 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 4554 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, EECD, eecd);
hw 4555 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 4558 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, EECD, eecd);
hw 4559 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 4570 dev/pci/if_em_hw.c em_release_eeprom(struct em_hw *hw)
hw 4576 dev/pci/if_em_hw.c eecd = E1000_READ_REG(hw, EECD);
hw 4578 dev/pci/if_em_hw.c if (hw->eeprom.type == em_eeprom_spi) {
hw 4582 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, EECD, eecd);
hw 4584 dev/pci/if_em_hw.c usec_delay(hw->eeprom.delay_usec);
hw 4585 dev/pci/if_em_hw.c } else if (hw->eeprom.type == em_eeprom_microwire) {
hw 4591 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, EECD, eecd);
hw 4595 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, EECD, eecd);
hw 4596 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 4597 dev/pci/if_em_hw.c usec_delay(hw->eeprom.delay_usec);
hw 4601 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, EECD, eecd);
hw 4602 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 4603 dev/pci/if_em_hw.c usec_delay(hw->eeprom.delay_usec);
hw 4607 dev/pci/if_em_hw.c if (hw->mac_type > em_82544) {
hw 4609 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, EECD, eecd);
hw 4612 dev/pci/if_em_hw.c em_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
hw 4621 dev/pci/if_em_hw.c em_spi_eeprom_ready(struct em_hw *hw)
hw 4635 dev/pci/if_em_hw.c em_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
hw 4636 dev/pci/if_em_hw.c hw->eeprom.opcode_bits);
hw 4637 dev/pci/if_em_hw.c spi_stat_reg = (uint8_t)em_shift_in_ee_bits(hw, 8);
hw 4644 dev/pci/if_em_hw.c em_standby_eeprom(hw);
hw 4667 dev/pci/if_em_hw.c em_read_eeprom(struct em_hw *hw,
hw 4672 dev/pci/if_em_hw.c struct em_eeprom_info *eeprom = &hw->eeprom;
hw 4679 dev/pci/if_em_hw.c em_init_eeprom_params(hw);
hw 4694 dev/pci/if_em_hw.c if (em_is_onboard_nvm_eeprom(hw) == TRUE &&
hw 4695 dev/pci/if_em_hw.c hw->eeprom.use_eerd == FALSE) {
hw 4697 dev/pci/if_em_hw.c if (em_acquire_eeprom(hw) != E1000_SUCCESS)
hw 4703 dev/pci/if_em_hw.c return em_read_eeprom_eerd(hw, offset, words, data);
hw 4707 dev/pci/if_em_hw.c return em_read_eeprom_ich8(hw, offset, words, data);
hw 4715 dev/pci/if_em_hw.c if (em_spi_eeprom_ready(hw)) {
hw 4716 dev/pci/if_em_hw.c em_release_eeprom(hw);
hw 4720 dev/pci/if_em_hw.c em_standby_eeprom(hw);
hw 4727 dev/pci/if_em_hw.c em_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
hw 4728 dev/pci/if_em_hw.c em_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
hw 4736 dev/pci/if_em_hw.c word_in = em_shift_in_ee_bits(hw, 16);
hw 4742 dev/pci/if_em_hw.c em_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
hw 4744 dev/pci/if_em_hw.c em_shift_out_ee_bits(hw, (uint16_t)(offset + i),
hw 4749 dev/pci/if_em_hw.c data[i] = em_shift_in_ee_bits(hw, 16);
hw 4750 dev/pci/if_em_hw.c em_standby_eeprom(hw);
hw 4755 dev/pci/if_em_hw.c em_release_eeprom(hw);
hw 4769 dev/pci/if_em_hw.c em_read_eeprom_eerd(struct em_hw *hw,
hw 4781 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, EERD, eerd);
hw 4782 dev/pci/if_em_hw.c error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
hw 4787 dev/pci/if_em_hw.c data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
hw 4803 dev/pci/if_em_hw.c em_write_eeprom_eewr(struct em_hw *hw,
hw 4812 dev/pci/if_em_hw.c if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
hw 4820 dev/pci/if_em_hw.c error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
hw 4825 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, EEWR, register_value);
hw 4827 dev/pci/if_em_hw.c error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
hw 4834 dev/pci/if_em_hw.c em_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
hw 4844 dev/pci/if_em_hw.c em_poll_eerd_eewr_done(struct em_hw *hw, int eerd)
hw 4852 dev/pci/if_em_hw.c reg = E1000_READ_REG(hw, EERD);
hw 4854 dev/pci/if_em_hw.c reg = E1000_READ_REG(hw, EEWR);
hw 4872 dev/pci/if_em_hw.c em_is_onboard_nvm_eeprom(struct em_hw *hw)
hw 4878 dev/pci/if_em_hw.c if (hw->mac_type == em_ich8lan)
hw 4881 dev/pci/if_em_hw.c if (hw->mac_type == em_82573) {
hw 4882 dev/pci/if_em_hw.c eecd = E1000_READ_REG(hw, EECD);
hw 4905 dev/pci/if_em_hw.c em_validate_eeprom_checksum(struct em_hw *hw)
hw 4912 dev/pci/if_em_hw.c if ((hw->mac_type == em_82573) &&
hw 4913 dev/pci/if_em_hw.c (em_is_onboard_nvm_eeprom(hw) == FALSE)) {
hw 4916 dev/pci/if_em_hw.c em_read_eeprom(hw, 0x10, 1, &eeprom_data);
hw 4922 dev/pci/if_em_hw.c em_read_eeprom(hw, 0x23, 1, &eeprom_data);
hw 4925 dev/pci/if_em_hw.c em_write_eeprom(hw, 0x23, 1, &eeprom_data);
hw 4926 dev/pci/if_em_hw.c em_update_eeprom_checksum(hw);
hw 4931 dev/pci/if_em_hw.c if (hw->mac_type == em_ich8lan) {
hw 4937 dev/pci/if_em_hw.c em_read_eeprom(hw, 0x19, 1, &eeprom_data);
hw 4940 dev/pci/if_em_hw.c em_write_eeprom(hw, 0x19, 1, &eeprom_data);
hw 4941 dev/pci/if_em_hw.c em_update_eeprom_checksum(hw);
hw 4946 dev/pci/if_em_hw.c if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
hw 4970 dev/pci/if_em_hw.c em_update_eeprom_checksum(struct em_hw *hw)
hw 4979 dev/pci/if_em_hw.c if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
hw 4986 dev/pci/if_em_hw.c if (em_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
hw 4989 dev/pci/if_em_hw.c } else if (hw->eeprom.type == em_eeprom_flash) {
hw 4990 dev/pci/if_em_hw.c em_commit_shadow_ram(hw);
hw 4991 dev/pci/if_em_hw.c } else if (hw->eeprom.type == em_eeprom_ich8) {
hw 4992 dev/pci/if_em_hw.c em_commit_shadow_ram(hw);
hw 4995 dev/pci/if_em_hw.c ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
hw 4997 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
hw 5015 dev/pci/if_em_hw.c em_write_eeprom(struct em_hw *hw,
hw 5020 dev/pci/if_em_hw.c struct em_eeprom_info *eeprom = &hw->eeprom;
hw 5027 dev/pci/if_em_hw.c em_init_eeprom_params(hw);
hw 5040 dev/pci/if_em_hw.c return em_write_eeprom_eewr(hw, offset, words, data);
hw 5043 dev/pci/if_em_hw.c return em_write_eeprom_ich8(hw, offset, words, data);
hw 5046 dev/pci/if_em_hw.c if (em_acquire_eeprom(hw) != E1000_SUCCESS)
hw 5050 dev/pci/if_em_hw.c status = em_write_eeprom_microwire(hw, offset, words, data);
hw 5052 dev/pci/if_em_hw.c status = em_write_eeprom_spi(hw, offset, words, data);
hw 5057 dev/pci/if_em_hw.c em_release_eeprom(hw);
hw 5072 dev/pci/if_em_hw.c em_write_eeprom_spi(struct em_hw *hw,
hw 5077 dev/pci/if_em_hw.c struct em_eeprom_info *eeprom = &hw->eeprom;
hw 5085 dev/pci/if_em_hw.c if (em_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
hw 5087 dev/pci/if_em_hw.c em_standby_eeprom(hw);
hw 5090 dev/pci/if_em_hw.c em_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
hw 5093 dev/pci/if_em_hw.c em_standby_eeprom(hw);
hw 5100 dev/pci/if_em_hw.c em_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
hw 5102 dev/pci/if_em_hw.c em_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
hw 5111 dev/pci/if_em_hw.c em_shift_out_ee_bits(hw, word_out, 16);
hw 5119 dev/pci/if_em_hw.c em_standby_eeprom(hw);
hw 5138 dev/pci/if_em_hw.c em_write_eeprom_microwire(struct em_hw *hw,
hw 5143 dev/pci/if_em_hw.c struct em_eeprom_info *eeprom = &hw->eeprom;
hw 5156 dev/pci/if_em_hw.c em_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
hw 5159 dev/pci/if_em_hw.c em_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
hw 5162 dev/pci/if_em_hw.c em_standby_eeprom(hw);
hw 5166 dev/pci/if_em_hw.c em_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
hw 5169 dev/pci/if_em_hw.c em_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
hw 5173 dev/pci/if_em_hw.c em_shift_out_ee_bits(hw, data[words_written], 16);
hw 5178 dev/pci/if_em_hw.c em_standby_eeprom(hw);
hw 5185 dev/pci/if_em_hw.c eecd = E1000_READ_REG(hw, EECD);
hw 5195 dev/pci/if_em_hw.c em_standby_eeprom(hw);
hw 5206 dev/pci/if_em_hw.c em_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
hw 5209 dev/pci/if_em_hw.c em_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
hw 5225 dev/pci/if_em_hw.c em_commit_shadow_ram(struct em_hw *hw)
hw 5238 dev/pci/if_em_hw.c if (hw->mac_type == em_82573) {
hw 5240 dev/pci/if_em_hw.c flop = E1000_READ_REG(hw, FLOP);
hw 5242 dev/pci/if_em_hw.c eecd = E1000_READ_REG(hw, EECD);
hw 5255 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
hw 5259 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD);
hw 5262 dev/pci/if_em_hw.c eecd = E1000_READ_REG(hw, EECD);
hw 5274 dev/pci/if_em_hw.c if (hw->mac_type == em_ich8lan && hw->eeprom_shadow_ram != NULL) {
hw 5278 dev/pci/if_em_hw.c if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) {
hw 5279 dev/pci/if_em_hw.c new_bank_offset = hw->flash_bank_size * 2;
hw 5281 dev/pci/if_em_hw.c em_erase_ich8_4k_segment(hw, 1);
hw 5283 dev/pci/if_em_hw.c old_bank_offset = hw->flash_bank_size * 2;
hw 5285 dev/pci/if_em_hw.c em_erase_ich8_4k_segment(hw, 0);
hw 5295 dev/pci/if_em_hw.c if (hw->eeprom_shadow_ram[i].modified == TRUE) {
hw 5296 dev/pci/if_em_hw.c low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word;
hw 5298 dev/pci/if_em_hw.c error = em_verify_write_ich8_byte(hw,
hw 5305 dev/pci/if_em_hw.c (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
hw 5309 dev/pci/if_em_hw.c em_read_ich8_byte(hw, (i << 1) + old_bank_offset,
hw 5312 dev/pci/if_em_hw.c error = em_verify_write_ich8_byte(hw,
hw 5318 dev/pci/if_em_hw.c em_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
hw 5337 dev/pci/if_em_hw.c error = em_verify_write_ich8_byte(hw,
hw 5356 dev/pci/if_em_hw.c em_read_ich8_byte(hw,
hw 5360 dev/pci/if_em_hw.c error = em_verify_write_ich8_byte(hw,
hw 5367 dev/pci/if_em_hw.c error = em_verify_write_ich8_byte(hw,
hw 5373 dev/pci/if_em_hw.c hw->eeprom_shadow_ram[i].modified = FALSE;
hw 5374 dev/pci/if_em_hw.c hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
hw 5389 dev/pci/if_em_hw.c em_read_part_num(struct em_hw *hw,
hw 5398 dev/pci/if_em_hw.c if (em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
hw 5406 dev/pci/if_em_hw.c if (em_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) {
hw 5423 dev/pci/if_em_hw.c em_read_mac_addr(struct em_hw * hw)
hw 5432 dev/pci/if_em_hw.c if (em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
hw 5436 dev/pci/if_em_hw.c hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
hw 5437 dev/pci/if_em_hw.c hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
hw 5440 dev/pci/if_em_hw.c switch (hw->mac_type) {
hw 5447 dev/pci/if_em_hw.c if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
hw 5448 dev/pci/if_em_hw.c hw->perm_mac_addr[5] ^= 0x01;
hw 5453 dev/pci/if_em_hw.c hw->mac_addr[i] = hw->perm_mac_addr[i];
hw 5467 dev/pci/if_em_hw.c em_init_rx_addrs(struct em_hw *hw)
hw 5477 dev/pci/if_em_hw.c em_rar_set(hw, hw->mac_addr, 0);
hw 5484 dev/pci/if_em_hw.c if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE))
hw 5486 dev/pci/if_em_hw.c if (hw->mac_type == em_ich8lan)
hw 5492 dev/pci/if_em_hw.c E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
hw 5493 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 5494 dev/pci/if_em_hw.c E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
hw 5495 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 5514 dev/pci/if_em_hw.c em_mc_addr_list_update(struct em_hw *hw,
hw 5528 dev/pci/if_em_hw.c hw->num_mc_addrs = mc_addr_count;
hw 5533 dev/pci/if_em_hw.c if (hw->mac_type == em_ich8lan)
hw 5539 dev/pci/if_em_hw.c if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE))
hw 5543 dev/pci/if_em_hw.c E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
hw 5544 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 5545 dev/pci/if_em_hw.c E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
hw 5546 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 5552 dev/pci/if_em_hw.c if (hw->mac_type == em_ich8lan)
hw 5556 dev/pci/if_em_hw.c E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
hw 5557 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 5571 dev/pci/if_em_hw.c hash_value = em_hash_mc_addr(hw,
hw 5581 dev/pci/if_em_hw.c em_rar_set(hw,
hw 5586 dev/pci/if_em_hw.c em_mta_set(hw, hash_value);
hw 5599 dev/pci/if_em_hw.c em_hash_mc_addr(struct em_hw *hw,
hw 5607 dev/pci/if_em_hw.c switch (hw->mc_filter_type) {
hw 5613 dev/pci/if_em_hw.c if (hw->mac_type == em_ich8lan) {
hw 5622 dev/pci/if_em_hw.c if (hw->mac_type == em_ich8lan) {
hw 5631 dev/pci/if_em_hw.c if (hw->mac_type == em_ich8lan) {
hw 5640 dev/pci/if_em_hw.c if (hw->mac_type == em_ich8lan) {
hw 5651 dev/pci/if_em_hw.c if (hw->mac_type == em_ich8lan)
hw 5664 dev/pci/if_em_hw.c em_mta_set(struct em_hw *hw,
hw 5680 dev/pci/if_em_hw.c if (hw->mac_type == em_ich8lan)
hw 5685 dev/pci/if_em_hw.c mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
hw 5693 dev/pci/if_em_hw.c if ((hw->mac_type == em_82544) && ((hash_reg & 0x1) == 1)) {
hw 5694 dev/pci/if_em_hw.c temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
hw 5695 dev/pci/if_em_hw.c E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
hw 5696 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 5697 dev/pci/if_em_hw.c E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
hw 5698 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 5700 dev/pci/if_em_hw.c E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
hw 5701 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 5713 dev/pci/if_em_hw.c em_rar_set(struct em_hw *hw,
hw 5745 dev/pci/if_em_hw.c switch (hw->mac_type) {
hw 5749 dev/pci/if_em_hw.c if (hw->leave_av_bit_off == TRUE)
hw 5757 dev/pci/if_em_hw.c E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
hw 5758 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 5759 dev/pci/if_em_hw.c E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
hw 5760 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 5769 dev/pci/if_em_hw.c em_clear_vfta(struct em_hw *hw)
hw 5776 dev/pci/if_em_hw.c if (hw->mac_type == em_ich8lan)
hw 5779 dev/pci/if_em_hw.c if (hw->mac_type == em_82573) {
hw 5780 dev/pci/if_em_hw.c if (hw->mng_cookie.vlan_id != 0) {
hw 5785 dev/pci/if_em_hw.c vfta_offset = (hw->mng_cookie.vlan_id >>
hw 5788 dev/pci/if_em_hw.c vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
hw 5797 dev/pci/if_em_hw.c E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
hw 5798 dev/pci/if_em_hw.c E1000_WRITE_FLUSH(hw);
hw 5803 dev/pci/if_em_hw.c em_id_led_init(struct em_hw * hw)
hw 5814 dev/pci/if_em_hw.c if (hw->mac_type < em_82540) {
hw 5819 dev/pci/if_em_hw.c ledctl = E1000_READ_REG(hw, LEDCTL);
hw 5820 dev/pci/if_em_hw.c hw->ledctl_default = ledctl;
hw 5821 dev/pci/if_em_hw.c hw->ledctl_mode1 = hw->ledctl_default;
hw 5822 dev/pci/if_em_hw.c hw->ledctl_mode2 = hw->ledctl_default;
hw 5824 dev/pci/if_em_hw.c if (em_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
hw 5829 dev/pci/if_em_hw.c if ((hw->mac_type == em_82573) &&
hw 5834 dev/pci/if_em_hw.c if (hw->mac_type == em_ich8lan)
hw 5846 dev/pci/if_em_hw.c hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
hw 5847 dev/pci/if_em_hw.c hw->ledctl_mode1 |= ledctl_on << (i << 3);
hw 5852 dev/pci/if_em_hw.c hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
hw 5853 dev/pci/if_em_hw.c hw->ledctl_mode1 |= ledctl_off << (i << 3);
hw 5863 dev/pci/if_em_hw.c hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
hw 5864 dev/pci/if_em_hw.c hw->ledctl_mode2 |= ledctl_on << (i << 3);
hw 5869 dev/pci/if_em_hw.c hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
hw 5870 dev/pci/if_em_hw.c hw->ledctl_mode2 |= ledctl_off << (i << 3);
hw 5886 dev/pci/if_em_hw.c em_clear_hw_cntrs(struct em_hw *hw)
hw 5890 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, CRCERRS);
hw 5891 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, SYMERRS);
hw 5892 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, MPC);
hw 5893 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, SCC);
hw 5894 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, ECOL);
hw 5895 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, MCC);
hw 5896 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, LATECOL);
hw 5897 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, COLC);
hw 5898 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, DC);
hw 5899 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, SEC);
hw 5900 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, RLEC);
hw 5901 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, XONRXC);
hw 5902 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, XONTXC);
hw 5903 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, XOFFRXC);
hw 5904 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, XOFFTXC);
hw 5905 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, FCRUC);
hw 5907 dev/pci/if_em_hw.c if (hw->mac_type != em_ich8lan) {
hw 5908 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, PRC64);
hw 5909 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, PRC127);
hw 5910 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, PRC255);
hw 5911 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, PRC511);
hw 5912 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, PRC1023);
hw 5913 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, PRC1522);
hw 5916 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, GPRC);
hw 5917 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, BPRC);
hw 5918 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, MPRC);
hw 5919 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, GPTC);
hw 5920 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, GORCL);
hw 5921 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, GORCH);
hw 5922 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, GOTCL);
hw 5923 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, GOTCH);
hw 5924 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, RNBC);
hw 5925 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, RUC);
hw 5926 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, RFC);
hw 5927 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, ROC);
hw 5928 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, RJC);
hw 5929 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, TORL);
hw 5930 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, TORH);
hw 5931 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, TOTL);
hw 5932 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, TOTH);
hw 5933 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, TPR);
hw 5934 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, TPT);
hw 5936 dev/pci/if_em_hw.c if (hw->mac_type != em_ich8lan) {
hw 5937 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, PTC64);
hw 5938 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, PTC127);
hw 5939 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, PTC255);
hw 5940 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, PTC511);
hw 5941 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, PTC1023);
hw 5942 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, PTC1522);
hw 5945 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, MPTC);
hw 5946 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, BPTC);
hw 5948 dev/pci/if_em_hw.c if (hw->mac_type < em_82543) return;
hw 5950 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, ALGNERRC);
hw 5951 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, RXERRC);
hw 5952 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, TNCRS);
hw 5953 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, CEXTERR);
hw 5954 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, TSCTC);
hw 5955 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, TSCTFC);
hw 5957 dev/pci/if_em_hw.c if (hw->mac_type <= em_82544) return;
hw 5959 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, MGTPRC);
hw 5960 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, MGTPDC);
hw 5961 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, MGTPTC);
hw 5963 dev/pci/if_em_hw.c if (hw->mac_type <= em_82547_rev_2) return;
hw 5965 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, IAC);
hw 5966 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, ICRXOC);
hw 5968 dev/pci/if_em_hw.c if (hw->mac_type == em_ich8lan) return;
hw 5970 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, ICRXPTC);
hw 5971 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, ICRXATC);
hw 5972 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, ICTXPTC);
hw 5973 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, ICTXATC);
hw 5974 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, ICTXQEC);
hw 5975 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, ICTXQMTC);
hw 5976 dev/pci/if_em_hw.c temp = E1000_READ_REG(hw, ICRXDMTC);
hw 5987 dev/pci/if_em_hw.c em_tbi_adjust_stats(struct em_hw *hw,
hw 6028 dev/pci/if_em_hw.c if (frame_len == hw->max_frame_size) {
hw 6065 dev/pci/if_em_hw.c em_get_bus_info(struct em_hw *hw)
hw 6071 dev/pci/if_em_hw.c switch (hw->mac_type) {
hw 6074 dev/pci/if_em_hw.c hw->bus_type = em_bus_type_unknown;
hw 6075 dev/pci/if_em_hw.c hw->bus_speed = em_bus_speed_unknown;
hw 6076 dev/pci/if_em_hw.c hw->bus_width = em_bus_width_unknown;
hw 6082 dev/pci/if_em_hw.c hw->bus_type = em_bus_type_pci_express;
hw 6083 dev/pci/if_em_hw.c hw->bus_speed = em_bus_speed_2500;
hw 6084 dev/pci/if_em_hw.c ret_val = em_read_pcie_cap_reg(hw,
hw 6088 dev/pci/if_em_hw.c hw->bus_width = em_bus_width_unknown;
hw 6090 dev/pci/if_em_hw.c hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >>
hw 6094 dev/pci/if_em_hw.c hw->bus_type = em_bus_type_pci_express;
hw 6095 dev/pci/if_em_hw.c hw->bus_speed = em_bus_speed_2500;
hw 6096 dev/pci/if_em_hw.c hw->bus_width = em_bus_width_pciex_1;
hw 6099 dev/pci/if_em_hw.c status = E1000_READ_REG(hw, STATUS);
hw 6100 dev/pci/if_em_hw.c hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
hw 6103 dev/pci/if_em_hw.c if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
hw 6104 dev/pci/if_em_hw.c hw->bus_speed = (hw->bus_type == em_bus_type_pci) ?
hw 6106 dev/pci/if_em_hw.c } else if (hw->bus_type == em_bus_type_pci) {
hw 6107 dev/pci/if_em_hw.c hw->bus_speed = (status & E1000_STATUS_PCI66) ?
hw 6112 dev/pci/if_em_hw.c hw->bus_speed = em_bus_speed_66;
hw 6115 dev/pci/if_em_hw.c hw->bus_speed = em_bus_speed_100;
hw 6118 dev/pci/if_em_hw.c hw->bus_speed = em_bus_speed_133;
hw 6121 dev/pci/if_em_hw.c hw->bus_speed = em_bus_speed_reserved;
hw 6125 dev/pci/if_em_hw.c hw->bus_width = (status & E1000_STATUS_BUS64) ?
hw 6140 dev/pci/if_em_hw.c em_write_reg_io(struct em_hw *hw,
hw 6144 dev/pci/if_em_hw.c unsigned long io_addr = hw->io_base;
hw 6145 dev/pci/if_em_hw.c unsigned long io_data = hw->io_base + 4;
hw 6147 dev/pci/if_em_hw.c em_io_write(hw, io_addr, offset);
hw 6148 dev/pci/if_em_hw.c em_io_write(hw, io_data, value);
hw 6167 dev/pci/if_em_hw.c em_get_cable_length(struct em_hw *hw,
hw 6181 dev/pci/if_em_hw.c if (hw->phy_type == em_phy_m88) {
hw 6183 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
hw 6216 dev/pci/if_em_hw.c } else if (hw->phy_type == em_phy_gg82563) {
hw 6217 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
hw 6244 dev/pci/if_em_hw.c } else if (hw->phy_type == em_phy_igp) { /* For IGP PHY */
hw 6255 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, agc_reg_array[i], &phy_data);
hw 6291 dev/pci/if_em_hw.c } else if (hw->phy_type == em_phy_igp_2 ||
hw 6292 dev/pci/if_em_hw.c hw->phy_type == em_phy_igp_3) {
hw 6302 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, agc_reg_array[i], &phy_data);
hw 6357 dev/pci/if_em_hw.c em_check_downshift(struct em_hw *hw)
hw 6364 dev/pci/if_em_hw.c if (hw->phy_type == em_phy_igp ||
hw 6365 dev/pci/if_em_hw.c hw->phy_type == em_phy_igp_3 ||
hw 6366 dev/pci/if_em_hw.c hw->phy_type == em_phy_igp_2) {
hw 6367 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
hw 6372 dev/pci/if_em_hw.c hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
hw 6373 dev/pci/if_em_hw.c } else if ((hw->phy_type == em_phy_m88) ||
hw 6374 dev/pci/if_em_hw.c (hw->phy_type == em_phy_gg82563)) {
hw 6375 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
hw 6380 dev/pci/if_em_hw.c hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
hw 6382 dev/pci/if_em_hw.c } else if (hw->phy_type == em_phy_ife) {
hw 6384 dev/pci/if_em_hw.c hw->speed_downgraded = FALSE;
hw 6403 dev/pci/if_em_hw.c em_config_dsp_after_link_change(struct em_hw *hw,
hw 6417 dev/pci/if_em_hw.c if (hw->phy_type != em_phy_igp)
hw 6421 dev/pci/if_em_hw.c ret_val = em_get_speed_and_duplex(hw, &speed, &duplex);
hw 6429 dev/pci/if_em_hw.c ret_val = em_get_cable_length(hw, &min_length, &max_length);
hw 6433 dev/pci/if_em_hw.c if ((hw->dsp_config_state == em_dsp_config_enabled) &&
hw 6437 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, dsp_reg_array[i],
hw 6444 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, dsp_reg_array[i],
hw 6449 dev/pci/if_em_hw.c hw->dsp_config_state = em_dsp_config_activated;
hw 6452 dev/pci/if_em_hw.c if ((hw->ffe_config_state == em_ffe_config_enabled) &&
hw 6459 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS,
hw 6466 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS,
hw 6473 dev/pci/if_em_hw.c hw->ffe_config_state = em_ffe_config_active;
hw 6475 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw,
hw 6489 dev/pci/if_em_hw.c if (hw->dsp_config_state == em_dsp_config_activated) {
hw 6492 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
hw 6498 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003);
hw 6505 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, 0x0000,
hw 6510 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
hw 6517 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw,dsp_reg_array[i], phy_data);
hw 6522 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, 0x0000,
hw 6530 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data);
hw 6535 dev/pci/if_em_hw.c hw->dsp_config_state = em_dsp_config_enabled;
hw 6538 dev/pci/if_em_hw.c if (hw->ffe_config_state == em_ffe_config_active) {
hw 6541 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
hw 6547 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003);
hw 6554 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, 0x0000,
hw 6558 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
hw 6563 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, 0x0000,
hw 6571 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data);
hw 6576 dev/pci/if_em_hw.c hw->ffe_config_state = em_ffe_config_enabled;
hw 6591 dev/pci/if_em_hw.c em_set_phy_mode(struct em_hw *hw)
hw 6598 dev/pci/if_em_hw.c if ((hw->mac_type == em_82545_rev_3) &&
hw 6599 dev/pci/if_em_hw.c (hw->media_type == em_media_type_copper)) {
hw 6600 dev/pci/if_em_hw.c ret_val = em_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
hw 6607 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
hw 6610 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
hw 6614 dev/pci/if_em_hw.c hw->phy_reset_disable = FALSE;
hw 6636 dev/pci/if_em_hw.c em_set_d3_lplu_state(struct em_hw *hw,
hw 6644 dev/pci/if_em_hw.c if (hw->phy_type != em_phy_igp && hw->phy_type != em_phy_igp_2
hw 6645 dev/pci/if_em_hw.c && hw->phy_type != em_phy_igp_3)
hw 6651 dev/pci/if_em_hw.c if (hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) {
hw 6652 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
hw 6655 dev/pci/if_em_hw.c } else if (hw->mac_type == em_ich8lan) {
hw 6659 dev/pci/if_em_hw.c phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
hw 6661 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
hw 6667 dev/pci/if_em_hw.c if (hw->mac_type == em_82541_rev_2 ||
hw 6668 dev/pci/if_em_hw.c hw->mac_type == em_82547_rev_2) {
hw 6670 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
hw 6674 dev/pci/if_em_hw.c if (hw->mac_type == em_ich8lan) {
hw 6676 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
hw 6679 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
hw 6690 dev/pci/if_em_hw.c if (hw->smart_speed == em_smart_speed_on) {
hw 6691 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
hw 6697 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
hw 6701 dev/pci/if_em_hw.c } else if (hw->smart_speed == em_smart_speed_off) {
hw 6702 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
hw 6708 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
hw 6714 dev/pci/if_em_hw.c } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
hw 6715 dev/pci/if_em_hw.c (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
hw 6716 dev/pci/if_em_hw.c (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
hw 6718 dev/pci/if_em_hw.c if (hw->mac_type == em_82541_rev_2 ||
hw 6719 dev/pci/if_em_hw.c hw->mac_type == em_82547_rev_2) {
hw 6721 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
hw 6725 dev/pci/if_em_hw.c if (hw->mac_type == em_ich8lan) {
hw 6727 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
hw 6730 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
hw 6738 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
hw 6743 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
hw 6766 dev/pci/if_em_hw.c em_set_d0_lplu_state(struct em_hw *hw,
hw 6774 dev/pci/if_em_hw.c if (hw->mac_type <= em_82547_rev_2)
hw 6777 dev/pci/if_em_hw.c if (hw->mac_type == em_ich8lan) {
hw 6778 dev/pci/if_em_hw.c phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
hw 6780 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
hw 6786 dev/pci/if_em_hw.c if (hw->mac_type == em_ich8lan) {
hw 6788 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
hw 6791 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
hw 6800 dev/pci/if_em_hw.c if (hw->smart_speed == em_smart_speed_on) {
hw 6801 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
hw 6807 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
hw 6811 dev/pci/if_em_hw.c } else if (hw->smart_speed == em_smart_speed_off) {
hw 6812 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
hw 6818 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
hw 6827 dev/pci/if_em_hw.c if (hw->mac_type == em_ich8lan) {
hw 6829 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
hw 6832 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
hw 6838 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
hw 6843 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
hw 6857 dev/pci/if_em_hw.c em_set_vco_speed(struct em_hw *hw)
hw 6865 dev/pci/if_em_hw.c switch (hw->mac_type) {
hw 6875 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
hw 6879 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
hw 6883 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
hw 6888 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
hw 6894 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
hw 6898 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
hw 6903 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
hw 6907 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
hw 6921 dev/pci/if_em_hw.c em_host_if_read_cookie(struct em_hw * hw, uint8_t *buffer)
hw 6932 dev/pci/if_em_hw.c E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
hw 6948 dev/pci/if_em_hw.c em_mng_enable_host_if(struct em_hw * hw)
hw 6954 dev/pci/if_em_hw.c hicr = E1000_READ_REG(hw, HICR);
hw 6961 dev/pci/if_em_hw.c hicr = E1000_READ_REG(hw, HICR);
hw 6980 dev/pci/if_em_hw.c em_check_mng_mode(struct em_hw *hw)
hw 6984 dev/pci/if_em_hw.c fwsm = E1000_READ_REG(hw, FWSM);
hw 6986 dev/pci/if_em_hw.c if (hw->mac_type == em_ich8lan) {
hw 7023 dev/pci/if_em_hw.c em_enable_tx_pkt_filtering(struct em_hw *hw)
hw 7029 dev/pci/if_em_hw.c struct em_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
hw 7030 dev/pci/if_em_hw.c uint8_t *buffer = (uint8_t *) &(hw->mng_cookie);
hw 7032 dev/pci/if_em_hw.c if (em_check_mng_mode(hw)) {
hw 7033 dev/pci/if_em_hw.c ret_val = em_mng_enable_host_if(hw);
hw 7035 dev/pci/if_em_hw.c ret_val = em_host_if_read_cookie(hw, buffer);
hw 7052 dev/pci/if_em_hw.c hw->tx_pkt_filtering = tx_filter;
hw 7058 dev/pci/if_em_hw.c em_polarity_reversal_workaround(struct em_hw *hw)
hw 7068 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
hw 7071 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
hw 7075 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
hw 7085 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
hw 7089 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
hw 7102 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
hw 7106 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
hw 7110 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
hw 7114 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
hw 7118 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
hw 7128 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
hw 7132 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
hw 7152 dev/pci/if_em_hw.c em_set_pci_express_master_disable(struct em_hw *hw)
hw 7158 dev/pci/if_em_hw.c if (hw->bus_type != em_bus_type_pci_express)
hw 7161 dev/pci/if_em_hw.c ctrl = E1000_READ_REG(hw, CTRL);
hw 7163 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, ctrl);
hw 7178 dev/pci/if_em_hw.c em_disable_pciex_master(struct em_hw *hw)
hw 7184 dev/pci/if_em_hw.c if (hw->bus_type != em_bus_type_pci_express)
hw 7187 dev/pci/if_em_hw.c em_set_pci_express_master_disable(hw);
hw 7190 dev/pci/if_em_hw.c if (!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
hw 7216 dev/pci/if_em_hw.c em_get_auto_rd_done(struct em_hw *hw)
hw 7222 dev/pci/if_em_hw.c switch (hw->mac_type) {
hw 7232 dev/pci/if_em_hw.c if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
hw 7248 dev/pci/if_em_hw.c if (hw->mac_type == em_82573)
hw 7264 dev/pci/if_em_hw.c em_get_phy_cfg_done(struct em_hw *hw)
hw 7271 dev/pci/if_em_hw.c switch (hw->mac_type) {
hw 7277 dev/pci/if_em_hw.c if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
hw 7283 dev/pci/if_em_hw.c if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
hw 7311 dev/pci/if_em_hw.c em_get_hw_eeprom_semaphore(struct em_hw *hw)
hw 7318 dev/pci/if_em_hw.c if (!hw->eeprom_semaphore_present)
hw 7321 dev/pci/if_em_hw.c if (hw->mac_type == em_80003es2lan) {
hw 7323 dev/pci/if_em_hw.c if (em_get_software_semaphore(hw) != E1000_SUCCESS)
hw 7328 dev/pci/if_em_hw.c timeout = hw->eeprom.word_size + 1;
hw 7330 dev/pci/if_em_hw.c swsm = E1000_READ_REG(hw, SWSM);
hw 7332 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, SWSM, swsm);
hw 7334 dev/pci/if_em_hw.c swsm = E1000_READ_REG(hw, SWSM);
hw 7344 dev/pci/if_em_hw.c em_put_hw_eeprom_semaphore(hw);
hw 7361 dev/pci/if_em_hw.c em_put_hw_eeprom_semaphore(struct em_hw *hw)
hw 7367 dev/pci/if_em_hw.c if (!hw->eeprom_semaphore_present)
hw 7370 dev/pci/if_em_hw.c swsm = E1000_READ_REG(hw, SWSM);
hw 7371 dev/pci/if_em_hw.c if (hw->mac_type == em_80003es2lan) {
hw 7376 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, SWSM, swsm);
hw 7390 dev/pci/if_em_hw.c em_get_software_semaphore(struct em_hw *hw)
hw 7392 dev/pci/if_em_hw.c int32_t timeout = hw->eeprom.word_size + 1;
hw 7397 dev/pci/if_em_hw.c if (hw->mac_type != em_80003es2lan)
hw 7401 dev/pci/if_em_hw.c swsm = E1000_READ_REG(hw, SWSM);
hw 7425 dev/pci/if_em_hw.c em_release_software_semaphore(struct em_hw *hw)
hw 7431 dev/pci/if_em_hw.c if (hw->mac_type != em_80003es2lan)
hw 7434 dev/pci/if_em_hw.c swsm = E1000_READ_REG(hw, SWSM);
hw 7437 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, SWSM, swsm);
hw 7452 dev/pci/if_em_hw.c em_check_phy_reset_block(struct em_hw *hw)
hw 7457 dev/pci/if_em_hw.c if (hw->mac_type == em_ich8lan) {
hw 7458 dev/pci/if_em_hw.c fwsm = E1000_READ_REG(hw, FWSM);
hw 7463 dev/pci/if_em_hw.c if (hw->mac_type > em_82547_rev_2)
hw 7464 dev/pci/if_em_hw.c manc = E1000_READ_REG(hw, MANC);
hw 7479 dev/pci/if_em_hw.c em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop)
hw 7485 dev/pci/if_em_hw.c if (hw->bus_type == em_bus_type_unknown)
hw 7486 dev/pci/if_em_hw.c em_get_bus_info(hw);
hw 7488 dev/pci/if_em_hw.c if (hw->bus_type != em_bus_type_pci_express)
hw 7492 dev/pci/if_em_hw.c gcr_reg = E1000_READ_REG(hw, GCR);
hw 7495 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, GCR, gcr_reg);
hw 7497 dev/pci/if_em_hw.c if (hw->mac_type == em_ich8lan) {
hw 7500 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL);
hw 7502 dev/pci/if_em_hw.c ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
hw 7504 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
hw 7520 dev/pci/if_em_hw.c em_get_software_flag(struct em_hw *hw)
hw 7527 dev/pci/if_em_hw.c if (hw->mac_type == em_ich8lan) {
hw 7529 dev/pci/if_em_hw.c extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
hw 7531 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
hw 7533 dev/pci/if_em_hw.c extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
hw 7559 dev/pci/if_em_hw.c em_release_software_flag(struct em_hw *hw)
hw 7565 dev/pci/if_em_hw.c if (hw->mac_type == em_ich8lan) {
hw 7566 dev/pci/if_em_hw.c extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL);
hw 7568 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
hw 7585 dev/pci/if_em_hw.c em_read_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words,
hw 7601 dev/pci/if_em_hw.c flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
hw 7604 dev/pci/if_em_hw.c bank_offset = flash_bank * (hw->flash_bank_size * 2);
hw 7606 dev/pci/if_em_hw.c error = em_get_software_flag(hw);
hw 7611 dev/pci/if_em_hw.c if (hw->eeprom_shadow_ram != NULL &&
hw 7612 dev/pci/if_em_hw.c hw->eeprom_shadow_ram[offset+i].modified == TRUE) {
hw 7613 dev/pci/if_em_hw.c data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
hw 7617 dev/pci/if_em_hw.c error = em_read_ich8_word(hw, act_offset, &word);
hw 7624 dev/pci/if_em_hw.c em_release_software_flag(hw);
hw 7641 dev/pci/if_em_hw.c em_write_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words,
hw 7647 dev/pci/if_em_hw.c error = em_get_software_flag(hw);
hw 7658 dev/pci/if_em_hw.c if (hw->eeprom_shadow_ram != NULL) {
hw 7661 dev/pci/if_em_hw.c hw->eeprom_shadow_ram[offset+i].modified = TRUE;
hw 7662 dev/pci/if_em_hw.c hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i];
hw 7676 dev/pci/if_em_hw.c em_release_software_flag(hw);
hw 7688 dev/pci/if_em_hw.c em_ich8_cycle_init(struct em_hw *hw)
hw 7696 dev/pci/if_em_hw.c hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
hw 7709 dev/pci/if_em_hw.c E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
hw 7724 dev/pci/if_em_hw.c E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
hw 7730 dev/pci/if_em_hw.c hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
hw 7741 dev/pci/if_em_hw.c E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
hw 7755 dev/pci/if_em_hw.c em_ich8_flash_cycle(struct em_hw *hw, uint32_t timeout)
hw 7763 dev/pci/if_em_hw.c hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
hw 7765 dev/pci/if_em_hw.c E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
hw 7769 dev/pci/if_em_hw.c hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
hw 7790 dev/pci/if_em_hw.c em_read_ich8_data(struct em_hw *hw, uint32_t index,
hw 7807 dev/pci/if_em_hw.c hw->flash_base_addr;
hw 7812 dev/pci/if_em_hw.c error = em_ich8_cycle_init(hw);
hw 7816 dev/pci/if_em_hw.c hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
hw 7820 dev/pci/if_em_hw.c E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
hw 7826 dev/pci/if_em_hw.c E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
hw 7828 dev/pci/if_em_hw.c error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
hw 7834 dev/pci/if_em_hw.c flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0);
hw 7846 dev/pci/if_em_hw.c hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
hw 7869 dev/pci/if_em_hw.c em_write_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size,
hw 7886 dev/pci/if_em_hw.c hw->flash_base_addr;
hw 7891 dev/pci/if_em_hw.c error = em_ich8_cycle_init(hw);
hw 7895 dev/pci/if_em_hw.c hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
hw 7899 dev/pci/if_em_hw.c E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
hw 7903 dev/pci/if_em_hw.c E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
hw 7910 dev/pci/if_em_hw.c E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
hw 7914 dev/pci/if_em_hw.c error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
hw 7922 dev/pci/if_em_hw.c hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
hw 7944 dev/pci/if_em_hw.c em_read_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t* data)
hw 7949 dev/pci/if_em_hw.c status = em_read_ich8_data(hw, index, 1, &word);
hw 7967 dev/pci/if_em_hw.c em_verify_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t byte)
hw 7974 dev/pci/if_em_hw.c error = em_write_ich8_byte(hw, index, byte);
hw 7979 dev/pci/if_em_hw.c error = em_write_ich8_byte(hw, index, byte);
hw 8000 dev/pci/if_em_hw.c em_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t data)
hw 8005 dev/pci/if_em_hw.c status = em_write_ich8_data(hw, index, 1, word);
hw 8018 dev/pci/if_em_hw.c em_read_ich8_word(struct em_hw *hw, uint32_t index, uint16_t *data)
hw 8021 dev/pci/if_em_hw.c status = em_read_ich8_data(hw, index, 2, data);
hw 8038 dev/pci/if_em_hw.c em_erase_ich8_4k_segment(struct em_hw *hw, uint32_t bank)
hw 8051 dev/pci/if_em_hw.c hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
hw 8081 dev/pci/if_em_hw.c error = em_ich8_cycle_init(hw);
hw 8089 dev/pci/if_em_hw.c hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
hw 8091 dev/pci/if_em_hw.c E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
hw 8098 dev/pci/if_em_hw.c flash_linear_address += hw->flash_base_addr;
hw 8101 dev/pci/if_em_hw.c E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
hw 8103 dev/pci/if_em_hw.c error = em_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT);
hw 8109 dev/pci/if_em_hw.c hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
hw 8129 dev/pci/if_em_hw.c em_init_lcd_from_nvm_config_region(struct em_hw *hw,
hw 8141 dev/pci/if_em_hw.c ret_val = em_read_eeprom(hw, (word_addr + i*2), 1, ®_data);
hw 8145 dev/pci/if_em_hw.c ret_val = em_read_eeprom(hw, (word_addr + i*2 + 1), 1, ®_addr);
hw 8149 dev/pci/if_em_hw.c ret_val = em_get_software_flag(hw);
hw 8153 dev/pci/if_em_hw.c ret_val = em_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data);
hw 8155 dev/pci/if_em_hw.c em_release_software_flag(hw);
hw 8170 dev/pci/if_em_hw.c em_init_lcd_from_nvm(struct em_hw *hw)
hw 8174 dev/pci/if_em_hw.c if (hw->phy_type != em_phy_igp_3)
hw 8178 dev/pci/if_em_hw.c reg_data = E1000_READ_REG(hw, FEXTNVM);
hw 8185 dev/pci/if_em_hw.c reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE;
hw 8191 dev/pci/if_em_hw.c reg_data = E1000_READ_REG(hw, STATUS);
hw 8193 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, STATUS, reg_data);
hw 8197 dev/pci/if_em_hw.c reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
hw 8199 dev/pci/if_em_hw.c reg_data = E1000_READ_REG(hw, EXTCNF_SIZE);
hw 8203 dev/pci/if_em_hw.c reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
hw 8209 dev/pci/if_em_hw.c ret_val = em_init_lcd_from_nvm_config_region(hw, cnf_base_addr,
hw 307 dev/pci/if_em_hw.h int32_t em_reset_hw(struct em_hw *hw);
hw 308 dev/pci/if_em_hw.h int32_t em_init_hw(struct em_hw *hw);
hw 309 dev/pci/if_em_hw.h int32_t em_set_mac_type(struct em_hw *hw);
hw 310 dev/pci/if_em_hw.h void em_set_media_type(struct em_hw *hw);
hw 313 dev/pci/if_em_hw.h int32_t em_setup_link(struct em_hw *hw);
hw 314 dev/pci/if_em_hw.h int32_t em_phy_setup_autoneg(struct em_hw *hw);
hw 315 dev/pci/if_em_hw.h void em_config_collision_dist(struct em_hw *hw);
hw 316 dev/pci/if_em_hw.h int32_t em_check_for_link(struct em_hw *hw);
hw 317 dev/pci/if_em_hw.h int32_t em_get_speed_and_duplex(struct em_hw *hw, uint16_t *speed, uint16_t *duplex);
hw 318 dev/pci/if_em_hw.h int32_t em_force_mac_fc(struct em_hw *hw);
hw 321 dev/pci/if_em_hw.h int32_t em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
hw 322 dev/pci/if_em_hw.h int32_t em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data);
hw 323 dev/pci/if_em_hw.h int32_t em_phy_hw_reset(struct em_hw *hw);
hw 324 dev/pci/if_em_hw.h int32_t em_phy_reset(struct em_hw *hw);
hw 325 dev/pci/if_em_hw.h int32_t em_phy_get_info(struct em_hw *hw, struct em_phy_info *phy_info);
hw 326 dev/pci/if_em_hw.h int32_t em_validate_mdi_setting(struct em_hw *hw);
hw 327 dev/pci/if_em_hw.h void em_phy_powerdown_workaround(struct em_hw *hw);
hw 330 dev/pci/if_em_hw.h int32_t em_init_eeprom_params(struct em_hw *hw);
hw 333 dev/pci/if_em_hw.h uint32_t em_enable_mng_pass_thru(struct em_hw *hw);
hw 374 dev/pci/if_em_hw.h int32_t em_read_part_num(struct em_hw *hw, uint32_t *part_num);
hw 375 dev/pci/if_em_hw.h int32_t em_mng_write_dhcp_info(struct em_hw *hw, uint8_t *buffer,
hw 377 dev/pci/if_em_hw.h boolean_t em_check_mng_mode(struct em_hw *hw);
hw 378 dev/pci/if_em_hw.h boolean_t em_enable_tx_pkt_filtering(struct em_hw *hw);
hw 379 dev/pci/if_em_hw.h int32_t em_read_eeprom(struct em_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
hw 380 dev/pci/if_em_hw.h int32_t em_validate_eeprom_checksum(struct em_hw *hw);
hw 381 dev/pci/if_em_hw.h int32_t em_update_eeprom_checksum(struct em_hw *hw);
hw 382 dev/pci/if_em_hw.h int32_t em_write_eeprom(struct em_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
hw 383 dev/pci/if_em_hw.h int32_t em_read_mac_addr(struct em_hw * hw);
hw 386 dev/pci/if_em_hw.h void em_mc_addr_list_update(struct em_hw *hw, uint8_t * mc_addr_list, uint32_t mc_addr_count,
hw 388 dev/pci/if_em_hw.h uint32_t em_hash_mc_addr(struct em_hw *hw, uint8_t *mc_addr);
hw 389 dev/pci/if_em_hw.h void em_mta_set(struct em_hw *hw, uint32_t hash_value);
hw 390 dev/pci/if_em_hw.h void em_rar_set(struct em_hw *hw, uint8_t *mc_addr, uint32_t rar_index);
hw 391 dev/pci/if_em_hw.h void em_write_vfta(struct em_hw *hw, uint32_t offset, uint32_t value);
hw 394 dev/pci/if_em_hw.h int32_t em_setup_led(struct em_hw *hw);
hw 395 dev/pci/if_em_hw.h int32_t em_cleanup_led(struct em_hw *hw);
hw 396 dev/pci/if_em_hw.h int32_t em_led_on(struct em_hw *hw);
hw 397 dev/pci/if_em_hw.h int32_t em_led_off(struct em_hw *hw);
hw 398 dev/pci/if_em_hw.h int32_t em_blink_led_start(struct em_hw *hw);
hw 403 dev/pci/if_em_hw.h void em_clear_hw_cntrs(struct em_hw *hw);
hw 404 dev/pci/if_em_hw.h void em_reset_adaptive(struct em_hw *hw);
hw 405 dev/pci/if_em_hw.h void em_update_adaptive(struct em_hw *hw);
hw 406 dev/pci/if_em_hw.h void em_tbi_adjust_stats(struct em_hw *hw, struct em_hw_stats *stats, uint32_t frame_len, uint8_t *mac_addr);
hw 407 dev/pci/if_em_hw.h void em_get_bus_info(struct em_hw *hw);
hw 408 dev/pci/if_em_hw.h void em_pci_set_mwi(struct em_hw *hw);
hw 409 dev/pci/if_em_hw.h void em_pci_clear_mwi(struct em_hw *hw);
hw 410 dev/pci/if_em_hw.h void em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value);
hw 411 dev/pci/if_em_hw.h void em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value);
hw 412 dev/pci/if_em_hw.h int32_t em_read_pcie_cap_reg(struct em_hw *hw, uint32_t reg, uint16_t *value);
hw 414 dev/pci/if_em_hw.h int32_t em_disable_pciex_master(struct em_hw *hw);
hw 415 dev/pci/if_em_hw.h int32_t em_check_phy_reset_block(struct em_hw *hw);
hw 84 dev/pci/if_em_osdep.h #define E1000_WRITE_FLUSH(hw) E1000_READ_REG(hw, STATUS)
hw 87 dev/pci/if_em_osdep.h #define E1000_READ_OFFSET(hw, offset) \
hw 88 dev/pci/if_em_osdep.h bus_space_read_4(((struct em_osdep *)(hw)->back)->mem_bus_space_tag, \
hw 89 dev/pci/if_em_osdep.h ((struct em_osdep *)(hw)->back)->mem_bus_space_handle, \
hw 93 dev/pci/if_em_osdep.h #define E1000_WRITE_OFFSET(hw, offset, value) \
hw 94 dev/pci/if_em_osdep.h bus_space_write_4(((struct em_osdep *)(hw)->back)->mem_bus_space_tag, \
hw 95 dev/pci/if_em_osdep.h ((struct em_osdep *)(hw)->back)->mem_bus_space_handle, \
hw 99 dev/pci/if_em_osdep.h #define E1000_REG_OFFSET(hw, reg) \
hw 100 dev/pci/if_em_osdep.h ((hw)->mac_type >= em_82543 ? E1000_##reg : E1000_82542_##reg)
hw 104 dev/pci/if_em_osdep.h #define E1000_READ_REG(hw, reg) \
hw 105 dev/pci/if_em_osdep.h bus_space_read_4(((struct em_osdep *)(hw)->back)->mem_bus_space_tag, \
hw 106 dev/pci/if_em_osdep.h ((struct em_osdep *)(hw)->back)->mem_bus_space_handle, \
hw 107 dev/pci/if_em_osdep.h ((hw)->mac_type >= em_82543 ? E1000_##reg : E1000_82542_##reg))
hw 109 dev/pci/if_em_osdep.h #define E1000_WRITE_REG(hw, reg, value) \
hw 110 dev/pci/if_em_osdep.h bus_space_write_4(((struct em_osdep *)(hw)->back)->mem_bus_space_tag, \
hw 111 dev/pci/if_em_osdep.h ((struct em_osdep *)(hw)->back)->mem_bus_space_handle, \
hw 112 dev/pci/if_em_osdep.h ((hw)->mac_type >= em_82543 ? E1000_##reg : E1000_82542_##reg), \
hw 115 dev/pci/if_em_osdep.h #define E1000_READ_REG_ARRAY(hw, reg, index) \
hw 116 dev/pci/if_em_osdep.h bus_space_read_4(((struct em_osdep *)(hw)->back)->mem_bus_space_tag, \
hw 117 dev/pci/if_em_osdep.h ((struct em_osdep *)(hw)->back)->mem_bus_space_handle, \
hw 118 dev/pci/if_em_osdep.h ((hw)->mac_type >= em_82543 ? E1000_##reg : E1000_82542_##reg) \
hw 121 dev/pci/if_em_osdep.h #define E1000_WRITE_REG_ARRAY(hw, reg, index, value) \
hw 122 dev/pci/if_em_osdep.h bus_space_write_4(((struct em_osdep *)(hw)->back)->mem_bus_space_tag, \
hw 123 dev/pci/if_em_osdep.h ((struct em_osdep *)(hw)->back)->mem_bus_space_handle, \
hw 124 dev/pci/if_em_osdep.h ((hw)->mac_type >= em_82543 ? E1000_##reg : E1000_82542_##reg) \
hw 130 dev/pci/if_em_osdep.h #define E1000_WRITE_REG_ARRAY_BYTE(hw, reg, index, value) \
hw 131 dev/pci/if_em_osdep.h bus_space_write_1(((struct em_osdep *)(hw)->back)->mem_bus_space_tag, \
hw 132 dev/pci/if_em_osdep.h ((struct em_osdep *)(hw)->back)->mem_bus_space_handle, \
hw 133 dev/pci/if_em_osdep.h ((hw)->mac_type >= em_82543 ? E1000_##reg : E1000_82542_##reg \
hw 136 dev/pci/if_em_osdep.h #define E1000_WRITE_REG_ARRAY_WORD(hw, reg, index, value) \
hw 137 dev/pci/if_em_osdep.h bus_space_write_2(((struct em_osdep *)(hw)->back)->mem_bus_space_tag, \
hw 138 dev/pci/if_em_osdep.h ((struct em_osdep *)(hw)->back)->mem_bus_space_handle, \
hw 139 dev/pci/if_em_osdep.h ((hw)->mac_type >= em_82543 ? E1000_##reg : E1000_82542_##reg \
hw 142 dev/pci/if_em_osdep.h #define E1000_READ_ICH_FLASH_REG(hw, reg) \
hw 143 dev/pci/if_em_osdep.h bus_space_read_4(((struct em_osdep *)(hw)->back)->flash_bus_space_tag, \
hw 144 dev/pci/if_em_osdep.h ((struct em_osdep *)(hw)->back)->flash_bus_space_handle, reg)
hw 146 dev/pci/if_em_osdep.h #define E1000_READ_ICH_FLASH_REG16(hw, reg) \
hw 147 dev/pci/if_em_osdep.h bus_space_read_2(((struct em_osdep *)(hw)->back)->flash_bus_space_tag, \
hw 148 dev/pci/if_em_osdep.h ((struct em_osdep *)(hw)->back)->flash_bus_space_handle, reg)
hw 150 dev/pci/if_em_osdep.h #define E1000_WRITE_ICH_FLASH_REG(hw, reg, value) \
hw 151 dev/pci/if_em_osdep.h bus_space_write_4(((struct em_osdep *)(hw)->back)->flash_bus_space_tag, \
hw 152 dev/pci/if_em_osdep.h ((struct em_osdep *)(hw)->back)->flash_bus_space_handle, \
hw 155 dev/pci/if_em_osdep.h #define E1000_WRITE_ICH_FLASH_REG16(hw, reg, value) \
hw 156 dev/pci/if_em_osdep.h bus_space_write_2(((struct em_osdep *)(hw)->back)->flash_bus_space_tag, \
hw 157 dev/pci/if_em_osdep.h ((struct em_osdep *)(hw)->back)->flash_bus_space_handle, \
hw 160 dev/pci/if_em_osdep.h #define em_io_read(hw, port) \
hw 161 dev/pci/if_em_osdep.h bus_space_read_4(((struct em_osdep *)(hw)->back)->io_bus_space_tag, \
hw 162 dev/pci/if_em_osdep.h ((struct em_osdep *)(hw)->back)->io_bus_space_handle, (port))
hw 164 dev/pci/if_em_osdep.h #define em_io_write(hw, port, value) \
hw 165 dev/pci/if_em_osdep.h bus_space_write_4(((struct em_osdep *)(hw)->back)->io_bus_space_tag, \
hw 166 dev/pci/if_em_osdep.h ((struct em_osdep *)(hw)->back)->io_bus_space_handle, \
hw 1097 dev/pci/if_iwi.c uint32_t hw;
hw 1099 dev/pci/if_iwi.c hw = CSR_READ_4(sc, IWI_CSR_RX_RIDX);
hw 1101 dev/pci/if_iwi.c for (; sc->rxq.cur != hw;) {
hw 1129 dev/pci/if_iwi.c hw = (hw == 0) ? IWI_RX_RING_COUNT - 1 : hw - 1;
hw 1130 dev/pci/if_iwi.c CSR_WRITE_4(sc, IWI_CSR_RX_WIDX, hw);
hw 1139 dev/pci/if_iwi.c uint32_t hw;
hw 1141 dev/pci/if_iwi.c hw = CSR_READ_4(sc, txq->csr_ridx);
hw 1143 dev/pci/if_iwi.c for (; txq->next != hw;) {
hw 190 dev/pci/if_ixgb.c sc->hw.fc.high_water = FCRTH;
hw 191 dev/pci/if_ixgb.c sc->hw.fc.low_water = FCRTL;
hw 192 dev/pci/if_ixgb.c sc->hw.fc.pause_time = FCPAUSE;
hw 193 dev/pci/if_ixgb.c sc->hw.fc.send_xon = TRUE;
hw 194 dev/pci/if_ixgb.c sc->hw.fc.type = FLOW_CONTROL;
hw 197 dev/pci/if_ixgb.c sc->hw.max_frame_size = IXGB_MAX_JUMBO_FRAME_SIZE;
hw 240 dev/pci/if_ixgb.c ixgb_clear_hw_cntrs(&sc->hw);
hw 444 dev/pci/if_ixgb.c if (IXGB_READ_REG(&sc->hw, STATUS) & IXGB_STATUS_TXOFF) {
hw 481 dev/pci/if_ixgb.c bcopy(sc->interface_data.ac_enaddr, sc->hw.curr_mac_addr,
hw 522 dev/pci/if_ixgb.c IXGB_WRITE_REG(&sc->hw, MFRMS,
hw 523 dev/pci/if_ixgb.c sc->hw.max_frame_size << IXGB_MFRMS_SHIFT);
hw 524 dev/pci/if_ixgb.c temp_reg = IXGB_READ_REG(&sc->hw, CTRL0);
hw 526 dev/pci/if_ixgb.c IXGB_WRITE_REG(&sc->hw, CTRL0, temp_reg);
hw 529 dev/pci/if_ixgb.c ixgb_clear_hw_cntrs(&sc->hw);
hw 553 dev/pci/if_ixgb.c reg_icr = IXGB_READ_REG(&sc->hw, ICR);
hw 570 dev/pci/if_ixgb.c ixgb_check_for_link(&sc->hw);
hw 576 dev/pci/if_ixgb.c IXGB_WRITE_REG(&sc->hw, IMC, IXGB_INT_RXDMT0);
hw 577 dev/pci/if_ixgb.c IXGB_WRITE_REG(&sc->hw, IMS, IXGB_INT_RXDMT0);
hw 603 dev/pci/if_ixgb.c ixgb_check_for_link(&sc->hw);
hw 609 dev/pci/if_ixgb.c if (!sc->hw.link_up) {
hw 615 dev/pci/if_ixgb.c if ((sc->hw.phy_type == ixgb_phy_type_g6104) ||
hw 616 dev/pci/if_ixgb.c (sc->hw.phy_type == ixgb_phy_type_txn17401))
hw 732 dev/pci/if_ixgb.c IXGB_WRITE_REG(&sc->hw, TDT, i);
hw 749 dev/pci/if_ixgb.c reg_rctl = IXGB_READ_REG(&sc->hw, RCTL);
hw 759 dev/pci/if_ixgb.c IXGB_WRITE_REG(&sc->hw, RCTL, reg_rctl);
hw 797 dev/pci/if_ixgb.c reg_rctl = IXGB_READ_REG(&sc->hw, RCTL);
hw 799 dev/pci/if_ixgb.c IXGB_WRITE_REG(&sc->hw, RCTL, reg_rctl);
hw 801 dev/pci/if_ixgb.c ixgb_mc_addr_list_update(&sc->hw, mta, mcnt, 0);
hw 823 dev/pci/if_ixgb.c ixgb_check_for_link(&sc->hw);
hw 839 dev/pci/if_ixgb.c if (sc->hw.link_up) {
hw 872 dev/pci/if_ixgb.c sc->hw.adapter_stopped = FALSE;
hw 873 dev/pci/if_ixgb.c ixgb_adapter_stop(&sc->hw);
hw 896 dev/pci/if_ixgb.c sc->hw.pci_cmd_word = pci_conf_read(pa->pa_pc, pa->pa_tag,
hw 900 dev/pci/if_ixgb.c sc->hw.vendor_id = PCI_VENDOR(pa->pa_id);
hw 901 dev/pci/if_ixgb.c sc->hw.device_id = PCI_PRODUCT(pa->pa_id);
hw 904 dev/pci/if_ixgb.c sc->hw.revision_id = PCI_REVISION(reg);
hw 907 dev/pci/if_ixgb.c sc->hw.subsystem_vendor_id = PCI_VENDOR(reg);
hw 908 dev/pci/if_ixgb.c sc->hw.subsystem_id = PCI_PRODUCT(reg);
hw 911 dev/pci/if_ixgb.c switch (sc->hw.device_id) {
hw 916 dev/pci/if_ixgb.c sc->hw.mac_type = ixgb_82597;
hw 919 dev/pci/if_ixgb.c INIT_DEBUGOUT1("Unknown device if 0x%x", sc->hw.device_id);
hw 921 dev/pci/if_ixgb.c sc->sc_dv.dv_xname, sc->hw.device_id);
hw 952 dev/pci/if_ixgb.c sc->hw.back = &sc->osdep;
hw 997 dev/pci/if_ixgb.c sc->hw.adapter_stopped = FALSE;
hw 998 dev/pci/if_ixgb.c ixgb_adapter_stop(&sc->hw);
hw 1001 dev/pci/if_ixgb.c if (!ixgb_validate_eeprom_checksum(&sc->hw)) {
hw 1006 dev/pci/if_ixgb.c if (!ixgb_init_hw(&sc->hw)) {
hw 1011 dev/pci/if_ixgb.c bcopy(sc->hw.curr_mac_addr, sc->interface_data.ac_enaddr,
hw 1053 dev/pci/if_ixgb.c if ((sc->hw.phy_type == ixgb_phy_type_g6104) ||
hw 1054 dev/pci/if_ixgb.c (sc->hw.phy_type == ixgb_phy_type_txn17401)) {
hw 1234 dev/pci/if_ixgb.c IXGB_WRITE_REG(&sc->hw, TDBAL, (u_int32_t)bus_addr);
hw 1235 dev/pci/if_ixgb.c IXGB_WRITE_REG(&sc->hw, TDBAH, (u_int32_t)(bus_addr >> 32));
hw 1236 dev/pci/if_ixgb.c IXGB_WRITE_REG(&sc->hw, TDLEN,
hw 1241 dev/pci/if_ixgb.c IXGB_WRITE_REG(&sc->hw, TDH, 0);
hw 1242 dev/pci/if_ixgb.c IXGB_WRITE_REG(&sc->hw, TDT, 0);
hw 1245 dev/pci/if_ixgb.c IXGB_READ_REG(&sc->hw, TDBAL),
hw 1246 dev/pci/if_ixgb.c IXGB_READ_REG(&sc->hw, TDLEN));
hw 1248 dev/pci/if_ixgb.c IXGB_WRITE_REG(&sc->hw, TIDV, sc->tx_int_delay);
hw 1251 dev/pci/if_ixgb.c reg_tctl = IXGB_READ_REG(&sc->hw, TCTL);
hw 1253 dev/pci/if_ixgb.c IXGB_WRITE_REG(&sc->hw, TCTL, reg_tctl);
hw 1491 dev/pci/if_ixgb.c if (sc->hw.max_frame_size <= (MCLBYTES - ETHER_ALIGN))
hw 1611 dev/pci/if_ixgb.c reg_rctl = IXGB_READ_REG(&sc->hw, RCTL);
hw 1612 dev/pci/if_ixgb.c IXGB_WRITE_REG(&sc->hw, RCTL, reg_rctl & ~IXGB_RCTL_RXEN);
hw 1615 dev/pci/if_ixgb.c IXGB_WRITE_REG(&sc->hw, RDTR,
hw 1620 dev/pci/if_ixgb.c IXGB_WRITE_REG(&sc->hw, RDBAL, (u_int32_t)bus_addr);
hw 1621 dev/pci/if_ixgb.c IXGB_WRITE_REG(&sc->hw, RDBAH, (u_int32_t)(bus_addr >> 32));
hw 1622 dev/pci/if_ixgb.c IXGB_WRITE_REG(&sc->hw, RDLEN, sc->num_rx_desc *
hw 1626 dev/pci/if_ixgb.c IXGB_WRITE_REG(&sc->hw, RDH, 0);
hw 1628 dev/pci/if_ixgb.c IXGB_WRITE_REG(&sc->hw, RDT, sc->num_rx_desc - 1);
hw 1633 dev/pci/if_ixgb.c IXGB_WRITE_REG(&sc->hw, RXDCTL, reg_rxdctl);
hw 1648 dev/pci/if_ixgb.c IXGB_WRITE_REG(&sc->hw, RAIDC, raidc);
hw 1652 dev/pci/if_ixgb.c reg_rxcsum = IXGB_READ_REG(&sc->hw, RXCSUM);
hw 1654 dev/pci/if_ixgb.c IXGB_WRITE_REG(&sc->hw, RXCSUM, reg_rxcsum);
hw 1657 dev/pci/if_ixgb.c reg_rctl = IXGB_READ_REG(&sc->hw, RCTL);
hw 1661 dev/pci/if_ixgb.c (sc->hw.mc_filter_type << IXGB_RCTL_MO_SHIFT);
hw 1682 dev/pci/if_ixgb.c IXGB_WRITE_REG(&sc->hw, RCTL, reg_rctl);
hw 1889 dev/pci/if_ixgb.c IXGB_WRITE_REG(&sc->hw, RDT, next_to_use);
hw 1931 dev/pci/if_ixgb.c IXGB_WRITE_REG(&sc->hw, IMS, (IXGB_INT_RXT0 | IXGB_INT_TXDW |
hw 1938 dev/pci/if_ixgb.c IXGB_WRITE_REG(&sc->hw, IMC, ~0);
hw 1942 dev/pci/if_ixgb.c ixgb_write_pci_cfg(struct ixgb_hw *hw,
hw 1946 dev/pci/if_ixgb.c struct pci_attach_args *pa = &((struct ixgb_osdep *)hw->back)->ixgb_pa;
hw 1962 dev/pci/if_ixgb.c sc->stats.crcerrs += IXGB_READ_REG(&sc->hw, CRCERRS);
hw 1963 dev/pci/if_ixgb.c sc->stats.gprcl += IXGB_READ_REG(&sc->hw, GPRCL);
hw 1964 dev/pci/if_ixgb.c sc->stats.gprch += IXGB_READ_REG(&sc->hw, GPRCH);
hw 1965 dev/pci/if_ixgb.c sc->stats.gorcl += IXGB_READ_REG(&sc->hw, GORCL);
hw 1966 dev/pci/if_ixgb.c sc->stats.gorch += IXGB_READ_REG(&sc->hw, GORCH);
hw 1967 dev/pci/if_ixgb.c sc->stats.bprcl += IXGB_READ_REG(&sc->hw, BPRCL);
hw 1968 dev/pci/if_ixgb.c sc->stats.bprch += IXGB_READ_REG(&sc->hw, BPRCH);
hw 1969 dev/pci/if_ixgb.c sc->stats.mprcl += IXGB_READ_REG(&sc->hw, MPRCL);
hw 1970 dev/pci/if_ixgb.c sc->stats.mprch += IXGB_READ_REG(&sc->hw, MPRCH);
hw 1971 dev/pci/if_ixgb.c sc->stats.roc += IXGB_READ_REG(&sc->hw, ROC);
hw 1973 dev/pci/if_ixgb.c sc->stats.mpc += IXGB_READ_REG(&sc->hw, MPC);
hw 1974 dev/pci/if_ixgb.c sc->stats.dc += IXGB_READ_REG(&sc->hw, DC);
hw 1975 dev/pci/if_ixgb.c sc->stats.rlec += IXGB_READ_REG(&sc->hw, RLEC);
hw 1976 dev/pci/if_ixgb.c sc->stats.xonrxc += IXGB_READ_REG(&sc->hw, XONRXC);
hw 1977 dev/pci/if_ixgb.c sc->stats.xontxc += IXGB_READ_REG(&sc->hw, XONTXC);
hw 1978 dev/pci/if_ixgb.c sc->stats.xoffrxc += IXGB_READ_REG(&sc->hw, XOFFRXC);
hw 1979 dev/pci/if_ixgb.c sc->stats.xofftxc += IXGB_READ_REG(&sc->hw, XOFFTXC);
hw 1980 dev/pci/if_ixgb.c sc->stats.gptcl += IXGB_READ_REG(&sc->hw, GPTCL);
hw 1981 dev/pci/if_ixgb.c sc->stats.gptch += IXGB_READ_REG(&sc->hw, GPTCH);
hw 1982 dev/pci/if_ixgb.c sc->stats.gotcl += IXGB_READ_REG(&sc->hw, GOTCL);
hw 1983 dev/pci/if_ixgb.c sc->stats.gotch += IXGB_READ_REG(&sc->hw, GOTCH);
hw 1984 dev/pci/if_ixgb.c sc->stats.ruc += IXGB_READ_REG(&sc->hw, RUC);
hw 1985 dev/pci/if_ixgb.c sc->stats.rfc += IXGB_READ_REG(&sc->hw, RFC);
hw 1986 dev/pci/if_ixgb.c sc->stats.rjc += IXGB_READ_REG(&sc->hw, RJC);
hw 1987 dev/pci/if_ixgb.c sc->stats.torl += IXGB_READ_REG(&sc->hw, TORL);
hw 1988 dev/pci/if_ixgb.c sc->stats.torh += IXGB_READ_REG(&sc->hw, TORH);
hw 1989 dev/pci/if_ixgb.c sc->stats.totl += IXGB_READ_REG(&sc->hw, TOTL);
hw 1990 dev/pci/if_ixgb.c sc->stats.toth += IXGB_READ_REG(&sc->hw, TOTH);
hw 1991 dev/pci/if_ixgb.c sc->stats.tprl += IXGB_READ_REG(&sc->hw, TPRL);
hw 1992 dev/pci/if_ixgb.c sc->stats.tprh += IXGB_READ_REG(&sc->hw, TPRH);
hw 1993 dev/pci/if_ixgb.c sc->stats.tptl += IXGB_READ_REG(&sc->hw, TPTL);
hw 1994 dev/pci/if_ixgb.c sc->stats.tpth += IXGB_READ_REG(&sc->hw, TPTH);
hw 1995 dev/pci/if_ixgb.c sc->stats.plt64c += IXGB_READ_REG(&sc->hw, PLT64C);
hw 1996 dev/pci/if_ixgb.c sc->stats.mptcl += IXGB_READ_REG(&sc->hw, MPTCL);
hw 1997 dev/pci/if_ixgb.c sc->stats.mptch += IXGB_READ_REG(&sc->hw, MPTCH);
hw 1998 dev/pci/if_ixgb.c sc->stats.bptcl += IXGB_READ_REG(&sc->hw, BPTCL);
hw 1999 dev/pci/if_ixgb.c sc->stats.bptch += IXGB_READ_REG(&sc->hw, BPTCH);
hw 2001 dev/pci/if_ixgb.c sc->stats.uprcl += IXGB_READ_REG(&sc->hw, UPRCL);
hw 2002 dev/pci/if_ixgb.c sc->stats.uprch += IXGB_READ_REG(&sc->hw, UPRCH);
hw 2003 dev/pci/if_ixgb.c sc->stats.vprcl += IXGB_READ_REG(&sc->hw, VPRCL);
hw 2004 dev/pci/if_ixgb.c sc->stats.vprch += IXGB_READ_REG(&sc->hw, VPRCH);
hw 2005 dev/pci/if_ixgb.c sc->stats.jprcl += IXGB_READ_REG(&sc->hw, JPRCL);
hw 2006 dev/pci/if_ixgb.c sc->stats.jprch += IXGB_READ_REG(&sc->hw, JPRCH);
hw 2007 dev/pci/if_ixgb.c sc->stats.rnbc += IXGB_READ_REG(&sc->hw, RNBC);
hw 2008 dev/pci/if_ixgb.c sc->stats.icbc += IXGB_READ_REG(&sc->hw, ICBC);
hw 2009 dev/pci/if_ixgb.c sc->stats.ecbc += IXGB_READ_REG(&sc->hw, ECBC);
hw 2010 dev/pci/if_ixgb.c sc->stats.uptcl += IXGB_READ_REG(&sc->hw, UPTCL);
hw 2011 dev/pci/if_ixgb.c sc->stats.uptch += IXGB_READ_REG(&sc->hw, UPTCH);
hw 2012 dev/pci/if_ixgb.c sc->stats.vptcl += IXGB_READ_REG(&sc->hw, VPTCL);
hw 2013 dev/pci/if_ixgb.c sc->stats.vptch += IXGB_READ_REG(&sc->hw, VPTCH);
hw 2014 dev/pci/if_ixgb.c sc->stats.jptcl += IXGB_READ_REG(&sc->hw, JPTCL);
hw 2015 dev/pci/if_ixgb.c sc->stats.jptch += IXGB_READ_REG(&sc->hw, JPTCH);
hw 2016 dev/pci/if_ixgb.c sc->stats.tsctc += IXGB_READ_REG(&sc->hw, TSCTC);
hw 2017 dev/pci/if_ixgb.c sc->stats.tsctfc += IXGB_READ_REG(&sc->hw, TSCTFC);
hw 2018 dev/pci/if_ixgb.c sc->stats.ibic += IXGB_READ_REG(&sc->hw, IBIC);
hw 2019 dev/pci/if_ixgb.c sc->stats.lfc += IXGB_READ_REG(&sc->hw, LFC);
hw 2020 dev/pci/if_ixgb.c sc->stats.pfrc += IXGB_READ_REG(&sc->hw, PFRC);
hw 2021 dev/pci/if_ixgb.c sc->stats.pftc += IXGB_READ_REG(&sc->hw, PFTC);
hw 2022 dev/pci/if_ixgb.c sc->stats.mcfrc += IXGB_READ_REG(&sc->hw, MCFRC);
hw 2057 dev/pci/if_ixgb.c bus_speed = sc->hw.bus.speed;
hw 2058 dev/pci/if_ixgb.c bus_type = sc->hw.bus.type;
hw 234 dev/pci/if_ixgb.h struct ixgb_hw hw;
hw 1164 dev/pci/if_msk.c u_int8_t hw, pmd;
hw 1365 dev/pci/if_msk.c hw = sk_win_read_1(sc, SK_Y2_HWRES);
hw 1366 dev/pci/if_msk.c if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) {
hw 141 dev/pci/if_san_common.c san_dev_attach(void *hw, u_int8_t *devname, int namelen)
hw 157 dev/pci/if_san_common.c card->hw = hw;
hw 160 dev/pci/if_san_common.c sdla_getcfg(card->hw, SDLA_CARDTYPE, &card->type);
hw 161 dev/pci/if_san_common.c if (sdla_is_te1(card->hw))
hw 164 dev/pci/if_san_common.c err = sdla_setup(card->hw);
hw 170 dev/pci/if_san_common.c err = sdla_intr_establish(card->hw, sdla_isr, (void*)card);
hw 174 dev/pci/if_san_common.c sdla_down(card->hw);
hw 232 dev/pci/if_san_common.c card->hw = NULL;
hw 234 dev/pci/if_san_common.c card->same_cpu->hw = NULL;
hw 250 dev/pci/if_san_common.c sdla_down(card->hw);
hw 251 dev/pci/if_san_common.c sdla_intr_disestablish(card->hw);
hw 307 dev/pci/if_san_common.c err = sdla_get_hwprobe(card->hw, (void**)&str);
hw 343 dev/pci/if_san_common.c sdla_getcfg(card->hw, SDLA_MEMORY, &memory);
hw 354 dev/pci/if_san_common.c sdla_peek(card->hw, dump.offset, data, dump.length);
hw 379 dev/pci/if_san_common.h void *hw; /* hw configuration */
hw 2055 dev/pci/if_san_te1.c sdla_getcfg(card->hw, SDLA_ADAPTERTYPE, &adapter_type);
hw 339 dev/pci/if_san_xilinx.c sdla_getcfg(card->hw, SDLA_BASEADDR, &card->u.xilinx.bar);
hw 362 dev/pci/if_san_xilinx.c sdla_getcfg(card->hw, SDLA_DMATAG, &sc->dmatag);
hw 967 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, ®);
hw 984 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg);
hw 989 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, ®);
hw 991 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg);
hw 995 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg);
hw 1003 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, ®);
hw 1005 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg);
hw 1017 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg);
hw 1021 dev/pci/if_san_xilinx.c sdla_getcfg(card->hw, SDLA_ADAPTERTYPE, &adapter_type);
hw 1055 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, ®);
hw 1057 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg);
hw 1081 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, ®);
hw 1086 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg);
hw 1115 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_DMA_CONTROL_REG, reg);
hw 1124 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG, reg);
hw 1127 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_DMA_RX_INTR_PENDING_REG, &tmp);
hw 1128 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_DMA_TX_INTR_PENDING_REG, &tmp);
hw 1129 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_HDLC_RX_INTR_PENDING_REG, &tmp);
hw 1130 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_HDLC_TX_INTR_PENDING_REG, &tmp);
hw 1131 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, (u_int32_t *)®);
hw 1139 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg);
hw 1149 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg);
hw 1167 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg);
hw 1177 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG, reg);
hw 1178 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, ®);
hw 1183 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg);
hw 1274 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw,
hw 1282 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw,
hw 1316 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw,
hw 1324 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw,
hw 1363 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw,
hw 1371 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw,
hw 1387 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG, ®);
hw 1392 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG,
hw 1423 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG, ®);
hw 1427 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG,
hw 1436 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw,
hw 1444 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw,
hw 1506 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, dma_descr, reg);
hw 1510 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, dma_descr, ®);
hw 1554 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, dma_descr, reg);
hw 1558 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, dma_descr, ®);
hw 1593 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_GLOBAL_INTER_MASK, ®);
hw 1596 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_GLOBAL_INTER_MASK, reg);
hw 1612 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_GLOBAL_INTER_MASK, ®);
hw 1623 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_GLOBAL_INTER_MASK, reg);
hw 1629 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG, ®);
hw 1634 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG,
hw 1645 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, dma_descr, reg);
hw 1647 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, dma_descr, reg);
hw 1663 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, dma_descr, ®);
hw 1716 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, dma_descr, reg);
hw 1742 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, dma_descr, reg);
hw 1804 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, dma_descr, ®);
hw 1890 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, dma_descr, reg);
hw 1921 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, dma_descr, reg);
hw 1940 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, dma_descr, ®);
hw 1975 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, dma_descr, reg);
hw 2085 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, dma_descr, &rx_el->align);
hw 2089 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, dma_descr, &rx_el->reg);
hw 2374 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_DMA_CONTROL_REG, ®);
hw 2381 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_DMA_CONTROL_REG, reg);
hw 2572 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_HDLC_TX_INTR_PENDING_REG, &tx_status);
hw 2573 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_HDLC_RX_INTR_PENDING_REG, &rx_status);
hw 2675 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, dma_descr, ®);
hw 2732 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, ®);
hw 2781 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_DMA_RX_INTR_PENDING_REG,
hw 2808 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_DMA_TX_INTR_PENDING_REG,
hw 2922 dev/pci/if_san_xilinx.c sdla_bus_read_2(card->hw, XILINX_MCPU_INTERFACE_ADDR, &org_off);
hw 2924 dev/pci/if_san_xilinx.c sdla_bus_write_2(card->hw, XILINX_MCPU_INTERFACE_ADDR, cpld_off);
hw 2926 dev/pci/if_san_xilinx.c sdla_bus_read_1(card->hw, XILINX_MCPU_INTERFACE, &tmp);
hw 2929 dev/pci/if_san_xilinx.c sdla_bus_write_2(card->hw, XILINX_MCPU_INTERFACE_ADDR, org_off);
hw 2943 dev/pci/if_san_xilinx.c sdla_bus_read_2(card->hw, XILINX_MCPU_INTERFACE_ADDR, &org_off);
hw 2945 dev/pci/if_san_xilinx.c sdla_bus_write_2(card->hw, XILINX_MCPU_INTERFACE_ADDR, off);
hw 2951 dev/pci/if_san_xilinx.c sdla_bus_write_1(card->hw, XILINX_MCPU_INTERFACE, data);
hw 2958 dev/pci/if_san_xilinx.c sdla_bus_write_2(card->hw, XILINX_MCPU_INTERFACE_ADDR, org_off);
hw 2969 dev/pci/if_san_xilinx.c sdla_bus_write_2(card->hw, XILINX_MCPU_INTERFACE_ADDR, off);
hw 2975 dev/pci/if_san_xilinx.c sdla_bus_write_1(card->hw, XILINX_MCPU_INTERFACE, value);
hw 2992 dev/pci/if_san_xilinx.c sdla_bus_write_2(card->hw, XILINX_MCPU_INTERFACE_ADDR, off);
hw 2993 dev/pci/if_san_xilinx.c sdla_bus_read_1(card->hw, XILINX_MCPU_INTERFACE, &tmp);
hw 3032 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_DMA_RX_INTR_PENDING_REG, ®);
hw 3033 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_DMA_TX_INTR_PENDING_REG, ®);
hw 3060 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_DMA_CONTROL_REG, ®);
hw 3062 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_DMA_CONTROL_REG, reg);
hw 3146 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_HDLC_RX_INTR_PENDING_REG, ®);
hw 3147 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_HDLC_TX_INTR_PENDING_REG, ®);
hw 3151 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, ®);
hw 3154 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg);
hw 3164 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, ®);
hw 3170 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg);
hw 3172 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_DMA_CONTROL_REG, ®);
hw 3174 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_DMA_CONTROL_REG, reg);
hw 3185 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, dma_descr, reg);
hw 3204 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, dma_descr, reg);
hw 3263 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG, ®);
hw 3267 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, reg_off, data);
hw 3473 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, &led);
hw 3486 dev/pci/if_san_xilinx.c sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, led);
hw 3551 dev/pci/if_san_xilinx.c sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, ®);
hw 421 dev/pci/if_san_xilinx.h sdla_bus_write_4(card->hw,AFT_TE3_RX_WDT_CTRL_REG,0);
hw 427 dev/pci/if_san_xilinx.h sdla_bus_write_4(card->hw,AFT_TE3_RX_WDT_CTRL_REG,timeout);
hw 432 dev/pci/if_san_xilinx.h sdla_bus_write_4(card->hw,AFT_TE3_TX_WDT_CTRL_REG,0);
hw 438 dev/pci/if_san_xilinx.h sdla_bus_write_4(card->hw,AFT_TE3_TX_WDT_CTRL_REG,timeout);
hw 63 dev/pci/if_sandrv.c #define IS_SUPPORTED_ADAPTER(hw) ((hw)->type == SDLA_AFT)
hw 68 dev/pci/if_sandrv.c #define IS_AFT(hw) (hw->type == SDLA_AFT)
hw 395 dev/pci/if_sandrv.c sdla_save_hw_probe(sdlahw_t *hw, int port)
hw 407 dev/pci/if_sandrv.c SDLA_ADPTR_DECODE(hw->hwcard->atype), hw->hwcard->slot_no,
hw 408 dev/pci/if_sandrv.c hw->hwcard->bus_no, hw->irq, SDLA_GET_CPU(hw->cpu_no), "PRI");
hw 410 dev/pci/if_sandrv.c hw->hwprobe = tmp_hw_probe;
hw 419 dev/pci/if_sandrv.c sdlahw_t* hw = NULL;
hw 425 dev/pci/if_sandrv.c hw = sdla_hw_register(hwcard, cpu_no, irq, pa);
hw 426 dev/pci/if_sandrv.c sdla_save_hw_probe(hw, 0);
hw 437 dev/pci/if_sandrv.c hw = sdla_hw_register(hwcard, cpu_no, irq, pa);
hw 438 dev/pci/if_sandrv.c sdla_save_hw_probe(hw, 0);
hw 450 dev/pci/if_sandrv.c hw = sdla_hw_register(hwcard, cpu_no, irq, pa);
hw 451 dev/pci/if_sandrv.c sdla_save_hw_probe(hw, 0);
hw 467 dev/pci/if_sandrv.c return (hw);
hw 475 dev/pci/if_sandrv.c sdlahw_t* hw;
hw 515 dev/pci/if_sandrv.c hw = sdla_aft_hw_select(hwcard, cpu, irq, pa);
hw 523 dev/pci/if_sandrv.c if (hw == NULL)
hw 525 dev/pci/if_sandrv.c if (san_dev_attach(hw, hw->devname, sizeof(hw->devname)))
hw 528 dev/pci/if_sandrv.c hw->used++;
hw 541 dev/pci/if_sandrv.c sdlahw_t *hw = (sdlahw_t*)phw;
hw 544 dev/pci/if_sandrv.c WAN_ASSERT(hw == NULL);
hw 545 dev/pci/if_sandrv.c hwcard = hw->hwcard;
hw 556 dev/pci/if_sandrv.c sdlahw_t *hw = (sdlahw_t*)phw;
hw 559 dev/pci/if_sandrv.c hw->devname);
hw 780 dev/pci/if_sandrv.c sdlahw_t* hw = (sdlahw_t*)phw;
hw 783 dev/pci/if_sandrv.c WAN_ASSERT(hw == NULL);
hw 784 dev/pci/if_sandrv.c SDLA_MAGIC(hw);
hw 785 dev/pci/if_sandrv.c WAN_ASSERT(hw->hwcard == NULL);
hw 786 dev/pci/if_sandrv.c hwcard = hw->hwcard;
hw 793 dev/pci/if_sandrv.c hw->devname, hw->hwcard->type);
hw 797 dev/pci/if_sandrv.c hw->dpmsize = SDLA_WINDOWSIZE;
hw 799 dev/pci/if_sandrv.c err = sdla_detect(hw);
hw 811 dev/pci/if_sandrv.c sdlahw_t* hw = (sdlahw_t*)phw;
hw 813 dev/pci/if_sandrv.c WAN_ASSERT(hw == NULL);
hw 814 dev/pci/if_sandrv.c SDLA_MAGIC(hw);
hw 815 dev/pci/if_sandrv.c WAN_ASSERT(hw->hwcard == NULL);
hw 816 dev/pci/if_sandrv.c card = hw->hwcard;
hw 820 dev/pci/if_sandrv.c if (hw->status & SDLA_MEM_MAPPED) {
hw 821 dev/pci/if_sandrv.c bus_space_unmap(hw->hwcard->memt,
hw 822 dev/pci/if_sandrv.c hw->dpmbase,
hw 824 dev/pci/if_sandrv.c hw->status &= ~SDLA_MEM_MAPPED;
hw 841 dev/pci/if_sandrv.c sdlahw_t* hw = (sdlahw_t*)phw;
hw 843 dev/pci/if_sandrv.c WAN_ASSERT(hw == NULL);
hw 844 dev/pci/if_sandrv.c SDLA_MAGIC(hw);
hw 845 dev/pci/if_sandrv.c WAN_ASSERT(hw->hwcard == NULL);
hw 846 dev/pci/if_sandrv.c card = hw->hwcard;
hw 849 dev/pci/if_sandrv.c sdla_pci_read_config_dword(hw, PCI_INT_STATUS, int_status);
hw 861 dev/pci/if_sandrv.c sdlahw_t *hw = (sdlahw_t*)phw;
hw 866 dev/pci/if_sandrv.c SDLA_MAGIC(hw);
hw 869 dev/pci/if_sandrv.c sdla_peek(hw, offset, (void*)&value, 1);
hw 872 dev/pci/if_sandrv.c hw->devname);
hw 876 dev/pci/if_sandrv.c sdla_poke(hw, offset, (void*)mbox, len);
hw 878 dev/pci/if_sandrv.c err = sdla_exec(hw, offset);
hw 881 dev/pci/if_sandrv.c hw->devname, mbox->wan_command);
hw 884 dev/pci/if_sandrv.c sdla_peek(hw, offset, (void*)mbox, sizeof(wan_cmd_t));
hw 886 dev/pci/if_sandrv.c sdla_peek(hw, offset+offsetof(wan_mbox_t, wan_data),
hw 900 dev/pci/if_sandrv.c sdla_exec(sdlahw_t *hw, unsigned long offset)
hw 907 dev/pci/if_sandrv.c sdla_poke(hw, offset, (void*)&value, 1);
hw 910 dev/pci/if_sandrv.c sdla_peek(hw, offset, (void*)&value, 1);
hw 915 dev/pci/if_sandrv.c "loops %lu (max=%u)\n", hw->devname,
hw 920 dev/pci/if_sandrv.c sdla_peek(hw, offset, (void*)&value, 1);
hw 940 dev/pci/if_sandrv.c sdlahw_t* hw = (sdlahw_t*)phw;
hw 943 dev/pci/if_sandrv.c WAN_ASSERT(hw == NULL);
hw 944 dev/pci/if_sandrv.c SDLA_MAGIC(hw);
hw 945 dev/pci/if_sandrv.c WAN_ASSERT(hw->hwcard == NULL);
hw 946 dev/pci/if_sandrv.c card = hw->hwcard;
hw 947 dev/pci/if_sandrv.c if (addr + len > hw->memory) /* verify arguments */
hw 952 dev/pci/if_sandrv.c sdla_peek_by_4(hw, addr, buf, len);
hw 971 dev/pci/if_sandrv.c sdla_peek_by_4(sdlahw_t *hw, unsigned long offset, void *buf, unsigned int len)
hw 975 dev/pci/if_sandrv.c sdla_bus_read_1(hw, offset++, (u_int8_t*)buf);
hw 982 dev/pci/if_sandrv.c sdla_bus_read_4(hw, offset, (u_int32_t*)buf);
hw 990 dev/pci/if_sandrv.c sdla_bus_read_1(hw, offset++, (u_int8_t*)buf);
hw 1009 dev/pci/if_sandrv.c sdlahw_t* hw = (sdlahw_t*)phw;
hw 1012 dev/pci/if_sandrv.c WAN_ASSERT(hw == NULL);
hw 1013 dev/pci/if_sandrv.c SDLA_MAGIC(hw);
hw 1014 dev/pci/if_sandrv.c WAN_ASSERT(hw->hwcard == NULL);
hw 1015 dev/pci/if_sandrv.c card = hw->hwcard;
hw 1016 dev/pci/if_sandrv.c if (addr + len > hw->memory) { /* verify arguments */
hw 1022 dev/pci/if_sandrv.c sdla_poke_by_4(hw, addr, buf, len);
hw 1041 dev/pci/if_sandrv.c sdla_poke_by_4(sdlahw_t *hw, unsigned long offset, void *buf, unsigned int len)
hw 1045 dev/pci/if_sandrv.c sdla_bus_write_1(hw, offset++, *(char *)buf);
hw 1052 dev/pci/if_sandrv.c sdla_bus_write_4(hw, offset, *(unsigned long *)buf);
hw 1060 dev/pci/if_sandrv.c sdla_bus_write_1(hw, offset++, *(char *)buf);
hw 1069 dev/pci/if_sandrv.c sdlahw_t *hw = (sdlahw_t*)phw;
hw 1071 dev/pci/if_sandrv.c SDLA_MAGIC(hw);
hw 1073 dev/pci/if_sandrv.c sdla_poke(hw, offset, (void*)&value, 1);
hw 1080 dev/pci/if_sandrv.c sdlahw_t *hw = (sdlahw_t*)phw;
hw 1083 dev/pci/if_sandrv.c SDLA_MAGIC(hw);
hw 1085 dev/pci/if_sandrv.c sdla_peek(hw, offset, (void*)&tmp, 1);
hw 1088 dev/pci/if_sandrv.c sdla_poke(hw, offset, (void*)&tmp, 1);
hw 1095 dev/pci/if_sandrv.c sdlahw_t *hw = (sdlahw_t*)phw;
hw 1098 dev/pci/if_sandrv.c SDLA_MAGIC(hw);
hw 1100 dev/pci/if_sandrv.c sdla_peek(hw, offset, (void*)&tmp, 1);
hw 1103 dev/pci/if_sandrv.c sdla_poke(hw, offset, (void*)&tmp, 1);
hw 1112 dev/pci/if_sandrv.c sdla_detect_aft(sdlahw_t *hw)
hw 1117 dev/pci/if_sandrv.c WAN_ASSERT(hw == NULL);
hw 1118 dev/pci/if_sandrv.c WAN_ASSERT(hw->hwcard == NULL);
hw 1119 dev/pci/if_sandrv.c card = hw->hwcard;
hw 1120 dev/pci/if_sandrv.c sdla_pci_read_config_dword(hw,
hw 1121 dev/pci/if_sandrv.c (hw->cpu_no == SDLA_CPU_A) ? PCI_IO_BASE_DWORD :
hw 1122 dev/pci/if_sandrv.c PCI_MEM_BASE0_DWORD, (u_int32_t*)&hw->mem_base_addr);
hw 1123 dev/pci/if_sandrv.c if (!hw->mem_base_addr) {
hw 1124 dev/pci/if_sandrv.c if (hw->cpu_no == SDLA_CPU_B) {
hw 1126 dev/pci/if_sandrv.c hw->devname);
hw 1129 dev/pci/if_sandrv.c hw->devname);
hw 1135 dev/pci/if_sandrv.c hw->devname, (unsigned long)hw->mem_base_addr);
hw 1137 dev/pci/if_sandrv.c sdla_pci_read_config_byte(hw, PCI_INTLINE, (u_int8_t*)&hw->irq);
hw 1138 dev/pci/if_sandrv.c if (hw->irq == PCI_IRQ_NOT_ALLOCATED) {
hw 1139 dev/pci/if_sandrv.c printf("%s: IRQ not allocated to AFT adapter\n", hw->devname);
hw 1145 dev/pci/if_sandrv.c hw->devname, hw->irq);
hw 1148 dev/pci/if_sandrv.c hw->memory=XILINX_PCI_MEM_SIZE;
hw 1151 dev/pci/if_sandrv.c bus_space_map(hw->hwcard->memt, hw->mem_base_addr, XILINX_PCI_MEM_SIZE,
hw 1152 dev/pci/if_sandrv.c 0, &hw->dpmbase);
hw 1153 dev/pci/if_sandrv.c if (!hw->dpmbase) {
hw 1154 dev/pci/if_sandrv.c printf("%s: couldn't map memory\n", hw->devname);
hw 1157 dev/pci/if_sandrv.c hw->status |= SDLA_MEM_MAPPED;
hw 1161 dev/pci/if_sandrv.c sdla_pci_read_config_word(hw, XILINX_PCI_CMD_REG, &ut_u16);
hw 1163 dev/pci/if_sandrv.c sdla_pci_write_config_word(hw, XILINX_PCI_CMD_REG, ut_u16);
hw 1166 dev/pci/if_sandrv.c sdla_pci_write_config_dword(hw, XILINX_PCI_LATENCY_REG,
hw 1177 dev/pci/if_sandrv.c sdla_detect(sdlahw_t *hw)
hw 1182 dev/pci/if_sandrv.c WAN_ASSERT(hw == NULL);
hw 1183 dev/pci/if_sandrv.c WAN_ASSERT(hw->hwcard == NULL);
hw 1184 dev/pci/if_sandrv.c card = hw->hwcard;
hw 1187 dev/pci/if_sandrv.c err = sdla_detect_aft(hw);
hw 1191 dev/pci/if_sandrv.c sdla_down(hw);
hw 1200 dev/pci/if_sandrv.c sdlahw_t *hw = (sdlahw_t*)phw;
hw 1202 dev/pci/if_sandrv.c WAN_ASSERT(hw == NULL);
hw 1203 dev/pci/if_sandrv.c SDLA_MAGIC(hw);
hw 1204 dev/pci/if_sandrv.c WAN_ASSERT(hw->hwcard == NULL);
hw 1205 dev/pci/if_sandrv.c hwcard = hw->hwcard;
hw 1221 dev/pci/if_sandrv.c sdlahw_t *hw = (sdlahw_t*)phw;
hw 1223 dev/pci/if_sandrv.c WAN_ASSERT(hw == NULL);
hw 1224 dev/pci/if_sandrv.c SDLA_MAGIC(hw);
hw 1225 dev/pci/if_sandrv.c WAN_ASSERT(hw->hwcard == NULL);
hw 1226 dev/pci/if_sandrv.c hwcard = hw->hwcard;
hw 1233 dev/pci/if_sandrv.c "User=T1/E1 Actual=%s\n", hw->devname,
hw 1242 dev/pci/if_sandrv.c "User=56K Actual=%s\n", hw->devname,
hw 1252 dev/pci/if_sandrv.c "User=S514(1/2/3) Actual=%s\n", hw->devname,
hw 1264 dev/pci/if_sandrv.c sdlahw_t* hw = (sdlahw_t*)phw;
hw 1267 dev/pci/if_sandrv.c WAN_ASSERT(hw == NULL);
hw 1268 dev/pci/if_sandrv.c SDLA_MAGIC(hw);
hw 1269 dev/pci/if_sandrv.c WAN_ASSERT(hw->hwcard == NULL);
hw 1270 dev/pci/if_sandrv.c hwcard = hw->hwcard;
hw 1276 dev/pci/if_sandrv.c *(bus_space_handle_t*)value = hw->dpmbase;
hw 1279 dev/pci/if_sandrv.c *(u_int32_t*)value = ((unsigned long)hw->dpmbase +
hw 1280 dev/pci/if_sandrv.c hw->dpmsize - 1);
hw 1283 dev/pci/if_sandrv.c *(u_int16_t*)value = hw->dpmsize;
hw 1286 dev/pci/if_sandrv.c *(u_int32_t*)value = hw->memory;
hw 1289 dev/pci/if_sandrv.c *(u_int16_t*)value = hw->irq;
hw 1295 dev/pci/if_sandrv.c *(u_int16_t*)value = hw->cpu_no;
hw 1310 dev/pci/if_sandrv.c *(u_int32_t*)value = hw->mem_base_addr;
hw 1320 dev/pci/if_sandrv.c sdlahw_t *hw = (sdlahw_t*)phw;
hw 1322 dev/pci/if_sandrv.c WAN_ASSERT(hw == NULL);
hw 1323 dev/pci/if_sandrv.c SDLA_MAGIC(hw);
hw 1325 dev/pci/if_sandrv.c *phwcard = hw->hwcard;
hw 1333 dev/pci/if_sandrv.c sdlahw_t *hw = (sdlahw_t*)phw;
hw 1335 dev/pci/if_sandrv.c WAN_ASSERT(hw == NULL);
hw 1336 dev/pci/if_sandrv.c SDLA_MAGIC(hw);
hw 1338 dev/pci/if_sandrv.c if (hw->hwprobe)
hw 1339 dev/pci/if_sandrv.c *str = hw->hwprobe->hw_info;
hw 1347 dev/pci/if_sandrv.c sdlahw_t *hw = (sdlahw_t*)phw;
hw 1349 dev/pci/if_sandrv.c WAN_ASSERT(hw == NULL);
hw 1350 dev/pci/if_sandrv.c SDLA_MAGIC(hw);
hw 1351 dev/pci/if_sandrv.c if (!(hw->status & SDLA_MEM_MAPPED))
hw 1353 dev/pci/if_sandrv.c bus_space_write_1(hw->hwcard->memt, hw->dpmbase, offset, value);
hw 1360 dev/pci/if_sandrv.c sdlahw_t *hw = (sdlahw_t*)phw;
hw 1362 dev/pci/if_sandrv.c WAN_ASSERT(hw == NULL);
hw 1363 dev/pci/if_sandrv.c SDLA_MAGIC(hw);
hw 1364 dev/pci/if_sandrv.c if (!(hw->status & SDLA_MEM_MAPPED))
hw 1366 dev/pci/if_sandrv.c bus_space_write_2(hw->hwcard->memt, hw->dpmbase, offset, value);
hw 1373 dev/pci/if_sandrv.c sdlahw_t *hw = (sdlahw_t*)phw;
hw 1375 dev/pci/if_sandrv.c WAN_ASSERT(hw == NULL);
hw 1376 dev/pci/if_sandrv.c SDLA_MAGIC(hw);
hw 1377 dev/pci/if_sandrv.c if (!(hw->status & SDLA_MEM_MAPPED))
hw 1379 dev/pci/if_sandrv.c bus_space_write_4(hw->hwcard->memt, hw->dpmbase, offset, value);
hw 1386 dev/pci/if_sandrv.c sdlahw_t *hw = (sdlahw_t*)phw;
hw 1388 dev/pci/if_sandrv.c WAN_ASSERT2(hw == NULL, 0);
hw 1389 dev/pci/if_sandrv.c SDLA_MAGIC(hw);
hw 1390 dev/pci/if_sandrv.c if (!(hw->status & SDLA_MEM_MAPPED))
hw 1392 dev/pci/if_sandrv.c *value = bus_space_read_1(hw->hwcard->memt, hw->dpmbase, offset);
hw 1399 dev/pci/if_sandrv.c sdlahw_t *hw = (sdlahw_t*)phw;
hw 1401 dev/pci/if_sandrv.c WAN_ASSERT2(hw == NULL, 0);
hw 1402 dev/pci/if_sandrv.c SDLA_MAGIC(hw);
hw 1403 dev/pci/if_sandrv.c if (!(hw->status & SDLA_MEM_MAPPED))
hw 1405 dev/pci/if_sandrv.c *value = bus_space_read_2(hw->hwcard->memt, hw->dpmbase, offset);
hw 1412 dev/pci/if_sandrv.c sdlahw_t *hw = (sdlahw_t*)phw;
hw 1414 dev/pci/if_sandrv.c WAN_ASSERT2(hw == NULL, 0);
hw 1415 dev/pci/if_sandrv.c WAN_ASSERT2(hw->dpmbase == 0, 0);
hw 1416 dev/pci/if_sandrv.c SDLA_MAGIC(hw);
hw 1417 dev/pci/if_sandrv.c if (!(hw->status & SDLA_MEM_MAPPED))
hw 1419 dev/pci/if_sandrv.c *value = bus_space_read_4(hw->hwcard->memt, hw->dpmbase, offset);
hw 1426 dev/pci/if_sandrv.c sdlahw_t *hw = (sdlahw_t*)phw;
hw 1429 dev/pci/if_sandrv.c WAN_ASSERT(hw == NULL);
hw 1430 dev/pci/if_sandrv.c SDLA_MAGIC(hw);
hw 1431 dev/pci/if_sandrv.c WAN_ASSERT(hw->hwcard == NULL);
hw 1432 dev/pci/if_sandrv.c hwcard = hw->hwcard;
hw 1440 dev/pci/if_sandrv.c sdlahw_t *hw = (sdlahw_t*)phw;
hw 1444 dev/pci/if_sandrv.c WAN_ASSERT(hw == NULL);
hw 1445 dev/pci/if_sandrv.c SDLA_MAGIC(hw);
hw 1446 dev/pci/if_sandrv.c WAN_ASSERT(hw->hwcard == NULL);
hw 1447 dev/pci/if_sandrv.c hwcard = hw->hwcard;
hw 1456 dev/pci/if_sandrv.c sdlahw_t *hw = (sdlahw_t*)phw;
hw 1460 dev/pci/if_sandrv.c WAN_ASSERT(hw == NULL);
hw 1461 dev/pci/if_sandrv.c SDLA_MAGIC(hw);
hw 1462 dev/pci/if_sandrv.c WAN_ASSERT(hw->hwcard == NULL);
hw 1463 dev/pci/if_sandrv.c hwcard = hw->hwcard;
hw 1472 dev/pci/if_sandrv.c sdlahw_t *hw = (sdlahw_t*)phw;
hw 1475 dev/pci/if_sandrv.c WAN_ASSERT(hw == NULL);
hw 1476 dev/pci/if_sandrv.c SDLA_MAGIC(hw);
hw 1477 dev/pci/if_sandrv.c WAN_ASSERT(hw->hwcard == NULL);
hw 1478 dev/pci/if_sandrv.c card = hw->hwcard;
hw 1486 dev/pci/if_sandrv.c sdlahw_t *hw = (sdlahw_t*)phw;
hw 1489 dev/pci/if_sandrv.c WAN_ASSERT(hw == NULL);
hw 1490 dev/pci/if_sandrv.c SDLA_MAGIC(hw);
hw 1491 dev/pci/if_sandrv.c WAN_ASSERT(hw->hwcard == NULL);
hw 1492 dev/pci/if_sandrv.c card = hw->hwcard;
hw 259 dev/pci/if_sandrv.h #define SDLA_MAGIC(hw) WAN_ASSERT((hw)->magic != SDLAHW_MAGIC)
hw 1387 dev/pci/if_wpi.c uint32_t hw;
hw 1389 dev/pci/if_wpi.c hw = letoh32(sc->shared->next);
hw 1390 dev/pci/if_wpi.c while (sc->rxq.cur != hw) {
hw 1483 dev/pci/if_wpi.c hw = (hw == 0) ? WPI_RX_RING_COUNT - 1 : hw - 1;
hw 1484 dev/pci/if_wpi.c WPI_WRITE(sc, WPI_RX_WIDX, hw & ~7);
hw 2757 dev/pci/if_wpi.c uint32_t rev, hw;
hw 2760 dev/pci/if_wpi.c hw = WPI_READ(sc, WPI_HWCONFIG);
hw 2765 dev/pci/if_wpi.c hw |= WPI_HW_ALM_MB;
hw 2767 dev/pci/if_wpi.c hw |= WPI_HW_ALM_MM;
hw 2770 dev/pci/if_wpi.c hw |= WPI_HW_SKU_MRC;
hw 2772 dev/pci/if_wpi.c hw &= ~WPI_HW_REV_D;
hw 2774 dev/pci/if_wpi.c hw |= WPI_HW_REV_D;
hw 2777 dev/pci/if_wpi.c hw |= WPI_HW_TYPE_B;
hw 2779 dev/pci/if_wpi.c DPRINTF(("setting h/w config %x\n", hw));
hw 2780 dev/pci/if_wpi.c WPI_WRITE(sc, WPI_HWCONFIG, hw);
hw 67 dev/pci/ixgb_ee.c static uint16_t ixgb_shift_in_bits(struct ixgb_hw *hw);
hw 69 dev/pci/ixgb_ee.c static void ixgb_shift_out_bits(struct ixgb_hw *hw, uint16_t data,
hw 71 dev/pci/ixgb_ee.c static void ixgb_standby_eeprom(struct ixgb_hw *hw);
hw 73 dev/pci/ixgb_ee.c static boolean_t ixgb_wait_eeprom_command(struct ixgb_hw *hw);
hw 75 dev/pci/ixgb_ee.c static void ixgb_cleanup_eeprom(struct ixgb_hw *hw);
hw 84 dev/pci/ixgb_ee.c ixgb_raise_clock(struct ixgb_hw *hw, uint32_t *eecd_reg)
hw 89 dev/pci/ixgb_ee.c IXGB_WRITE_REG(hw, EECD, *eecd_reg);
hw 101 dev/pci/ixgb_ee.c ixgb_lower_clock(struct ixgb_hw *hw, uint32_t *eecd_reg)
hw 106 dev/pci/ixgb_ee.c IXGB_WRITE_REG(hw, EECD, *eecd_reg);
hw 119 dev/pci/ixgb_ee.c ixgb_shift_out_bits(struct ixgb_hw *hw, uint16_t data, uint16_t count)
hw 128 dev/pci/ixgb_ee.c eecd_reg = IXGB_READ_REG(hw, EECD);
hw 141 dev/pci/ixgb_ee.c IXGB_WRITE_REG(hw, EECD, eecd_reg);
hw 145 dev/pci/ixgb_ee.c ixgb_raise_clock(hw, &eecd_reg);
hw 146 dev/pci/ixgb_ee.c ixgb_lower_clock(hw, &eecd_reg);
hw 154 dev/pci/ixgb_ee.c IXGB_WRITE_REG(hw, EECD, eecd_reg);
hw 164 dev/pci/ixgb_ee.c ixgb_shift_in_bits(struct ixgb_hw *hw)
hw 176 dev/pci/ixgb_ee.c eecd_reg = IXGB_READ_REG(hw, EECD);
hw 183 dev/pci/ixgb_ee.c ixgb_raise_clock(hw, &eecd_reg);
hw 185 dev/pci/ixgb_ee.c eecd_reg = IXGB_READ_REG(hw, EECD);
hw 191 dev/pci/ixgb_ee.c ixgb_lower_clock(hw, &eecd_reg);
hw 206 dev/pci/ixgb_ee.c ixgb_setup_eeprom(struct ixgb_hw *hw)
hw 210 dev/pci/ixgb_ee.c eecd_reg = IXGB_READ_REG(hw, EECD);
hw 214 dev/pci/ixgb_ee.c IXGB_WRITE_REG(hw, EECD, eecd_reg);
hw 218 dev/pci/ixgb_ee.c IXGB_WRITE_REG(hw, EECD, eecd_reg);
hw 228 dev/pci/ixgb_ee.c ixgb_standby_eeprom(struct ixgb_hw *hw)
hw 232 dev/pci/ixgb_ee.c eecd_reg = IXGB_READ_REG(hw, EECD);
hw 236 dev/pci/ixgb_ee.c IXGB_WRITE_REG(hw, EECD, eecd_reg);
hw 241 dev/pci/ixgb_ee.c IXGB_WRITE_REG(hw, EECD, eecd_reg);
hw 246 dev/pci/ixgb_ee.c IXGB_WRITE_REG(hw, EECD, eecd_reg);
hw 251 dev/pci/ixgb_ee.c IXGB_WRITE_REG(hw, EECD, eecd_reg);
hw 262 dev/pci/ixgb_ee.c ixgb_clock_eeprom(struct ixgb_hw *hw)
hw 266 dev/pci/ixgb_ee.c eecd_reg = IXGB_READ_REG(hw, EECD);
hw 270 dev/pci/ixgb_ee.c IXGB_WRITE_REG(hw, EECD, eecd_reg);
hw 275 dev/pci/ixgb_ee.c IXGB_WRITE_REG(hw, EECD, eecd_reg);
hw 286 dev/pci/ixgb_ee.c ixgb_cleanup_eeprom(struct ixgb_hw *hw)
hw 290 dev/pci/ixgb_ee.c eecd_reg = IXGB_READ_REG(hw, EECD);
hw 294 dev/pci/ixgb_ee.c IXGB_WRITE_REG(hw, EECD, eecd_reg);
hw 296 dev/pci/ixgb_ee.c ixgb_clock_eeprom(hw);
hw 312 dev/pci/ixgb_ee.c ixgb_wait_eeprom_command(struct ixgb_hw *hw)
hw 319 dev/pci/ixgb_ee.c ixgb_standby_eeprom(hw);
hw 325 dev/pci/ixgb_ee.c eecd_reg = IXGB_READ_REG(hw, EECD);
hw 350 dev/pci/ixgb_ee.c ixgb_validate_eeprom_checksum(struct ixgb_hw *hw)
hw 356 dev/pci/ixgb_ee.c checksum += ixgb_read_eeprom(hw, i);
hw 373 dev/pci/ixgb_ee.c ixgb_update_eeprom_checksum(struct ixgb_hw *hw)
hw 379 dev/pci/ixgb_ee.c checksum += ixgb_read_eeprom(hw, i);
hw 383 dev/pci/ixgb_ee.c ixgb_write_eeprom(hw, EEPROM_CHECKSUM_REG, checksum);
hw 399 dev/pci/ixgb_ee.c ixgb_write_eeprom(struct ixgb_hw *hw, uint16_t offset, uint16_t data)
hw 401 dev/pci/ixgb_ee.c struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
hw 404 dev/pci/ixgb_ee.c ixgb_setup_eeprom(hw);
hw 409 dev/pci/ixgb_ee.c ixgb_shift_out_bits(hw, EEPROM_EWEN_OPCODE, 5);
hw 410 dev/pci/ixgb_ee.c ixgb_shift_out_bits(hw, 0, 4);
hw 413 dev/pci/ixgb_ee.c ixgb_standby_eeprom(hw);
hw 416 dev/pci/ixgb_ee.c ixgb_shift_out_bits(hw, EEPROM_WRITE_OPCODE, 3);
hw 417 dev/pci/ixgb_ee.c ixgb_shift_out_bits(hw, offset, 6);
hw 420 dev/pci/ixgb_ee.c ixgb_shift_out_bits(hw, data, 16);
hw 422 dev/pci/ixgb_ee.c ixgb_wait_eeprom_command(hw);
hw 425 dev/pci/ixgb_ee.c ixgb_standby_eeprom(hw);
hw 430 dev/pci/ixgb_ee.c ixgb_shift_out_bits(hw, EEPROM_EWDS_OPCODE, 5);
hw 431 dev/pci/ixgb_ee.c ixgb_shift_out_bits(hw, 0, 4);
hw 434 dev/pci/ixgb_ee.c ixgb_cleanup_eeprom(hw);
hw 452 dev/pci/ixgb_ee.c ixgb_read_eeprom(struct ixgb_hw *hw, uint16_t offset)
hw 457 dev/pci/ixgb_ee.c ixgb_setup_eeprom(hw);
hw 460 dev/pci/ixgb_ee.c ixgb_shift_out_bits(hw, EEPROM_READ_OPCODE, 3);
hw 464 dev/pci/ixgb_ee.c ixgb_shift_out_bits(hw, offset, 6);
hw 467 dev/pci/ixgb_ee.c data = ixgb_shift_in_bits(hw);
hw 470 dev/pci/ixgb_ee.c ixgb_standby_eeprom(hw);
hw 486 dev/pci/ixgb_ee.c ixgb_get_eeprom_data(struct ixgb_hw *hw)
hw 494 dev/pci/ixgb_ee.c ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
hw 500 dev/pci/ixgb_ee.c ee_data = ixgb_read_eeprom(hw, i);
hw 502 dev/pci/ixgb_ee.c hw->eeprom[i] = le16_to_cpu(ee_data);
hw 533 dev/pci/ixgb_ee.c ixgb_check_and_get_eeprom_data(struct ixgb_hw *hw)
hw 535 dev/pci/ixgb_ee.c struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
hw 541 dev/pci/ixgb_ee.c return ixgb_get_eeprom_data(hw);
hw 555 dev/pci/ixgb_ee.c ixgb_get_eeprom_word(struct ixgb_hw *hw, uint16_t index)
hw 559 dev/pci/ixgb_ee.c (ixgb_check_and_get_eeprom_data(hw) == TRUE)) {
hw 560 dev/pci/ixgb_ee.c return (hw->eeprom[index]);
hw 575 dev/pci/ixgb_ee.c ixgb_get_ee_mac_addr(struct ixgb_hw *hw, uint8_t *mac_addr)
hw 578 dev/pci/ixgb_ee.c struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
hw 582 dev/pci/ixgb_ee.c if(ixgb_check_and_get_eeprom_data(hw) == TRUE) {
hw 600 dev/pci/ixgb_ee.c ixgb_get_ee_pba_number(struct ixgb_hw *hw)
hw 602 dev/pci/ixgb_ee.c if(ixgb_check_and_get_eeprom_data(hw) == TRUE)
hw 603 dev/pci/ixgb_ee.c return (le16_to_cpu(hw->eeprom[EEPROM_PBA_1_2_REG])
hw 604 dev/pci/ixgb_ee.c | (le16_to_cpu(hw->eeprom[EEPROM_PBA_3_4_REG]) << 16));
hw 619 dev/pci/ixgb_ee.c ixgb_get_ee_device_id(struct ixgb_hw *hw)
hw 621 dev/pci/ixgb_ee.c struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
hw 623 dev/pci/ixgb_ee.c if(ixgb_check_and_get_eeprom_data(hw) == TRUE)
hw 105 dev/pci/ixgb_ee.h uint16_t ixgb_read_eeprom(struct ixgb_hw *hw, uint16_t reg);
hw 107 dev/pci/ixgb_ee.h boolean_t ixgb_validate_eeprom_checksum(struct ixgb_hw *hw);
hw 109 dev/pci/ixgb_ee.h void ixgb_update_eeprom_checksum(struct ixgb_hw *hw);
hw 111 dev/pci/ixgb_ee.h void ixgb_write_eeprom(struct ixgb_hw *hw, uint16_t reg, uint16_t data);
hw 72 dev/pci/ixgb_hw.c static uint32_t ixgb_hash_mc_addr(struct ixgb_hw *hw, uint8_t *mc_addr);
hw 74 dev/pci/ixgb_hw.c static void ixgb_mta_set(struct ixgb_hw *hw, uint32_t hash_value);
hw 76 dev/pci/ixgb_hw.c static void ixgb_get_bus_info(struct ixgb_hw *hw);
hw 78 dev/pci/ixgb_hw.c static boolean_t ixgb_link_reset(struct ixgb_hw *hw);
hw 80 dev/pci/ixgb_hw.c static void ixgb_optics_reset(struct ixgb_hw *hw);
hw 82 dev/pci/ixgb_hw.c static ixgb_phy_type ixgb_identify_phy(struct ixgb_hw *hw);
hw 84 dev/pci/ixgb_hw.c uint32_t ixgb_mac_reset(struct ixgb_hw *hw);
hw 87 dev/pci/ixgb_hw.c ixgb_mac_reset(struct ixgb_hw *hw)
hw 102 dev/pci/ixgb_hw.c IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg);
hw 104 dev/pci/ixgb_hw.c IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
hw 109 dev/pci/ixgb_hw.c ctrl_reg = IXGB_READ_REG(hw, CTRL0);
hw 115 dev/pci/ixgb_hw.c if(hw->phy_type == ixgb_phy_type_txn17401) {
hw 116 dev/pci/ixgb_hw.c ixgb_optics_reset(hw);
hw 128 dev/pci/ixgb_hw.c ixgb_adapter_stop(struct ixgb_hw *hw)
hw 137 dev/pci/ixgb_hw.c if(hw->adapter_stopped) {
hw 144 dev/pci/ixgb_hw.c hw->adapter_stopped = TRUE;
hw 148 dev/pci/ixgb_hw.c IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF);
hw 153 dev/pci/ixgb_hw.c IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN);
hw 154 dev/pci/ixgb_hw.c IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN);
hw 163 dev/pci/ixgb_hw.c ctrl_reg = ixgb_mac_reset(hw);
hw 167 dev/pci/ixgb_hw.c IXGB_WRITE_REG(hw, IMC, 0xffffffff);
hw 170 dev/pci/ixgb_hw.c icr_reg = IXGB_READ_REG(hw, ICR);
hw 185 dev/pci/ixgb_hw.c ixgb_identify_xpak_vendor(struct ixgb_hw *hw)
hw 198 dev/pci/ixgb_hw.c ixgb_read_phy_reg(hw, MDIO_PMA_PMD_XPAK_VENDOR_NAME + i,
hw 225 dev/pci/ixgb_hw.c ixgb_identify_phy(struct ixgb_hw *hw)
hw 233 dev/pci/ixgb_hw.c switch(hw->device_id) {
hw 243 dev/pci/ixgb_hw.c xpak_vendor = ixgb_identify_xpak_vendor(hw);
hw 260 dev/pci/ixgb_hw.c xpak_vendor = ixgb_identify_xpak_vendor(hw);
hw 297 dev/pci/ixgb_hw.c ixgb_init_hw(struct ixgb_hw *hw)
hw 311 dev/pci/ixgb_hw.c ctrl_reg = ixgb_mac_reset(hw);
hw 316 dev/pci/ixgb_hw.c IXGB_WRITE_REG_IO(hw, CTRL1, IXGB_CTRL1_EE_RST);
hw 318 dev/pci/ixgb_hw.c IXGB_WRITE_REG(hw, CTRL1, IXGB_CTRL1_EE_RST);
hw 324 dev/pci/ixgb_hw.c if(ixgb_get_eeprom_data(hw) == FALSE) {
hw 329 dev/pci/ixgb_hw.c hw->device_id = ixgb_get_ee_device_id(hw);
hw 330 dev/pci/ixgb_hw.c hw->phy_type = ixgb_identify_phy(hw);
hw 334 dev/pci/ixgb_hw.c ixgb_init_rx_addrs(hw);
hw 340 dev/pci/ixgb_hw.c if(!mac_addr_valid(hw->curr_mac_addr)) {
hw 346 dev/pci/ixgb_hw.c hw->adapter_stopped = FALSE;
hw 349 dev/pci/ixgb_hw.c ixgb_get_bus_info(hw);
hw 354 dev/pci/ixgb_hw.c IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
hw 357 dev/pci/ixgb_hw.c ixgb_clear_vfta(hw);
hw 360 dev/pci/ixgb_hw.c ixgb_clear_hw_cntrs(hw);
hw 363 dev/pci/ixgb_hw.c status = ixgb_setup_fc(hw);
hw 366 dev/pci/ixgb_hw.c ixgb_check_for_link(hw);
hw 381 dev/pci/ixgb_hw.c ixgb_init_rx_addrs(struct ixgb_hw *hw)
hw 392 dev/pci/ixgb_hw.c if(!mac_addr_valid(hw->curr_mac_addr)) {
hw 395 dev/pci/ixgb_hw.c ixgb_get_ee_mac_addr(hw, hw->curr_mac_addr);
hw 398 dev/pci/ixgb_hw.c hw->curr_mac_addr[0], hw->curr_mac_addr[1],
hw 399 dev/pci/ixgb_hw.c hw->curr_mac_addr[2]);
hw 400 dev/pci/ixgb_hw.c DEBUGOUT3("%.2X %.2X %.2X\n", hw->curr_mac_addr[3],
hw 401 dev/pci/ixgb_hw.c hw->curr_mac_addr[4], hw->curr_mac_addr[5]);
hw 407 dev/pci/ixgb_hw.c hw->curr_mac_addr[0], hw->curr_mac_addr[1],
hw 408 dev/pci/ixgb_hw.c hw->curr_mac_addr[2]);
hw 409 dev/pci/ixgb_hw.c DEBUGOUT3("%.2X %.2X %.2X\n", hw->curr_mac_addr[3],
hw 410 dev/pci/ixgb_hw.c hw->curr_mac_addr[4], hw->curr_mac_addr[5]);
hw 412 dev/pci/ixgb_hw.c ixgb_rar_set(hw, hw->curr_mac_addr, 0);
hw 418 dev/pci/ixgb_hw.c IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
hw 419 dev/pci/ixgb_hw.c IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
hw 439 dev/pci/ixgb_hw.c ixgb_mc_addr_list_update(struct ixgb_hw *hw, uint8_t *mc_addr_list,
hw 450 dev/pci/ixgb_hw.c hw->num_mc_addrs = mc_addr_count;
hw 455 dev/pci/ixgb_hw.c IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
hw 456 dev/pci/ixgb_hw.c IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
hw 462 dev/pci/ixgb_hw.c IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
hw 479 dev/pci/ixgb_hw.c ixgb_rar_set(hw,
hw 487 dev/pci/ixgb_hw.c ixgb_hash_mc_addr(hw,
hw 495 dev/pci/ixgb_hw.c ixgb_mta_set(hw, hash_value);
hw 513 dev/pci/ixgb_hw.c ixgb_hash_mc_addr(struct ixgb_hw *hw, uint8_t *mc_addr)
hw 521 dev/pci/ixgb_hw.c switch(hw->mc_filter_type) {
hw 561 dev/pci/ixgb_hw.c ixgb_mta_set(struct ixgb_hw *hw, uint32_t hash_value)
hw 575 dev/pci/ixgb_hw.c mta_reg = IXGB_READ_REG_ARRAY(hw, MTA, hash_reg);
hw 577 dev/pci/ixgb_hw.c IXGB_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta_reg);
hw 589 dev/pci/ixgb_hw.c ixgb_rar_set(struct ixgb_hw *hw, uint8_t *addr, uint32_t index)
hw 606 dev/pci/ixgb_hw.c IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
hw 607 dev/pci/ixgb_hw.c IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
hw 619 dev/pci/ixgb_hw.c ixgb_write_vfta(struct ixgb_hw *hw, uint32_t offset, uint32_t value)
hw 621 dev/pci/ixgb_hw.c IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value);
hw 631 dev/pci/ixgb_hw.c ixgb_clear_vfta(struct ixgb_hw *hw)
hw 636 dev/pci/ixgb_hw.c IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
hw 647 dev/pci/ixgb_hw.c ixgb_setup_fc(struct ixgb_hw *hw)
hw 656 dev/pci/ixgb_hw.c ctrl_reg = IXGB_READ_REG(hw, CTRL0);
hw 669 dev/pci/ixgb_hw.c switch(hw->fc.type) {
hw 682 dev/pci/ixgb_hw.c pap_reg = hw->fc.pause_time;
hw 688 dev/pci/ixgb_hw.c pap_reg = hw->fc.pause_time;
hw 698 dev/pci/ixgb_hw.c IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
hw 701 dev/pci/ixgb_hw.c IXGB_WRITE_REG(hw, PAP, pap_reg);
hw 709 dev/pci/ixgb_hw.c if(!(hw->fc.type & ixgb_fc_tx_pause)) {
hw 710 dev/pci/ixgb_hw.c IXGB_WRITE_REG(hw, FCRTL, 0);
hw 711 dev/pci/ixgb_hw.c IXGB_WRITE_REG(hw, FCRTH, 0);
hw 716 dev/pci/ixgb_hw.c if(hw->fc.send_xon) {
hw 717 dev/pci/ixgb_hw.c IXGB_WRITE_REG(hw, FCRTL,
hw 718 dev/pci/ixgb_hw.c (hw->fc.low_water | IXGB_FCRTL_XONE));
hw 720 dev/pci/ixgb_hw.c IXGB_WRITE_REG(hw, FCRTL, hw->fc.low_water);
hw 722 dev/pci/ixgb_hw.c IXGB_WRITE_REG(hw, FCRTH, hw->fc.high_water);
hw 743 dev/pci/ixgb_hw.c ixgb_read_phy_reg(struct ixgb_hw *hw, uint32_t reg_address,
hw 760 dev/pci/ixgb_hw.c IXGB_WRITE_REG(hw, MSCA, command);
hw 772 dev/pci/ixgb_hw.c command = IXGB_READ_REG(hw, MSCA);
hw 786 dev/pci/ixgb_hw.c IXGB_WRITE_REG(hw, MSCA, command);
hw 798 dev/pci/ixgb_hw.c command = IXGB_READ_REG(hw, MSCA);
hw 808 dev/pci/ixgb_hw.c data = IXGB_READ_REG(hw, MSRWD);
hw 831 dev/pci/ixgb_hw.c ixgb_write_phy_reg(struct ixgb_hw *hw, uint32_t reg_address,
hw 842 dev/pci/ixgb_hw.c IXGB_WRITE_REG(hw, MSRWD, (uint32_t)data);
hw 850 dev/pci/ixgb_hw.c IXGB_WRITE_REG(hw, MSCA, command);
hw 862 dev/pci/ixgb_hw.c command = IXGB_READ_REG(hw, MSCA);
hw 876 dev/pci/ixgb_hw.c IXGB_WRITE_REG(hw, MSCA, command);
hw 888 dev/pci/ixgb_hw.c command = IXGB_READ_REG(hw, MSCA);
hw 907 dev/pci/ixgb_hw.c ixgb_check_for_link(struct ixgb_hw *hw)
hw 914 dev/pci/ixgb_hw.c xpcss_reg = IXGB_READ_REG(hw, XPCSS);
hw 915 dev/pci/ixgb_hw.c status_reg = IXGB_READ_REG(hw, STATUS);
hw 919 dev/pci/ixgb_hw.c hw->link_up = TRUE;
hw 923 dev/pci/ixgb_hw.c hw->link_up = ixgb_link_reset(hw);
hw 929 dev/pci/ixgb_hw.c hw->link_up = ixgb_link_reset(hw);
hw 944 dev/pci/ixgb_hw.c ixgb_check_for_bad_link(struct ixgb_hw *hw)
hw 949 dev/pci/ixgb_hw.c if(hw->phy_type == ixgb_phy_type_txn17401) {
hw 950 dev/pci/ixgb_hw.c newLFC = IXGB_READ_REG(hw, LFC);
hw 951 dev/pci/ixgb_hw.c newRFC = IXGB_READ_REG(hw, RFC);
hw 952 dev/pci/ixgb_hw.c if((hw->lastLFC + 250 < newLFC) || (hw->lastRFC + 250 < newRFC)) {
hw 956 dev/pci/ixgb_hw.c hw->lastLFC = newLFC;
hw 957 dev/pci/ixgb_hw.c hw->lastRFC = newRFC;
hw 969 dev/pci/ixgb_hw.c ixgb_clear_hw_cntrs(struct ixgb_hw *hw)
hw 976 dev/pci/ixgb_hw.c if(hw->adapter_stopped) {
hw 981 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, TPRL);
hw 982 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, TPRH);
hw 983 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, GPRCL);
hw 984 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, GPRCH);
hw 985 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, BPRCL);
hw 986 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, BPRCH);
hw 987 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, MPRCL);
hw 988 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, MPRCH);
hw 989 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, UPRCL);
hw 990 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, UPRCH);
hw 991 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, VPRCL);
hw 992 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, VPRCH);
hw 993 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, JPRCL);
hw 994 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, JPRCH);
hw 995 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, GORCL);
hw 996 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, GORCH);
hw 997 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, TORL);
hw 998 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, TORH);
hw 999 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, RNBC);
hw 1000 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, RUC);
hw 1001 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, ROC);
hw 1002 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, RLEC);
hw 1003 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, CRCERRS);
hw 1004 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, ICBC);
hw 1005 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, ECBC);
hw 1006 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, MPC);
hw 1007 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, TPTL);
hw 1008 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, TPTH);
hw 1009 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, GPTCL);
hw 1010 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, GPTCH);
hw 1011 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, BPTCL);
hw 1012 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, BPTCH);
hw 1013 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, MPTCL);
hw 1014 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, MPTCH);
hw 1015 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, UPTCL);
hw 1016 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, UPTCH);
hw 1017 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, VPTCL);
hw 1018 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, VPTCH);
hw 1019 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, JPTCL);
hw 1020 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, JPTCH);
hw 1021 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, GOTCL);
hw 1022 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, GOTCH);
hw 1023 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, TOTL);
hw 1024 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, TOTH);
hw 1025 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, DC);
hw 1026 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, PLT64C);
hw 1027 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, TSCTC);
hw 1028 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, TSCTFC);
hw 1029 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, IBIC);
hw 1030 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, RFC);
hw 1031 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, LFC);
hw 1032 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, PFRC);
hw 1033 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, PFTC);
hw 1034 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, MCFRC);
hw 1035 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, MCFTC);
hw 1036 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, XONRXC);
hw 1037 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, XONTXC);
hw 1038 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, XOFFRXC);
hw 1039 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, XOFFTXC);
hw 1040 dev/pci/ixgb_hw.c temp_reg = IXGB_READ_REG(hw, RJC);
hw 1050 dev/pci/ixgb_hw.c ixgb_led_on(struct ixgb_hw *hw)
hw 1052 dev/pci/ixgb_hw.c uint32_t ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
hw 1056 dev/pci/ixgb_hw.c IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
hw 1066 dev/pci/ixgb_hw.c ixgb_led_off(struct ixgb_hw *hw)
hw 1068 dev/pci/ixgb_hw.c uint32_t ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
hw 1072 dev/pci/ixgb_hw.c IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
hw 1082 dev/pci/ixgb_hw.c ixgb_get_bus_info(struct ixgb_hw *hw)
hw 1086 dev/pci/ixgb_hw.c status_reg = IXGB_READ_REG(hw, STATUS);
hw 1088 dev/pci/ixgb_hw.c hw->bus.type =
hw 1092 dev/pci/ixgb_hw.c if(hw->bus.type == ixgb_bus_type_pci) {
hw 1093 dev/pci/ixgb_hw.c hw->bus.speed =
hw 1099 dev/pci/ixgb_hw.c hw->bus.speed = ixgb_bus_speed_66;
hw 1102 dev/pci/ixgb_hw.c hw->bus.speed = ixgb_bus_speed_100;
hw 1105 dev/pci/ixgb_hw.c hw->bus.speed = ixgb_bus_speed_133;
hw 1108 dev/pci/ixgb_hw.c hw->bus.speed = ixgb_bus_speed_reserved;
hw 1113 dev/pci/ixgb_hw.c hw->bus.width =
hw 1163 dev/pci/ixgb_hw.c ixgb_link_reset(struct ixgb_hw *hw)
hw 1171 dev/pci/ixgb_hw.c IXGB_WRITE_REG(hw, CTRL0,
hw 1172 dev/pci/ixgb_hw.c IXGB_READ_REG(hw, CTRL0) | IXGB_CTRL0_LRST);
hw 1178 dev/pci/ixgb_hw.c ((IXGB_READ_REG(hw, STATUS) & IXGB_STATUS_LU) &&
hw 1179 dev/pci/ixgb_hw.c (IXGB_READ_REG(hw, XPCSS) &
hw 1194 dev/pci/ixgb_hw.c ixgb_optics_reset(struct ixgb_hw *hw)
hw 1196 dev/pci/ixgb_hw.c if(hw->phy_type == ixgb_phy_type_txn17401) {
hw 1199 dev/pci/ixgb_hw.c ixgb_write_phy_reg(hw,
hw 1205 dev/pci/ixgb_hw.c mdio_reg = ixgb_read_phy_reg(hw,
hw 823 dev/pci/ixgb_hw.h extern boolean_t ixgb_adapter_stop(struct ixgb_hw *hw);
hw 824 dev/pci/ixgb_hw.h extern boolean_t ixgb_init_hw(struct ixgb_hw *hw);
hw 825 dev/pci/ixgb_hw.h extern boolean_t ixgb_adapter_start(struct ixgb_hw *hw);
hw 826 dev/pci/ixgb_hw.h extern void ixgb_check_for_link(struct ixgb_hw *hw);
hw 827 dev/pci/ixgb_hw.h extern boolean_t ixgb_check_for_bad_link(struct ixgb_hw *hw);
hw 828 dev/pci/ixgb_hw.h extern void ixgb_rar_set(struct ixgb_hw *hw, uint8_t *addr, uint32_t index);
hw 829 dev/pci/ixgb_hw.h extern void ixgb_init_rx_addrs(struct ixgb_hw *hw);
hw 830 dev/pci/ixgb_hw.h extern boolean_t ixgb_setup_fc(struct ixgb_hw *hw);
hw 831 dev/pci/ixgb_hw.h extern void ixgb_clear_hw_cntrs(struct ixgb_hw *hw);
hw 834 dev/pci/ixgb_hw.h extern uint16_t ixgb_read_phy_reg(struct ixgb_hw *hw, uint32_t reg_addr,
hw 837 dev/pci/ixgb_hw.h extern void ixgb_write_phy_reg(struct ixgb_hw *hw, uint32_t reg_addr,
hw 843 dev/pci/ixgb_hw.h extern void ixgb_mc_addr_list_update(struct ixgb_hw *hw, uint8_t *mc_addr_list,
hw 847 dev/pci/ixgb_hw.h extern void ixgb_write_vfta(struct ixgb_hw *hw, uint32_t offset,
hw 850 dev/pci/ixgb_hw.h extern void ixgb_clear_vfta(struct ixgb_hw *hw);
hw 853 dev/pci/ixgb_hw.h void ixgb_get_ee_mac_addr(struct ixgb_hw *hw, uint8_t *mac_addr);
hw 854 dev/pci/ixgb_hw.h uint32_t ixgb_get_ee_pba_number(struct ixgb_hw *hw);
hw 855 dev/pci/ixgb_hw.h uint16_t ixgb_get_ee_device_id(struct ixgb_hw *hw);
hw 856 dev/pci/ixgb_hw.h boolean_t ixgb_get_eeprom_data(struct ixgb_hw *hw);
hw 857 dev/pci/ixgb_hw.h uint16_t ixgb_get_eeprom_word(struct ixgb_hw *hw, uint16_t index);
hw 860 dev/pci/ixgb_hw.h void ixgb_led_on(struct ixgb_hw *hw);
hw 861 dev/pci/ixgb_hw.h void ixgb_led_off(struct ixgb_hw *hw);
hw 862 dev/pci/ixgb_hw.h void ixgb_write_pci_cfg(struct ixgb_hw *hw, uint32_t reg, uint16_t *value);
hw 197 dev/sbus/bpp.c struct hwstate *hw = &dsc->sc_hwstate;
hw 200 dev/sbus/bpp.c hw->hw_hcr = bus_space_read_2(sc->sc_bustag, h, L64854_REG_HCR);
hw 201 dev/sbus/bpp.c hw->hw_ocr = bus_space_read_2(sc->sc_bustag, h, L64854_REG_OCR);
hw 202 dev/sbus/bpp.c hw->hw_tcr = bus_space_read_1(sc->sc_bustag, h, L64854_REG_TCR);
hw 203 dev/sbus/bpp.c hw->hw_or = bus_space_read_1(sc->sc_bustag, h, L64854_REG_OR);
hw 206 dev/sbus/bpp.c hw->hw_hcr, hw->hw_ocr, hw->hw_tcr, hw->hw_or));
hw 208 dev/sbus/bpp.c hw->hw_hcr = ((ack_rate<<BPP_HCR_DSS_SHFT)&BPP_HCR_DSS_MASK)
hw 210 dev/sbus/bpp.c hw->hw_ocr |= BPP_OCR_ACK_OP;
hw 215 dev/sbus/bpp.c bpp_setparams(struct bpp_softc *sc, struct hwstate *hw)
hw 221 dev/sbus/bpp.c bus_space_write_2(t, h, L64854_REG_HCR, hw->hw_hcr);
hw 222 dev/sbus/bpp.c bus_space_write_2(t, h, L64854_REG_OCR, hw->hw_ocr);
hw 223 dev/sbus/bpp.c bus_space_write_1(t, h, L64854_REG_TCR, hw->hw_tcr);
hw 224 dev/sbus/bpp.c bus_space_write_1(t, h, L64854_REG_OR, hw->hw_or);
hw 229 dev/sbus/bpp.c irq |= (hw->hw_irq & BPP_ALLIRP);
hw 232 dev/sbus/bpp.c hw->hw_hcr, hw->hw_ocr, hw->hw_tcr, hw->hw_or, irq));