This source file includes following definitions.
- xilinx_config_t
- api_rx_hdr_t
- api_rx_element_t
- api_tx_hdr_t
- api_tx_element_t
- aft_trc_el_t
- wp_rx_element_t
- xilinx_valid_mtu
- xilinx_dma_buf_bits
- aft_reset_rx_watchdog
- aft_enable_rx_watchdog
- aft_reset_tx_watchdog
- aft_enable_tx_watchdog
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37 #ifndef __IF_SAN_XILINX_H
38 #define __IF_SAN_XILINX_H
39
40 #define XILINX_CHIP_CFG_REG 0x40
41
42 #define XILINX_MCPU_INTERFACE 0x44
43 #define XILINX_MCPU_INTERFACE_ADDR 0x46
44
45 #define XILINX_GLOBAL_INTER_MASK 0x4C
46
47
48 #define XILINX_HDLC_TX_INTR_PENDING_REG 0x50
49 #define XILINX_HDLC_RX_INTR_PENDING_REG 0x54
50
51 enum {
52 WP_FIFO_ERROR_BIT,
53 WP_CRC_ERROR_BIT,
54 WP_ABORT_ERROR_BIT,
55 };
56
57 #define WP_MAX_FIFO_FRAMES 7
58
59 #define XILINX_DMA_TX_INTR_PENDING_REG 0x58
60 #define XILINX_DMA_RX_INTR_PENDING_REG 0x5C
61
62 #define XILINX_TIMESLOT_HDLC_CHAN_REG 0x60
63
64 #define AFT_T3_RXTX_ADDR_SELECT_REG 0x60
65
66 #define XILINX_CURRENT_TIMESLOT_MASK 0x00001F00
67 #define XILINX_CURRENT_TIMESLOT_SHIFT 8
68
69 #define XILINX_HDLC_CONTROL_REG 0x64
70 #define XILINX_HDLC_ADDR_REG 0x68
71
72 #define XILINX_CONTROL_RAM_ACCESS_BUF 0x6C
73
74
75
76 #define XILINX_DMA_CONTROL_REG 0x70
77 #define XILINX_DMA_TX_STATUS_REG 0x74
78 #define AFT_TE3_TX_WDT_CTRL_REG 0x74
79 #define XILINX_DMA_RX_STATUS_REG 0x78
80 #define AFT_TE3_RX_WDT_CTRL_REG 0x78
81 #define XILINX_DMA_DATA_REG 0x7C
82
83 #define AFT_TE3_CRNT_DMA_DESC_ADDR_REG 0x80
84
85 #define XILINX_TxDMA_DESCRIPTOR_LO 0x100
86 #define XILINX_TxDMA_DESCRIPTOR_HI 0x104
87 #define XILINX_RxDMA_DESCRIPTOR_LO 0x108
88 #define XILINX_RxDMA_DESCRIPTOR_HI 0x10C
89
90
91 #define INTERFACE_TYPE_T1_E1_BIT 0
92 #define INTERFACE_TYPE_T3_E3_BIT 0
93
94 #define XILINX_RED_LED 1
95 #define AFT_T3_HDLC_TRANS_MODE 1
96 #define FRONT_END_FRAME_FLAG_ENABLE_BIT 2
97 #define AFT_T3_CLOCK_MODE 2
98 #define SIGNALLING_ENABLE_BIT 3
99 #define FRONT_END_RESET_BIT 4
100 #define CHIP_RESET_BIT 5
101 #define HDLC_CORE_RESET_BIT 6
102 #define HDLC_CORE_READY_FLAG_BIT 7
103 #define GLOBAL_INTR_ENABLE_BIT 8
104 #define ERROR_INTR_ENABLE_BIT 9
105 #define FRONT_END_INTR_ENABLE_BIT 10
106
107 #define CHIP_ERROR_MASK 0x00FF0000
108
109 #define AFT_TE3_TX_WDT_INTR_PND 26
110 #define AFT_TE3_RX_WDT_INTR_PND 27
111
112 #define FRONT_END_INTR_FLAG 28
113 #define SECURITY_STATUS_FLAG 29
114 #define ERROR_INTR_FLAG 30
115 #define DMA_INTR_FLAG 31
116
117 #define XILINX_GLOBAL_INTER_STATUS 0xD0000000
118
119 #define TIMESLOT_BIT_SHIFT 16
120 #define TIMESLOT_BIT_MASK 0x001F0000
121 #define HDLC_LOGIC_CH_BIT_MASK 0x0000001F
122
123 #define HDLC_LCH_TIMESLOT_MASK 0x001F001F
124
125
126 #define HDLC_RX_CHAN_ENABLE_BIT 0
127 #define HDLC_RX_FRAME_DATA_BIT 1
128 #define HDLC_RC_CHAN_ACTIVE_BIT 2
129 #define HDLC_RX_FRAME_ERROR_BIT 3
130 #define HDLC_RX_FRAME_ABORT_BIT 4
131 #define HDLC_RX_PROT_DISABLE_BIT 16
132 #define HDLC_RX_ADDR_RECOGN_DIS_BIT 17
133 #define HDLC_RX_ADDR_FIELD_DISC_BIT 18
134 #define HDLC_RX_ADDR_SIZE_BIT 19
135 #define HDLC_RX_BRD_ADDR_MATCH_BIT 20
136 #define HDLC_RX_FCS_SIZE_BIT 21
137 #define HDLC_CORE_RX_IDLE_LINE_BIT 22
138 #define HDLC_CODE_RX_ABORT_LINE_BIT 23
139 #define HDLC_TX_CHAN_ENABLE_BIT 24
140 #define HDLC_TX_PROT_DISABLE_BIT 25
141 #define HDLC_TX_ADDR_INSERTION_BIT 26
142 #define HDLC_TX_ADDR_SIZE_BIT 27
143 #define HDLC_TX_FCS_SIZE_BIT 28
144 #define HDLC_TX_FRAME_ABORT_BIT 29
145 #define HDLC_TX_STOP_TX_ON_ABORT_BIT 30
146 #define HDLC_TX_CHANNEL_ACTIVE_BIT 31
147
148
149 #define CONTROL_RAM_DATA_MASK 0x0000001F
150
151
152 #define HDLC_FIFO_BASE_ADDR_SHIFT 16
153 #define HDLC_FIFO_BASE_ADDR_MASK 0x1F
154
155 #define HDLC_FIFO_SIZE_SHIFT 8
156 #define HDLC_FIFO_SIZE_MASK 0x1F
157
158 #define HDLC_FREE_LOGIC_CH 31
159 #define TRANSPARENT_MODE_BIT 31
160
161
162 #define DMA_SIZE_BIT_SHIFT 0
163 #define DMA_FIFO_HI_MARK_BIT_SHIFT 4
164 #define DMA_FIFO_LO_MARK_BIT_SHIFT 8
165 #define DMA_FIFO_T3_MARK_BIT_SHIFT 8
166
167 #define DMA_ACTIVE_CHANNEL_BIT_SHIFT 16
168 #define DMA_ACTIVE_CHANNEL_BIT_MASK 0xFFE0FFFF
169
170 #define DMA_ENGINE_ENABLE_BIT 31
171
172 #define DMA_CHAIN_TE3_MASK 0x0000000F
173
174 #define TxDMA_LO_PC_ADDR_PTR_BIT_MASK 0xFFFFFFFC
175 #define TxDMA_LO_ALIGNMENT_BIT_MASK 0x00000003
176 #define TxDMA_HI_DMA_DATA_LENGTH_MASK 0x000007FF
177
178 #define TxDMA_HI_DMA_PCI_ERROR_MASK 0x00007800
179 #define TxDMA_HI_DMA_PCI_ERROR_M_ABRT 0x00000800
180 #define TxDMA_HI_DMA_PCI_ERROR_T_ABRT 0x00001000
181 #define TxDMA_HI_DMA_PCI_ERROR_DS_TOUT 0x00002000
182 #define TxDMA_HI_DMA_PCI_ERROR_RETRY_TOUT 0x00004000
183
184
185 #define INIT_DMA_FIFO_CMD_BIT 28
186 #define TxDMA_HI_DMA_FRAME_START_BIT 30
187 #define TxDMA_HI_DMA_FRAME_END_BIT 29
188 #define TxDMA_HI_DMA_GO_READY_BIT 31
189 #define DMA_FIFO_BASE_ADDR_SHIFT 20
190 #define DMA_FIFO_BASE_ADDR_MASK 0x1F
191 #define DMA_FIFO_SIZE_SHIFT 15
192 #define DMA_FIFO_SIZE_MASK 0x1F
193
194 #define DMA_FIFO_PARAM_CLEAR_MASK 0xFE007FFF
195
196 #define FIFO_32B 0x00
197 #define FIFO_64B 0x01
198 #define FIFO_128B 0x03
199 #define FIFO_256B 0x07
200 #define FIFO_512B 0x0F
201 #define FIFO_1024B 0x1F
202
203
204 #define RxDMA_LO_PC_ADDR_PTR_BIT_MASK 0xFFFFFFFC
205 #define RxDMA_LO_ALIGNMENT_BIT_MASK 0x00000003
206 #define RxDMA_HI_DMA_DATA_LENGTH_MASK 0x000007FF
207
208 #define RxDMA_HI_DMA_PCI_ERROR_MASK 0x00007800
209 #define RxDMA_HI_DMA_PCI_ERROR_M_ABRT 0x00000800
210 #define RxDMA_HI_DMA_PCI_ERROR_T_ABRT 0x00001000
211 #define RxDMA_HI_DMA_PCI_ERROR_DS_TOUT 0x00002000
212 #define RxDMA_HI_DMA_PCI_ERROR_RETRY_TOUT 0x00004000
213
214
215 #define RxDMA_HI_DMA_COMMAND_BIT_SHIFT 28
216 #define RxDMA_HI_DMA_FRAME_START_BIT 30
217 #define RxDMA_HI_DMA_CRC_ERROR_BIT 25
218 #define RxDMA_HI_DMA_FRAME_ABORT_BIT 26
219 #define RxDMA_HI_DMA_FRAME_END_BIT 29
220 #define RxDMA_HI_DMA_GO_READY_BIT 31
221
222 #define DMA_HI_TE3_INTR_DISABLE_BIT 27
223 #define DMA_HI_TE3_NOT_LAST_FRAME_BIT 24
224
225 #define AFT_TE3_CRNT_TX_DMA_MASK 0x0000000F
226 #define AFT_TE3_CRNT_RX_DMA_MASK 0x000000F0
227 #define AFT_TE3_CRNT_RX_DMA_SHIFT 4
228
229 typedef struct xilinx_config
230 {
231 unsigned long xilinx_chip_cfg_reg;
232 unsigned long xilinx_dma_control_reg;
233 } xilinx_config_t;
234
235
236 #define XILINX_DMA_SIZE 10
237 #define XILINX_DMA_FIFO_UP 8
238 #define XILINX_DMA_FIFO_LO 8
239 #define AFT_T3_DMA_FIFO_MARK 8
240 #define XILINX_DEFLT_ACTIVE_CH 0
241
242 #define MAX_XILINX_TX_DMA_SIZE 0xFFFF
243
244 #define MIN_WP_PRI_MTU 128
245 #define DEFAULT_WP_PRI_MTU 1500
246 #define MAX_WP_PRI_MTU 8188
247
248
249 #define MAX_DATA_SIZE 2000
250 struct sdla_hdlc_api {
251 unsigned int cmd;
252 unsigned short len;
253 unsigned char bar;
254 unsigned short offset;
255 unsigned char data[MAX_DATA_SIZE];
256 };
257
258 #pragma pack(1)
259 typedef struct {
260 unsigned char error_flag;
261 unsigned short time_stamp;
262 unsigned char reserved[13];
263 } api_rx_hdr_t;
264
265 typedef struct {
266 api_rx_hdr_t api_rx_hdr;
267 unsigned char data[1];
268 } api_rx_element_t;
269
270 typedef struct {
271 unsigned char attr;
272 unsigned char misc_Tx_bits;
273 unsigned char reserved[14];
274 } api_tx_hdr_t;
275
276 typedef struct {
277 api_tx_hdr_t api_tx_hdr;
278 unsigned char data[1];
279 } api_tx_element_t;
280 #pragma pack()
281
282 #undef wan_udphdr_data
283 #define wan_udphdr_data wan_udphdr_u.aft.data
284
285
286
287 #define PMC_CONTROL_REG 0x00
288
289
290 #define PMC_RESET_BIT 0
291 #define PMC_CLOCK_SELECT 1
292
293 #define LED_CONTROL_REG 0x01
294
295 #define JP8_VALUE 0x02
296 #define JP7_VALUE 0x01
297 #define SW0_VALUE 0x04
298 #define SW1_VALUE 0x08
299
300
301 #define SECURITY_CPLD_REG 0x09
302
303 #define SECURITY_CPLD_MASK 0x03
304 #define SECURITY_CPLD_SHIFT 0x02
305
306 #define SECURITY_1LINE_UNCH 0x00
307 #define SECURITY_1LINE_CH 0x01
308 #define SECURITY_2LINE_UNCH 0x02
309 #define SECURITY_2LINE_CH 0x03
310
311
312
313 #define WRITE_DEF_SECTOR_DSBL 0x01
314 #define FRONT_END_TYPE_MASK 0x38
315
316 #define BIT_DEV_ADDR_CLEAR 0x600
317 #define BIT_DEV_ADDR_CPLD 0x200
318
319 #define MEMORY_TYPE_SRAM 0x00
320 #define MEMORY_TYPE_FLASH 0x01
321 #define MASK_MEMORY_TYPE_SRAM 0x10
322 #define MASK_MEMORY_TYPE_FLASH 0x20
323
324 #define BIT_A18_SECTOR_SA4_SA7 0x20
325 #define USER_SECTOR_START_ADDR 0x40000
326
327 #define MAX_TRACE_QUEUE 100
328
329 #define TX_DMA_BUF_INIT 0
330
331 #define MAX_TRACE_BUFFER (MAX_LGTH_UDP_MGNT_PKT - \
332 sizeof(iphdr_t) - \
333 sizeof(udphdr_t) - \
334 sizeof(wan_mgmt_t) - \
335 sizeof(wan_trace_info_t) - \
336 sizeof(wan_cmd_t))
337
338 enum {
339 ROUTER_UP_TIME = 0x50,
340 ENABLE_TRACING,
341 DISABLE_TRACING,
342 GET_TRACE_INFO,
343 READ_CODE_VERSION,
344 FLUSH_OPERATIONAL_STATS,
345 OPERATIONAL_STATS,
346 READ_OPERATIONAL_STATS,
347 READ_CONFIGURATION,
348 COMMS_ERROR_STATS_STRUCT,
349 AFT_LINK_STATUS
350 };
351
352 #define UDPMGMT_SIGNATURE "AFTPIPEA"
353
354
355 typedef struct {
356 unsigned char flag;
357 unsigned short length;
358 unsigned char rsrv0[2];
359 unsigned char attr;
360 unsigned short tmstamp;
361 unsigned char rsrv1[4];
362 unsigned long offset;
363 } aft_trc_el_t;
364
365
366 typedef struct wp_rx_element
367 {
368 unsigned long dma_addr;
369 unsigned int reg;
370 unsigned int align;
371 unsigned char pkt_error;
372 }wp_rx_element_t;
373
374
375 #if defined(_KERNEL)
376
377 static __inline unsigned short xilinx_valid_mtu(unsigned short mtu)
378 {
379 if (mtu <= 128) {
380 return 128;
381 } else if (mtu <= 256) {
382 return 256;
383 } else if (mtu <= 512) {
384 return 512;
385 } else if (mtu <= 1024) {
386 return 1024;
387 } else if (mtu <= 2048) {
388 return 2048;
389 } else if (mtu <= 4096) {
390 return 4096;
391 } else if (mtu <= 8188) {
392 return 8188;
393 } else {
394 return 0;
395 }
396 }
397
398 static __inline unsigned short xilinx_dma_buf_bits(unsigned short dma_bufs)
399 {
400 if (dma_bufs < 2) {
401 return 0;
402 } else if (dma_bufs < 3) {
403 return 1;
404 } else if (dma_bufs < 5) {
405 return 2;
406 } else if (dma_bufs < 9) {
407 return 3;
408 } else if (dma_bufs < 17) {
409 return 4;
410 } else {
411 return 0;
412 }
413 }
414
415 #define AFT_TX_TIMEOUT 25
416 #define AFT_RX_TIMEOUT 10
417 #define AFT_MAX_WTD_TIMEOUT 250
418
419 static __inline void aft_reset_rx_watchdog(sdla_t *card)
420 {
421 sdla_bus_write_4(card->hw,AFT_TE3_RX_WDT_CTRL_REG,0);
422 }
423
424 static __inline void aft_enable_rx_watchdog(sdla_t *card, unsigned char timeout)
425 {
426 aft_reset_rx_watchdog(card);
427 sdla_bus_write_4(card->hw,AFT_TE3_RX_WDT_CTRL_REG,timeout);
428 }
429
430 static __inline void aft_reset_tx_watchdog(sdla_t *card)
431 {
432 sdla_bus_write_4(card->hw,AFT_TE3_TX_WDT_CTRL_REG,0);
433 }
434
435 static __inline void aft_enable_tx_watchdog(sdla_t *card, unsigned char timeout)
436 {
437 aft_reset_tx_watchdog(card);
438 sdla_bus_write_4(card->hw,AFT_TE3_TX_WDT_CTRL_REG,timeout);
439 }
440
441 #endif
442
443 #endif