XILINX_TIMESLOT_HDLC_CHAN_REG 1124 dev/pci/if_san_xilinx.c 	sdla_bus_write_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG, reg);
XILINX_TIMESLOT_HDLC_CHAN_REG 1177 dev/pci/if_san_xilinx.c 	sdla_bus_write_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG, reg);
XILINX_TIMESLOT_HDLC_CHAN_REG 1275 dev/pci/if_san_xilinx.c 			    XILINX_TIMESLOT_HDLC_CHAN_REG, &reg);
XILINX_TIMESLOT_HDLC_CHAN_REG 1283 dev/pci/if_san_xilinx.c 			    XILINX_TIMESLOT_HDLC_CHAN_REG,
XILINX_TIMESLOT_HDLC_CHAN_REG 1317 dev/pci/if_san_xilinx.c 				    XILINX_TIMESLOT_HDLC_CHAN_REG, &reg);
XILINX_TIMESLOT_HDLC_CHAN_REG 1325 dev/pci/if_san_xilinx.c 				    XILINX_TIMESLOT_HDLC_CHAN_REG,
XILINX_TIMESLOT_HDLC_CHAN_REG 1364 dev/pci/if_san_xilinx.c 			    XILINX_TIMESLOT_HDLC_CHAN_REG, &reg);
XILINX_TIMESLOT_HDLC_CHAN_REG 1372 dev/pci/if_san_xilinx.c 			    XILINX_TIMESLOT_HDLC_CHAN_REG,
XILINX_TIMESLOT_HDLC_CHAN_REG 1387 dev/pci/if_san_xilinx.c 	sdla_bus_read_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG, &reg);
XILINX_TIMESLOT_HDLC_CHAN_REG 1392 dev/pci/if_san_xilinx.c 	sdla_bus_write_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG,
XILINX_TIMESLOT_HDLC_CHAN_REG 1423 dev/pci/if_san_xilinx.c 		sdla_bus_read_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG, &reg);
XILINX_TIMESLOT_HDLC_CHAN_REG 1427 dev/pci/if_san_xilinx.c 		sdla_bus_write_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG,
XILINX_TIMESLOT_HDLC_CHAN_REG 1437 dev/pci/if_san_xilinx.c 				    XILINX_TIMESLOT_HDLC_CHAN_REG, &reg);
XILINX_TIMESLOT_HDLC_CHAN_REG 1445 dev/pci/if_san_xilinx.c 				    XILINX_TIMESLOT_HDLC_CHAN_REG,
XILINX_TIMESLOT_HDLC_CHAN_REG 1629 dev/pci/if_san_xilinx.c 	sdla_bus_read_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG, &reg);
XILINX_TIMESLOT_HDLC_CHAN_REG 1634 dev/pci/if_san_xilinx.c 	sdla_bus_write_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG,
XILINX_TIMESLOT_HDLC_CHAN_REG 3263 dev/pci/if_san_xilinx.c 		sdla_bus_read_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG, &reg);