HDLC_LCH_TIMESLOT_MASK 1279 dev/pci/if_san_xilinx.c 			reg &= HDLC_LCH_TIMESLOT_MASK; /* mask not valid bits*/
HDLC_LCH_TIMESLOT_MASK 1321 dev/pci/if_san_xilinx.c 				reg &= HDLC_LCH_TIMESLOT_MASK;
HDLC_LCH_TIMESLOT_MASK 1369 dev/pci/if_san_xilinx.c 			reg &= HDLC_LCH_TIMESLOT_MASK;
HDLC_LCH_TIMESLOT_MASK 1390 dev/pci/if_san_xilinx.c 	reg &= HDLC_LCH_TIMESLOT_MASK;         /* mask not valid bits */
HDLC_LCH_TIMESLOT_MASK 1425 dev/pci/if_san_xilinx.c 		reg &= HDLC_LCH_TIMESLOT_MASK;	/* mask not valid bits */
HDLC_LCH_TIMESLOT_MASK 1441 dev/pci/if_san_xilinx.c 				reg &= HDLC_LCH_TIMESLOT_MASK;
HDLC_LCH_TIMESLOT_MASK 1632 dev/pci/if_san_xilinx.c 	reg &= HDLC_LCH_TIMESLOT_MASK;         /* mask not valid bits */