root/dev/pci/if_em_hw.c

DEFINITIONS

1. em_set_phy_type
2. em_phy_init_script
3. em_set_mac_type
4. em_set_media_type
5. em_reset_hw
6. em_initialize_hardware_bits
7. em_init_hw
8. em_adjust_serdes_amplitude
9. em_setup_link
10. em_setup_fiber_serdes_link
11. em_copper_link_preconfig
12. em_copper_link_igp_setup
13. em_copper_link_ggp_setup
14. em_copper_link_mgp_setup
15. em_copper_link_autoneg
16. em_copper_link_postconfig
17. em_setup_copper_link
18. em_configure_kmrn_for_10_100
19. em_configure_kmrn_for_1000
20. em_phy_setup_autoneg
21. em_phy_force_speed_duplex
22. em_config_collision_dist
23. em_config_mac_to_phy
24. em_force_mac_fc
25. em_config_fc_after_link_up
26. em_check_for_link
27. em_get_speed_and_duplex
28. em_wait_autoneg
29. em_raise_mdi_clk
30. em_lower_mdi_clk
31. em_shift_out_mdi_bits
32. em_shift_in_mdi_bits
33. em_swfw_sync_acquire
34. em_swfw_sync_release
35. em_read_phy_reg
36. em_read_phy_reg_ex
37. em_write_phy_reg
38. em_write_phy_reg_ex
39. em_read_kmrn_reg
40. em_write_kmrn_reg
41. em_phy_hw_reset
42. em_phy_reset
43. em_kumeran_lock_loss_workaround
44. em_detect_gig_phy
45. em_phy_reset_dsp
46. em_init_eeprom_params
47. em_raise_ee_clk
48. em_lower_ee_clk
49. em_shift_out_ee_bits
50. em_shift_in_ee_bits
51. em_acquire_eeprom
52. em_standby_eeprom
53. em_release_eeprom
54. em_spi_eeprom_ready
55. em_read_eeprom
56. em_read_eeprom_eerd
57. em_write_eeprom_eewr
58. em_poll_eerd_eewr_done
59. em_is_onboard_nvm_eeprom
60. em_validate_eeprom_checksum
61. em_update_eeprom_checksum
62. em_write_eeprom
63. em_write_eeprom_spi
64. em_write_eeprom_microwire
65. em_commit_shadow_ram
66. em_read_part_num
67. em_read_mac_addr
68. em_init_rx_addrs
69. em_mc_addr_list_update
70. em_hash_mc_addr
71. em_mta_set
72. em_rar_set
73. em_clear_vfta
74. em_id_led_init
75. em_clear_hw_cntrs
76. em_tbi_adjust_stats
77. em_get_bus_info
78. em_write_reg_io
79. em_get_cable_length
80. em_check_downshift
81. em_config_dsp_after_link_change
82. em_set_phy_mode
83. em_set_d3_lplu_state
84. em_set_d0_lplu_state
85. em_set_vco_speed
86. em_host_if_read_cookie
87. em_mng_enable_host_if
88. em_check_mng_mode
89. em_calculate_mng_checksum
90. em_enable_tx_pkt_filtering
91. em_polarity_reversal_workaround
92. em_set_pci_express_master_disable
93. em_disable_pciex_master
94. em_get_auto_rd_done
95. em_get_phy_cfg_done
96. em_get_hw_eeprom_semaphore
97. em_put_hw_eeprom_semaphore
98. em_get_software_semaphore
99. em_release_software_semaphore
100. em_check_phy_reset_block
101. em_set_pci_ex_no_snoop
102. em_get_software_flag
103. em_release_software_flag
104. em_read_eeprom_ich8
105. em_write_eeprom_ich8
106. em_ich8_cycle_init
107. em_ich8_flash_cycle
108. em_read_ich8_data
109. em_write_ich8_data
110. em_read_ich8_byte
111. em_verify_write_ich8_byte
112. em_write_ich8_byte
113. em_read_ich8_word
114. em_erase_ich8_4k_segment
115. em_init_lcd_from_nvm_config_region
116. em_init_lcd_from_nvm

    1 /*******************************************************************************
    2 
    3   Copyright (c) 2001-2005, Intel Corporation 
    4   All rights reserved.
    5   
    6   Redistribution and use in source and binary forms, with or without 
    7   modification, are permitted provided that the following conditions are met:
    8   
    9    1. Redistributions of source code must retain the above copyright notice, 
   10       this list of conditions and the following disclaimer.
   11   
   12    2. Redistributions in binary form must reproduce the above copyright 
   13       notice, this list of conditions and the following disclaimer in the 
   14       documentation and/or other materials provided with the distribution.
   15   
   16    3. Neither the name of the Intel Corporation nor the names of its 
   17       contributors may be used to endorse or promote products derived from 
   18       this software without specific prior written permission.
   19   
   20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
   22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
   23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
   24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
   25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
   26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
   27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
   28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
   29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   30   POSSIBILITY OF SUCH DAMAGE.
   31 
   32 *******************************************************************************/
   34 /* $OpenBSD: if_em_hw.c,v 1.26 2007/05/09 18:02:46 deraadt Exp $ */
   36 /* if_em_hw.c
   37  * Shared functions for accessing and configuring the MAC
   38  */
   40 #if 0
   41 #include <sys/cdefs.h>
   42 __FBSDID("$FreeBSD: if_em_hw.c,v 1.16 2005/05/26 23:32:02 tackerman Exp $");
   43 #endif
   45 #include <sys/param.h>
   46 #include <sys/systm.h>
   47 #include <sys/sockio.h>
   48 #include <sys/mbuf.h>
   49 #include <sys/malloc.h>
   50 #include <sys/kernel.h>
   51 #include <sys/device.h>
   52 #include <sys/socket.h>
   54 #include <net/if.h>
   55 #include <net/if_dl.h>
   56 #include <net/if_media.h>
   58 #ifdef INET
   59 #include <netinet/in.h>
   60 #include <netinet/in_systm.h>
   61 #include <netinet/in_var.h>
   62 #include <netinet/ip.h>
   63 #include <netinet/if_ether.h>
   64 #endif
   66 #include <uvm/uvm_extern.h>
   68 #include <dev/pci/pcireg.h>
   69 #include <dev/pci/pcivar.h>
   70 #include <dev/pci/pcidevs.h>
   72 #include <dev/pci/if_em_hw.h>
   74 #define STATIC
   76 static int32_t em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask);
   77 static void em_swfw_sync_release(struct em_hw *hw, uint16_t mask);
   78 static int32_t em_read_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *data);
   79 static int32_t em_write_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data);
   80 static int32_t em_get_software_semaphore(struct em_hw *hw);
   81 static void em_release_software_semaphore(struct em_hw *hw);
   83 static int32_t em_check_downshift(struct em_hw *hw);
   84 static void em_clear_vfta(struct em_hw *hw);
   85 static int32_t em_commit_shadow_ram(struct em_hw *hw);
   86 static int32_t em_config_dsp_after_link_change(struct em_hw *hw, boolean_t link_up);
   87 static int32_t em_config_fc_after_link_up(struct em_hw *hw);
   88 static int32_t em_detect_gig_phy(struct em_hw *hw);
   89 static int32_t em_erase_ich8_4k_segment(struct em_hw *hw, uint32_t bank);
   90 static int32_t em_get_auto_rd_done(struct em_hw *hw);
   91 static int32_t em_get_cable_length(struct em_hw *hw, uint16_t *min_length, uint16_t *max_length);
   92 static int32_t em_get_hw_eeprom_semaphore(struct em_hw *hw);
   93 static int32_t em_get_phy_cfg_done(struct em_hw *hw);
   94 static int32_t em_get_software_flag(struct em_hw *hw);
   95 static int32_t em_ich8_cycle_init(struct em_hw *hw);
   96 static int32_t em_ich8_flash_cycle(struct em_hw *hw, uint32_t timeout);
   97 static int32_t em_id_led_init(struct em_hw *hw);
   98 static int32_t em_init_lcd_from_nvm_config_region(struct em_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size);
   99 static int32_t em_init_lcd_from_nvm(struct em_hw *hw);
  100 static void em_init_rx_addrs(struct em_hw *hw);
  101 static void em_initialize_hardware_bits(struct em_hw *hw);
  102 static boolean_t em_is_onboard_nvm_eeprom(struct em_hw *hw);
  103 static int32_t em_kumeran_lock_loss_workaround(struct em_hw *hw);
  104 static int32_t em_mng_enable_host_if(struct em_hw *hw);
  105 static int32_t em_read_eeprom_eerd(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
  106 static int32_t em_write_eeprom_eewr(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
  107 static int32_t em_poll_eerd_eewr_done(struct em_hw *hw, int eerd);
  108 static void em_put_hw_eeprom_semaphore(struct em_hw *hw);
  109 static int32_t em_read_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t *data);
  110 static int32_t em_verify_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t byte);
  111 static int32_t em_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t byte);
  112 static int32_t em_read_ich8_word(struct em_hw *hw, uint32_t index, uint16_t *data);
  113 static int32_t em_read_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, uint16_t *data);
  114 static int32_t em_write_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, uint16_t data);
  115 static int32_t em_read_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
  116 static int32_t em_write_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
  117 static void em_release_software_flag(struct em_hw *hw);
  118 static int32_t em_set_d3_lplu_state(struct em_hw *hw, boolean_t active);
  119 static int32_t em_set_d0_lplu_state(struct em_hw *hw, boolean_t active);
  120 static int32_t em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop);
  121 static void em_set_pci_express_master_disable(struct em_hw *hw);
  122 static int32_t em_wait_autoneg(struct em_hw *hw);
  123 static void em_write_reg_io(struct em_hw *hw, uint32_t offset, uint32_t value);
  124 static int32_t em_set_phy_type(struct em_hw *hw);
  125 static void em_phy_init_script(struct em_hw *hw);
  126 static int32_t em_setup_copper_link(struct em_hw *hw);
  127 static int32_t em_setup_fiber_serdes_link(struct em_hw *hw);
  128 static int32_t em_adjust_serdes_amplitude(struct em_hw *hw);
  129 static int32_t em_phy_force_speed_duplex(struct em_hw *hw);
  130 static int32_t em_config_mac_to_phy(struct em_hw *hw);
  131 static void em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl);
  132 static void em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl);
  133 static void em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data,
uint16_t count);
  135 static uint16_t em_shift_in_mdi_bits(struct em_hw *hw);
  136 static int32_t em_phy_reset_dsp(struct em_hw *hw);
  137 static int32_t em_write_eeprom_spi(struct em_hw *hw, uint16_t offset,
uint16_t words, uint16_t *data);
  139 static int32_t em_write_eeprom_microwire(struct em_hw *hw,
uint16_t offset, uint16_t words,
uint16_t *data);
  142 static int32_t em_spi_eeprom_ready(struct em_hw *hw);
  143 static void em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd);
  144 static void em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd);
  145 static void em_shift_out_ee_bits(struct em_hw *hw, uint16_t data,
uint16_t count);
  147 static int32_t em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr,
uint16_t phy_data);
  149 static int32_t em_read_phy_reg_ex(struct em_hw *hw,uint32_t reg_addr,
uint16_t *phy_data);
  151 static uint16_t em_shift_in_ee_bits(struct em_hw *hw, uint16_t count);
  152 static int32_t em_acquire_eeprom(struct em_hw *hw);
  153 static void em_release_eeprom(struct em_hw *hw);
  154 static void em_standby_eeprom(struct em_hw *hw);
  155 static int32_t em_set_vco_speed(struct em_hw *hw);
  156 static int32_t em_polarity_reversal_workaround(struct em_hw *hw);
  157 static int32_t em_set_phy_mode(struct em_hw *hw);
  158 static int32_t em_host_if_read_cookie(struct em_hw *hw, uint8_t *buffer);
  159 static uint8_t em_calculate_mng_checksum(char *buffer, uint32_t length);
  160 static int32_t em_configure_kmrn_for_10_100(struct em_hw *hw,
uint16_t duplex);
  162 static int32_t em_configure_kmrn_for_1000(struct em_hw *hw);
  164 /* IGP cable length table */
  165 static const
uint16_t em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
  167     { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
  168       5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
  169       25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
  170       40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
  171       60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
  172       90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
  173       100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
  174       110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
  176 static const
uint16_t em_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
  178     { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
  179       0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
  180       6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
  181       21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
  182       40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
  183       60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
  184       83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
  185       104, 109, 114, 118, 121, 124};
  187 /******************************************************************************
  188  * Set the phy type member in the hw struct.
  189  *
  190  * hw - Struct containing variables accessed by shared code
  191  *****************************************************************************/
STATIC int32_t
em_set_phy_type(struct em_hw *hw)
  194 {
DEBUGFUNC("em_set_phy_type");
  197     if (hw->mac_type == em_undefined)
  198         return -E1000_ERR_PHY_TYPE;
  200     switch (hw->phy_id) {
  201     case M88E1000_E_PHY_ID:
  202     case M88E1000_I_PHY_ID:
  203     case M88E1011_I_PHY_ID:
  204     case M88E1111_I_PHY_ID:
hw->phy_type = em_phy_m88;
  206         break;
  207     case IGP01E1000_I_PHY_ID:
  208         if (hw->mac_type == em_82541 ||
hw->mac_type == em_82541_rev_2 ||
hw->mac_type == em_82547 ||
hw->mac_type == em_82547_rev_2) {
hw->phy_type = em_phy_igp;
  213             break;
  214         }
  215     case IGP03E1000_E_PHY_ID:
hw->phy_type = em_phy_igp_3;
  217         break;
  218     case IFE_E_PHY_ID:
  219     case IFE_PLUS_E_PHY_ID:
  220     case IFE_C_E_PHY_ID:
hw->phy_type = em_phy_ife;
  222         break;
  223     case GG82563_E_PHY_ID:
  224         if (hw->mac_type == em_80003es2lan) {
hw->phy_type = em_phy_gg82563;
  226             break;
  227         }
  228         /* FALLTHROUGH */
  229     default:
  230         /* Should never have loaded on this device */
hw->phy_type = em_phy_undefined;
  232         return -E1000_ERR_PHY_TYPE;
  233     }
  235     return E1000_SUCCESS;
  236 }
  238 /******************************************************************************
  239  * IGP phy init script - initializes the GbE PHY
  240  *
  241  * hw - Struct containing variables accessed by shared code
  242  *****************************************************************************/
  243 static void
em_phy_init_script(struct em_hw *hw)
  245 {
uint32_t ret_val;
uint16_t phy_saved_data;
DEBUGFUNC("em_phy_init_script");
  251     if (hw->phy_init_script) {
msec_delay(20);
  254         /* Save off the current value of register 0x2F5B to be restored at
  255          * the end of this routine. */
ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
  258         /* Disabled the PHY transmitter */
em_write_phy_reg(hw, 0x2F5B, 0x0003);
msec_delay(20);
em_write_phy_reg(hw,0x0000,0x0140);
msec_delay(5);
  267         switch (hw->mac_type) {
  268         case em_82541:
  269         case em_82547:
em_write_phy_reg(hw, 0x1F95, 0x0001);
em_write_phy_reg(hw, 0x1F71, 0xBD21);
em_write_phy_reg(hw, 0x1F79, 0x0018);
em_write_phy_reg(hw, 0x1F30, 0x1600);
em_write_phy_reg(hw, 0x1F31, 0x0014);
em_write_phy_reg(hw, 0x1F32, 0x161C);
em_write_phy_reg(hw, 0x1F94, 0x0003);
em_write_phy_reg(hw, 0x1F96, 0x003F);
em_write_phy_reg(hw, 0x2010, 0x0008);
  287             break;
  289         case em_82541_rev_2:
  290         case em_82547_rev_2:
em_write_phy_reg(hw, 0x1F73, 0x0099);
  292             break;
  293         default:
  294             break;
  295         }
em_write_phy_reg(hw, 0x0000, 0x3300);
msec_delay(20);
  301         /* Now enable the transmitter */
em_write_phy_reg(hw, 0x2F5B, phy_saved_data);
  304         if (hw->mac_type == em_82547) {
uint16_t fused, fine, coarse;
  307             /* Move to analog registers page */
em_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
  310             if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
em_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
  316                 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
  319                 } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
  323                         (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
  324                         (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
em_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
em_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
  329             }
  330         }
  331     }
  332 }
  334 /******************************************************************************
  335  * Set the mac type member in the hw struct.
  336  *
  337  * hw - Struct containing variables accessed by shared code
  338  *****************************************************************************/
int32_t
em_set_mac_type(struct em_hw *hw)
  341 {
DEBUGFUNC("em_set_mac_type");
  344     switch (hw->device_id) {
  345     case E1000_DEV_ID_82542:
  346         switch (hw->revision_id) {
  347         case E1000_82542_2_0_REV_ID:
hw->mac_type = em_82542_rev2_0;
  349             break;
  350         case E1000_82542_2_1_REV_ID:
hw->mac_type = em_82542_rev2_1;
  352             break;
  353         default:
  354             /* Invalid 82542 revision ID */
  355             return -E1000_ERR_MAC_TYPE;
  356         }
  357         break;
  358     case E1000_DEV_ID_82543GC_FIBER:
  359     case E1000_DEV_ID_82543GC_COPPER:
hw->mac_type = em_82543;
  361         break;
  362     case E1000_DEV_ID_82544EI_COPPER:
  363     case E1000_DEV_ID_82544EI_FIBER:
  364     case E1000_DEV_ID_82544GC_COPPER:
  365     case E1000_DEV_ID_82544GC_LOM:
hw->mac_type = em_82544;
  367         break;
  368     case E1000_DEV_ID_82540EM:
  369     case E1000_DEV_ID_82540EM_LOM:
  370     case E1000_DEV_ID_82540EP:
  371     case E1000_DEV_ID_82540EP_LOM:
  372     case E1000_DEV_ID_82540EP_LP:
hw->mac_type = em_82540;
  374         break;
  375     case E1000_DEV_ID_82545EM_COPPER:
  376     case E1000_DEV_ID_82545EM_FIBER:
hw->mac_type = em_82545;
  378         break;
  379     case E1000_DEV_ID_82545GM_COPPER:
  380     case E1000_DEV_ID_82545GM_FIBER:
  381     case E1000_DEV_ID_82545GM_SERDES:
hw->mac_type = em_82545_rev_3;
  383         break;
  384     case E1000_DEV_ID_82546EB_COPPER:
  385     case E1000_DEV_ID_82546EB_FIBER:
  386     case E1000_DEV_ID_82546EB_QUAD_COPPER:
hw->mac_type = em_82546;
  388         break;
  389     case E1000_DEV_ID_82546GB_COPPER:
  390     case E1000_DEV_ID_82546GB_FIBER:
  391     case E1000_DEV_ID_82546GB_SERDES:
  392     case E1000_DEV_ID_82546GB_PCIE:
  393     case E1000_DEV_ID_82546GB_QUAD_COPPER:
  394     case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
  395     case E1000_DEV_ID_82546GB_2:
hw->mac_type = em_82546_rev_3;
  397         break;
  398     case E1000_DEV_ID_82541EI:
  399     case E1000_DEV_ID_82541EI_MOBILE:
  400     case E1000_DEV_ID_82541ER_LOM:
hw->mac_type = em_82541;
  402         break;
  403     case E1000_DEV_ID_82541ER:
  404     case E1000_DEV_ID_82541GI:
  405     case E1000_DEV_ID_82541GI_LF:
  406     case E1000_DEV_ID_82541GI_MOBILE:
hw->mac_type = em_82541_rev_2;
  408         break;
  409     case E1000_DEV_ID_82547EI:
  410     case E1000_DEV_ID_82547EI_MOBILE:
hw->mac_type = em_82547;
  412         break;
  413     case E1000_DEV_ID_82547GI:
hw->mac_type = em_82547_rev_2;
  415         break;
  416     case E1000_DEV_ID_82571EB_AF:
  417     case E1000_DEV_ID_82571EB_AT:
  418     case E1000_DEV_ID_82571EB_COPPER:
  419     case E1000_DEV_ID_82571EB_FIBER:
  420     case E1000_DEV_ID_82571EB_SERDES:
  421     case E1000_DEV_ID_82571EB_QUAD_COPPER:
  422     case E1000_DEV_ID_82571EB_QUAD_FIBER:
  423     case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
hw->mac_type = em_82571;
  425         break;
  426     case E1000_DEV_ID_82572EI_COPPER:
  427     case E1000_DEV_ID_82572EI_FIBER:
  428     case E1000_DEV_ID_82572EI_SERDES:
  429     case E1000_DEV_ID_82572EI:
hw->mac_type = em_82572;
  431         break;
  432     case E1000_DEV_ID_82573E:
  433     case E1000_DEV_ID_82573E_IAMT:
  434     case E1000_DEV_ID_82573E_PM:
  435     case E1000_DEV_ID_82573L:
  436     case E1000_DEV_ID_82573L_PL_1:
  437     case E1000_DEV_ID_82573L_PL_2:
  438     case E1000_DEV_ID_82573V_PM:
hw->mac_type = em_82573;
  440         break;
  441     case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
  442     case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
  443     case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
  444     case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
hw->mac_type = em_80003es2lan;
  446         break;
  447     case E1000_DEV_ID_ICH8_IGP_M_AMT:
  448     case E1000_DEV_ID_ICH8_IGP_AMT:
  449     case E1000_DEV_ID_ICH8_IGP_C:
  450     case E1000_DEV_ID_ICH8_IFE:
  451     case E1000_DEV_ID_ICH8_IFE_GT:
  452     case E1000_DEV_ID_ICH8_IFE_G:
  453     case E1000_DEV_ID_ICH8_IGP_M:
hw->mac_type = em_ich8lan;
  455         break;
  456     default:
  457         /* Should never have loaded on this device */
  458         return -E1000_ERR_MAC_TYPE;
  459     }
  461     switch (hw->mac_type) {
  462     case em_ich8lan:
hw->swfwhw_semaphore_present = TRUE;
hw->asf_firmware_present = TRUE;
  465         break;
  466     case em_80003es2lan:
hw->swfw_sync_present = TRUE;
  468         /* FALLTHROUGH */
  469     case em_82571:
  470     case em_82572:
  471     case em_82573:
hw->eeprom_semaphore_present = TRUE;
  473         /* FALLTHROUGH */
  474     case em_82541:
  475     case em_82547:
  476     case em_82541_rev_2:
  477     case em_82547_rev_2:
hw->asf_firmware_present = TRUE;
  479         break;
  480     default:
  481         break;
  482     }
  484     return E1000_SUCCESS;
  485 }
  487 /*****************************************************************************
  488  * Set media type and TBI compatibility.
  489  *
  490  * hw - Struct containing variables accessed by shared code
  491  * **************************************************************************/
  492 void
em_set_media_type(struct em_hw *hw)
  494 {
uint32_t status;
DEBUGFUNC("em_set_media_type");
  499     if (hw->mac_type != em_82543) {
  500         /* tbi_compatibility is only valid on 82543 */
hw->tbi_compatibility_en = FALSE;
  502     }
  504     switch (hw->device_id) {
  505     case E1000_DEV_ID_82545GM_SERDES:
  506     case E1000_DEV_ID_82546GB_SERDES:
  507     case E1000_DEV_ID_82571EB_SERDES:
  508     case E1000_DEV_ID_82572EI_SERDES:
  509     case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
hw->media_type = em_media_type_internal_serdes;
  511         break;
  512     default:
  513         switch (hw->mac_type) {
  514         case em_82542_rev2_0:
  515         case em_82542_rev2_1:
hw->media_type = em_media_type_fiber;
  517             break;
  518         case em_ich8lan:
  519         case em_82573:
  520             /* The STATUS_TBIMODE bit is reserved or reused for the this
  521              * device.
  522              */
hw->media_type = em_media_type_copper;
  524             break;
  525         default:
status = E1000_READ_REG(hw, STATUS);
  527             if (status & E1000_STATUS_TBIMODE) {
hw->media_type = em_media_type_fiber;
  529                 /* tbi_compatibility not valid on fiber */
hw->tbi_compatibility_en = FALSE;
  531             } else {
hw->media_type = em_media_type_copper;
  533             }
  534             break;
  535         }
  536     }
  537 }
  539 /******************************************************************************
  540  * Reset the transmit and receive units; mask and clear all interrupts.
  541  *
  542  * hw - Struct containing variables accessed by shared code
  543  *****************************************************************************/
int32_t
em_reset_hw(struct em_hw *hw)
  546 {
uint32_t ctrl;
uint32_t ctrl_ext;
uint32_t icr;
uint32_t manc;
uint32_t led_ctrl;
uint32_t timeout;
uint32_t extcnf_ctrl;
int32_t ret_val;
DEBUGFUNC("em_reset_hw");
  558     /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
  559     if (hw->mac_type == em_82542_rev2_0) {
DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
em_pci_clear_mwi(hw);
  562     }
  564     if (hw->bus_type == em_bus_type_pci_express) {
  565         /* Prevent the PCI-E bus from sticking if there is no TLP connection
  566          * on the last TLP read/write transaction when MAC is reset.
  567          */
  568         if (em_disable_pciex_master(hw) != E1000_SUCCESS) {
DEBUGOUT("PCI-E Master disable polling has failed.\n");
  570         }
  571     }
  573     /* Clear interrupt mask to stop board from generating interrupts */
DEBUGOUT("Masking off all interrupts\n");
E1000_WRITE_REG(hw, IMC, 0xffffffff);
  577     /* Disable the Transmit and Receive units.  Then delay to allow
  578      * any pending transactions to complete before we hit the MAC with
  579      * the global reset.
  580      */
E1000_WRITE_REG(hw, RCTL, 0);
E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
E1000_WRITE_FLUSH(hw);
  585     /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
hw->tbi_compatibility_on = FALSE;
  588     /* Delay to allow any outstanding PCI transactions to complete before
  589      * resetting the device
  590      */
msec_delay(10);
ctrl = E1000_READ_REG(hw, CTRL);
  595     /* Must reset the PHY before resetting the MAC */
  596     if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
msec_delay(5);
  599     }
  601     /* Must acquire the MDIO ownership before MAC reset.
  602      * Ownership defaults to firmware after a reset. */
  603     if (hw->mac_type == em_82573) {
timeout = 10;
extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
  609         do {
E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
  613             if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
  614                 break;
  615             else
extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
msec_delay(2);
timeout--;
  620         } while (timeout);
  621     }
  623     /* Workaround for ICH8 bit corruption issue in FIFO memory */
  624     if (hw->mac_type == em_ich8lan) {
  625         /* Set Tx and Rx buffer allocation to 8k apiece. */
E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);
  627         /* Set Packet Buffer Size to 16k. */
E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);
  629     }
  631     /* Issue a global reset to the MAC.  This will reset the chip's
  632      * transmit, receive, DMA, and link units.  It will not effect
  633      * the current PCI configuration.  The global reset bit is self-
  634      * clearing, and should clear within a microsecond.
  635      */
DEBUGOUT("Issuing a global reset to MAC\n");
  638     switch (hw->mac_type) {
  639         case em_82544:
  640         case em_82540:
  641         case em_82545:
  642         case em_82546:
  643         case em_82541:
  644         case em_82541_rev_2:
  645             /* These controllers can't ack the 64-bit write when issuing the
  646              * reset, so use IO-mapping as a workaround to issue the reset */
E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
  648             break;
  649         case em_82545_rev_3:
  650         case em_82546_rev_3:
  651             /* Reset is performed on a shadow of the control register */
E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
  653             break;
  654         case em_ich8lan:
  655             if (!hw->phy_reset_disable &&
em_check_phy_reset_block(hw) == E1000_SUCCESS) {
  657                 /* em_ich8lan PHY HW reset requires MAC CORE reset
  658                  * at the same time to make sure the interface between
  659                  * MAC and the external PHY is reset.
  660                  */
ctrl |= E1000_CTRL_PHY_RST;
  662             }
em_get_software_flag(hw);
E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
msec_delay(5);
  667             break;
  668         default:
E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
  670             break;
  671     }
  673     /* After MAC reset, force reload of EEPROM to restore power-on settings to
  674      * device.  Later controllers reload the EEPROM automatically, so just wait
  675      * for reload to complete.
  676      */
  677     switch (hw->mac_type) {
  678         case em_82542_rev2_0:
  679         case em_82542_rev2_1:
  680         case em_82543:
  681         case em_82544:
  682             /* Wait for reset to complete */
usec_delay(10);
ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
ctrl_ext |= E1000_CTRL_EXT_EE_RST;
E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
E1000_WRITE_FLUSH(hw);
  688             /* Wait for EEPROM reload */
msec_delay(2);
  690             break;
  691         case em_82541:
  692         case em_82541_rev_2:
  693         case em_82547:
  694         case em_82547_rev_2:
  695             /* Wait for EEPROM reload */
msec_delay(20);
  697             break;
  698         case em_82573:
  699             if (em_is_onboard_nvm_eeprom(hw) == FALSE) {
usec_delay(10);
ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
ctrl_ext |= E1000_CTRL_EXT_EE_RST;
E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
E1000_WRITE_FLUSH(hw);
  705             }
  706             /* FALLTHROUGH */
  707         default:
  708             /* Auto read done will delay 5ms or poll based on mac type */
ret_val = em_get_auto_rd_done(hw);
  710             if (ret_val)
  711                 return ret_val;
  712             break;
  713     }
  715     /* Disable HW ARPs on ASF enabled adapters */
  716     if (hw->mac_type >= em_82540 && hw->mac_type <= em_82547_rev_2) {
manc = E1000_READ_REG(hw, MANC);
manc &= ~(E1000_MANC_ARP_EN);
E1000_WRITE_REG(hw, MANC, manc);
  720     }
  722     if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
em_phy_init_script(hw);
  725         /* Configure activity LED after PHY reset */
led_ctrl = E1000_READ_REG(hw, LEDCTL);
led_ctrl &= IGP_ACTIVITY_LED_MASK;
led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
  730     }
  732     /* Clear interrupt mask to stop board from generating interrupts */
DEBUGOUT("Masking off all interrupts\n");
E1000_WRITE_REG(hw, IMC, 0xffffffff);
  736     /* Clear any pending interrupt events. */
icr = E1000_READ_REG(hw, ICR);
  739     /* If MWI was previously enabled, reenable it. */
  740     if (hw->mac_type == em_82542_rev2_0) {
  741         if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
em_pci_set_mwi(hw);
  743     }
  745     if (hw->mac_type == em_ich8lan) {
uint32_t kab = E1000_READ_REG(hw, KABGTXD);
kab |= E1000_KABGTXD_BGSQLBIAS;
E1000_WRITE_REG(hw, KABGTXD, kab);
  749     }
  751     return E1000_SUCCESS;
  752 }
  754 /******************************************************************************
  755  *
  756  * Initialize a number of hardware-dependent bits
  757  *
  758  * hw: Struct containing variables accessed by shared code
  759  *
  760  *****************************************************************************/
STATIC void
em_initialize_hardware_bits(struct em_hw *hw)
  763 {
  764     if ((hw->mac_type >= em_82571) && (!hw->initialize_hw_bits_disable)) {
  765         /* Settings common to all silicon */
uint32_t reg_ctrl, reg_ctrl_ext;
uint32_t reg_tarc0, reg_tarc1;
uint32_t reg_tctl;
uint32_t reg_txdctl, reg_txdctl1;
reg_tarc0 = E1000_READ_REG(hw, TARC0);
reg_tarc0 &= ~0x78000000;           /* Clear bits 30, 29, 28, and 27 */
reg_txdctl = E1000_READ_REG(hw, TXDCTL);
reg_txdctl |= E1000_TXDCTL_COUNT_DESC;       /* Set bit 22 */
E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;      /* Set bit 22 */
E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
  782         switch (hw->mac_type) {
  783             case em_82571:
  784             case em_82572:
reg_tarc1 = E1000_READ_REG(hw, TARC1);
reg_tctl = E1000_READ_REG(hw, TCTL);
  788                 /* Set the phy Tx compatible mode bits */
reg_tarc1 &= ~0x60000000;   /* Clear bits 30 and 29 */
reg_tarc0 |= 0x07800000;    /* Set TARC0 bits 23-26 */
reg_tarc1 |= 0x07000000;    /* Set TARC1 bits 24-26 */
  794                 if (reg_tctl & E1000_TCTL_MULR)
reg_tarc1 &= ~0x10000000;   /* Clear bit 28 if MULR is 1b */
  796                 else
reg_tarc1 |= 0x10000000;    /* Set bit 28 if MULR is 0b */
E1000_WRITE_REG(hw, TARC1, reg_tarc1);
  800                 break;
  801             case em_82573:
reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
reg_ctrl = E1000_READ_REG(hw, CTRL);
reg_ctrl_ext &= ~0x00800000;    /* Clear bit 23 */
reg_ctrl_ext |= 0x00400000;     /* Set bit 22 */
reg_ctrl &= ~0x20000000;        /* Clear bit 29 */
E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
E1000_WRITE_REG(hw, CTRL, reg_ctrl);
  811                 break;
  812             case em_80003es2lan:
  813                 if ((hw->media_type == em_media_type_fiber) ||
  814                     (hw->media_type == em_media_type_internal_serdes)) {
reg_tarc0 &= ~0x00100000;   /* Clear bit 20 */
  816                 }
reg_tctl = E1000_READ_REG(hw, TCTL);
reg_tarc1 = E1000_READ_REG(hw, TARC1);
  820                 if (reg_tctl & E1000_TCTL_MULR)
reg_tarc1 &= ~0x10000000;   /* Clear bit 28 if MULR is 1b */
  822                 else
reg_tarc1 |= 0x10000000;    /* Set bit 28 if MULR is 0b */
E1000_WRITE_REG(hw, TARC1, reg_tarc1);
  826                 break;
  827             case em_ich8lan:
  828                 if ((hw->revision_id < 3) ||
  829                     ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
  830                      (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
reg_tarc0 |= 0x30000000;    /* Set TARC0 bits 29 and 28 */
reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
reg_ctrl_ext |= 0x00400000;     /* Set bit 22 */
E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
reg_tarc0 |= 0x0d800000;    /* Set TARC0 bits 23, 24, 26, 27 */
reg_tarc1 = E1000_READ_REG(hw, TARC1);
reg_tctl = E1000_READ_REG(hw, TCTL);
  841                 if (reg_tctl & E1000_TCTL_MULR)
reg_tarc1 &= ~0x10000000;   /* Clear bit 28 if MULR is 1b */
  843                 else
reg_tarc1 |= 0x10000000;    /* Set bit 28 if MULR is 0b */
reg_tarc1 |= 0x45000000;        /* Set bit 24, 26 and 30 */
E1000_WRITE_REG(hw, TARC1, reg_tarc1);
  849                 break;
  850             default:
  851                 break;
  852         }
E1000_WRITE_REG(hw, TARC0, reg_tarc0);
  855     }
  856 }
  858 /******************************************************************************
  859  * Performs basic configuration of the adapter.
  860  *
  861  * hw - Struct containing variables accessed by shared code
  862  *
  863  * Assumes that the controller has previously been reset and is in a
  864  * post-reset uninitialized state. Initializes the receive address registers,
  865  * multicast table, and VLAN filter table. Calls routines to setup link
  866  * configuration and flow control settings. Clears all on-chip counters. Leaves
  867  * the transmit and receive units disabled and uninitialized.
  868  *****************************************************************************/
int32_t
em_init_hw(struct em_hw *hw)
  871 {
uint32_t ctrl;
uint32_t i;
int32_t ret_val;
uint16_t pcix_cmd_word;
uint16_t pcix_stat_hi_word;
uint16_t cmd_mmrbc;
uint16_t stat_mmrbc;
uint32_t mta_size;
uint32_t reg_data;
uint32_t ctrl_ext;
DEBUGFUNC("em_init_hw");
  885     /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
  886     if ((hw->mac_type == em_ich8lan) &&
  887         ((hw->revision_id < 3) ||
  888          ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
  889           (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
reg_data = E1000_READ_REG(hw, STATUS);
reg_data &= ~0x80000000;
E1000_WRITE_REG(hw, STATUS, reg_data);
  893     }
  895     /* Initialize Identification LED */
ret_val = em_id_led_init(hw);
  897     if (ret_val) {
DEBUGOUT("Error Initializing Identification LED\n");
  899         return ret_val;
  900     }
  902     /* Set the media type and TBI compatibility */
em_set_media_type(hw);
  905     /* Must be called after em_set_media_type because media_type is used */
em_initialize_hardware_bits(hw);
  908     /* Disabling VLAN filtering. */
DEBUGOUT("Initializing the IEEE VLAN\n");
  910     /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
  911     if (hw->mac_type != em_ich8lan) {
  912         if (hw->mac_type < em_82545_rev_3)
E1000_WRITE_REG(hw, VET, 0);
em_clear_vfta(hw);
  915     }
  917     /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
  918     if (hw->mac_type == em_82542_rev2_0) {
DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
em_pci_clear_mwi(hw);
E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
E1000_WRITE_FLUSH(hw);
msec_delay(5);
  924     }
  926     /* Setup the receive address. This involves initializing all of the Receive
  927      * Address Registers (RARs 0 - 15).
  928      */
em_init_rx_addrs(hw);
  931     /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
  932     if (hw->mac_type == em_82542_rev2_0) {
E1000_WRITE_REG(hw, RCTL, 0);
E1000_WRITE_FLUSH(hw);
msec_delay(1);
  936         if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
em_pci_set_mwi(hw);
  938     }
  940     /* Zero out the Multicast HASH table */
DEBUGOUT("Zeroing the MTA\n");
mta_size = E1000_MC_TBL_SIZE;
  943     if (hw->mac_type == em_ich8lan)
mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
  945     for (i = 0; i < mta_size; i++) {
E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
  947         /* use write flush to prevent Memory Write Block (MWB) from
  948          * occuring when accessing our register space */
E1000_WRITE_FLUSH(hw);
  950     }
  952     /* Set the PCI priority bit correctly in the CTRL register.  This
  953      * determines if the adapter gives priority to receives, or if it
  954      * gives equal priority to transmits and receives.  Valid only on
  955      * 82542 and 82543 silicon.
  956      */
  957     if (hw->dma_fairness && hw->mac_type <= em_82543) {
ctrl = E1000_READ_REG(hw, CTRL);
E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
  960     }
  962     switch (hw->mac_type) {
  963     case em_82545_rev_3:
  964     case em_82546_rev_3:
  965         break;
  966     default:
  967         /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
  968         if (hw->bus_type == em_bus_type_pcix) {
em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
  971                 &pcix_stat_hi_word);
cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
PCIX_COMMAND_MMRBC_SHIFT;
stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
PCIX_STATUS_HI_MMRBC_SHIFT;
  976             if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
  978             if (cmd_mmrbc > stat_mmrbc) {
pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
  982                     &pcix_cmd_word);
  983             }
  984         }
  985         break;
  986     }
  988     /* More time needed for PHY to initialize */
  989     if (hw->mac_type == em_ich8lan)
msec_delay(15);
  992     /* Call a subroutine to configure the link and setup flow control. */
ret_val = em_setup_link(hw);
  995     /* Set the transmit descriptor write-back policy */
  996     if (hw->mac_type > em_82544) {
ctrl = E1000_READ_REG(hw, TXDCTL);
ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
E1000_WRITE_REG(hw, TXDCTL, ctrl);
 1000     }
 1002     if (hw->mac_type == em_82573) {
em_enable_tx_pkt_filtering(hw);
 1004     }
 1006     switch (hw->mac_type) {
 1007     default:
 1008         break;
 1009     case em_80003es2lan:
 1010         /* Enable retransmit on late collisions */
reg_data = E1000_READ_REG(hw, TCTL);
reg_data |= E1000_TCTL_RTLC;
E1000_WRITE_REG(hw, TCTL, reg_data);
 1015         /* Configure Gigabit Carry Extend Padding */
reg_data = E1000_READ_REG(hw, TCTL_EXT);
reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
 1021         /* Configure Transmit Inter-Packet Gap */
reg_data = E1000_READ_REG(hw, TIPG);
reg_data &= ~E1000_TIPG_IPGT_MASK;
reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
E1000_WRITE_REG(hw, TIPG, reg_data);
reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
reg_data &= ~0x00100000;
E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
 1030         /* FALLTHROUGH */
 1031     case em_82571:
 1032     case em_82572:
 1033     case em_ich8lan:
ctrl = E1000_READ_REG(hw, TXDCTL1);
ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
E1000_WRITE_REG(hw, TXDCTL1, ctrl);
 1037         break;
 1038     }
 1040     if (hw->mac_type == em_82573) {
uint32_t gcr = E1000_READ_REG(hw, GCR);
gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
E1000_WRITE_REG(hw, GCR, gcr);
 1044     }
 1046     /* Clear all of the statistics registers (clear on read).  It is
 1047      * important that we do this after we have tried to establish link
 1048      * because the symbol error count will increment wildly if there
 1049      * is no link.
 1050      */
em_clear_hw_cntrs(hw);
 1053     /* ICH8 No-snoop bits are opposite polarity.
 1054      * Set to snoop by default after reset. */
 1055     if (hw->mac_type == em_ich8lan)
em_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
 1058     if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
 1061         /* Relaxed ordering must be disabled to avoid a parity
 1062          * error crash in a PCI slot. */
ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
 1065     }
 1067     return ret_val;
 1068 }
 1070 /******************************************************************************
 1071  * Adjust SERDES output amplitude based on EEPROM setting.
 1072  *
 1073  * hw - Struct containing variables accessed by shared code.
 1074  *****************************************************************************/
 1075 static int32_t
em_adjust_serdes_amplitude(struct em_hw *hw)
 1077 {
uint16_t eeprom_data;
int32_t  ret_val;
DEBUGFUNC("em_adjust_serdes_amplitude");
 1083     if (hw->media_type != em_media_type_internal_serdes)
 1084         return E1000_SUCCESS;
 1086     switch (hw->mac_type) {
 1087     case em_82545_rev_3:
 1088     case em_82546_rev_3:
 1089         break;
 1090     default:
 1091         return E1000_SUCCESS;
 1092     }
ret_val = em_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
 1095     if (ret_val) {
 1096         return ret_val;
 1097     }
 1099     if (eeprom_data != EEPROM_RESERVED_WORD) {
 1100         /* Adjust SERDES output amplitude only. */
eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
 1103         if (ret_val)
 1104             return ret_val;
 1105     }
 1107     return E1000_SUCCESS;
 1108 }
 1110 /******************************************************************************
 1111  * Configures flow control and link settings.
 1112  *
 1113  * hw - Struct containing variables accessed by shared code
 1114  *
 1115  * Determines which flow control settings to use. Calls the appropriate media-
 1116  * specific link configuration function. Configures the flow control settings.
 1117  * Assuming the adapter has a valid link partner, a valid link should be
 1118  * established. Assumes the hardware has previously been reset and the
 1119  * transmitter and receiver are not enabled.
 1120  *****************************************************************************/
int32_t
em_setup_link(struct em_hw *hw)
 1123 {
uint32_t ctrl_ext;
int32_t ret_val;
uint16_t eeprom_data;
DEBUGFUNC("em_setup_link");
 1130     /* In the case of the phy reset being blocked, we already have a link.
 1131      * We do not have to set it up again. */
 1132     if (em_check_phy_reset_block(hw))
 1133         return E1000_SUCCESS;
 1135     /* Read and store word 0x0F of the EEPROM. This word contains bits
 1136      * that determine the hardware's default PAUSE (flow control) mode,
 1137      * a bit that determines whether the HW defaults to enabling or
 1138      * disabling auto-negotiation, and the direction of the
 1139      * SW defined pins. If there is no SW over-ride of the flow
 1140      * control setting, then the variable hw->fc will
 1141      * be initialized based on a value in the EEPROM.
 1142      */
 1143     if (hw->fc == E1000_FC_DEFAULT) {
 1144         switch (hw->mac_type) {
 1145         case em_ich8lan:
 1146         case em_82573:
hw->fc = E1000_FC_FULL;
 1148             break;
 1149         default:
ret_val = em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
 1151                                         1, &eeprom_data);
 1152             if (ret_val) {
DEBUGOUT("EEPROM Read Error\n");
 1154                 return -E1000_ERR_EEPROM;
 1155             }
 1156             if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
hw->fc = E1000_FC_NONE;
 1158             else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
EEPROM_WORD0F_ASM_DIR)
hw->fc = E1000_FC_TX_PAUSE;
 1161             else
hw->fc = E1000_FC_FULL;
 1163             break;
 1164         }
 1165     }
 1167     /* We want to save off the original Flow Control configuration just
 1168      * in case we get disconnected and then reconnected into a different
 1169      * hub or switch with different Flow Control capabilities.
 1170      */
 1171     if (hw->mac_type == em_82542_rev2_0)
hw->fc &= (~E1000_FC_TX_PAUSE);
 1174     if ((hw->mac_type < em_82543) && (hw->report_tx_early == 1))
hw->fc &= (~E1000_FC_RX_PAUSE);
hw->original_fc = hw->fc;
DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
 1181     /* Take the 4 bits from EEPROM word 0x0F that determine the initial
 1182      * polarity value for the SW controlled pins, and setup the
 1183      * Extended Device Control reg with that info.
 1184      * This is needed because one of the SW controlled pins is used for
 1185      * signal detection.  So this should be done before em_setup_pcs_link()
 1186      * or em_phy_setup() is called.
 1187      */
 1188     if (hw->mac_type == em_82543) {
ret_val = em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
 1190                                     1, &eeprom_data);
 1191         if (ret_val) {
DEBUGOUT("EEPROM Read Error\n");
 1193             return -E1000_ERR_EEPROM;
 1194         }
ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
SWDPIO__EXT_SHIFT);
E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
 1198     }
 1200     /* Call the necessary subroutine to configure the link. */
ret_val = (hw->media_type == em_media_type_copper) ?
em_setup_copper_link(hw) :
em_setup_fiber_serdes_link(hw);
 1205     /* Initialize the flow control address, type, and PAUSE timer
 1206      * registers to their default values.  This is done even if flow
 1207      * control is disabled, because it does not hurt anything to
 1208      * initialize these registers.
 1209      */
DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
 1212     /* FCAL/H and FCT are hardcoded to standard values in em_ich8lan. */
 1213     if (hw->mac_type != em_ich8lan) {
E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
 1217     }
E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
 1221     /* Set the flow control receive threshold registers.  Normally,
 1222      * these registers will be set to a default threshold that may be
 1223      * adjusted later by the driver's runtime code.  However, if the
 1224      * ability to transmit pause frames in not enabled, then these
 1225      * registers will be set to 0.
 1226      */
 1227     if (!(hw->fc & E1000_FC_TX_PAUSE)) {
E1000_WRITE_REG(hw, FCRTL, 0);
E1000_WRITE_REG(hw, FCRTH, 0);
 1230     } else {
 1231         /* We need to set up the Receive Threshold high and low water marks
 1232          * as well as (optionally) enabling the transmission of XON frames.
 1233          */
 1234         if (hw->fc_send_xon) {
E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
 1237         } else {
E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
 1240         }
 1241     }
 1242     return ret_val;
 1243 }
 1245 /******************************************************************************
 1246  * Sets up link for a fiber based or serdes based adapter
 1247  *
 1248  * hw - Struct containing variables accessed by shared code
 1249  *
 1250  * Manipulates Physical Coding Sublayer functions in order to configure
 1251  * link. Assumes the hardware has been previously reset and the transmitter
 1252  * and receiver are not enabled.
 1253  *****************************************************************************/
 1254 static int32_t
em_setup_fiber_serdes_link(struct em_hw *hw)
 1256 {
uint32_t ctrl;
uint32_t status;
uint32_t txcw = 0;
uint32_t i;
uint32_t signal = 0;
int32_t ret_val;
DEBUGFUNC("em_setup_fiber_serdes_link");
 1266     /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
 1267      * until explicitly turned off or a power cycle is performed.  A read to
 1268      * the register does not indicate its status.  Therefore, we ensure
 1269      * loopback mode is disabled during initialization.
 1270      */
 1271     if (hw->mac_type == em_82571 || hw->mac_type == em_82572)
E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);
 1274     /* On adapters with a MAC newer than 82544, SWDP 1 will be
 1275      * set when the optics detect a signal. On older adapters, it will be
 1276      * cleared when there is a signal.  This applies to fiber media only.
 1277      * If we're on serdes media, adjust the output amplitude to value
 1278      * set in the EEPROM.
 1279      */
ctrl = E1000_READ_REG(hw, CTRL);
 1281     if (hw->media_type == em_media_type_fiber)
signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0;
ret_val = em_adjust_serdes_amplitude(hw);
 1285     if (ret_val)
 1286         return ret_val;
 1288     /* Take the link out of reset */
ctrl &= ~(E1000_CTRL_LRST);
 1291     /* Adjust VCO speed to improve BER performance */
ret_val = em_set_vco_speed(hw);
 1293     if (ret_val)
 1294         return ret_val;
em_config_collision_dist(hw);
 1298     /* Check for a software override of the flow control settings, and setup
 1299      * the device accordingly.  If auto-negotiation is enabled, then software
 1300      * will have to set the "PAUSE" bits to the correct value in the Tranmsit
 1301      * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
 1302      * auto-negotiation is disabled, then software will have to manually
 1303      * configure the two flow control enable bits in the CTRL register.
 1304      *
 1305      * The possible values of the "fc" parameter are:
 1306      *      0:  Flow control is completely disabled
 1307      *      1:  Rx flow control is enabled (we can receive pause frames, but
 1308      *          not send pause frames).
 1309      *      2:  Tx flow control is enabled (we can send pause frames but we do
 1310      *          not support receiving pause frames).
 1311      *      3:  Both Rx and TX flow control (symmetric) are enabled.
 1312      */
 1313     switch (hw->fc) {
 1314     case E1000_FC_NONE:
 1315         /* Flow control is completely disabled by a software over-ride. */
txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
 1317         break;
 1318     case E1000_FC_RX_PAUSE:
 1319         /* RX Flow control is enabled and TX Flow control is disabled by a
 1320          * software over-ride. Since there really isn't a way to advertise
 1321          * that we are capable of RX Pause ONLY, we will advertise that we
 1322          * support both symmetric and asymmetric RX PAUSE. Later, we will
 1323          *  disable the adapter's ability to send PAUSE frames.
 1324          */
txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
 1326         break;
 1327     case E1000_FC_TX_PAUSE:
 1328         /* TX Flow control is enabled, and RX Flow control is disabled, by a
 1329          * software over-ride.
 1330          */
txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
 1332         break;
 1333     case E1000_FC_FULL:
 1334         /* Flow control (both RX and TX) is enabled by a software over-ride. */
txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
 1336         break;
 1337     default:
DEBUGOUT("Flow control param set incorrectly\n");
 1339         return -E1000_ERR_CONFIG;
 1340         break;
 1341     }
 1343     /* Since auto-negotiation is enabled, take the link out of reset (the link
 1344      * will be in reset, because we previously reset the chip). This will
 1345      * restart auto-negotiation.  If auto-neogtiation is successful then the
 1346      * link-up status bit will be set and the flow control enable bits (RFCE
 1347      * and TFCE) will be set according to their negotiated value.
 1348      */
DEBUGOUT("Auto-negotiation enabled\n");
E1000_WRITE_REG(hw, TXCW, txcw);
E1000_WRITE_REG(hw, CTRL, ctrl);
E1000_WRITE_FLUSH(hw);
hw->txcw = txcw;
msec_delay(1);
 1358     /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
 1359      * indication in the Device Status Register.  Time-out if a link isn't
 1360      * seen in 500 milliseconds seconds (Auto-negotiation should complete in
 1361      * less than 500 milliseconds even if the other end is doing it in SW).
 1362      * For internal serdes, we just assume a signal is present, then poll.
 1363      */
 1364     if (hw->media_type == em_media_type_internal_serdes ||
 1365        (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
DEBUGOUT("Looking for Link\n");
 1367         for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
msec_delay(10);
status = E1000_READ_REG(hw, STATUS);
 1370             if (status & E1000_STATUS_LU) break;
 1371         }
 1372         if (i == (LINK_UP_TIMEOUT / 10)) {
DEBUGOUT("Never got a valid link from auto-neg!!!\n");
hw->autoneg_failed = 1;
 1375             /* AutoNeg failed to achieve a link, so we'll call
 1376              * em_check_for_link. This routine will force the link up if
 1377              * we detect a signal. This will allow us to communicate with
 1378              * non-autonegotiating link partners.
 1379              */
ret_val = em_check_for_link(hw);
 1381             if (ret_val) {
DEBUGOUT("Error while checking for link\n");
 1383                 return ret_val;
 1384             }
hw->autoneg_failed = 0;
 1386         } else {
hw->autoneg_failed = 0;
DEBUGOUT("Valid Link Found\n");
 1389         }
 1390     } else {
DEBUGOUT("No Signal Detected\n");
 1392     }
 1393     return E1000_SUCCESS;
 1394 }
 1396 /******************************************************************************
 1397 * Make sure we have a valid PHY and change PHY mode before link setup.
 1398 *
 1399 * hw - Struct containing variables accessed by shared code
 1400 ******************************************************************************/
 1401 static int32_t
em_copper_link_preconfig(struct em_hw *hw)
 1403 {
uint32_t ctrl;
int32_t ret_val;
uint16_t phy_data;
DEBUGFUNC("em_copper_link_preconfig");
ctrl = E1000_READ_REG(hw, CTRL);
 1411     /* With 82543, we need to force speed and duplex on the MAC equal to what
 1412      * the PHY speed and duplex configuration is. In addition, we need to
 1413      * perform a hardware reset on the PHY to take it out of reset.
 1414      */
 1415     if (hw->mac_type > em_82543) {
ctrl |= E1000_CTRL_SLU;
ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
E1000_WRITE_REG(hw, CTRL, ctrl);
 1419     } else {
ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
E1000_WRITE_REG(hw, CTRL, ctrl);
ret_val = em_phy_hw_reset(hw);
 1423         if (ret_val)
 1424             return ret_val;
 1425     }
 1427     /* Make sure we have a valid PHY */
ret_val = em_detect_gig_phy(hw);
 1429     if (ret_val) {
DEBUGOUT("Error, did not detect valid phy.\n");
 1431         return ret_val;
 1432     }
DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
 1435     /* Set PHY to class A mode (if necessary) */
ret_val = em_set_phy_mode(hw);
 1437     if (ret_val)
 1438         return ret_val;
 1440     if ((hw->mac_type == em_82545_rev_3) ||
 1441        (hw->mac_type == em_82546_rev_3)) {
ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
phy_data |= 0x00000008;
ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
 1445     }
 1447     if (hw->mac_type <= em_82543 ||
hw->mac_type == em_82541 || hw->mac_type == em_82547 ||
hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2)
hw->phy_reset_disable = FALSE;
 1452    return E1000_SUCCESS;
 1453 }
 1456 /********************************************************************
 1457 * Copper link setup for em_phy_igp series.
 1458 *
 1459 * hw - Struct containing variables accessed by shared code
 1460 *********************************************************************/
 1461 static int32_t
em_copper_link_igp_setup(struct em_hw *hw)
 1463 {
uint32_t led_ctrl;
int32_t ret_val;
uint16_t phy_data;
DEBUGFUNC("em_copper_link_igp_setup");
 1470     if (hw->phy_reset_disable)
 1471         return E1000_SUCCESS;
ret_val = em_phy_reset(hw);
 1474     if (ret_val) {
DEBUGOUT("Error Resetting the PHY\n");
 1476         return ret_val;
 1477     }
 1479     /* Wait 15ms for MAC to configure PHY from eeprom settings */
msec_delay(15);
 1481     if (hw->mac_type != em_ich8lan) {
 1482     /* Configure activity LED after PHY reset */
led_ctrl = E1000_READ_REG(hw, LEDCTL);
led_ctrl &= IGP_ACTIVITY_LED_MASK;
led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
 1487     }
 1489     /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
 1490     if (hw->phy_type == em_phy_igp) {
 1491         /* disable lplu d3 during driver init */
ret_val = em_set_d3_lplu_state(hw, FALSE);
 1493         if (ret_val) {
DEBUGOUT("Error Disabling LPLU D3\n");
 1495             return ret_val;
 1496         }
 1497     }
 1499     /* disable lplu d0 during driver init */
ret_val = em_set_d0_lplu_state(hw, FALSE);
 1501     if (ret_val) {
DEBUGOUT("Error Disabling LPLU D0\n");
 1503         return ret_val;
 1504     }
 1505     /* Configure mdi-mdix settings */
ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
 1507     if (ret_val)
 1508         return ret_val;
 1510     if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
hw->dsp_config_state = em_dsp_config_disabled;
 1512         /* Force MDI for earlier revs of the IGP PHY */
phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
hw->mdix = 1;
 1516     } else {
hw->dsp_config_state = em_dsp_config_enabled;
phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
 1520         switch (hw->mdix) {
 1521         case 1:
phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
 1523             break;
 1524         case 2:
phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
 1526             break;
 1527         case 0:
 1528         default:
phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
 1530             break;
 1531         }
 1532     }
ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
 1534     if (ret_val)
 1535         return ret_val;
 1537     /* set auto-master slave resolution settings */
 1538     if (hw->autoneg) {
em_ms_type phy_ms_setting = hw->master_slave;
 1541         if (hw->ffe_config_state == em_ffe_config_active)
hw->ffe_config_state = em_ffe_config_enabled;
 1544         if (hw->dsp_config_state == em_dsp_config_activated)
hw->dsp_config_state = em_dsp_config_enabled;
 1547         /* when autonegotiation advertisement is only 1000Mbps then we
 1548           * should disable SmartSpeed and enable Auto MasterSlave
 1549           * resolution as hardware default. */
 1550         if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
 1551             /* Disable SmartSpeed */
ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 1553                                          &phy_data);
 1554             if (ret_val)
 1555                 return ret_val;
phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
phy_data);
 1559             if (ret_val)
 1560                 return ret_val;
 1561             /* Set auto Master/Slave resolution process */
ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
 1563             if (ret_val)
 1564                 return ret_val;
phy_data &= ~CR_1000T_MS_ENABLE;
ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
 1567             if (ret_val)
 1568                 return ret_val;
 1569         }
ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
 1572         if (ret_val)
 1573             return ret_val;
 1575         /* load defaults for future use */
hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
 1577                                         ((phy_data & CR_1000T_MS_VALUE) ?
em_ms_force_master :
em_ms_force_slave) :
em_ms_auto;
 1582         switch (phy_ms_setting) {
 1583         case em_ms_force_master:
phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
 1585             break;
 1586         case em_ms_force_slave:
phy_data |= CR_1000T_MS_ENABLE;
phy_data &= ~(CR_1000T_MS_VALUE);
 1589             break;
 1590         case em_ms_auto:
phy_data &= ~CR_1000T_MS_ENABLE;
 1592             break;
 1593         default:
 1594             break;
 1595         }
ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
 1597         if (ret_val)
 1598             return ret_val;
 1599     }
 1601     return E1000_SUCCESS;
 1602 }
 1604 /********************************************************************
 1605 * Copper link setup for em_phy_gg82563 series.
 1606 *
 1607 * hw - Struct containing variables accessed by shared code
 1608 *********************************************************************/
 1609 static int32_t
em_copper_link_ggp_setup(struct em_hw *hw)
 1611 {
int32_t ret_val;
uint16_t phy_data;
uint32_t reg_data;
DEBUGFUNC("em_copper_link_ggp_setup");
 1618     if (!hw->phy_reset_disable) {
 1620         /* Enable CRS on TX for half-duplex operation. */
ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
 1622                                      &phy_data);
 1623         if (ret_val)
 1624             return ret_val;
phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 1627         /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
phy_data);
 1632         if (ret_val)
 1633             return ret_val;
 1635         /* Options:
 1636          *   MDI/MDI-X = 0 (default)
 1637          *   0 - Auto for all speeds
 1638          *   1 - MDI mode
 1639          *   2 - MDI-X mode
 1640          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
 1641          */
ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
 1643         if (ret_val)
 1644             return ret_val;
phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
 1648         switch (hw->mdix) {
 1649         case 1:
phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
 1651             break;
 1652         case 2:
phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
 1654             break;
 1655         case 0:
 1656         default:
phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
 1658             break;
 1659         }
 1661         /* Options:
 1662          *   disable_polarity_correction = 0 (default)
 1663          *       Automatic Correction for Reversed Cable Polarity
 1664          *   0 - Disabled
 1665          *   1 - Enabled
 1666          */
phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
 1668         if (hw->disable_polarity_correction == 1)
phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
 1672         if (ret_val)
 1673             return ret_val;
 1675         /* SW Reset the PHY so all changes take effect */
ret_val = em_phy_reset(hw);
 1677         if (ret_val) {
DEBUGOUT("Error Resetting the PHY\n");
 1679             return ret_val;
 1680         }
 1681     } /* phy_reset_disable */
 1683     if (hw->mac_type == em_80003es2lan) {
 1684         /* Bypass RX and TX FIFO's */
ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
 1688         if (ret_val)
 1689             return ret_val;
ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
 1692         if (ret_val)
 1693             return ret_val;
phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
 1698         if (ret_val)
 1699             return ret_val;
reg_data = E1000_READ_REG(hw, CTRL_EXT);
reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
ret_val = em_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
 1706                                           &phy_data);
 1707         if (ret_val)
 1708             return ret_val;
 1710         /* Do not init these registers when the HW is in IAMT mode, since the
 1711          * firmware will have already initialized them.  We only initialize
 1712          * them if the HW is not in IAMT mode.
 1713          */
 1714         if (em_check_mng_mode(hw) == FALSE) {
 1715             /* Enable Electrical Idle on the PHY */
phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
ret_val = em_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
phy_data);
 1719             if (ret_val)
 1720                 return ret_val;
ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
 1723                                          &phy_data);
 1724             if (ret_val)
 1725                 return ret_val;
phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
phy_data);
 1731             if (ret_val)
 1732                 return ret_val;
 1733         }
 1735         /* Workaround: Disable padding in Kumeran interface in the MAC
 1736          * and in the PHY to avoid CRC errors.
 1737          */
ret_val = em_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
 1739                                      &phy_data);
 1740         if (ret_val)
 1741             return ret_val;
phy_data |= GG82563_ICR_DIS_PADDING;
ret_val = em_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
phy_data);
 1745         if (ret_val)
 1746             return ret_val;
 1747     }
 1749     return E1000_SUCCESS;
 1750 }
 1752 /********************************************************************
 1753 * Copper link setup for em_phy_m88 series.
 1754 *
 1755 * hw - Struct containing variables accessed by shared code
 1756 *********************************************************************/
 1757 static int32_t
em_copper_link_mgp_setup(struct em_hw *hw)
 1759 {
int32_t ret_val;
uint16_t phy_data;
DEBUGFUNC("em_copper_link_mgp_setup");
 1765     if (hw->phy_reset_disable)
 1766         return E1000_SUCCESS;
 1768     /* Enable CRS on TX. This must be set for half-duplex operation. */
ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
 1770     if (ret_val)
 1771         return ret_val;
phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
 1775     /* Options:
 1776      *   MDI/MDI-X = 0 (default)
 1777      *   0 - Auto for all speeds
 1778      *   1 - MDI mode
 1779      *   2 - MDI-X mode
 1780      *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
 1781      */
phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
 1784     switch (hw->mdix) {
 1785     case 1:
phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
 1787         break;
 1788     case 2:
phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
 1790         break;
 1791     case 3:
phy_data |= M88E1000_PSCR_AUTO_X_1000T;
 1793         break;
 1794     case 0:
 1795     default:
phy_data |= M88E1000_PSCR_AUTO_X_MODE;
 1797         break;
 1798     }
 1800     /* Options:
 1801      *   disable_polarity_correction = 0 (default)
 1802      *       Automatic Correction for Reversed Cable Polarity
 1803      *   0 - Disabled
 1804      *   1 - Enabled
 1805      */
phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
 1807     if (hw->disable_polarity_correction == 1)
phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
 1810     if (ret_val)
 1811         return ret_val;
 1813     if (hw->phy_revision < M88E1011_I_REV_4) {
 1814         /* Force TX_CLK in the Extended PHY Specific Control Register
 1815          * to 25MHz clock.
 1816          */
ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
 1818         if (ret_val)
 1819             return ret_val;
phy_data |= M88E1000_EPSCR_TX_CLK_25;
 1823         if ((hw->phy_revision == E1000_REVISION_2) &&
 1824             (hw->phy_id == M88E1111_I_PHY_ID)) {
 1825             /* Vidalia Phy, set the downshift counter to 5x */
phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
ret_val = em_write_phy_reg(hw,
M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
 1830             if (ret_val)
 1831                 return ret_val;
 1832         } else {
 1833             /* Configure Master and Slave downshift values */
phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
ret_val = em_write_phy_reg(hw,
M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
 1840             if (ret_val)
 1841                return ret_val;
 1842         }
 1843     }
 1845     /* SW Reset the PHY so all changes take effect */
ret_val = em_phy_reset(hw);
 1847     if (ret_val) {
DEBUGOUT("Error Resetting the PHY\n");
 1849         return ret_val;
 1850     }
 1852    return E1000_SUCCESS;
 1853 }
 1855 /********************************************************************
 1856 * Setup auto-negotiation and flow control advertisements,
 1857 * and then perform auto-negotiation.
 1858 *
 1859 * hw - Struct containing variables accessed by shared code
 1860 *********************************************************************/
 1861 static int32_t
em_copper_link_autoneg(struct em_hw *hw)
 1863 {
int32_t ret_val;
uint16_t phy_data;
DEBUGFUNC("em_copper_link_autoneg");
 1869     /* Perform some bounds checking on the hw->autoneg_advertised
 1870      * parameter.  If this variable is zero, then set it to the default.
 1871      */
hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
 1874     /* If autoneg_advertised is zero, we assume it was not defaulted
 1875      * by the calling code so we set to advertise full capability.
 1876      */
 1877     if (hw->autoneg_advertised == 0)
hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 1880     /* IFE phy only supports 10/100 */
 1881     if (hw->phy_type == em_phy_ife)
hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
ret_val = em_phy_setup_autoneg(hw);
 1886     if (ret_val) {
DEBUGOUT("Error Setting up Auto-Negotiation\n");
 1888         return ret_val;
 1889     }
DEBUGOUT("Restarting Auto-Neg\n");
 1892     /* Restart auto-negotiation by setting the Auto Neg Enable bit and
 1893      * the Auto Neg Restart bit in the PHY control register.
 1894      */
ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data);
 1896     if (ret_val)
 1897         return ret_val;
phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data);
 1901     if (ret_val)
 1902         return ret_val;
 1904     /* Does the user want to wait for Auto-Neg to complete here, or
 1905      * check at a later time (for example, callback routine).
 1906      */
 1907     if (hw->wait_autoneg_complete) {
ret_val = em_wait_autoneg(hw);
 1909         if (ret_val) {
DEBUGOUT("Error while waiting for autoneg to complete\n");
 1911             return ret_val;
 1912         }
 1913     }
hw->get_link_status = TRUE;
 1917     return E1000_SUCCESS;
 1918 }
 1920 /******************************************************************************
 1921 * Config the MAC and the PHY after link is up.
 1922 *   1) Set up the MAC to the current PHY speed/duplex
 1923 *      if we are on 82543.  If we
 1924 *      are on newer silicon, we only need to configure
 1925 *      collision distance in the Transmit Control Register.
 1926 *   2) Set up flow control on the MAC to that established with
 1927 *      the link partner.
 1928 *   3) Config DSP to improve Gigabit link quality for some PHY revisions.
 1929 *
 1930 * hw - Struct containing variables accessed by shared code
 1931 ******************************************************************************/
 1932 static int32_t
em_copper_link_postconfig(struct em_hw *hw)
 1934 {
int32_t ret_val;
DEBUGFUNC("em_copper_link_postconfig");
 1938     if (hw->mac_type >= em_82544) {
em_config_collision_dist(hw);
 1940     } else {
ret_val = em_config_mac_to_phy(hw);
 1942         if (ret_val) {
DEBUGOUT("Error configuring MAC to PHY settings\n");
 1944             return ret_val;
 1945         }
 1946     }
ret_val = em_config_fc_after_link_up(hw);
 1948     if (ret_val) {
DEBUGOUT("Error Configuring Flow Control\n");
 1950         return ret_val;
 1951     }
 1953     /* Config DSP to improve Giga link quality */
 1954     if (hw->phy_type == em_phy_igp) {
ret_val = em_config_dsp_after_link_change(hw, TRUE);
 1956         if (ret_val) {
DEBUGOUT("Error Configuring DSP after link up\n");
 1958             return ret_val;
 1959         }
 1960     }
 1962     return E1000_SUCCESS;
 1963 }
 1965 /******************************************************************************
 1966 * Detects which PHY is present and setup the speed and duplex
 1967 *
 1968 * hw - Struct containing variables accessed by shared code
 1969 ******************************************************************************/
 1970 static int32_t
em_setup_copper_link(struct em_hw *hw)
 1972 {
int32_t ret_val;
uint16_t i;
uint16_t phy_data;
uint16_t reg_data;
DEBUGFUNC("em_setup_copper_link");
 1980     switch (hw->mac_type) {
 1981     case em_80003es2lan:
 1982     case em_ich8lan:
 1983         /* Set the mac to wait the maximum time between each
 1984          * iteration and increase the max iterations when
 1985          * polling the phy; this fixes erroneous timeouts at 10Mbps. */
ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
 1987         if (ret_val)
 1988             return ret_val;
ret_val = em_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
 1990         if (ret_val)
 1991             return ret_val;
reg_data |= 0x3F;
ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
 1994         if (ret_val)
 1995             return ret_val;
 1996     default:
 1997         break;
 1998     }
 2000     /* Check if it is a valid PHY and set PHY mode if necessary. */
ret_val = em_copper_link_preconfig(hw);
 2002     if (ret_val)
 2003         return ret_val;
 2005     switch (hw->mac_type) {
 2006     case em_80003es2lan:
 2007         /* Kumeran registers are written-only */
reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
reg_data);
 2012         if (ret_val)
 2013             return ret_val;
 2014         break;
 2015     default:
 2016         break;
 2017     }
 2019     if (hw->phy_type == em_phy_igp ||
hw->phy_type == em_phy_igp_3 ||
hw->phy_type == em_phy_igp_2) {
ret_val = em_copper_link_igp_setup(hw);
 2023         if (ret_val)
 2024             return ret_val;
 2025     } else if (hw->phy_type == em_phy_m88) {
ret_val = em_copper_link_mgp_setup(hw);
 2027         if (ret_val)
 2028             return ret_val;
 2029     } else if (hw->phy_type == em_phy_gg82563) {
ret_val = em_copper_link_ggp_setup(hw);
 2031         if (ret_val)
 2032             return ret_val;
 2033     }
 2035     if (hw->autoneg) {
 2036         /* Setup autoneg and flow control advertisement
 2037           * and perform autonegotiation */
ret_val = em_copper_link_autoneg(hw);
 2039         if (ret_val)
 2040             return ret_val;
 2041     } else {
 2042         /* PHY will be set to 10H, 10F, 100H,or 100F
 2043           * depending on value from forced_speed_duplex. */
DEBUGOUT("Forcing speed and duplex\n");
ret_val = em_phy_force_speed_duplex(hw);
 2046         if (ret_val) {
DEBUGOUT("Error Forcing Speed and Duplex\n");
 2048             return ret_val;
 2049         }
 2050     }
 2052     /* Check link status. Wait up to 100 microseconds for link to become
 2053      * valid.
 2054      */
 2055     for (i = 0; i < 10; i++) {
ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
 2057         if (ret_val)
 2058             return ret_val;
ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
 2060         if (ret_val)
 2061             return ret_val;
 2063         if (phy_data & MII_SR_LINK_STATUS) {
 2064             /* Config the MAC and PHY after link is up */
ret_val = em_copper_link_postconfig(hw);
 2066             if (ret_val)
 2067                 return ret_val;
DEBUGOUT("Valid link established!!!\n");
 2070             return E1000_SUCCESS;
 2071         }
usec_delay(10);
 2073     }
DEBUGOUT("Unable to establish link!!!\n");
 2076     return E1000_SUCCESS;
 2077 }
 2079 /******************************************************************************
 2080 * Configure the MAC-to-PHY interface for 10/100Mbps
 2081 *
 2082 * hw - Struct containing variables accessed by shared code
 2083 ******************************************************************************/
 2084 static int32_t
em_configure_kmrn_for_10_100(struct em_hw *hw, uint16_t duplex)
 2086 {
int32_t ret_val = E1000_SUCCESS;
uint32_t tipg;
uint16_t reg_data;
DEBUGFUNC("em_configure_kmrn_for_10_100");
reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
reg_data);
 2096     if (ret_val)
 2097         return ret_val;
 2099     /* Configure Transmit Inter-Packet Gap */
tipg = E1000_READ_REG(hw, TIPG);
tipg &= ~E1000_TIPG_IPGT_MASK;
tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
E1000_WRITE_REG(hw, TIPG, tipg);
ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
 2107     if (ret_val)
 2108         return ret_val;
 2110     if (duplex == HALF_DUPLEX)
reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
 2112     else
reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
 2117     return ret_val;
 2118 }
 2120 static int32_t
em_configure_kmrn_for_1000(struct em_hw *hw)
 2122 {
int32_t ret_val = E1000_SUCCESS;
uint16_t reg_data;
uint32_t tipg;
DEBUGFUNC("em_configure_kmrn_for_1000");
reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
reg_data);
 2132     if (ret_val)
 2133         return ret_val;
 2135     /* Configure Transmit Inter-Packet Gap */
tipg = E1000_READ_REG(hw, TIPG);
tipg &= ~E1000_TIPG_IPGT_MASK;
tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
E1000_WRITE_REG(hw, TIPG, tipg);
ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
 2143     if (ret_val)
 2144         return ret_val;
reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
 2149     return ret_val;
 2150 }
 2152 /******************************************************************************
 2153 * Configures PHY autoneg and flow control advertisement settings
 2154 *
 2155 * hw - Struct containing variables accessed by shared code
 2156 ******************************************************************************/
int32_t
em_phy_setup_autoneg(struct em_hw *hw)
 2159 {
int32_t ret_val;
uint16_t mii_autoneg_adv_reg;
uint16_t mii_1000t_ctrl_reg;
DEBUGFUNC("em_phy_setup_autoneg");
 2166     /* Read the MII Auto-Neg Advertisement Register (Address 4). */
ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
 2168     if (ret_val)
 2169         return ret_val;
 2171     if (hw->phy_type != em_phy_ife) {
 2172         /* Read the MII 1000Base-T Control Register (Address 9). */
ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
 2174         if (ret_val)
 2175             return ret_val;
 2176     } else
mii_1000t_ctrl_reg=0;
 2179     /* Need to parse both autoneg_advertised and fc and set up
 2180      * the appropriate PHY registers.  First we will parse for
 2181      * autoneg_advertised software override.  Since we can advertise
 2182      * a plethora of combinations, we need to check each bit
 2183      * individually.
 2184      */
 2186     /* First we clear all the 10/100 mb speed bits in the Auto-Neg
 2187      * Advertisement Register (Address 4) and the 1000 mb speed bits in
 2188      * the  1000Base-T Control Register (Address 9).
 2189      */
mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
 2195     /* Do we want to advertise 10 Mb Half Duplex? */
 2196     if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
DEBUGOUT("Advertise 10mb Half duplex\n");
mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
 2199     }
 2201     /* Do we want to advertise 10 Mb Full Duplex? */
 2202     if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
DEBUGOUT("Advertise 10mb Full duplex\n");
mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
 2205     }
 2207     /* Do we want to advertise 100 Mb Half Duplex? */
 2208     if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
DEBUGOUT("Advertise 100mb Half duplex\n");
mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
 2211     }
 2213     /* Do we want to advertise 100 Mb Full Duplex? */
 2214     if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
DEBUGOUT("Advertise 100mb Full duplex\n");
mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
 2217     }
 2219     /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
 2220     if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
 2222     }
 2224     /* Do we want to advertise 1000 Mb Full Duplex? */
 2225     if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
DEBUGOUT("Advertise 1000mb Full duplex\n");
mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
 2228         if (hw->phy_type == em_phy_ife) {
DEBUGOUT("em_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
 2230         }
 2231     }
 2233     /* Check for a software override of the flow control settings, and
 2234      * setup the PHY advertisement registers accordingly.  If
 2235      * auto-negotiation is enabled, then software will have to set the
 2236      * "PAUSE" bits to the correct value in the Auto-Negotiation
 2237      * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
 2238      *
 2239      * The possible values of the "fc" parameter are:
 2240      *      0:  Flow control is completely disabled
 2241      *      1:  Rx flow control is enabled (we can receive pause frames
 2242      *          but not send pause frames).
 2243      *      2:  Tx flow control is enabled (we can send pause frames
 2244      *          but we do not support receiving pause frames).
 2245      *      3:  Both Rx and TX flow control (symmetric) are enabled.
 2246      *  other:  No software override.  The flow control configuration
 2247      *          in the EEPROM is used.
 2248      */
 2249     switch (hw->fc) {
 2250     case E1000_FC_NONE: /* 0 */
 2251         /* Flow control (RX & TX) is completely disabled by a
 2252          * software over-ride.
 2253          */
mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
 2255         break;
 2256     case E1000_FC_RX_PAUSE: /* 1 */
 2257         /* RX Flow control is enabled, and TX Flow control is
 2258          * disabled, by a software over-ride.
 2259          */
 2260         /* Since there really isn't a way to advertise that we are
 2261          * capable of RX Pause ONLY, we will advertise that we
 2262          * support both symmetric and asymmetric RX PAUSE.  Later
 2263          * (in em_config_fc_after_link_up) we will disable the
 2264          *hw's ability to send PAUSE frames.
 2265          */
mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
 2267         break;
 2268     case E1000_FC_TX_PAUSE: /* 2 */
 2269         /* TX Flow control is enabled, and RX Flow control is
 2270          * disabled, by a software over-ride.
 2271          */
mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
 2274         break;
 2275     case E1000_FC_FULL: /* 3 */
 2276         /* Flow control (both RX and TX) is enabled by a software
 2277          * over-ride.
 2278          */
mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
 2280         break;
 2281     default:
DEBUGOUT("Flow control param set incorrectly\n");
 2283         return -E1000_ERR_CONFIG;
 2284     }
ret_val = em_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
 2287     if (ret_val)
 2288         return ret_val;
DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
 2292     if (hw->phy_type != em_phy_ife) {
ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
 2294         if (ret_val)
 2295             return ret_val;
 2296     }
 2298     return E1000_SUCCESS;
 2299 }
 2301 /******************************************************************************
 2302 * Force PHY speed and duplex settings to hw->forced_speed_duplex
 2303 *
 2304 * hw - Struct containing variables accessed by shared code
 2305 ******************************************************************************/
 2306 static int32_t
em_phy_force_speed_duplex(struct em_hw *hw)
 2308 {
uint32_t ctrl;
int32_t ret_val;
uint16_t mii_ctrl_reg;
uint16_t mii_status_reg;
uint16_t phy_data;
uint16_t i;
DEBUGFUNC("em_phy_force_speed_duplex");
 2318     /* Turn off Flow control if we are forcing speed and duplex. */
hw->fc = E1000_FC_NONE;
DEBUGOUT1("hw->fc = %d\n", hw->fc);
 2323     /* Read the Device Control Register. */
ctrl = E1000_READ_REG(hw, CTRL);
 2326     /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
ctrl &= ~(DEVICE_SPEED_MASK);
 2330     /* Clear the Auto Speed Detect Enable bit. */
ctrl &= ~E1000_CTRL_ASDE;
 2333     /* Read the MII Control Register. */
ret_val = em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
 2335     if (ret_val)
 2336         return ret_val;
 2338     /* We need to disable autoneg in order to force link and duplex. */
mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
 2342     /* Are we forcing Full or Half Duplex? */
 2343     if (hw->forced_speed_duplex == em_100_full ||
hw->forced_speed_duplex == em_10_full) {
 2345         /* We want to force full duplex so we SET the full duplex bits in the
 2346          * Device and MII Control Registers.
 2347          */
ctrl |= E1000_CTRL_FD;
mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
DEBUGOUT("Full Duplex\n");
 2351     } else {
 2352         /* We want to force half duplex so we CLEAR the full duplex bits in
 2353          * the Device and MII Control Registers.
 2354          */
ctrl &= ~E1000_CTRL_FD;
mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
DEBUGOUT("Half Duplex\n");
 2358     }
 2360     /* Are we forcing 100Mbps??? */
 2361     if (hw->forced_speed_duplex == em_100_full ||
hw->forced_speed_duplex == em_100_half) {
 2363         /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
ctrl |= E1000_CTRL_SPD_100;
mii_ctrl_reg |= MII_CR_SPEED_100;
mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
DEBUGOUT("Forcing 100mb ");
 2368     } else {
 2369         /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
mii_ctrl_reg |= MII_CR_SPEED_10;
mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
DEBUGOUT("Forcing 10mb ");
 2374     }
em_config_collision_dist(hw);
 2378     /* Write the configured values back to the Device Control Reg. */
E1000_WRITE_REG(hw, CTRL, ctrl);
 2381     if ((hw->phy_type == em_phy_m88) ||
 2382         (hw->phy_type == em_phy_gg82563)) {
ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
 2384         if (ret_val)
 2385             return ret_val;
 2387         /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
 2388          * forced whenever speed are duplex are forced.
 2389          */
phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
 2392         if (ret_val)
 2393             return ret_val;
DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
 2397         /* Need to reset the PHY or these changes will be ignored */
mii_ctrl_reg |= MII_CR_RESET;
 2399     /* Disable MDI-X support for 10/100 */
 2400     } else if (hw->phy_type == em_phy_ife) {
ret_val = em_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
 2402         if (ret_val)
 2403             return ret_val;
phy_data &= ~IFE_PMC_AUTO_MDIX;
phy_data &= ~IFE_PMC_FORCE_MDIX;
ret_val = em_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
 2409         if (ret_val)
 2410             return ret_val;
 2411     } else {
 2412         /* Clear Auto-Crossover to force MDI manually.  IGP requires MDI
 2413          * forced whenever speed or duplex are forced.
 2414          */
ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
 2416         if (ret_val)
 2417             return ret_val;
phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
 2423         if (ret_val)
 2424             return ret_val;
 2425     }
 2427     /* Write back the modified PHY MII control register. */
ret_val = em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
 2429     if (ret_val)
 2430         return ret_val;
usec_delay(1);
 2434     /* The wait_autoneg_complete flag may be a little misleading here.
 2435      * Since we are forcing speed and duplex, Auto-Neg is not enabled.
 2436      * But we do want to delay for a period while forcing only so we
 2437      * don't generate false No Link messages.  So we will wait here
 2438      * only if the user has set wait_autoneg_complete to 1, which is
 2439      * the default.
 2440      */
 2441     if (hw->wait_autoneg_complete) {
 2442         /* We will wait for autoneg to complete. */
DEBUGOUT("Waiting for forced speed/duplex link.\n");
mii_status_reg = 0;
 2446         /* We will wait for autoneg to complete or 4.5 seconds to expire. */
 2447         for (i = PHY_FORCE_TIME; i > 0; i--) {
 2448             /* Read the MII Status Register and wait for Auto-Neg Complete bit
 2449              * to be set.
 2450              */
ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
 2452             if (ret_val)
 2453                 return ret_val;
ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
 2456             if (ret_val)
 2457                 return ret_val;
 2459             if (mii_status_reg & MII_SR_LINK_STATUS) break;
msec_delay(100);
 2461         }
 2462         if ((i == 0) &&
 2463            ((hw->phy_type == em_phy_m88) ||
 2464             (hw->phy_type == em_phy_gg82563))) {
 2465             /* We didn't get link.  Reset the DSP and wait again for link. */
ret_val = em_phy_reset_dsp(hw);
 2467             if (ret_val) {
DEBUGOUT("Error Resetting PHY DSP\n");
 2469                 return ret_val;
 2470             }
 2471         }
 2472         /* This loop will early-out if the link condition has been met.  */
 2473         for (i = PHY_FORCE_TIME; i > 0; i--) {
 2474             if (mii_status_reg & MII_SR_LINK_STATUS) break;
msec_delay(100);
 2476             /* Read the MII Status Register and wait for Auto-Neg Complete bit
 2477              * to be set.
 2478              */
ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
 2480             if (ret_val)
 2481                 return ret_val;
ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
 2484             if (ret_val)
 2485                 return ret_val;
 2486         }
 2487     }
 2489     if (hw->phy_type == em_phy_m88) {
 2490         /* Because we reset the PHY above, we need to re-force TX_CLK in the
 2491          * Extended PHY Specific Control Register to 25MHz clock.  This value
 2492          * defaults back to a 2.5MHz clock when the PHY is reset.
 2493          */
ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
 2495         if (ret_val)
 2496             return ret_val;
phy_data |= M88E1000_EPSCR_TX_CLK_25;
ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
 2500         if (ret_val)
 2501             return ret_val;
 2503         /* In addition, because of the s/w reset above, we need to enable CRS on
 2504          * TX.  This must be set for both full and half duplex operation.
 2505          */
ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
 2507         if (ret_val)
 2508             return ret_val;
phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
 2512         if (ret_val)
 2513             return ret_val;
 2515         if ((hw->mac_type == em_82544 || hw->mac_type == em_82543) &&
 2516             (!hw->autoneg) && (hw->forced_speed_duplex == em_10_full ||
hw->forced_speed_duplex == em_10_half)) {
ret_val = em_polarity_reversal_workaround(hw);
 2519             if (ret_val)
 2520                 return ret_val;
 2521         }
 2522     } else if (hw->phy_type == em_phy_gg82563) {
 2523         /* The TX_CLK of the Extended PHY Specific Control Register defaults
 2524          * to 2.5MHz on a reset.  We need to re-force it back to 25MHz, if
 2525          * we're not in a forced 10/duplex configuration. */
ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
 2527         if (ret_val)
 2528             return ret_val;
phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
 2531         if ((hw->forced_speed_duplex == em_10_full) ||
 2532             (hw->forced_speed_duplex == em_10_half))
phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
 2534         else
phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
 2537         /* Also due to the reset, we need to enable CRS on Tx. */
phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
 2541         if (ret_val)
 2542             return ret_val;
 2543     }
 2544     return E1000_SUCCESS;
 2545 }
 2547 /******************************************************************************
 2548 * Sets the collision distance in the Transmit Control register
 2549 *
 2550 * hw - Struct containing variables accessed by shared code
 2551 *
 2552 * Link should have been established previously. Reads the speed and duplex
 2553 * information from the Device Status register.
 2554 ******************************************************************************/
 2555 void
em_config_collision_dist(struct em_hw *hw)
 2557 {
uint32_t tctl, coll_dist;
DEBUGFUNC("em_config_collision_dist");
 2562     if (hw->mac_type < em_82543)
coll_dist = E1000_COLLISION_DISTANCE_82542;
 2564     else
coll_dist = E1000_COLLISION_DISTANCE;
tctl = E1000_READ_REG(hw, TCTL);
tctl &= ~E1000_TCTL_COLD;
tctl |= coll_dist << E1000_COLD_SHIFT;
E1000_WRITE_REG(hw, TCTL, tctl);
E1000_WRITE_FLUSH(hw);
 2574 }
 2576 /******************************************************************************
 2577 * Sets MAC speed and duplex settings to reflect the those in the PHY
 2578 *
 2579 * hw - Struct containing variables accessed by shared code
 2580 * mii_reg - data to write to the MII control register
 2581 *
 2582 * The contents of the PHY register containing the needed information need to
 2583 * be passed in.
 2584 ******************************************************************************/
 2585 static int32_t
em_config_mac_to_phy(struct em_hw *hw)
 2587 {
uint32_t ctrl;
int32_t ret_val;
uint16_t phy_data;
DEBUGFUNC("em_config_mac_to_phy");
 2594     /* 82544 or newer MAC, Auto Speed Detection takes care of
 2595     * MAC speed/duplex configuration.*/
 2596     if (hw->mac_type >= em_82544)
 2597         return E1000_SUCCESS;
 2599     /* Read the Device Control Register and set the bits to Force Speed
 2600      * and Duplex.
 2601      */
ctrl = E1000_READ_REG(hw, CTRL);
ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
 2606     /* Set up duplex in the Device Control and Transmit Control
 2607      * registers depending on negotiated values.
 2608      */
ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
 2610     if (ret_val)
 2611         return ret_val;
 2613     if (phy_data & M88E1000_PSSR_DPLX)
ctrl |= E1000_CTRL_FD;
 2615     else
ctrl &= ~E1000_CTRL_FD;
em_config_collision_dist(hw);
 2620     /* Set up speed in the Device Control register depending on
 2621      * negotiated values.
 2622      */
 2623     if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
ctrl |= E1000_CTRL_SPD_1000;
 2625     else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
ctrl |= E1000_CTRL_SPD_100;
 2628     /* Write the configured values back to the Device Control Reg. */
E1000_WRITE_REG(hw, CTRL, ctrl);
 2630     return E1000_SUCCESS;
 2631 }
 2633 /******************************************************************************
 2634  * Forces the MAC's flow control settings.
 2635  *
 2636  * hw - Struct containing variables accessed by shared code
 2637  *
 2638  * Sets the TFCE and RFCE bits in the device control register to reflect
 2639  * the adapter settings. TFCE and RFCE need to be explicitly set by
 2640  * software when a Copper PHY is used because autonegotiation is managed
 2641  * by the PHY rather than the MAC. Software must also configure these
 2642  * bits when link is forced on a fiber connection.
 2643  *****************************************************************************/
int32_t
em_force_mac_fc(struct em_hw *hw)
 2646 {
uint32_t ctrl;
DEBUGFUNC("em_force_mac_fc");
 2651     /* Get the current configuration of the Device Control Register */
ctrl = E1000_READ_REG(hw, CTRL);
 2654     /* Because we didn't get link via the internal auto-negotiation
 2655      * mechanism (we either forced link or we got link via PHY
 2656      * auto-neg), we have to manually enable/disable transmit an
 2657      * receive flow control.
 2658      *
 2659      * The "Case" statement below enables/disable flow control
 2660      * according to the "hw->fc" parameter.
 2661      *
 2662      * The possible values of the "fc" parameter are:
 2663      *      0:  Flow control is completely disabled
 2664      *      1:  Rx flow control is enabled (we can receive pause
 2665      *          frames but not send pause frames).
 2666      *      2:  Tx flow control is enabled (we can send pause frames
 2667      *          frames but we do not receive pause frames).
 2668      *      3:  Both Rx and TX flow control (symmetric) is enabled.
 2669      *  other:  No other values should be possible at this point.
 2670      */
 2672     switch (hw->fc) {
 2673     case E1000_FC_NONE:
ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
 2675         break;
 2676     case E1000_FC_RX_PAUSE:
ctrl &= (~E1000_CTRL_TFCE);
ctrl |= E1000_CTRL_RFCE;
 2679         break;
 2680     case E1000_FC_TX_PAUSE:
ctrl &= (~E1000_CTRL_RFCE);
ctrl |= E1000_CTRL_TFCE;
 2683         break;
 2684     case E1000_FC_FULL:
ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
 2686         break;
 2687     default:
DEBUGOUT("Flow control param set incorrectly\n");
 2689         return -E1000_ERR_CONFIG;
 2690     }
 2692     /* Disable TX Flow Control for 82542 (rev 2.0) */
 2693     if (hw->mac_type == em_82542_rev2_0)
ctrl &= (~E1000_CTRL_TFCE);
E1000_WRITE_REG(hw, CTRL, ctrl);
 2697     return E1000_SUCCESS;
 2698 }
 2700 /******************************************************************************
 2701  * Configures flow control settings after link is established
 2702  *
 2703  * hw - Struct containing variables accessed by shared code
 2704  *
 2705  * Should be called immediately after a valid link has been established.
 2706  * Forces MAC flow control settings if link was forced. When in MII/GMII mode
 2707  * and autonegotiation is enabled, the MAC flow control settings will be set
 2708  * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
 2709  * and RFCE bits will be automaticaly set to the negotiated flow control mode.
 2710  *****************************************************************************/
STATIC int32_t
em_config_fc_after_link_up(struct em_hw *hw)
 2713 {
int32_t ret_val;
uint16_t mii_status_reg;
uint16_t mii_nway_adv_reg;
uint16_t mii_nway_lp_ability_reg;
uint16_t speed;
uint16_t duplex;
DEBUGFUNC("em_config_fc_after_link_up");
 2723     /* Check for the case where we have fiber media and auto-neg failed
 2724      * so we had to force link.  In this case, we need to force the
 2725      * configuration of the MAC to match the "fc" parameter.
 2726      */
 2727     if (((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed)) ||
 2728         ((hw->media_type == em_media_type_internal_serdes) &&
 2729          (hw->autoneg_failed)) ||
 2730         ((hw->media_type == em_media_type_copper) && (!hw->autoneg))) {
ret_val = em_force_mac_fc(hw);
 2732         if (ret_val) {
DEBUGOUT("Error forcing flow control settings\n");
 2734             return ret_val;
 2735         }
 2736     }
 2738     /* Check for the case where we have copper media and auto-neg is
 2739      * enabled.  In this case, we need to check and see if Auto-Neg
 2740      * has completed, and if so, how the PHY and link partner has
 2741      * flow control configured.
 2742      */
 2743     if ((hw->media_type == em_media_type_copper) && hw->autoneg) {
 2744         /* Read the MII Status Register and check to see if AutoNeg
 2745          * has completed.  We read this twice because this reg has
 2746          * some "sticky" (latched) bits.
 2747          */
ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
 2749         if (ret_val)
 2750             return ret_val;
ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
 2752         if (ret_val)
 2753             return ret_val;
 2755         if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
 2756             /* The AutoNeg process has completed, so we now need to
 2757              * read both the Auto Negotiation Advertisement Register
 2758              * (Address 4) and the Auto_Negotiation Base Page Ability
 2759              * Register (Address 5) to determine how flow control was
 2760              * negotiated.
 2761              */
ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV,
 2763                                          &mii_nway_adv_reg);
 2764             if (ret_val)
 2765                 return ret_val;
ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY,
 2767                                          &mii_nway_lp_ability_reg);
 2768             if (ret_val)
 2769                 return ret_val;
 2771             /* Two bits in the Auto Negotiation Advertisement Register
 2772              * (Address 4) and two bits in the Auto Negotiation Base
 2773              * Page Ability Register (Address 5) determine flow control
 2774              * for both the PHY and the link partner.  The following
 2775              * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
 2776              * 1999, describes these PAUSE resolution bits and how flow
 2777              * control is determined based upon these settings.
 2778              * NOTE:  DC = Don't Care
 2779              *
 2780              *   LOCAL DEVICE  |   LINK PARTNER
 2781              * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
 2782              *-------|---------|-------|---------|--------------------
 2783              *   0   |    0    |  DC   |   DC    | em_fc_none
 2784              *   0   |    1    |   0   |   DC    | em_fc_none
 2785              *   0   |    1    |   1   |    0    | em_fc_none
 2786              *   0   |    1    |   1   |    1    | em_fc_tx_pause
 2787              *   1   |    0    |   0   |   DC    | em_fc_none
 2788              *   1   |   DC    |   1   |   DC    | em_fc_full
 2789              *   1   |    1    |   0   |    0    | em_fc_none
 2790              *   1   |    1    |   0   |    1    | em_fc_rx_pause
 2791              *
 2792              */
 2793             /* Are both PAUSE bits set to 1?  If so, this implies
 2794              * Symmetric Flow Control is enabled at both ends.  The
 2795              * ASM_DIR bits are irrelevant per the spec.
 2796              *
 2797              * For Symmetric Flow Control:
 2798              *
 2799              *   LOCAL DEVICE  |   LINK PARTNER
 2800              * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
 2801              *-------|---------|-------|---------|--------------------
 2802              *   1   |   DC    |   1   |   DC    | em_fc_full
 2803              *
 2804              */
 2805             if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
 2806                 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
 2807                 /* Now we need to check if the user selected RX ONLY
 2808                  * of pause frames.  In this case, we had to advertise
 2809                  * FULL flow control because we could not advertise RX
 2810                  * ONLY. Hence, we must now check to see if we need to
 2811                  * turn OFF  the TRANSMISSION of PAUSE frames.
 2812                  */
 2813                 if (hw->original_fc == E1000_FC_FULL) {
hw->fc = E1000_FC_FULL;
DEBUGOUT("Flow Control = FULL.\n");
 2816                 } else {
hw->fc = E1000_FC_RX_PAUSE;
DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
 2819                 }
 2820             }
 2821             /* For receiving PAUSE frames ONLY.
 2822              *
 2823              *   LOCAL DEVICE  |   LINK PARTNER
 2824              * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
 2825              *-------|---------|-------|---------|--------------------
 2826              *   0   |    1    |   1   |    1    | em_fc_tx_pause
 2827              *
 2828              */
 2829             else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
 2830                      (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
 2831                      (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
 2832                      (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
hw->fc = E1000_FC_TX_PAUSE;
DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
 2835             }
 2836             /* For transmitting PAUSE frames ONLY.
 2837              *
 2838              *   LOCAL DEVICE  |   LINK PARTNER
 2839              * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
 2840              *-------|---------|-------|---------|--------------------
 2841              *   1   |    1    |   0   |    1    | em_fc_rx_pause
 2842              *
 2843              */
 2844             else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
 2845                      (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
 2846                      !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
 2847                      (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
hw->fc = E1000_FC_RX_PAUSE;
DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
 2850             }
 2851             /* Per the IEEE spec, at this point flow control should be
 2852              * disabled.  However, we want to consider that we could
 2853              * be connected to a legacy switch that doesn't advertise
 2854              * desired flow control, but can be forced on the link
 2855              * partner.  So if we advertised no flow control, that is
 2856              * what we will resolve to.  If we advertised some kind of
 2857              * receive capability (Rx Pause Only or Full Flow Control)
 2858              * and the link partner advertised none, we will configure
 2859              * ourselves to enable Rx Flow Control only.  We can do
 2860              * this safely for two reasons:  If the link partner really
 2861              * didn't want flow control enabled, and we enable Rx, no
 2862              * harm done since we won't be receiving any PAUSE frames
 2863              * anyway.  If the intent on the link partner was to have
 2864              * flow control enabled, then by us enabling RX only, we
 2865              * can at least receive pause frames and process them.
 2866              * This is a good idea because in most cases, since we are
 2867              * predominantly a server NIC, more times than not we will
 2868              * be asked to delay transmission of packets than asking
 2869              * our link partner to pause transmission of frames.
 2870              */
 2871             else if ((hw->original_fc == E1000_FC_NONE||
hw->original_fc == E1000_FC_TX_PAUSE) ||
hw->fc_strict_ieee) {
hw->fc = E1000_FC_NONE;
DEBUGOUT("Flow Control = NONE.\n");
 2876             } else {
hw->fc = E1000_FC_RX_PAUSE;
DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
 2879             }
 2881             /* Now we need to do one last check...  If we auto-
 2882              * negotiated to HALF DUPLEX, flow control should not be
 2883              * enabled per IEEE 802.3 spec.
 2884              */
ret_val = em_get_speed_and_duplex(hw, &speed, &duplex);
 2886             if (ret_val) {
DEBUGOUT("Error getting link speed and duplex\n");
 2888                 return ret_val;
 2889             }
 2891             if (duplex == HALF_DUPLEX)
hw->fc = E1000_FC_NONE;
 2894             /* Now we call a subroutine to actually force the MAC
 2895              * controller to use the correct flow control settings.
 2896              */
ret_val = em_force_mac_fc(hw);
 2898             if (ret_val) {
DEBUGOUT("Error forcing flow control settings\n");
 2900                 return ret_val;
 2901             }
 2902         } else {
DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
 2904         }
 2905     }
 2906     return E1000_SUCCESS;
 2907 }
 2909 /******************************************************************************
 2910  * Checks to see if the link status of the hardware has changed.
 2911  *
 2912  * hw - Struct containing variables accessed by shared code
 2913  *
 2914  * Called by any function that needs to check the link status of the adapter.
 2915  *****************************************************************************/
int32_t
em_check_for_link(struct em_hw *hw)
 2918 {
uint32_t rxcw = 0;
uint32_t ctrl;
uint32_t status;
uint32_t rctl;
uint32_t icr;
uint32_t signal = 0;
int32_t ret_val;
uint16_t phy_data;
DEBUGFUNC("em_check_for_link");
ctrl = E1000_READ_REG(hw, CTRL);
status = E1000_READ_REG(hw, STATUS);
 2933     /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
 2934      * set when the optics detect a signal. On older adapters, it will be
 2935      * cleared when there is a signal.  This applies to fiber media only.
 2936      */
 2937     if ((hw->media_type == em_media_type_fiber) ||
 2938         (hw->media_type == em_media_type_internal_serdes)) {
rxcw = E1000_READ_REG(hw, RXCW);
 2941         if (hw->media_type == em_media_type_fiber) {
signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0;
 2943             if (status & E1000_STATUS_LU)
hw->get_link_status = FALSE;
 2945         }
 2946     }
 2948     /* If we have a copper PHY then we only want to go out to the PHY
 2949      * registers to see if Auto-Neg has completed and/or if our link
 2950      * status has changed.  The get_link_status flag will be set if we
 2951      * receive a Link Status Change interrupt or we have Rx Sequence
 2952      * Errors.
 2953      */
 2954     if ((hw->media_type == em_media_type_copper) && hw->get_link_status) {
 2955         /* First we want to see if the MII Status Register reports
 2956          * link.  If so, then we want to get the current speed/duplex
 2957          * of the PHY.
 2958          * Read the register twice since the link bit is sticky.
 2959          */
ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
 2961         if (ret_val)
 2962             return ret_val;
ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
 2964         if (ret_val)
 2965             return ret_val;
 2967         if (phy_data & MII_SR_LINK_STATUS) {
hw->get_link_status = FALSE;
 2969             /* Check if there was DownShift, must be checked immediately after
 2970              * link-up */
em_check_downshift(hw);
 2973             /* If we are on 82544 or 82543 silicon and speed/duplex
 2974              * are forced to 10H or 10F, then we will implement the polarity
 2975              * reversal workaround.  We disable interrupts first, and upon
 2976              * returning, place the devices interrupt state to its previous
 2977              * value except for the link status change interrupt which will
 2978              * happen due to the execution of this workaround.
 2979              */
 2981             if ((hw->mac_type == em_82544 || hw->mac_type == em_82543) &&
 2982                 (!hw->autoneg) &&
 2983                 (hw->forced_speed_duplex == em_10_full ||
hw->forced_speed_duplex == em_10_half)) {
E1000_WRITE_REG(hw, IMC, 0xffffffff);
ret_val = em_polarity_reversal_workaround(hw);
icr = E1000_READ_REG(hw, ICR);
E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC));
E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK);
 2990             }
 2992         } else {
 2993             /* No link detected */
em_config_dsp_after_link_change(hw, FALSE);
 2995             return 0;
 2996         }
 2998         /* If we are forcing speed/duplex, then we simply return since
 2999          * we have already determined whether we have link or not.
 3000          */
 3001         if (!hw->autoneg) return -E1000_ERR_CONFIG;
 3003         /* optimize the dsp settings for the igp phy */
em_config_dsp_after_link_change(hw, TRUE);
 3006         /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
 3007          * have Si on board that is 82544 or newer, Auto
 3008          * Speed Detection takes care of MAC speed/duplex
 3009          * configuration.  So we only need to configure Collision
 3010          * Distance in the MAC.  Otherwise, we need to force
 3011          * speed/duplex on the MAC to the current PHY speed/duplex
 3012          * settings.
 3013          */
 3014         if (hw->mac_type >= em_82544)
em_config_collision_dist(hw);
 3016         else {
ret_val = em_config_mac_to_phy(hw);
 3018             if (ret_val) {
DEBUGOUT("Error configuring MAC to PHY settings\n");
 3020                 return ret_val;
 3021             }
 3022         }
 3024         /* Configure Flow Control now that Auto-Neg has completed. First, we
 3025          * need to restore the desired flow control settings because we may
 3026          * have had to re-autoneg with a different link partner.
 3027          */
ret_val = em_config_fc_after_link_up(hw);
 3029         if (ret_val) {
DEBUGOUT("Error configuring flow control\n");
 3031             return ret_val;
 3032         }
 3034         /* At this point we know that we are on copper and we have
 3035          * auto-negotiated link.  These are conditions for checking the link
 3036          * partner capability register.  We use the link speed to determine if
 3037          * TBI compatibility needs to be turned on or off.  If the link is not
 3038          * at gigabit speed, then TBI compatibility is not needed.  If we are
 3039          * at gigabit speed, we turn on TBI compatibility.
 3040          */
 3041         if (hw->tbi_compatibility_en) {
uint16_t speed, duplex;
ret_val = em_get_speed_and_duplex(hw, &speed, &duplex);
 3044             if (ret_val) {
DEBUGOUT("Error getting link speed and duplex\n");
 3046                 return ret_val;
 3047             }
 3048             if (speed != SPEED_1000) {
 3049                 /* If link speed is not set to gigabit speed, we do not need
 3050                  * to enable TBI compatibility.
 3051                  */
 3052                 if (hw->tbi_compatibility_on) {
 3053                     /* If we previously were in the mode, turn it off. */
rctl = E1000_READ_REG(hw, RCTL);
rctl &= ~E1000_RCTL_SBP;
E1000_WRITE_REG(hw, RCTL, rctl);
hw->tbi_compatibility_on = FALSE;
 3058                 }
 3059             } else {
 3060                 /* If TBI compatibility is was previously off, turn it on. For
 3061                  * compatibility with a TBI link partner, we will store bad
 3062                  * packets. Some frames have an additional byte on the end and
 3063                  * will look like CRC errors to to the hardware.
 3064                  */
 3065                 if (!hw->tbi_compatibility_on) {
hw->tbi_compatibility_on = TRUE;
rctl = E1000_READ_REG(hw, RCTL);
rctl |= E1000_RCTL_SBP;
E1000_WRITE_REG(hw, RCTL, rctl);
 3070                 }
 3071             }
 3072         }
 3073     }
 3074     /* If we don't have link (auto-negotiation failed or link partner cannot
 3075      * auto-negotiate), the cable is plugged in (we have signal), and our
 3076      * link partner is not trying to auto-negotiate with us (we are receiving
 3077      * idles or data), we need to force link up. We also need to give
 3078      * auto-negotiation time to complete, in case the cable was just plugged
 3079      * in. The autoneg_failed flag does this.
 3080      */
 3081     else if ((((hw->media_type == em_media_type_fiber) &&
 3082               ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
 3083               (hw->media_type == em_media_type_internal_serdes)) &&
 3084               (!(status & E1000_STATUS_LU)) &&
 3085               (!(rxcw & E1000_RXCW_C))) {
 3086         if (hw->autoneg_failed == 0) {
hw->autoneg_failed = 1;
 3088             return 0;
 3089         }
DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
 3092         /* Disable auto-negotiation in the TXCW register */
E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
 3095         /* Force link-up and also force full-duplex. */
ctrl = E1000_READ_REG(hw, CTRL);
ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
E1000_WRITE_REG(hw, CTRL, ctrl);
 3100         /* Configure Flow Control after forcing link up. */
ret_val = em_config_fc_after_link_up(hw);
 3102         if (ret_val) {
DEBUGOUT("Error configuring flow control\n");
 3104             return ret_val;
 3105         }
 3106     }
 3107     /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
 3108      * auto-negotiation in the TXCW register and disable forced link in the
 3109      * Device Control register in an attempt to auto-negotiate with our link
 3110      * partner.
 3111      */
 3112     else if (((hw->media_type == em_media_type_fiber) ||
 3113               (hw->media_type == em_media_type_internal_serdes)) &&
 3114               (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
E1000_WRITE_REG(hw, TXCW, hw->txcw);
E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
hw->serdes_link_down = FALSE;
 3120     }
 3121     /* If we force link for non-auto-negotiation switch, check link status
 3122      * based on MAC synchronization for internal serdes media type.
 3123      */
 3124     else if ((hw->media_type == em_media_type_internal_serdes) &&
 3125              !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
 3126         /* SYNCH bit and IV bit are sticky. */
usec_delay(10);
 3128         if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
 3129             if (!(rxcw & E1000_RXCW_IV)) {
hw->serdes_link_down = FALSE;
DEBUGOUT("SERDES: Link is up.\n");
 3132             }
 3133         } else {
hw->serdes_link_down = TRUE;
DEBUGOUT("SERDES: Link is down.\n");
 3136         }
 3137     }
 3138     if ((hw->media_type == em_media_type_internal_serdes) &&
 3139         (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
 3141     }
 3142     return E1000_SUCCESS;
 3143 }
 3145 /******************************************************************************
 3146  * Detects the current speed and duplex settings of the hardware.
 3147  *
 3148  * hw - Struct containing variables accessed by shared code
 3149  * speed - Speed of the connection
 3150  * duplex - Duplex setting of the connection
 3151  *****************************************************************************/
int32_t
em_get_speed_and_duplex(struct em_hw *hw,
uint16_t *speed,
uint16_t *duplex)
 3156 {
uint32_t status;
int32_t ret_val;
uint16_t phy_data;
DEBUGFUNC("em_get_speed_and_duplex");
 3163     if (hw->mac_type >= em_82543) {
status = E1000_READ_REG(hw, STATUS);
 3165         if (status & E1000_STATUS_SPEED_1000) {
 3166             *speed = SPEED_1000;
DEBUGOUT("1000 Mbs, ");
 3168         } else if (status & E1000_STATUS_SPEED_100) {
 3169             *speed = SPEED_100;
DEBUGOUT("100 Mbs, ");
 3171         } else {
 3172             *speed = SPEED_10;
DEBUGOUT("10 Mbs, ");
 3174         }
 3176         if (status & E1000_STATUS_FD) {
 3177             *duplex = FULL_DUPLEX;
DEBUGOUT("Full Duplex\n");
 3179         } else {
 3180             *duplex = HALF_DUPLEX;
DEBUGOUT(" Half Duplex\n");
 3182         }
 3183     } else {
DEBUGOUT("1000 Mbs, Full Duplex\n");
 3185         *speed = SPEED_1000;
 3186         *duplex = FULL_DUPLEX;
 3187     }
 3189     /* IGP01 PHY may advertise full duplex operation after speed downgrade even
 3190      * if it is operating at half duplex.  Here we set the duplex settings to
 3191      * match the duplex in the link partner's capabilities.
 3192      */
 3193     if (hw->phy_type == em_phy_igp && hw->speed_downgraded) {
ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
 3195         if (ret_val)
 3196             return ret_val;
 3198         if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
 3199             *duplex = HALF_DUPLEX;
 3200         else {
ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
 3202             if (ret_val)
 3203                 return ret_val;
 3204             if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
 3205                (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
 3206                 *duplex = HALF_DUPLEX;
 3207         }
 3208     }
 3210     if ((hw->mac_type == em_80003es2lan) &&
 3211         (hw->media_type == em_media_type_copper)) {
 3212         if (*speed == SPEED_1000)
ret_val = em_configure_kmrn_for_1000(hw);
 3214         else
ret_val = em_configure_kmrn_for_10_100(hw, *duplex);
 3216         if (ret_val)
 3217             return ret_val;
 3218     }
 3220     if ((hw->phy_type == em_phy_igp_3) && (*speed == SPEED_1000)) {
ret_val = em_kumeran_lock_loss_workaround(hw);
 3222         if (ret_val)
 3223             return ret_val;
 3224     }
 3226     return E1000_SUCCESS;
 3227 }
 3229 /******************************************************************************
 3230 * Blocks until autoneg completes or times out (~4.5 seconds)
 3231 *
 3232 * hw - Struct containing variables accessed by shared code
 3233 ******************************************************************************/
STATIC int32_t
em_wait_autoneg(struct em_hw *hw)
 3236 {
int32_t ret_val;
uint16_t i;
uint16_t phy_data;
DEBUGFUNC("em_wait_autoneg");
DEBUGOUT("Waiting for Auto-Neg to complete.\n");
 3244     /* We will wait for autoneg to complete or 4.5 seconds to expire. */
 3245     for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
 3246         /* Read the MII Status Register and wait for Auto-Neg
 3247          * Complete bit to be set.
 3248          */
ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
 3250         if (ret_val)
 3251             return ret_val;
ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
 3253         if (ret_val)
 3254             return ret_val;
 3255         if (phy_data & MII_SR_AUTONEG_COMPLETE) {
 3256             return E1000_SUCCESS;
 3257         }
msec_delay(100);
 3259     }
 3260     return E1000_SUCCESS;
 3261 }
 3263 /******************************************************************************
 3264 * Raises the Management Data Clock
 3265 *
 3266 * hw - Struct containing variables accessed by shared code
 3267 * ctrl - Device control register's current value
 3268 ******************************************************************************/
 3269 static void
em_raise_mdi_clk(struct em_hw *hw,
uint32_t *ctrl)
 3272 {
 3273     /* Raise the clock input to the Management Data Clock (by setting the MDC
 3274      * bit), and then delay 10 microseconds.
 3275      */
E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
E1000_WRITE_FLUSH(hw);
usec_delay(10);
 3279 }
 3281 /******************************************************************************
 3282 * Lowers the Management Data Clock
 3283 *
 3284 * hw - Struct containing variables accessed by shared code
 3285 * ctrl - Device control register's current value
 3286 ******************************************************************************/
 3287 static void
em_lower_mdi_clk(struct em_hw *hw,
uint32_t *ctrl)
 3290 {
 3291     /* Lower the clock input to the Management Data Clock (by clearing the MDC
 3292      * bit), and then delay 10 microseconds.
 3293      */
E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
E1000_WRITE_FLUSH(hw);
usec_delay(10);
 3297 }
 3299 /******************************************************************************
 3300 * Shifts data bits out to the PHY
 3301 *
 3302 * hw - Struct containing variables accessed by shared code
 3303 * data - Data to send out to the PHY
 3304 * count - Number of bits to shift out
 3305 *
 3306 * Bits are shifted out in MSB to LSB order.
 3307 ******************************************************************************/
 3308 static void
em_shift_out_mdi_bits(struct em_hw *hw,
uint32_t data,
uint16_t count)
 3312 {
uint32_t ctrl;
uint32_t mask;
 3316     /* We need to shift "count" number of bits out to the PHY. So, the value
 3317      * in the "data" parameter will be shifted out to the PHY one bit at a
 3318      * time. In order to do this, "data" must be broken down into bits.
 3319      */
mask = 0x01;
mask <<= (count - 1);
ctrl = E1000_READ_REG(hw, CTRL);
 3325     /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
 3328     while (mask) {
 3329         /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
 3330          * then raising and lowering the Management Data Clock. A "0" is
 3331          * shifted out to the PHY by setting the MDIO bit to "0" and then
 3332          * raising and lowering the clock.
 3333          */
 3334         if (data & mask)
ctrl |= E1000_CTRL_MDIO;
 3336         else
ctrl &= ~E1000_CTRL_MDIO;
E1000_WRITE_REG(hw, CTRL, ctrl);
E1000_WRITE_FLUSH(hw);
usec_delay(10);
em_raise_mdi_clk(hw, &ctrl);
em_lower_mdi_clk(hw, &ctrl);
mask = mask >> 1;
 3348     }
 3349 }
 3351 /******************************************************************************
 3352 * Shifts data bits in from the PHY
 3353 *
 3354 * hw - Struct containing variables accessed by shared code
 3355 *
 3356 * Bits are shifted in in MSB to LSB order.
 3357 ******************************************************************************/
 3358 static uint16_t
em_shift_in_mdi_bits(struct em_hw *hw)
 3360 {
uint32_t ctrl;
uint16_t data = 0;
uint8_t i;
 3365     /* In order to read a register from the PHY, we need to shift in a total
 3366      * of 18 bits from the PHY. The first two bit (turnaround) times are used
 3367      * to avoid contention on the MDIO pin when a read operation is performed.
 3368      * These two bits are ignored by us and thrown away. Bits are "shifted in"
 3369      * by raising the input to the Management Data Clock (setting the MDC bit),
 3370      * and then reading the value of the MDIO bit.
 3371      */
ctrl = E1000_READ_REG(hw, CTRL);
 3374     /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
ctrl &= ~E1000_CTRL_MDIO_DIR;
ctrl &= ~E1000_CTRL_MDIO;
E1000_WRITE_REG(hw, CTRL, ctrl);
E1000_WRITE_FLUSH(hw);
 3381     /* Raise and Lower the clock before reading in the data. This accounts for
 3382      * the turnaround bits. The first clock occurred when we clocked out the
 3383      * last bit of the Register Address.
 3384      */
em_raise_mdi_clk(hw, &ctrl);
em_lower_mdi_clk(hw, &ctrl);
 3388     for (data = 0, i = 0; i < 16; i++) {
data = data << 1;
em_raise_mdi_clk(hw, &ctrl);
ctrl = E1000_READ_REG(hw, CTRL);
 3392         /* Check to see if we shifted in a "1". */
 3393         if (ctrl & E1000_CTRL_MDIO)
data |= 1;
em_lower_mdi_clk(hw, &ctrl);
 3396     }
em_raise_mdi_clk(hw, &ctrl);
em_lower_mdi_clk(hw, &ctrl);
 3401     return data;
 3402 }
STATIC int32_t
em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask)
 3406 {
uint32_t swfw_sync = 0;
uint32_t swmask = mask;
uint32_t fwmask = mask << 16;
int32_t timeout = 200;
DEBUGFUNC("em_swfw_sync_acquire");
 3414     if (hw->swfwhw_semaphore_present)
 3415         return em_get_software_flag(hw);
 3417     if (!hw->swfw_sync_present)
 3418         return em_get_hw_eeprom_semaphore(hw);
 3420     while (timeout) {
 3421             if (em_get_hw_eeprom_semaphore(hw))
 3422                 return -E1000_ERR_SWFW_SYNC;
swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
 3425             if (!(swfw_sync & (fwmask | swmask))) {
 3426                 break;
 3427             }
 3429             /* firmware currently using resource (fwmask) */
 3430             /* or other software thread currently using resource (swmask) */
em_put_hw_eeprom_semaphore(hw);
msec_delay_irq(5);
timeout--;
 3434     }
 3436     if (!timeout) {
DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
 3438         return -E1000_ERR_SWFW_SYNC;
 3439     }
swfw_sync |= swmask;
E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
em_put_hw_eeprom_semaphore(hw);
 3445     return E1000_SUCCESS;
 3446 }
STATIC void
em_swfw_sync_release(struct em_hw *hw, uint16_t mask)
 3450 {
uint32_t swfw_sync;
uint32_t swmask = mask;
DEBUGFUNC("em_swfw_sync_release");
 3456     if (hw->swfwhw_semaphore_present) {
em_release_software_flag(hw);
 3458         return;
 3459     }
 3461     if (!hw->swfw_sync_present) {
em_put_hw_eeprom_semaphore(hw);
 3463         return;
 3464     }
 3466     /* if (em_get_hw_eeprom_semaphore(hw))
 3467      *    return -E1000_ERR_SWFW_SYNC; */
 3468     while (em_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
 3469         /* empty */
swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
swfw_sync &= ~swmask;
E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
em_put_hw_eeprom_semaphore(hw);
 3476 }
 3478 /*****************************************************************************
 3479 * Reads the value from a PHY register, if the value is on a specific non zero
 3480 * page, sets the page first.
 3481 * hw - Struct containing variables accessed by shared code
 3482 * reg_addr - address of the PHY register to read
 3483 ******************************************************************************/
int32_t
em_read_phy_reg(struct em_hw *hw,
uint32_t reg_addr,
uint16_t *phy_data)
 3488 {
uint32_t ret_val;
uint16_t swfw;
DEBUGFUNC("em_read_phy_reg");
 3494     if ((hw->mac_type == em_80003es2lan) &&
 3495         (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
swfw = E1000_SWFW_PHY1_SM;
 3497     } else {
swfw = E1000_SWFW_PHY0_SM;
 3499     }
 3500     if (em_swfw_sync_acquire(hw, swfw))
 3501         return -E1000_ERR_SWFW_SYNC;
 3503     if ((hw->phy_type == em_phy_igp ||
hw->phy_type == em_phy_igp_3 ||
hw->phy_type == em_phy_igp_2) &&
 3506        (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
 3508                                          (uint16_t)reg_addr);
 3509         if (ret_val) {
em_swfw_sync_release(hw, swfw);
 3511             return ret_val;
 3512         }
 3513     } else if (hw->phy_type == em_phy_gg82563) {
 3514         if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
 3515             (hw->mac_type == em_80003es2lan)) {
 3516             /* Select Configuration Page */
 3517             if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
ret_val = em_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
 3519                           (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
 3520             } else {
 3521                 /* Use Alternative Page Select register to access
 3522                  * registers 30 and 31
 3523                  */
ret_val = em_write_phy_reg_ex(hw,
GG82563_PHY_PAGE_SELECT_ALT,
 3526                           (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
 3527             }
 3529             if (ret_val) {
em_swfw_sync_release(hw, swfw);
 3531                 return ret_val;
 3532             }
 3533         }
 3534     }
ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
phy_data);
em_swfw_sync_release(hw, swfw);
 3540     return ret_val;
 3541 }
STATIC int32_t
em_read_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr,
uint16_t *phy_data)
 3546 {
uint32_t i;
uint32_t mdic = 0;
 3549     const uint32_t phy_addr = 1;
DEBUGFUNC("em_read_phy_reg_ex");
 3553     if (reg_addr > MAX_PHY_REG_ADDRESS) {
DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
 3555         return -E1000_ERR_PARAM;
 3556     }
 3558     if (hw->mac_type > em_82543) {
 3559         /* Set up Op-code, Phy Address, and register address in the MDI
 3560          * Control register.  The MAC will take care of interfacing with the
 3561          * PHY to retrieve the desired data.
 3562          */
mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
 3564                 (phy_addr << E1000_MDIC_PHY_SHIFT) |
 3565                 (E1000_MDIC_OP_READ));
E1000_WRITE_REG(hw, MDIC, mdic);
 3569         /* Poll the ready bit to see if the MDI read completed */
 3570         for (i = 0; i < 64; i++) {
usec_delay(50);
mdic = E1000_READ_REG(hw, MDIC);
 3573             if (mdic & E1000_MDIC_READY) break;
 3574         }
 3575         if (!(mdic & E1000_MDIC_READY)) {
DEBUGOUT("MDI Read did not complete\n");
 3577             return -E1000_ERR_PHY;
 3578         }
 3579         if (mdic & E1000_MDIC_ERROR) {
DEBUGOUT("MDI Error\n");
 3581             return -E1000_ERR_PHY;
 3582         }
 3583         *phy_data = (uint16_t) mdic;
 3584     } else {
 3585         /* We must first send a preamble through the MDIO pin to signal the
 3586          * beginning of an MII instruction.  This is done by sending 32
 3587          * consecutive "1" bits.
 3588          */
em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
 3591         /* Now combine the next few fields that are required for a read
 3592          * operation.  We use this method instead of calling the
 3593          * em_shift_out_mdi_bits routine five different times. The format of
 3594          * a MII read instruction consists of a shift out of 14 bits and is
 3595          * defined as follows:
 3596          *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
 3597          * followed by a shift in of 18 bits.  This first two bits shifted in
 3598          * are TurnAround bits used to avoid contention on the MDIO pin when a
 3599          * READ operation is performed.  These two bits are thrown away
 3600          * followed by a shift in of 16 bits which contains the desired data.
 3601          */
mdic = ((reg_addr) | (phy_addr << 5) |
 3603                 (PHY_OP_READ << 10) | (PHY_SOF << 12));
em_shift_out_mdi_bits(hw, mdic, 14);
 3607         /* Now that we've shifted out the read command to the MII, we need to
 3608          * "shift in" the 16-bit value (18 total bits) of the requested PHY
 3609          * register address.
 3610          */
 3611         *phy_data = em_shift_in_mdi_bits(hw);
 3612     }
 3613     return E1000_SUCCESS;
 3614 }
 3616 /******************************************************************************
 3617 * Writes a value to a PHY register
 3618 *
 3619 * hw - Struct containing variables accessed by shared code
 3620 * reg_addr - address of the PHY register to write
 3621 * data - data to write to the PHY
 3622 ******************************************************************************/
int32_t
em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr,
uint16_t phy_data)
 3626 {
uint32_t ret_val;
uint16_t swfw;
DEBUGFUNC("em_write_phy_reg");
 3632     if ((hw->mac_type == em_80003es2lan) &&
 3633         (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
swfw = E1000_SWFW_PHY1_SM;
 3635     } else {
swfw = E1000_SWFW_PHY0_SM;
 3637     }
 3638     if (em_swfw_sync_acquire(hw, swfw))
 3639         return -E1000_ERR_SWFW_SYNC;
 3641     if ((hw->phy_type == em_phy_igp ||
hw->phy_type == em_phy_igp_3 ||
hw->phy_type == em_phy_igp_2) &&
 3644        (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
 3646                                          (uint16_t)reg_addr);
 3647         if (ret_val) {
em_swfw_sync_release(hw, swfw);
 3649             return ret_val;
 3650         }
 3651     } else if (hw->phy_type == em_phy_gg82563) {
 3652         if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
 3653             (hw->mac_type == em_80003es2lan)) {
 3654             /* Select Configuration Page */
 3655             if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
ret_val = em_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
 3657                           (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
 3658             } else {
 3659                 /* Use Alternative Page Select register to access
 3660                  * registers 30 and 31
 3661                  */
ret_val = em_write_phy_reg_ex(hw,
GG82563_PHY_PAGE_SELECT_ALT,
 3664                           (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
 3665             }
 3667             if (ret_val) {
em_swfw_sync_release(hw, swfw);
 3669                 return ret_val;
 3670             }
 3671         }
 3672     }
ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
phy_data);
em_swfw_sync_release(hw, swfw);
 3678     return ret_val;
 3679 }
STATIC int32_t
em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr,
uint16_t phy_data)
 3684 {
uint32_t i;
uint32_t mdic = 0;
 3687     const uint32_t phy_addr = 1;
DEBUGFUNC("em_write_phy_reg_ex");
 3691     if (reg_addr > MAX_PHY_REG_ADDRESS) {
DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
 3693         return -E1000_ERR_PARAM;
 3694     }
 3696     if (hw->mac_type > em_82543) {
 3697         /* Set up Op-code, Phy Address, register address, and data intended
 3698          * for the PHY register in the MDI Control register.  The MAC will take
 3699          * care of interfacing with the PHY to send the desired data.
 3700          */
mdic = (((uint32_t) phy_data) |
 3702                 (reg_addr << E1000_MDIC_REG_SHIFT) |
 3703                 (phy_addr << E1000_MDIC_PHY_SHIFT) |
 3704                 (E1000_MDIC_OP_WRITE));
E1000_WRITE_REG(hw, MDIC, mdic);
 3708         /* Poll the ready bit to see if the MDI read completed */
 3709         for (i = 0; i < 641; i++) {
usec_delay(5);
mdic = E1000_READ_REG(hw, MDIC);
 3712             if (mdic & E1000_MDIC_READY) break;
 3713         }
 3714         if (!(mdic & E1000_MDIC_READY)) {
DEBUGOUT("MDI Write did not complete\n");
 3716             return -E1000_ERR_PHY;
 3717         }
 3718     } else {
 3719         /* We'll need to use the SW defined pins to shift the write command
 3720          * out to the PHY. We first send a preamble to the PHY to signal the
 3721          * beginning of the MII instruction.  This is done by sending 32
 3722          * consecutive "1" bits.
 3723          */
em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
 3726         /* Now combine the remaining required fields that will indicate a
 3727          * write operation. We use this method instead of calling the
 3728          * em_shift_out_mdi_bits routine for each field in the command. The
 3729          * format of a MII write instruction is as follows:
 3730          * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
 3731          */
mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
 3733                 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
mdic <<= 16;
mdic |= (uint32_t) phy_data;
em_shift_out_mdi_bits(hw, mdic, 32);
 3738     }
 3740     return E1000_SUCCESS;
 3741 }
STATIC int32_t
em_read_kmrn_reg(struct em_hw *hw,
uint32_t reg_addr,
uint16_t *data)
 3747 {
uint32_t reg_val;
uint16_t swfw;
DEBUGFUNC("em_read_kmrn_reg");
 3752     if ((hw->mac_type == em_80003es2lan) &&
 3753         (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
swfw = E1000_SWFW_PHY1_SM;
 3755     } else {
swfw = E1000_SWFW_PHY0_SM;
 3757     }
 3758     if (em_swfw_sync_acquire(hw, swfw))
 3759         return -E1000_ERR_SWFW_SYNC;
 3761     /* Write register address */
reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
E1000_KUMCTRLSTA_OFFSET) |
E1000_KUMCTRLSTA_REN;
E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
usec_delay(2);
 3768     /* Read the data returned */
reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
 3770     *data = (uint16_t)reg_val;
em_swfw_sync_release(hw, swfw);
 3773     return E1000_SUCCESS;
 3774 }
STATIC int32_t
em_write_kmrn_reg(struct em_hw *hw,
uint32_t reg_addr,
uint16_t data)
 3780 {
uint32_t reg_val;
uint16_t swfw;
DEBUGFUNC("em_write_kmrn_reg");
 3785     if ((hw->mac_type == em_80003es2lan) &&
 3786         (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
swfw = E1000_SWFW_PHY1_SM;
 3788     } else {
swfw = E1000_SWFW_PHY0_SM;
 3790     }
 3791     if (em_swfw_sync_acquire(hw, swfw))
 3792         return -E1000_ERR_SWFW_SYNC;
reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
E1000_KUMCTRLSTA_OFFSET) | data;
E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
usec_delay(2);
em_swfw_sync_release(hw, swfw);
 3800     return E1000_SUCCESS;
 3801 }
 3803 /******************************************************************************
 3804 * Returns the PHY to the power-on reset state
 3805 *
 3806 * hw - Struct containing variables accessed by shared code
 3807 ******************************************************************************/
int32_t
em_phy_hw_reset(struct em_hw *hw)
 3810 {
uint32_t ctrl, ctrl_ext;
uint32_t led_ctrl;
int32_t ret_val;
uint16_t swfw;
DEBUGFUNC("em_phy_hw_reset");
 3818     /* In the case of the phy reset being blocked, it's not an error, we
 3819      * simply return success without performing the reset. */
ret_val = em_check_phy_reset_block(hw);
 3821     if (ret_val)
 3822         return E1000_SUCCESS;
DEBUGOUT("Resetting Phy...\n");
 3826     if (hw->mac_type > em_82543) {
 3827         if ((hw->mac_type == em_80003es2lan) &&
 3828             (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
swfw = E1000_SWFW_PHY1_SM;
 3830         } else {
swfw = E1000_SWFW_PHY0_SM;
 3832         }
 3833         if (em_swfw_sync_acquire(hw, swfw)) {
DEBUGOUT("Unable to acquire swfw sync\n");
 3835             return -E1000_ERR_SWFW_SYNC;
 3836         }
 3837         /* Read the device control register and assert the E1000_CTRL_PHY_RST
 3838          * bit. Then, take it out of reset.
 3839          * For pre-em_82571 hardware, we delay for 10ms between the assert
 3840          * and deassert.  For em_82571 hardware and later, we instead delay
 3841          * for 50us between and 10ms after the deassertion.
 3842          */
ctrl = E1000_READ_REG(hw, CTRL);
E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
E1000_WRITE_FLUSH(hw);
 3847         if (hw->mac_type < em_82571)
msec_delay(10);
 3849         else
usec_delay(100);
E1000_WRITE_REG(hw, CTRL, ctrl);
E1000_WRITE_FLUSH(hw);
 3855         if (hw->mac_type >= em_82571)
msec_delay_irq(10);
em_swfw_sync_release(hw, swfw);
 3858     } else {
 3859         /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
 3860          * bit to put the PHY into reset. Then, take it out of reset.
 3861          */
ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
E1000_WRITE_FLUSH(hw);
msec_delay(10);
ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
E1000_WRITE_FLUSH(hw);
 3871     }
usec_delay(150);
 3874     if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
 3875         /* Configure activity LED after PHY reset */
led_ctrl = E1000_READ_REG(hw, LEDCTL);
led_ctrl &= IGP_ACTIVITY_LED_MASK;
led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
 3880     }
 3882     /* Wait for FW to finish PHY configuration. */
ret_val = em_get_phy_cfg_done(hw);
 3884     if (ret_val != E1000_SUCCESS)
 3885         return ret_val;
em_release_software_semaphore(hw);
 3888     if ((hw->mac_type == em_ich8lan) && (hw->phy_type == em_phy_igp_3))
ret_val = em_init_lcd_from_nvm(hw);
 3891     return ret_val;
 3892 }
 3894 /******************************************************************************
 3895 * Resets the PHY
 3896 *
 3897 * hw - Struct containing variables accessed by shared code
 3898 *
 3899 * Sets bit 15 of the MII Control regiser
 3900 ******************************************************************************/
int32_t
em_phy_reset(struct em_hw *hw)
 3903 {
int32_t ret_val;
uint16_t phy_data;
DEBUGFUNC("em_phy_reset");
 3909     /* In the case of the phy reset being blocked, it's not an error, we
 3910      * simply return success without performing the reset. */
ret_val = em_check_phy_reset_block(hw);
 3912     if (ret_val)
 3913         return E1000_SUCCESS;
 3915     switch (hw->phy_type) {
 3916     case em_phy_igp:
 3917     case em_phy_igp_2:
 3918     case em_phy_igp_3:
 3919     case em_phy_ife:
ret_val = em_phy_hw_reset(hw);
 3921         if (ret_val)
 3922             return ret_val;
 3923         break;
 3924     default:
ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data);
 3926         if (ret_val)
 3927             return ret_val;
phy_data |= MII_CR_RESET;
ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data);
 3931         if (ret_val)
 3932             return ret_val;
usec_delay(1);
 3935         break;
 3936     }
 3938     if (hw->phy_type == em_phy_igp || hw->phy_type == em_phy_igp_2)
em_phy_init_script(hw);
 3941     return E1000_SUCCESS;
 3942 }
 3944 /******************************************************************************
 3945 * Work-around for 82566 Kumeran PCS lock loss:
 3946 * On link status change (i.e. PCI reset, speed change) and link is up and
 3947 * speed is gigabit-
 3948 * 0) if workaround is optionally disabled do nothing
 3949 * 1) wait 1ms for Kumeran link to come up
 3950 * 2) check Kumeran Diagnostic register PCS lock loss bit
 3951 * 3) if not set the link is locked (all is good), otherwise...
 3952 * 4) reset the PHY
 3953 * 5) repeat up to 10 times
 3954 * Note: this is only called for IGP3 copper when speed is 1gb.
 3955 *
 3956 * hw - struct containing variables accessed by shared code
 3957 ******************************************************************************/
STATIC int32_t
em_kumeran_lock_loss_workaround(struct em_hw *hw)
 3960 {
int32_t ret_val;
int32_t reg;
int32_t cnt;
uint16_t phy_data;
 3966     if (hw->kmrn_lock_loss_workaround_disabled)
 3967         return E1000_SUCCESS;
 3969     /* Make sure link is up before proceeding.  If not just return.
 3970      * Attempting this while link is negotiating fouled up link
 3971      * stability */
ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
 3975     if (phy_data & MII_SR_LINK_STATUS) {
 3976         for (cnt = 0; cnt < 10; cnt++) {
 3977             /* read once to clear */
ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
 3979             if (ret_val)
 3980                 return ret_val;
 3981             /* and again to get new status */
ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
 3983             if (ret_val)
 3984                 return ret_val;
 3986             /* check for PCS lock */
 3987             if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
 3988                 return E1000_SUCCESS;
 3990             /* Issue PHY reset */
em_phy_hw_reset(hw);
msec_delay_irq(5);
 3993         }
 3994         /* Disable GigE link negotiation */
reg = E1000_READ_REG(hw, PHY_CTRL);
E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
 3999         /* unable to acquire PCS lock */
 4000         return E1000_ERR_PHY;
 4001     }
 4003     return E1000_SUCCESS;
 4004 }
 4006 /******************************************************************************
 4007 * Probes the expected PHY address for known PHY IDs
 4008 *
 4009 * hw - Struct containing variables accessed by shared code
 4010 ******************************************************************************/
STATIC int32_t
em_detect_gig_phy(struct em_hw *hw)
 4013 {
int32_t phy_init_status, ret_val;
uint16_t phy_id_high, phy_id_low;
boolean_t match = FALSE;
DEBUGFUNC("em_detect_gig_phy");
 4020     if (hw->phy_id != 0)
 4021         return E1000_SUCCESS;
 4023     /* The 82571 firmware may still be configuring the PHY.  In this
 4024      * case, we cannot access the PHY until the configuration is done.  So
 4025      * we explicitly set the PHY values. */
 4026     if (hw->mac_type == em_82571 ||
hw->mac_type == em_82572) {
hw->phy_id = IGP01E1000_I_PHY_ID;
hw->phy_type = em_phy_igp_2;
 4030         return E1000_SUCCESS;
 4031     }
 4033     /* ESB-2 PHY reads require em_phy_gg82563 to be set because of a work-
 4034      * around that forces PHY page 0 to be set or the reads fail.  The rest of
 4035      * the code in this routine uses em_read_phy_reg to read the PHY ID.
 4036      * So for ESB-2 we need to have this set so our reads won't fail.  If the
 4037      * attached PHY is not a em_phy_gg82563, the routines below will figure
 4038      * this out as well. */
 4039     if (hw->mac_type == em_80003es2lan)
hw->phy_type = em_phy_gg82563;
 4042     /* Read the PHY ID Registers to identify which PHY is onboard. */
ret_val = em_read_phy_reg(hw, PHY_ID1, &phy_id_high);
 4044     if (ret_val)
 4045         return ret_val;
hw->phy_id = (uint32_t) (phy_id_high << 16);
usec_delay(20);
ret_val = em_read_phy_reg(hw, PHY_ID2, &phy_id_low);
 4050     if (ret_val)
 4051         return ret_val;
hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
 4056     switch (hw->mac_type) {
 4057     case em_82543:
 4058         if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
 4059         break;
 4060     case em_82544:
 4061         if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
 4062         break;
 4063     case em_82540:
 4064     case em_82545:
 4065     case em_82545_rev_3:
 4066     case em_82546:
 4067     case em_82546_rev_3:
 4068         if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
 4069         break;
 4070     case em_82541:
 4071     case em_82541_rev_2:
 4072     case em_82547:
 4073     case em_82547_rev_2:
 4074         if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
 4075         break;
 4076     case em_82573:
 4077         if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
 4078         break;
 4079     case em_80003es2lan:
 4080         if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
 4081         break;
 4082     case em_ich8lan:
 4083         if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE;
 4084         if (hw->phy_id == IFE_E_PHY_ID) match = TRUE;
 4085         if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE;
 4086         if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE;
 4087         break;
 4088     default:
DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
 4090         return -E1000_ERR_CONFIG;
 4091     }
phy_init_status = em_set_phy_type(hw);
 4094     if ((match) && (phy_init_status == E1000_SUCCESS)) {
DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
 4096         return E1000_SUCCESS;
 4097     }
DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
 4099     return -E1000_ERR_PHY;
 4100 }
 4102 /******************************************************************************
 4103 * Resets the PHY's DSP
 4104 *
 4105 * hw - Struct containing variables accessed by shared code
 4106 ******************************************************************************/
 4107 static int32_t
em_phy_reset_dsp(struct em_hw *hw)
 4109 {
int32_t ret_val;
DEBUGFUNC("em_phy_reset_dsp");
 4113     do {
 4114         if (hw->phy_type != em_phy_gg82563) {
ret_val = em_write_phy_reg(hw, 29, 0x001d);
 4116             if (ret_val) break;
 4117         }
ret_val = em_write_phy_reg(hw, 30, 0x00c1);
 4119         if (ret_val) break;
ret_val = em_write_phy_reg(hw, 30, 0x0000);
 4121         if (ret_val) break;
ret_val = E1000_SUCCESS;
 4123     } while (0);
 4125     return ret_val;
 4126 }
 4128 /******************************************************************************
 4129  * Sets up eeprom variables in the hw struct.  Must be called after mac_type
 4130  * is configured.  Additionally, if this is ICH8, the flash controller GbE
 4131  * registers must be mapped, or this will crash.
 4132  *
 4133  * hw - Struct containing variables accessed by shared code
 4134  *****************************************************************************/
int32_t
em_init_eeprom_params(struct em_hw *hw)
 4137 {
 4138     struct em_eeprom_info *eeprom = &hw->eeprom;
uint32_t eecd = E1000_READ_REG(hw, EECD);
int32_t ret_val = E1000_SUCCESS;
uint16_t eeprom_size;
DEBUGFUNC("em_init_eeprom_params");
 4145     switch (hw->mac_type) {
 4146     case em_82542_rev2_0:
 4147     case em_82542_rev2_1:
 4148     case em_82543:
 4149     case em_82544:
eeprom->type = em_eeprom_microwire;
eeprom->word_size = 64;
eeprom->opcode_bits = 3;
eeprom->address_bits = 6;
eeprom->delay_usec = 50;
eeprom->use_eerd = FALSE;
eeprom->use_eewr = FALSE;
 4157         break;
 4158     case em_82540:
 4159     case em_82545:
 4160     case em_82545_rev_3:
 4161     case em_82546:
 4162     case em_82546_rev_3:
eeprom->type = em_eeprom_microwire;
eeprom->opcode_bits = 3;
eeprom->delay_usec = 50;
 4166         if (eecd & E1000_EECD_SIZE) {
eeprom->word_size = 256;
eeprom->address_bits = 8;
 4169         } else {
eeprom->word_size = 64;
eeprom->address_bits = 6;
 4172         }
eeprom->use_eerd = FALSE;
eeprom->use_eewr = FALSE;
 4175         break;
 4176     case em_82541:
 4177     case em_82541_rev_2:
 4178     case em_82547:
 4179     case em_82547_rev_2:
 4180         if (eecd & E1000_EECD_TYPE) {
eeprom->type = em_eeprom_spi;
eeprom->opcode_bits = 8;
eeprom->delay_usec = 1;
 4184             if (eecd & E1000_EECD_ADDR_BITS) {
eeprom->page_size = 32;
eeprom->address_bits = 16;
 4187             } else {
eeprom->page_size = 8;
eeprom->address_bits = 8;
 4190             }
 4191         } else {
eeprom->type = em_eeprom_microwire;
eeprom->opcode_bits = 3;
eeprom->delay_usec = 50;
 4195             if (eecd & E1000_EECD_ADDR_BITS) {
eeprom->word_size = 256;
eeprom->address_bits = 8;
 4198             } else {
eeprom->word_size = 64;
eeprom->address_bits = 6;
 4201             }
 4202         }
eeprom->use_eerd = FALSE;
eeprom->use_eewr = FALSE;
 4205         break;
 4206     case em_82571:
 4207     case em_82572:
eeprom->type = em_eeprom_spi;
eeprom->opcode_bits = 8;
eeprom->delay_usec = 1;
 4211         if (eecd & E1000_EECD_ADDR_BITS) {
eeprom->page_size = 32;
eeprom->address_bits = 16;
 4214         } else {
eeprom->page_size = 8;
eeprom->address_bits = 8;
 4217         }
eeprom->use_eerd = FALSE;
eeprom->use_eewr = FALSE;
 4220         break;
 4221     case em_82573:
eeprom->type = em_eeprom_spi;
eeprom->opcode_bits = 8;
eeprom->delay_usec = 1;
 4225         if (eecd & E1000_EECD_ADDR_BITS) {
eeprom->page_size = 32;
eeprom->address_bits = 16;
 4228         } else {
eeprom->page_size = 8;
eeprom->address_bits = 8;
 4231         }
eeprom->use_eerd = TRUE;
eeprom->use_eewr = TRUE;
 4234         if (em_is_onboard_nvm_eeprom(hw) == FALSE) {
eeprom->type = em_eeprom_flash;
eeprom->word_size = 2048;
 4238             /* Ensure that the Autonomous FLASH update bit is cleared due to
 4239              * Flash update issue on parts which use a FLASH for NVM. */
eecd &= ~E1000_EECD_AUPDEN;
E1000_WRITE_REG(hw, EECD, eecd);
 4242         }
 4243         break;
 4244     case em_80003es2lan:
eeprom->type = em_eeprom_spi;
eeprom->opcode_bits = 8;
eeprom->delay_usec = 1;
 4248         if (eecd & E1000_EECD_ADDR_BITS) {
eeprom->page_size = 32;
eeprom->address_bits = 16;
 4251         } else {
eeprom->page_size = 8;
eeprom->address_bits = 8;
 4254         }
eeprom->use_eerd = TRUE;
eeprom->use_eewr = FALSE;
 4257         break;
 4258     case em_ich8lan:
 4259     {
int32_t  i = 0;
uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG);
eeprom->type = em_eeprom_ich8;
eeprom->use_eerd = FALSE;
eeprom->use_eewr = FALSE;
eeprom->word_size = E1000_SHADOW_RAM_WORDS;
 4268         /* Zero the shadow RAM structure. But don't load it from NVM
 4269          * so as to save time for driver init */
 4270         if (hw->eeprom_shadow_ram != NULL) {
 4271             for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
hw->eeprom_shadow_ram[i].modified = FALSE;
hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
 4274             }
 4275         }
hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
ICH_FLASH_SECTOR_SIZE;
hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1;
hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
hw->flash_bank_size /= 2 * sizeof(uint16_t);
 4287         break;
 4288     }
 4289     default:
 4290         break;
 4291     }
 4293     if (eeprom->type == em_eeprom_spi) {
 4294         /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
 4295          * 32KB (incremented by powers of 2).
 4296          */
 4297         if (hw->mac_type <= em_82547_rev_2) {
 4298             /* Set to default value for initial eeprom read. */
eeprom->word_size = 64;
ret_val = em_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
 4301             if (ret_val)
 4302                 return ret_val;
eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
 4304             /* 256B eeprom size was not supported in earlier hardware, so we
 4305              * bump eeprom_size up one to ensure that "1" (which maps to 256B)
 4306              * is never the result used in the shifting logic below. */
 4307             if (eeprom_size)
eeprom_size++;
 4309         } else {
eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
E1000_EECD_SIZE_EX_SHIFT);
 4312         }
eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
 4315     }
 4316     return ret_val;
 4317 }
 4319 /******************************************************************************
 4320  * Raises the EEPROM's clock input.
 4321  *
 4322  * hw - Struct containing variables accessed by shared code
 4323  * eecd - EECD's current value
 4324  *****************************************************************************/
 4325 static void
em_raise_ee_clk(struct em_hw *hw,
uint32_t *eecd)
 4328 {
 4329     /* Raise the clock input to the EEPROM (by setting the SK bit), and then
 4330      * wait <delay> microseconds.
 4331      */
 4332     *eecd = *eecd | E1000_EECD_SK;
E1000_WRITE_REG(hw, EECD, *eecd);
E1000_WRITE_FLUSH(hw);
usec_delay(hw->eeprom.delay_usec);
 4336 }
 4338 /******************************************************************************
 4339  * Lowers the EEPROM's clock input.
 4340  *
 4341  * hw - Struct containing variables accessed by shared code
 4342  * eecd - EECD's current value
 4343  *****************************************************************************/
 4344 static void
em_lower_ee_clk(struct em_hw *hw,
uint32_t *eecd)
 4347 {
 4348     /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
 4349      * wait 50 microseconds.
 4350      */
 4351     *eecd = *eecd & ~E1000_EECD_SK;
E1000_WRITE_REG(hw, EECD, *eecd);
E1000_WRITE_FLUSH(hw);
usec_delay(hw->eeprom.delay_usec);
 4355 }
 4357 /******************************************************************************
 4358  * Shift data bits out to the EEPROM.
 4359  *
 4360  * hw - Struct containing variables accessed by shared code
 4361  * data - data to send to the EEPROM
 4362  * count - number of bits to shift out
 4363  *****************************************************************************/
 4364 static void
em_shift_out_ee_bits(struct em_hw *hw,
uint16_t data,
uint16_t count)
 4368 {
 4369     struct em_eeprom_info *eeprom = &hw->eeprom;
uint32_t eecd;
uint32_t mask;
 4373     /* We need to shift "count" bits out to the EEPROM. So, value in the
 4374      * "data" parameter will be shifted out to the EEPROM one bit at a time.
 4375      * In order to do this, "data" must be broken down into bits.
 4376      */
mask = 0x01 << (count - 1);
eecd = E1000_READ_REG(hw, EECD);
 4379     if (eeprom->type == em_eeprom_microwire) {
eecd &= ~E1000_EECD_DO;
 4381     } else if (eeprom->type == em_eeprom_spi) {
eecd |= E1000_EECD_DO;
 4383     }
 4384     do {
 4385         /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
 4386          * and then raising and then lowering the clock (the SK bit controls
 4387          * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
 4388          * by setting "DI" to "0" and then raising and then lowering the clock.
 4389          */
eecd &= ~E1000_EECD_DI;
 4392         if (data & mask)
eecd |= E1000_EECD_DI;
E1000_WRITE_REG(hw, EECD, eecd);
E1000_WRITE_FLUSH(hw);
usec_delay(eeprom->delay_usec);
em_raise_ee_clk(hw, &eecd);
em_lower_ee_clk(hw, &eecd);
mask = mask >> 1;
 4405     } while (mask);
 4407     /* We leave the "DI" bit set to "0" when we leave this routine. */
eecd &= ~E1000_EECD_DI;
E1000_WRITE_REG(hw, EECD, eecd);
 4410 }
 4412 /******************************************************************************
 4413  * Shift data bits in from the EEPROM
 4414  *
 4415  * hw - Struct containing variables accessed by shared code
 4416  *****************************************************************************/
 4417 static uint16_t
em_shift_in_ee_bits(struct em_hw *hw,
uint16_t count)
 4420 {
uint32_t eecd;
uint32_t i;
uint16_t data;
 4425     /* In order to read a register from the EEPROM, we need to shift 'count'
 4426      * bits in from the EEPROM. Bits are "shifted in" by raising the clock
 4427      * input to the EEPROM (setting the SK bit), and then reading the value of
 4428      * the "DO" bit.  During this "shifting in" process the "DI" bit should
 4429      * always be clear.
 4430      */
eecd = E1000_READ_REG(hw, EECD);
eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
data = 0;
 4437     for (i = 0; i < count; i++) {
data = data << 1;
em_raise_ee_clk(hw, &eecd);
eecd = E1000_READ_REG(hw, EECD);
eecd &= ~(E1000_EECD_DI);
 4444         if (eecd & E1000_EECD_DO)
data |= 1;
em_lower_ee_clk(hw, &eecd);
 4448     }
 4450     return data;
 4451 }
 4453 /******************************************************************************
 4454  * Prepares EEPROM for access
 4455  *
 4456  * hw - Struct containing variables accessed by shared code
 4457  *
 4458  * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
 4459  * function should be called before issuing a command to the EEPROM.
 4460  *****************************************************************************/
 4461 static int32_t
em_acquire_eeprom(struct em_hw *hw)
 4463 {
 4464     struct em_eeprom_info *eeprom = &hw->eeprom;
uint32_t eecd, i=0;
DEBUGFUNC("em_acquire_eeprom");
 4469     if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
 4470         return -E1000_ERR_SWFW_SYNC;
eecd = E1000_READ_REG(hw, EECD);
 4473     if (hw->mac_type != em_82573) {
 4474         /* Request EEPROM Access */
 4475         if (hw->mac_type > em_82544) {
eecd |= E1000_EECD_REQ;
E1000_WRITE_REG(hw, EECD, eecd);
eecd = E1000_READ_REG(hw, EECD);
 4479             while ((!(eecd & E1000_EECD_GNT)) &&
 4480                   (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
i++;
usec_delay(5);
eecd = E1000_READ_REG(hw, EECD);
 4484             }
 4485             if (!(eecd & E1000_EECD_GNT)) {
eecd &= ~E1000_EECD_REQ;
E1000_WRITE_REG(hw, EECD, eecd);
DEBUGOUT("Could not acquire EEPROM grant\n");
em_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
 4490                 return -E1000_ERR_EEPROM;
 4491             }
 4492         }
 4493     }
 4495     /* Setup EEPROM for Read/Write */
 4497     if (eeprom->type == em_eeprom_microwire) {
 4498         /* Clear SK and DI */
eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
E1000_WRITE_REG(hw, EECD, eecd);
 4502         /* Set CS */
eecd |= E1000_EECD_CS;
E1000_WRITE_REG(hw, EECD, eecd);
 4505     } else if (eeprom->type == em_eeprom_spi) {
 4506         /* Clear SK and CS */
eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
E1000_WRITE_REG(hw, EECD, eecd);
usec_delay(1);
 4510     }
 4512     return E1000_SUCCESS;
 4513 }
 4515 /******************************************************************************
 4516  * Returns EEPROM to a "standby" state
 4517  *
 4518  * hw - Struct containing variables accessed by shared code
 4519  *****************************************************************************/
 4520 static void
em_standby_eeprom(struct em_hw *hw)
 4522 {
 4523     struct em_eeprom_info *eeprom = &hw->eeprom;
uint32_t eecd;
eecd = E1000_READ_REG(hw, EECD);
 4528     if (eeprom->type == em_eeprom_microwire) {
eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
E1000_WRITE_REG(hw, EECD, eecd);
E1000_WRITE_FLUSH(hw);
usec_delay(eeprom->delay_usec);
 4534         /* Clock high */
eecd |= E1000_EECD_SK;
E1000_WRITE_REG(hw, EECD, eecd);
E1000_WRITE_FLUSH(hw);
usec_delay(eeprom->delay_usec);
 4540         /* Select EEPROM */
eecd |= E1000_EECD_CS;
E1000_WRITE_REG(hw, EECD, eecd);
E1000_WRITE_FLUSH(hw);
usec_delay(eeprom->delay_usec);
 4546         /* Clock low */
eecd &= ~E1000_EECD_SK;
E1000_WRITE_REG(hw, EECD, eecd);
E1000_WRITE_FLUSH(hw);
usec_delay(eeprom->delay_usec);
 4551     } else if (eeprom->type == em_eeprom_spi) {
 4552         /* Toggle CS to flush commands */
eecd |= E1000_EECD_CS;
E1000_WRITE_REG(hw, EECD, eecd);
E1000_WRITE_FLUSH(hw);
usec_delay(eeprom->delay_usec);
eecd &= ~E1000_EECD_CS;
E1000_WRITE_REG(hw, EECD, eecd);
E1000_WRITE_FLUSH(hw);
usec_delay(eeprom->delay_usec);
 4561     }
 4562 }
 4564 /******************************************************************************
 4565  * Terminates a command by inverting the EEPROM's chip select pin
 4566  *
 4567  * hw - Struct containing variables accessed by shared code
 4568  *****************************************************************************/
 4569 static void
em_release_eeprom(struct em_hw *hw)
 4571 {
uint32_t eecd;
DEBUGFUNC("em_release_eeprom");
eecd = E1000_READ_REG(hw, EECD);
 4578     if (hw->eeprom.type == em_eeprom_spi) {
eecd |= E1000_EECD_CS;  /* Pull CS high */
eecd &= ~E1000_EECD_SK; /* Lower SCK */
E1000_WRITE_REG(hw, EECD, eecd);
usec_delay(hw->eeprom.delay_usec);
 4585     } else if (hw->eeprom.type == em_eeprom_microwire) {
 4586         /* cleanup eeprom */
 4588         /* CS on Microwire is active-high */
eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
E1000_WRITE_REG(hw, EECD, eecd);
 4593         /* Rising edge of clock */
eecd |= E1000_EECD_SK;
E1000_WRITE_REG(hw, EECD, eecd);
E1000_WRITE_FLUSH(hw);
usec_delay(hw->eeprom.delay_usec);
 4599         /* Falling edge of clock */
eecd &= ~E1000_EECD_SK;
E1000_WRITE_REG(hw, EECD, eecd);
E1000_WRITE_FLUSH(hw);
usec_delay(hw->eeprom.delay_usec);
 4604     }
 4606     /* Stop requesting EEPROM access */
 4607     if (hw->mac_type > em_82544) {
eecd &= ~E1000_EECD_REQ;
E1000_WRITE_REG(hw, EECD, eecd);
 4610     }
em_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
 4613 }
 4615 /******************************************************************************
 4616  * Reads a 16 bit word from the EEPROM.
 4617  *
 4618  * hw - Struct containing variables accessed by shared code
 4619  *****************************************************************************/
STATIC int32_t
em_spi_eeprom_ready(struct em_hw *hw)
 4622 {
uint16_t retry_count = 0;
uint8_t spi_stat_reg;
DEBUGFUNC("em_spi_eeprom_ready");
 4628     /* Read "Status Register" repeatedly until the LSB is cleared.  The
 4629      * EEPROM will signal that the command has been completed by clearing
 4630      * bit 0 of the internal status register.  If it's not cleared within
 4631      * 5 milliseconds, then error out.
 4632      */
retry_count = 0;
 4634     do {
em_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
hw->eeprom.opcode_bits);
spi_stat_reg = (uint8_t)em_shift_in_ee_bits(hw, 8);
 4638         if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
 4639             break;
usec_delay(5);
retry_count += 5;
em_standby_eeprom(hw);
 4645     } while (retry_count < EEPROM_MAX_RETRY_SPI);
 4647     /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
 4648      * only 0-5mSec on 5V devices)
 4649      */
 4650     if (retry_count >= EEPROM_MAX_RETRY_SPI) {
DEBUGOUT("SPI EEPROM Status error\n");
 4652         return -E1000_ERR_EEPROM;
 4653     }
 4655     return E1000_SUCCESS;
 4656 }
 4658 /******************************************************************************
 4659  * Reads a 16 bit word from the EEPROM.
 4660  *
 4661  * hw - Struct containing variables accessed by shared code
 4662  * offset - offset of  word in the EEPROM to read
 4663  * data - word read from the EEPROM
 4664  * words - number of words to read
 4665  *****************************************************************************/
int32_t
em_read_eeprom(struct em_hw *hw,
uint16_t offset,
uint16_t words,
uint16_t *data)
 4671 {
 4672     struct em_eeprom_info *eeprom = &hw->eeprom;
uint32_t i = 0;
DEBUGFUNC("em_read_eeprom");
 4677     /* If eeprom is not yet detected, do so now */
 4678     if (eeprom->word_size == 0)
em_init_eeprom_params(hw);
 4681     /* A check for invalid values:  offset too large, too many words, and not
 4682      * enough words.
 4683      */
 4684     if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
 4685        (words == 0)) {
DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size);
 4687         return -E1000_ERR_EEPROM;
 4688     }
 4690     /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
 4691      * directly. In this case, we need to acquire the EEPROM so that
 4692      * FW or other port software does not interrupt.
 4693      */
 4694     if (em_is_onboard_nvm_eeprom(hw) == TRUE &&
hw->eeprom.use_eerd == FALSE) {
 4696         /* Prepare the EEPROM for bit-bang reading */
 4697         if (em_acquire_eeprom(hw) != E1000_SUCCESS)
 4698             return -E1000_ERR_EEPROM;
 4699     }
 4701     /* Eerd register EEPROM access requires no eeprom aquire/release */
 4702     if (eeprom->use_eerd == TRUE)
 4703         return em_read_eeprom_eerd(hw, offset, words, data);
 4705     /* ICH EEPROM access is done via the ICH flash controller */
 4706     if (eeprom->type == em_eeprom_ich8)
 4707         return em_read_eeprom_ich8(hw, offset, words, data);
 4709     /* Set up the SPI or Microwire EEPROM for bit-bang reading.  We have
 4710      * acquired the EEPROM at this point, so any returns should relase it */
 4711     if (eeprom->type == em_eeprom_spi) {
uint16_t word_in;
uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
 4715         if (em_spi_eeprom_ready(hw)) {
em_release_eeprom(hw);
 4717             return -E1000_ERR_EEPROM;
 4718         }
em_standby_eeprom(hw);
 4722         /* Some SPI eeproms use the 8th address bit embedded in the opcode */
 4723         if ((eeprom->address_bits == 8) && (offset >= 128))
read_opcode |= EEPROM_A8_OPCODE_SPI;
 4726         /* Send the READ command (opcode + addr)  */
em_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
em_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
 4730         /* Read the data.  The address of the eeprom internally increments with
 4731          * each byte (spi) being read, saving on the overhead of eeprom setup
 4732          * and tear-down.  The address counter will roll over if reading beyond
 4733          * the size of the eeprom, thus allowing the entire memory to be read
 4734          * starting from any offset. */
 4735         for (i = 0; i < words; i++) {
word_in = em_shift_in_ee_bits(hw, 16);
data[i] = (word_in >> 8) | (word_in << 8);
 4738         }
 4739     } else if (eeprom->type == em_eeprom_microwire) {
 4740         for (i = 0; i < words; i++) {
 4741             /* Send the READ command (opcode + addr)  */
em_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
eeprom->opcode_bits);
em_shift_out_ee_bits(hw, (uint16_t)(offset + i),
eeprom->address_bits);
 4747             /* Read the data.  For microwire, each word requires the overhead
 4748              * of eeprom setup and tear-down. */
data[i] = em_shift_in_ee_bits(hw, 16);
em_standby_eeprom(hw);
 4751         }
 4752     }
 4754     /* End this read operation */
em_release_eeprom(hw);
 4757     return E1000_SUCCESS;
 4758 }
 4760 /******************************************************************************
 4761  * Reads a 16 bit word from the EEPROM using the EERD register.
 4762  *
 4763  * hw - Struct containing variables accessed by shared code
 4764  * offset - offset of  word in the EEPROM to read
 4765  * data - word read from the EEPROM
 4766  * words - number of words to read
 4767  *****************************************************************************/
STATIC int32_t
em_read_eeprom_eerd(struct em_hw *hw,
uint16_t offset,
uint16_t words,
uint16_t *data)
 4773 {
uint32_t i, eerd = 0;
int32_t error = 0;
 4777     for (i = 0; i < words; i++) {
eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
E1000_EEPROM_RW_REG_START;
E1000_WRITE_REG(hw, EERD, eerd);
error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
 4784         if (error) {
 4785             break;
 4786         }
data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
 4789     }
 4791     return error;
 4792 }
 4794 /******************************************************************************
 4795  * Writes a 16 bit word from the EEPROM using the EEWR register.
 4796  *
 4797  * hw - Struct containing variables accessed by shared code
 4798  * offset - offset of  word in the EEPROM to read
 4799  * data - word read from the EEPROM
 4800  * words - number of words to read
 4801  *****************************************************************************/
STATIC int32_t
em_write_eeprom_eewr(struct em_hw *hw,
uint16_t offset,
uint16_t words,
uint16_t *data)
 4807 {
uint32_t    register_value = 0;
uint32_t    i              = 0;
int32_t     error          = 0;
 4812     if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
 4813         return -E1000_ERR_SWFW_SYNC;
 4815     for (i = 0; i < words; i++) {
register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
 4817                          ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) |
E1000_EEPROM_RW_REG_START;
error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
 4821         if (error) {
 4822             break;
 4823         }
E1000_WRITE_REG(hw, EEWR, register_value);
error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
 4829         if (error) {
 4830             break;
 4831         }
 4832     }
em_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
 4835     return error;
 4836 }
 4838 /******************************************************************************
 4839  * Polls the status bit (bit 1) of the EERD to determine when the read is done.
 4840  *
 4841  * hw - Struct containing variables accessed by shared code
 4842  *****************************************************************************/
STATIC int32_t
em_poll_eerd_eewr_done(struct em_hw *hw, int eerd)
 4845 {
uint32_t attempts = 100000;
uint32_t i, reg = 0;
int32_t done = E1000_ERR_EEPROM;
 4850     for (i = 0; i < attempts; i++) {
 4851         if (eerd == E1000_EEPROM_POLL_READ)
reg = E1000_READ_REG(hw, EERD);
 4853         else
reg = E1000_READ_REG(hw, EEWR);
 4856         if (reg & E1000_EEPROM_RW_REG_DONE) {
done = E1000_SUCCESS;
 4858             break;
 4859         }
usec_delay(5);
 4861     }
 4863     return done;
 4864 }
 4866 /***************************************************************************
 4867 * Description:     Determines if the onboard NVM is FLASH or EEPROM.
 4868 *
 4869 * hw - Struct containing variables accessed by shared code
 4870 ****************************************************************************/
STATIC boolean_t
em_is_onboard_nvm_eeprom(struct em_hw *hw)
 4873 {
uint32_t eecd = 0;
DEBUGFUNC("em_is_onboard_nvm_eeprom");
 4878     if (hw->mac_type == em_ich8lan)
 4879         return FALSE;
 4881     if (hw->mac_type == em_82573) {
eecd = E1000_READ_REG(hw, EECD);
 4884         /* Isolate bits 15 & 16 */
eecd = ((eecd >> 15) & 0x03);
 4887         /* If both bits are set, device is Flash type */
 4888         if (eecd == 0x03) {
 4889             return FALSE;
 4890         }
 4891     }
 4892     return TRUE;
 4893 }
 4895 /******************************************************************************
 4896  * Verifies that the EEPROM has a valid checksum
 4897  *
 4898  * hw - Struct containing variables accessed by shared code
 4899  *
 4900  * Reads the first 64 16 bit words of the EEPROM and sums the values read.
 4901  * If the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
 4902  * valid.
 4903  *****************************************************************************/
int32_t
em_validate_eeprom_checksum(struct em_hw *hw)
 4906 {
uint16_t checksum = 0;
uint16_t i, eeprom_data;
DEBUGFUNC("em_validate_eeprom_checksum");
 4912     if ((hw->mac_type == em_82573) &&
 4913         (em_is_onboard_nvm_eeprom(hw) == FALSE)) {
 4914         /* Check bit 4 of word 10h.  If it is 0, firmware is done updating
 4915          * 10h-12h.  Checksum may need to be fixed. */
em_read_eeprom(hw, 0x10, 1, &eeprom_data);
 4917         if ((eeprom_data & 0x10) == 0) {
 4918             /* Read 0x23 and check bit 15.  This bit is a 1 when the checksum
 4919              * has already been fixed.  If the checksum is still wrong and this
 4920              * bit is a 1, we need to return bad checksum.  Otherwise, we need
 4921              * to set this bit to a 1 and update the checksum. */
em_read_eeprom(hw, 0x23, 1, &eeprom_data);
 4923             if ((eeprom_data & 0x8000) == 0) {
eeprom_data |= 0x8000;
em_write_eeprom(hw, 0x23, 1, &eeprom_data);
em_update_eeprom_checksum(hw);
 4927             }
 4928         }
 4929     }
 4931     if (hw->mac_type == em_ich8lan) {
 4932         /* Drivers must allocate the shadow ram structure for the
 4933          * EEPROM checksum to be updated.  Otherwise, this bit as well
 4934          * as the checksum must both be set correctly for this
 4935          * validation to pass.
 4936          */
em_read_eeprom(hw, 0x19, 1, &eeprom_data);
 4938         if ((eeprom_data & 0x40) == 0) {
eeprom_data |= 0x40;
em_write_eeprom(hw, 0x19, 1, &eeprom_data);
em_update_eeprom_checksum(hw);
 4942         }
 4943     }
 4945     for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
 4946         if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
DEBUGOUT("EEPROM Read Error\n");
 4948             return -E1000_ERR_EEPROM;
 4949         }
checksum += eeprom_data;
 4951     }
 4953     if (checksum == (uint16_t) EEPROM_SUM)
 4954         return E1000_SUCCESS;
 4955     else {
DEBUGOUT("EEPROM Checksum Invalid\n");
 4957         return -E1000_ERR_EEPROM;
 4958     }
 4959 }
 4961 /******************************************************************************
 4962  * Calculates the EEPROM checksum and writes it to the EEPROM
 4963  *
 4964  * hw - Struct containing variables accessed by shared code
 4965  *
 4966  * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
 4967  * Writes the difference to word offset 63 of the EEPROM.
 4968  *****************************************************************************/
int32_t
em_update_eeprom_checksum(struct em_hw *hw)
 4971 {
uint32_t ctrl_ext;
uint16_t checksum = 0;
uint16_t i, eeprom_data;
DEBUGFUNC("em_update_eeprom_checksum");
 4978     for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
 4979         if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
DEBUGOUT("EEPROM Read Error\n");
 4981             return -E1000_ERR_EEPROM;
 4982         }
checksum += eeprom_data;
 4984     }
checksum = (uint16_t) EEPROM_SUM - checksum;
 4986     if (em_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
DEBUGOUT("EEPROM Write Error\n");
 4988         return -E1000_ERR_EEPROM;
 4989     } else if (hw->eeprom.type == em_eeprom_flash) {
em_commit_shadow_ram(hw);
 4991     } else if (hw->eeprom.type == em_eeprom_ich8) {
em_commit_shadow_ram(hw);
 4993         /* Reload the EEPROM, or else modifications will not appear
 4994          * until after next adapter reset. */
ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
ctrl_ext |= E1000_CTRL_EXT_EE_RST;
E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
msec_delay(10);
 4999     }
 5000     return E1000_SUCCESS;
 5001 }
 5003 /******************************************************************************
 5004  * Parent function for writing words to the different EEPROM types.
 5005  *
 5006  * hw - Struct containing variables accessed by shared code
 5007  * offset - offset within the EEPROM to be written to
 5008  * words - number of words to write
 5009  * data - 16 bit word to be written to the EEPROM
 5010  *
 5011  * If em_update_eeprom_checksum is not called after this function, the
 5012  * EEPROM will most likely contain an invalid checksum.
 5013  *****************************************************************************/
int32_t
em_write_eeprom(struct em_hw *hw,
uint16_t offset,
uint16_t words,
uint16_t *data)
 5019 {
 5020     struct em_eeprom_info *eeprom = &hw->eeprom;
int32_t status = 0;
DEBUGFUNC("em_write_eeprom");
 5025     /* If eeprom is not yet detected, do so now */
 5026     if (eeprom->word_size == 0)
em_init_eeprom_params(hw);
 5029     /* A check for invalid values:  offset too large, too many words, and not
 5030      * enough words.
 5031      */
 5032     if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
 5033        (words == 0)) {
DEBUGOUT("\"words\" parameter out of bounds\n");
 5035         return -E1000_ERR_EEPROM;
 5036     }
 5038     /* 82573 writes only through eewr */
 5039     if (eeprom->use_eewr == TRUE)
 5040         return em_write_eeprom_eewr(hw, offset, words, data);
 5042     if (eeprom->type == em_eeprom_ich8)
 5043         return em_write_eeprom_ich8(hw, offset, words, data);
 5045     /* Prepare the EEPROM for writing  */
 5046     if (em_acquire_eeprom(hw) != E1000_SUCCESS)
 5047         return -E1000_ERR_EEPROM;
 5049     if (eeprom->type == em_eeprom_microwire) {
status = em_write_eeprom_microwire(hw, offset, words, data);
 5051     } else {
status = em_write_eeprom_spi(hw, offset, words, data);
msec_delay(10);
 5054     }
 5056     /* Done with writing */
em_release_eeprom(hw);
 5059     return status;
 5060 }
 5062 /******************************************************************************
 5063  * Writes a 16 bit word to a given offset in an SPI EEPROM.
 5064  *
 5065  * hw - Struct containing variables accessed by shared code
 5066  * offset - offset within the EEPROM to be written to
 5067  * words - number of words to write
 5068  * data - pointer to array of 8 bit words to be written to the EEPROM
 5069  *
 5070  *****************************************************************************/
STATIC int32_t
em_write_eeprom_spi(struct em_hw *hw,
uint16_t offset,
uint16_t words,
uint16_t *data)
 5076 {
 5077     struct em_eeprom_info *eeprom = &hw->eeprom;
uint16_t widx = 0;
DEBUGFUNC("em_write_eeprom_spi");
 5082     while (widx < words) {
uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
 5085         if (em_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
em_standby_eeprom(hw);
 5089         /*  Send the WRITE ENABLE command (8 bit opcode )  */
em_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
eeprom->opcode_bits);
em_standby_eeprom(hw);
 5095         /* Some SPI eeproms use the 8th address bit embedded in the opcode */
 5096         if ((eeprom->address_bits == 8) && (offset >= 128))
write_opcode |= EEPROM_A8_OPCODE_SPI;
 5099         /* Send the Write command (8-bit opcode + addr) */
em_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
em_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
eeprom->address_bits);
 5105         /* Send the data */
 5107         /* Loop to allow for up to whole page write (32 bytes) of eeprom */
 5108         while (widx < words) {
uint16_t word_out = data[widx];
word_out = (word_out >> 8) | (word_out << 8);
em_shift_out_ee_bits(hw, word_out, 16);
widx++;
 5114             /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
 5115              * operation, while the smaller eeproms are capable of an 8-byte
 5116              * PAGE WRITE operation.  Break the inner loop to pass new address
 5117              */
 5118             if ((((offset + widx)*2) % eeprom->page_size) == 0) {
em_standby_eeprom(hw);
 5120                 break;
 5121             }
 5122         }
 5123     }
 5125     return E1000_SUCCESS;
 5126 }
 5128 /******************************************************************************
 5129  * Writes a 16 bit word to a given offset in a Microwire EEPROM.
 5130  *
 5131  * hw - Struct containing variables accessed by shared code
 5132  * offset - offset within the EEPROM to be written to
 5133  * words - number of words to write
 5134  * data - pointer to array of 16 bit words to be written to the EEPROM
 5135  *
 5136  *****************************************************************************/
STATIC int32_t
em_write_eeprom_microwire(struct em_hw *hw,
uint16_t offset,
uint16_t words,
uint16_t *data)
 5142 {
 5143     struct em_eeprom_info *eeprom = &hw->eeprom;
uint32_t eecd;
uint16_t words_written = 0;
uint16_t i = 0;
DEBUGFUNC("em_write_eeprom_microwire");
 5150     /* Send the write enable command to the EEPROM (3-bit opcode plus
 5151      * 6/8-bit dummy address beginning with 11).  It's less work to include
 5152      * the 11 of the dummy address as part of the opcode than it is to shift
 5153      * it over the correct number of bits for the address.  This puts the
 5154      * EEPROM into write/erase mode.
 5155      */
em_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
 5157                             (uint16_t)(eeprom->opcode_bits + 2));
em_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
 5161     /* Prepare the EEPROM */
em_standby_eeprom(hw);
 5164     while (words_written < words) {
 5165         /* Send the Write command (3-bit opcode + addr) */
em_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
eeprom->opcode_bits);
em_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
eeprom->address_bits);
 5172         /* Send the data */
em_shift_out_ee_bits(hw, data[words_written], 16);
 5175         /* Toggle the CS line.  This in effect tells the EEPROM to execute
 5176          * the previous command.
 5177          */
em_standby_eeprom(hw);
 5180         /* Read DO repeatedly until it is high (equal to '1').  The EEPROM will
 5181          * signal that the command has been completed by raising the DO signal.
 5182          * If DO does not go high in 10 milliseconds, then error out.
 5183          */
 5184         for (i = 0; i < 200; i++) {
eecd = E1000_READ_REG(hw, EECD);
 5186             if (eecd & E1000_EECD_DO) break;
usec_delay(50);
 5188         }
 5189         if (i == 200) {
DEBUGOUT("EEPROM Write did not complete\n");
 5191             return -E1000_ERR_EEPROM;
 5192         }
 5194         /* Recover from write */
em_standby_eeprom(hw);
words_written++;
 5198     }
 5200     /* Send the write disable command to the EEPROM (3-bit opcode plus
 5201      * 6/8-bit dummy address beginning with 10).  It's less work to include
 5202      * the 10 of the dummy address as part of the opcode than it is to shift
 5203      * it over the correct number of bits for the address.  This takes the
 5204      * EEPROM out of write/erase mode.
 5205      */
em_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
 5207                             (uint16_t)(eeprom->opcode_bits + 2));
em_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
 5211     return E1000_SUCCESS;
 5212 }
 5214 /******************************************************************************
 5215  * Flushes the cached eeprom to NVM. This is done by saving the modified values
 5216  * in the eeprom cache and the non modified values in the currently active bank
 5217  * to the new bank.
 5218  *
 5219  * hw - Struct containing variables accessed by shared code
 5220  * offset - offset of  word in the EEPROM to read
 5221  * data - word read from the EEPROM
 5222  * words - number of words to read
 5223  *****************************************************************************/
STATIC int32_t
em_commit_shadow_ram(struct em_hw *hw)
 5226 {
uint32_t attempts = 100000;
uint32_t eecd = 0;
uint32_t flop = 0;
uint32_t i = 0;
int32_t error = E1000_SUCCESS;
uint32_t old_bank_offset = 0;
uint32_t new_bank_offset = 0;
uint8_t low_byte = 0;
uint8_t high_byte = 0;
boolean_t sector_write_failed = FALSE;
 5238     if (hw->mac_type == em_82573) {
 5239         /* The flop register will be used to determine if flash type is STM */
flop = E1000_READ_REG(hw, FLOP);
 5241         for (i=0; i < attempts; i++) {
eecd = E1000_READ_REG(hw, EECD);
 5243             if ((eecd & E1000_EECD_FLUPD) == 0) {
 5244                 break;
 5245             }
usec_delay(5);
 5247         }
 5249         if (i == attempts) {
 5250             return -E1000_ERR_EEPROM;
 5251         }
 5253         /* If STM opcode located in bits 15:8 of flop, reset firmware */
 5254         if ((flop & 0xFF00) == E1000_STM_OPCODE) {
E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
 5256         }
 5258         /* Perform the flash update */
E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD);
 5261         for (i=0; i < attempts; i++) {
eecd = E1000_READ_REG(hw, EECD);
 5263             if ((eecd & E1000_EECD_FLUPD) == 0) {
 5264                 break;
 5265             }
usec_delay(5);
 5267         }
 5269         if (i == attempts) {
 5270             return -E1000_ERR_EEPROM;
 5271         }
 5272     }
 5274     if (hw->mac_type == em_ich8lan && hw->eeprom_shadow_ram != NULL) {
 5275         /* We're writing to the opposite bank so if we're on bank 1,
 5276          * write to bank 0 etc.  We also need to erase the segment that
 5277          * is going to be written */
 5278         if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) {
new_bank_offset = hw->flash_bank_size * 2;
old_bank_offset = 0;
em_erase_ich8_4k_segment(hw, 1);
 5282         } else {
old_bank_offset = hw->flash_bank_size * 2;
new_bank_offset = 0;
em_erase_ich8_4k_segment(hw, 0);
 5286         }
sector_write_failed = FALSE;
 5289         /* Loop for every byte in the shadow RAM,
 5290          * which is in units of words. */
 5291         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
 5292             /* Determine whether to write the value stored
 5293              * in the other NVM bank or a modified value stored
 5294              * in the shadow RAM */
 5295             if (hw->eeprom_shadow_ram[i].modified == TRUE) {
low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word;
usec_delay(100);
error = em_verify_write_ich8_byte(hw,
 5299                             (i << 1) + new_bank_offset, low_byte);
 5301                 if (error != E1000_SUCCESS)
sector_write_failed = TRUE;
 5303                 else {
high_byte =
 5305                         (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
usec_delay(100);
 5307                 }
 5308             } else {
em_read_ich8_byte(hw, (i << 1) + old_bank_offset,
 5310                                      &low_byte);
usec_delay(100);
error = em_verify_write_ich8_byte(hw,
 5313                             (i << 1) + new_bank_offset, low_byte);
 5315                 if (error != E1000_SUCCESS)
sector_write_failed = TRUE;
 5317                 else {
em_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
 5319                                          &high_byte);
usec_delay(100);
 5321                 }
 5322             }
 5324             /* If the write of the low byte was successful, go ahread and
 5325              * write the high byte while checking to make sure that if it
 5326              * is the signature byte, then it is handled properly */
 5327             if (sector_write_failed == FALSE) {
 5328                 /* If the word is 0x13, then make sure the signature bits
 5329                  * (15:14) are 11b until the commit has completed.
 5330                  * This will allow us to write 10b which indicates the
 5331                  * signature is valid.  We want to do this after the write
 5332                  * has completed so that we don't mark the segment valid
 5333                  * while the write is still in progress */
 5334                 if (i == E1000_ICH_NVM_SIG_WORD)
high_byte = E1000_ICH_NVM_SIG_MASK | high_byte;
error = em_verify_write_ich8_byte(hw,
 5338                             (i << 1) + new_bank_offset + 1, high_byte);
 5339                 if (error != E1000_SUCCESS)
sector_write_failed = TRUE;
 5342             } else {
 5343                 /* If the write failed then break from the loop and
 5344                  * return an error */
 5345                 break;
 5346             }
 5347         }
 5349         /* Don't bother writing the segment valid bits if sector
 5350          * programming failed. */
 5351         if (sector_write_failed == FALSE) {
 5352             /* Finally validate the new segment by setting bit 15:14
 5353              * to 10b in word 0x13 , this can be done without an
 5354              * erase as well since these bits are 11 to start with
 5355              * and we need to change bit 14 to 0b */
em_read_ich8_byte(hw,
E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
 5358                                  &high_byte);
high_byte &= 0xBF;
error = em_verify_write_ich8_byte(hw,
E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte);
 5362             /* And invalidate the previously valid segment by setting
 5363              * its signature word (0x13) high_byte to 0b. This can be
 5364              * done without an erase because flash erase sets all bits
 5365              * to 1's. We can write 1's to 0's without an erase */
 5366             if (error == E1000_SUCCESS) {
error = em_verify_write_ich8_byte(hw,
E1000_ICH_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0);
 5369             }
 5371             /* Clear the now not used entry in the cache */
 5372             for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
hw->eeprom_shadow_ram[i].modified = FALSE;
hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
 5375             }
 5376         }
 5377     }
 5379     return error;
 5380 }
 5382 /******************************************************************************
 5383  * Reads the adapter's part number from the EEPROM
 5384  *
 5385  * hw - Struct containing variables accessed by shared code
 5386  * part_num - Adapter's part number
 5387  *****************************************************************************/
int32_t
em_read_part_num(struct em_hw *hw,
uint32_t *part_num)
 5391 {
uint16_t offset = EEPROM_PBA_BYTE_1;
uint16_t eeprom_data;
DEBUGFUNC("em_read_part_num");
 5397     /* Get word 0 from EEPROM */
 5398     if (em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
DEBUGOUT("EEPROM Read Error\n");
 5400         return -E1000_ERR_EEPROM;
 5401     }
 5402     /* Save word 0 in upper half of part_num */
 5403     *part_num = (uint32_t) (eeprom_data << 16);
 5405     /* Get word 1 from EEPROM */
 5406     if (em_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) {
DEBUGOUT("EEPROM Read Error\n");
 5408         return -E1000_ERR_EEPROM;
 5409     }
 5410     /* Save word 1 in lower half of part_num */
 5411     *part_num |= eeprom_data;
 5413     return E1000_SUCCESS;
 5414 }
 5416 /******************************************************************************
 5417  * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
 5418  * second function of dual function devices
 5419  *
 5420  * hw - Struct containing variables accessed by shared code
 5421  *****************************************************************************/
int32_t
em_read_mac_addr(struct em_hw * hw)
 5424 {
uint16_t offset;
uint16_t eeprom_data, i;
DEBUGFUNC("em_read_mac_addr");
 5430     for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
offset = i >> 1;
 5432         if (em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
DEBUGOUT("EEPROM Read Error\n");
 5434             return -E1000_ERR_EEPROM;
 5435         }
hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
 5438     }
 5440     switch (hw->mac_type) {
 5441     default:
 5442         break;
 5443     case em_82546:
 5444     case em_82546_rev_3:
 5445     case em_82571:
 5446     case em_80003es2lan:
 5447         if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
hw->perm_mac_addr[5] ^= 0x01;
 5449         break;
 5450     }
 5452     for (i = 0; i < NODE_ADDRESS_SIZE; i++)
hw->mac_addr[i] = hw->perm_mac_addr[i];
 5454     return E1000_SUCCESS;
 5455 }
 5457 /******************************************************************************
 5458  * Initializes receive address filters.
 5459  *
 5460  * hw - Struct containing variables accessed by shared code
 5461  *
 5462  * Places the MAC address in receive address register 0 and clears the rest
 5463  * of the receive addresss registers. Clears the multicast table. Assumes
 5464  * the receiver is in reset when the routine is called.
 5465  *****************************************************************************/
STATIC void
em_init_rx_addrs(struct em_hw *hw)
 5468 {
uint32_t i;
uint32_t rar_num;
DEBUGFUNC("em_init_rx_addrs");
 5474     /* Setup the receive address. */
DEBUGOUT("Programming MAC Address into RAR[0]\n");
em_rar_set(hw, hw->mac_addr, 0);
rar_num = E1000_RAR_ENTRIES;
 5481     /* Reserve a spot for the Locally Administered Address to work around
 5482      * an 82571 issue in which a reset on one port will reload the MAC on
 5483      * the other port. */
 5484     if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE))
rar_num -= 1;
 5486     if (hw->mac_type == em_ich8lan)
rar_num = E1000_RAR_ENTRIES_ICH8LAN;
 5489     /* Zero out the other 15 receive addresses. */
DEBUGOUT("Clearing RAR[1-15]\n");
 5491     for (i = 1; i < rar_num; i++) {
E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
E1000_WRITE_FLUSH(hw);
E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
E1000_WRITE_FLUSH(hw);
 5496     }
 5497 }
 5499 /******************************************************************************
 5500  * Updates the MAC's list of multicast addresses.
 5501  *
 5502  * hw - Struct containing variables accessed by shared code
 5503  * mc_addr_list - the list of new multicast addresses
 5504  * mc_addr_count - number of addresses
 5505  * pad - number of bytes between addresses in the list
 5506  * rar_used_count - offset where to start adding mc addresses into the RAR's
 5507  *
 5508  * The given list replaces any existing list. Clears the last 15 receive
 5509  * address registers and the multicast table. Uses receive address registers
 5510  * for the first 15 multicast addresses, and hashes the rest into the
 5511  * multicast table.
 5512  *****************************************************************************/
 5513 void
em_mc_addr_list_update(struct em_hw *hw,
uint8_t *mc_addr_list,
uint32_t mc_addr_count,
uint32_t pad,
uint32_t rar_used_count)
 5519 {
uint32_t hash_value;
uint32_t i;
uint32_t num_rar_entry;
uint32_t num_mta_entry;
DEBUGFUNC("em_mc_addr_list_update");
 5527     /* Set the new number of MC addresses that we are being requested to use. */
hw->num_mc_addrs = mc_addr_count;
 5530     /* Clear RAR[1-15] */
DEBUGOUT(" Clearing RAR[1-15]\n");
num_rar_entry = E1000_RAR_ENTRIES;
 5533     if (hw->mac_type == em_ich8lan)
num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN;
 5536     /* Reserve a spot for the Locally Administered Address to work around
 5537      * an 82571 issue in which a reset on one port will reload the MAC on
 5538      * the other port. */
 5539     if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE))
num_rar_entry -= 1;
 5542     for (i = rar_used_count; i < num_rar_entry; i++) {
E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
E1000_WRITE_FLUSH(hw);
E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
E1000_WRITE_FLUSH(hw);
 5547     }
 5549     /* Clear the MTA */
DEBUGOUT(" Clearing MTA\n");
num_mta_entry = E1000_NUM_MTA_REGISTERS;
 5552     if (hw->mac_type == em_ich8lan)
num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN;
 5555     for (i = 0; i < num_mta_entry; i++) {
E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
E1000_WRITE_FLUSH(hw);
 5558     }
 5560     /* Add the new addresses */
 5561     for (i = 0; i < mc_addr_count; i++) {
DEBUGOUT(" Adding the multicast addresses:\n");
DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1],
mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2],
mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3],
mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4],
mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]);
hash_value = em_hash_mc_addr(hw,
mc_addr_list +
 5573                                         (i * (ETH_LENGTH_OF_ADDRESS + pad)));
DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
 5577         /* Place this multicast address in the RAR if there is room, *
 5578          * else put it in the MTA
 5579          */
 5580         if (rar_used_count < num_rar_entry) {
em_rar_set(hw,
mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)),
rar_used_count);
rar_used_count++;
 5585         } else {
em_mta_set(hw, hash_value);
 5587         }
 5588     }
DEBUGOUT("MC Update Complete\n");
 5590 }
 5592 /******************************************************************************
 5593  * Hashes an address to determine its location in the multicast table
 5594  *
 5595  * hw - Struct containing variables accessed by shared code
 5596  * mc_addr - the multicast address to hash
 5597  *****************************************************************************/
uint32_t
em_hash_mc_addr(struct em_hw *hw,
uint8_t *mc_addr)
 5601 {
uint32_t hash_value = 0;
 5604     /* The portion of the address that is used for the hash table is
 5605      * determined by the mc_filter_type setting.
 5606      */
 5607     switch (hw->mc_filter_type) {
 5608     /* [0] [1] [2] [3] [4] [5]
 5609      * 01  AA  00  12  34  56
 5610      * LSB                 MSB
 5611      */
 5612     case 0:
 5613         if (hw->mac_type == em_ich8lan) {
 5614             /* [47:38] i.e. 0x158 for above example address */
hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2));
 5616         } else {
 5617             /* [47:36] i.e. 0x563 for above example address */
hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
 5619         }
 5620         break;
 5621     case 1:
 5622         if (hw->mac_type == em_ich8lan) {
 5623             /* [46:37] i.e. 0x2B1 for above example address */
hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3));
 5625         } else {
 5626             /* [46:35] i.e. 0xAC6 for above example address */
hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
 5628         }
 5629         break;
 5630     case 2:
 5631         if (hw->mac_type == em_ich8lan) {
 5632             /*[45:36] i.e. 0x163 for above example address */
hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
 5634         } else {
 5635             /* [45:34] i.e. 0x5D8 for above example address */
hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
 5637         }
 5638         break;
 5639     case 3:
 5640         if (hw->mac_type == em_ich8lan) {
 5641             /* [43:34] i.e. 0x18D for above example address */
hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
 5643         } else {
 5644             /* [43:32] i.e. 0x634 for above example address */
hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
 5646         }
 5647         break;
 5648     }
hash_value &= 0xFFF;
 5651     if (hw->mac_type == em_ich8lan)
hash_value &= 0x3FF;
 5654     return hash_value;
 5655 }
 5657 /******************************************************************************
 5658  * Sets the bit in the multicast table corresponding to the hash value.
 5659  *
 5660  * hw - Struct containing variables accessed by shared code
 5661  * hash_value - Multicast address hash value
 5662  *****************************************************************************/
 5663 void
em_mta_set(struct em_hw *hw,
uint32_t hash_value)
 5666 {
uint32_t hash_bit, hash_reg;
uint32_t mta;
uint32_t temp;
 5671     /* The MTA is a register array of 128 32-bit registers.
 5672      * It is treated like an array of 4096 bits.  We want to set
 5673      * bit BitArray[hash_value]. So we figure out what register
 5674      * the bit is in, read it, OR in the new bit, then write
 5675      * back the new value.  The register is determined by the
 5676      * upper 7 bits of the hash value and the bit within that
 5677      * register are determined by the lower 5 bits of the value.
 5678      */
hash_reg = (hash_value >> 5) & 0x7F;
 5680     if (hw->mac_type == em_ich8lan)
hash_reg &= 0x1F;
hash_bit = hash_value & 0x1F;
mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
mta |= (1 << hash_bit);
 5689     /* If we are on an 82544 and we are trying to write an odd offset
 5690      * in the MTA, save off the previous entry before writing and
 5691      * restore the old value after writing.
 5692      */
 5693     if ((hw->mac_type == em_82544) && ((hash_reg & 0x1) == 1)) {
temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
E1000_WRITE_FLUSH(hw);
E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
E1000_WRITE_FLUSH(hw);
 5699     } else {
E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
E1000_WRITE_FLUSH(hw);
 5702     }
 5703 }
 5705 /******************************************************************************
 5706  * Puts an ethernet address into a receive address register.
 5707  *
 5708  * hw - Struct containing variables accessed by shared code
 5709  * addr - Address to put into receive address register
 5710  * index - Receive address register to write
 5711  *****************************************************************************/
 5712 void
em_rar_set(struct em_hw *hw,
uint8_t *addr,
uint32_t index)
 5716 {
uint32_t rar_low, rar_high;
 5719     /* HW expects these in little endian so we reverse the byte order
 5720      * from network order (big endian) to little endian
 5721      */
rar_low = ((uint32_t) addr[0] |
 5723                ((uint32_t) addr[1] << 8) |
 5724                ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8));
 5727     /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
 5728      * unit hang.
 5729      *
 5730      * Description:
 5731      * If there are any Rx frames queued up or otherwise present in the HW
 5732      * before RSS is enabled, and then we enable RSS, the HW Rx unit will
 5733      * hang.  To work around this issue, we have to disable receives and
 5734      * flush out all Rx frames before we enable RSS. To do so, we modify we
 5735      * redirect all Rx traffic to manageability and then reset the HW.
 5736      * This flushes away Rx frames, and (since the redirections to
 5737      * manageability persists across resets) keeps new ones from coming in
 5738      * while we work.  Then, we clear the Address Valid AV bit for all MAC
 5739      * addresses and undo the re-direction to manageability.
 5740      * Now, frames are coming in again, but the MAC won't accept them, so
 5741      * far so good.  We now proceed to initialize RSS (if necessary) and
 5742      * configure the Rx unit.  Last, we re-enable the AV bits and continue
 5743      * on our merry way.
 5744      */
 5745     switch (hw->mac_type) {
 5746     case em_82571:
 5747     case em_82572:
 5748     case em_80003es2lan:
 5749         if (hw->leave_av_bit_off == TRUE)
 5750             break;
 5751     default:
 5752         /* Indicate to hardware the Address is Valid. */
rar_high |= E1000_RAH_AV;
 5754         break;
 5755     }
E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
E1000_WRITE_FLUSH(hw);
E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
E1000_WRITE_FLUSH(hw);
 5761 }
 5763 /******************************************************************************
 5764  * Clears the VLAN filer table
 5765  *
 5766  * hw - Struct containing variables accessed by shared code
 5767  *****************************************************************************/
STATIC void
em_clear_vfta(struct em_hw *hw)
 5770 {
uint32_t offset;
uint32_t vfta_value = 0;
uint32_t vfta_offset = 0;
uint32_t vfta_bit_in_reg = 0;
 5776     if (hw->mac_type == em_ich8lan)
 5777         return;
 5779     if (hw->mac_type == em_82573) {
 5780         if (hw->mng_cookie.vlan_id != 0) {
 5781             /* The VFTA is a 4096b bit-field, each identifying a single VLAN
 5782              * ID.  The following operations determine which 32b entry
 5783              * (i.e. offset) into the array we want to set the VLAN ID
 5784              * (i.e. bit) of the manageability unit. */
vfta_offset = (hw->mng_cookie.vlan_id >>
E1000_VFTA_ENTRY_SHIFT) &
E1000_VFTA_ENTRY_MASK;
vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
 5790         }
 5791     }
 5792     for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
 5793         /* If the offset we want to clear is the same offset of the
 5794          * manageability VLAN ID, then clear all bits except that of the
 5795          * manageability unit */
vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
E1000_WRITE_FLUSH(hw);
 5799     }
 5800 }
STATIC int32_t
em_id_led_init(struct em_hw * hw)
 5804 {
uint32_t ledctl;
 5806     const uint32_t ledctl_mask = 0x000000FF;
 5807     const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
 5808     const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
uint16_t eeprom_data, i, temp;
 5810     const uint16_t led_mask = 0x0F;
DEBUGFUNC("em_id_led_init");
 5814     if (hw->mac_type < em_82540) {
 5815         /* Nothing to do */
 5816         return E1000_SUCCESS;
 5817     }
ledctl = E1000_READ_REG(hw, LEDCTL);
hw->ledctl_default = ledctl;
hw->ledctl_mode1 = hw->ledctl_default;
hw->ledctl_mode2 = hw->ledctl_default;
 5824     if (em_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
DEBUGOUT("EEPROM Read Error\n");
 5826         return -E1000_ERR_EEPROM;
 5827     }
 5829     if ((hw->mac_type == em_82573) &&
 5830         (eeprom_data == ID_LED_RESERVED_82573))
eeprom_data = ID_LED_DEFAULT_82573;
 5832     else if ((eeprom_data == ID_LED_RESERVED_0000) ||
 5833             (eeprom_data == ID_LED_RESERVED_FFFF)) {
 5834         if (hw->mac_type == em_ich8lan)
eeprom_data = ID_LED_DEFAULT_ICH8LAN;
 5836         else
eeprom_data = ID_LED_DEFAULT;
 5838     }
 5840     for (i = 0; i < 4; i++) {
temp = (eeprom_data >> (i << 2)) & led_mask;
 5842         switch (temp) {
 5843         case ID_LED_ON1_DEF2:
 5844         case ID_LED_ON1_ON2:
 5845         case ID_LED_ON1_OFF2:
hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
hw->ledctl_mode1 |= ledctl_on << (i << 3);
 5848             break;
 5849         case ID_LED_OFF1_DEF2:
 5850         case ID_LED_OFF1_ON2:
 5851         case ID_LED_OFF1_OFF2:
hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
hw->ledctl_mode1 |= ledctl_off << (i << 3);
 5854             break;
 5855         default:
 5856             /* Do nothing */
 5857             break;
 5858         }
 5859         switch (temp) {
 5860         case ID_LED_DEF1_ON2:
 5861         case ID_LED_ON1_ON2:
 5862         case ID_LED_OFF1_ON2:
hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
hw->ledctl_mode2 |= ledctl_on << (i << 3);
 5865             break;
 5866         case ID_LED_DEF1_OFF2:
 5867         case ID_LED_ON1_OFF2:
 5868         case ID_LED_OFF1_OFF2:
hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
hw->ledctl_mode2 |= ledctl_off << (i << 3);
 5871             break;
 5872         default:
 5873             /* Do nothing */
 5874             break;
 5875         }
 5876     }
 5877     return E1000_SUCCESS;
 5878 }
 5880 /******************************************************************************
 5881  * Clears all hardware statistics counters.
 5882  *
 5883  * hw - Struct containing variables accessed by shared code
 5884  *****************************************************************************/
 5885 void
em_clear_hw_cntrs(struct em_hw *hw)
 5887 {
 5888     volatile uint32_t temp;
temp = E1000_READ_REG(hw, CRCERRS);
temp = E1000_READ_REG(hw, SYMERRS);
temp = E1000_READ_REG(hw, MPC);
temp = E1000_READ_REG(hw, SCC);
temp = E1000_READ_REG(hw, ECOL);
temp = E1000_READ_REG(hw, MCC);
temp = E1000_READ_REG(hw, LATECOL);
temp = E1000_READ_REG(hw, COLC);
temp = E1000_READ_REG(hw, DC);
temp = E1000_READ_REG(hw, SEC);
temp = E1000_READ_REG(hw, RLEC);
temp = E1000_READ_REG(hw, XONRXC);
temp = E1000_READ_REG(hw, XONTXC);
temp = E1000_READ_REG(hw, XOFFRXC);
temp = E1000_READ_REG(hw, XOFFTXC);
temp = E1000_READ_REG(hw, FCRUC);
 5907     if (hw->mac_type != em_ich8lan) {
temp = E1000_READ_REG(hw, PRC64);
temp = E1000_READ_REG(hw, PRC127);
temp = E1000_READ_REG(hw, PRC255);
temp = E1000_READ_REG(hw, PRC511);
temp = E1000_READ_REG(hw, PRC1023);
temp = E1000_READ_REG(hw, PRC1522);
 5914     }
temp = E1000_READ_REG(hw, GPRC);
temp = E1000_READ_REG(hw, BPRC);
temp = E1000_READ_REG(hw, MPRC);
temp = E1000_READ_REG(hw, GPTC);
temp = E1000_READ_REG(hw, GORCL);
temp = E1000_READ_REG(hw, GORCH);
temp = E1000_READ_REG(hw, GOTCL);
temp = E1000_READ_REG(hw, GOTCH);
temp = E1000_READ_REG(hw, RNBC);
temp = E1000_READ_REG(hw, RUC);
temp = E1000_READ_REG(hw, RFC);
temp = E1000_READ_REG(hw, ROC);
temp = E1000_READ_REG(hw, RJC);
temp = E1000_READ_REG(hw, TORL);
temp = E1000_READ_REG(hw, TORH);
temp = E1000_READ_REG(hw, TOTL);
temp = E1000_READ_REG(hw, TOTH);
temp = E1000_READ_REG(hw, TPR);
temp = E1000_READ_REG(hw, TPT);
 5936     if (hw->mac_type != em_ich8lan) {
temp = E1000_READ_REG(hw, PTC64);
temp = E1000_READ_REG(hw, PTC127);
temp = E1000_READ_REG(hw, PTC255);
temp = E1000_READ_REG(hw, PTC511);
temp = E1000_READ_REG(hw, PTC1023);
temp = E1000_READ_REG(hw, PTC1522);
 5943     }
temp = E1000_READ_REG(hw, MPTC);
temp = E1000_READ_REG(hw, BPTC);
 5948     if (hw->mac_type < em_82543) return;
temp = E1000_READ_REG(hw, ALGNERRC);
temp = E1000_READ_REG(hw, RXERRC);
temp = E1000_READ_REG(hw, TNCRS);
temp = E1000_READ_REG(hw, CEXTERR);
temp = E1000_READ_REG(hw, TSCTC);
temp = E1000_READ_REG(hw, TSCTFC);
 5957     if (hw->mac_type <= em_82544) return;
temp = E1000_READ_REG(hw, MGTPRC);
temp = E1000_READ_REG(hw, MGTPDC);
temp = E1000_READ_REG(hw, MGTPTC);
 5963     if (hw->mac_type <= em_82547_rev_2) return;
temp = E1000_READ_REG(hw, IAC);
temp = E1000_READ_REG(hw, ICRXOC);
 5968     if (hw->mac_type == em_ich8lan) return;
temp = E1000_READ_REG(hw, ICRXPTC);
temp = E1000_READ_REG(hw, ICRXATC);
temp = E1000_READ_REG(hw, ICTXPTC);
temp = E1000_READ_REG(hw, ICTXATC);
temp = E1000_READ_REG(hw, ICTXQEC);
temp = E1000_READ_REG(hw, ICTXQMTC);
temp = E1000_READ_REG(hw, ICRXDMTC);
 5977 }
 5979 /******************************************************************************
 5980  * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
 5981  *
 5982  * hw - Struct containing variables accessed by shared code
 5983  * frame_len - The length of the frame in question
 5984  * mac_addr - The Ethernet destination address of the frame in question
 5985  *****************************************************************************/
 5986 void
em_tbi_adjust_stats(struct em_hw *hw,
 5988                        struct em_hw_stats *stats,
uint32_t frame_len,
uint8_t *mac_addr)
 5991 {
uint64_t carry_bit;
 5994     /* First adjust the frame length. */
frame_len--;
 5996     /* We need to adjust the statistics counters, since the hardware
 5997      * counters overcount this packet as a CRC error and undercount
 5998      * the packet as a good packet
 5999      */
 6000     /* This packet should not be counted as a CRC error.    */
stats->crcerrs--;
 6002     /* This packet does count as a Good Packet Received.    */
stats->gprc++;
 6005     /* Adjust the Good Octets received counters             */
carry_bit = 0x80000000 & stats->gorcl;
stats->gorcl += frame_len;
 6008     /* If the high bit of Gorcl (the low 32 bits of the Good Octets
 6009      * Received Count) was one before the addition,
 6010      * AND it is zero after, then we lost the carry out,
 6011      * need to add one to Gorch (Good Octets Received Count High).
 6012      * This could be simplified if all environments supported
 6013      * 64-bit integers.
 6014      */
 6015     if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
stats->gorch++;
 6017     /* Is this a broadcast or multicast?  Check broadcast first,
 6018      * since the test for a multicast frame will test positive on
 6019      * a broadcast frame.
 6020      */
 6021     if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
 6022         /* Broadcast packet */
stats->bprc++;
 6024     else if (*mac_addr & 0x01)
 6025         /* Multicast packet */
stats->mprc++;
 6028     if (frame_len == hw->max_frame_size) {
 6029         /* In this case, the hardware has overcounted the number of
 6030          * oversize frames.
 6031          */
 6032         if (stats->roc > 0)
stats->roc--;
 6034     }
 6036     /* Adjust the bin counters when the extra byte put the frame in the
 6037      * wrong bin. Remember that the frame_len was adjusted above.
 6038      */
 6039     if (frame_len == 64) {
stats->prc64++;
stats->prc127--;
 6042     } else if (frame_len == 127) {
stats->prc127++;
stats->prc255--;
 6045     } else if (frame_len == 255) {
stats->prc255++;
stats->prc511--;
 6048     } else if (frame_len == 511) {
stats->prc511++;
stats->prc1023--;
 6051     } else if (frame_len == 1023) {
stats->prc1023++;
stats->prc1522--;
 6054     } else if (frame_len == 1522) {
stats->prc1522++;
 6056     }
 6057 }
 6059 /******************************************************************************
 6060  * Gets the current PCI bus type, speed, and width of the hardware
 6061  *
 6062  * hw - Struct containing variables accessed by shared code
 6063  *****************************************************************************/
 6064 void
em_get_bus_info(struct em_hw *hw)
 6066 {
int32_t ret_val;
uint16_t pci_ex_link_status;
uint32_t status;
 6071     switch (hw->mac_type) {
 6072     case em_82542_rev2_0:
 6073     case em_82542_rev2_1:
hw->bus_type = em_bus_type_unknown;
hw->bus_speed = em_bus_speed_unknown;
hw->bus_width = em_bus_width_unknown;
 6077         break;
 6078     case em_82571:
 6079     case em_82572:
 6080     case em_82573:
 6081     case em_80003es2lan:
hw->bus_type = em_bus_type_pci_express;
hw->bus_speed = em_bus_speed_2500;
ret_val = em_read_pcie_cap_reg(hw,
PCI_EX_LINK_STATUS,
 6086                                       &pci_ex_link_status);
 6087         if (ret_val)
hw->bus_width = em_bus_width_unknown;
 6089         else
hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >>
PCI_EX_LINK_WIDTH_SHIFT;
 6092         break;
 6093     case em_ich8lan:
hw->bus_type = em_bus_type_pci_express;
hw->bus_speed = em_bus_speed_2500;
hw->bus_width = em_bus_width_pciex_1;
 6097         break;
 6098     default:
status = E1000_READ_REG(hw, STATUS);
hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
em_bus_type_pcix : em_bus_type_pci;
 6103         if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
hw->bus_speed = (hw->bus_type == em_bus_type_pci) ?
em_bus_speed_66 : em_bus_speed_120;
 6106         } else if (hw->bus_type == em_bus_type_pci) {
hw->bus_speed = (status & E1000_STATUS_PCI66) ?
em_bus_speed_66 : em_bus_speed_33;
 6109         } else {
 6110             switch (status & E1000_STATUS_PCIX_SPEED) {
 6111             case E1000_STATUS_PCIX_SPEED_66:
hw->bus_speed = em_bus_speed_66;
 6113                 break;
 6114             case E1000_STATUS_PCIX_SPEED_100:
hw->bus_speed = em_bus_speed_100;
 6116                 break;
 6117             case E1000_STATUS_PCIX_SPEED_133:
hw->bus_speed = em_bus_speed_133;
 6119                 break;
 6120             default:
hw->bus_speed = em_bus_speed_reserved;
 6122                 break;
 6123             }
 6124         }
hw->bus_width = (status & E1000_STATUS_BUS64) ?
em_bus_width_64 : em_bus_width_32;
 6127         break;
 6128     }
 6129 }
 6131 /******************************************************************************
 6132  * Writes a value to one of the devices registers using port I/O (as opposed to
 6133  * memory mapped I/O). Only 82544 and newer devices support port I/O.
 6134  *
 6135  * hw - Struct containing variables accessed by shared code
 6136  * offset - offset to write to
 6137  * value - value to write
 6138  *****************************************************************************/
STATIC void
em_write_reg_io(struct em_hw *hw,
uint32_t offset,
uint32_t value)
 6143 {
 6144     unsigned long io_addr = hw->io_base;
 6145     unsigned long io_data = hw->io_base + 4;
em_io_write(hw, io_addr, offset);
em_io_write(hw, io_data, value);
 6149 }
 6151 /******************************************************************************
 6152  * Estimates the cable length.
 6153  *
 6154  * hw - Struct containing variables accessed by shared code
 6155  * min_length - The estimated minimum length
 6156  * max_length - The estimated maximum length
 6157  *
 6158  * returns: - E1000_ERR_XXX
 6159  *            E1000_SUCCESS
 6160  *
 6161  * This function always returns a ranged length (minimum & maximum).
 6162  * So for M88 phy's, this function interprets the one value returned from the
 6163  * register to the minimum and maximum range.
 6164  * For IGP phy's, the function calculates the range by the AGC registers.
 6165  *****************************************************************************/
STATIC int32_t
em_get_cable_length(struct em_hw *hw,
uint16_t *min_length,
uint16_t *max_length)
 6170 {
int32_t ret_val;
uint16_t agc_value = 0;
uint16_t i, phy_data;
uint16_t cable_length;
DEBUGFUNC("em_get_cable_length");
 6178     *min_length = *max_length = 0;
 6180     /* Use old method for Phy older than IGP */
 6181     if (hw->phy_type == em_phy_m88) {
ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
 6184                                      &phy_data);
 6185         if (ret_val)
 6186             return ret_val;
cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
M88E1000_PSSR_CABLE_LENGTH_SHIFT;
 6190         /* Convert the enum value to ranged values */
 6191         switch (cable_length) {
 6192         case em_cable_length_50:
 6193             *min_length = 0;
 6194             *max_length = em_igp_cable_length_50;
 6195             break;
 6196         case em_cable_length_50_80:
 6197             *min_length = em_igp_cable_length_50;
 6198             *max_length = em_igp_cable_length_80;
 6199             break;
 6200         case em_cable_length_80_110:
 6201             *min_length = em_igp_cable_length_80;
 6202             *max_length = em_igp_cable_length_110;
 6203             break;
 6204         case em_cable_length_110_140:
 6205             *min_length = em_igp_cable_length_110;
 6206             *max_length = em_igp_cable_length_140;
 6207             break;
 6208         case em_cable_length_140:
 6209             *min_length = em_igp_cable_length_140;
 6210             *max_length = em_igp_cable_length_170;
 6211             break;
 6212         default:
 6213             return -E1000_ERR_PHY;
 6214             break;
 6215         }
 6216     } else if (hw->phy_type == em_phy_gg82563) {
ret_val = em_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
 6218                                      &phy_data);
 6219         if (ret_val)
 6220             return ret_val;
cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
 6223         switch (cable_length) {
 6224         case em_gg_cable_length_60:
 6225             *min_length = 0;
 6226             *max_length = em_igp_cable_length_60;
 6227             break;
 6228         case em_gg_cable_length_60_115:
 6229             *min_length = em_igp_cable_length_60;
 6230             *max_length = em_igp_cable_length_115;
 6231             break;
 6232         case em_gg_cable_length_115_150:
 6233             *min_length = em_igp_cable_length_115;
 6234             *max_length = em_igp_cable_length_150;
 6235             break;
 6236         case em_gg_cable_length_150:
 6237             *min_length = em_igp_cable_length_150;
 6238             *max_length = em_igp_cable_length_180;
 6239             break;
 6240         default:
 6241             return -E1000_ERR_PHY;
 6242             break;
 6243         }
 6244     } else if (hw->phy_type == em_phy_igp) { /* For IGP PHY */
uint16_t cur_agc_value;
uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
 6248                                                          {IGP01E1000_PHY_AGC_A,
IGP01E1000_PHY_AGC_B,
IGP01E1000_PHY_AGC_C,
IGP01E1000_PHY_AGC_D};
 6252         /* Read the AGC registers for all channels */
 6253         for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
ret_val = em_read_phy_reg(hw, agc_reg_array[i], &phy_data);
 6256             if (ret_val)
 6257                 return ret_val;
cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
 6261             /* Value bound check. */
 6262             if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
 6263                 (cur_agc_value == 0))
 6264                 return -E1000_ERR_PHY;
agc_value += cur_agc_value;
 6268             /* Update minimal AGC value. */
 6269             if (min_agc_value > cur_agc_value)
min_agc_value = cur_agc_value;
 6271         }
 6273         /* Remove the minimal AGC result for length < 50m */
 6274         if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * em_igp_cable_length_50) {
agc_value -= min_agc_value;
 6277             /* Get the average length of the remaining 3 channels */
agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
 6279         } else {
 6280             /* Get the average length of all the 4 channels. */
agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
 6282         }
 6284         /* Set the range of the calculated length. */
 6285         *min_length = ((em_igp_cable_length_table[agc_value] -
IGP01E1000_AGC_RANGE) > 0) ?
 6287                        (em_igp_cable_length_table[agc_value] -
IGP01E1000_AGC_RANGE) : 0;
 6289         *max_length = em_igp_cable_length_table[agc_value] +
IGP01E1000_AGC_RANGE;
 6291     } else if (hw->phy_type == em_phy_igp_2 ||
hw->phy_type == em_phy_igp_3) {
uint16_t cur_agc_index, max_agc_index = 0;
uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
 6296                                                          {IGP02E1000_PHY_AGC_A,
IGP02E1000_PHY_AGC_B,
IGP02E1000_PHY_AGC_C,
IGP02E1000_PHY_AGC_D};
 6300         /* Read the AGC registers for all channels */
 6301         for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
ret_val = em_read_phy_reg(hw, agc_reg_array[i], &phy_data);
 6303             if (ret_val)
 6304                 return ret_val;
 6306             /* Getting bits 15:9, which represent the combination of course and
 6307              * fine gain values.  The result is a number that can be put into
 6308              * the lookup table to obtain the approximate cable length. */
cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
IGP02E1000_AGC_LENGTH_MASK;
 6312             /* Array index bound check. */
 6313             if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) ||
 6314                 (cur_agc_index == 0))
 6315                 return -E1000_ERR_PHY;
 6317             /* Remove min & max AGC values from calculation. */
 6318             if (em_igp_2_cable_length_table[min_agc_index] >
em_igp_2_cable_length_table[cur_agc_index])
min_agc_index = cur_agc_index;
 6321             if (em_igp_2_cable_length_table[max_agc_index] <
em_igp_2_cable_length_table[cur_agc_index])
max_agc_index = cur_agc_index;
agc_value += em_igp_2_cable_length_table[cur_agc_index];
 6326         }
agc_value -= (em_igp_2_cable_length_table[min_agc_index] +
em_igp_2_cable_length_table[max_agc_index]);
agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
 6332         /* Calculate cable length with the error range of +/- 10 meters. */
 6333         *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
 6334                        (agc_value - IGP02E1000_AGC_RANGE) : 0;
 6335         *max_length = agc_value + IGP02E1000_AGC_RANGE;
 6336     }
 6338     return E1000_SUCCESS;
 6339 }
 6341 /******************************************************************************
 6342  * Check if Downshift occured
 6343  *
 6344  * hw - Struct containing variables accessed by shared code
 6345  * downshift - output parameter : 0 - No Downshift ocured.
 6346  *                                1 - Downshift ocured.
 6347  *
 6348  * returns: - E1000_ERR_XXX
 6349  *            E1000_SUCCESS
 6350  *
 6351  * For phy's older then IGP, this function reads the Downshift bit in the Phy
 6352  * Specific Status register.  For IGP phy's, it reads the Downgrade bit in the
 6353  * Link Health register.  In IGP this bit is latched high, so the driver must
 6354  * read it immediately after link is established.
 6355  *****************************************************************************/
STATIC int32_t
em_check_downshift(struct em_hw *hw)
 6358 {
int32_t ret_val;
uint16_t phy_data;
DEBUGFUNC("em_check_downshift");
 6364     if (hw->phy_type == em_phy_igp ||
hw->phy_type == em_phy_igp_3 ||
hw->phy_type == em_phy_igp_2) {
ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
 6368                                      &phy_data);
 6369         if (ret_val)
 6370             return ret_val;
hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
 6373     } else if ((hw->phy_type == em_phy_m88) ||
 6374                (hw->phy_type == em_phy_gg82563)) {
ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
 6376                                      &phy_data);
 6377         if (ret_val)
 6378             return ret_val;
hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
M88E1000_PSSR_DOWNSHIFT_SHIFT;
 6382     } else if (hw->phy_type == em_phy_ife) {
 6383         /* em_phy_ife supports 10/100 speed only */
hw->speed_downgraded = FALSE;
 6385     }
 6387     return E1000_SUCCESS;
 6388 }
 6390 /*****************************************************************************
 6391  *
 6392  * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
 6393  * gigabit link is achieved to improve link quality.
 6394  *
 6395  * hw: Struct containing variables accessed by shared code
 6396  *
 6397  * returns: - E1000_ERR_PHY if fail to read/write the PHY
 6398  *            E1000_SUCCESS at any other case.
 6399  *
 6400  ****************************************************************************/
STATIC int32_t
em_config_dsp_after_link_change(struct em_hw *hw,
boolean_t link_up)
 6405 {
int32_t ret_val;
uint16_t phy_data, phy_saved_data, speed, duplex, i;
uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
 6409                                         {IGP01E1000_PHY_AGC_PARAM_A,
IGP01E1000_PHY_AGC_PARAM_B,
IGP01E1000_PHY_AGC_PARAM_C,
IGP01E1000_PHY_AGC_PARAM_D};
uint16_t min_length, max_length;
DEBUGFUNC("em_config_dsp_after_link_change");
 6417     if (hw->phy_type != em_phy_igp)
 6418         return E1000_SUCCESS;
 6420     if (link_up) {
ret_val = em_get_speed_and_duplex(hw, &speed, &duplex);
 6422         if (ret_val) {
DEBUGOUT("Error getting link speed and duplex\n");
 6424             return ret_val;
 6425         }
 6427         if (speed == SPEED_1000) {
ret_val = em_get_cable_length(hw, &min_length, &max_length);
 6430             if (ret_val)
 6431                 return ret_val;
 6433             if ((hw->dsp_config_state == em_dsp_config_enabled) &&
min_length >= em_igp_cable_length_50) {
 6436                 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
ret_val = em_read_phy_reg(hw, dsp_reg_array[i],
 6438                                                  &phy_data);
 6439                     if (ret_val)
 6440                         return ret_val;
phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
ret_val = em_write_phy_reg(hw, dsp_reg_array[i],
phy_data);
 6446                     if (ret_val)
 6447                         return ret_val;
 6448                 }
hw->dsp_config_state = em_dsp_config_activated;
 6450             }
 6452             if ((hw->ffe_config_state == em_ffe_config_enabled) &&
 6453                (min_length < em_igp_cable_length_50)) {
uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
uint32_t idle_errs = 0;
 6458                 /* clear previous idle error counts */
ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS,
 6460                                              &phy_data);
 6461                 if (ret_val)
 6462                     return ret_val;
 6464                 for (i = 0; i < ffe_idle_err_timeout; i++) {
usec_delay(1000);
ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS,
 6467                                                  &phy_data);
 6468                     if (ret_val)
 6469                         return ret_val;
idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
 6472                     if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
hw->ffe_config_state = em_ffe_config_active;
ret_val = em_write_phy_reg(hw,
IGP01E1000_PHY_DSP_FFE,
IGP01E1000_PHY_DSP_FFE_CM_CP);
 6478                         if (ret_val)
 6479                             return ret_val;
 6480                         break;
 6481                     }
 6483                     if (idle_errs)
ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
 6485                 }
 6486             }
 6487         }
 6488     } else {
 6489         if (hw->dsp_config_state == em_dsp_config_activated) {
 6490             /* Save off the current value of register 0x2F5B to be restored at
 6491              * the end of the routines. */
ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
 6494             if (ret_val)
 6495                 return ret_val;
 6497             /* Disable the PHY transmitter */
ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003);
 6500             if (ret_val)
 6501                 return ret_val;
msec_delay_irq(20);
ret_val = em_write_phy_reg(hw, 0x0000,
IGP01E1000_IEEE_FORCE_GIGA);
 6507             if (ret_val)
 6508                 return ret_val;
 6509             for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
ret_val = em_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
 6511                 if (ret_val)
 6512                     return ret_val;
phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
phy_data |=  IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
ret_val = em_write_phy_reg(hw,dsp_reg_array[i], phy_data);
 6518                 if (ret_val)
 6519                     return ret_val;
 6520             }
ret_val = em_write_phy_reg(hw, 0x0000,
IGP01E1000_IEEE_RESTART_AUTONEG);
 6524             if (ret_val)
 6525                 return ret_val;
msec_delay_irq(20);
 6529             /* Now enable the transmitter */
ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data);
 6532             if (ret_val)
 6533                 return ret_val;
hw->dsp_config_state = em_dsp_config_enabled;
 6536         }
 6538         if (hw->ffe_config_state == em_ffe_config_active) {
 6539             /* Save off the current value of register 0x2F5B to be restored at
 6540              * the end of the routines. */
ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
 6543             if (ret_val)
 6544                 return ret_val;
 6546             /* Disable the PHY transmitter */
ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003);
 6549             if (ret_val)
 6550                 return ret_val;
msec_delay_irq(20);
ret_val = em_write_phy_reg(hw, 0x0000,
IGP01E1000_IEEE_FORCE_GIGA);
 6556             if (ret_val)
 6557                 return ret_val;
ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
IGP01E1000_PHY_DSP_FFE_DEFAULT);
 6560             if (ret_val)
 6561                 return ret_val;
ret_val = em_write_phy_reg(hw, 0x0000,
IGP01E1000_IEEE_RESTART_AUTONEG);
 6565             if (ret_val)
 6566                 return ret_val;
msec_delay_irq(20);
 6570             /* Now enable the transmitter */
ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data);
 6573             if (ret_val)
 6574                 return ret_val;
hw->ffe_config_state = em_ffe_config_enabled;
 6577         }
 6578     }
 6579     return E1000_SUCCESS;
 6580 }
 6582 /*****************************************************************************
 6583  * Set PHY to class A mode
 6584  * Assumes the following operations will follow to enable the new class mode.
 6585  *  1. Do a PHY soft reset
 6586  *  2. Restart auto-negotiation or force link.
 6587  *
 6588  * hw - Struct containing variables accessed by shared code
 6589  ****************************************************************************/
 6590 static int32_t
em_set_phy_mode(struct em_hw *hw)
 6592 {
int32_t ret_val;
uint16_t eeprom_data;
DEBUGFUNC("em_set_phy_mode");
 6598     if ((hw->mac_type == em_82545_rev_3) &&
 6599         (hw->media_type == em_media_type_copper)) {
ret_val = em_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
 6601         if (ret_val) {
 6602             return ret_val;
 6603         }
 6605         if ((eeprom_data != EEPROM_RESERVED_WORD) &&
 6606             (eeprom_data & EEPROM_PHY_CLASS_A)) {
ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
 6608             if (ret_val)
 6609                 return ret_val;
ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
 6611             if (ret_val)
 6612                 return ret_val;
hw->phy_reset_disable = FALSE;
 6615         }
 6616     }
 6618     return E1000_SUCCESS;
 6619 }
 6621 /*****************************************************************************
 6622  *
 6623  * This function sets the lplu state according to the active flag.  When
 6624  * activating lplu this function also disables smart speed and vise versa.
 6625  * lplu will not be activated unless the device autonegotiation advertisement
 6626  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
 6627  * hw: Struct containing variables accessed by shared code
 6628  * active - true to enable lplu false to disable lplu.
 6629  *
 6630  * returns: - E1000_ERR_PHY if fail to read/write the PHY
 6631  *            E1000_SUCCESS at any other case.
 6632  *
 6633  ****************************************************************************/
STATIC int32_t
em_set_d3_lplu_state(struct em_hw *hw,
boolean_t active)
 6638 {
uint32_t phy_ctrl = 0;
int32_t ret_val;
uint16_t phy_data;
DEBUGFUNC("em_set_d3_lplu_state");
 6644     if (hw->phy_type != em_phy_igp && hw->phy_type != em_phy_igp_2
 6645         && hw->phy_type != em_phy_igp_3)
 6646         return E1000_SUCCESS;
 6648     /* During driver activity LPLU should not be used or it will attain link
 6649      * from the lowest speeds starting from 10Mbps. The capability is used for
 6650      * Dx transitions and states */
 6651     if (hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) {
ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
 6653         if (ret_val)
 6654             return ret_val;
 6655     } else if (hw->mac_type == em_ich8lan) {
 6656         /* MAC writes into PHY register based on the state transition
 6657          * and start auto-negotiation. SW driver can overwrite the settings
 6658          * in CSR PHY power control E1000_PHY_CTRL register. */
phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
 6660     } else {
ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
 6662         if (ret_val)
 6663             return ret_val;
 6664     }
 6666     if (!active) {
 6667         if (hw->mac_type == em_82541_rev_2 ||
hw->mac_type == em_82547_rev_2) {
phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
 6671             if (ret_val)
 6672                 return ret_val;
 6673         } else {
 6674             if (hw->mac_type == em_ich8lan) {
phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
 6677             } else {
phy_data &= ~IGP02E1000_PM_D3_LPLU;
ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
phy_data);
 6681                 if (ret_val)
 6682                     return ret_val;
 6683             }
 6684         }
 6686         /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
 6687          * Dx states where the power conservation is most important.  During
 6688          * driver activity we should enable SmartSpeed, so performance is
 6689          * maintained. */
 6690         if (hw->smart_speed == em_smart_speed_on) {
ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 6692                                          &phy_data);
 6693             if (ret_val)
 6694                 return ret_val;
phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
phy_data);
 6699             if (ret_val)
 6700                 return ret_val;
 6701         } else if (hw->smart_speed == em_smart_speed_off) {
ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 6703                                          &phy_data);
 6704             if (ret_val)
 6705                 return ret_val;
phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
phy_data);
 6710             if (ret_val)
 6711                 return ret_val;
 6712         }
 6714     } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
 6715                (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
 6716                (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
 6718         if (hw->mac_type == em_82541_rev_2 ||
hw->mac_type == em_82547_rev_2) {
phy_data |= IGP01E1000_GMII_FLEX_SPD;
ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
 6722             if (ret_val)
 6723                 return ret_val;
 6724         } else {
 6725             if (hw->mac_type == em_ich8lan) {
phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
 6728             } else {
phy_data |= IGP02E1000_PM_D3_LPLU;
ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
phy_data);
 6732                 if (ret_val)
 6733                     return ret_val;
 6734             }
 6735         }
 6737         /* When LPLU is enabled we should disable SmartSpeed */
ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
 6739         if (ret_val)
 6740             return ret_val;
phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
 6744         if (ret_val)
 6745             return ret_val;
 6747     }
 6748     return E1000_SUCCESS;
 6749 }
 6751 /*****************************************************************************
 6752  *
 6753  * This function sets the lplu d0 state according to the active flag.  When
 6754  * activating lplu this function also disables smart speed and vise versa.
 6755  * lplu will not be activated unless the device autonegotiation advertisement
 6756  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
 6757  * hw: Struct containing variables accessed by shared code
 6758  * active - true to enable lplu false to disable lplu.
 6759  *
 6760  * returns: - E1000_ERR_PHY if fail to read/write the PHY
 6761  *            E1000_SUCCESS at any other case.
 6762  *
 6763  ****************************************************************************/
STATIC int32_t
em_set_d0_lplu_state(struct em_hw *hw,
boolean_t active)
 6768 {
uint32_t phy_ctrl = 0;
int32_t ret_val;
uint16_t phy_data;
DEBUGFUNC("em_set_d0_lplu_state");
 6774     if (hw->mac_type <= em_82547_rev_2)
 6775         return E1000_SUCCESS;
 6777     if (hw->mac_type == em_ich8lan) {
phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
 6779     } else {
ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
 6781         if (ret_val)
 6782             return ret_val;
 6783     }
 6785     if (!active) {
 6786         if (hw->mac_type == em_ich8lan) {
phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
 6789         } else {
phy_data &= ~IGP02E1000_PM_D0_LPLU;
ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
 6792             if (ret_val)
 6793                 return ret_val;
 6794         }
 6796         /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
 6797          * Dx states where the power conservation is most important.  During
 6798          * driver activity we should enable SmartSpeed, so performance is
 6799          * maintained. */
 6800         if (hw->smart_speed == em_smart_speed_on) {
ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 6802                                          &phy_data);
 6803             if (ret_val)
 6804                 return ret_val;
phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
phy_data);
 6809             if (ret_val)
 6810                 return ret_val;
 6811         } else if (hw->smart_speed == em_smart_speed_off) {
ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 6813                                          &phy_data);
 6814             if (ret_val)
 6815                 return ret_val;
phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
phy_data);
 6820             if (ret_val)
 6821                 return ret_val;
 6822         }
 6825     } else {
 6827         if (hw->mac_type == em_ich8lan) {
phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
 6830         } else {
phy_data |= IGP02E1000_PM_D0_LPLU;
ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
 6833             if (ret_val)
 6834                 return ret_val;
 6835         }
 6837         /* When LPLU is enabled we should disable SmartSpeed */
ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
 6839         if (ret_val)
 6840             return ret_val;
phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
 6844         if (ret_val)
 6845             return ret_val;
 6847     }
 6848     return E1000_SUCCESS;
 6849 }
 6851 /******************************************************************************
 6852  * Change VCO speed register to improve Bit Error Rate performance of SERDES.
 6853  *
 6854  * hw - Struct containing variables accessed by shared code
 6855  *****************************************************************************/
 6856 static int32_t
em_set_vco_speed(struct em_hw *hw)
 6858 {
int32_t  ret_val;
uint16_t default_page = 0;
uint16_t phy_data;
DEBUGFUNC("em_set_vco_speed");
 6865     switch (hw->mac_type) {
 6866     case em_82545_rev_3:
 6867     case em_82546_rev_3:
 6868        break;
 6869     default:
 6870         return E1000_SUCCESS;
 6871     }
 6873     /* Set PHY register 30, page 5, bit 8 to 0 */
ret_val = em_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
 6876     if (ret_val)
 6877         return ret_val;
ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
 6880     if (ret_val)
 6881         return ret_val;
ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
 6884     if (ret_val)
 6885         return ret_val;
phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
 6889     if (ret_val)
 6890         return ret_val;
 6892     /* Set PHY register 30, page 4, bit 11 to 1 */
ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
 6895     if (ret_val)
 6896         return ret_val;
ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
 6899     if (ret_val)
 6900         return ret_val;
phy_data |= M88E1000_PHY_VCO_REG_BIT11;
ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
 6904     if (ret_val)
 6905         return ret_val;
ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
 6908     if (ret_val)
 6909         return ret_val;
 6911     return E1000_SUCCESS;
 6912 }
 6915 /*****************************************************************************
 6916  * This function reads the cookie from ARC ram.
 6917  *
 6918  * returns: - E1000_SUCCESS .
 6919  ****************************************************************************/
STATIC int32_t
em_host_if_read_cookie(struct em_hw * hw, uint8_t *buffer)
 6922 {
uint8_t i;
uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET;
uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH;
length = (length >> 2);
offset = (offset >> 2);
 6930     for (i = 0; i < length; i++) {
 6931         *((uint32_t *) buffer + i) =
E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
 6933     }
 6934     return E1000_SUCCESS;
 6935 }
 6938 /*****************************************************************************
 6939  * This function checks whether the HOST IF is enabled for command operaton
 6940  * and also checks whether the previous command is completed.
 6941  * It busy waits in case of previous command is not completed.
 6942  *
 6943  * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
 6944  *            timeout
 6945  *          - E1000_SUCCESS for success.
 6946  ****************************************************************************/
STATIC int32_t
em_mng_enable_host_if(struct em_hw * hw)
 6949 {
uint32_t hicr;
uint8_t i;
 6953     /* Check that the host interface is enabled. */
hicr = E1000_READ_REG(hw, HICR);
 6955     if ((hicr & E1000_HICR_EN) == 0) {
DEBUGOUT("E1000_HOST_EN bit disabled.\n");
 6957         return -E1000_ERR_HOST_INTERFACE_COMMAND;
 6958     }
 6959     /* check the previous command is completed */
 6960     for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
hicr = E1000_READ_REG(hw, HICR);
 6962         if (!(hicr & E1000_HICR_C))
 6963             break;
msec_delay_irq(1);
 6965     }
 6967     if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
DEBUGOUT("Previous command timeout failed .\n");
 6969         return -E1000_ERR_HOST_INTERFACE_COMMAND;
 6970     }
 6971     return E1000_SUCCESS;
 6972 }
 6974 /*****************************************************************************
 6975  * This function checks the mode of the firmware.
 6976  *
 6977  * returns  - TRUE when the mode is IAMT or FALSE.
 6978  ****************************************************************************/
boolean_t
em_check_mng_mode(struct em_hw *hw)
 6981 {
uint32_t fwsm;
fwsm = E1000_READ_REG(hw, FWSM);
 6986     if (hw->mac_type == em_ich8lan) {
 6987         if ((fwsm & E1000_FWSM_MODE_MASK) ==
 6988             (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
 6989             return TRUE;
 6990     } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
 6991                (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
 6992         return TRUE;
 6994     return FALSE;
 6995 }
 6997 /*****************************************************************************
 6998  * This function calculates the checksum.
 6999  *
 7000  * returns  - checksum of buffer contents.
 7001  ****************************************************************************/
STATIC uint8_t
em_calculate_mng_checksum(char *buffer, uint32_t length)
 7004 {
uint8_t sum = 0;
uint32_t i;
 7008     if (!buffer)
 7009         return 0;
 7011     for (i=0; i < length; i++)
sum += buffer[i];
 7014     return (uint8_t) (0 - sum);
 7015 }
 7017 /*****************************************************************************
 7018  * This function checks whether tx pkt filtering needs to be enabled or not.
 7019  *
 7020  * returns  - TRUE for packet filtering or FALSE.
 7021  ****************************************************************************/
boolean_t
em_enable_tx_pkt_filtering(struct em_hw *hw)
 7024 {
 7025     /* called in init as well as watchdog timer functions */
int32_t ret_val, checksum;
boolean_t tx_filter = FALSE;
 7029     struct em_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
uint8_t *buffer = (uint8_t *) &(hw->mng_cookie);
 7032     if (em_check_mng_mode(hw)) {
ret_val = em_mng_enable_host_if(hw);
 7034         if (ret_val == E1000_SUCCESS) {
ret_val = em_host_if_read_cookie(hw, buffer);
 7036             if (ret_val == E1000_SUCCESS) {
checksum = hdr->checksum;
hdr->checksum = 0;
 7039                 if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
checksum == em_calculate_mng_checksum((char *)buffer,
E1000_MNG_DHCP_COOKIE_LENGTH)) {
 7042                     if (hdr->status &
E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
tx_filter = TRUE;
 7045                 } else
tx_filter = TRUE;
 7047             } else
tx_filter = TRUE;
 7049         }
 7050     }
hw->tx_pkt_filtering = tx_filter;
 7053     return tx_filter;
 7054 }
 7057 static int32_t
em_polarity_reversal_workaround(struct em_hw *hw)
 7059 {
int32_t ret_val;
uint16_t mii_status_reg;
uint16_t i;
 7064     /* Polarity reversal workaround for forced 10F/10H links. */
 7066     /* Disable the transmitter on the PHY */
ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
 7069     if (ret_val)
 7070         return ret_val;
ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
 7072     if (ret_val)
 7073         return ret_val;
ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
 7076     if (ret_val)
 7077         return ret_val;
 7079     /* This loop will early-out if the NO link condition has been met. */
 7080     for (i = PHY_FORCE_TIME; i > 0; i--) {
 7081         /* Read the MII Status Register and wait for Link Status bit
 7082          * to be clear.
 7083          */
ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
 7086         if (ret_val)
 7087             return ret_val;
ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
 7090         if (ret_val)
 7091             return ret_val;
 7093         if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
msec_delay_irq(100);
 7095     }
 7097     /* Recommended delay time after link has been lost */
msec_delay_irq(1000);
 7100     /* Now we will re-enable the transmitter on the PHY */
ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
 7103     if (ret_val)
 7104         return ret_val;
msec_delay_irq(50);
ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
 7107     if (ret_val)
 7108         return ret_val;
msec_delay_irq(50);
ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
 7111     if (ret_val)
 7112         return ret_val;
msec_delay_irq(50);
ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
 7115     if (ret_val)
 7116         return ret_val;
ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
 7119     if (ret_val)
 7120         return ret_val;
 7122     /* This loop will early-out if the link condition has been met. */
 7123     for (i = PHY_FORCE_TIME; i > 0; i--) {
 7124         /* Read the MII Status Register and wait for Link Status bit
 7125          * to be set.
 7126          */
ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
 7129         if (ret_val)
 7130             return ret_val;
ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
 7133         if (ret_val)
 7134             return ret_val;
 7136         if (mii_status_reg & MII_SR_LINK_STATUS) break;
msec_delay_irq(100);
 7138     }
 7139     return E1000_SUCCESS;
 7140 }
 7142 /***************************************************************************
 7143  *
 7144  * Disables PCI-Express master access.
 7145  *
 7146  * hw: Struct containing variables accessed by shared code
 7147  *
 7148  * returns: - none.
 7149  *
 7150  ***************************************************************************/
STATIC void
em_set_pci_express_master_disable(struct em_hw *hw)
 7153 {
uint32_t ctrl;
DEBUGFUNC("em_set_pci_express_master_disable");
 7158     if (hw->bus_type != em_bus_type_pci_express)
 7159         return;
ctrl = E1000_READ_REG(hw, CTRL);
ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
E1000_WRITE_REG(hw, CTRL, ctrl);
 7164 }
 7166 /*******************************************************************************
 7167  *
 7168  * Disables PCI-Express master access and verifies there are no pending requests
 7169  *
 7170  * hw: Struct containing variables accessed by shared code
 7171  *
 7172  * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
 7173  *            caused the master requests to be disabled.
 7174  *            E1000_SUCCESS master requests disabled.
 7175  *
 7176  ******************************************************************************/
int32_t
em_disable_pciex_master(struct em_hw *hw)
 7179 {
int32_t timeout = MASTER_DISABLE_TIMEOUT;   /* 80ms */
DEBUGFUNC("em_disable_pciex_master");
 7184     if (hw->bus_type != em_bus_type_pci_express)
 7185         return E1000_SUCCESS;
em_set_pci_express_master_disable(hw);
 7189     while (timeout) {
 7190         if (!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
 7191             break;
 7192         else
usec_delay(100);
timeout--;
 7195     }
 7197     if (!timeout) {
DEBUGOUT("Master requests are pending.\n");
 7199         return -E1000_ERR_MASTER_REQUESTS_PENDING;
 7200     }
 7202     return E1000_SUCCESS;
 7203 }
 7205 /*******************************************************************************
 7206  *
 7207  * Check for EEPROM Auto Read bit done.
 7208  *
 7209  * hw: Struct containing variables accessed by shared code
 7210  *
 7211  * returns: - E1000_ERR_RESET if fail to reset MAC
 7212  *            E1000_SUCCESS at any other case.
 7213  *
 7214  ******************************************************************************/
STATIC int32_t
em_get_auto_rd_done(struct em_hw *hw)
 7217 {
int32_t timeout = AUTO_READ_DONE_TIMEOUT;
DEBUGFUNC("em_get_auto_rd_done");
 7222     switch (hw->mac_type) {
 7223     default:
msec_delay(5);
 7225         break;
 7226     case em_82571:
 7227     case em_82572:
 7228     case em_82573:
 7229     case em_80003es2lan:
 7230     case em_ich8lan:
 7231         while (timeout) {
 7232             if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
 7233                 break;
 7234             else msec_delay(1);
timeout--;
 7236         }
 7238         if (!timeout) {
DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
 7240             return -E1000_ERR_RESET;
 7241         }
 7242         break;
 7243     }
 7245     /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high.
 7246      * Need to wait for PHY configuration completion before accessing NVM
 7247      * and PHY. */
 7248     if (hw->mac_type == em_82573)
msec_delay(25);
 7251     return E1000_SUCCESS;
 7252 }
 7254 /***************************************************************************
 7255  * Checks if the PHY configuration is done
 7256  *
 7257  * hw: Struct containing variables accessed by shared code
 7258  *
 7259  * returns: - E1000_ERR_RESET if fail to reset MAC
 7260  *            E1000_SUCCESS at any other case.
 7261  *
 7262  ***************************************************************************/
STATIC int32_t
em_get_phy_cfg_done(struct em_hw *hw)
 7265 {
int32_t timeout = PHY_CFG_TIMEOUT;
uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
DEBUGFUNC("em_get_phy_cfg_done");
 7271     switch (hw->mac_type) {
 7272     default:
msec_delay_irq(10);
 7274         break;
 7275     case em_80003es2lan:
 7276         /* Separate *_CFG_DONE_* bit for each port */
 7277         if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
 7279         /* FALLTHROUGH */
 7280     case em_82571:
 7281     case em_82572:
 7282         while (timeout) {
 7283             if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
 7284                 break;
 7285             else
msec_delay(1);
timeout--;
 7288         }
 7289         if (!timeout) {
DEBUGOUT("MNG configuration cycle has not completed.\n");
 7291             return -E1000_ERR_RESET;
 7292         }
 7293         break;
 7294     }
 7296     return E1000_SUCCESS;
 7297 }
 7299 /***************************************************************************
 7300  *
 7301  * Using the combination of SMBI and SWESMBI semaphore bits when resetting
 7302  * adapter or Eeprom access.
 7303  *
 7304  * hw: Struct containing variables accessed by shared code
 7305  *
 7306  * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
 7307  *            E1000_SUCCESS at any other case.
 7308  *
 7309  ***************************************************************************/
STATIC int32_t
em_get_hw_eeprom_semaphore(struct em_hw *hw)
 7312 {
int32_t timeout;
uint32_t swsm;
DEBUGFUNC("em_get_hw_eeprom_semaphore");
 7318     if (!hw->eeprom_semaphore_present)
 7319         return E1000_SUCCESS;
 7321     if (hw->mac_type == em_80003es2lan) {
 7322         /* Get the SW semaphore. */
 7323         if (em_get_software_semaphore(hw) != E1000_SUCCESS)
 7324             return -E1000_ERR_EEPROM;
 7325     }
 7327     /* Get the FW semaphore. */
timeout = hw->eeprom.word_size + 1;
 7329     while (timeout) {
swsm = E1000_READ_REG(hw, SWSM);
swsm |= E1000_SWSM_SWESMBI;
E1000_WRITE_REG(hw, SWSM, swsm);
 7333         /* if we managed to set the bit we got the semaphore. */
swsm = E1000_READ_REG(hw, SWSM);
 7335         if (swsm & E1000_SWSM_SWESMBI)
 7336             break;
usec_delay(50);
timeout--;
 7340     }
 7342     if (!timeout) {
 7343         /* Release semaphores */
em_put_hw_eeprom_semaphore(hw);
DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
 7346         return -E1000_ERR_EEPROM;
 7347     }
 7349     return E1000_SUCCESS;
 7350 }
 7352 /***************************************************************************
 7353  * This function clears HW semaphore bits.
 7354  *
 7355  * hw: Struct containing variables accessed by shared code
 7356  *
 7357  * returns: - None.
 7358  *
 7359  ***************************************************************************/
STATIC void
em_put_hw_eeprom_semaphore(struct em_hw *hw)
 7362 {
uint32_t swsm;
DEBUGFUNC("em_put_hw_eeprom_semaphore");
 7367     if (!hw->eeprom_semaphore_present)
 7368         return;
swsm = E1000_READ_REG(hw, SWSM);
 7371     if (hw->mac_type == em_80003es2lan) {
 7372         /* Release both semaphores. */
swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
 7374     } else
swsm &= ~(E1000_SWSM_SWESMBI);
E1000_WRITE_REG(hw, SWSM, swsm);
 7377 }
 7379 /***************************************************************************
 7380  *
 7381  * Obtaining software semaphore bit (SMBI) before resetting PHY.
 7382  *
 7383  * hw: Struct containing variables accessed by shared code
 7384  *
 7385  * returns: - E1000_ERR_RESET if fail to obtain semaphore.
 7386  *            E1000_SUCCESS at any other case.
 7387  *
 7388  ***************************************************************************/
STATIC int32_t
em_get_software_semaphore(struct em_hw *hw)
 7391 {
int32_t timeout = hw->eeprom.word_size + 1;
uint32_t swsm;
DEBUGFUNC("em_get_software_semaphore");
 7397     if (hw->mac_type != em_80003es2lan)
 7398         return E1000_SUCCESS;
 7400     while (timeout) {
swsm = E1000_READ_REG(hw, SWSM);
 7402         /* If SMBI bit cleared, it is now set and we hold the semaphore */
 7403         if (!(swsm & E1000_SWSM_SMBI))
 7404             break;
msec_delay_irq(1);
timeout--;
 7407     }
 7409     if (!timeout) {
DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
 7411         return -E1000_ERR_RESET;
 7412     }
 7414     return E1000_SUCCESS;
 7415 }
 7417 /***************************************************************************
 7418  *
 7419  * Release semaphore bit (SMBI).
 7420  *
 7421  * hw: Struct containing variables accessed by shared code
 7422  *
 7423  ***************************************************************************/
STATIC void
em_release_software_semaphore(struct em_hw *hw)
 7426 {
uint32_t swsm;
DEBUGFUNC("em_release_software_semaphore");
 7431     if (hw->mac_type != em_80003es2lan)
 7432         return;
swsm = E1000_READ_REG(hw, SWSM);
 7435     /* Release the SW semaphores.*/
swsm &= ~E1000_SWSM_SMBI;
E1000_WRITE_REG(hw, SWSM, swsm);
 7438 }
 7440 /******************************************************************************
 7441  * Checks if PHY reset is blocked due to SOL/IDER session, for example.
 7442  * Returning E1000_BLK_PHY_RESET isn't necessarily an error.  But it's up to
 7443  * the caller to figure out how to deal with it.
 7444  *
 7445  * hw - Struct containing variables accessed by shared code
 7446  *
 7447  * returns: - E1000_BLK_PHY_RESET
 7448  *            E1000_SUCCESS
 7449  *
 7450  *****************************************************************************/
int32_t
em_check_phy_reset_block(struct em_hw *hw)
 7453 {
uint32_t manc = 0;
uint32_t fwsm = 0;
 7457     if (hw->mac_type == em_ich8lan) {
fwsm = E1000_READ_REG(hw, FWSM);
 7459         return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
 7460                                             : E1000_BLK_PHY_RESET;
 7461     }
 7463     if (hw->mac_type > em_82547_rev_2)
manc = E1000_READ_REG(hw, MANC);
 7465     return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
E1000_BLK_PHY_RESET : E1000_SUCCESS;
 7467 }
 7469 /******************************************************************************
 7470  * Configure PCI-Ex no-snoop
 7471  *
 7472  * hw - Struct containing variables accessed by shared code.
 7473  * no_snoop - Bitmap of no-snoop events.
 7474  *
 7475  * returns: E1000_SUCCESS
 7476  *
 7477  *****************************************************************************/
STATIC int32_t
em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop)
 7480 {
uint32_t gcr_reg = 0;
DEBUGFUNC("em_set_pci_ex_no_snoop");
 7485     if (hw->bus_type == em_bus_type_unknown)
em_get_bus_info(hw);
 7488     if (hw->bus_type != em_bus_type_pci_express)
 7489         return E1000_SUCCESS;
 7491     if (no_snoop) {
gcr_reg = E1000_READ_REG(hw, GCR);
gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
gcr_reg |= no_snoop;
E1000_WRITE_REG(hw, GCR, gcr_reg);
 7496     }
 7497     if (hw->mac_type == em_ich8lan) {
uint32_t ctrl_ext;
E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL);
ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
 7505     }
 7507     return E1000_SUCCESS;
 7508 }
 7510 /***************************************************************************
 7511  *
 7512  * Get software semaphore FLAG bit (SWFLAG).
 7513  * SWFLAG is used to synchronize the access to all shared resource between
 7514  * SW, FW and HW.
 7515  *
 7516  * hw: Struct containing variables accessed by shared code
 7517  *
 7518  ***************************************************************************/
STATIC int32_t
em_get_software_flag(struct em_hw *hw)
 7521 {
int32_t timeout = PHY_CFG_TIMEOUT;
uint32_t extcnf_ctrl;
DEBUGFUNC("em_get_software_flag");
 7527     if (hw->mac_type == em_ich8lan) {
 7528         while (timeout) {
extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
 7534             if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 7535                 break;
msec_delay_irq(1);
timeout--;
 7538         }
 7540         if (!timeout) {
DEBUGOUT("FW or HW locks the resource too long.\n");
 7542             return -E1000_ERR_CONFIG;
 7543         }
 7544     }
 7546     return E1000_SUCCESS;
 7547 }
 7549 /***************************************************************************
 7550  *
 7551  * Release software semaphore FLAG bit (SWFLAG).
 7552  * SWFLAG is used to synchronize the access to all shared resource between
 7553  * SW, FW and HW.
 7554  *
 7555  * hw: Struct containing variables accessed by shared code
 7556  *
 7557  ***************************************************************************/
STATIC void
em_release_software_flag(struct em_hw *hw)
 7560 {
uint32_t extcnf_ctrl;
DEBUGFUNC("em_release_software_flag");
 7565     if (hw->mac_type == em_ich8lan) {
extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL);
extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
 7569     }
 7571     return;
 7572 }
 7575 /******************************************************************************
 7576  * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
 7577  * register.
 7578  *
 7579  * hw - Struct containing variables accessed by shared code
 7580  * offset - offset of word in the EEPROM to read
 7581  * data - word read from the EEPROM
 7582  * words - number of words to read
 7583  *****************************************************************************/
STATIC int32_t
em_read_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words,
uint16_t *data)
 7587 {
int32_t  error = E1000_SUCCESS;
uint32_t flash_bank = 0;
uint32_t act_offset = 0;
uint32_t bank_offset = 0;
uint16_t word = 0;
uint16_t i = 0;
 7595     /* We need to know which is the valid flash bank.  In the event
 7596      * that we didn't allocate eeprom_shadow_ram, we may not be
 7597      * managing flash_bank.  So it cannot be trusted and needs
 7598      * to be updated with each read.
 7599      */
 7600     /* Value of bit 22 corresponds to the flash bank we're on. */
flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
 7603     /* Adjust offset appropriately if we're on bank 1 - adjust for word size */
bank_offset = flash_bank * (hw->flash_bank_size * 2);
error = em_get_software_flag(hw);
 7607     if (error != E1000_SUCCESS)
 7608         return error;
 7610     for (i = 0; i < words; i++) {
 7611         if (hw->eeprom_shadow_ram != NULL &&
hw->eeprom_shadow_ram[offset+i].modified == TRUE) {
data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
 7614         } else {
 7615             /* The NVM part needs a byte offset, hence * 2 */
act_offset = bank_offset + ((offset + i) * 2);
error = em_read_ich8_word(hw, act_offset, &word);
 7618             if (error != E1000_SUCCESS)
 7619                 break;
data[i] = word;
 7621         }
 7622     }
em_release_software_flag(hw);
 7626     return error;
 7627 }
 7629 /******************************************************************************
 7630  * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
 7631  * register.  Actually, writes are written to the shadow ram cache in the hw
 7632  * structure hw->em_shadow_ram.  em_commit_shadow_ram flushes this to
 7633  * the NVM, which occurs when the NVM checksum is updated.
 7634  *
 7635  * hw - Struct containing variables accessed by shared code
 7636  * offset - offset of word in the EEPROM to write
 7637  * words - number of words to write
 7638  * data - words to write to the EEPROM
 7639  *****************************************************************************/
STATIC int32_t
em_write_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words,
uint16_t *data)
 7643 {
uint32_t i = 0;
int32_t error = E1000_SUCCESS;
error = em_get_software_flag(hw);
 7648     if (error != E1000_SUCCESS)
 7649         return error;
 7651     /* A driver can write to the NVM only if it has eeprom_shadow_ram
 7652      * allocated.  Subsequent reads to the modified words are read from
 7653      * this cached structure as well.  Writes will only go into this
 7654      * cached structure unless it's followed by a call to
 7655      * em_update_eeprom_checksum() where it will commit the changes
 7656      * and clear the "modified" field.
 7657      */
 7658     if (hw->eeprom_shadow_ram != NULL) {
 7659         for (i = 0; i < words; i++) {
 7660             if ((offset + i) < E1000_SHADOW_RAM_WORDS) {
hw->eeprom_shadow_ram[offset+i].modified = TRUE;
hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i];
 7663             } else {
error = -E1000_ERR_EEPROM;
 7665                 break;
 7666             }
 7667         }
 7668     } else {
 7669         /* Drivers have the option to not allocate eeprom_shadow_ram as long
 7670          * as they don't perform any NVM writes.  An attempt in doing so
 7671          * will result in this error.
 7672          */
error = -E1000_ERR_EEPROM;
 7674     }
em_release_software_flag(hw);
 7678     return error;
 7679 }
 7681 /******************************************************************************
 7682  * This function does initial flash setup so that a new read/write/erase cycle
 7683  * can be started.
 7684  *
 7685  * hw - The pointer to the hw structure
 7686  ****************************************************************************/
STATIC int32_t
em_ich8_cycle_init(struct em_hw *hw)
 7689 {
 7690     union ich8_hws_flash_status hsfsts;
int32_t error = E1000_ERR_EEPROM;
int32_t i     = 0;
DEBUGFUNC("em_ich8_cycle_init");
hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
 7698     /* May be check the Flash Des Valid bit in Hw status */
 7699     if (hsfsts.hsf_status.fldesvalid == 0) {
DEBUGOUT("Flash descriptor invalid.  SW Sequencing must be used.");
 7701         return error;
 7702     }
 7704     /* Clear FCERR in Hw status by writing 1 */
 7705     /* Clear DAEL in Hw status by writing a 1 */
hsfsts.hsf_status.flcerr = 1;
hsfsts.hsf_status.dael = 1;
E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
 7711     /* Either we should have a hardware SPI cycle in progress bit to check
 7712      * against, in order to start a new cycle or FDONE bit should be changed
 7713      * in the hardware so that it is 1 after harware reset, which can then be
 7714      * used as an indication whether a cycle is in progress or has been
 7715      * completed .. we should also have some software semaphore mechanism to
 7716      * guard FDONE or the cycle in progress bit so that two threads access to
 7717      * those bits can be sequentiallized or a way so that 2 threads dont
 7718      * start the cycle at the same time */
 7720     if (hsfsts.hsf_status.flcinprog == 0) {
 7721         /* There is no cycle running at present, so we can start a cycle */
 7722         /* Begin by setting Flash Cycle Done. */
hsfsts.hsf_status.flcdone = 1;
E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
error = E1000_SUCCESS;
 7726     } else {
 7727         /* otherwise poll for sometime so the current cycle has a chance
 7728          * to end before giving up. */
 7729         for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) {
hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
 7731             if (hsfsts.hsf_status.flcinprog == 0) {
error = E1000_SUCCESS;
 7733                 break;
 7734             }
usec_delay(1);
 7736         }
 7737         if (error == E1000_SUCCESS) {
 7738             /* Successful in waiting for previous cycle to timeout,
 7739              * now set the Flash Cycle Done. */
hsfsts.hsf_status.flcdone = 1;
E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
 7742         } else {
DEBUGOUT("Flash controller busy, cannot get access");
 7744         }
 7745     }
 7746     return error;
 7747 }
 7749 /******************************************************************************
 7750  * This function starts a flash cycle and waits for its completion
 7751  *
 7752  * hw - The pointer to the hw structure
 7753  ****************************************************************************/
STATIC int32_t
em_ich8_flash_cycle(struct em_hw *hw, uint32_t timeout)
 7756 {
 7757     union ich8_hws_flash_ctrl hsflctl;
 7758     union ich8_hws_flash_status hsfsts;
int32_t error = E1000_ERR_EEPROM;
uint32_t i = 0;
 7762     /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
hsflctl.hsf_ctrl.flcgo = 1;
E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
 7767     /* wait till FDONE bit is set to 1 */
 7768     do {
hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
 7770         if (hsfsts.hsf_status.flcdone == 1)
 7771             break;
usec_delay(1);
i++;
 7774     } while (i < timeout);
 7775     if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) {
error = E1000_SUCCESS;
 7777     }
 7778     return error;
 7779 }
 7781 /******************************************************************************
 7782  * Reads a byte or word from the NVM using the ICH8 flash access registers.
 7783  *
 7784  * hw - The pointer to the hw structure
 7785  * index - The index of the byte or word to read.
 7786  * size - Size of data to read, 1=byte 2=word
 7787  * data - Pointer to the word to store the value read.
 7788  *****************************************************************************/
STATIC int32_t
em_read_ich8_data(struct em_hw *hw, uint32_t index,
uint32_t size, uint16_t* data)
 7792 {
 7793     union ich8_hws_flash_status hsfsts;
 7794     union ich8_hws_flash_ctrl hsflctl;
uint32_t flash_linear_address;
uint32_t flash_data = 0;
int32_t error = -E1000_ERR_EEPROM;
int32_t count = 0;
DEBUGFUNC("em_read_ich8_data");
 7802     if (size < 1  || size > 2 || data == 0x0 ||
index > ICH_FLASH_LINEAR_ADDR_MASK)
 7804         return error;
flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
hw->flash_base_addr;
 7809     do {
usec_delay(1);
 7811         /* Steps */
error = em_ich8_cycle_init(hw);
 7813         if (error != E1000_SUCCESS)
 7814             break;
hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
 7817         /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
hsflctl.hsf_ctrl.fldbcount = size - 1;
hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
 7822         /* Write the last 24 bits of index into Flash Linear address field in
 7823          * Flash Address */
 7824         /* TODO: TBD maybe check the index against the size of flash */
E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
 7830         /* Check if FCERR is set to 1, if set to 1, clear it and try the whole
 7831          * sequence a few more times, else read in (shift in) the Flash Data0,
 7832          * the order is least significant byte first msb to lsb */
 7833         if (error == E1000_SUCCESS) {
flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0);
 7835             if (size == 1) {
 7836                 *data = (uint8_t)(flash_data & 0x000000FF);
 7837             } else if (size == 2) {
 7838                 *data = (uint16_t)(flash_data & 0x0000FFFF);
 7839             }
 7840             break;
 7841         } else {
 7842             /* If we've gotten here, then things are probably completely hosed,
 7843              * but if the error condition is detected, it won't hurt to give
 7844              * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
 7845              */
hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
 7847             if (hsfsts.hsf_status.flcerr == 1) {
 7848                 /* Repeat for some time before giving up. */
 7849                 continue;
 7850             } else if (hsfsts.hsf_status.flcdone == 0) {
DEBUGOUT("Timeout error - flash cycle did not complete.");
 7852                 break;
 7853             }
 7854         }
 7855     } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
 7857     return error;
 7858 }
 7860 /******************************************************************************
 7861  * Writes One /two bytes to the NVM using the ICH8 flash access registers.
 7862  *
 7863  * hw - The pointer to the hw structure
 7864  * index - The index of the byte/word to read.
 7865  * size - Size of data to read, 1=byte 2=word
 7866  * data - The byte(s) to write to the NVM.
 7867  *****************************************************************************/
STATIC int32_t
em_write_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size,
uint16_t data)
 7871 {
 7872     union ich8_hws_flash_status hsfsts;
 7873     union ich8_hws_flash_ctrl hsflctl;
uint32_t flash_linear_address;
uint32_t flash_data = 0;
int32_t error = -E1000_ERR_EEPROM;
int32_t count = 0;
DEBUGFUNC("em_write_ich8_data");
 7881     if (size < 1  || size > 2 || data > size * 0xff ||
index > ICH_FLASH_LINEAR_ADDR_MASK)
 7883         return error;
flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
hw->flash_base_addr;
 7888     do {
usec_delay(1);
 7890         /* Steps */
error = em_ich8_cycle_init(hw);
 7892         if (error != E1000_SUCCESS)
 7893             break;
hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
 7896         /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
hsflctl.hsf_ctrl.fldbcount = size -1;
hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
 7901         /* Write the last 24 bits of index into Flash Linear address field in
 7902          * Flash Address */
E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
 7905         if (size == 1)
flash_data = (uint32_t)data & 0x00FF;
 7907         else
flash_data = (uint32_t)data;
E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
 7912         /* check if FCERR is set to 1 , if set to 1, clear it and try the whole
 7913          * sequence a few more times else done */
error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
 7915         if (error == E1000_SUCCESS) {
 7916             break;
 7917         } else {
 7918             /* If we're here, then things are most likely completely hosed,
 7919              * but if the error condition is detected, it won't hurt to give
 7920              * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
 7921              */
hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
 7923             if (hsfsts.hsf_status.flcerr == 1) {
 7924                 /* Repeat for some time before giving up. */
 7925                 continue;
 7926             } else if (hsfsts.hsf_status.flcdone == 0) {
DEBUGOUT("Timeout error - flash cycle did not complete.");
 7928                 break;
 7929             }
 7930         }
 7931     } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
 7933     return error;
 7934 }
 7936 /******************************************************************************
 7937  * Reads a single byte from the NVM using the ICH8 flash access registers.
 7938  *
 7939  * hw - pointer to em_hw structure
 7940  * index - The index of the byte to read.
 7941  * data - Pointer to a byte to store the value read.
 7942  *****************************************************************************/
STATIC int32_t
em_read_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t* data)
 7945 {
int32_t status = E1000_SUCCESS;
uint16_t word = 0;
status = em_read_ich8_data(hw, index, 1, &word);
 7950     if (status == E1000_SUCCESS) {
 7951         *data = (uint8_t)word;
 7952     }
 7954     return status;
 7955 }
 7957 /******************************************************************************
 7958  * Writes a single byte to the NVM using the ICH8 flash access registers.
 7959  * Performs verification by reading back the value and then going through
 7960  * a retry algorithm before giving up.
 7961  *
 7962  * hw - pointer to em_hw structure
 7963  * index - The index of the byte to write.
 7964  * byte - The byte to write to the NVM.
 7965  *****************************************************************************/
STATIC int32_t
em_verify_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t byte)
 7968 {
int32_t error = E1000_SUCCESS;
int32_t program_retries = 0;
DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index);
error = em_write_ich8_byte(hw, index, byte);
 7976     if (error != E1000_SUCCESS) {
 7977         for (program_retries = 0; program_retries < 100; program_retries++) {
DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", byte, index);
error = em_write_ich8_byte(hw, index, byte);
usec_delay(100);
 7981             if (error == E1000_SUCCESS)
 7982                 break;
 7983         }
 7984     }
 7986     if (program_retries == 100)
error = E1000_ERR_EEPROM;
 7989     return error;
 7990 }
 7992 /******************************************************************************
 7993  * Writes a single byte to the NVM using the ICH8 flash access registers.
 7994  *
 7995  * hw - pointer to em_hw structure
 7996  * index - The index of the byte to read.
 7997  * data - The byte to write to the NVM.
 7998  *****************************************************************************/
STATIC int32_t
em_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t data)
 8001 {
int32_t status = E1000_SUCCESS;
uint16_t word = (uint16_t)data;
status = em_write_ich8_data(hw, index, 1, word);
 8007     return status;
 8008 }
 8010 /******************************************************************************
 8011  * Reads a word from the NVM using the ICH8 flash access registers.
 8012  *
 8013  * hw - pointer to em_hw structure
 8014  * index - The starting byte index of the word to read.
 8015  * data - Pointer to a word to store the value read.
 8016  *****************************************************************************/
STATIC int32_t
em_read_ich8_word(struct em_hw *hw, uint32_t index, uint16_t *data)
 8019 {
int32_t status = E1000_SUCCESS;
status = em_read_ich8_data(hw, index, 2, data);
 8022     return status;
 8023 }
 8026 /******************************************************************************
 8027  * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0
 8028  * based.
 8029  *
 8030  * hw - pointer to em_hw structure
 8031  * bank - 0 for first bank, 1 for second bank
 8032  *
 8033  * Note that this function may actually erase as much as 8 or 64 KBytes.  The
 8034  * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the
 8035  * bank size may be 4, 8 or 64 KBytes
 8036  *****************************************************************************/
int32_t
em_erase_ich8_4k_segment(struct em_hw *hw, uint32_t bank)
 8039 {
 8040     union ich8_hws_flash_status hsfsts;
 8041     union ich8_hws_flash_ctrl hsflctl;
uint32_t flash_linear_address;
int32_t  count = 0;
int32_t  error = E1000_ERR_EEPROM;
int32_t  iteration;
int32_t  sub_sector_size = 0;
int32_t  bank_size;
int32_t  j = 0;
int32_t  error_flag = 0;
hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
 8053     /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
 8054     /* 00: The Hw sector is 256 bytes, hence we need to erase 16
 8055      *     consecutive sectors.  The start index for the nth Hw sector can be
 8056      *     calculated as bank * 4096 + n * 256
 8057      * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
 8058      *     The start index for the nth Hw sector can be calculated
 8059      *     as bank * 4096
 8060      * 10: The HW sector is 8K bytes
 8061      * 11: The Hw sector size is 64K bytes */
 8062     if (hsfsts.hsf_status.berasesz == 0x0) {
 8063         /* Hw sector size 256 */
sub_sector_size = ICH_FLASH_SEG_SIZE_256;
bank_size = ICH_FLASH_SECTOR_SIZE;
iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256;
 8067     } else if (hsfsts.hsf_status.berasesz == 0x1) {
bank_size = ICH_FLASH_SEG_SIZE_4K;
iteration = 1;
 8070     } else if (hsfsts.hsf_status.berasesz == 0x3) {
bank_size = ICH_FLASH_SEG_SIZE_64K;
iteration = 1;
 8073     } else {
 8074         return error;
 8075     }
 8077     for (j = 0; j < iteration ; j++) {
 8078         do {
count++;
 8080             /* Steps */
error = em_ich8_cycle_init(hw);
 8082             if (error != E1000_SUCCESS) {
error_flag = 1;
 8084                 break;
 8085             }
 8087             /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash
 8088              * Control */
hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
 8093             /* Write the last 24 bits of an index within the block into Flash
 8094              * Linear address field in Flash Address.  This probably needs to
 8095              * be calculated here based off the on-chip erase sector size and
 8096              * the software bank size (4, 8 or 64 KBytes) */
flash_linear_address = bank * bank_size + j * sub_sector_size;
flash_linear_address += hw->flash_base_addr;
flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK;
E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
error = em_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT);
 8104             /* Check if FCERR is set to 1.  If 1, clear it and try the whole
 8105              * sequence a few more times else Done */
 8106             if (error == E1000_SUCCESS) {
 8107                 break;
 8108             } else {
hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
 8110                 if (hsfsts.hsf_status.flcerr == 1) {
 8111                     /* repeat for some time before giving up */
 8112                     continue;
 8113                 } else if (hsfsts.hsf_status.flcdone == 0) {
error_flag = 1;
 8115                     break;
 8116                 }
 8117             }
 8118         } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
 8119         if (error_flag == 1)
 8120             break;
 8121     }
 8122     if (error_flag != 1)
error = E1000_SUCCESS;
 8124     return error;
 8125 }
STATIC int32_t
em_init_lcd_from_nvm_config_region(struct em_hw *hw,
uint32_t cnf_base_addr, uint32_t cnf_size)
 8131 {
uint32_t ret_val = E1000_SUCCESS;
uint16_t word_addr, reg_data, reg_addr;
uint16_t i;
 8136     /* cnf_base_addr is in DWORD */
word_addr = (uint16_t)(cnf_base_addr << 1);
 8139     /* cnf_size is returned in size of dwords */
 8140     for (i = 0; i < cnf_size; i++) {
ret_val = em_read_eeprom(hw, (word_addr + i*2), 1, &reg_data);
 8142         if (ret_val)
 8143             return ret_val;
ret_val = em_read_eeprom(hw, (word_addr + i*2 + 1), 1, &reg_addr);
 8146         if (ret_val)
 8147             return ret_val;
ret_val = em_get_software_flag(hw);
 8150         if (ret_val != E1000_SUCCESS)
 8151             return ret_val;
ret_val = em_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data);
em_release_software_flag(hw);
 8156     }
 8158     return ret_val;
 8159 }
 8161 /******************************************************************************
 8162  * This function initializes the PHY from the NVM on ICH8 platforms. This
 8163  * is needed due to an issue where the NVM configuration is not properly
 8164  * autoloaded after power transitions. Therefore, after each PHY reset, we
 8165  * will load the configuration data out of the NVM manually.
 8166  *
 8167  * hw: Struct containing variables accessed by shared code
 8168  *****************************************************************************/
STATIC int32_t
em_init_lcd_from_nvm(struct em_hw *hw)
 8171 {
uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop;
 8174     if (hw->phy_type != em_phy_igp_3)
 8175           return E1000_SUCCESS;
 8177     /* Check if SW needs configure the PHY */
reg_data = E1000_READ_REG(hw, FEXTNVM);
 8179     if (!(reg_data & FEXTNVM_SW_CONFIG))
 8180         return E1000_SUCCESS;
 8182     /* Wait for basic configuration completes before proceeding*/
loop = 0;
 8184     do {
reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE;
usec_delay(100);
loop++;
 8188     } while ((!reg_data) && (loop < 50));
 8190     /* Clear the Init Done bit for the next init event */
reg_data = E1000_READ_REG(hw, STATUS);
reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
E1000_WRITE_REG(hw, STATUS, reg_data);
 8195     /* Make sure HW does not configure LCD from PHY extended configuration
 8196        before SW configuration */
reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
 8198     if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
reg_data = E1000_READ_REG(hw, EXTCNF_SIZE);
cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
cnf_size >>= 16;
 8202         if (cnf_size) {
reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
 8205             /* cnf_base_addr is in DWORD */
cnf_base_addr >>= 16;
 8208             /* Configure LCD from extended configuration region. */
ret_val = em_init_lcd_from_nvm_config_region(hw, cnf_base_addr,
cnf_size);
 8211             if (ret_val)
 8212                 return ret_val;
 8213         }
 8214     }
 8216     return E1000_SUCCESS;
 8217 }