ctrl 179 arch/i386/i386/dkcsum.c int type, ctrl, adap, part, unit;
ctrl 183 arch/i386/i386/dkcsum.c ctrl = B_CONTROLLER(bootdev);
ctrl 187 arch/i386/i386/dkcsum.c pribootdev = MAKEBOOTDEV(type, ctrl, adap, unit, part);
ctrl 195 arch/i386/i386/dkcsum.c int type, ctrl, adap, part, unit;
ctrl 199 arch/i386/i386/dkcsum.c ctrl = B_CONTROLLER(bootdev);
ctrl 203 arch/i386/i386/dkcsum.c altbootdev = MAKEBOOTDEV(type, ctrl, adap, unit, part);
ctrl 89 arch/i386/i386/powernow-k7.c #define WRITE_FIDVID(fid, vid, ctrl) \
ctrl 91 arch/i386/i386/powernow-k7.c (((ctrl) << 32) | (1ULL << 16) | ((vid) << 8) | (fid)))
ctrl 304 arch/i386/i386/powernow-k7.c uint32_t ctrl;
ctrl 310 arch/i386/i386/powernow-k7.c ctrl = pss[n].pss_ctrl;
ctrl 311 arch/i386/i386/powernow-k7.c state.fid = PN7_ACPI_CTRL_TO_FID(ctrl);
ctrl 312 arch/i386/i386/powernow-k7.c state.vid = PN7_ACPI_CTRL_TO_VID(ctrl);
ctrl 333 arch/i386/i386/powernow-k7.c uint32_t ctrl;
ctrl 340 arch/i386/i386/powernow-k7.c ctrl = pss[curs].pss_ctrl;
ctrl 341 arch/i386/i386/powernow-k7.c cstate->sgtc = PN7_ACPI_CTRL_TO_SGTC(ctrl);
ctrl 349 arch/i386/i386/powernow-k7.c uint32_t ctrl;
ctrl 369 arch/i386/i386/powernow-k7.c ctrl = pss[curs].pss_ctrl;
ctrl 370 arch/i386/i386/powernow-k7.c cstate->sgtc = PN7_ACPI_CTRL_TO_SGTC(ctrl);
ctrl 92 arch/i386/i386/powernow-k8.c #define WRITE_FIDVID(fid, vid, ctrl) \
ctrl 94 arch/i386/i386/powernow-k8.c (((ctrl) << 32) | (1ULL << 16) | ((vid) << 8) | (fid)))
ctrl 355 arch/i386/i386/powernow-k8.c uint32_t ctrl;
ctrl 362 arch/i386/i386/powernow-k8.c ctrl = pss[n].pss_ctrl;
ctrl 363 arch/i386/i386/powernow-k8.c state.fid = PN8_ACPI_CTRL_TO_FID(ctrl);
ctrl 364 arch/i386/i386/powernow-k8.c state.vid = PN8_ACPI_CTRL_TO_VID(ctrl);
ctrl 386 arch/i386/i386/powernow-k8.c uint32_t ctrl;
ctrl 393 arch/i386/i386/powernow-k8.c ctrl = pss[curs].pss_ctrl;
ctrl 394 arch/i386/i386/powernow-k8.c cstate->vst = PN8_ACPI_CTRL_TO_VST(ctrl);
ctrl 395 arch/i386/i386/powernow-k8.c cstate->mvs = PN8_ACPI_CTRL_TO_MVS(ctrl);
ctrl 396 arch/i386/i386/powernow-k8.c cstate->pll = PN8_ACPI_CTRL_TO_PLL(ctrl);
ctrl 397 arch/i386/i386/powernow-k8.c cstate->irt = PN8_ACPI_CTRL_TO_IRT(ctrl);
ctrl 406 arch/i386/i386/powernow-k8.c uint32_t ctrl;
ctrl 415 arch/i386/i386/powernow-k8.c ctrl = pss[curs].pss_ctrl;
ctrl 417 arch/i386/i386/powernow-k8.c cstate->vst = PN8_ACPI_CTRL_TO_VST(ctrl);
ctrl 418 arch/i386/i386/powernow-k8.c cstate->mvs = PN8_ACPI_CTRL_TO_MVS(ctrl);
ctrl 419 arch/i386/i386/powernow-k8.c cstate->pll = PN8_ACPI_CTRL_TO_PLL(ctrl);
ctrl 420 arch/i386/i386/powernow-k8.c cstate->irt = PN8_ACPI_CTRL_TO_IRT(ctrl);
ctrl 1149 dev/ic/acx.c uint8_t ctrl, error;
ctrl 1151 dev/ic/acx.c ctrl = FW_TXDESC_GETFIELD_1(sc, buf, f_tx_ctrl);
ctrl 1152 dev/ic/acx.c if ((ctrl & (DESC_CTRL_HOSTOWN | DESC_CTRL_ACXDONE)) !=
ctrl 2182 dev/ic/acx.c uint8_t ctrl;
ctrl 2295 dev/ic/acx.c ctrl = FW_TXDESC_GETFIELD_1(sc, txbuf, f_tx_ctrl);
ctrl 2296 dev/ic/acx.c ctrl |= sc->chip_fw_txdesc_ctrl; /* extra chip specific flags */
ctrl 2297 dev/ic/acx.c ctrl &= ~(DESC_CTRL_HOSTOWN | DESC_CTRL_ACXDONE);
ctrl 2312 dev/ic/acx.c FW_TXDESC_SETFIELD_1(sc, txbuf, f_tx_ctrl, ctrl);
ctrl 2188 dev/isa/gus.c u_char ctrl;
ctrl 2190 dev/isa/gus.c ctrl = (port & 0xf0) >> 4; /* set port address middle nibble */
ctrl 2194 dev/isa/gus.c ctrl |= GUS_MAX_CODEC_ENABLE;
ctrl 2196 dev/isa/gus.c ctrl |= GUS_MAX_RECCHAN16;
ctrl 2198 dev/isa/gus.c ctrl |= GUS_MAX_PLAYCHAN16;
ctrl 2200 dev/isa/gus.c bus_space_write_1(iot, ioh1, GUS_MAX_CTRL, ctrl);
ctrl 1265 dev/pci/autri.c u_int32_t delta, dch[2], ctrl;
ctrl 1272 dev/pci/autri.c ctrl = AUTRI_CTRL_LOOPMODE;
ctrl 1276 dev/pci/autri.c ctrl |= AUTRI_CTRL_SIGNED;
ctrl 1282 dev/pci/autri.c ctrl |= AUTRI_CTRL_16BIT;
ctrl 1287 dev/pci/autri.c ctrl |= AUTRI_CTRL_STEREO;
ctrl 1303 dev/pci/autri.c ctrl |= AUTRI_CTRL_WAVEVOL;
ctrl 1312 dev/pci/autri.c ctrl |= AUTRI_CTRL_MUTE_SIS;
ctrl 1317 dev/pci/autri.c ctrl |= AUTRI_CTRL_MUTE;
ctrl 1333 dev/pci/autri.c ctrl |= AUTRI_CTRL_MUTE_SIS;
ctrl 1335 dev/pci/autri.c ctrl |= AUTRI_CTRL_MUTE;
ctrl 1347 dev/pci/autri.c cr[4] = ctrl;
ctrl 1354 dev/pci/autri.c cr[4] = ctrl;
ctrl 1361 dev/pci/autri.c cr[4] = ctrl;
ctrl 1368 dev/pci/autri.c cr[4] = ctrl;
ctrl 83 dev/pci/if_bce.c u_int32_t ctrl;
ctrl 158 dev/pci/if_bce.c __bced->ctrl = htole32(BCE_RXBUF_LEN); \
ctrl 160 dev/pci/if_bce.c __bced->ctrl = htole32(BCE_RXBUF_LEN | CTRL_EOT); \
ctrl 599 dev/pci/if_bce.c u_int32_t ctrl;
ctrl 601 dev/pci/if_bce.c ctrl = dmamap->dm_segs[seg].ds_len & CTRL_BC_MASK;
ctrl 603 dev/pci/if_bce.c ctrl |= CTRL_SOF;
ctrl 605 dev/pci/if_bce.c ctrl |= CTRL_EOF;
ctrl 607 dev/pci/if_bce.c ctrl |= CTRL_EOT;
ctrl 608 dev/pci/if_bce.c ctrl |= CTRL_IOC;
ctrl 609 dev/pci/if_bce.c sc->bce_tx_ring[sc->bce_txsnext].ctrl = htole32(ctrl);
ctrl 131 dev/pci/if_em_hw.c static void em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl);
ctrl 132 dev/pci/if_em_hw.c static void em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl);
ctrl 547 dev/pci/if_em_hw.c uint32_t ctrl;
ctrl 593 dev/pci/if_em_hw.c ctrl = E1000_READ_REG(hw, CTRL);
ctrl 597 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
ctrl 647 dev/pci/if_em_hw.c E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
ctrl 652 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
ctrl 661 dev/pci/if_em_hw.c ctrl |= E1000_CTRL_PHY_RST;
ctrl 665 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
ctrl 669 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
ctrl 872 dev/pci/if_em_hw.c uint32_t ctrl;
ctrl 958 dev/pci/if_em_hw.c ctrl = E1000_READ_REG(hw, CTRL);
ctrl 959 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
ctrl 997 dev/pci/if_em_hw.c ctrl = E1000_READ_REG(hw, TXDCTL);
ctrl 998 dev/pci/if_em_hw.c ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
ctrl 999 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, TXDCTL, ctrl);
ctrl 1034 dev/pci/if_em_hw.c ctrl = E1000_READ_REG(hw, TXDCTL1);
ctrl 1035 dev/pci/if_em_hw.c ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
ctrl 1036 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, TXDCTL1, ctrl);
ctrl 1257 dev/pci/if_em_hw.c uint32_t ctrl;
ctrl 1280 dev/pci/if_em_hw.c ctrl = E1000_READ_REG(hw, CTRL);
ctrl 1289 dev/pci/if_em_hw.c ctrl &= ~(E1000_CTRL_LRST);
ctrl 1352 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, ctrl);
ctrl 1404 dev/pci/if_em_hw.c uint32_t ctrl;
ctrl 1410 dev/pci/if_em_hw.c ctrl = E1000_READ_REG(hw, CTRL);
ctrl 1416 dev/pci/if_em_hw.c ctrl |= E1000_CTRL_SLU;
ctrl 1417 dev/pci/if_em_hw.c ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
ctrl 1418 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, ctrl);
ctrl 1420 dev/pci/if_em_hw.c ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
ctrl 1421 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, ctrl);
ctrl 2309 dev/pci/if_em_hw.c uint32_t ctrl;
ctrl 2324 dev/pci/if_em_hw.c ctrl = E1000_READ_REG(hw, CTRL);
ctrl 2327 dev/pci/if_em_hw.c ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
ctrl 2328 dev/pci/if_em_hw.c ctrl &= ~(DEVICE_SPEED_MASK);
ctrl 2331 dev/pci/if_em_hw.c ctrl &= ~E1000_CTRL_ASDE;
ctrl 2348 dev/pci/if_em_hw.c ctrl |= E1000_CTRL_FD;
ctrl 2355 dev/pci/if_em_hw.c ctrl &= ~E1000_CTRL_FD;
ctrl 2364 dev/pci/if_em_hw.c ctrl |= E1000_CTRL_SPD_100;
ctrl 2370 dev/pci/if_em_hw.c ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
ctrl 2379 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, ctrl);
ctrl 2588 dev/pci/if_em_hw.c uint32_t ctrl;
ctrl 2602 dev/pci/if_em_hw.c ctrl = E1000_READ_REG(hw, CTRL);
ctrl 2603 dev/pci/if_em_hw.c ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
ctrl 2604 dev/pci/if_em_hw.c ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
ctrl 2614 dev/pci/if_em_hw.c ctrl |= E1000_CTRL_FD;
ctrl 2616 dev/pci/if_em_hw.c ctrl &= ~E1000_CTRL_FD;
ctrl 2624 dev/pci/if_em_hw.c ctrl |= E1000_CTRL_SPD_1000;
ctrl 2626 dev/pci/if_em_hw.c ctrl |= E1000_CTRL_SPD_100;
ctrl 2629 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, ctrl);
ctrl 2647 dev/pci/if_em_hw.c uint32_t ctrl;
ctrl 2652 dev/pci/if_em_hw.c ctrl = E1000_READ_REG(hw, CTRL);
ctrl 2674 dev/pci/if_em_hw.c ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
ctrl 2677 dev/pci/if_em_hw.c ctrl &= (~E1000_CTRL_TFCE);
ctrl 2678 dev/pci/if_em_hw.c ctrl |= E1000_CTRL_RFCE;
ctrl 2681 dev/pci/if_em_hw.c ctrl &= (~E1000_CTRL_RFCE);
ctrl 2682 dev/pci/if_em_hw.c ctrl |= E1000_CTRL_TFCE;
ctrl 2685 dev/pci/if_em_hw.c ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
ctrl 2694 dev/pci/if_em_hw.c ctrl &= (~E1000_CTRL_TFCE);
ctrl 2696 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, ctrl);
ctrl 2920 dev/pci/if_em_hw.c uint32_t ctrl;
ctrl 2930 dev/pci/if_em_hw.c ctrl = E1000_READ_REG(hw, CTRL);
ctrl 3082 dev/pci/if_em_hw.c ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
ctrl 3096 dev/pci/if_em_hw.c ctrl = E1000_READ_REG(hw, CTRL);
ctrl 3097 dev/pci/if_em_hw.c ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
ctrl 3098 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, ctrl);
ctrl 3114 dev/pci/if_em_hw.c (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
ctrl 3117 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
ctrl 3271 dev/pci/if_em_hw.c uint32_t *ctrl)
ctrl 3276 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
ctrl 3289 dev/pci/if_em_hw.c uint32_t *ctrl)
ctrl 3294 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
ctrl 3313 dev/pci/if_em_hw.c uint32_t ctrl;
ctrl 3323 dev/pci/if_em_hw.c ctrl = E1000_READ_REG(hw, CTRL);
ctrl 3326 dev/pci/if_em_hw.c ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
ctrl 3335 dev/pci/if_em_hw.c ctrl |= E1000_CTRL_MDIO;
ctrl 3337 dev/pci/if_em_hw.c ctrl &= ~E1000_CTRL_MDIO;
ctrl 3339 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, ctrl);
ctrl 3344 dev/pci/if_em_hw.c em_raise_mdi_clk(hw, &ctrl);
ctrl 3345 dev/pci/if_em_hw.c em_lower_mdi_clk(hw, &ctrl);
ctrl 3361 dev/pci/if_em_hw.c uint32_t ctrl;
ctrl 3372 dev/pci/if_em_hw.c ctrl = E1000_READ_REG(hw, CTRL);
ctrl 3375 dev/pci/if_em_hw.c ctrl &= ~E1000_CTRL_MDIO_DIR;
ctrl 3376 dev/pci/if_em_hw.c ctrl &= ~E1000_CTRL_MDIO;
ctrl 3378 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, ctrl);
ctrl 3385 dev/pci/if_em_hw.c em_raise_mdi_clk(hw, &ctrl);
ctrl 3386 dev/pci/if_em_hw.c em_lower_mdi_clk(hw, &ctrl);
ctrl 3390 dev/pci/if_em_hw.c em_raise_mdi_clk(hw, &ctrl);
ctrl 3391 dev/pci/if_em_hw.c ctrl = E1000_READ_REG(hw, CTRL);
ctrl 3393 dev/pci/if_em_hw.c if (ctrl & E1000_CTRL_MDIO)
ctrl 3395 dev/pci/if_em_hw.c em_lower_mdi_clk(hw, &ctrl);
ctrl 3398 dev/pci/if_em_hw.c em_raise_mdi_clk(hw, &ctrl);
ctrl 3399 dev/pci/if_em_hw.c em_lower_mdi_clk(hw, &ctrl);
ctrl 3811 dev/pci/if_em_hw.c uint32_t ctrl, ctrl_ext;
ctrl 3843 dev/pci/if_em_hw.c ctrl = E1000_READ_REG(hw, CTRL);
ctrl 3844 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
ctrl 3852 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, ctrl);
ctrl 7154 dev/pci/if_em_hw.c uint32_t ctrl;
ctrl 7161 dev/pci/if_em_hw.c ctrl = E1000_READ_REG(hw, CTRL);
ctrl 7162 dev/pci/if_em_hw.c ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
ctrl 7163 dev/pci/if_em_hw.c E1000_WRITE_REG(hw, CTRL, ctrl);
ctrl 3242 dev/pci/pciide.c u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL);
ctrl 3297 dev/pci/pciide.c if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) {
ctrl 3313 dev/pci/pciide.c ctrl &= ~CMD_CTRL_2PORT;
ctrl 3315 dev/pci/pciide.c CMD_CTRL, ctrl);
ctrl 1562 dev/pci/ubsec.c volatile u_int32_t ctrl;
ctrl 1564 dev/pci/ubsec.c ctrl = READ_REG(sc, BS_CTRL);
ctrl 1565 dev/pci/ubsec.c ctrl |= BS_CTRL_RESET;
ctrl 1566 dev/pci/ubsec.c WRITE_REG(sc, BS_CTRL, ctrl);
ctrl 1580 dev/pci/ubsec.c u_int32_t ctrl;
ctrl 1582 dev/pci/ubsec.c ctrl = READ_REG(sc, BS_CTRL);
ctrl 1583 dev/pci/ubsec.c ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64);
ctrl 1584 dev/pci/ubsec.c ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT;
ctrl 1587 dev/pci/ubsec.c ctrl |= BS_CTRL_MCR2INT;
ctrl 1589 dev/pci/ubsec.c ctrl &= ~BS_CTRL_MCR2INT;
ctrl 1592 dev/pci/ubsec.c ctrl &= ~BS_CTRL_SWNORM;
ctrl 1594 dev/pci/ubsec.c WRITE_REG(sc, BS_CTRL, ctrl);
ctrl 352 dev/pci/yds.c u_int ctrl;
ctrl 399 dev/pci/yds.c ctrl = YREAD2(sc, YDS_GLOBAL_CONTROL);
ctrl 400 dev/pci/yds.c YWRITE2(sc, YDS_GLOBAL_CONTROL, ctrl & ~0x0007);
ctrl 303 dev/pci/ydsreg.h } ctrl[N_REC_SLOT_CTRL];
ctrl 1095 dev/raidframe/rf_reconstruct.c RF_PerDiskReconCtrl_t *ctrl =
ctrl 1098 dev/raidframe/rf_reconstruct.c RF_ReconBuffer_t *rbuf = ctrl->rbuf;
ctrl 1109 dev/raidframe/rf_reconstruct.c if (ctrl->headSepCounter <=
ctrl 1115 dev/raidframe/rf_reconstruct.c ctrl->ru_count++;
ctrl 1116 dev/raidframe/rf_reconstruct.c if (ctrl->ru_count < RUsPerPU) {
ctrl 1117 dev/raidframe/rf_reconstruct.c ctrl->diskOffset += sectorsPerRU;
ctrl 1120 dev/raidframe/rf_reconstruct.c ctrl->curPSID++;
ctrl 1121 dev/raidframe/rf_reconstruct.c ctrl->ru_count = 0;
ctrl 1124 dev/raidframe/rf_reconstruct.c if (ctrl->curPSID >=
ctrl 1127 dev/raidframe/rf_reconstruct.c ++(ctrl->headSepCounter));
ctrl 1137 dev/raidframe/rf_reconstruct.c ctrl->curPSID, row, col, &ctrl->diskOffset,
ctrl 1141 dev/raidframe/rf_reconstruct.c ctrl->ru_count = RUsPerPU - 1;
ctrl 1145 dev/raidframe/rf_reconstruct.c rbuf->which_ru = ctrl->ru_count;
ctrl 1151 dev/raidframe/rf_reconstruct.c " reconstructed.\n", ctrl->curPSID, ctrl->ru_count);
ctrl 1156 dev/raidframe/rf_reconstruct.c ctrl->headSepCounter++;
ctrl 1158 dev/raidframe/rf_reconstruct.c rf_CheckForNewMinHeadSep(raidPtr, row, ctrl->headSepCounter);
ctrl 1165 dev/raidframe/rf_reconstruct.c rbuf->parityStripeID = ctrl->curPSID;
ctrl 1166 dev/raidframe/rf_reconstruct.c rbuf->which_ru = ctrl->ru_count;
ctrl 1187 dev/raidframe/rf_reconstruct.c RF_PerDiskReconCtrl_t *ctrl =
ctrl 1191 dev/raidframe/rf_reconstruct.c RF_StripeNum_t psid = ctrl->curPSID;
ctrl 1192 dev/raidframe/rf_reconstruct.c RF_ReconUnitNum_t which_ru = ctrl->ru_count;
ctrl 1201 dev/raidframe/rf_reconstruct.c if (rf_CheckHeadSeparation(raidPtr, ctrl, row, col,
ctrl 1202 dev/raidframe/rf_reconstruct.c ctrl->headSepCounter, which_ru))
ctrl 1213 dev/raidframe/rf_reconstruct.c status = rf_CheckForcedOrBlockedReconstruction(raidPtr, pssPtr, ctrl,
ctrl 1235 dev/raidframe/rf_reconstruct.c ctrl->rbuf->failedDiskSectorOffset)) {
ctrl 1246 dev/raidframe/rf_reconstruct.c " buf %lx.\n", psid, row, col, ctrl->diskOffset,
ctrl 1247 dev/raidframe/rf_reconstruct.c ctrl->rbuf->buffer);
ctrl 1258 dev/raidframe/rf_reconstruct.c req = rf_CreateDiskQueueData(RF_IO_TYPE_READ, ctrl->diskOffset,
ctrl 1259 dev/raidframe/rf_reconstruct.c sectorsPerRU, ctrl->rbuf->buffer, psid, which_ru,
ctrl 1260 dev/raidframe/rf_reconstruct.c rf_ReconReadDoneProc, (void *) ctrl, NULL,
ctrl 1265 dev/raidframe/rf_reconstruct.c ctrl->rbuf->arg = (void *) req;
ctrl 1510 dev/raidframe/rf_reconstruct.c RF_PerDiskReconCtrl_t *ctrl = (RF_PerDiskReconCtrl_t *) arg;
ctrl 1511 dev/raidframe/rf_reconstruct.c RF_Raid_t *raidPtr = ctrl->reconCtrl->reconDesc->raidPtr;
ctrl 1520 dev/raidframe/rf_reconstruct.c RF_ETIMER_STOP(raidPtr->recon_tracerecs[ctrl->col].recon_timer);
ctrl 1521 dev/raidframe/rf_reconstruct.c RF_ETIMER_EVAL(raidPtr->recon_tracerecs[ctrl->col].recon_timer);
ctrl 1522 dev/raidframe/rf_reconstruct.c raidPtr->recon_tracerecs[ctrl->col].specific.recon.
ctrl 1524 dev/raidframe/rf_reconstruct.c RF_ETIMER_VAL_US(raidPtr->recon_tracerecs[ctrl->col].recon_timer);
ctrl 1525 dev/raidframe/rf_reconstruct.c RF_ETIMER_START(raidPtr->recon_tracerecs[ctrl->col].recon_timer);
ctrl 1527 dev/raidframe/rf_reconstruct.c rf_CauseReconEvent(raidPtr, ctrl->row, ctrl->col, NULL,
ctrl 1619 dev/raidframe/rf_reconstruct.c RF_PerDiskReconCtrl_t *ctrl,
ctrl 1640 dev/raidframe/rf_reconstruct.c ((ctrl->headSepCounter - reconCtrlPtr->minHeadSepCounter) >
ctrl 1644 dev/raidframe/rf_reconstruct.c raidPtr->raidid, row, col, ctrl->headSepCounter,
ctrl 1651 dev/raidframe/rf_reconstruct.c cb->callbackArg.v = (ctrl->headSepCounter -
ctrl 1677 dev/raidframe/rf_reconstruct.c ctrl->reconCtrl->reconDesc->hsStallCount++;
ctrl 1698 dev/raidframe/rf_reconstruct.c RF_PerDiskReconCtrl_t *ctrl,
ctrl 212 dev/sbus/bereg.h u_int32_t ctrl; /* control */
ctrl 175 dev/sbus/cgthree.c u_int8_t ctrl;
ctrl 498 dev/sbus/cgthree.c u_int8_t sts, ctrl;
ctrl 501 dev/sbus/cgthree.c ctrl = FBC_READ(sc, CG3_FBC_CTRL);
ctrl 503 dev/sbus/cgthree.c if (ctrl & FBC_CTRL_TIME) {
ctrl 515 dev/sbus/cgthree.c ctrl &= ~(FBC_CTRL_XTAL | FBC_CTRL_DIV);
ctrl 516 dev/sbus/cgthree.c ctrl |= cg3_videoctrl[i].ctrl |
ctrl 518 dev/sbus/cgthree.c FBC_WRITE(sc, CG3_FBC_CTRL, ctrl);
ctrl 70 dev/sbus/qereg.h u_int32_t ctrl; /* control */
ctrl 833 net/bsd-comp.c int adrs, ctrl, ilen;
ctrl 843 net/bsd-comp.c ctrl = PPP_CONTROL(rptr);
ctrl 890 net/bsd-comp.c wptr[1] = ctrl;
ctrl 1288 net/if_ppp.c u_char *cp, adrs, ctrl;
ctrl 1305 net/if_ppp.c ctrl = PPP_CONTROL(cp);
ctrl 1413 net/if_ppp.c cp[1] = ctrl;