root/dev/pci/pciide.c

DEFINITIONS

1. pciide_pci_read
2. pciide_pci_write
3. pciide_lookup_product
4. pciide_match
5. pciide_attach
6. pciide_mapregs_compat
7. pciide_mapregs_native
8. pciide_mapreg_dma
9. pciide_intr_flag
10. pciide_compat_intr
11. pciide_pci_intr
12. pciide_dmacmd_read
13. pciide_dmacmd_write
14. pciide_dmactl_read
15. pciide_dmactl_write
16. pciide_dmatbl_write
17. pciide_channel_dma_setup
18. pciide_dma_table_setup
19. pciide_dma_init
20. pciide_dma_start
21. pciide_dma_finish
22. pciide_irqack
23. pciide_chansetup
24. pciide_mapchan
25. pciide_chan_candisable
26. pciide_map_compat_intr
27. pciide_unmap_compat_intr
28. pciide_print_channels
29. pciide_print_modes
30. default_chip_map
31. sata_chip_map
32. sata_setup_channel
33. piix_timing_debug
34. piix_chip_map
35. piixsata_chip_map
36. piix_setup_channel
37. piix3_4_setup_channel
38. piix_setup_idetim_timings
39. piix_setup_idetim_drvs
40. piix_setup_sidetim_timings
41. amd756_chip_map
42. amd756_setup_channel
43. apollo_chip_map
44. apollo_setup_channel
45. cmd_channel_map
46. cmd_pci_intr
47. cmd_chip_map
48. cmd0643_9_chip_map
49. cmd0643_9_setup_channel
50. cmd646_9_irqack
51. cmd680_chip_map
52. cmd680_channel_map
53. cmd680_setup_channel
54. sii_fixup_cacheline
55. sii3112_chip_map
56. sii3112_setup_channel
57. sii3112_drv_probe
58. sii3114_chip_map
59. sii3114_mapreg_dma
60. sii3114_chansetup
61. sii3114_mapchan
62. sii3114_read_reg
63. sii3114_write_reg
64. sii3114_dmacmd_read
65. sii3114_dmacmd_write
66. sii3114_dmactl_read
67. sii3114_dmactl_write
68. sii3114_dmatbl_write
69. cy693_chip_map
70. cy693_setup_channel
71. sis_hostbr_match
72. sis_south_match
73. sis_chip_map
74. sis96x_setup_channel
75. sis_setup_channel
76. natsemi_chip_map
77. natsemi_setup_channel
78. natsemi_irqack
79. natsemi_pci_intr
80. ns_scx200_chip_map
81. ns_scx200_setup_channel
82. acer_chip_map
83. acer_setup_channel
84. acer_pci_intr
85. hpt_chip_map
86. hpt_setup_channel
87. hpt_pci_intr
88. pdc268_config_read
89. pdc268_config_write
90. pdc202xx_chip_map
91. pdc202xx_setup_channel
92. pdc20268_setup_channel
93. pdc202xx_pci_intr
94. pdc20265_pci_intr
95. pdc20262_dma_start
96. pdc20262_dma_finish
97. pdcsata_chip_map
98. pdc203xx_setup_channel
99. pdc203xx_pci_intr
100. pdc205xx_pci_intr
101. pdc203xx_irqack
102. pdc203xx_dma_start
103. pdc203xx_dma_finish
104. pdc203xx_read_reg
105. pdc203xx_write_reg
106. pdc205xx_do_reset
107. pdc205xx_drv_probe
108. opti_read_config
109. opti_write_config
110. opti_chip_map
111. opti_setup_channel
112. serverworks_chip_map
113. serverworks_setup_channel
114. serverworks_pci_intr
115. svwsata_chip_map
116. svwsata_mapreg_dma
117. svwsata_dmacmd_read
118. svwsata_dmacmd_write
119. svwsata_dmactl_read
120. svwsata_dmactl_write
121. svwsata_dmatbl_write
122. svwsata_mapchan
123. svwsata_drv_probe
124. svwsata_read_reg
125. svwsata_write_reg
126. svwsata_lba48_write_reg
127. acard_chip_map
128. acard_setup_channel
129. nforce_chip_map
130. nforce_setup_channel
131. nforce_pci_intr
132. artisea_chip_map
133. ite_chip_map
134. ite_setup_channel
135. ixp_chip_map
136. ixp_setup_channel
137. jmicron_chip_map
138. jmicron_setup_channel

    1 /*      $OpenBSD: pciide.c,v 1.272 2007/07/02 14:01:14 dlg Exp $        */
    2 /*      $NetBSD: pciide.c,v 1.127 2001/08/03 01:31:08 tsutsui Exp $     */
    4 /*
    5  * Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. All advertising materials mentioning features or use of this software
   16  *    must display the following acknowledgement:
   17  *      This product includes software developed by Manuel Bouyer.
   18  * 4. Neither the name of the University nor the names of its contributors
   19  *    may be used to endorse or promote products derived from this software
   20  *    without specific prior written permission.
   21  *
   22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   24  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   25  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   28  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   29  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   32  *
   33  */
   35 /*
   36  * Copyright (c) 1996, 1998 Christopher G. Demetriou.  All rights reserved.
   37  *
   38  * Redistribution and use in source and binary forms, with or without
   39  * modification, are permitted provided that the following conditions
   40  * are met:
   41  * 1. Redistributions of source code must retain the above copyright
   42  *    notice, this list of conditions and the following disclaimer.
   43  * 2. Redistributions in binary form must reproduce the above copyright
   44  *    notice, this list of conditions and the following disclaimer in the
   45  *    documentation and/or other materials provided with the distribution.
   46  * 3. All advertising materials mentioning features or use of this software
   47  *    must display the following acknowledgement:
   48  *      This product includes software developed by Christopher G. Demetriou
   49  *      for the NetBSD Project.
   50  * 4. The name of the author may not be used to endorse or promote products
   51  *    derived from this software without specific prior written permission
   52  *
   53  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   54  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   55  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   56  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   57  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   58  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   59  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   60  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   61  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   62  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   63  */
   65 /*
   66  * PCI IDE controller driver.
   67  *
   68  * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD
   69  * sys/dev/pci/ppb.c, revision 1.16).
   70  *
   71  * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and
   72  * "Programming Interface for Bus Master IDE Controller, Revision 1.0
   73  * 5/16/94" from the PCI SIG.
   74  *
   75  */
   77 #define DEBUG_DMA       0x01
   78 #define DEBUG_XFERS     0x02
   79 #define DEBUG_FUNCS     0x08
   80 #define DEBUG_PROBE     0x10
   82 #ifdef WDCDEBUG
   83 #ifndef WDCDEBUG_PCIIDE_MASK
   84 #define WDCDEBUG_PCIIDE_MASK 0x00
   85 #endif
   86 int wdcdebug_pciide_mask = WDCDEBUG_PCIIDE_MASK;
   87 #define WDCDEBUG_PRINT(args, level) do {                \
   88         if ((wdcdebug_pciide_mask & (level)) != 0)      \
printf args;                            \
   90 } while (0)
   91 #else
   92 #define WDCDEBUG_PRINT(args, level)
   93 #endif
   94 #include <sys/param.h>
   95 #include <sys/systm.h>
   96 #include <sys/device.h>
   97 #include <sys/malloc.h>
   99 #include <machine/bus.h>
  100 #include <machine/endian.h>
  102 #include <dev/ata/atavar.h>
  103 #include <dev/ata/satareg.h>
  104 #include <dev/ic/wdcreg.h>
  105 #include <dev/ic/wdcvar.h>
  107 #include <dev/pci/pcireg.h>
  108 #include <dev/pci/pcivar.h>
  109 #include <dev/pci/pcidevs.h>
  111 #if defined(SMALL_KERNEL)
  112 #define INLINE
  113 #else
  114 #define INLINE __inline
  115 #endif
  117 #include <dev/pci/pciidereg.h>
  118 #include <dev/pci/pciidevar.h>
  119 #include <dev/pci/pciide_piix_reg.h>
  120 #include <dev/pci/pciide_amd_reg.h>
  121 #include <dev/pci/pciide_apollo_reg.h>
  122 #include <dev/pci/pciide_cmd_reg.h>
  123 #include <dev/pci/pciide_sii3112_reg.h>
  124 #include <dev/pci/pciide_cy693_reg.h>
  125 #include <dev/pci/pciide_sis_reg.h>
  126 #include <dev/pci/pciide_acer_reg.h>
  127 #include <dev/pci/pciide_pdc202xx_reg.h>
  128 #include <dev/pci/pciide_opti_reg.h>
  129 #include <dev/pci/pciide_hpt_reg.h>
  130 #include <dev/pci/pciide_acard_reg.h>
  131 #include <dev/pci/pciide_natsemi_reg.h>
  132 #include <dev/pci/pciide_nforce_reg.h>
  133 #include <dev/pci/pciide_i31244_reg.h>
  134 #include <dev/pci/pciide_ite_reg.h>
  135 #include <dev/pci/pciide_ixp_reg.h>
  136 #include <dev/pci/pciide_svwsata_reg.h>
  137 #include <dev/pci/pciide_jmicron_reg.h>
  138 #include <dev/pci/cy82c693var.h>
  140 /* inlines for reading/writing 8-bit PCI registers */
  142 static INLINE u_int8_t pciide_pci_read(pci_chipset_tag_t, pcitag_t,
  143                                         int);
  144 static INLINE void pciide_pci_write(pci_chipset_tag_t, pcitag_t,
  145                                         int, u_int8_t);
  147 static INLINE u_int8_t
pciide_pci_read(pci_chipset_tag_t pc, pcitag_t pa, int reg)
  149 {
  150         return (pci_conf_read(pc, pa, (reg & ~0x03)) >>
  151             ((reg & 0x03) * 8) & 0xff);
  152 }
  154 static INLINE void
pciide_pci_write(pci_chipset_tag_t pc, pcitag_t pa, int reg, u_int8_t val)
  156 {
pcireg_t pcival;
pcival = pci_conf_read(pc, pa, (reg & ~0x03));
pcival &= ~(0xff << ((reg & 0x03) * 8));
pcival |= (val << ((reg & 0x03) * 8));
pci_conf_write(pc, pa, (reg & ~0x03), pcival);
  163 }
  165 void default_chip_map(struct pciide_softc *, struct pci_attach_args *);
  167 void sata_chip_map(struct pciide_softc *, struct pci_attach_args *);
  168 void sata_setup_channel(struct channel_softc *);
  170 void piix_chip_map(struct pciide_softc *, struct pci_attach_args *);
  171 void piixsata_chip_map(struct pciide_softc *, struct pci_attach_args *);
  172 void piix_setup_channel(struct channel_softc *);
  173 void piix3_4_setup_channel(struct channel_softc *);
  174 void piix_timing_debug(struct pciide_softc *);
  176 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t);
  177 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *);
  178 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t);
  180 void amd756_chip_map(struct pciide_softc *, struct pci_attach_args *);
  181 void amd756_setup_channel(struct channel_softc *);
  183 void apollo_chip_map(struct pciide_softc *, struct pci_attach_args *);
  184 void apollo_setup_channel(struct channel_softc *);
  186 void cmd_chip_map(struct pciide_softc *, struct pci_attach_args *);
  187 void cmd0643_9_chip_map(struct pciide_softc *, struct pci_attach_args *);
  188 void cmd0643_9_setup_channel(struct channel_softc *);
  189 void cmd680_chip_map(struct pciide_softc *, struct pci_attach_args *);
  190 void cmd680_setup_channel(struct channel_softc *);
  191 void cmd680_channel_map(struct pci_attach_args *, struct pciide_softc *, int);
  192 void cmd_channel_map(struct pci_attach_args *,
  193                         struct pciide_softc *, int);
  194 int  cmd_pci_intr(void *);
  195 void cmd646_9_irqack(struct channel_softc *);
  197 void sii_fixup_cacheline(struct pciide_softc *, struct pci_attach_args *);
  198 void sii3112_chip_map(struct pciide_softc *, struct pci_attach_args *);
  199 void sii3112_setup_channel(struct channel_softc *);
  200 void sii3112_drv_probe(struct channel_softc *);
  201 void sii3114_chip_map(struct pciide_softc *, struct pci_attach_args *);
  202 void sii3114_mapreg_dma(struct pciide_softc *, struct pci_attach_args *);
  203 int  sii3114_chansetup(struct pciide_softc *, int);
  204 void sii3114_mapchan(struct pciide_channel *);
u_int8_t sii3114_dmacmd_read(struct pciide_softc *, int);
  206 void sii3114_dmacmd_write(struct pciide_softc *, int, u_int8_t);
u_int8_t sii3114_dmactl_read(struct pciide_softc *, int);
  208 void sii3114_dmactl_write(struct pciide_softc *, int, u_int8_t);
  209 void sii3114_dmatbl_write(struct pciide_softc *, int, u_int32_t);
  211 void cy693_chip_map(struct pciide_softc *, struct pci_attach_args *);
  212 void cy693_setup_channel(struct channel_softc *);
  214 void sis_chip_map(struct pciide_softc *, struct pci_attach_args *);
  215 void sis_setup_channel(struct channel_softc *);
  216 void sis96x_setup_channel(struct channel_softc *);
  217 int  sis_hostbr_match(struct pci_attach_args *);
  218 int  sis_south_match(struct pci_attach_args *);
  220 void natsemi_chip_map(struct pciide_softc *, struct pci_attach_args *);
  221 void natsemi_setup_channel(struct channel_softc *);
  222 int  natsemi_pci_intr(void *);
  223 void natsemi_irqack(struct channel_softc *);
  224 void ns_scx200_chip_map(struct pciide_softc *, struct pci_attach_args *);
  225 void ns_scx200_setup_channel(struct channel_softc *);
  227 void acer_chip_map(struct pciide_softc *, struct pci_attach_args *);
  228 void acer_setup_channel(struct channel_softc *);
  229 int  acer_pci_intr(void *);
  231 void pdc202xx_chip_map(struct pciide_softc *, struct pci_attach_args *);
  232 void pdc202xx_setup_channel(struct channel_softc *);
  233 void pdc20268_setup_channel(struct channel_softc *);
  234 int  pdc202xx_pci_intr(void *);
  235 int  pdc20265_pci_intr(void *);
  236 void pdc20262_dma_start(void *, int, int);
  237 int  pdc20262_dma_finish(void *, int, int, int);
  239 void pdcsata_chip_map(struct pciide_softc *, struct pci_attach_args *);
  240 void pdc203xx_setup_channel(struct channel_softc *);
  241 int  pdc203xx_pci_intr(void *);
  242 void pdc203xx_irqack(struct channel_softc *);
  243 void pdc203xx_dma_start(void *,int ,int);
  244 int  pdc203xx_dma_finish(void *, int, int, int);
  245 int  pdc205xx_pci_intr(void *);
  246 void pdc205xx_do_reset(struct channel_softc *);
  247 void pdc205xx_drv_probe(struct channel_softc *);
  249 void opti_chip_map(struct pciide_softc *, struct pci_attach_args *);
  250 void opti_setup_channel(struct channel_softc *);
  252 void hpt_chip_map(struct pciide_softc *, struct pci_attach_args *);
  253 void hpt_setup_channel(struct channel_softc *);
  254 int  hpt_pci_intr(void *);
  256 void acard_chip_map(struct pciide_softc *, struct pci_attach_args *);
  257 void acard_setup_channel(struct channel_softc *);
  259 void serverworks_chip_map(struct pciide_softc *, struct pci_attach_args *);
  260 void serverworks_setup_channel(struct channel_softc *);
  261 int  serverworks_pci_intr(void *);
  263 void svwsata_chip_map(struct pciide_softc *, struct pci_attach_args *);
  264 void svwsata_mapreg_dma(struct pciide_softc *, struct pci_attach_args *);
  265 void svwsata_mapchan(struct pciide_channel *);
u_int8_t svwsata_dmacmd_read(struct pciide_softc *, int);
  267 void svwsata_dmacmd_write(struct pciide_softc *, int, u_int8_t);
u_int8_t svwsata_dmactl_read(struct pciide_softc *, int);
  269 void svwsata_dmactl_write(struct pciide_softc *, int, u_int8_t);
  270 void svwsata_dmatbl_write(struct pciide_softc *, int, u_int32_t);
  271 void svwsata_drv_probe(struct channel_softc *);
  273 void nforce_chip_map(struct pciide_softc *, struct pci_attach_args *);
  274 void nforce_setup_channel(struct channel_softc *);
  275 int  nforce_pci_intr(void *);
  277 void artisea_chip_map(struct pciide_softc *, struct pci_attach_args *);
  279 void ite_chip_map(struct pciide_softc *, struct pci_attach_args *);
  280 void ite_setup_channel(struct channel_softc *);
  282 void ixp_chip_map(struct pciide_softc *, struct pci_attach_args *);
  283 void ixp_setup_channel(struct channel_softc *);
  285 void jmicron_chip_map(struct pciide_softc *, struct pci_attach_args *);
  286 void jmicron_setup_channel(struct channel_softc *);
u_int8_t pciide_dmacmd_read(struct pciide_softc *, int);
  289 void pciide_dmacmd_write(struct pciide_softc *, int, u_int8_t);
u_int8_t pciide_dmactl_read(struct pciide_softc *, int);
  291 void pciide_dmactl_write(struct pciide_softc *, int, u_int8_t);
  292 void pciide_dmatbl_write(struct pciide_softc *, int, u_int32_t);
  294 void pciide_channel_dma_setup(struct pciide_channel *);
  295 int  pciide_dma_table_setup(struct pciide_softc *, int, int);
  296 int  pciide_dma_init(void *, int, int, void *, size_t, int);
  297 void pciide_dma_start(void *, int, int);
  298 int  pciide_dma_finish(void *, int, int, int);
  299 void pciide_irqack(struct channel_softc *);
  300 void pciide_print_modes(struct pciide_channel *);
  301 void pciide_print_channels(int, pcireg_t);
  303 struct pciide_product_desc {
u_int32_t ide_product;
u_short ide_flags;
  306         /* map and setup chip, probe drives */
  307         void (*chip_map)(struct pciide_softc *, struct pci_attach_args *);
  308 };
  310 /* Flags for ide_flags */
  311 #define IDE_PCI_CLASS_OVERRIDE  0x0001  /* accept even if class != pciide */
  312 #define IDE_16BIT_IOSPACE       0x0002  /* I/O space BARS ignore upper word */
  314 /* Default product description for devices not known from this controller */
  315 const struct pciide_product_desc default_product_desc = {
  316         0,                              /* Generic PCI IDE controller */
  317         0,
default_chip_map
  319 };
  321 const struct pciide_product_desc pciide_intel_products[] =  {
  322         { PCI_PRODUCT_INTEL_31244,      /* Intel 31244 SATA */
  323           0,
artisea_chip_map
  325         },
  326         { PCI_PRODUCT_INTEL_82092AA,    /* Intel 82092AA IDE */
  327           0,
default_chip_map
  329         },
  330         { PCI_PRODUCT_INTEL_82371FB_IDE, /* Intel 82371FB IDE (PIIX) */
  331           0,
piix_chip_map
  333         },
  334         { PCI_PRODUCT_INTEL_82371FB_ISA, /* Intel 82371FB IDE (PIIX) */
  335           0,
piix_chip_map
  337         },
  338         { PCI_PRODUCT_INTEL_82372FB_IDE, /* Intel 82372FB IDE (PIIX4) */
  339           0,
piix_chip_map
  341         },
  342         { PCI_PRODUCT_INTEL_82371SB_IDE, /* Intel 82371SB IDE (PIIX3) */
  343           0,
piix_chip_map
  345         },
  346         { PCI_PRODUCT_INTEL_82371AB_IDE, /* Intel 82371AB IDE (PIIX4) */
  347           0,
piix_chip_map
  349         },
  350         { PCI_PRODUCT_INTEL_82371MX, /* Intel 82371MX IDE */
  351           0,
piix_chip_map
  353         },
  354         { PCI_PRODUCT_INTEL_82440MX_IDE, /* Intel 82440MX IDE */
  355           0,
piix_chip_map
  357         },
  358         { PCI_PRODUCT_INTEL_82451NX, /* Intel 82451NX (PIIX4) IDE */
  359           0,
piix_chip_map
  361         },
  362         { PCI_PRODUCT_INTEL_82801AA_IDE, /* Intel 82801AA IDE (ICH) */
  363           0,
piix_chip_map
  365         },
  366         { PCI_PRODUCT_INTEL_82801AB_IDE, /* Intel 82801AB IDE (ICH0) */
  367           0,
piix_chip_map
  369         },
  370         { PCI_PRODUCT_INTEL_82801BAM_IDE, /* Intel 82801BAM IDE (ICH2) */
  371           0,
piix_chip_map
  373         },
  374         { PCI_PRODUCT_INTEL_82801BA_IDE, /* Intel 82801BA IDE (ICH2) */
  375           0,
piix_chip_map
  377         },
  378         { PCI_PRODUCT_INTEL_82801CAM_IDE, /* Intel 82801CAM IDE (ICH3) */
  379           0,
piix_chip_map
  381         },
  382         { PCI_PRODUCT_INTEL_82801CA_IDE, /* Intel 82801CA IDE (ICH3) */
  383           0,
piix_chip_map
  385         },
  386         { PCI_PRODUCT_INTEL_82801DB_IDE, /* Intel 82801DB IDE (ICH4) */
  387           0,
piix_chip_map
  389         },
  390         { PCI_PRODUCT_INTEL_82801DBL_IDE, /* Intel 82801DBL IDE (ICH4-L) */
  391           0,
piix_chip_map
  393         },
  394         { PCI_PRODUCT_INTEL_82801DBM_IDE, /* Intel 82801DBM IDE (ICH4-M) */
  395           0,
piix_chip_map
  397         },
  398         { PCI_PRODUCT_INTEL_82801EB_IDE, /* Intel 82801EB/ER (ICH5/5R) IDE */
  399           0,
piix_chip_map
  401         },
  402         { PCI_PRODUCT_INTEL_82801EB_SATA, /* Intel 82801EB (ICH5) SATA */
  403           0,
piixsata_chip_map
  405         },
  406         { PCI_PRODUCT_INTEL_82801ER_SATA, /* Intel 82801ER (ICH5R) SATA */
IDE_PCI_CLASS_OVERRIDE,
piixsata_chip_map
  409         },
  410         { PCI_PRODUCT_INTEL_6300ESB_IDE, /* Intel 6300ESB IDE */
IDE_PCI_CLASS_OVERRIDE,
piix_chip_map
  413         },
  414         { PCI_PRODUCT_INTEL_6300ESB_SATA, /* Intel 6300ESB SATA */
IDE_PCI_CLASS_OVERRIDE,
piixsata_chip_map
  417         },
  418         { PCI_PRODUCT_INTEL_6300ESB_SATA2, /* Intel 6300ESB SATA */
IDE_PCI_CLASS_OVERRIDE,
piixsata_chip_map
  421         },
  422         { PCI_PRODUCT_INTEL_6321ESB_IDE, /* Intel 6321ESB IDE */
IDE_PCI_CLASS_OVERRIDE,
piix_chip_map
  425         },
  426         { PCI_PRODUCT_INTEL_82801FB_IDE,  /* Intel 82801FB (ICH6) IDE */
IDE_PCI_CLASS_OVERRIDE,
piix_chip_map
  429         },
  430         { PCI_PRODUCT_INTEL_82801FBM_SATA,  /* Intel 82801FBM (ICH6M) SATA */
IDE_PCI_CLASS_OVERRIDE,
piixsata_chip_map
  433         },
  434         { PCI_PRODUCT_INTEL_82801FB_SATA, /* Intel 82801FB (ICH6) SATA */
IDE_PCI_CLASS_OVERRIDE,
piixsata_chip_map
  437         },
  438         { PCI_PRODUCT_INTEL_82801FR_SATA, /* Intel 82801FR (ICH6R) SATA */
IDE_PCI_CLASS_OVERRIDE,
piixsata_chip_map
  441         },
  442         { PCI_PRODUCT_INTEL_82801GB_IDE,  /* Intel 82801GB (ICH7) IDE */
IDE_PCI_CLASS_OVERRIDE,
piix_chip_map
  445         },
  446         { PCI_PRODUCT_INTEL_82801GB_SATA, /* Intel 82801GB (ICH7) SATA */
IDE_PCI_CLASS_OVERRIDE,
piixsata_chip_map
  449         },
  450         { PCI_PRODUCT_INTEL_82801GR_SATA, /* Intel 82801GR (ICH7R) SATA */
IDE_PCI_CLASS_OVERRIDE,
piixsata_chip_map
  453         },
  454         { PCI_PRODUCT_INTEL_82801GR_AHCI, /* Intel 82801GR (ICH7R) AHCI */
IDE_PCI_CLASS_OVERRIDE,
piixsata_chip_map
  457         },
  458         { PCI_PRODUCT_INTEL_82801GBM_SATA, /* Intel 82801GBM (ICH7M) SATA */
IDE_PCI_CLASS_OVERRIDE,
piixsata_chip_map
  461         },
  462         { PCI_PRODUCT_INTEL_82801GBM_AHCI, /* Intel 82801GBM (ICH7M) AHCI */
IDE_PCI_CLASS_OVERRIDE,
piixsata_chip_map
  465         },
  466         { PCI_PRODUCT_INTEL_82801GHM_RAID, /* Intel 82801GHM (ICH7-M DH) SATA */
IDE_PCI_CLASS_OVERRIDE,
piixsata_chip_map
  469         },
  470         { PCI_PRODUCT_INTEL_82801H_SATA_1_6P, /* Intel 82801H (ICH8) SATA */
IDE_PCI_CLASS_OVERRIDE,
piixsata_chip_map
  473         },
  474         { PCI_PRODUCT_INTEL_82801H_AHCI, /* Intel 82801H (ICH8) AHCI */
IDE_PCI_CLASS_OVERRIDE,
piixsata_chip_map
  477         },
  478         { PCI_PRODUCT_INTEL_82801H_RAID, /* Intel 82801H (ICH8) SATA */
IDE_PCI_CLASS_OVERRIDE,
piixsata_chip_map
  481         },
  482         { PCI_PRODUCT_INTEL_82801H_SATA_1_4P, /* Intel 82801H (ICH8) SATA */
IDE_PCI_CLASS_OVERRIDE,
piixsata_chip_map
  485         },
  486         { PCI_PRODUCT_INTEL_82801H_SATA_2, /* Intel 82801H (ICH8) SATA */
IDE_PCI_CLASS_OVERRIDE,
piixsata_chip_map
  489         },
  490         { PCI_PRODUCT_INTEL_82801HBM_SATA_1, /* Intel 82801HBM (ICH8M) SATA */
IDE_PCI_CLASS_OVERRIDE,
piixsata_chip_map
  493         },
  494         { PCI_PRODUCT_INTEL_82801HBM_SATA_2, /* Intel 82801HBM (ICH8M) SATA */
IDE_PCI_CLASS_OVERRIDE,
piixsata_chip_map
  497         },
  498         { PCI_PRODUCT_INTEL_82801HBM_IDE, /* Intel 82801HBM (ICH8M) IDE */
  499           0,
piix_chip_map
  501         },
  502         { PCI_PRODUCT_INTEL_6321ESB_SATA, /* Intel 6321ESB SATA */
  503           0,
piixsata_chip_map
  505         }
  506 };
  508 const struct pciide_product_desc pciide_amd_products[] =  {
  509         { PCI_PRODUCT_AMD_PBC756_IDE,   /* AMD 756 */
  510           0,
amd756_chip_map
  512         },
  513         { PCI_PRODUCT_AMD_766_IDE, /* AMD 766 */
  514           0,
amd756_chip_map
  516         },
  517         { PCI_PRODUCT_AMD_PBC768_IDE,
  518           0,
amd756_chip_map
  520         },
  521         { PCI_PRODUCT_AMD_8111_IDE,
  522           0,
amd756_chip_map
  524         },
  525         { PCI_PRODUCT_AMD_CS5536_IDE,
  526           0,
amd756_chip_map
  528         }
  529 };
  531 #ifdef notyet
  532 const struct pciide_product_desc pciide_opti_products[] = {
  534         { PCI_PRODUCT_OPTI_82C621,
  535           0,
opti_chip_map
  537         },
  538         { PCI_PRODUCT_OPTI_82C568,
  539           0,
opti_chip_map
  541         },
  542         { PCI_PRODUCT_OPTI_82D568,
  543           0,
opti_chip_map
  545         }
  546 };
  547 #endif
  549 const struct pciide_product_desc pciide_cmd_products[] =  {
  550         { PCI_PRODUCT_CMDTECH_640,      /* CMD Technology PCI0640 */
  551           0,
cmd_chip_map
  553         },
  554         { PCI_PRODUCT_CMDTECH_643,      /* CMD Technology PCI0643 */
  555           0,
cmd0643_9_chip_map
  557         },
  558         { PCI_PRODUCT_CMDTECH_646,      /* CMD Technology PCI0646 */
  559           0,
cmd0643_9_chip_map
  561         },
  562         { PCI_PRODUCT_CMDTECH_648,      /* CMD Technology PCI0648 */
IDE_PCI_CLASS_OVERRIDE,
cmd0643_9_chip_map
  565         },
  566         { PCI_PRODUCT_CMDTECH_649,      /* CMD Technology PCI0649 */
IDE_PCI_CLASS_OVERRIDE,
cmd0643_9_chip_map
  569         },
  570         { PCI_PRODUCT_CMDTECH_680,      /* CMD Technology PCI0680 */
IDE_PCI_CLASS_OVERRIDE,
cmd680_chip_map
  573         },
  574         { PCI_PRODUCT_CMDTECH_3112,     /* SiI3112 SATA */
IDE_PCI_CLASS_OVERRIDE,
sii3112_chip_map
  577         },
  578         { PCI_PRODUCT_CMDTECH_3512,     /* SiI3512 SATA */
IDE_PCI_CLASS_OVERRIDE,
sii3112_chip_map
  581         },
  582         { PCI_PRODUCT_CMDTECH_AAR_1210SA, /* Adaptec AAR-1210SA */
IDE_PCI_CLASS_OVERRIDE,
sii3112_chip_map
  585         },
  586         { PCI_PRODUCT_CMDTECH_3114,     /* SiI3114 */
IDE_PCI_CLASS_OVERRIDE,
sii3114_chip_map
  589         }
  590 };
  592 const struct pciide_product_desc pciide_via_products[] =  {
  593         { PCI_PRODUCT_VIATECH_VT82C416, /* VIA VT82C416 IDE */
  594           0,
apollo_chip_map
  596         },
  597         { PCI_PRODUCT_VIATECH_VT82C571, /* VIA VT82C571 IDE */
  598           0,
apollo_chip_map
  600         },
  601         { PCI_PRODUCT_VIATECH_VT6410, /* VIA VT6410 IDE */
IDE_PCI_CLASS_OVERRIDE,
apollo_chip_map
  604         },
  605         { PCI_PRODUCT_VIATECH_CX700_IDE, /* VIA CX700 IDE */
  606           0,
apollo_chip_map
  608         },
  609         { PCI_PRODUCT_VIATECH_VT6420_SATA, /* VIA VT6420 SATA */
IDE_PCI_CLASS_OVERRIDE,
sata_chip_map
  612         },
  613         { PCI_PRODUCT_VIATECH_VT6421_SATA, /* VIA VT6421 SATA */
IDE_PCI_CLASS_OVERRIDE,
sata_chip_map
  616         },
  617         { PCI_PRODUCT_VIATECH_VT8237A_SATA, /* VIA VT8237A SATA */
IDE_PCI_CLASS_OVERRIDE,
sata_chip_map
  620         },
  621         { PCI_PRODUCT_VIATECH_VT8237A_SATA_2, /* VIA VT8237A SATA */
  622           0,
sata_chip_map
  624         },
  625         { PCI_PRODUCT_VIATECH_VT8251_SATA, /* VIA VT8251 SATA */
IDE_PCI_CLASS_OVERRIDE,
sata_chip_map
  628         }
  629 };
  631 const struct pciide_product_desc pciide_cypress_products[] =  {
  632         { PCI_PRODUCT_CONTAQ_82C693,    /* Contaq CY82C693 IDE */
IDE_16BIT_IOSPACE,
cy693_chip_map
  635         }
  636 };
  638 const struct pciide_product_desc pciide_sis_products[] =  {
  639         { PCI_PRODUCT_SIS_5513,         /* SIS 5513 EIDE */
  640           0,
sis_chip_map
  642         },
  643         { PCI_PRODUCT_SIS_180,          /* SIS 180 SATA */
IDE_PCI_CLASS_OVERRIDE,
sata_chip_map
  646         },
  647         { PCI_PRODUCT_SIS_181,          /* SIS 181 SATA */
IDE_PCI_CLASS_OVERRIDE,
sata_chip_map
  650         },
  651         { PCI_PRODUCT_SIS_182,          /* SIS 182 SATA */
IDE_PCI_CLASS_OVERRIDE,
sata_chip_map
  654         }
  655 };
  657 const struct pciide_product_desc pciide_natsemi_products[] =  {
  658         { PCI_PRODUCT_NS_PC87415,       /* National Semi PC87415 IDE */
  659           0,
natsemi_chip_map
  661         },
  662         { PCI_PRODUCT_NS_SCx200_IDE,    /* National Semi SCx200 IDE */
  663           0,
ns_scx200_chip_map
  665         }
  666 };
  668 const struct pciide_product_desc pciide_acer_products[] =  {
  669         { PCI_PRODUCT_ALI_M5229,        /* Acer Labs M5229 UDMA IDE */
  670           0,
acer_chip_map
  672         }
  673 };
  675 const struct pciide_product_desc pciide_triones_products[] =  {
  676         { PCI_PRODUCT_TRIONES_HPT366,   /* Highpoint HPT36x/37x IDE */
IDE_PCI_CLASS_OVERRIDE,
hpt_chip_map,
  679         },
  680         { PCI_PRODUCT_TRIONES_HPT372A,  /* Highpoint HPT372A IDE */
IDE_PCI_CLASS_OVERRIDE,
hpt_chip_map
  683         },
  684         { PCI_PRODUCT_TRIONES_HPT302,   /* Highpoint HPT302 IDE */
IDE_PCI_CLASS_OVERRIDE,
hpt_chip_map
  687         },
  688         { PCI_PRODUCT_TRIONES_HPT371,   /* Highpoint HPT371 IDE */
IDE_PCI_CLASS_OVERRIDE,
hpt_chip_map
  691         },
  692         { PCI_PRODUCT_TRIONES_HPT374,   /* Highpoint HPT374 IDE */
IDE_PCI_CLASS_OVERRIDE,
hpt_chip_map
  695         }
  696 };
  698 const struct pciide_product_desc pciide_promise_products[] =  {
  699         { PCI_PRODUCT_PROMISE_PDC20246,
IDE_PCI_CLASS_OVERRIDE,
pdc202xx_chip_map,
  702         },
  703         { PCI_PRODUCT_PROMISE_PDC20262,
IDE_PCI_CLASS_OVERRIDE,
pdc202xx_chip_map,
  706         },
  707         { PCI_PRODUCT_PROMISE_PDC20265,
IDE_PCI_CLASS_OVERRIDE,
pdc202xx_chip_map,
  710         },
  711         { PCI_PRODUCT_PROMISE_PDC20267,
IDE_PCI_CLASS_OVERRIDE,
pdc202xx_chip_map,
  714         },
  715         { PCI_PRODUCT_PROMISE_PDC20268,
IDE_PCI_CLASS_OVERRIDE,
pdc202xx_chip_map,
  718         },
  719         { PCI_PRODUCT_PROMISE_PDC20268R,
IDE_PCI_CLASS_OVERRIDE,
pdc202xx_chip_map,
  722         },
  723         { PCI_PRODUCT_PROMISE_PDC20269,
IDE_PCI_CLASS_OVERRIDE,
pdc202xx_chip_map,
  726         },
  727         { PCI_PRODUCT_PROMISE_PDC20271,
IDE_PCI_CLASS_OVERRIDE,
pdc202xx_chip_map,
  730         },
  731         { PCI_PRODUCT_PROMISE_PDC20275,
IDE_PCI_CLASS_OVERRIDE,
pdc202xx_chip_map,
  734         },
  735         { PCI_PRODUCT_PROMISE_PDC20276,
IDE_PCI_CLASS_OVERRIDE,
pdc202xx_chip_map,
  738         },
  739         { PCI_PRODUCT_PROMISE_PDC20277,
IDE_PCI_CLASS_OVERRIDE,
pdc202xx_chip_map,
  742         },
  743         { PCI_PRODUCT_PROMISE_PDC20318,
IDE_PCI_CLASS_OVERRIDE,
pdcsata_chip_map,
  746         },
  747         { PCI_PRODUCT_PROMISE_PDC20319,
IDE_PCI_CLASS_OVERRIDE,
pdcsata_chip_map,
  750         },
  751         { PCI_PRODUCT_PROMISE_PDC20371,
IDE_PCI_CLASS_OVERRIDE,
pdcsata_chip_map,
  754         },
  755         { PCI_PRODUCT_PROMISE_PDC20375,
IDE_PCI_CLASS_OVERRIDE,
pdcsata_chip_map,
  758         },
  759         { PCI_PRODUCT_PROMISE_PDC20376,
IDE_PCI_CLASS_OVERRIDE,
pdcsata_chip_map,
  762         },
  763         { PCI_PRODUCT_PROMISE_PDC20377,
IDE_PCI_CLASS_OVERRIDE,
pdcsata_chip_map,
  766         },
  767         { PCI_PRODUCT_PROMISE_PDC20378,
IDE_PCI_CLASS_OVERRIDE,
pdcsata_chip_map,
  770         },
  771         { PCI_PRODUCT_PROMISE_PDC20379,
IDE_PCI_CLASS_OVERRIDE,
pdcsata_chip_map,
  774         },
  775         { PCI_PRODUCT_PROMISE_PDC40518,
IDE_PCI_CLASS_OVERRIDE,
pdcsata_chip_map,
  778         },
  779         { PCI_PRODUCT_PROMISE_PDC40519,
IDE_PCI_CLASS_OVERRIDE,
pdcsata_chip_map,
  782         },
  783         { PCI_PRODUCT_PROMISE_PDC40718,
IDE_PCI_CLASS_OVERRIDE,
pdcsata_chip_map,
  786         },
  787         { PCI_PRODUCT_PROMISE_PDC40719,
IDE_PCI_CLASS_OVERRIDE,
pdcsata_chip_map,
  790         },
  791         { PCI_PRODUCT_PROMISE_PDC40779,
IDE_PCI_CLASS_OVERRIDE,
pdcsata_chip_map,
  794         },
  795         { PCI_PRODUCT_PROMISE_PDC20571,
IDE_PCI_CLASS_OVERRIDE,
pdcsata_chip_map,
  798         },
  799         { PCI_PRODUCT_PROMISE_PDC20575,
IDE_PCI_CLASS_OVERRIDE,
pdcsata_chip_map,
  802         },
  803         { PCI_PRODUCT_PROMISE_PDC20579,
IDE_PCI_CLASS_OVERRIDE,
pdcsata_chip_map,
  806         },
  807         { PCI_PRODUCT_PROMISE_PDC20771,
IDE_PCI_CLASS_OVERRIDE,
pdcsata_chip_map,
  810         },
  811         { PCI_PRODUCT_PROMISE_PDC20775,
IDE_PCI_CLASS_OVERRIDE,
pdcsata_chip_map,
  814         }
  815 };
  817 const struct pciide_product_desc pciide_acard_products[] =  {
  818         { PCI_PRODUCT_ACARD_ATP850U,    /* Acard ATP850U Ultra33 Controller */
IDE_PCI_CLASS_OVERRIDE,
acard_chip_map,
  821         },
  822         { PCI_PRODUCT_ACARD_ATP860,     /* Acard ATP860 Ultra66 Controller */
IDE_PCI_CLASS_OVERRIDE,
acard_chip_map,
  825         },
  826         { PCI_PRODUCT_ACARD_ATP860A,    /* Acard ATP860-A Ultra66 Controller */
IDE_PCI_CLASS_OVERRIDE,
acard_chip_map,
  829         },
  830         { PCI_PRODUCT_ACARD_ATP865A,    /* Acard ATP865-A Ultra133 Controller */
IDE_PCI_CLASS_OVERRIDE,
acard_chip_map,
  833         },
  834         { PCI_PRODUCT_ACARD_ATP865R,    /* Acard ATP865-R Ultra133 Controller */
IDE_PCI_CLASS_OVERRIDE,
acard_chip_map,
  837         }
  838 };
  840 const struct pciide_product_desc pciide_serverworks_products[] =  {
  841         { PCI_PRODUCT_RCC_OSB4_IDE,
  842           0,
serverworks_chip_map,
  844         },
  845         { PCI_PRODUCT_RCC_CSB5_IDE,
  846           0,
serverworks_chip_map,
  848         },
  849         { PCI_PRODUCT_RCC_CSB6_IDE,
  850           0,
serverworks_chip_map,
  852         },
  853         { PCI_PRODUCT_RCC_CSB6_RAID_IDE,
  854           0,
serverworks_chip_map,
  856         },
  857         { PCI_PRODUCT_RCC_HT_1000_IDE,
  858           0,
serverworks_chip_map,
  860         },
  861         { PCI_PRODUCT_RCC_K2_SATA,
IDE_PCI_CLASS_OVERRIDE,
svwsata_chip_map,
  864         },
  865         { PCI_PRODUCT_RCC_FRODO4_SATA,
  866           0,
svwsata_chip_map,
  868         },
  869         { PCI_PRODUCT_RCC_FRODO8_SATA,
  870           0,
svwsata_chip_map,
  872         },
  873         { PCI_PRODUCT_RCC_HT_1000_SATA_1,
  874           0,
svwsata_chip_map,
  876         },
  877         { PCI_PRODUCT_RCC_HT_1000_SATA_2,
  878           0,
svwsata_chip_map,
  880         }
  881 };
  883 const struct pciide_product_desc pciide_nvidia_products[] = {
  884         { PCI_PRODUCT_NVIDIA_NFORCE_IDE,
  885           0,
nforce_chip_map
  887         },
  888         { PCI_PRODUCT_NVIDIA_NFORCE2_IDE,
  889           0,
nforce_chip_map
  891         },
  892         { PCI_PRODUCT_NVIDIA_NFORCE2_400_IDE,
  893           0,
nforce_chip_map
  895         },
  896         { PCI_PRODUCT_NVIDIA_NFORCE3_IDE,
  897           0,
nforce_chip_map
  899         },
  900         { PCI_PRODUCT_NVIDIA_NFORCE3_250_IDE,
  901           0,
nforce_chip_map
  903         },
  904         { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133,
  905           0,
nforce_chip_map
  907         },
  908         { PCI_PRODUCT_NVIDIA_MCP04_IDE,
  909           0,
nforce_chip_map
  911         },
  912         { PCI_PRODUCT_NVIDIA_MCP51_IDE,
  913           0,
nforce_chip_map
  915         },
  916         { PCI_PRODUCT_NVIDIA_MCP55_IDE,
  917           0,
nforce_chip_map
  919         },
  920         { PCI_PRODUCT_NVIDIA_MCP61_IDE,
  921           0,
nforce_chip_map
  923         },
  924         { PCI_PRODUCT_NVIDIA_MCP65_IDE,
  925           0,
nforce_chip_map
  927         },
  928         { PCI_PRODUCT_NVIDIA_MCP67_IDE,
  929           0,
nforce_chip_map
  931         },
  932         { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA,
  933           0,
sata_chip_map
  935         },
  936         { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA,
  937           0,
sata_chip_map
  939         },
  940         { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2,
  941           0,
sata_chip_map
  943         },
  944         { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1,
  945           0,
sata_chip_map
  947         },
  948         { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2,
  949           0,
sata_chip_map
  951         },
  952         { PCI_PRODUCT_NVIDIA_MCP04_SATA,
  953           0,
sata_chip_map
  955         },
  956         { PCI_PRODUCT_NVIDIA_MCP04_SATA2,
  957           0,
sata_chip_map
  959         },
  960         { PCI_PRODUCT_NVIDIA_MCP51_SATA,
  961           0,
sata_chip_map
  963         },
  964         { PCI_PRODUCT_NVIDIA_MCP51_SATA2,
  965           0,
sata_chip_map
  967         },
  968         { PCI_PRODUCT_NVIDIA_MCP55_SATA,
  969           0,
sata_chip_map
  971         },
  972         { PCI_PRODUCT_NVIDIA_MCP55_SATA2,
  973           0,
sata_chip_map
  975         },
  976         { PCI_PRODUCT_NVIDIA_MCP61_SATA,
  977           0,
sata_chip_map
  979         },
  980         { PCI_PRODUCT_NVIDIA_MCP61_SATA2,
  981           0,
sata_chip_map
  983         },
  984         { PCI_PRODUCT_NVIDIA_MCP61_SATA3,
  985           0,
sata_chip_map
  987         },
  988         { PCI_PRODUCT_NVIDIA_MCP65_SATA,
  989           0,
sata_chip_map
  991         },
  992         { PCI_PRODUCT_NVIDIA_MCP65_SATA2,
  993           0,
sata_chip_map
  995         },
  996         { PCI_PRODUCT_NVIDIA_MCP65_SATA3,
  997           0,
sata_chip_map
  999         },
 1000         { PCI_PRODUCT_NVIDIA_MCP65_SATA4,
 1001           0,
sata_chip_map
 1003         },
 1004         { PCI_PRODUCT_NVIDIA_MCP67_SATA,
 1005           0,
sata_chip_map
 1007         },
 1008         { PCI_PRODUCT_NVIDIA_MCP67_SATA2,
 1009           0,
sata_chip_map
 1011         },
 1012         { PCI_PRODUCT_NVIDIA_MCP67_SATA3,
 1013           0,
sata_chip_map
 1015         },
 1016         { PCI_PRODUCT_NVIDIA_MCP67_SATA4,
 1017           0,
sata_chip_map
 1019         }
 1020 };
 1022 const struct pciide_product_desc pciide_ite_products[] = {
 1023         { PCI_PRODUCT_ITEXPRESS_IT8211F,
IDE_PCI_CLASS_OVERRIDE,
ite_chip_map
 1026         },
 1027         { PCI_PRODUCT_ITEXPRESS_IT8212F,
IDE_PCI_CLASS_OVERRIDE,
ite_chip_map
 1030         }
 1031 };
 1033 const struct pciide_product_desc pciide_ati_products[] = {
 1034         { PCI_PRODUCT_ATI_IXP_IDE_200,
 1035           0,
ixp_chip_map
 1037         },
 1038         { PCI_PRODUCT_ATI_IXP_IDE_300,
 1039           0,
ixp_chip_map
 1041         },
 1042         { PCI_PRODUCT_ATI_IXP_IDE_400,
 1043           0,
ixp_chip_map
 1045         },
 1046         { PCI_PRODUCT_ATI_IXP_IDE_600,
 1047           0,
ixp_chip_map
 1049         },
 1050         { PCI_PRODUCT_ATI_IXP_SATA_300,
IDE_PCI_CLASS_OVERRIDE,
sii3112_chip_map
 1053         },
 1054         { PCI_PRODUCT_ATI_IXP_SATA_400_1,
IDE_PCI_CLASS_OVERRIDE,
sii3112_chip_map
 1057         },
 1058         { PCI_PRODUCT_ATI_IXP_SATA_400_2,
IDE_PCI_CLASS_OVERRIDE,
sii3112_chip_map
 1061         }
 1062 };
 1064 const struct pciide_product_desc pciide_jmicron_products[] = {
 1065         { PCI_PRODUCT_JMICRON_JMB361,
 1066           0,
jmicron_chip_map
 1068         },
 1069         { PCI_PRODUCT_JMICRON_JMB363,
 1070           0,
jmicron_chip_map
 1072         },
 1073         { PCI_PRODUCT_JMICRON_JMB365,
 1074           0,
jmicron_chip_map
 1076         },
 1077         { PCI_PRODUCT_JMICRON_JMB366,
 1078           0,
jmicron_chip_map
 1080         },
 1081         { PCI_PRODUCT_JMICRON_JMB368,
 1082           0,
jmicron_chip_map
 1084         }
 1085 };
 1087 struct pciide_vendor_desc {
u_int32_t ide_vendor;
 1089         const struct pciide_product_desc *ide_products;
 1090         int ide_nproducts;
 1091 };
 1093 const struct pciide_vendor_desc pciide_vendors[] = {
 1094         { PCI_VENDOR_INTEL, pciide_intel_products,
 1095           sizeof(pciide_intel_products)/sizeof(pciide_intel_products[0]) },
 1096         { PCI_VENDOR_AMD, pciide_amd_products,
 1097           sizeof(pciide_amd_products)/sizeof(pciide_amd_products[0]) },
 1098 #ifdef notyet
 1099         { PCI_VENDOR_OPTI, pciide_opti_products,
 1100           sizeof(pciide_opti_products)/sizeof(pciide_opti_products[0]) },
 1101 #endif
 1102         { PCI_VENDOR_CMDTECH, pciide_cmd_products,
 1103           sizeof(pciide_cmd_products)/sizeof(pciide_cmd_products[0]) },
 1104         { PCI_VENDOR_VIATECH, pciide_via_products,
 1105           sizeof(pciide_via_products)/sizeof(pciide_via_products[0]) },
 1106         { PCI_VENDOR_CONTAQ, pciide_cypress_products,
 1107           sizeof(pciide_cypress_products)/sizeof(pciide_cypress_products[0]) },
 1108         { PCI_VENDOR_SIS, pciide_sis_products,
 1109           sizeof(pciide_sis_products)/sizeof(pciide_sis_products[0]) },
 1110         { PCI_VENDOR_NS, pciide_natsemi_products,
 1111           sizeof(pciide_natsemi_products)/sizeof(pciide_natsemi_products[0]) },
 1112         { PCI_VENDOR_ALI, pciide_acer_products,
 1113           sizeof(pciide_acer_products)/sizeof(pciide_acer_products[0]) },
 1114         { PCI_VENDOR_TRIONES, pciide_triones_products,
 1115           sizeof(pciide_triones_products)/sizeof(pciide_triones_products[0]) },
 1116         { PCI_VENDOR_ACARD, pciide_acard_products,
 1117           sizeof(pciide_acard_products)/sizeof(pciide_acard_products[0]) },
 1118         { PCI_VENDOR_RCC, pciide_serverworks_products,
 1119           sizeof(pciide_serverworks_products)/sizeof(pciide_serverworks_products[0]) },
 1120         { PCI_VENDOR_PROMISE, pciide_promise_products,
 1121           sizeof(pciide_promise_products)/sizeof(pciide_promise_products[0]) },
 1122         { PCI_VENDOR_NVIDIA, pciide_nvidia_products,
 1123           sizeof(pciide_nvidia_products)/sizeof(pciide_nvidia_products[0]) },
 1124         { PCI_VENDOR_ITEXPRESS, pciide_ite_products,
 1125           sizeof(pciide_ite_products)/sizeof(pciide_ite_products[0]) },
 1126         { PCI_VENDOR_ATI, pciide_ati_products,
 1127           sizeof(pciide_ati_products)/sizeof(pciide_ati_products[0]) },
 1128         { PCI_VENDOR_JMICRON, pciide_jmicron_products,
 1129           sizeof(pciide_jmicron_products)/sizeof(pciide_jmicron_products[0]) }
 1130 };
 1132 /* options passed via the 'flags' config keyword */
 1133 #define PCIIDE_OPTIONS_DMA      0x01
 1135 int     pciide_match(struct device *, void *, void *);
 1136 void    pciide_attach(struct device *, struct device *, void *);
 1138 struct cfattach pciide_pci_ca = {
 1139         sizeof(struct pciide_softc), pciide_match, pciide_attach
 1140 };
 1142 struct cfattach pciide_jmb_ca = {
 1143         sizeof(struct pciide_softc), pciide_match, pciide_attach
 1144 };
 1146 struct cfdriver pciide_cd = {
NULL, "pciide", DV_DULL
 1148 };
 1150 int     pciide_mapregs_compat( struct pci_attach_args *,
 1151             struct pciide_channel *, int, bus_size_t *, bus_size_t *);
 1152 int     pciide_mapregs_native(struct pci_attach_args *,
 1153             struct pciide_channel *, bus_size_t *, bus_size_t *,
 1154             int (*pci_intr)(void *));
 1155 void    pciide_mapreg_dma(struct pciide_softc *,
 1156             struct pci_attach_args *);
 1157 int     pciide_chansetup(struct pciide_softc *, int, pcireg_t);
 1158 void    pciide_mapchan(struct pci_attach_args *,
 1159             struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *,
 1160             int (*pci_intr)(void *));
 1161 int     pciide_chan_candisable(struct pciide_channel *);
 1162 void    pciide_map_compat_intr( struct pci_attach_args *,
 1163             struct pciide_channel *, int, int);
 1164 void    pciide_unmap_compat_intr( struct pci_attach_args *,
 1165             struct pciide_channel *, int, int);
 1166 int     pciide_compat_intr(void *);
 1167 int     pciide_pci_intr(void *);
 1168 int     pciide_intr_flag(struct pciide_channel *);
 1170 const struct pciide_product_desc *pciide_lookup_product(u_int32_t);
 1172 const struct pciide_product_desc *
pciide_lookup_product(u_int32_t id)
 1174 {
 1175         const struct pciide_product_desc *pp;
 1176         const struct pciide_vendor_desc *vp;
 1177         int i;
 1179         for (i = 0, vp = pciide_vendors;
i < sizeof(pciide_vendors)/sizeof(pciide_vendors[0]);
vp++, i++)
 1182                 if (PCI_VENDOR(id) == vp->ide_vendor)
 1183                         break;
 1185         if (i == sizeof(pciide_vendors)/sizeof(pciide_vendors[0]))
 1186                 return (NULL);
 1188         for (pp = vp->ide_products, i = 0; i < vp->ide_nproducts; pp++, i++)
 1189                 if (PCI_PRODUCT(id) == pp->ide_product)
 1190                         break;
 1192         if (i == vp->ide_nproducts)
 1193                 return (NULL);
 1194         return (pp);
 1195 }
 1197 int
pciide_match(struct device *parent, void *match, void *aux)
 1199 {
 1200         struct pci_attach_args *pa = aux;
 1201         const struct pciide_product_desc *pp;
 1203         /*
 1204          * Some IDE controllers have severe bugs when used in PCI mode.
 1205          * We punt and attach them to the ISA bus instead.
 1206          */
 1207         if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PCTECH &&
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_PCTECH_RZ1000)
 1209                 return (0);
 1211         /*
 1212          * Some controllers (e.g. promise Ultra-33) don't claim to be PCI IDE
 1213          * controllers. Let see if we can deal with it anyway.
 1214          */
pp = pciide_lookup_product(pa->pa_id);
 1216         if (pp  && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE))
 1217                 return (1);
 1219         /*
 1220          * Check the ID register to see that it's a PCI IDE controller.
 1221          * If it is, we assume that we can deal with it; it _should_
 1222          * work in a standardized way...
 1223          */
 1224         if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE) {
 1225                 switch (PCI_SUBCLASS(pa->pa_class)) {
 1226                 case PCI_SUBCLASS_MASS_STORAGE_IDE:
 1227                         return (1);
 1229                 /*
 1230                  * We only match these if we know they have
 1231                  * a match, as we may not support native interfaces
 1232                  * on them.
 1233                  */
 1234                 case PCI_SUBCLASS_MASS_STORAGE_SATA:
 1235                 case PCI_SUBCLASS_MASS_STORAGE_RAID:
 1236                         if (pp)
 1237                                 return (1);
 1238                         else
 1239                                 return (0);
 1240                         break;
 1241                 }
 1242         }
 1244         return (0);
 1245 }
 1247 void
pciide_attach(struct device *parent, struct device *self, void *aux)
 1249 {
 1250         struct pciide_softc *sc = (struct pciide_softc *)self;
 1251         struct pci_attach_args *pa = aux;
sc->sc_pp = pciide_lookup_product(pa->pa_id);
 1254         if (sc->sc_pp == NULL)
sc->sc_pp = &default_product_desc;
sc->sc_rev = PCI_REVISION(pa->pa_class);
sc->sc_pc = pa->pa_pc;
sc->sc_tag = pa->pa_tag;
 1261         /* Set up DMA defaults; these might be adjusted by chip_map. */
sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX;
sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_ALIGN;
sc->sc_dmacmd_read = pciide_dmacmd_read;
sc->sc_dmacmd_write = pciide_dmacmd_write;
sc->sc_dmactl_read = pciide_dmactl_read;
sc->sc_dmactl_write = pciide_dmactl_write;
sc->sc_dmatbl_write = pciide_dmatbl_write;
WDCDEBUG_PRINT((" sc_pc=%p, sc_tag=%p, pa_class=0x%x\n", sc->sc_pc,
sc->sc_tag, pa->pa_class), DEBUG_PROBE);
sc->sc_pp->chip_map(sc, pa);
WDCDEBUG_PRINT(("pciide: command/status register=0x%x\n",
pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG)),
DEBUG_PROBE);
 1279 }
 1281 int
pciide_mapregs_compat(struct pci_attach_args *pa, struct pciide_channel *cp,
 1283     int compatchan, bus_size_t *cmdsizep, bus_size_t *ctlsizep)
 1284 {
 1285         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 1286         struct channel_softc *wdc_cp = &cp->wdc_channel;
pcireg_t csr;
cp->compat = 1;
 1290         *cmdsizep = PCIIDE_COMPAT_CMD_SIZE;
 1291         *ctlsizep = PCIIDE_COMPAT_CTL_SIZE;
csr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG,
csr | PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE);
wdc_cp->cmd_iot = pa->pa_iot;
 1299         if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan),
PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) {
printf("%s: couldn't map %s cmd regs\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
 1303                 return (0);
 1304         }
wdc_cp->ctl_iot = pa->pa_iot;
 1308         if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan),
PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) {
printf("%s: couldn't map %s ctl regs\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh,
PCIIDE_COMPAT_CMD_SIZE);
 1314                 return (0);
 1315         }
 1317         return (1);
 1318 }
 1320 int
pciide_mapregs_native(struct pci_attach_args *pa, struct pciide_channel *cp,
bus_size_t *cmdsizep, bus_size_t *ctlsizep, int (*pci_intr)(void *))
 1323 {
 1324         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 1325         struct channel_softc *wdc_cp = &cp->wdc_channel;
 1326         const char *intrstr;
pci_intr_handle_t intrhandle;
pcireg_t maptype;
cp->compat = 0;
 1332         if (sc->sc_pci_ih == NULL) {
 1333                 if (pci_intr_map(pa, &intrhandle) != 0) {
printf("%s: couldn't map native-PCI interrupt\n",
sc->sc_wdcdev.sc_dev.dv_xname);
 1336                         return (0);
 1337                 }
intrstr = pci_intr_string(pa->pa_pc, intrhandle);
sc->sc_pci_ih = pci_intr_establish(pa->pa_pc,
intrhandle, IPL_BIO, pci_intr, sc,
sc->sc_wdcdev.sc_dev.dv_xname);
 1342                 if (sc->sc_pci_ih != NULL) {
printf("%s: using %s for native-PCI interrupt\n",
sc->sc_wdcdev.sc_dev.dv_xname,
intrstr ? intrstr : "unknown interrupt");
 1346                 } else {
printf("%s: couldn't establish native-PCI interrupt",
sc->sc_wdcdev.sc_dev.dv_xname);
 1349                         if (intrstr != NULL)
printf(" at %s", intrstr);
printf("\n");
 1352                         return (0);
 1353                 }
 1354         }
cp->ih = sc->sc_pci_ih;
maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag,
PCIIDE_REG_CMD_BASE(wdc_cp->channel));
WDCDEBUG_PRINT(("%s: %s cmd regs mapping: %s\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name,
 1361             (maptype == PCI_MAPREG_TYPE_IO ? "I/O" : "memory")), DEBUG_PROBE);
 1362         if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel),
maptype, 0,
 1364             &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep, 0) != 0) {
printf("%s: couldn't map %s cmd regs\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
 1367                 return (0);
 1368         }
maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag,
PCIIDE_REG_CTL_BASE(wdc_cp->channel));
WDCDEBUG_PRINT(("%s: %s ctl regs mapping: %s\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name,
 1374             (maptype == PCI_MAPREG_TYPE_IO ? "I/O": "memory")), DEBUG_PROBE);
 1375         if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel),
maptype, 0,
 1377             &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep, 0) != 0) {
printf("%s: couldn't map %s ctl regs\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep);
 1381                 return (0);
 1382         }
 1383         /*
 1384          * In native mode, 4 bytes of I/O space are mapped for the control
 1385          * register, the control register is at offset 2. Pass the generic
 1386          * code a handle for only one byte at the right offset.
 1387          */
 1388         if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1,
 1389             &wdc_cp->ctl_ioh) != 0) {
printf("%s: unable to subregion %s ctl regs\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep);
bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep);
 1394                 return (0);
 1395         }
 1396         return (1);
 1397 }
 1399 void
pciide_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa)
 1401 {
pcireg_t maptype;
bus_addr_t addr;
 1405         /*
 1406          * Map DMA registers
 1407          *
 1408          * Note that sc_dma_ok is the right variable to test to see if
 1409          * DMA can be done.  If the interface doesn't support DMA,
 1410          * sc_dma_ok will never be non-zero.  If the DMA regs couldn't
 1411          * be mapped, it'll be zero.  I.e., sc_dma_ok will only be
 1412          * non-zero if the interface supports DMA and the registers
 1413          * could be mapped.
 1414          *
 1415          * XXX Note that despite the fact that the Bus Master IDE specs
 1416          * XXX say that "The bus master IDE function uses 16 bytes of IO
 1417          * XXX space", some controllers (at least the United
 1418          * XXX Microelectronics UM8886BF) place it in memory space.
 1419          */
maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag,
PCIIDE_REG_BUS_MASTER_DMA);
 1424         switch (maptype) {
 1425         case PCI_MAPREG_TYPE_IO:
sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag,
PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO,
 1428                     &addr, NULL, NULL) == 0);
 1429                 if (sc->sc_dma_ok == 0) {
printf(", unused (couldn't query registers)");
 1431                         break;
 1432                 }
 1433                 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE)
 1434                     && addr >= 0x10000) {
sc->sc_dma_ok = 0;
printf(", unused (registers at unsafe address %#lx)", addr);
 1437                         break;
 1438                 }
 1439                 /* FALLTHROUGH */
 1441         case PCI_MAPREG_MEM_TYPE_32BIT:
sc->sc_dma_ok = (pci_mapreg_map(pa,
PCIIDE_REG_BUS_MASTER_DMA, maptype, 0,
 1444                     &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL, 0) == 0);
sc->sc_dmat = pa->pa_dmat;
 1446                 if (sc->sc_dma_ok == 0) {
printf(", unused (couldn't map registers)");
 1448                 } else {
sc->sc_wdcdev.dma_arg = sc;
sc->sc_wdcdev.dma_init = pciide_dma_init;
sc->sc_wdcdev.dma_start = pciide_dma_start;
sc->sc_wdcdev.dma_finish = pciide_dma_finish;
 1453                 }
 1454                 break;
 1456         default:
sc->sc_dma_ok = 0;
printf(", (unsupported maptype 0x%x)", maptype);
 1459                 break;
 1460         }
 1461 }
 1463 int
pciide_intr_flag(struct pciide_channel *cp)
 1465 {
 1466         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 1467         int chan = cp->wdc_channel.channel;
 1469         if (cp->dma_in_progress) {
 1470                 int retry = 10;
 1471                 int status;
 1473                 /* Check the status register */
 1474                 for (retry = 10; retry > 0; retry--) {
status = PCIIDE_DMACTL_READ(sc, chan);
 1476                         if (status & IDEDMA_CTL_INTR) {
 1477                                 break;
 1478                         }
DELAY(5);
 1480                 }
 1482                 /* Not for us.  */
 1483                 if (retry == 0)
 1484                         return (0);
 1486                 return (1);
 1487         }
 1489         return (-1);
 1490 }
 1492 int
pciide_compat_intr(void *arg)
 1494 {
 1495         struct pciide_channel *cp = arg;
 1497         if (pciide_intr_flag(cp) == 0)
 1498                 return (0);
 1500 #ifdef DIAGNOSTIC
 1501         /* should only be called for a compat channel */
 1502         if (cp->compat == 0)
panic("pciide compat intr called for non-compat chan %p", cp);
 1504 #endif
 1505         return (wdcintr(&cp->wdc_channel));
 1506 }
 1508 int
pciide_pci_intr(void *arg)
 1510 {
 1511         struct pciide_softc *sc = arg;
 1512         struct pciide_channel *cp;
 1513         struct channel_softc *wdc_cp;
 1514         int i, rv, crv;
rv = 0;
 1517         for (i = 0; i < sc->sc_wdcdev.nchannels; i++) {
cp = &sc->pciide_channels[i];
wdc_cp = &cp->wdc_channel;
 1521                 /* If a compat channel skip. */
 1522                 if (cp->compat)
 1523                         continue;
 1525                 if (pciide_intr_flag(cp) == 0)
 1526                         continue;
crv = wdcintr(wdc_cp);
 1529                 if (crv == 0)
 1530                         ;               /* leave rv alone */
 1531                 else if (crv == 1)
rv = 1;         /* claim the intr */
 1533                 else if (rv == 0)       /* crv should be -1 in this case */
rv = crv;       /* if we've done no better, take it */
 1535         }
 1536         return (rv);
 1537 }
u_int8_t
pciide_dmacmd_read(struct pciide_softc *sc, int chan)
 1541 {
 1542         return (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CMD(chan)));
 1544 }
 1546 void
pciide_dmacmd_write(struct pciide_softc *sc, int chan, u_int8_t val)
 1548 {
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CMD(chan), val);
 1551 }
u_int8_t
pciide_dmactl_read(struct pciide_softc *sc, int chan)
 1555 {
 1556         return (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CTL(chan)));
 1558 }
 1560 void
pciide_dmactl_write(struct pciide_softc *sc, int chan, u_int8_t val)
 1562 {
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CTL(chan), val);
 1565 }
 1567 void
pciide_dmatbl_write(struct pciide_softc *sc, int chan, u_int32_t val)
 1569 {
bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_TBL(chan), val);
 1572 }
 1574 void
pciide_channel_dma_setup(struct pciide_channel *cp)
 1576 {
 1577         int drive;
 1578         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 1579         struct ata_drive_datas *drvp;
 1581         for (drive = 0; drive < 2; drive++) {
drvp = &cp->wdc_channel.ch_drive[drive];
 1583                 /* If no drive, skip */
 1584                 if ((drvp->drive_flags & DRIVE) == 0)
 1585                         continue;
 1586                 /* setup DMA if needed */
 1587                 if (((drvp->drive_flags & DRIVE_DMA) == 0 &&
 1588                     (drvp->drive_flags & DRIVE_UDMA) == 0) ||
sc->sc_dma_ok == 0) {
drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA);
 1591                         continue;
 1592                 }
 1593                 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive)
 1594                     != 0) {
 1595                         /* Abort DMA setup */
drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA);
 1597                         continue;
 1598                 }
 1599         }
 1600 }
 1602 int
pciide_dma_table_setup(struct pciide_softc *sc, int channel, int drive)
 1604 {
bus_dma_segment_t seg;
 1606         int error, rseg;
 1607         const bus_size_t dma_table_size =
 1608             sizeof(struct idedma_table) * NIDEDMA_TABLES;
 1609         struct pciide_dma_maps *dma_maps =
 1610             &sc->pciide_channels[channel].dma_maps[drive];
 1612         /* If table was already allocated, just return */
 1613         if (dma_maps->dma_table)
 1614                 return (0);
 1616         /* Allocate memory for the DMA tables and map it */
 1617         if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size,
IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg,
BUS_DMA_NOWAIT)) != 0) {
printf("%s:%d: unable to allocate table DMA for "
 1621                     "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname,
channel, drive, error);
 1623                 return (error);
 1624         }
 1626         if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
dma_table_size,
 1628             (caddr_t *)&dma_maps->dma_table,
BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
printf("%s:%d: unable to map table DMA for"
 1631                     "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname,
channel, drive, error);
 1633                 return (error);
 1634         }
WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %ld, "
 1637             "phy 0x%lx\n", dma_maps->dma_table, dma_table_size,
seg.ds_addr), DEBUG_PROBE);
 1640         /* Create and load table DMA map for this disk */
 1641         if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size,
 1642             1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT,
 1643             &dma_maps->dmamap_table)) != 0) {
printf("%s:%d: unable to create table DMA map for "
 1645                     "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname,
channel, drive, error);
 1647                 return (error);
 1648         }
 1649         if ((error = bus_dmamap_load(sc->sc_dmat,
dma_maps->dmamap_table,
dma_maps->dma_table,
dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) {
printf("%s:%d: unable to load table DMA map for "
 1654                     "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname,
channel, drive, error);
 1656                 return (error);
 1657         }
WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n",
dma_maps->dmamap_table->dm_segs[0].ds_addr), DEBUG_PROBE);
 1660         /* Create a xfer DMA map for this drive */
 1661         if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX,
NIDEDMA_TABLES, sc->sc_dma_maxsegsz, sc->sc_dma_boundary,
BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
 1664             &dma_maps->dmamap_xfer)) != 0) {
printf("%s:%d: unable to create xfer DMA map for "
 1666                     "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname,
channel, drive, error);
 1668                 return (error);
 1669         }
 1670         return (0);
 1671 }
 1673 int
pciide_dma_init(void *v, int channel, int drive, void *databuf,
size_t datalen, int flags)
 1676 {
 1677         struct pciide_softc *sc = v;
 1678         int error, seg;
 1679         struct pciide_channel *cp = &sc->pciide_channels[channel];
 1680         struct pciide_dma_maps *dma_maps =
 1681             &sc->pciide_channels[channel].dma_maps[drive];
 1682 #ifndef BUS_DMA_RAW
 1683 #define BUS_DMA_RAW 0
 1684 #endif
error = bus_dmamap_load(sc->sc_dmat,
dma_maps->dmamap_xfer,
databuf, datalen, NULL, BUS_DMA_NOWAIT|BUS_DMA_RAW);
 1689         if (error) {
printf("%s:%d: unable to load xfer DMA map for "
 1691                     "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname,
channel, drive, error);
 1693                 return (error);
 1694         }
bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0,
dma_maps->dmamap_xfer->dm_mapsize,
 1698             (flags & WDC_DMA_READ) ?
BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
 1701         for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) {
 1702 #ifdef DIAGNOSTIC
 1703                 /* A segment must not cross a 64k boundary */
 1704                 {
u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr;
u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len;
 1707                 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) !=
 1708                     ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) {
printf("pciide_dma: segment %d physical addr 0x%lx"
 1710                             " len 0x%lx not properly aligned\n",
seg, phys, len);
panic("pciide_dma: buf align");
 1713                 }
 1714                 }
 1715 #endif
dma_maps->dma_table[seg].base_addr =
htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr);
dma_maps->dma_table[seg].byte_count =
htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len &
IDEDMA_BYTE_COUNT_MASK);
WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n",
seg, letoh32(dma_maps->dma_table[seg].byte_count),
letoh32(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA);
 1725         }
dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |=
htole32(IDEDMA_BYTE_COUNT_EOT);
bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0,
dma_maps->dmamap_table->dm_mapsize,
BUS_DMASYNC_PREWRITE);
 1733         /* Maps are ready. Start DMA function */
 1734 #ifdef DIAGNOSTIC
 1735         if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) {
printf("pciide_dma_init: addr 0x%lx not properly aligned\n",
dma_maps->dmamap_table->dm_segs[0].ds_addr);
panic("pciide_dma_init: table align");
 1739         }
 1740 #endif
 1742         /* Clear status bits */
PCIIDE_DMACTL_WRITE(sc, channel, PCIIDE_DMACTL_READ(sc, channel));
 1744         /* Write table addr */
PCIIDE_DMATBL_WRITE(sc, channel,
dma_maps->dmamap_table->dm_segs[0].ds_addr);
 1747         /* set read/write */
PCIIDE_DMACMD_WRITE(sc, channel,
 1749             ((flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE : 0) | cp->idedma_cmd);
 1750         /* remember flags */
dma_maps->dma_flags = flags;
 1752         return (0);
 1753 }
 1755 void
pciide_dma_start(void *v, int channel, int drive)
 1757 {
 1758         struct pciide_softc *sc = v;
WDCDEBUG_PRINT(("pciide_dma_start\n"), DEBUG_XFERS);
PCIIDE_DMACMD_WRITE(sc, channel, PCIIDE_DMACMD_READ(sc, channel) |
IDEDMA_CMD_START);
sc->pciide_channels[channel].dma_in_progress = 1;
 1765 }
 1767 int
pciide_dma_finish(void *v, int channel, int drive, int force)
 1769 {
 1770         struct pciide_softc *sc = v;
 1771         struct pciide_channel *cp = &sc->pciide_channels[channel];
u_int8_t status;
 1773         int error = 0;
 1774         struct pciide_dma_maps *dma_maps =
 1775             &sc->pciide_channels[channel].dma_maps[drive];
status = PCIIDE_DMACTL_READ(sc, channel);
WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status),
DEBUG_XFERS);
 1781         if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) {
error = WDC_DMAST_NOIRQ;
 1783                 goto done;
 1784         }
 1786         /* stop DMA channel */
PCIIDE_DMACMD_WRITE(sc, channel,
 1788             ((dma_maps->dma_flags & WDC_DMA_READ) ?
 1789             0x00 : IDEDMA_CMD_WRITE) | cp->idedma_cmd);
 1791         /* Unload the map of the data buffer */
bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0,
dma_maps->dmamap_xfer->dm_mapsize,
 1794             (dma_maps->dma_flags & WDC_DMA_READ) ?
BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer);
 1798         /* Clear status bits */
PCIIDE_DMACTL_WRITE(sc, channel, status);
 1801         if ((status & IDEDMA_CTL_ERR) != 0) {
printf("%s:%d:%d: bus-master DMA error: status=0x%x\n",
sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status);
error |= WDC_DMAST_ERR;
 1805         }
 1807         if ((status & IDEDMA_CTL_INTR) == 0) {
printf("%s:%d:%d: bus-master DMA error: missing interrupt, "
 1809                     "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel,
drive, status);
error |= WDC_DMAST_NOIRQ;
 1812         }
 1814         if ((status & IDEDMA_CTL_ACT) != 0) {
 1815                 /* data underrun, may be a valid condition for ATAPI */
error |= WDC_DMAST_UNDER;
 1817         }
done:
sc->pciide_channels[channel].dma_in_progress = 0;
 1821         return (error);
 1822 }
 1824 void
pciide_irqack(struct channel_softc *chp)
 1826 {
 1827         struct pciide_channel *cp = (struct pciide_channel *)chp;
 1828         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 1829         int chan = chp->channel;
 1831         /* clear status bits in IDE DMA registers */
PCIIDE_DMACTL_WRITE(sc, chan, PCIIDE_DMACTL_READ(sc, chan));
 1833 }
 1835 /* some common code used by several chip_map */
 1836 int
pciide_chansetup(struct pciide_softc *sc, int channel, pcireg_t interface)
 1838 {
 1839         struct pciide_channel *cp = &sc->pciide_channels[channel];
sc->wdc_chanarray[channel] = &cp->wdc_channel;
cp->name = PCIIDE_CHANNEL_NAME(channel);
cp->wdc_channel.channel = channel;
cp->wdc_channel.wdc = &sc->sc_wdcdev;
cp->wdc_channel.ch_queue =
malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT);
 1846         if (cp->wdc_channel.ch_queue == NULL) {
printf("%s: %s "
 1848                     "cannot allocate memory for command queue",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
 1850                 return (0);
 1851         }
cp->hw_ok = 1;
 1854         return (1);
 1855 }
 1857 /* some common code used by several chip channel_map */
 1858 void
pciide_mapchan(struct pci_attach_args *pa, struct pciide_channel *cp,
pcireg_t interface, bus_size_t *cmdsizep, bus_size_t *ctlsizep,
 1861     int (*pci_intr)(void *))
 1862 {
 1863         struct channel_softc *wdc_cp = &cp->wdc_channel;
 1865         if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel))
cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep,
pci_intr);
 1868         else
cp->hw_ok = pciide_mapregs_compat(pa, cp,
wdc_cp->channel, cmdsizep, ctlsizep);
 1871         if (cp->hw_ok == 0)
 1872                 return;
wdc_cp->data32iot = wdc_cp->cmd_iot;
wdc_cp->data32ioh = wdc_cp->cmd_ioh;
wdcattach(wdc_cp);
 1876 }
 1878 /*
 1879  * Generic code to call to know if a channel can be disabled. Return 1
 1880  * if channel can be disabled, 0 if not
 1881  */
 1882 int
pciide_chan_candisable(struct pciide_channel *cp)
 1884 {
 1885         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 1886         struct channel_softc *wdc_cp = &cp->wdc_channel;
 1888         if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 &&
 1889             (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) {
printf("%s: %s disabled (no drives)\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
cp->hw_ok = 0;
 1893                 return (1);
 1894         }
 1895         return (0);
 1896 }
 1898 /*
 1899  * generic code to map the compat intr if hw_ok=1 and it is a compat channel.
 1900  * Set hw_ok=0 on failure
 1901  */
 1902 void
pciide_map_compat_intr(struct pci_attach_args *pa, struct pciide_channel *cp,
 1904     int compatchan, int interface)
 1905 {
 1906         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 1907         struct channel_softc *wdc_cp = &cp->wdc_channel;
 1909         if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0)
 1910                 return;
cp->compat = 1;
cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev,
pa, compatchan, pciide_compat_intr, cp);
 1915         if (cp->ih == NULL) {
printf("%s: no compatibility interrupt for use by %s\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
cp->hw_ok = 0;
 1919         }
 1920 }
 1922 /*
 1923  * generic code to unmap the compat intr if hw_ok=1 and it is a compat channel.
 1924  * Set hw_ok=0 on failure
 1925  */
 1926 void
pciide_unmap_compat_intr(struct pci_attach_args *pa, struct pciide_channel *cp,
 1928     int compatchan, int interface)
 1929 {
 1930         struct channel_softc *wdc_cp = &cp->wdc_channel;
 1932         if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0)
 1933                 return;
pciide_machdep_compat_intr_disestablish(pa->pa_pc, cp->ih);
 1936 }
 1938 void
pciide_print_channels(int nchannels, pcireg_t interface)
 1940 {
 1941         int i;
 1943         for (i = 0; i < nchannels; i++) {
printf(", %s %s to %s", PCIIDE_CHANNEL_NAME(i),
 1945                     (interface & PCIIDE_INTERFACE_SETTABLE(i)) ?
 1946                     "configured" : "wired",
 1947                     (interface & PCIIDE_INTERFACE_PCI(i)) ? "native-PCI" :
 1948                     "compatibility");
 1949         }
printf("\n");
 1952 }
 1954 void
pciide_print_modes(struct pciide_channel *cp)
 1956 {
wdc_print_current_modes(&cp->wdc_channel);
 1958 }
 1960 void
default_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
 1962 {
 1963         struct pciide_channel *cp;
pcireg_t interface = PCI_INTERFACE(pa->pa_class);
pcireg_t csr;
 1966         int channel, drive;
 1967         struct ata_drive_datas *drvp;
u_int8_t idedma_ctl;
bus_size_t cmdsize, ctlsize;
 1970         char *failreason;
 1972         if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) {
printf(": DMA");
 1974                 if (sc->sc_pp == &default_product_desc &&
 1975                     (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags &
PCIIDE_OPTIONS_DMA) == 0) {
printf(" (unsupported)");
sc->sc_dma_ok = 0;
 1979                 } else {
pciide_mapreg_dma(sc, pa);
 1981                         if (sc->sc_dma_ok != 0)
printf(", (partial support)");
 1983                 }
 1984         } else {
printf(": no DMA");
sc->sc_dma_ok = 0;
 1987         }
 1988         if (sc->sc_dma_ok) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK;
sc->sc_wdcdev.irqack = pciide_irqack;
 1991         }
sc->sc_wdcdev.PIO_cap = 0;
sc->sc_wdcdev.DMA_cap = 0;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16;
pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
 2000         for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
cp = &sc->pciide_channels[channel];
 2002                 if (pciide_chansetup(sc, channel, interface) == 0)
 2003                         continue;
 2004                 if (interface & PCIIDE_INTERFACE_PCI(channel)) {
cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize,
 2006                             &ctlsize, pciide_pci_intr);
 2007                 } else {
cp->hw_ok = pciide_mapregs_compat(pa, cp,
channel, &cmdsize, &ctlsize);
 2010                 }
 2011                 if (cp->hw_ok == 0)
 2012                         continue;
 2013                 /*
 2014                  * Check to see if something appears to be there.
 2015                  */
failreason = NULL;
pciide_map_compat_intr(pa, cp, channel, interface);
 2018                 if (cp->hw_ok == 0)
 2019                         continue;
 2020                 if (!wdcprobe(&cp->wdc_channel)) {
failreason = "not responding; disabled or no drives?";
 2022                         goto next;
 2023                 }
 2024                 /*
 2025                  * Now, make sure it's actually attributable to this PCI IDE
 2026                  * channel by trying to access the channel again while the
 2027                  * PCI IDE controller's I/O space is disabled.  (If the
 2028                  * channel no longer appears to be there, it belongs to
 2029                  * this controller.)  YUCK!
 2030                  */
csr = pci_conf_read(sc->sc_pc, sc->sc_tag,
PCI_COMMAND_STATUS_REG);
pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG,
csr & ~PCI_COMMAND_IO_ENABLE);
 2035                 if (wdcprobe(&cp->wdc_channel))
failreason = "other hardware responding at addresses";
pci_conf_write(sc->sc_pc, sc->sc_tag,
PCI_COMMAND_STATUS_REG, csr);
next:
 2040                 if (failreason) {
printf("%s: %s ignored (%s)\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name,
failreason);
cp->hw_ok = 0;
pciide_unmap_compat_intr(pa, cp, channel, interface);
bus_space_unmap(cp->wdc_channel.cmd_iot,
cp->wdc_channel.cmd_ioh, cmdsize);
 2048                         if (interface & PCIIDE_INTERFACE_PCI(channel))
bus_space_unmap(cp->wdc_channel.ctl_iot,
cp->ctl_baseioh, ctlsize);
 2051                         else
bus_space_unmap(cp->wdc_channel.ctl_iot,
cp->wdc_channel.ctl_ioh, ctlsize);
 2054                 }
 2055                 if (cp->hw_ok) {
cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot;
cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh;
wdcattach(&cp->wdc_channel);
 2059                 }
 2060         }
 2062         if (sc->sc_dma_ok == 0)
 2063                 return;
 2065         /* Allocate DMA maps */
 2066         for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
idedma_ctl = 0;
cp = &sc->pciide_channels[channel];
 2069                 for (drive = 0; drive < 2; drive++) {
drvp = &cp->wdc_channel.ch_drive[drive];
 2071                         /* If no drive, skip */
 2072                         if ((drvp->drive_flags & DRIVE) == 0)
 2073                                 continue;
 2074                         if ((drvp->drive_flags & DRIVE_DMA) == 0)
 2075                                 continue;
 2076                         if (pciide_dma_table_setup(sc, channel, drive) != 0) {
 2077                                 /* Abort DMA setup */
printf("%s:%d:%d: cannot allocate DMA maps, "
 2079                                     "using PIO transfers\n",
sc->sc_wdcdev.sc_dev.dv_xname,
channel, drive);
drvp->drive_flags &= ~DRIVE_DMA;
 2083                         }
printf("%s:%d:%d: using DMA data transfers\n",
sc->sc_wdcdev.sc_dev.dv_xname,
channel, drive);
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
 2088                 }
 2089                 if (idedma_ctl != 0) {
 2090                         /* Add software bits in status register */
PCIIDE_DMACTL_WRITE(sc, channel, idedma_ctl);
 2092                 }
 2093         }
 2094 }
 2096 void
sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
 2098 {
 2099         struct pciide_channel *cp;
pcireg_t interface = PCI_INTERFACE(pa->pa_class);
 2101         int channel;
bus_size_t cmdsize, ctlsize;
 2104         if (interface == 0) {
WDCDEBUG_PRINT(("sata_chip_map interface == 0\n"),
DEBUG_PROBE);
interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
 2109         }
printf(": DMA");
pciide_mapreg_dma(sc, pa);
printf("\n");
 2115         if (sc->sc_dma_ok) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA |
WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK;
sc->sc_wdcdev.irqack = pciide_irqack;
 2119         }
sc->sc_wdcdev.PIO_cap = 4;
sc->sc_wdcdev.DMA_cap = 2;
sc->sc_wdcdev.UDMA_cap = 6;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
WDC_CAPABILITY_MODE | WDC_CAPABILITY_SATA;
sc->sc_wdcdev.set_modes = sata_setup_channel;
 2130         for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
cp = &sc->pciide_channels[channel];
 2132                 if (pciide_chansetup(sc, channel, interface) == 0)
 2133                         continue;
pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
pciide_pci_intr);
sata_setup_channel(&cp->wdc_channel);
 2137         }
 2138 }
 2140 void
sata_setup_channel(struct channel_softc *chp)
 2142 {
 2143         struct ata_drive_datas *drvp;
 2144         int drive;
u_int32_t idedma_ctl;
 2146         struct pciide_channel *cp = (struct pciide_channel *)chp;
 2147         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 2149         /* setup DMA if needed */
pciide_channel_dma_setup(cp);
idedma_ctl = 0;
 2154         for (drive = 0; drive < 2; drive++) {
drvp = &chp->ch_drive[drive];
 2156                 /* If no drive, skip */
 2157                 if ((drvp->drive_flags & DRIVE) == 0)
 2158                         continue;
 2159                 if (drvp->drive_flags & DRIVE_UDMA) {
 2160                         /* use Ultra/DMA */
drvp->drive_flags &= ~DRIVE_DMA;
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
 2163                 } else if (drvp->drive_flags & DRIVE_DMA) {
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
 2165                 }
 2166         }
 2168         /*
 2169          * Nothing to do to setup modes; it is meaningless in S-ATA
 2170          * (but many S-ATA drives still want to get the SET_FEATURE
 2171          * command).
 2172          */
 2173         if (idedma_ctl != 0) {
 2174                 /* Add software bits in status register */
PCIIDE_DMACTL_WRITE(sc, chp->channel, idedma_ctl);
 2176         }
pciide_print_modes(cp);
 2178 }
 2180 void
piix_timing_debug(struct pciide_softc *sc)
 2182 {
WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x",
pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)),
DEBUG_PROBE);
 2186         if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE &&
sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_ISA) {
WDCDEBUG_PRINT((", sidetim=0x%x",
pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)),
DEBUG_PROBE);
 2191                 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) {
WDCDEBUG_PRINT((", udamreg 0x%x",
pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)),
DEBUG_PROBE);
 2195                 }
 2196                 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6321ESB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CAM_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBL_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801GB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82372FB_IDE) {
WDCDEBUG_PRINT((", IDE_CONTROL 0x%x",
pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)),
DEBUG_PROBE);
 2215                 }
 2216         }
WDCDEBUG_PRINT(("\n"), DEBUG_PROBE);
 2218 }
 2220 void
piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
 2222 {
 2223         struct pciide_channel *cp;
 2224         int channel;
u_int32_t idetim;
bus_size_t cmdsize, ctlsize;
pcireg_t interface = PCI_INTERFACE(pa->pa_class);
printf(": DMA");
pciide_mapreg_dma(sc, pa);
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
WDC_CAPABILITY_MODE;
 2234         if (sc->sc_dma_ok) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK;
sc->sc_wdcdev.irqack = pciide_irqack;
 2237                 switch (sc->sc_pp->ide_product) {
 2238                 case PCI_PRODUCT_INTEL_6300ESB_IDE:
 2239                 case PCI_PRODUCT_INTEL_6321ESB_IDE:
 2240                 case PCI_PRODUCT_INTEL_82371AB_IDE:
 2241                 case PCI_PRODUCT_INTEL_82372FB_IDE:
 2242                 case PCI_PRODUCT_INTEL_82440MX_IDE:
 2243                 case PCI_PRODUCT_INTEL_82451NX:
 2244                 case PCI_PRODUCT_INTEL_82801AA_IDE:
 2245                 case PCI_PRODUCT_INTEL_82801AB_IDE:
 2246                 case PCI_PRODUCT_INTEL_82801BAM_IDE:
 2247                 case PCI_PRODUCT_INTEL_82801BA_IDE:
 2248                 case PCI_PRODUCT_INTEL_82801CAM_IDE:
 2249                 case PCI_PRODUCT_INTEL_82801CA_IDE:
 2250                 case PCI_PRODUCT_INTEL_82801DB_IDE:
 2251                 case PCI_PRODUCT_INTEL_82801DBL_IDE:
 2252                 case PCI_PRODUCT_INTEL_82801DBM_IDE:
 2253                 case PCI_PRODUCT_INTEL_82801EB_IDE:
 2254                 case PCI_PRODUCT_INTEL_82801FB_IDE:
 2255                 case PCI_PRODUCT_INTEL_82801GB_IDE:
 2256                 case PCI_PRODUCT_INTEL_82801HBM_IDE:
sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
 2258                         break;
 2259                 }
 2260         }
sc->sc_wdcdev.PIO_cap = 4;
sc->sc_wdcdev.DMA_cap = 2;
 2263         switch (sc->sc_pp->ide_product) {
 2264         case PCI_PRODUCT_INTEL_82801AA_IDE:
 2265         case PCI_PRODUCT_INTEL_82372FB_IDE:
sc->sc_wdcdev.UDMA_cap = 4;
 2267                 break;
 2268         case PCI_PRODUCT_INTEL_6300ESB_IDE:
 2269         case PCI_PRODUCT_INTEL_6321ESB_IDE:
 2270         case PCI_PRODUCT_INTEL_82801BAM_IDE:
 2271         case PCI_PRODUCT_INTEL_82801BA_IDE:
 2272         case PCI_PRODUCT_INTEL_82801CAM_IDE:
 2273         case PCI_PRODUCT_INTEL_82801CA_IDE:
 2274         case PCI_PRODUCT_INTEL_82801DB_IDE:
 2275         case PCI_PRODUCT_INTEL_82801DBL_IDE:
 2276         case PCI_PRODUCT_INTEL_82801DBM_IDE:
 2277         case PCI_PRODUCT_INTEL_82801EB_IDE:
 2278         case PCI_PRODUCT_INTEL_82801FB_IDE:
 2279         case PCI_PRODUCT_INTEL_82801GB_IDE:
 2280         case PCI_PRODUCT_INTEL_82801HBM_IDE:
sc->sc_wdcdev.UDMA_cap = 5;
 2282                 break;
 2283         default:
sc->sc_wdcdev.UDMA_cap = 2;
 2285                 break;
 2286         }
 2288         if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_ISA) {
sc->sc_wdcdev.set_modes = piix_setup_channel;
 2291         } else {
sc->sc_wdcdev.set_modes = piix3_4_setup_channel;
 2293         }
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
piix_timing_debug(sc);
 2301         for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
cp = &sc->pciide_channels[channel];
 2304                 /* PIIX is compat-only */
 2305                 if (pciide_chansetup(sc, channel, 0) == 0)
 2306                         continue;
idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM);
 2308                 if ((PIIX_IDETIM_READ(idetim, channel) &
PIIX_IDETIM_IDE) == 0) {
printf("%s: %s ignored (disabled)\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
 2312                         continue;
 2313                 }
 2314                 /* PIIX are compat-only pciide devices */
pciide_map_compat_intr(pa, cp, channel, 0);
 2316                 if (cp->hw_ok == 0)
 2317                         continue;
pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr);
 2319                 if (cp->hw_ok == 0)
 2320                         goto next;
 2321                 if (pciide_chan_candisable(cp)) {
idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE,
channel);
pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM,
idetim);
 2326                 }
 2327                 if (cp->hw_ok == 0)
 2328                         goto next;
sc->sc_wdcdev.set_modes(&cp->wdc_channel);
next:
 2331                 if (cp->hw_ok == 0)
pciide_unmap_compat_intr(pa, cp, channel, 0);
 2333         }
piix_timing_debug(sc);
 2336 }
 2338 void
piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
 2340 {
 2341         struct pciide_channel *cp;
pcireg_t interface = PCI_INTERFACE(pa->pa_class);
 2343         int channel;
bus_size_t cmdsize, ctlsize;
u_int8_t reg, ich = 0;
printf(": DMA");
pciide_mapreg_dma(sc, pa);
 2350         if (sc->sc_dma_ok) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA |
WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK;
sc->sc_wdcdev.irqack = pciide_irqack;
sc->sc_wdcdev.DMA_cap = 2;
sc->sc_wdcdev.UDMA_cap = 6;
 2356         }
sc->sc_wdcdev.PIO_cap = 4;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
WDC_CAPABILITY_MODE | WDC_CAPABILITY_SATA;
sc->sc_wdcdev.set_modes = sata_setup_channel;
 2365         switch(sc->sc_pp->ide_product) {
 2366         case PCI_PRODUCT_INTEL_6300ESB_SATA:
 2367         case PCI_PRODUCT_INTEL_6300ESB_SATA2:
 2368         case PCI_PRODUCT_INTEL_82801EB_SATA:
 2369         case PCI_PRODUCT_INTEL_82801ER_SATA:
ich = 5;
 2371                 break;
 2372         case PCI_PRODUCT_INTEL_82801FB_SATA:
 2373         case PCI_PRODUCT_INTEL_82801FR_SATA:
 2374         case PCI_PRODUCT_INTEL_82801FBM_SATA:
ich = 6;
 2376                 break;
 2377         default:
ich = 7;
 2379                 break;
 2380         }
 2382         /*
 2383          * Put the SATA portion of controllers that don't operate in combined
 2384          * mode into native PCI modes so the maximum number of devices can be
 2385          * used.  Intel calls this "enhanced mode"
 2386          */
 2387         if (ich == 5) {
reg = pciide_pci_read(sc->sc_pc, sc->sc_tag, ICH5_SATA_MAP);
 2389                 if ((reg & ICH5_SATA_MAP_COMBINED) == 0) {
reg = pciide_pci_read(pa->pa_pc, pa->pa_tag,
ICH5_SATA_PI);
reg |= ICH5_SATA_PI_PRI_NATIVE |
ICH5_SATA_PI_SEC_NATIVE;
pciide_pci_write(pa->pa_pc, pa->pa_tag,
ICH5_SATA_PI, reg);
interface |= PCIIDE_INTERFACE_PCI(0) |
PCIIDE_INTERFACE_PCI(1);
 2398                 }
 2399         } else {
reg = pciide_pci_read(sc->sc_pc, sc->sc_tag, ICH5_SATA_MAP) &
ICH6_SATA_MAP_CMB_MASK;
 2402                 if (reg != ICH6_SATA_MAP_CMB_PRI &&
reg != ICH6_SATA_MAP_CMB_SEC) {
reg = pciide_pci_read(pa->pa_pc, pa->pa_tag,
ICH5_SATA_PI);
reg |= ICH5_SATA_PI_PRI_NATIVE |
ICH5_SATA_PI_SEC_NATIVE;
pciide_pci_write(pa->pa_pc, pa->pa_tag,
ICH5_SATA_PI, reg);
interface |= PCIIDE_INTERFACE_PCI(0) |
PCIIDE_INTERFACE_PCI(1);
 2414                         /*
 2415                          * Ask for SATA IDE Mode, we don't need to do this
 2416                          * for the combined mode case as combined mode is
 2417                          * only allowed in IDE Mode
 2418                          */
 2419                         if (ich >= 7) {
reg = pciide_pci_read(sc->sc_pc, sc->sc_tag,
ICH5_SATA_MAP) & ~ICH7_SATA_MAP_SMS_MASK;
pciide_pci_write(pa->pa_pc, pa->pa_tag,
ICH5_SATA_MAP, reg);
 2424                         }
 2425                 }
 2426         }
pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
 2430         for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
cp = &sc->pciide_channels[channel];
 2432                 if (pciide_chansetup(sc, channel, interface) == 0)
 2433                         continue;
pciide_map_compat_intr(pa, cp, channel, interface);
 2436                 if (cp->hw_ok == 0)
 2437                         continue;
pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
pciide_pci_intr);
 2441                 if (cp->hw_ok != 0)
sc->sc_wdcdev.set_modes(&cp->wdc_channel);
 2444                 if (cp->hw_ok == 0)
pciide_unmap_compat_intr(pa, cp, channel, interface);
 2446         }
 2447 }
 2449 void
piix_setup_channel(struct channel_softc *chp)
 2451 {
u_int8_t mode[2], drive;
u_int32_t oidetim, idetim, idedma_ctl;
 2454         struct pciide_channel *cp = (struct pciide_channel *)chp;
 2455         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 2456         struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive;
oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM);
idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel);
idedma_ctl = 0;
 2462         /* set up new idetim: Enable IDE registers decode */
idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE,
chp->channel);
 2466         /* setup DMA */
pciide_channel_dma_setup(cp);
 2469         /*
 2470          * Here we have to mess up with drives mode: PIIX can't have
 2471          * different timings for master and slave drives.
 2472          * We need to find the best combination.
 2473          */
 2475         /* If both drives supports DMA, take the lower mode */
 2476         if ((drvp[0].drive_flags & DRIVE_DMA) &&
 2477             (drvp[1].drive_flags & DRIVE_DMA)) {
mode[0] = mode[1] =
min(drvp[0].DMA_mode, drvp[1].DMA_mode);
drvp[0].DMA_mode = mode[0];
drvp[1].DMA_mode = mode[1];
 2482                 goto ok;
 2483         }
 2484         /*
 2485          * If only one drive supports DMA, use its mode, and
 2486          * put the other one in PIO mode 0 if mode not compatible
 2487          */
 2488         if (drvp[0].drive_flags & DRIVE_DMA) {
mode[0] = drvp[0].DMA_mode;
mode[1] = drvp[1].PIO_mode;
 2491                 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] ||
piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]])
mode[1] = drvp[1].PIO_mode = 0;
 2494                 goto ok;
 2495         }
 2496         if (drvp[1].drive_flags & DRIVE_DMA) {
mode[1] = drvp[1].DMA_mode;
mode[0] = drvp[0].PIO_mode;
 2499                 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] ||
piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]])
mode[0] = drvp[0].PIO_mode = 0;
 2502                 goto ok;
 2503         }
 2504         /*
 2505          * If both drives are not DMA, takes the lower mode, unless
 2506          * one of them is PIO mode < 2
 2507          */
 2508         if (drvp[0].PIO_mode < 2) {
mode[0] = drvp[0].PIO_mode = 0;
mode[1] = drvp[1].PIO_mode;
 2511         } else if (drvp[1].PIO_mode < 2) {
mode[1] = drvp[1].PIO_mode = 0;
mode[0] = drvp[0].PIO_mode;
 2514         } else {
mode[0] = mode[1] =
min(drvp[1].PIO_mode, drvp[0].PIO_mode);
drvp[0].PIO_mode = mode[0];
drvp[1].PIO_mode = mode[1];
 2519         }
ok:     /* The modes are setup */
 2521         for (drive = 0; drive < 2; drive++) {
 2522                 if (drvp[drive].drive_flags & DRIVE_DMA) {
idetim |= piix_setup_idetim_timings(
mode[drive], 1, chp->channel);
 2525                         goto end;
 2526                 }
 2527         }
 2528         /* If we are there, none of the drives are DMA */
 2529         if (mode[0] >= 2)
idetim |= piix_setup_idetim_timings(
mode[0], 0, chp->channel);
 2532         else
idetim |= piix_setup_idetim_timings(
mode[1], 0, chp->channel);
end:    /*
 2536          * timing mode is now set up in the controller. Enable
 2537          * it per-drive
 2538          */
 2539         for (drive = 0; drive < 2; drive++) {
 2540                 /* If no drive, skip */
 2541                 if ((drvp[drive].drive_flags & DRIVE) == 0)
 2542                         continue;
idetim |= piix_setup_idetim_drvs(&drvp[drive]);
 2544                 if (drvp[drive].drive_flags & DRIVE_DMA)
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
 2546         }
 2547         if (idedma_ctl != 0) {
 2548                 /* Add software bits in status register */
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CTL(chp->channel),
idedma_ctl);
 2552         }
pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim);
pciide_print_modes(cp);
 2555 }
 2557 void
piix3_4_setup_channel(struct channel_softc *chp)
 2559 {
 2560         struct ata_drive_datas *drvp;
u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl;
 2562         struct pciide_channel *cp = (struct pciide_channel *)chp;
 2563         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 2564         int drive;
 2565         int channel = chp->channel;
oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM);
sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM);
udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG);
ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG);
idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel);
sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) |
PIIX_SIDETIM_RTC_MASK(channel));
idedma_ctl = 0;
 2576         /* If channel disabled, no need to go further */
 2577         if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0)
 2578                 return;
 2579         /* set up new idetim: Enable IDE registers decode */
idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel);
 2582         /* setup DMA if needed */
pciide_channel_dma_setup(cp);
 2585         for (drive = 0; drive < 2; drive++) {
udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) |
PIIX_UDMATIM_SET(0x3, channel, drive));
drvp = &chp->ch_drive[drive];
 2589                 /* If no drive, skip */
 2590                 if ((drvp->drive_flags & DRIVE) == 0)
 2591                         continue;
 2592                 if (((drvp->drive_flags & DRIVE_DMA) == 0 &&
 2593                     (drvp->drive_flags & DRIVE_UDMA) == 0))
 2594                         goto pio;
 2596                 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6321ESB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CAM_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBL_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801GB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82372FB_IDE) {
ideconf |= PIIX_CONFIG_PINGPONG;
 2613                 }
 2614                 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6321ESB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CAM_IDE||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBL_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801GB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) {
 2627                         /* setup Ultra/100 */
 2628                         if (drvp->UDMA_mode > 2 &&
 2629                             (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0)
drvp->UDMA_mode = 2;
 2631                         if (drvp->UDMA_mode > 4) {
ideconf |= PIIX_CONFIG_UDMA100(channel, drive);
 2633                         } else {
ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive);
 2635                                 if (drvp->UDMA_mode > 2) {
ideconf |= PIIX_CONFIG_UDMA66(channel,
drive);
 2638                                 } else {
ideconf &= ~PIIX_CONFIG_UDMA66(channel,
drive);
 2641                                 }
 2642                         }
 2643                 }
 2644                 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82372FB_IDE) {
 2646                         /* setup Ultra/66 */
 2647                         if (drvp->UDMA_mode > 2 &&
 2648                             (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0)
drvp->UDMA_mode = 2;
 2650                         if (drvp->UDMA_mode > 2)
ideconf |= PIIX_CONFIG_UDMA66(channel, drive);
 2652                         else
ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive);
 2654                 }
 2656                 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) &&
 2657                     (drvp->drive_flags & DRIVE_UDMA)) {
 2658                         /* use Ultra/DMA */
drvp->drive_flags &= ~DRIVE_DMA;
udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive);
udmareg |= PIIX_UDMATIM_SET(
piix4_sct_udma[drvp->UDMA_mode], channel, drive);
 2663                 } else {
 2664                         /* use Multiword DMA */
drvp->drive_flags &= ~DRIVE_UDMA;
 2666                         if (drive == 0) {
idetim |= piix_setup_idetim_timings(
drvp->DMA_mode, 1, channel);
 2669                         } else {
sidetim |= piix_setup_sidetim_timings(
drvp->DMA_mode, 1, channel);
idetim =PIIX_IDETIM_SET(idetim,
PIIX_IDETIM_SITRE, channel);
 2674                         }
 2675                 }
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
pio:            /* use PIO mode */
idetim |= piix_setup_idetim_drvs(drvp);
 2680                 if (drive == 0) {
idetim |= piix_setup_idetim_timings(
drvp->PIO_mode, 0, channel);
 2683                 } else {
sidetim |= piix_setup_sidetim_timings(
drvp->PIO_mode, 0, channel);
idetim =PIIX_IDETIM_SET(idetim,
PIIX_IDETIM_SITRE, channel);
 2688                 }
 2689         }
 2690         if (idedma_ctl != 0) {
 2691                 /* Add software bits in status register */
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CTL(channel),
idedma_ctl);
 2695         }
pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim);
pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim);
pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg);
pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf);
pciide_print_modes(cp);
 2701 }
 2704 /* setup ISP and RTC fields, based on mode */
 2705 static u_int32_t
piix_setup_idetim_timings(u_int8_t mode, u_int8_t dma, u_int8_t channel)
 2707 {
 2709         if (dma)
 2710                 return (PIIX_IDETIM_SET(0,
PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) |
PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]),
channel));
 2714         else
 2715                 return (PIIX_IDETIM_SET(0,
PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) |
PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]),
channel));
 2719 }
 2721 /* setup DTE, PPE, IE and TIME field based on PIO mode */
 2722 static u_int32_t
piix_setup_idetim_drvs(struct ata_drive_datas *drvp)
 2724 {
u_int32_t ret = 0;
 2726         struct channel_softc *chp = drvp->chnl_softc;
u_int8_t channel = chp->channel;
u_int8_t drive = drvp->drive;
 2730         /*
 2731          * If drive is using UDMA, timings setups are independant
 2732          * So just check DMA and PIO here.
 2733          */
 2734         if (drvp->drive_flags & DRIVE_DMA) {
 2735                 /* if mode = DMA mode 0, use compatible timings */
 2736                 if ((drvp->drive_flags & DRIVE_DMA) &&
drvp->DMA_mode == 0) {
drvp->PIO_mode = 0;
 2739                         return (ret);
 2740                 }
ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel);
 2742                 /*
 2743                  * PIO and DMA timings are the same, use fast timings for PIO
 2744                  * too, else use compat timings.
 2745                  */
 2746                 if ((piix_isp_pio[drvp->PIO_mode] !=
piix_isp_dma[drvp->DMA_mode]) ||
 2748                     (piix_rtc_pio[drvp->PIO_mode] !=
piix_rtc_dma[drvp->DMA_mode]))
drvp->PIO_mode = 0;
 2751                 /* if PIO mode <= 2, use compat timings for PIO */
 2752                 if (drvp->PIO_mode <= 2) {
ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive),
channel);
 2755                         return (ret);
 2756                 }
 2757         }
 2759         /*
 2760          * Now setup PIO modes. If mode < 2, use compat timings.
 2761          * Else enable fast timings. Enable IORDY and prefetch/post
 2762          * if PIO mode >= 3.
 2763          */
 2765         if (drvp->PIO_mode < 2)
 2766                 return (ret);
ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel);
 2769         if (drvp->PIO_mode >= 3) {
ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel);
ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel);
 2772         }
 2773         return (ret);
 2774 }
 2776 /* setup values in SIDETIM registers, based on mode */
 2777 static u_int32_t
piix_setup_sidetim_timings(u_int8_t mode, u_int8_t dma, u_int8_t channel)
 2779 {
 2780         if (dma)
 2781                 return (PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) |
PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel));
 2783         else
 2784                 return (PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) |
PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel));
 2786 }
 2788 void
amd756_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
 2790 {
 2791         struct pciide_channel *cp;
pcireg_t interface = PCI_INTERFACE(pa->pa_class);
 2793         int channel;
pcireg_t chanenable;
bus_size_t cmdsize, ctlsize;
printf(": DMA");
pciide_mapreg_dma(sc, pa);
sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
WDC_CAPABILITY_MODE;
 2801         if (sc->sc_dma_ok) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
sc->sc_wdcdev.irqack = pciide_irqack;
 2805         }
sc->sc_wdcdev.PIO_cap = 4;
sc->sc_wdcdev.DMA_cap = 2;
 2808         switch (sc->sc_pp->ide_product) {
 2809         case PCI_PRODUCT_AMD_8111_IDE:
sc->sc_wdcdev.UDMA_cap = 6;
 2811                 break;
 2812         case PCI_PRODUCT_AMD_766_IDE:
 2813         case PCI_PRODUCT_AMD_PBC768_IDE:
sc->sc_wdcdev.UDMA_cap = 5;
 2815                 break;
 2816         default:
sc->sc_wdcdev.UDMA_cap = 4;
 2818                 break;
 2819         }
sc->sc_wdcdev.set_modes = amd756_setup_channel;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN);
pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
 2827         for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
cp = &sc->pciide_channels[channel];
 2829                 if (pciide_chansetup(sc, channel, interface) == 0)
 2830                         continue;
 2832                 if ((chanenable & AMD756_CHAN_EN(channel)) == 0) {
printf("%s: %s ignored (disabled)\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
 2835                         continue;
 2836                 }
pciide_map_compat_intr(pa, cp, channel, interface);
 2838                 if (cp->hw_ok == 0)
 2839                         continue;
pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
pciide_pci_intr);
 2844                 if (pciide_chan_candisable(cp)) {
chanenable &= ~AMD756_CHAN_EN(channel);
 2846                 }
 2847                 if (cp->hw_ok == 0) {
pciide_unmap_compat_intr(pa, cp, channel, interface);
 2849                         continue;
 2850                 }
amd756_setup_channel(&cp->wdc_channel);
 2853         }
pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN,
chanenable);
 2856         return;
 2857 }
 2859 void
amd756_setup_channel(struct channel_softc *chp)
 2861 {
u_int32_t udmatim_reg, datatim_reg;
u_int8_t idedma_ctl;
 2864         int mode, drive;
 2865         struct ata_drive_datas *drvp;
 2866         struct pciide_channel *cp = (struct pciide_channel *)chp;
 2867         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
pcireg_t chanenable;
 2869 #ifndef PCIIDE_AMD756_ENABLEDMA
 2870         int product = sc->sc_pp->ide_product;
 2871         int rev = sc->sc_rev;
 2872 #endif
idedma_ctl = 0;
datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_DATATIM);
udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_UDMA);
datatim_reg &= ~AMD756_DATATIM_MASK(chp->channel);
udmatim_reg &= ~AMD756_UDMA_MASK(chp->channel);
chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag,
AMD756_CHANSTATUS_EN);
 2882         /* setup DMA if needed */
pciide_channel_dma_setup(cp);
 2885         for (drive = 0; drive < 2; drive++) {
drvp = &chp->ch_drive[drive];
 2887                 /* If no drive, skip */
 2888                 if ((drvp->drive_flags & DRIVE) == 0)
 2889                         continue;
 2890                 /* add timing values, setup DMA if needed */
 2891                 if (((drvp->drive_flags & DRIVE_DMA) == 0 &&
 2892                     (drvp->drive_flags & DRIVE_UDMA) == 0)) {
mode = drvp->PIO_mode;
 2894                         goto pio;
 2895                 }
 2896                 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) &&
 2897                     (drvp->drive_flags & DRIVE_UDMA)) {
 2898                         /* use Ultra/DMA */
drvp->drive_flags &= ~DRIVE_DMA;
 2901                         /* Check cable */
 2902                         if ((chanenable & AMD756_CABLE(chp->channel,
drive)) == 0 && drvp->UDMA_mode > 2) {
WDCDEBUG_PRINT(("%s(%s:%d:%d): 80-wire "
 2905                                     "cable not detected\n", drvp->drive_name,
sc->sc_wdcdev.sc_dev.dv_xname,
chp->channel, drive), DEBUG_PROBE);
drvp->UDMA_mode = 2;
 2909                         }
udmatim_reg |= AMD756_UDMA_EN(chp->channel, drive) |
AMD756_UDMA_EN_MTH(chp->channel, drive) |
AMD756_UDMA_TIME(chp->channel, drive,
amd756_udma_tim[drvp->UDMA_mode]);
 2915                         /* can use PIO timings, MW DMA unused */
mode = drvp->PIO_mode;
 2917                 } else {
 2918                         /* use Multiword DMA, but only if revision is OK */
drvp->drive_flags &= ~DRIVE_UDMA;
 2920 #ifndef PCIIDE_AMD756_ENABLEDMA
 2921                         /*
 2922                          * The workaround doesn't seem to be necessary
 2923                          * with all drives, so it can be disabled by
 2924                          * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if
 2925                          * triggered.
 2926                          */
 2927                         if (AMD756_CHIPREV_DISABLEDMA(product, rev)) {
printf("%s:%d:%d: multi-word DMA disabled due "
 2929                                     "to chip revision\n",
sc->sc_wdcdev.sc_dev.dv_xname,
chp->channel, drive);
mode = drvp->PIO_mode;
drvp->drive_flags &= ~DRIVE_DMA;
 2934                                 goto pio;
 2935                         }
 2936 #endif
 2937                         /* mode = min(pio, dma+2) */
 2938                         if (drvp->PIO_mode <= (drvp->DMA_mode +2))
mode = drvp->PIO_mode;
 2940                         else
mode = drvp->DMA_mode + 2;
 2942                 }
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
pio:            /* setup PIO mode */
 2946                 if (mode <= 2) {
drvp->DMA_mode = 0;
drvp->PIO_mode = 0;
mode = 0;
 2950                 } else {
drvp->PIO_mode = mode;
drvp->DMA_mode = mode - 2;
 2953                 }
datatim_reg |=
AMD756_DATATIM_PULSE(chp->channel, drive,
amd756_pio_set[mode]) |
AMD756_DATATIM_RECOV(chp->channel, drive,
amd756_pio_rec[mode]);
 2959         }
 2960         if (idedma_ctl != 0) {
 2961                 /* Add software bits in status register */
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CTL(chp->channel),
idedma_ctl);
 2965         }
pciide_print_modes(cp);
pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_DATATIM, datatim_reg);
pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_UDMA, udmatim_reg);
 2969 }
 2971 void
apollo_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
 2973 {
 2974         struct pciide_channel *cp;
pcireg_t interface;
 2976         int channel;
u_int32_t ideconf;
bus_size_t cmdsize, ctlsize;
pcitag_t tag;
pcireg_t id, class;
 2982         /*
 2983          * Fake interface since VT6410 is claimed to be a ``RAID'' device.
 2984          */
 2985         if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) {
interface = PCI_INTERFACE(pa->pa_class);
 2987         } else {
interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
 2990         }
 2992         if ((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_VIATECH_VT6410) ||
 2993             (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_VIATECH_CX700_IDE)) { 
printf(": ATA133");
sc->sc_wdcdev.UDMA_cap = 6;
 2996         } else {
 2997                 /* 
 2998                  * Determine the DMA capabilities by looking at the
 2999                  * ISA bridge.
 3000                  */
tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0);
id = pci_conf_read(sc->sc_pc, tag, PCI_ID_REG);
class = pci_conf_read(sc->sc_pc, tag, PCI_CLASS_REG);
 3005                 /*
 3006                  * XXX On the VT8237, the ISA bridge is on a different
 3007                  * device.
 3008                  */
 3009                 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE &&
pa->pa_device == 15) {
tag = pci_make_tag(pa->pa_pc, pa->pa_bus, 17, 0);
id = pci_conf_read(sc->sc_pc, tag, PCI_ID_REG);
class = pci_conf_read(sc->sc_pc, tag, PCI_CLASS_REG);
 3014                 }
 3016                 switch (PCI_PRODUCT(id)) {
 3017                 case PCI_PRODUCT_VIATECH_VT82C586_ISA:
 3018                         if (PCI_REVISION(class) >= 0x02) {
printf(": ATA33");
sc->sc_wdcdev.UDMA_cap = 2;
 3021                         } else {
printf(": DMA");
sc->sc_wdcdev.UDMA_cap = 0;
 3024                         }
 3025                         break;
 3026                 case PCI_PRODUCT_VIATECH_VT82C596A:
 3027                         if (PCI_REVISION(class) >= 0x12) {
printf(": ATA66");
sc->sc_wdcdev.UDMA_cap = 4;
 3030                         } else {
printf(": ATA33");
sc->sc_wdcdev.UDMA_cap = 2;
 3033                         }
 3034                         break;
 3036                 case PCI_PRODUCT_VIATECH_VT82C686A_ISA:
 3037                         if (PCI_REVISION(class) >= 0x40) {
printf(": ATA100");
sc->sc_wdcdev.UDMA_cap = 5;
 3040                         } else {
printf(": ATA66");
sc->sc_wdcdev.UDMA_cap = 4;
 3043                         }
 3044                         break;
 3045                 case PCI_PRODUCT_VIATECH_VT8231_ISA:
 3046                 case PCI_PRODUCT_VIATECH_VT8233_ISA:
printf(": ATA100");
sc->sc_wdcdev.UDMA_cap = 5;
 3049                         break;
 3050                 case PCI_PRODUCT_VIATECH_VT8233A_ISA:
 3051                 case PCI_PRODUCT_VIATECH_VT8235_ISA:
 3052                 case PCI_PRODUCT_VIATECH_VT8237_ISA:
printf(": ATA133");
sc->sc_wdcdev.UDMA_cap = 6;
 3055                         break;
 3056                 default:
printf(": DMA");
sc->sc_wdcdev.UDMA_cap = 0;
 3059                         break;
 3060                 }
 3061         }
pciide_mapreg_dma(sc, pa);
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
WDC_CAPABILITY_MODE;
 3066         if (sc->sc_dma_ok) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK;
sc->sc_wdcdev.irqack = pciide_irqack;
 3069                 if (sc->sc_wdcdev.UDMA_cap > 0)
sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
 3071         }
sc->sc_wdcdev.PIO_cap = 4;
sc->sc_wdcdev.DMA_cap = 2;
sc->sc_wdcdev.set_modes = apollo_setup_channel;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, "
 3081             "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n",
pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF),
pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC),
pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM),
pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)),
DEBUG_PROBE);
 3088         for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
cp = &sc->pciide_channels[channel];
 3090                 if (pciide_chansetup(sc, channel, interface) == 0)
 3091                         continue;
ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF);
 3094                 if ((ideconf & APO_IDECONF_EN(channel)) == 0) {
printf("%s: %s ignored (disabled)\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
 3097                         continue;
 3098                 }
pciide_map_compat_intr(pa, cp, channel, interface);
 3100                 if (cp->hw_ok == 0)
 3101                         continue;
pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
pciide_pci_intr);
 3105                 if (cp->hw_ok == 0) {
 3106                         goto next;
 3107                 }
 3108                 if (pciide_chan_candisable(cp)) {
ideconf &= ~APO_IDECONF_EN(channel);
pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF,
ideconf);
 3112                 }
 3114                 if (cp->hw_ok == 0)
 3115                         goto next;
apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel);
next:
 3118                 if (cp->hw_ok == 0)
pciide_unmap_compat_intr(pa, cp, channel, interface);
 3120         }
WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n",
pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM),
pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE);
 3124 }
 3126 void
apollo_setup_channel(struct channel_softc *chp)
 3128 {
u_int32_t udmatim_reg, datatim_reg;
u_int8_t idedma_ctl;
 3131         int mode, drive;
 3132         struct ata_drive_datas *drvp;
 3133         struct pciide_channel *cp = (struct pciide_channel *)chp;
 3134         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
idedma_ctl = 0;
datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM);
udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA);
datatim_reg &= ~APO_DATATIM_MASK(chp->channel);
udmatim_reg &= ~APO_UDMA_MASK(chp->channel);
 3142         /* setup DMA if needed */
pciide_channel_dma_setup(cp);
 3145         /*
 3146          * We can't mix Ultra/33 and Ultra/66 on the same channel, so
 3147          * downgrade to Ultra/33 if needed
 3148          */
 3149         if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA) &&
 3150             (chp->ch_drive[1].drive_flags & DRIVE_UDMA)) {
 3151                 /* both drives UDMA */
 3152                 if (chp->ch_drive[0].UDMA_mode > 2 &&
chp->ch_drive[1].UDMA_mode <= 2) {
 3154                         /* drive 0 Ultra/66, drive 1 Ultra/33 */
chp->ch_drive[0].UDMA_mode = 2;
 3156                 } else if (chp->ch_drive[1].UDMA_mode > 2 &&
chp->ch_drive[0].UDMA_mode <= 2) {
 3158                         /* drive 1 Ultra/66, drive 0 Ultra/33 */
chp->ch_drive[1].UDMA_mode = 2;
 3160                 }
 3161         }
 3163         for (drive = 0; drive < 2; drive++) {
drvp = &chp->ch_drive[drive];
 3165                 /* If no drive, skip */
 3166                 if ((drvp->drive_flags & DRIVE) == 0)
 3167                         continue;
 3168                 /* add timing values, setup DMA if needed */
 3169                 if (((drvp->drive_flags & DRIVE_DMA) == 0 &&
 3170                     (drvp->drive_flags & DRIVE_UDMA) == 0)) {
mode = drvp->PIO_mode;
 3172                         goto pio;
 3173                 }
 3174                 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) &&
 3175                     (drvp->drive_flags & DRIVE_UDMA)) {
 3176                         /* use Ultra/DMA */
drvp->drive_flags &= ~DRIVE_DMA;
udmatim_reg |= APO_UDMA_EN(chp->channel, drive) |
APO_UDMA_EN_MTH(chp->channel, drive);
 3180                         if (sc->sc_wdcdev.UDMA_cap == 6) {
udmatim_reg |= APO_UDMA_TIME(chp->channel,
drive, apollo_udma133_tim[drvp->UDMA_mode]);
 3183                         } else if (sc->sc_wdcdev.UDMA_cap == 5) {
 3184                                 /* 686b */
udmatim_reg |= APO_UDMA_TIME(chp->channel,
drive, apollo_udma100_tim[drvp->UDMA_mode]);
 3187                         } else if (sc->sc_wdcdev.UDMA_cap == 4) {
 3188                                 /* 596b or 686a */
udmatim_reg |= APO_UDMA_CLK66(chp->channel);
udmatim_reg |= APO_UDMA_TIME(chp->channel,
drive, apollo_udma66_tim[drvp->UDMA_mode]);
 3192                         } else {
 3193                                 /* 596a or 586b */
udmatim_reg |= APO_UDMA_TIME(chp->channel,
drive, apollo_udma33_tim[drvp->UDMA_mode]);
 3196                         }
 3197                         /* can use PIO timings, MW DMA unused */
mode = drvp->PIO_mode;
 3199                 } else {
 3200                         /* use Multiword DMA */
drvp->drive_flags &= ~DRIVE_UDMA;
 3202                         /* mode = min(pio, dma+2) */
 3203                         if (drvp->PIO_mode <= (drvp->DMA_mode +2))
mode = drvp->PIO_mode;
 3205                         else
mode = drvp->DMA_mode + 2;
 3207                 }
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
pio:            /* setup PIO mode */
 3211                 if (mode <= 2) {
drvp->DMA_mode = 0;
drvp->PIO_mode = 0;
mode = 0;
 3215                 } else {
drvp->PIO_mode = mode;
drvp->DMA_mode = mode - 2;
 3218                 }
datatim_reg |=
APO_DATATIM_PULSE(chp->channel, drive,
apollo_pio_set[mode]) |
APO_DATATIM_RECOV(chp->channel, drive,
apollo_pio_rec[mode]);
 3224         }
 3225         if (idedma_ctl != 0) {
 3226                 /* Add software bits in status register */
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CTL(chp->channel),
idedma_ctl);
 3230         }
pciide_print_modes(cp);
pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg);
pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg);
 3234 }
 3236 void
cmd_channel_map(struct pci_attach_args *pa, struct pciide_softc *sc,
 3238     int channel)
 3239 {
 3240         struct pciide_channel *cp = &sc->pciide_channels[channel];
bus_size_t cmdsize, ctlsize;
u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL);
pcireg_t interface;
 3244         int one_channel;
 3246         /*
 3247          * The 0648/0649 can be told to identify as a RAID controller.
 3248          * In this case, we have to fake interface
 3249          */
 3250         if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) {
interface = PCIIDE_INTERFACE_SETTABLE(0) |
PCIIDE_INTERFACE_SETTABLE(1);
 3253                 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) &
CMD_CONF_DSA1)
interface |= PCIIDE_INTERFACE_PCI(0) |
PCIIDE_INTERFACE_PCI(1);
 3257         } else {
interface = PCI_INTERFACE(pa->pa_class);
 3259         }
sc->wdc_chanarray[channel] = &cp->wdc_channel;
cp->name = PCIIDE_CHANNEL_NAME(channel);
cp->wdc_channel.channel = channel;
cp->wdc_channel.wdc = &sc->sc_wdcdev;
 3266         /*
 3267          * Older CMD64X doesn't have independant channels
 3268          */
 3269         switch (sc->sc_pp->ide_product) {
 3270         case PCI_PRODUCT_CMDTECH_649:
one_channel = 0;
 3272                 break;
 3273         default:
one_channel = 1;
 3275                 break;
 3276         }
 3278         if (channel > 0 && one_channel) {
cp->wdc_channel.ch_queue =
sc->pciide_channels[0].wdc_channel.ch_queue;
 3281         } else {
cp->wdc_channel.ch_queue =
malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT);
 3284         }
 3285         if (cp->wdc_channel.ch_queue == NULL) {
printf(
 3287                     "%s: %s cannot allocate memory for command queue",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
 3289                 return;
 3290         }
 3292         /*
 3293          * with a CMD PCI64x, if we get here, the first channel is enabled:
 3294          * there's no way to disable the first channel without disabling
 3295          * the whole device
 3296          */
 3297          if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) {
printf("%s: %s ignored (disabled)\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
 3300                 return;
 3301         }
cp->hw_ok = 1;
pciide_map_compat_intr(pa, cp, channel, interface);
 3304         if (cp->hw_ok == 0)
 3305                 return;
pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr);
 3307         if (cp->hw_ok == 0) {
pciide_unmap_compat_intr(pa, cp, channel, interface);
 3309                 return;
 3310         }
 3311         if (pciide_chan_candisable(cp)) {
 3312                 if (channel == 1) {
ctrl &= ~CMD_CTRL_2PORT;
pciide_pci_write(pa->pa_pc, pa->pa_tag,
CMD_CTRL, ctrl);
pciide_unmap_compat_intr(pa, cp, channel, interface);
 3317                 }
 3318         }
 3319 }
 3321 int
cmd_pci_intr(void *arg)
 3323 {
 3324         struct pciide_softc *sc = arg;
 3325         struct pciide_channel *cp;
 3326         struct channel_softc *wdc_cp;
 3327         int i, rv, crv;
u_int32_t priirq, secirq;
rv = 0;
priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF);
secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23);
 3333         for (i = 0; i < sc->sc_wdcdev.nchannels; i++) {
cp = &sc->pciide_channels[i];
wdc_cp = &cp->wdc_channel;
 3336                 /* If a compat channel skip. */
 3337                 if (cp->compat)
 3338                         continue;
 3339                 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) ||
 3340                     (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) {
crv = wdcintr(wdc_cp);
 3342                         if (crv == 0) {
 3343 #if 0
printf("%s:%d: bogus intr\n",
sc->sc_wdcdev.sc_dev.dv_xname, i);
 3346 #endif
 3347                         } else
rv = 1;
 3349                 }
 3350         }
 3351         return (rv);
 3352 }
 3354 void
cmd_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
 3356 {
 3357         int channel;
pcireg_t interface = PCI_INTERFACE(pa->pa_class);
printf(": no DMA");
sc->sc_dma_ok = 0;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16;
pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
 3369         for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
cmd_channel_map(pa, sc, channel);
 3371         }
 3372 }
 3374 void
cmd0643_9_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
 3376 {
 3377         struct pciide_channel *cp;
 3378         int channel;
 3379         int rev = sc->sc_rev;
pcireg_t interface;
 3382         /*
 3383          * The 0648/0649 can be told to identify as a RAID controller.
 3384          * In this case, we have to fake interface
 3385          */
 3386         if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) {
interface = PCIIDE_INTERFACE_SETTABLE(0) |
PCIIDE_INTERFACE_SETTABLE(1);
 3389                 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) &
CMD_CONF_DSA1)
interface |= PCIIDE_INTERFACE_PCI(0) |
PCIIDE_INTERFACE_PCI(1);
 3393         } else {
interface = PCI_INTERFACE(pa->pa_class);
 3395         }
printf(": DMA");
pciide_mapreg_dma(sc, pa);
sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
WDC_CAPABILITY_MODE;
 3401         if (sc->sc_dma_ok) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK;
 3403                 switch (sc->sc_pp->ide_product) {
 3404                 case PCI_PRODUCT_CMDTECH_649:
sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
sc->sc_wdcdev.UDMA_cap = 5;
sc->sc_wdcdev.irqack = cmd646_9_irqack;
 3408                         break;
 3409                 case PCI_PRODUCT_CMDTECH_648:
sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
sc->sc_wdcdev.UDMA_cap = 4;
sc->sc_wdcdev.irqack = cmd646_9_irqack;
 3413                         break;
 3414                 case PCI_PRODUCT_CMDTECH_646:
 3415                         if (rev >= CMD0646U2_REV) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
sc->sc_wdcdev.UDMA_cap = 2;
 3418                         } else if (rev >= CMD0646U_REV) {
 3419                         /*
 3420                          * Linux's driver claims that the 646U is broken
 3421                          * with UDMA. Only enable it if we know what we're
 3422                          * doing
 3423                          */
 3424 #ifdef PCIIDE_CMD0646U_ENABLEUDMA
sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
sc->sc_wdcdev.UDMA_cap = 2;
 3427 #endif
 3428                                 /* explicitly disable UDMA */
pciide_pci_write(sc->sc_pc, sc->sc_tag,
CMD_UDMATIM(0), 0);
pciide_pci_write(sc->sc_pc, sc->sc_tag,
CMD_UDMATIM(1), 0);
 3433                         }
sc->sc_wdcdev.irqack = cmd646_9_irqack;
 3435                         break;
 3436                 default:
sc->sc_wdcdev.irqack = pciide_irqack;
 3438                 }
 3439         }
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
sc->sc_wdcdev.PIO_cap = 4;
sc->sc_wdcdev.DMA_cap = 2;
sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel;
pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n",
pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54),
pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)),
DEBUG_PROBE);
 3453         for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
cp = &sc->pciide_channels[channel];
cmd_channel_map(pa, sc, channel);
 3456                 if (cp->hw_ok == 0)
 3457                         continue;
cmd0643_9_setup_channel(&cp->wdc_channel);
 3459         }
 3460         /*
 3461          * note - this also makes sure we clear the irq disable and reset
 3462          * bits
 3463          */
pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE);
WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n",
pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54),
pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)),
DEBUG_PROBE);
 3469 }
 3471 void
cmd0643_9_setup_channel(struct channel_softc *chp)
 3473 {
 3474         struct ata_drive_datas *drvp;
u_int8_t tim;
u_int32_t idedma_ctl, udma_reg;
 3477         int drive;
 3478         struct pciide_channel *cp = (struct pciide_channel *)chp;
 3479         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
idedma_ctl = 0;
 3482         /* setup DMA if needed */
pciide_channel_dma_setup(cp);
 3485         for (drive = 0; drive < 2; drive++) {
drvp = &chp->ch_drive[drive];
 3487                 /* If no drive, skip */
 3488                 if ((drvp->drive_flags & DRIVE) == 0)
 3489                         continue;
 3490                 /* add timing values, setup DMA if needed */
tim = cmd0643_9_data_tim_pio[drvp->PIO_mode];
 3492                 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) {
 3493                         if (drvp->drive_flags & DRIVE_UDMA) {
 3494                                 /* UltraDMA on a 646U2, 0648 or 0649 */
drvp->drive_flags &= ~DRIVE_DMA;
udma_reg = pciide_pci_read(sc->sc_pc,
sc->sc_tag, CMD_UDMATIM(chp->channel));
 3498                                 if (drvp->UDMA_mode > 2 &&
 3499                                     (pciide_pci_read(sc->sc_pc, sc->sc_tag,
CMD_BICSR) &
CMD_BICSR_80(chp->channel)) == 0) {
WDCDEBUG_PRINT(("%s(%s:%d:%d): "
 3503                                             "80-wire cable not detected\n",
drvp->drive_name,
sc->sc_wdcdev.sc_dev.dv_xname,
chp->channel, drive), DEBUG_PROBE);
drvp->UDMA_mode = 2;
 3508                                 }
 3509                                 if (drvp->UDMA_mode > 2)
udma_reg &= ~CMD_UDMATIM_UDMA33(drive);
 3511                                 else if (sc->sc_wdcdev.UDMA_cap > 2)
udma_reg |= CMD_UDMATIM_UDMA33(drive);
udma_reg |= CMD_UDMATIM_UDMA(drive);
udma_reg &= ~(CMD_UDMATIM_TIM_MASK <<
CMD_UDMATIM_TIM_OFF(drive));
udma_reg |=
 3517                                     (cmd0646_9_tim_udma[drvp->UDMA_mode] <<
CMD_UDMATIM_TIM_OFF(drive));
pciide_pci_write(sc->sc_pc, sc->sc_tag,
CMD_UDMATIM(chp->channel), udma_reg);
 3521                         } else {
 3522                                 /*
 3523                                  * use Multiword DMA.
 3524                                  * Timings will be used for both PIO and DMA,
 3525                                  * so adjust DMA mode if needed
 3526                                  * if we have a 0646U2/8/9, turn off UDMA
 3527                                  */
 3528                                 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) {
udma_reg = pciide_pci_read(sc->sc_pc,
sc->sc_tag,
CMD_UDMATIM(chp->channel));
udma_reg &= ~CMD_UDMATIM_UDMA(drive);
pciide_pci_write(sc->sc_pc, sc->sc_tag,
CMD_UDMATIM(chp->channel),
udma_reg);
 3536                                 }
 3537                                 if (drvp->PIO_mode >= 3 &&
 3538                                     (drvp->DMA_mode + 2) > drvp->PIO_mode) {
drvp->DMA_mode = drvp->PIO_mode - 2;
 3540                                 }
tim = cmd0643_9_data_tim_dma[drvp->DMA_mode];
 3542                         }
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
 3544                 }
pciide_pci_write(sc->sc_pc, sc->sc_tag,
CMD_DATA_TIM(chp->channel, drive), tim);
 3547         }
 3548         if (idedma_ctl != 0) {
 3549                 /* Add software bits in status register */
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CTL(chp->channel),
idedma_ctl);
 3553         }
pciide_print_modes(cp);
 3555 #ifdef __sparc64__
 3556         /*
 3557          * The Ultra 5 has a tendency to hang during reboot.  This is due
 3558          * to the PCI0646U asserting a PCI interrupt line when the chip
 3559          * registers claim that it is not.  Performing a reset at this
 3560          * point appears to eliminate the symptoms.  It is likely the
 3561          * real cause is still lurking somewhere in the code.
 3562          */
wdcreset(chp, SILENT);
 3564 #endif /* __sparc64__ */
 3565 }
 3567 void
cmd646_9_irqack(struct channel_softc *chp)
 3569 {
u_int32_t priirq, secirq;
 3571         struct pciide_channel *cp = (struct pciide_channel *)chp;
 3572         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 3574         if (chp->channel == 0) {
priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF);
pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq);
 3577         } else {
secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23);
pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq);
 3580         }
pciide_irqack(chp);
 3582 }
 3584 void
cmd680_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
 3586 {
 3587         struct pciide_channel *cp;
 3588         int channel;
printf("\n%s: bus-master DMA support present",
sc->sc_wdcdev.sc_dev.dv_xname);
pciide_mapreg_dma(sc, pa);
printf("\n");
sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
WDC_CAPABILITY_MODE;
 3596         if (sc->sc_dma_ok) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK;
sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
sc->sc_wdcdev.UDMA_cap = 6;
sc->sc_wdcdev.irqack = pciide_irqack;
 3601         }
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
sc->sc_wdcdev.PIO_cap = 4;
sc->sc_wdcdev.DMA_cap = 2;
sc->sc_wdcdev.set_modes = cmd680_setup_channel;
pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x80, 0x00);
pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x84, 0x00);
pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x8a,
pciide_pci_read(sc->sc_pc, sc->sc_tag, 0x8a) | 0x01);
 3613         for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
cp = &sc->pciide_channels[channel];
cmd680_channel_map(pa, sc, channel);
 3616                 if (cp->hw_ok == 0)
 3617                         continue;
cmd680_setup_channel(&cp->wdc_channel);
 3619         }
 3620 }
 3622 void
cmd680_channel_map(struct pci_attach_args *pa, struct pciide_softc *sc,
 3624     int channel)
 3625 {
 3626         struct pciide_channel *cp = &sc->pciide_channels[channel];
bus_size_t cmdsize, ctlsize;
 3628         int interface, i, reg;
 3629         static const u_int8_t init_val[] =
 3630             {             0x8a, 0x32, 0x8a, 0x32, 0x8a, 0x32,
 3631               0x92, 0x43, 0x92, 0x43, 0x09, 0x40, 0x09, 0x40 };
 3633         if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) {
interface = PCIIDE_INTERFACE_SETTABLE(0) |
PCIIDE_INTERFACE_SETTABLE(1);
interface |= PCIIDE_INTERFACE_PCI(0) |
PCIIDE_INTERFACE_PCI(1);
 3638         } else {
interface = PCI_INTERFACE(pa->pa_class);
 3640         }
sc->wdc_chanarray[channel] = &cp->wdc_channel;
cp->name = PCIIDE_CHANNEL_NAME(channel);
cp->wdc_channel.channel = channel;
cp->wdc_channel.wdc = &sc->sc_wdcdev;
cp->wdc_channel.ch_queue =
malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT);
 3649         if (cp->wdc_channel.ch_queue == NULL) {
printf("%s %s: "
 3651                     "can't allocate memory for command queue",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
 3653                     return;
 3654         }
 3656         /* XXX */
reg = 0xa2 + channel * 16;
 3658         for (i = 0; i < sizeof(init_val); i++)
pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]);
printf("%s: %s %s to %s mode\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name,
 3663             (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ?
 3664             "configured" : "wired",
 3665             (interface & PCIIDE_INTERFACE_PCI(channel)) ?
 3666             "native-PCI" : "compatibility");
pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, pciide_pci_intr);
 3669         if (cp->hw_ok == 0)
 3670                 return;
pciide_map_compat_intr(pa, cp, channel, interface);
 3672 }
 3674 void
cmd680_setup_channel(struct channel_softc *chp)
 3676 {
 3677         struct ata_drive_datas *drvp;
u_int8_t mode, off, scsc;
u_int16_t val;
u_int32_t idedma_ctl;
 3681         int drive;
 3682         struct pciide_channel *cp = (struct pciide_channel *)chp;
 3683         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
pci_chipset_tag_t pc = sc->sc_pc;
pcitag_t pa = sc->sc_tag;
 3686         static const u_int8_t udma2_tbl[] =
 3687             { 0x0f, 0x0b, 0x07, 0x06, 0x03, 0x02, 0x01 };
 3688         static const u_int8_t udma_tbl[] =
 3689             { 0x0c, 0x07, 0x05, 0x04, 0x02, 0x01, 0x00 };
 3690         static const u_int16_t dma_tbl[] =
 3691             { 0x2208, 0x10c2, 0x10c1 };
 3692         static const u_int16_t pio_tbl[] =
 3693             { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
idedma_ctl = 0;
pciide_channel_dma_setup(cp);
mode = pciide_pci_read(pc, pa, 0x80 + chp->channel * 4);
 3699         for (drive = 0; drive < 2; drive++) {
drvp = &chp->ch_drive[drive];
 3701                 /* If no drive, skip */
 3702                 if ((drvp->drive_flags & DRIVE) == 0)
 3703                         continue;
mode &= ~(0x03 << (drive * 4));
 3705                 if (drvp->drive_flags & DRIVE_UDMA) {
drvp->drive_flags &= ~DRIVE_DMA;
off = 0xa0 + chp->channel * 16;
 3708                         if (drvp->UDMA_mode > 2 &&
 3709                             (pciide_pci_read(pc, pa, off) & 0x01) == 0)
drvp->UDMA_mode = 2;
scsc = pciide_pci_read(pc, pa, 0x8a);
 3712                         if (drvp->UDMA_mode == 6 && (scsc & 0x30) == 0) {
pciide_pci_write(pc, pa, 0x8a, scsc | 0x01);
scsc = pciide_pci_read(pc, pa, 0x8a);
 3715                                 if ((scsc & 0x30) == 0)
drvp->UDMA_mode = 5;
 3717                         }
mode |= 0x03 << (drive * 4);
off = 0xac + chp->channel * 16 + drive * 2;
val = pciide_pci_read(pc, pa, off) & ~0x3f;
 3721                         if (scsc & 0x30)
val |= udma2_tbl[drvp->UDMA_mode];
 3723                         else
val |= udma_tbl[drvp->UDMA_mode];
pciide_pci_write(pc, pa, off, val);
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
 3727                 } else if (drvp->drive_flags & DRIVE_DMA) {
mode |= 0x02 << (drive * 4);
off = 0xa8 + chp->channel * 16 + drive * 2;
val = dma_tbl[drvp->DMA_mode];
pciide_pci_write(pc, pa, off, val & 0xff);
pciide_pci_write(pc, pa, off, val >> 8);
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
 3734                 } else {
mode |= 0x01 << (drive * 4);
off = 0xa4 + chp->channel * 16 + drive * 2;
val = pio_tbl[drvp->PIO_mode];
pciide_pci_write(pc, pa, off, val & 0xff);
pciide_pci_write(pc, pa, off, val >> 8);
 3740                 }
 3741         }
pciide_pci_write(pc, pa, 0x80 + chp->channel * 4, mode);
 3744         if (idedma_ctl != 0) {
 3745                 /* Add software bits in status register */
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CTL(chp->channel),
idedma_ctl);
 3749         }
pciide_print_modes(cp);
 3751 }
 3753 /*
 3754  * When the Silicon Image 3112 retries a PCI memory read command,
 3755  * it may retry it as a memory read multiple command under some
 3756  * circumstances.  This can totally confuse some PCI controllers,
 3757  * so ensure that it will never do this by making sure that the
 3758  * Read Threshold (FIFO Read Request Control) field of the FIFO
 3759  * Valid Byte Count and Control registers for both channels (BA5
 3760  * offset 0x40 and 0x44) are set to be at least as large as the
 3761  * cacheline size register.
 3762  */
 3763 void
sii_fixup_cacheline(struct pciide_softc *sc, struct pci_attach_args *pa)
 3765 {
pcireg_t cls, reg40, reg44;
cls = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
cls = (cls >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK;
cls *= 4;
 3771         if (cls > 224) {
cls = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
cls &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT);
cls |= ((224/4) << PCI_CACHELINE_SHIFT);
pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, cls);
cls = 224;
 3777         }
 3778         if (cls < 32)
cls = 32;
cls = (cls + 31) / 32;
reg40 = ba5_read_4(sc, 0x40);
reg44 = ba5_read_4(sc, 0x44);
 3783         if ((reg40 & 0x7) < cls)
ba5_write_4(sc, 0x40, (reg40 & ~0x07) | cls);
 3785         if ((reg44 & 0x7) < cls)
ba5_write_4(sc, 0x44, (reg44 & ~0x07) | cls);
 3787 }
 3789 void
sii3112_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
 3791 {
 3792         struct pciide_channel *cp;
bus_size_t cmdsize, ctlsize;
pcireg_t interface, scs_cmd, cfgctl;
 3795         int channel;
 3796         struct pciide_satalink *sl = sc->sc_cookie;
 3798         /* Allocate memory for private data */
sc->sc_cookie = malloc(sizeof(struct pciide_satalink), M_DEVBUF,
M_NOWAIT);
sl = sc->sc_cookie;
bzero(sl, sizeof(*sl));
 3804 #define SII3112_RESET_BITS                                              \
 3805         (SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET |                        \
SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET |                        \
SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET)
 3809         /*
 3810          * Reset everything and then unblock all of the interrupts.
 3811          */
scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD);
pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD,
scs_cmd | SII3112_RESET_BITS);
delay(50 * 1000);
pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD,
scs_cmd & SCS_CMD_BA5_EN);
delay(50 * 1000);
 3820         if (scs_cmd & SCS_CMD_BA5_EN) {
 3821                 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14,
PCI_MAPREG_TYPE_MEM |
PCI_MAPREG_MEM_TYPE_32BIT, 0,
 3824                                    &sl->ba5_st, &sl->ba5_sh,
NULL, NULL, 0) != 0)
printf(": unable to map BA5 register space\n");
 3827                 else
sl->ba5_en = 1;
 3829         } else {
cfgctl = pci_conf_read(pa->pa_pc, pa->pa_tag,
SII3112_PCI_CFGCTL);
pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_PCI_CFGCTL,
cfgctl | CFGCTL_BA5INDEN);
 3834         }
printf(": DMA");
pciide_mapreg_dma(sc, pa);
printf("\n");
 3840         /*
 3841          * Rev. <= 0x01 of the 3112 have a bug that can cause data
 3842          * corruption if DMA transfers cross an 8K boundary.  This is
 3843          * apparently hard to tickle, but we'll go ahead and play it
 3844          * safe.
 3845          */
 3846         if (sc->sc_rev <= 0x01) {
sc->sc_dma_maxsegsz = 8192;
sc->sc_dma_boundary = 8192;
 3849         }
sii_fixup_cacheline(sc, pa);
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32;
sc->sc_wdcdev.PIO_cap = 4;
 3855         if (sc->sc_dma_ok) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
sc->sc_wdcdev.irqack = pciide_irqack;
sc->sc_wdcdev.DMA_cap = 2;
sc->sc_wdcdev.UDMA_cap = 6;
 3861         }
sc->sc_wdcdev.set_modes = sii3112_setup_channel;
 3864         /* We can use SControl and SStatus to probe for drives. */
sc->sc_wdcdev.drv_probe = sii3112_drv_probe;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
 3870         /*
 3871          * The 3112 either identifies itself as a RAID storage device
 3872          * or a Misc storage device.  Fake up the interface bits for
 3873          * what our driver expects.
 3874          */
 3875         if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) {
interface = PCI_INTERFACE(pa->pa_class);
 3877         } else {
interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
 3880         }
 3882         for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
cp = &sc->pciide_channels[channel];
 3884                 if (pciide_chansetup(sc, channel, interface) == 0)
 3885                         continue;
pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
pciide_pci_intr);
 3888                 if (cp->hw_ok == 0)
 3889                         continue;
sc->sc_wdcdev.set_modes(&cp->wdc_channel);
 3891         }
 3892 }
 3894 void
sii3112_setup_channel(struct channel_softc *chp)
 3896 {
 3897         struct ata_drive_datas *drvp;
 3898         int drive;
u_int32_t idedma_ctl, dtm;
 3900         struct pciide_channel *cp = (struct pciide_channel *)chp;
 3901         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 3903         /* setup DMA if needed */
pciide_channel_dma_setup(cp);
idedma_ctl = 0;
dtm = 0;
 3909         for (drive = 0; drive < 2; drive++) {
drvp = &chp->ch_drive[drive];
 3911                 /* If no drive, skip */
 3912                 if ((drvp->drive_flags & DRIVE) == 0)
 3913                         continue;
 3914                 if (drvp->drive_flags & DRIVE_UDMA) {
 3915                         /* use Ultra/DMA */
drvp->drive_flags &= ~DRIVE_DMA;
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
dtm |= DTM_IDEx_DMA;
 3919                 } else if (drvp->drive_flags & DRIVE_DMA) {
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
dtm |= DTM_IDEx_DMA;
 3922                 } else {
dtm |= DTM_IDEx_PIO;
 3924                 }
 3925         }
 3927         /*
 3928          * Nothing to do to setup modes; it is meaningless in S-ATA
 3929          * (but many S-ATA drives still want to get the SET_FEATURE
 3930          * command).
 3931          */
 3932         if (idedma_ctl != 0) {
 3933                 /* Add software bits in status register */
PCIIDE_DMACTL_WRITE(sc, chp->channel, idedma_ctl);
 3935         }
BA5_WRITE_4(sc, chp->channel, ba5_IDE_DTM, dtm);
pciide_print_modes(cp);
 3938 }
 3940 void
sii3112_drv_probe(struct channel_softc *chp)
 3942 {
 3943         struct pciide_channel *cp = (struct pciide_channel *)chp;
 3944         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
uint32_t scontrol, sstatus;
uint8_t scnt, sn, cl, ch;
 3947         int i, s;
 3949         /* XXX This should be done by other code. */
 3950         for (i = 0; i < 2; i++) {
chp->ch_drive[i].chnl_softc = chp;
chp->ch_drive[i].drive = i;
 3953         }
 3955         /*
 3956          * The 3112 is a 2-port part, and only has one drive per channel
 3957          * (each port emulates a master drive).
 3958          *
 3959          * The 3114 is similar, but has 4 channels.
 3960          */
 3962         /*
 3963          * Request communication initialization sequence, any speed.
 3964          * Performing this is the equivalent of an ATA Reset.
 3965          */
scontrol = SControl_DET_INIT | SControl_SPD_ANY;
 3968         /*
 3969          * XXX We don't yet support SATA power management; disable all
 3970          * power management state transitions.
 3971          */
scontrol |= SControl_IPM_NONE;
BA5_WRITE_4(sc, chp->channel, ba5_SControl, scontrol);
delay(50 * 1000);
scontrol &= ~SControl_DET_INIT;
BA5_WRITE_4(sc, chp->channel, ba5_SControl, scontrol);
delay(50 * 1000);
sstatus = BA5_READ_4(sc, chp->channel, ba5_SStatus);
 3981 #if 0
printf("%s: port %d: SStatus=0x%08x, SControl=0x%08x\n",
sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus,
BA5_READ_4(sc, chp->channel, ba5_SControl));
 3985 #endif
 3986         switch (sstatus & SStatus_DET_mask) {
 3987         case SStatus_DET_NODEV:
 3988                 /* No device; be silent. */
 3989                 break;
 3991         case SStatus_DET_DEV_NE:
printf("%s: port %d: device connected, but "
 3993                     "communication not established\n",
sc->sc_wdcdev.sc_dev.dv_xname, chp->channel);
 3995                 break;
 3997         case SStatus_DET_OFFLINE:
printf("%s: port %d: PHY offline\n",
sc->sc_wdcdev.sc_dev.dv_xname, chp->channel);
 4000                 break;
 4002         case SStatus_DET_DEV:
 4003                 /*
 4004                  * XXX ATAPI detection doesn't currently work.  Don't
 4005                  * XXX know why.  But, it's not like the standard method
 4006                  * XXX can detect an ATAPI device connected via a SATA/PATA
 4007                  * XXX bridge, so at least this is no worse.  --thorpej
 4008                  */
 4009                 if (chp->_vtbl != NULL)
CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (0 << 4));
 4011                 else
bus_space_write_1(chp->cmd_iot, chp->cmd_ioh,
wdr_sdh & _WDC_REGMASK, WDSD_IBM | (0 << 4));
delay(10);      /* 400ns delay */
 4015                 /* Save register contents. */
 4016                 if (chp->_vtbl != NULL) {
scnt = CHP_READ_REG(chp, wdr_seccnt);
sn = CHP_READ_REG(chp, wdr_sector);
cl = CHP_READ_REG(chp, wdr_cyl_lo);
ch = CHP_READ_REG(chp, wdr_cyl_hi);
 4021                 } else {
scnt = bus_space_read_1(chp->cmd_iot,
chp->cmd_ioh, wdr_seccnt & _WDC_REGMASK);
sn = bus_space_read_1(chp->cmd_iot,
chp->cmd_ioh, wdr_sector & _WDC_REGMASK);
cl = bus_space_read_1(chp->cmd_iot,
chp->cmd_ioh, wdr_cyl_lo & _WDC_REGMASK);
ch = bus_space_read_1(chp->cmd_iot,
chp->cmd_ioh, wdr_cyl_hi & _WDC_REGMASK);
 4030                 }
 4031 #if 0
printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n",
sc->sc_wdcdev.sc_dev.dv_xname, chp->channel,
scnt, sn, cl, ch);
 4035 #endif
 4036                 /*
 4037                  * scnt and sn are supposed to be 0x1 for ATAPI, but in some
 4038                  * cases we get wrong values here, so ignore it.
 4039                  */
s = splbio();
 4041                 if (cl == 0x14 && ch == 0xeb)
chp->ch_drive[0].drive_flags |= DRIVE_ATAPI;
 4043                 else
chp->ch_drive[0].drive_flags |= DRIVE_ATA;
splx(s);
printf("%s: port %d: device present",
sc->sc_wdcdev.sc_dev.dv_xname, chp->channel);
 4049                 switch ((sstatus & SStatus_SPD_mask) >> SStatus_SPD_shift) {
 4050                 case 1:
printf(", speed: 1.5Gb/s");
 4052                         break;
 4053                 case 2:
printf(", speed: 3.0Gb/s");
 4055                         break;
 4056                 }
printf("\n");
 4058                 break;
 4060         default:
printf("%s: port %d: unknown SStatus: 0x%08x\n",
sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus);
 4063         }
 4064 }
 4066 void
sii3114_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
 4068 {
 4069         struct pciide_channel *cp;
pcireg_t scs_cmd;
pci_intr_handle_t intrhandle;
 4072         const char *intrstr;
 4073         int channel;
 4074         struct pciide_satalink *sl = sc->sc_cookie;
 4076         /* Allocate memory for private data */
sc->sc_cookie = malloc(sizeof(struct pciide_satalink), M_DEVBUF,
M_NOWAIT);
sl = sc->sc_cookie;
bzero(sl, sizeof(*sl));
 4082 #define SII3114_RESET_BITS                                              \
 4083         (SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET |                        \
SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET |                        \
SCS_CMD_FF3_RESET | SCS_CMD_FF2_RESET |                        \
SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET |                      \
SCS_CMD_IDE3_RESET | SCS_CMD_IDE2_RESET)
 4089         /*
 4090          * Reset everything and then unblock all of the interrupts.
 4091          */
scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD);
pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD,
scs_cmd | SII3114_RESET_BITS);
delay(50 * 1000);
pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD,
scs_cmd & SCS_CMD_M66EN);
delay(50 * 1000);
 4100         /*
 4101          * On the 3114, the BA5 register space is always enabled.  In
 4102          * order to use the 3114 in any sane way, we must use this BA5
 4103          * register space, and so we consider it an error if we cannot
 4104          * map it.
 4105          *
 4106          * As a consequence of using BA5, our register mapping is different
 4107          * from a normal PCI IDE controller's, and so we are unable to use
 4108          * most of the common PCI IDE register mapping functions.
 4109          */
 4110         if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14,
PCI_MAPREG_TYPE_MEM |
PCI_MAPREG_MEM_TYPE_32BIT, 0,
 4113                            &sl->ba5_st, &sl->ba5_sh,
NULL, NULL, 0) != 0) {
printf(": unable to map BA5 register space\n");
 4116                 return;
 4117         }
sl->ba5_en = 1;
 4120         /*
 4121          * Set the Interrupt Steering bit in the IDEDMA_CMD register of
 4122          * channel 2.  This is required at all times for proper operation
 4123          * when using the BA5 register space (otherwise interrupts from
 4124          * all 4 channels won't work).
 4125          */
BA5_WRITE_4(sc, 2, ba5_IDEDMA_CMD, IDEDMA_CMD_INT_STEER);
printf(": DMA");
sii3114_mapreg_dma(sc, pa);
printf("\n");
sii_fixup_cacheline(sc, pa);
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32;
sc->sc_wdcdev.PIO_cap = 4;
 4136         if (sc->sc_dma_ok) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
sc->sc_wdcdev.irqack = pciide_irqack;
sc->sc_wdcdev.DMA_cap = 2;
sc->sc_wdcdev.UDMA_cap = 6;
 4142         }
sc->sc_wdcdev.set_modes = sii3112_setup_channel;
 4145         /* We can use SControl and SStatus to probe for drives. */
sc->sc_wdcdev.drv_probe = sii3112_drv_probe;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = 4;
 4151         /* Map and establish the interrupt handler. */
 4152         if (pci_intr_map(pa, &intrhandle) != 0) {
printf("%s: couldn't map native-PCI interrupt\n",
sc->sc_wdcdev.sc_dev.dv_xname);
 4155                 return;
 4156         }
intrstr = pci_intr_string(pa->pa_pc, intrhandle);
sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO,
 4159                                            /* XXX */
pciide_pci_intr, sc,
sc->sc_wdcdev.sc_dev.dv_xname);
 4162         if (sc->sc_pci_ih != NULL) {
printf("%s: using %s for native-PCI interrupt\n",
sc->sc_wdcdev.sc_dev.dv_xname,
intrstr ? intrstr : "unknown interrupt");
 4166         } else {
printf("%s: couldn't establish native-PCI interrupt",
sc->sc_wdcdev.sc_dev.dv_xname);
 4169                 if (intrstr != NULL)
printf(" at %s", intrstr);
printf("\n");
 4172                 return;
 4173         }
 4175         for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
cp = &sc->pciide_channels[channel];
 4177                 if (sii3114_chansetup(sc, channel) == 0)
 4178                         continue;
sii3114_mapchan(cp);
 4180                 if (cp->hw_ok == 0)
 4181                         continue;
sc->sc_wdcdev.set_modes(&cp->wdc_channel);
 4183         }
 4184 }
 4186 void
sii3114_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa)
 4188 {
 4189         struct pciide_channel *pc;
 4190         int chan, reg;
bus_size_t size;
 4192         struct pciide_satalink *sl = sc->sc_cookie;
sc->sc_wdcdev.dma_arg = sc;
sc->sc_wdcdev.dma_init = pciide_dma_init;
sc->sc_wdcdev.dma_start = pciide_dma_start;
sc->sc_wdcdev.dma_finish = pciide_dma_finish;
 4199         /*
 4200          * Slice off a subregion of BA5 for each of the channel's DMA
 4201          * registers.
 4202          */
sc->sc_dma_iot = sl->ba5_st;
 4205         for (chan = 0; chan < 4; chan++) {
pc = &sc->pciide_channels[chan];
 4207                 for (reg = 0; reg < IDEDMA_NREGS; reg++) {
size = 4;
 4209                         if (size > (IDEDMA_SCH_OFFSET - reg))
size = IDEDMA_SCH_OFFSET - reg;
 4211                         if (bus_space_subregion(sl->ba5_st,
sl->ba5_sh,
satalink_ba5_regmap[chan].ba5_IDEDMA_CMD + reg,
size, &sl->regs[chan].dma_iohs[reg]) != 0) {
sc->sc_dma_ok = 0;
printf(": can't subregion offset "
 4217                                     "%lu size %lu",
 4218                                     (u_long) satalink_ba5_regmap[
chan].ba5_IDEDMA_CMD + reg,
 4220                                     (u_long) size);
 4221                                 return;
 4222                         }
 4223                 }
 4224         }
sc->sc_dmacmd_read = sii3114_dmacmd_read;
sc->sc_dmacmd_write = sii3114_dmacmd_write;
sc->sc_dmactl_read = sii3114_dmactl_read;
sc->sc_dmactl_write = sii3114_dmactl_write;
sc->sc_dmatbl_write = sii3114_dmatbl_write;
 4232         /* DMA registers all set up! */
sc->sc_dmat = pa->pa_dmat;
sc->sc_dma_ok = 1;
 4235 }
 4237 int
sii3114_chansetup(struct pciide_softc *sc, int channel)
 4239 {
 4240         static const char *channel_names[] = {
 4241                 "port 0",
 4242                 "port 1",
 4243                 "port 2",
 4244                 "port 3",
 4245         };
 4246         struct pciide_channel *cp = &sc->pciide_channels[channel];
sc->wdc_chanarray[channel] = &cp->wdc_channel;
 4250         /*
 4251          * We must always keep the Interrupt Steering bit set in channel 2's
 4252          * IDEDMA_CMD register.
 4253          */
 4254         if (channel == 2)
cp->idedma_cmd = IDEDMA_CMD_INT_STEER;
cp->name = channel_names[channel];
cp->wdc_channel.channel = channel;
cp->wdc_channel.wdc = &sc->sc_wdcdev;
cp->wdc_channel.ch_queue =
malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT);
 4262         if (cp->wdc_channel.ch_queue == NULL) {
printf("%s %s channel: "
 4264                     "can't allocate memory for command queue",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
 4266                 return (0);
 4267         }
 4268         return (1);
 4269 }
 4271 void
sii3114_mapchan(struct pciide_channel *cp)
 4273 {
 4274         struct channel_softc *wdc_cp = &cp->wdc_channel;
 4275         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 4276         struct pciide_satalink *sl = sc->sc_cookie;
 4277         int chan = wdc_cp->channel;
 4278         int i;
cp->hw_ok = 0;
cp->compat = 0;
cp->ih = sc->sc_pci_ih;
sl->regs[chan].cmd_iot = sl->ba5_st;
 4285         if (bus_space_subregion(sl->ba5_st, sl->ba5_sh,
satalink_ba5_regmap[chan].ba5_IDE_TF0,
 4287                         9, &sl->regs[chan].cmd_baseioh) != 0) {
printf("%s: couldn't subregion %s cmd base\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
 4290                 return;
 4291         }
sl->regs[chan].ctl_iot = sl->ba5_st;
 4294         if (bus_space_subregion(sl->ba5_st, sl->ba5_sh,
satalink_ba5_regmap[chan].ba5_IDE_TF8,
 4296                         1, &cp->ctl_baseioh) != 0) {
printf("%s: couldn't subregion %s ctl base\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
 4299                 return;
 4300         }
sl->regs[chan].ctl_ioh = cp->ctl_baseioh;
 4303         for (i = 0; i < WDC_NREG; i++) {
 4304                 if (bus_space_subregion(sl->regs[chan].cmd_iot,
sl->regs[chan].cmd_baseioh,
i, i == 0 ? 4 : 1,
 4307                     &sl->regs[chan].cmd_iohs[i]) != 0) {
printf("%s: couldn't subregion %s channel "
 4309                             "cmd regs\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
 4311                         return;
 4312                 }
 4313         }
sl->regs[chan].cmd_iohs[wdr_status & _WDC_REGMASK] =
sl->regs[chan].cmd_iohs[wdr_command & _WDC_REGMASK];
sl->regs[chan].cmd_iohs[wdr_features & _WDC_REGMASK] =
sl->regs[chan].cmd_iohs[wdr_error & _WDC_REGMASK];
wdc_cp->data32iot = wdc_cp->cmd_iot = sl->regs[chan].cmd_iot;
wdc_cp->data32ioh = wdc_cp->cmd_ioh = sl->regs[chan].cmd_iohs[0];
wdc_cp->_vtbl = &wdc_sii3114_vtbl;
wdcattach(wdc_cp);
cp->hw_ok = 1;
 4323 }
u_int8_t
sii3114_read_reg(struct channel_softc *chp, enum wdc_regs reg)
 4327 {
 4328         struct pciide_channel *cp = (struct pciide_channel *)chp;
 4329         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 4330         struct pciide_satalink *sl = sc->sc_cookie;
 4332         if (reg & _WDC_AUX)
 4333                 return (bus_space_read_1(sl->regs[chp->channel].ctl_iot,
sl->regs[chp->channel].ctl_ioh, reg & _WDC_REGMASK));
 4335         else
 4336                 return (bus_space_read_1(sl->regs[chp->channel].cmd_iot,
sl->regs[chp->channel].cmd_iohs[reg & _WDC_REGMASK], 0));
 4338 }
 4340 void
sii3114_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int8_t val)
 4342 {
 4343         struct pciide_channel *cp = (struct pciide_channel *)chp;
 4344         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 4345         struct pciide_satalink *sl = sc->sc_cookie;
 4347         if (reg & _WDC_AUX)
bus_space_write_1(sl->regs[chp->channel].ctl_iot,
sl->regs[chp->channel].ctl_ioh, reg & _WDC_REGMASK, val);
 4350         else
bus_space_write_1(sl->regs[chp->channel].cmd_iot,
sl->regs[chp->channel].cmd_iohs[reg & _WDC_REGMASK],
 4353                     0, val);
 4354 }
u_int8_t
sii3114_dmacmd_read(struct pciide_softc *sc, int chan)
 4358 {
 4359         struct pciide_satalink *sl = sc->sc_cookie;
 4361         return (bus_space_read_1(sc->sc_dma_iot,
sl->regs[chan].dma_iohs[IDEDMA_CMD(0)], 0));
 4363 }
 4365 void
sii3114_dmacmd_write(struct pciide_softc *sc, int chan, u_int8_t val)
 4367 {
 4368         struct pciide_satalink *sl = sc->sc_cookie;
bus_space_write_1(sc->sc_dma_iot,
sl->regs[chan].dma_iohs[IDEDMA_CMD(0)], 0, val);
 4372 }
u_int8_t
sii3114_dmactl_read(struct pciide_softc *sc, int chan)
 4376 {
 4377         struct pciide_satalink *sl = sc->sc_cookie;
 4379         return (bus_space_read_1(sc->sc_dma_iot,
sl->regs[chan].dma_iohs[IDEDMA_CTL(0)], 0));
 4381 }
 4383 void
sii3114_dmactl_write(struct pciide_softc *sc, int chan, u_int8_t val)
 4385 {
 4386         struct pciide_satalink *sl = sc->sc_cookie;
bus_space_write_1(sc->sc_dma_iot,
sl->regs[chan].dma_iohs[IDEDMA_CTL(0)], 0, val);
 4390 }
 4392 void
sii3114_dmatbl_write(struct pciide_softc *sc, int chan, u_int32_t val)
 4394 {
 4395         struct pciide_satalink *sl = sc->sc_cookie;
bus_space_write_4(sc->sc_dma_iot,
sl->regs[chan].dma_iohs[IDEDMA_TBL(0)], 0, val);
 4399 }
 4401 void
cy693_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
 4403 {
 4404         struct pciide_channel *cp;
pcireg_t interface = PCI_INTERFACE(pa->pa_class);
bus_size_t cmdsize, ctlsize;
 4407         struct pciide_cy *cy;
 4409         /* Allocate memory for private data */
sc->sc_cookie = malloc(sizeof(struct pciide_cy), M_DEVBUF, M_NOWAIT);
cy = sc->sc_cookie;
bzero(cy, sizeof(*cy));
 4414         /*
 4415          * this chip has 2 PCI IDE functions, one for primary and one for
 4416          * secondary. So we need to call pciide_mapregs_compat() with
 4417          * the real channel
 4418          */
 4419         if (pa->pa_function == 1) {
cy->cy_compatchan = 0;
 4421         } else if (pa->pa_function == 2) {
cy->cy_compatchan = 1;
 4423         } else {
printf(": unexpected PCI function %d\n", pa->pa_function);
 4425                 return;
 4426         }
 4428         if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) {
printf(": DMA");
pciide_mapreg_dma(sc, pa);
 4431         } else {
printf(": no DMA");
sc->sc_dma_ok = 0;
 4434         }
cy->cy_handle = cy82c693_init(pa->pa_iot);
 4437         if (cy->cy_handle == NULL) {
printf(", (unable to map ctl registers)");
sc->sc_dma_ok = 0;
 4440         }
sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
WDC_CAPABILITY_MODE;
 4444         if (sc->sc_dma_ok) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK;
sc->sc_wdcdev.irqack = pciide_irqack;
 4447         }
sc->sc_wdcdev.PIO_cap = 4;
sc->sc_wdcdev.DMA_cap = 2;
sc->sc_wdcdev.set_modes = cy693_setup_channel;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = 1;
 4455         /* Only one channel for this chip; if we are here it's enabled */
cp = &sc->pciide_channels[0];
sc->wdc_chanarray[0] = &cp->wdc_channel;
cp->name = PCIIDE_CHANNEL_NAME(0);
cp->wdc_channel.channel = 0;
cp->wdc_channel.wdc = &sc->sc_wdcdev;
cp->wdc_channel.ch_queue =
malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT);
 4463         if (cp->wdc_channel.ch_queue == NULL) {
printf(": cannot allocate memory for command queue\n");
 4465                 return;
 4466         }
printf(", %s %s to ", PCIIDE_CHANNEL_NAME(0),
 4468             (interface & PCIIDE_INTERFACE_SETTABLE(0)) ?
 4469             "configured" : "wired");
 4470         if (interface & PCIIDE_INTERFACE_PCI(0)) {
printf("native-PCI\n");
cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize,
pciide_pci_intr);
 4474         } else {
printf("compatibility\n");
cp->hw_ok = pciide_mapregs_compat(pa, cp, cy->cy_compatchan,
 4477                     &cmdsize, &ctlsize);
 4478         }
cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot;
cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh;
pciide_map_compat_intr(pa, cp, cy->cy_compatchan, interface);
 4483         if (cp->hw_ok == 0)
 4484                 return;
wdcattach(&cp->wdc_channel);
 4486         if (pciide_chan_candisable(cp)) {
pci_conf_write(sc->sc_pc, sc->sc_tag,
PCI_COMMAND_STATUS_REG, 0);
 4489         }
 4490         if (cp->hw_ok == 0) {
pciide_unmap_compat_intr(pa, cp, cy->cy_compatchan,
interface);
 4493                 return;
 4494         }
WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n",
pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE);
cy693_setup_channel(&cp->wdc_channel);
WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n",
pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE);
 4501 }
 4503 void
cy693_setup_channel(struct channel_softc *chp)
 4505 {
 4506         struct ata_drive_datas *drvp;
 4507         int drive;
u_int32_t cy_cmd_ctrl;
u_int32_t idedma_ctl;
 4510         struct pciide_channel *cp = (struct pciide_channel *)chp;
 4511         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 4512         int dma_mode = -1;
 4513         struct pciide_cy *cy = sc->sc_cookie;
cy_cmd_ctrl = idedma_ctl = 0;
 4517         /* setup DMA if needed */
pciide_channel_dma_setup(cp);
 4520         for (drive = 0; drive < 2; drive++) {
drvp = &chp->ch_drive[drive];
 4522                 /* If no drive, skip */
 4523                 if ((drvp->drive_flags & DRIVE) == 0)
 4524                         continue;
 4525                 /* add timing values, setup DMA if needed */
 4526                 if (drvp->drive_flags & DRIVE_DMA) {
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
 4528                         /* use Multiword DMA */
 4529                         if (dma_mode == -1 || dma_mode > drvp->DMA_mode)
dma_mode = drvp->DMA_mode;
 4531                 }
cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] <<
CY_CMD_CTRL_IOW_PULSE_OFF(drive));
cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] <<
CY_CMD_CTRL_IOW_REC_OFF(drive));
cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] <<
CY_CMD_CTRL_IOR_PULSE_OFF(drive));
cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] <<
CY_CMD_CTRL_IOR_REC_OFF(drive));
 4540         }
pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl);
chp->ch_drive[0].DMA_mode = dma_mode;
chp->ch_drive[1].DMA_mode = dma_mode;
 4545         if (dma_mode == -1)
dma_mode = 0;
 4548         if (cy->cy_handle != NULL) {
 4549                 /* Note: `multiple' is implied. */
cy82c693_write(cy->cy_handle,
 4551                     (cy->cy_compatchan == 0) ?
CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode);
 4553         }
pciide_print_modes(cp);
 4557         if (idedma_ctl != 0) {
 4558                 /* Add software bits in status register */
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CTL(chp->channel), idedma_ctl);
 4561         }
 4562 }
 4564 static struct sis_hostbr_type {
u_int16_t id;
u_int8_t rev;
u_int8_t udma_mode;
 4568         char *name;
u_int8_t type;
 4570 #define SIS_TYPE_NOUDMA 0
 4571 #define SIS_TYPE_66     1
 4572 #define SIS_TYPE_100OLD 2
 4573 #define SIS_TYPE_100NEW 3
 4574 #define SIS_TYPE_133OLD 4
 4575 #define SIS_TYPE_133NEW 5
 4576 #define SIS_TYPE_SOUTH  6
 4577 } sis_hostbr_type[] = {
 4578         /* Most infos here are from sos@freebsd.org */
 4579         {PCI_PRODUCT_SIS_530, 0x00, 4, "530", SIS_TYPE_66},
 4580 #if 0
 4581         /*
 4582          * controllers associated to a rev 0x2 530 Host to PCI Bridge
 4583          * have problems with UDMA (info provided by Christos)
 4584          */
 4585         {PCI_PRODUCT_SIS_530, 0x02, 0, "530 (buggy)", SIS_TYPE_NOUDMA},
 4586 #endif
 4587         {PCI_PRODUCT_SIS_540, 0x00, 4, "540", SIS_TYPE_66},
 4588         {PCI_PRODUCT_SIS_550, 0x00, 4, "550", SIS_TYPE_66},
 4589         {PCI_PRODUCT_SIS_620, 0x00, 4, "620", SIS_TYPE_66},
 4590         {PCI_PRODUCT_SIS_630, 0x00, 4, "630", SIS_TYPE_66},
 4591         {PCI_PRODUCT_SIS_630, 0x30, 5, "630S", SIS_TYPE_100NEW},
 4592         {PCI_PRODUCT_SIS_633, 0x00, 5, "633", SIS_TYPE_100NEW},
 4593         {PCI_PRODUCT_SIS_635, 0x00, 5, "635", SIS_TYPE_100NEW},
 4594         {PCI_PRODUCT_SIS_640, 0x00, 4, "640", SIS_TYPE_SOUTH},
 4595         {PCI_PRODUCT_SIS_645, 0x00, 6, "645", SIS_TYPE_SOUTH},
 4596         {PCI_PRODUCT_SIS_646, 0x00, 6, "645DX", SIS_TYPE_SOUTH},
 4597         {PCI_PRODUCT_SIS_648, 0x00, 6, "648", SIS_TYPE_SOUTH},
 4598         {PCI_PRODUCT_SIS_650, 0x00, 6, "650", SIS_TYPE_SOUTH},
 4599         {PCI_PRODUCT_SIS_651, 0x00, 6, "651", SIS_TYPE_SOUTH},
 4600         {PCI_PRODUCT_SIS_652, 0x00, 6, "652", SIS_TYPE_SOUTH},
 4601         {PCI_PRODUCT_SIS_655, 0x00, 6, "655", SIS_TYPE_SOUTH},
 4602         {PCI_PRODUCT_SIS_658, 0x00, 6, "658", SIS_TYPE_SOUTH},
 4603         {PCI_PRODUCT_SIS_661, 0x00, 6, "661", SIS_TYPE_SOUTH},
 4604         {PCI_PRODUCT_SIS_730, 0x00, 5, "730", SIS_TYPE_100OLD},
 4605         {PCI_PRODUCT_SIS_733, 0x00, 5, "733", SIS_TYPE_100NEW},
 4606         {PCI_PRODUCT_SIS_735, 0x00, 5, "735", SIS_TYPE_100NEW},
 4607         {PCI_PRODUCT_SIS_740, 0x00, 5, "740", SIS_TYPE_SOUTH},
 4608         {PCI_PRODUCT_SIS_741, 0x00, 6, "741", SIS_TYPE_SOUTH},
 4609         {PCI_PRODUCT_SIS_745, 0x00, 5, "745", SIS_TYPE_100NEW},
 4610         {PCI_PRODUCT_SIS_746, 0x00, 6, "746", SIS_TYPE_SOUTH},
 4611         {PCI_PRODUCT_SIS_748, 0x00, 6, "748", SIS_TYPE_SOUTH},
 4612         {PCI_PRODUCT_SIS_750, 0x00, 6, "750", SIS_TYPE_SOUTH},
 4613         {PCI_PRODUCT_SIS_751, 0x00, 6, "751", SIS_TYPE_SOUTH},
 4614         {PCI_PRODUCT_SIS_752, 0x00, 6, "752", SIS_TYPE_SOUTH},
 4615         {PCI_PRODUCT_SIS_755, 0x00, 6, "755", SIS_TYPE_SOUTH},
 4616         {PCI_PRODUCT_SIS_760, 0x00, 6, "760", SIS_TYPE_SOUTH},
 4617         /*
 4618          * From sos@freebsd.org: the 0x961 ID will never be found in real world
 4619          * {PCI_PRODUCT_SIS_961, 0x00, 6, "961", SIS_TYPE_133NEW},
 4620          */
 4621         {PCI_PRODUCT_SIS_962, 0x00, 6, "962", SIS_TYPE_133NEW},
 4622         {PCI_PRODUCT_SIS_963, 0x00, 6, "963", SIS_TYPE_133NEW}
 4623 };
 4625 static struct sis_hostbr_type *sis_hostbr_type_match;
 4627 int
sis_hostbr_match(struct pci_attach_args *pa)
 4629 {
 4630         int i;
 4632         if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_SIS)
 4633                 return (0);
sis_hostbr_type_match = NULL;
 4635         for (i = 0;
i < sizeof(sis_hostbr_type) / sizeof(sis_hostbr_type[0]);
i++) {
 4638                 if (PCI_PRODUCT(pa->pa_id) == sis_hostbr_type[i].id &&
PCI_REVISION(pa->pa_class) >= sis_hostbr_type[i].rev)
sis_hostbr_type_match = &sis_hostbr_type[i];
 4641         }
 4642         return (sis_hostbr_type_match != NULL);
 4643 }
 4645 int
sis_south_match(struct pci_attach_args *pa)
 4647 {
 4648         return(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS &&
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_85C503 &&
PCI_REVISION(pa->pa_class) >= 0x10);
 4651 }
 4653 void
sis_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
 4655 {
 4656         struct pciide_channel *cp;
 4657         int channel;
u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0);
pcireg_t interface = PCI_INTERFACE(pa->pa_class);
 4660         int rev = sc->sc_rev;
bus_size_t cmdsize, ctlsize;
pcitag_t br_tag;
 4663         struct pci_attach_args br_pa;
 4664         struct pciide_sis *sis;
 4666         /* Allocate memory for private data */
sc->sc_cookie = malloc(sizeof(struct pciide_sis), M_DEVBUF, M_NOWAIT);
sis = sc->sc_cookie;
bzero(sis, sizeof(*sis));
 4671         /* Find PCI bridge (dev 0 func 0 on the same bus) */
br_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, 0, 0);
br_pa.pa_id = pci_conf_read(sc->sc_pc, br_tag, PCI_ID_REG);
br_pa.pa_class = pci_conf_read(sc->sc_pc, br_tag, PCI_CLASS_REG);
WDCDEBUG_PRINT(("%s: PCI bridge pa_id=0x%x pa_class=0x%x\n",
__func__, br_pa.pa_id, br_pa.pa_class), DEBUG_PROBE);
 4678         if (sis_hostbr_match(&br_pa)) {
 4679                 if (sis_hostbr_type_match->type == SIS_TYPE_SOUTH) {
pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_57,
pciide_pci_read(sc->sc_pc, sc->sc_tag,
SIS_REG_57) & 0x7f);
 4683                         if (sc->sc_pp->ide_product == SIS_PRODUCT_5518) {
sis->sis_type = SIS_TYPE_133NEW;
sc->sc_wdcdev.UDMA_cap =
sis_hostbr_type_match->udma_mode;
 4687                         } else {
 4688                                 /* Find ISA bridge (func 0 of the same dev) */
br_tag = pci_make_tag(pa->pa_pc, pa->pa_bus,
pa->pa_device, 0);
br_pa.pa_id = pci_conf_read(sc->sc_pc,
br_tag, PCI_ID_REG);
br_pa.pa_class = pci_conf_read(sc->sc_pc,
br_tag, PCI_CLASS_REG);
WDCDEBUG_PRINT(("%s: ISA bridge "
 4696                                     "pa_id=0x%x pa_class=0x%x\n",
__func__, br_pa.pa_id, br_pa.pa_class),
DEBUG_PROBE);
 4700                                 if (sis_south_match(&br_pa)) {
sis->sis_type = SIS_TYPE_133OLD;
sc->sc_wdcdev.UDMA_cap =
sis_hostbr_type_match->udma_mode;
 4704                                 } else {
sis->sis_type = SIS_TYPE_100NEW;
sc->sc_wdcdev.UDMA_cap =
sis_hostbr_type_match->udma_mode;
 4708                                 }
 4709                         }
 4710                 } else {
sis->sis_type = sis_hostbr_type_match->type;
sc->sc_wdcdev.UDMA_cap =
sis_hostbr_type_match->udma_mode;
 4714                 }
printf(": %s", sis_hostbr_type_match->name);
 4716         } else {
printf(": 5597/5598");
 4718                 if (rev >= 0xd0) {
sc->sc_wdcdev.UDMA_cap = 2;
sis->sis_type = SIS_TYPE_66;
 4721                 } else {
sc->sc_wdcdev.UDMA_cap = 0;
sis->sis_type = SIS_TYPE_NOUDMA;
 4724                 }
 4725         }
printf(": DMA");
pciide_mapreg_dma(sc, pa);
sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
WDC_CAPABILITY_MODE;
 4732         if (sc->sc_dma_ok) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK;
sc->sc_wdcdev.irqack = pciide_irqack;
 4735                 if (sis->sis_type >= SIS_TYPE_66)
sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
 4737         }
sc->sc_wdcdev.PIO_cap = 4;
sc->sc_wdcdev.DMA_cap = 2;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
 4744         switch (sis->sis_type) {
 4745         case SIS_TYPE_NOUDMA:
 4746         case SIS_TYPE_66:
 4747         case SIS_TYPE_100OLD:
sc->sc_wdcdev.set_modes = sis_setup_channel;
pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC,
pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) |
SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE | SIS_MISC_GTC);
 4752                 break;
 4753         case SIS_TYPE_100NEW:
 4754         case SIS_TYPE_133OLD:
sc->sc_wdcdev.set_modes = sis_setup_channel;
pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_49,
pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_49) | 0x01);
 4758                 break;
 4759         case SIS_TYPE_133NEW:
sc->sc_wdcdev.set_modes = sis96x_setup_channel;
pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_50,
pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_50) & 0xf7);
pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_52,
pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_52) & 0xf7);
 4765                 break;
 4766         }
pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
 4770         for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
cp = &sc->pciide_channels[channel];
 4772                 if (pciide_chansetup(sc, channel, interface) == 0)
 4773                         continue;
 4774                 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) ||
 4775                     (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) {
printf("%s: %s ignored (disabled)\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
 4778                         continue;
 4779                 }
pciide_map_compat_intr(pa, cp, channel, interface);
 4781                 if (cp->hw_ok == 0)
 4782                         continue;
pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
pciide_pci_intr);
 4785                 if (cp->hw_ok == 0) {
pciide_unmap_compat_intr(pa, cp, channel, interface);
 4787                         continue;
 4788                 }
 4789                 if (pciide_chan_candisable(cp)) {
 4790                         if (channel == 0)
sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN;
 4792                         else
sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN;
pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0,
sis_ctr0);
 4796                 }
 4797                 if (cp->hw_ok == 0) {
pciide_unmap_compat_intr(pa, cp, channel, interface);
 4799                         continue;
 4800                 }
sc->sc_wdcdev.set_modes(&cp->wdc_channel);
 4802         }
 4803 }
 4805 void
sis96x_setup_channel(struct channel_softc *chp)
 4807 {
 4808         struct ata_drive_datas *drvp;
 4809         int drive;
u_int32_t sis_tim;
u_int32_t idedma_ctl;
 4812         int regtim;
 4813         struct pciide_channel *cp = (struct pciide_channel *)chp;
 4814         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
sis_tim = 0;
idedma_ctl = 0;
 4818         /* setup DMA if needed */
pciide_channel_dma_setup(cp);
 4821         for (drive = 0; drive < 2; drive++) {
regtim = SIS_TIM133(
pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_57),
chp->channel, drive);
drvp = &chp->ch_drive[drive];
 4826                 /* If no drive, skip */
 4827                 if ((drvp->drive_flags & DRIVE) == 0)
 4828                         continue;
 4829                 /* add timing values, setup DMA if needed */
 4830                 if (drvp->drive_flags & DRIVE_UDMA) {
 4831                         /* use Ultra/DMA */
drvp->drive_flags &= ~DRIVE_DMA;
 4833                         if (pciide_pci_read(sc->sc_pc, sc->sc_tag,
SIS96x_REG_CBL(chp->channel)) & SIS96x_REG_CBL_33) {
 4835                                 if (drvp->UDMA_mode > 2)
drvp->UDMA_mode = 2;
 4837                         }
sis_tim |= sis_udma133new_tim[drvp->UDMA_mode];
sis_tim |= sis_pio133new_tim[drvp->PIO_mode];
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
 4841                 } else if (drvp->drive_flags & DRIVE_DMA) {
 4842                         /*
 4843                          * use Multiword DMA
 4844                          * Timings will be used for both PIO and DMA,
 4845                          * so adjust DMA mode if needed
 4846                          */
 4847                         if (drvp->PIO_mode > (drvp->DMA_mode + 2))
drvp->PIO_mode = drvp->DMA_mode + 2;
 4849                         if (drvp->DMA_mode + 2 > (drvp->PIO_mode))
drvp->DMA_mode = (drvp->PIO_mode > 2) ?
drvp->PIO_mode - 2 : 0;
sis_tim |= sis_dma133new_tim[drvp->DMA_mode];
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
 4854                 } else {
sis_tim |= sis_pio133new_tim[drvp->PIO_mode];
 4856                 }
WDCDEBUG_PRINT(("sis96x_setup_channel: new timings reg for "
 4858                     "channel %d drive %d: 0x%x (reg 0x%x)\n",
chp->channel, drive, sis_tim, regtim), DEBUG_PROBE);
pci_conf_write(sc->sc_pc, sc->sc_tag, regtim, sis_tim);
 4861         }
 4862         if (idedma_ctl != 0) {
 4863                 /* Add software bits in status register */
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CTL(chp->channel), idedma_ctl);
 4866         }
pciide_print_modes(cp);
 4868 }
 4870 void
sis_setup_channel(struct channel_softc *chp)
 4872 {
 4873         struct ata_drive_datas *drvp;
 4874         int drive;
u_int32_t sis_tim;
u_int32_t idedma_ctl;
 4877         struct pciide_channel *cp = (struct pciide_channel *)chp;
 4878         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 4879         struct pciide_sis *sis = sc->sc_cookie;
WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for "
 4882             "channel %d 0x%x\n", chp->channel,
pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))),
DEBUG_PROBE);
sis_tim = 0;
idedma_ctl = 0;
 4887         /* setup DMA if needed */
pciide_channel_dma_setup(cp);
 4890         for (drive = 0; drive < 2; drive++) {
drvp = &chp->ch_drive[drive];
 4892                 /* If no drive, skip */
 4893                 if ((drvp->drive_flags & DRIVE) == 0)
 4894                         continue;
 4895                 /* add timing values, setup DMA if needed */
 4896                 if ((drvp->drive_flags & DRIVE_DMA) == 0 &&
 4897                     (drvp->drive_flags & DRIVE_UDMA) == 0)
 4898                         goto pio;
 4900                 if (drvp->drive_flags & DRIVE_UDMA) {
 4901                         /* use Ultra/DMA */
drvp->drive_flags &= ~DRIVE_DMA;
 4903                         if (pciide_pci_read(sc->sc_pc, sc->sc_tag,
SIS_REG_CBL) & SIS_REG_CBL_33(chp->channel)) {
 4905                                 if (drvp->UDMA_mode > 2)
drvp->UDMA_mode = 2;
 4907                         }
 4908                         switch (sis->sis_type) {
 4909                         case SIS_TYPE_66:
 4910                         case SIS_TYPE_100OLD:
sis_tim |= sis_udma66_tim[drvp->UDMA_mode] <<
SIS_TIM66_UDMA_TIME_OFF(drive);
 4913                                 break;
 4914                         case SIS_TYPE_100NEW:
sis_tim |=
sis_udma100new_tim[drvp->UDMA_mode] <<
SIS_TIM100_UDMA_TIME_OFF(drive);
 4918                                 break;
 4919                         case SIS_TYPE_133OLD:
sis_tim |=
sis_udma133old_tim[drvp->UDMA_mode] <<
SIS_TIM100_UDMA_TIME_OFF(drive);
 4923                                 break;
 4924                         default:
printf("unknown SiS IDE type %d\n",
sis->sis_type);
 4927                         }
 4928                 } else {
 4929                         /*
 4930                          * use Multiword DMA
 4931                          * Timings will be used for both PIO and DMA,
 4932                          * so adjust DMA mode if needed
 4933                          */
 4934                         if (drvp->PIO_mode > (drvp->DMA_mode + 2))
drvp->PIO_mode = drvp->DMA_mode + 2;
 4936                         if (drvp->DMA_mode + 2 > (drvp->PIO_mode))
drvp->DMA_mode = (drvp->PIO_mode > 2) ?
drvp->PIO_mode - 2 : 0;
 4939                         if (drvp->DMA_mode == 0)
drvp->PIO_mode = 0;
 4941                 }
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
pio:            switch (sis->sis_type) {
 4944                 case SIS_TYPE_NOUDMA:
 4945                 case SIS_TYPE_66:
 4946                 case SIS_TYPE_100OLD:
sis_tim |= sis_pio_act[drvp->PIO_mode] <<
SIS_TIM66_ACT_OFF(drive);
sis_tim |= sis_pio_rec[drvp->PIO_mode] <<
SIS_TIM66_REC_OFF(drive);
 4951                         break;
 4952                 case SIS_TYPE_100NEW:
 4953                 case SIS_TYPE_133OLD:
sis_tim |= sis_pio_act[drvp->PIO_mode] <<
SIS_TIM100_ACT_OFF(drive);
sis_tim |= sis_pio_rec[drvp->PIO_mode] <<
SIS_TIM100_REC_OFF(drive);
 4958                         break;
 4959                 default:
printf("unknown SiS IDE type %d\n",
sis->sis_type);
 4962                 }
 4963         }
WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for "
 4965             "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE);
pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim);
 4967         if (idedma_ctl != 0) {
 4968                 /* Add software bits in status register */
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CTL(chp->channel), idedma_ctl);
 4971         }
pciide_print_modes(cp);
 4973 }
 4975 void
natsemi_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
 4977 {
 4978         struct pciide_channel *cp;
 4979         int channel;
pcireg_t interface, ctl;
bus_size_t cmdsize, ctlsize;
printf(": DMA");
pciide_mapreg_dma(sc, pa);
sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16;
 4987         if (sc->sc_dma_ok) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK;
sc->sc_wdcdev.irqack = natsemi_irqack;
 4990         }
pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CCBT, 0xb7);
 4994         /*
 4995          * Mask off interrupts from both channels, appropriate channel(s)
 4996          * will be unmasked later.
 4997          */
pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2,
pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2) |
NATSEMI_CHMASK(0) | NATSEMI_CHMASK(1));
sc->sc_wdcdev.PIO_cap = 4;
sc->sc_wdcdev.DMA_cap = 2;
sc->sc_wdcdev.set_modes = natsemi_setup_channel;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag,
PCI_CLASS_REG));
interface &= ~PCIIDE_CHANSTATUS_EN;     /* Reserved on PC87415 */
pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
 5013         /* If we're in PCIIDE mode, unmask INTA, otherwise mask it. */
ctl = pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL1);
 5015         if (interface & (PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1)))
ctl &= ~NATSEMI_CTRL1_INTAMASK;
 5017         else
ctl |= NATSEMI_CTRL1_INTAMASK;
pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL1, ctl);
 5021         for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
cp = &sc->pciide_channels[channel];
 5023                 if (pciide_chansetup(sc, channel, interface) == 0)
 5024                         continue;
pciide_map_compat_intr(pa, cp, channel, interface);
 5027                 if (cp->hw_ok == 0)
 5028                         continue;
pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
natsemi_pci_intr);
 5032                 if (cp->hw_ok == 0) {
pciide_unmap_compat_intr(pa, cp, channel, interface);
 5034                         continue;
 5035                 }
natsemi_setup_channel(&cp->wdc_channel);
 5037         }
 5038 }
 5040 void
natsemi_setup_channel(struct channel_softc *chp)
 5042 {
 5043         struct ata_drive_datas *drvp;
 5044         int drive, ndrives = 0;
u_int32_t idedma_ctl = 0;
 5046         struct pciide_channel *cp = (struct pciide_channel *)chp;
 5047         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
u_int8_t tim;
 5050         /* setup DMA if needed */
pciide_channel_dma_setup(cp);
 5053         for (drive = 0; drive < 2; drive++) {
drvp = &chp->ch_drive[drive];
 5055                 /* If no drive, skip */
 5056                 if ((drvp->drive_flags & DRIVE) == 0)
 5057                         continue;
ndrives++;
 5060                 /* add timing values, setup DMA if needed */
 5061                 if ((drvp->drive_flags & DRIVE_DMA) == 0) {
tim = natsemi_pio_pulse[drvp->PIO_mode] |
 5063                             (natsemi_pio_recover[drvp->PIO_mode] << 4);
 5064                 } else {
 5065                         /*
 5066                          * use Multiword DMA
 5067                          * Timings will be used for both PIO and DMA,
 5068                          * so adjust DMA mode if needed
 5069                          */
 5070                         if (drvp->PIO_mode >= 3 &&
 5071                             (drvp->DMA_mode + 2) > drvp->PIO_mode) {
drvp->DMA_mode = drvp->PIO_mode - 2;
 5073                         }
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
tim = natsemi_dma_pulse[drvp->DMA_mode] |
 5076                             (natsemi_dma_recover[drvp->DMA_mode] << 4);
 5077                 }
pciide_pci_write(sc->sc_pc, sc->sc_tag,
NATSEMI_RTREG(chp->channel, drive), tim);
pciide_pci_write(sc->sc_pc, sc->sc_tag,
NATSEMI_WTREG(chp->channel, drive), tim);
 5083         }
 5084         if (idedma_ctl != 0) {
 5085                 /* Add software bits in status register */
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CTL(chp->channel), idedma_ctl);
 5088         }
 5089         if (ndrives > 0) {
 5090                 /* Unmask the channel if at least one drive is found */
pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2,
pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2) &
 5093                     ~(NATSEMI_CHMASK(chp->channel)));
 5094         }
pciide_print_modes(cp);
 5098         /* Go ahead and ack interrupts generated during probe. */
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CTL(chp->channel),
bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CTL(chp->channel)));
 5103 }
 5105 void
natsemi_irqack(struct channel_softc *chp)
 5107 {
 5108         struct pciide_channel *cp = (struct pciide_channel *)chp;
 5109         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
u_int8_t clr;
 5112         /* The "clear" bits are in the wrong register *sigh* */
clr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CMD(chp->channel));
clr |= bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CTL(chp->channel)) &
 5117             (IDEDMA_CTL_ERR | IDEDMA_CTL_INTR);
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CMD(chp->channel), clr);
 5120 }
 5122 int
natsemi_pci_intr(void *arg)
 5124 {
 5125         struct pciide_softc *sc = arg;
 5126         struct pciide_channel *cp;
 5127         struct channel_softc *wdc_cp;
 5128         int i, rv, crv;
u_int8_t msk;
rv = 0;
msk = pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2);
 5133         for (i = 0; i < sc->sc_wdcdev.nchannels; i++) {
cp = &sc->pciide_channels[i];
wdc_cp = &cp->wdc_channel;
 5137                 /* If a compat channel skip. */
 5138                 if (cp->compat)
 5139                         continue;
 5141                 /* If this channel is masked, skip it. */
 5142                 if (msk & NATSEMI_CHMASK(i))
 5143                         continue;
 5145                 if (pciide_intr_flag(cp) == 0)
 5146                         continue;
crv = wdcintr(wdc_cp);
 5149                 if (crv == 0)
 5150                         ;               /* leave rv alone */
 5151                 else if (crv == 1)
rv = 1;         /* claim the intr */
 5153                 else if (rv == 0)       /* crv should be -1 in this case */
rv = crv;       /* if we've done no better, take it */
 5155         }
 5156         return (rv);
 5157 }
 5159 void
ns_scx200_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
 5161 {
 5162         struct pciide_channel *cp;
 5163         int channel;
pcireg_t interface = PCI_INTERFACE(pa->pa_class);
bus_size_t cmdsize, ctlsize;
printf(": DMA");
pciide_mapreg_dma(sc, pa);
sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
WDC_CAPABILITY_MODE;
 5172         if (sc->sc_dma_ok) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
sc->sc_wdcdev.irqack = pciide_irqack;
 5176         }
sc->sc_wdcdev.PIO_cap = 4;
sc->sc_wdcdev.DMA_cap = 2;
sc->sc_wdcdev.UDMA_cap = 2;
sc->sc_wdcdev.set_modes = ns_scx200_setup_channel;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
 5185         /*
 5186          * Soekris net4801 errata 0003:
 5187          *
 5188          * The SC1100 built in busmaster IDE controller is pretty standard,
 5189          * but have two bugs: data transfers need to be dword aligned and
 5190          * it cannot do an exact 64Kbyte data transfer.
 5191          *
 5192          * Assume that reducing maximum segment size by one page
 5193          * will be enough, and restrict boundary too for extra certainty.
 5194          */
 5195         if (sc->sc_pp->ide_product == PCI_PRODUCT_NS_SCx200_IDE) {
sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX - PAGE_SIZE;
sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_MAX - PAGE_SIZE;
 5198         }
 5200         /*
 5201          * This chip seems to be unable to do one-sector transfers
 5202          * using DMA.
 5203          */
sc->sc_wdcdev.quirks = WDC_QUIRK_NOSHORTDMA;
pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
 5208         for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
cp = &sc->pciide_channels[channel];
 5210                 if (pciide_chansetup(sc, channel, interface) == 0)
 5211                         continue;
pciide_map_compat_intr(pa, cp, channel, interface);
 5213                 if (cp->hw_ok == 0)
 5214                         continue;
pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
pciide_pci_intr);
 5217                 if (cp->hw_ok == 0) {
pciide_unmap_compat_intr(pa, cp, channel, interface);
 5219                         continue;
 5220                 }
sc->sc_wdcdev.set_modes(&cp->wdc_channel);
 5222         }
 5223 }
 5225 void
ns_scx200_setup_channel(struct channel_softc *chp)
 5227 {
 5228         struct ata_drive_datas *drvp;
 5229         int drive, mode;
u_int32_t idedma_ctl;
 5231         struct pciide_channel *cp = (struct pciide_channel*)chp;
 5232         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 5233         int channel = chp->channel;
 5234         int pioformat;
pcireg_t piotim, dmatim;
 5237         /* Setup DMA if needed */
pciide_channel_dma_setup(cp);
idedma_ctl = 0;
pioformat = (pci_conf_read(sc->sc_pc, sc->sc_tag,
SCx200_TIM_DMA(0, 0)) >> SCx200_PIOFORMAT_SHIFT) & 0x01;
WDCDEBUG_PRINT(("%s: pio format %d\n", __func__, pioformat),
DEBUG_PROBE);
 5247         /* Per channel settings */
 5248         for (drive = 0; drive < 2; drive++) {
drvp = &chp->ch_drive[drive];
 5251                 /* If no drive, skip */
 5252                 if ((drvp->drive_flags & DRIVE) == 0)
 5253                         continue;
piotim = pci_conf_read(sc->sc_pc, sc->sc_tag,
SCx200_TIM_PIO(channel, drive));
dmatim = pci_conf_read(sc->sc_pc, sc->sc_tag,
SCx200_TIM_DMA(channel, drive));
WDCDEBUG_PRINT(("%s:%d:%d: piotim=0x%x, dmatim=0x%x\n",
sc->sc_wdcdev.sc_dev.dv_xname, channel, drive,
piotim, dmatim), DEBUG_PROBE);
 5263                 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) != 0 &&
 5264                     (drvp->drive_flags & DRIVE_UDMA) != 0) {
 5265                         /* Setup UltraDMA mode */
drvp->drive_flags &= ~DRIVE_DMA;
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
dmatim = scx200_udma33[drvp->UDMA_mode];
mode = drvp->PIO_mode;
 5270                 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) != 0 &&
 5271                     (drvp->drive_flags & DRIVE_DMA) != 0) {
 5272                         /* Setup multiword DMA mode */
drvp->drive_flags &= ~DRIVE_UDMA;
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
dmatim = scx200_dma33[drvp->DMA_mode];
 5277                         /* mode = min(pio, dma + 2) */
 5278                         if (drvp->PIO_mode <= (drvp->DMA_mode + 2))
mode = drvp->PIO_mode;
 5280                         else
mode = drvp->DMA_mode + 2;
 5282                 } else {
mode = drvp->PIO_mode;
 5284                 }
 5286                 /* Setup PIO mode */
drvp->PIO_mode = mode;
 5288                 if (mode < 2)
drvp->DMA_mode = 0;
 5290                 else
drvp->DMA_mode = mode - 2;
piotim = scx200_pio33[pioformat][drvp->PIO_mode];
WDCDEBUG_PRINT(("%s:%d:%d: new piotim=0x%x, dmatim=0x%x\n",
sc->sc_wdcdev.sc_dev.dv_xname, channel, drive,
piotim, dmatim), DEBUG_PROBE);
pci_conf_write(sc->sc_pc, sc->sc_tag,
SCx200_TIM_PIO(channel, drive), piotim);
pci_conf_write(sc->sc_pc, sc->sc_tag,
SCx200_TIM_DMA(channel, drive), dmatim);
 5303         }
 5305         if (idedma_ctl != 0) {
 5306                 /* Add software bits in status register */
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CTL(channel), idedma_ctl);
 5309         }
pciide_print_modes(cp);
 5312 }
 5314 void
acer_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
 5316 {
 5317         struct pciide_channel *cp;
 5318         int channel;
pcireg_t cr, interface;
bus_size_t cmdsize, ctlsize;
 5321         int rev = sc->sc_rev;
printf(": DMA");
pciide_mapreg_dma(sc, pa);
sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
WDC_CAPABILITY_MODE;
 5328         if (sc->sc_dma_ok) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA;
 5330                 if (rev >= 0x20) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
 5332                         if (rev >= 0xC4)
sc->sc_wdcdev.UDMA_cap = 5;
 5334                         else if (rev >= 0xC2)
sc->sc_wdcdev.UDMA_cap = 4;
 5336                         else
sc->sc_wdcdev.UDMA_cap = 2;
 5338                 }
sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
sc->sc_wdcdev.irqack = pciide_irqack;
 5341         }
sc->sc_wdcdev.PIO_cap = 4;
sc->sc_wdcdev.DMA_cap = 2;
sc->sc_wdcdev.set_modes = acer_setup_channel;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC,
 5350             (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) |
ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE);
 5353         /* Enable "microsoft register bits" R/W. */
pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3,
pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI);
pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1,
pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) &
 5358             ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1)));
pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2,
pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) &
 5361             ~ACER_CHANSTATUSREGS_RO);
cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG);
cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT);
pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr);
 5365         /* Don't use cr, re-read the real register content instead */
interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag,
PCI_CLASS_REG));
pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
 5371         /* From linux: enable "Cable Detection" */
 5372         if (rev >= 0xC2)
pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B,
pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B)
 5375                     | ACER_0x4B_CDETECT);
 5377         for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
cp = &sc->pciide_channels[channel];
 5379                 if (pciide_chansetup(sc, channel, interface) == 0)
 5380                         continue;
 5381                 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) {
printf("%s: %s ignored (disabled)\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
 5384                         continue;
 5385                 }
pciide_map_compat_intr(pa, cp, channel, interface);
 5387                 if (cp->hw_ok == 0)
 5388                         continue;
pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
 5390                     (rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr);
 5391                 if (cp->hw_ok == 0) {
pciide_unmap_compat_intr(pa, cp, channel, interface);
 5393                         continue;
 5394                 }
 5395                 if (pciide_chan_candisable(cp)) {
cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT);
pci_conf_write(sc->sc_pc, sc->sc_tag,
PCI_CLASS_REG, cr);
 5399                 }
 5400                 if (cp->hw_ok == 0) {
pciide_unmap_compat_intr(pa, cp, channel, interface);
 5402                         continue;
 5403                 }
acer_setup_channel(&cp->wdc_channel);
 5405         }
 5406 }
 5408 void
acer_setup_channel(struct channel_softc *chp)
 5410 {
 5411         struct ata_drive_datas *drvp;
 5412         int drive;
u_int32_t acer_fifo_udma;
u_int32_t idedma_ctl;
 5415         struct pciide_channel *cp = (struct pciide_channel *)chp;
 5416         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
idedma_ctl = 0;
acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA);
WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n",
acer_fifo_udma), DEBUG_PROBE);
 5422         /* setup DMA if needed */
pciide_channel_dma_setup(cp);
 5425         if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) &
DRIVE_UDMA) {       /* check 80 pins cable */
 5427                 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) &
ACER_0x4A_80PIN(chp->channel)) {
WDCDEBUG_PRINT(("%s:%d: 80-wire cable not detected\n",
sc->sc_wdcdev.sc_dev.dv_xname, chp->channel),
DEBUG_PROBE);
 5432                         if (chp->ch_drive[0].UDMA_mode > 2)
chp->ch_drive[0].UDMA_mode = 2;
 5434                         if (chp->ch_drive[1].UDMA_mode > 2)
chp->ch_drive[1].UDMA_mode = 2;
 5436                 }
 5437         }
 5439         for (drive = 0; drive < 2; drive++) {
drvp = &chp->ch_drive[drive];
 5441                 /* If no drive, skip */
 5442                 if ((drvp->drive_flags & DRIVE) == 0)
 5443                         continue;
WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for "
 5445                     "channel %d drive %d 0x%x\n", chp->channel, drive,
pciide_pci_read(sc->sc_pc, sc->sc_tag,
ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE);
 5448                 /* clear FIFO/DMA mode */
acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) |
ACER_UDMA_EN(chp->channel, drive) |
ACER_UDMA_TIM(chp->channel, drive, 0x7));
 5453                 /* add timing values, setup DMA if needed */
 5454                 if ((drvp->drive_flags & DRIVE_DMA) == 0 &&
 5455                     (drvp->drive_flags & DRIVE_UDMA) == 0) {
acer_fifo_udma |=
ACER_FTH_OPL(chp->channel, drive, 0x1);
 5458                         goto pio;
 5459                 }
acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2);
 5462                 if (drvp->drive_flags & DRIVE_UDMA) {
 5463                         /* use Ultra/DMA */
drvp->drive_flags &= ~DRIVE_DMA;
acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive);
acer_fifo_udma |=
ACER_UDMA_TIM(chp->channel, drive,
acer_udma[drvp->UDMA_mode]);
 5469                         /* XXX disable if one drive < UDMA3 ? */
 5470                         if (drvp->UDMA_mode >= 3) {
pciide_pci_write(sc->sc_pc, sc->sc_tag,
ACER_0x4B,
pciide_pci_read(sc->sc_pc, sc->sc_tag,
ACER_0x4B) | ACER_0x4B_UDMA66);
 5475                         }
 5476                 } else {
 5477                         /*
 5478                          * use Multiword DMA
 5479                          * Timings will be used for both PIO and DMA,
 5480                          * so adjust DMA mode if needed
 5481                          */
 5482                         if (drvp->PIO_mode > (drvp->DMA_mode + 2))
drvp->PIO_mode = drvp->DMA_mode + 2;
 5484                         if (drvp->DMA_mode + 2 > (drvp->PIO_mode))
drvp->DMA_mode = (drvp->PIO_mode > 2) ?
drvp->PIO_mode - 2 : 0;
 5487                         if (drvp->DMA_mode == 0)
drvp->PIO_mode = 0;
 5489                 }
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
pio:            pciide_pci_write(sc->sc_pc, sc->sc_tag,
ACER_IDETIM(chp->channel, drive),
acer_pio[drvp->PIO_mode]);
 5494         }
WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n",
acer_fifo_udma), DEBUG_PROBE);
pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma);
 5498         if (idedma_ctl != 0) {
 5499                 /* Add software bits in status register */
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CTL(chp->channel), idedma_ctl);
 5502         }
pciide_print_modes(cp);
 5504 }
 5506 int
acer_pci_intr(void *arg)
 5508 {
 5509         struct pciide_softc *sc = arg;
 5510         struct pciide_channel *cp;
 5511         struct channel_softc *wdc_cp;
 5512         int i, rv, crv;
u_int32_t chids;
rv = 0;
chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS);
 5517         for (i = 0; i < sc->sc_wdcdev.nchannels; i++) {
cp = &sc->pciide_channels[i];
wdc_cp = &cp->wdc_channel;
 5520                 /* If a compat channel skip. */
 5521                 if (cp->compat)
 5522                         continue;
 5523                 if (chids & ACER_CHIDS_INT(i)) {
crv = wdcintr(wdc_cp);
 5525                         if (crv == 0)
printf("%s:%d: bogus intr\n",
sc->sc_wdcdev.sc_dev.dv_xname, i);
 5528                         else
rv = 1;
 5530                 }
 5531         }
 5532         return (rv);
 5533 }
 5535 void
hpt_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
 5537 {
 5538         struct pciide_channel *cp;
 5539         int i, compatchan, revision;
pcireg_t interface;
bus_size_t cmdsize, ctlsize;
revision = sc->sc_rev;
 5545         /*
 5546          * when the chip is in native mode it identifies itself as a
 5547          * 'misc mass storage'. Fake interface in this case.
 5548          */
 5549         if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) {
interface = PCI_INTERFACE(pa->pa_class);
 5551         } else {
interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
PCIIDE_INTERFACE_PCI(0);
 5554                 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 &&
 5555                    (revision == HPT370_REV || revision == HPT370A_REV ||
revision == HPT372_REV)) ||
sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A ||
sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 ||
sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 ||
sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374)
interface |= PCIIDE_INTERFACE_PCI(1);
 5562         }
printf(": DMA");
pciide_mapreg_dma(sc, pa);
printf("\n");
sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
WDC_CAPABILITY_MODE;
 5569         if (sc->sc_dma_ok) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
sc->sc_wdcdev.irqack = pciide_irqack;
 5573         }
sc->sc_wdcdev.PIO_cap = 4;
sc->sc_wdcdev.DMA_cap = 2;
sc->sc_wdcdev.set_modes = hpt_setup_channel;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
 5579         if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 &&
revision == HPT366_REV) {
sc->sc_wdcdev.UDMA_cap = 4;
 5582                 /*
 5583                  * The 366 has 2 PCI IDE functions, one for primary and one
 5584                  * for secondary. So we need to call pciide_mapregs_compat()
 5585                  * with the real channel
 5586                  */
 5587                 if (pa->pa_function == 0) {
compatchan = 0;
 5589                 } else if (pa->pa_function == 1) {
compatchan = 1;
 5591                 } else {
printf("%s: unexpected PCI function %d\n",
sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function);
 5594                         return;
 5595                 }
sc->sc_wdcdev.nchannels = 1;
 5597         } else {
sc->sc_wdcdev.nchannels = 2;
 5599                 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A ||
sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 ||
sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 ||
sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374)
sc->sc_wdcdev.UDMA_cap = 6;
 5604                 else if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366) {
 5605                         if (revision == HPT372_REV)
sc->sc_wdcdev.UDMA_cap = 6;
 5607                         else
sc->sc_wdcdev.UDMA_cap = 5;
 5609                 }
 5610         }
 5611         for (i = 0; i < sc->sc_wdcdev.nchannels; i++) {
cp = &sc->pciide_channels[i];
 5613                 if (sc->sc_wdcdev.nchannels > 1) {
compatchan = i;
 5615                         if((pciide_pci_read(sc->sc_pc, sc->sc_tag,
HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) {
printf("%s: %s ignored (disabled)\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
 5619                                 continue;
 5620                         }
 5621                 }
 5622                 if (pciide_chansetup(sc, i, interface) == 0)
 5623                         continue;
 5624                 if (interface & PCIIDE_INTERFACE_PCI(i)) {
cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize,
 5626                             &ctlsize, hpt_pci_intr);
 5627                 } else {
cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan,
 5629                             &cmdsize, &ctlsize);
 5630                 }
 5631                 if (cp->hw_ok == 0)
 5632                         return;
cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot;
cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh;
wdcattach(&cp->wdc_channel);
hpt_setup_channel(&cp->wdc_channel);
 5637         }
 5638         if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 &&
 5639             (revision == HPT370_REV || revision == HPT370A_REV ||
revision == HPT372_REV)) ||
sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A ||
sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 ||
sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 ||
sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) {
 5645                 /*
 5646                  * Turn off fast interrupts
 5647                  */
pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT370_CTRL2(0),
pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT370_CTRL2(0)) &
 5650                     ~(HPT370_CTRL2_FASTIRQ | HPT370_CTRL2_HIRQ));
pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT370_CTRL2(1),
pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT370_CTRL2(1)) &
 5653                 ~(HPT370_CTRL2_FASTIRQ | HPT370_CTRL2_HIRQ));
 5655                 /*
 5656                  * HPT370 and highter has a bit to disable interrupts,
 5657                  * make sure to clear it
 5658                  */
pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL,
pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) &
 5661                     ~HPT_CSEL_IRQDIS);
 5662         }
 5663         /* set clocks, etc (mandatory on 372/4, optional otherwise) */
 5664         if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A ||
sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 ||
sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 ||
sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374 ||
 5668             (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 &&
revision == HPT372_REV))
pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_SC2,
 5671                     (pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_SC2) &
HPT_SC2_MAEN) | HPT_SC2_OSC_EN);
 5674         return;
 5675 }
 5677 void
hpt_setup_channel(struct channel_softc *chp)
 5679 {
 5680         struct ata_drive_datas *drvp;
 5681         int drive;
 5682         int cable;
u_int32_t before, after;
u_int32_t idedma_ctl;
 5685         struct pciide_channel *cp = (struct pciide_channel *)chp;
 5686         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 5687         int revision = sc->sc_rev;
u_int32_t *tim_pio, *tim_dma, *tim_udma;
cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL);
 5692         /* setup DMA if needed */
pciide_channel_dma_setup(cp);
idedma_ctl = 0;
 5697         switch (sc->sc_pp->ide_product) {
 5698         case PCI_PRODUCT_TRIONES_HPT366:
 5699                 if (revision == HPT370_REV ||
revision == HPT370A_REV) {
tim_pio = hpt370_pio;
tim_dma = hpt370_dma;
tim_udma = hpt370_udma;
 5704                 } else if (revision == HPT372_REV) {
tim_pio = hpt372_pio;
tim_dma = hpt372_dma;
tim_udma = hpt372_udma;
 5708                 } else {
tim_pio = hpt366_pio;
tim_dma = hpt366_dma;
tim_udma = hpt366_udma;
 5712                 }
 5713                 break;
 5714         case PCI_PRODUCT_TRIONES_HPT372A:
 5715         case PCI_PRODUCT_TRIONES_HPT302:
 5716         case PCI_PRODUCT_TRIONES_HPT371:
tim_pio = hpt372_pio;
tim_dma = hpt372_dma;
tim_udma = hpt372_udma;
 5720                 break;
 5721         case PCI_PRODUCT_TRIONES_HPT374:
tim_pio = hpt374_pio;
tim_dma = hpt374_dma;
tim_udma = hpt374_udma;
 5725                 break;
 5726         default:
printf("%s: no known timing values\n",
sc->sc_wdcdev.sc_dev.dv_xname);
 5729                 goto end;
 5730         }
 5732         /* Per drive settings */
 5733         for (drive = 0; drive < 2; drive++) {
drvp = &chp->ch_drive[drive];
 5735                 /* If no drive, skip */
 5736                 if ((drvp->drive_flags & DRIVE) == 0)
 5737                         continue;
before = pci_conf_read(sc->sc_pc, sc->sc_tag,
HPT_IDETIM(chp->channel, drive));
 5741                 /* add timing values, setup DMA if needed */
 5742                 if (drvp->drive_flags & DRIVE_UDMA) {
 5743                         /* use Ultra/DMA */
drvp->drive_flags &= ~DRIVE_DMA;
 5745                         if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 &&
drvp->UDMA_mode > 2) {
WDCDEBUG_PRINT(("%s(%s:%d:%d): 80-wire "
 5748                                     "cable not detected\n", drvp->drive_name,
sc->sc_wdcdev.sc_dev.dv_xname,
chp->channel, drive), DEBUG_PROBE);
drvp->UDMA_mode = 2;
 5752                         }
after = tim_udma[drvp->UDMA_mode];
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
 5755                 } else if (drvp->drive_flags & DRIVE_DMA) {
 5756                         /*
 5757                          * use Multiword DMA.
 5758                          * Timings will be used for both PIO and DMA, so adjust
 5759                          * DMA mode if needed
 5760                          */
 5761                         if (drvp->PIO_mode >= 3 &&
 5762                             (drvp->DMA_mode + 2) > drvp->PIO_mode) {
drvp->DMA_mode = drvp->PIO_mode - 2;
 5764                         }
after = tim_dma[drvp->DMA_mode];
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
 5767                 } else {
 5768                         /* PIO only */
after = tim_pio[drvp->PIO_mode];
 5770                 }
pci_conf_write(sc->sc_pc, sc->sc_tag,
HPT_IDETIM(chp->channel, drive), after);
WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x "
 5774                     "(BIOS 0x%08x)\n", sc->sc_wdcdev.sc_dev.dv_xname,
after, before), DEBUG_PROBE);
 5776         }
end:
 5778         if (idedma_ctl != 0) {
 5779                 /* Add software bits in status register */
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CTL(chp->channel), idedma_ctl);
 5782         }
pciide_print_modes(cp);
 5784 }
 5786 int
hpt_pci_intr(void *arg)
 5788 {
 5789         struct pciide_softc *sc = arg;
 5790         struct pciide_channel *cp;
 5791         struct channel_softc *wdc_cp;
 5792         int rv = 0;
 5793         int dmastat, i, crv;
 5795         for (i = 0; i < sc->sc_wdcdev.nchannels; i++) {
dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CTL(i));
 5798                 if((dmastat & (IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) !=
IDEDMA_CTL_INTR)
 5800                     continue;
cp = &sc->pciide_channels[i];
wdc_cp = &cp->wdc_channel;
crv = wdcintr(wdc_cp);
 5804                 if (crv == 0) {
printf("%s:%d: bogus intr\n",
sc->sc_wdcdev.sc_dev.dv_xname, i);
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CTL(i), dmastat);
 5809                 } else
rv = 1;
 5811         }
 5812         return (rv);
 5813 }
 5815 /* Macros to test product */
 5816 #define PDC_IS_262(sc)                                                  \
 5817         ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20262 ||    \
 5818         (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20265  ||    \
 5819         (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20267)
 5820 #define PDC_IS_265(sc)                                                  \
 5821         ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20265 ||    \
 5822         (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20267  ||    \
 5823         (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20268  ||    \
 5824         (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20268R ||    \
 5825         (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269  ||    \
 5826         (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271  ||    \
 5827         (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275  ||    \
 5828         (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276  ||    \
 5829         (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277)
 5830 #define PDC_IS_268(sc)                                                  \
 5831         ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20268 ||    \
 5832         (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20268R ||    \
 5833         (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269  ||    \
 5834         (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271  ||    \
 5835         (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275  ||    \
 5836         (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276  ||    \
 5837         (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277)
 5838 #define PDC_IS_269(sc)                                                  \
 5839         ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269 ||    \
 5840         (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271  ||    \
 5841         (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275  ||    \
 5842         (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276  ||    \
 5843         (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277)
 5845 static INLINE u_int8_t
pdc268_config_read(struct channel_softc *chp, int index)
 5847 {
 5848         struct pciide_channel *cp = (struct pciide_channel *)chp;
 5849         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 5850         int channel = chp->channel;
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
PDC268_INDEX(channel), index);
 5854         return (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh,
PDC268_DATA(channel)));
 5856 }
 5858 /* unused */
 5859 static __inline void
 5860 pdc268_config_write(struct channel_softc *chp, int index, u_int8_t value)
 5861 {
 5862         struct pciide_channel *cp = (struct pciide_channel *)chp;
 5863         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 5864         int channel = chp->channel;
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
PDC268_INDEX(channel), index);
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
PDC268_DATA(channel), value);
 5870 }
 5872 void
pdc202xx_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
 5874 {
 5875         struct pciide_channel *cp;
 5876         int channel;
pcireg_t interface, st, mode;
bus_size_t cmdsize, ctlsize;
 5880         if (!PDC_IS_268(sc)) {
st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE);
WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n",
st), DEBUG_PROBE);
 5884         }
 5886         /* turn off  RAID mode */
 5887         if (!PDC_IS_268(sc))
st &= ~PDC2xx_STATE_IDERAID;
 5890         /*
 5891          * can't rely on the PCI_CLASS_REG content if the chip was in raid
 5892          * mode. We have to fake interface
 5893          */
interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1);
 5895         if (PDC_IS_268(sc) || (st & PDC2xx_STATE_NATIVE))
interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
printf(": DMA");
pciide_mapreg_dma(sc, pa);
sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
WDC_CAPABILITY_MODE;
 5903         if (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20246 ||
PDC_IS_262(sc))
sc->sc_wdcdev.cap |= WDC_CAPABILITY_NO_ATAPI_DMA;
 5906         if (sc->sc_dma_ok) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
sc->sc_wdcdev.irqack = pciide_irqack;
 5910         }
sc->sc_wdcdev.PIO_cap = 4;
sc->sc_wdcdev.DMA_cap = 2;
 5913         if (PDC_IS_269(sc))
sc->sc_wdcdev.UDMA_cap = 6;
 5915         else if (PDC_IS_265(sc))
sc->sc_wdcdev.UDMA_cap = 5;
 5917         else if (PDC_IS_262(sc))
sc->sc_wdcdev.UDMA_cap = 4;
 5919         else
sc->sc_wdcdev.UDMA_cap = 2;
sc->sc_wdcdev.set_modes = PDC_IS_268(sc) ?
pdc20268_setup_channel : pdc202xx_setup_channel;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
 5926         if (PDC_IS_262(sc)) {
sc->sc_wdcdev.dma_start = pdc20262_dma_start;
sc->sc_wdcdev.dma_finish = pdc20262_dma_finish;
 5929         }
pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
 5932         if (!PDC_IS_268(sc)) {
 5933                 /* setup failsafe defaults */
mode = 0;
mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]);
mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]);
mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]);
mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]);
 5939                 for (channel = 0;
channel < sc->sc_wdcdev.nchannels;
channel++) {
WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d "
 5943                             "drive 0 initial timings  0x%x, now 0x%x\n",
channel, pci_conf_read(sc->sc_pc, sc->sc_tag,
PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp),
DEBUG_PROBE);
pci_conf_write(sc->sc_pc, sc->sc_tag,
PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp);
WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d "
 5950                             "drive 1 initial timings  0x%x, now 0x%x\n",
channel, pci_conf_read(sc->sc_pc, sc->sc_tag,
PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE);
pci_conf_write(sc->sc_pc, sc->sc_tag,
PDC2xx_TIM(channel, 1), mode);
 5955                 }
mode = PDC2xx_SCR_DMA;
 5958                 if (PDC_IS_262(sc)) {
mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT);
 5960                 } else {
 5961                         /* the BIOS set it up this way */
mode = PDC2xx_SCR_SET_GEN(mode, 0x1);
 5963                 }
mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */
mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */
WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR  0x%x, "
 5967                     "now 0x%x\n",
bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh,
PDC2xx_SCR),
mode), DEBUG_PROBE);
bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh,
PDC2xx_SCR, mode);
 5974                 /* controller initial state register is OK even without BIOS */
 5975                 /* Set DMA mode to IDE DMA compatibility */
mode =
bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM);
WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode),
DEBUG_PROBE);
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM,
mode | 0x1);
mode =
bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM);
WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE);
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM,
mode | 0x1);
 5987         }
 5989         for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
cp = &sc->pciide_channels[channel];
 5991                 if (pciide_chansetup(sc, channel, interface) == 0)
 5992                         continue;
 5993                 if (!PDC_IS_268(sc) && (st & (PDC_IS_262(sc) ?
PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) {
printf("%s: %s ignored (disabled)\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
 5997                         continue;
 5998                 }
pciide_map_compat_intr(pa, cp, channel, interface);
 6000                 if (cp->hw_ok == 0)
 6001                         continue;
 6002                 if (PDC_IS_265(sc))
pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
pdc20265_pci_intr);
 6005                 else
pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
pdc202xx_pci_intr);
 6008                 if (cp->hw_ok == 0) {
pciide_unmap_compat_intr(pa, cp, channel, interface);
 6010                         continue;
 6011                 }
 6012                 if (!PDC_IS_268(sc) && pciide_chan_candisable(cp)) {
st &= ~(PDC_IS_262(sc) ?
PDC262_STATE_EN(channel):PDC246_STATE_EN(channel));
pciide_unmap_compat_intr(pa, cp, channel, interface);
 6016                 }
 6017                 if (PDC_IS_268(sc))
pdc20268_setup_channel(&cp->wdc_channel);
 6019                 else
pdc202xx_setup_channel(&cp->wdc_channel);
 6021         }
 6022         if (!PDC_IS_268(sc)) {
WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state "
 6024                     "0x%x\n", st), DEBUG_PROBE);
pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st);
 6026         }
 6027         return;
 6028 }
 6030 void
pdc202xx_setup_channel(struct channel_softc *chp)
 6032 {
 6033         struct ata_drive_datas *drvp;
 6034         int drive;
pcireg_t mode, st;
u_int32_t idedma_ctl, scr, atapi;
 6037         struct pciide_channel *cp = (struct pciide_channel *)chp;
 6038         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 6039         int channel = chp->channel;
 6041         /* setup DMA if needed */
pciide_channel_dma_setup(cp);
idedma_ctl = 0;
WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n",
sc->sc_wdcdev.sc_dev.dv_xname,
bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)),
DEBUG_PROBE);
 6050         /* Per channel settings */
 6051         if (PDC_IS_262(sc)) {
scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh,
PDC262_U66);
st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE);
 6055                 /* Check cable */
 6056                 if ((st & PDC262_STATE_80P(channel)) != 0 &&
 6057                     ((chp->ch_drive[0].drive_flags & DRIVE_UDMA &&
chp->ch_drive[0].UDMA_mode > 2) ||
 6059                     (chp->ch_drive[1].drive_flags & DRIVE_UDMA &&
chp->ch_drive[1].UDMA_mode > 2))) {
WDCDEBUG_PRINT(("%s:%d: 80-wire cable not detected\n",
sc->sc_wdcdev.sc_dev.dv_xname, channel),
DEBUG_PROBE);
 6064                         if (chp->ch_drive[0].UDMA_mode > 2)
chp->ch_drive[0].UDMA_mode = 2;
 6066                         if (chp->ch_drive[1].UDMA_mode > 2)
chp->ch_drive[1].UDMA_mode = 2;
 6068                 }
 6069                 /* Trim UDMA mode */
 6070                 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA &&
chp->ch_drive[0].UDMA_mode <= 2) ||
 6072                     (chp->ch_drive[1].drive_flags & DRIVE_UDMA &&
chp->ch_drive[1].UDMA_mode <= 2)) {
 6074                         if (chp->ch_drive[0].UDMA_mode > 2)
chp->ch_drive[0].UDMA_mode = 2;
 6076                         if (chp->ch_drive[1].UDMA_mode > 2)
chp->ch_drive[1].UDMA_mode = 2;
 6078                 }
 6079                 /* Set U66 if needed */
 6080                 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA &&
chp->ch_drive[0].UDMA_mode > 2) ||
 6082                     (chp->ch_drive[1].drive_flags & DRIVE_UDMA &&
chp->ch_drive[1].UDMA_mode > 2))
scr |= PDC262_U66_EN(channel);
 6085                 else
scr &= ~PDC262_U66_EN(channel);
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
PDC262_U66, scr);
WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n",
sc->sc_wdcdev.sc_dev.dv_xname, channel,
bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh,
PDC262_ATAPI(channel))), DEBUG_PROBE);
 6093                 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI ||
chp->ch_drive[1].drive_flags & DRIVE_ATAPI) {
 6095                         if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) &&
 6096                             !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) &&
 6097                             (chp->ch_drive[1].drive_flags & DRIVE_DMA)) ||
 6098                             ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) &&
 6099                             !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) &&
 6100                             (chp->ch_drive[0].drive_flags & DRIVE_DMA)))
atapi = 0;
 6102                         else
atapi = PDC262_ATAPI_UDMA;
bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh,
PDC262_ATAPI(channel), atapi);
 6106                 }
 6107         }
 6108         for (drive = 0; drive < 2; drive++) {
drvp = &chp->ch_drive[drive];
 6110                 /* If no drive, skip */
 6111                 if ((drvp->drive_flags & DRIVE) == 0)
 6112                         continue;
mode = 0;
 6114                 if (drvp->drive_flags & DRIVE_UDMA) {
 6115                         /* use Ultra/DMA */
drvp->drive_flags &= ~DRIVE_DMA;
mode = PDC2xx_TIM_SET_MB(mode,
pdc2xx_udma_mb[drvp->UDMA_mode]);
mode = PDC2xx_TIM_SET_MC(mode,
pdc2xx_udma_mc[drvp->UDMA_mode]);
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
 6122                 } else if (drvp->drive_flags & DRIVE_DMA) {
mode = PDC2xx_TIM_SET_MB(mode,
pdc2xx_dma_mb[drvp->DMA_mode]);
mode = PDC2xx_TIM_SET_MC(mode,
pdc2xx_dma_mc[drvp->DMA_mode]);
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
 6128                 } else {
mode = PDC2xx_TIM_SET_MB(mode,
pdc2xx_dma_mb[0]);
mode = PDC2xx_TIM_SET_MC(mode,
pdc2xx_dma_mc[0]);
 6133                 }
mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]);
mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]);
 6136                 if (drvp->drive_flags & DRIVE_ATA)
mode |= PDC2xx_TIM_PRE;
mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY;
 6139                 if (drvp->PIO_mode >= 3) {
mode |= PDC2xx_TIM_IORDY;
 6141                         if (drive == 0)
mode |= PDC2xx_TIM_IORDYp;
 6143                 }
WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d "
 6145                     "timings 0x%x\n",
sc->sc_wdcdev.sc_dev.dv_xname,
chp->channel, drive, mode), DEBUG_PROBE);
pci_conf_write(sc->sc_pc, sc->sc_tag,
PDC2xx_TIM(chp->channel, drive), mode);
 6150         }
 6151         if (idedma_ctl != 0) {
 6152                 /* Add software bits in status register */
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CTL(channel), idedma_ctl);
 6155         }
pciide_print_modes(cp);
 6157 }
 6159 void
pdc20268_setup_channel(struct channel_softc *chp)
 6161 {
 6162         struct ata_drive_datas *drvp;
 6163         int drive, cable;
u_int32_t idedma_ctl;
 6165         struct pciide_channel *cp = (struct pciide_channel *)chp;
 6166         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 6167         int channel = chp->channel;
 6169         /* check 80 pins cable */
cable = pdc268_config_read(chp, 0x0b) & PDC268_CABLE;
 6172         /* setup DMA if needed */
pciide_channel_dma_setup(cp);
idedma_ctl = 0;
 6177         for (drive = 0; drive < 2; drive++) {
drvp = &chp->ch_drive[drive];
 6179                 /* If no drive, skip */
 6180                 if ((drvp->drive_flags & DRIVE) == 0)
 6181                         continue;
 6182                 if (drvp->drive_flags & DRIVE_UDMA) {
 6183                         /* use Ultra/DMA */
drvp->drive_flags &= ~DRIVE_DMA;
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
 6186                         if (cable && drvp->UDMA_mode > 2) {
WDCDEBUG_PRINT(("%s(%s:%d:%d): 80-wire "
 6188                                     "cable not detected\n", drvp->drive_name,
sc->sc_wdcdev.sc_dev.dv_xname,
channel, drive), DEBUG_PROBE);
drvp->UDMA_mode = 2;
 6192                         }
 6193                 } else if (drvp->drive_flags & DRIVE_DMA) {
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
 6195                 }
 6196         }
 6197         /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */
 6198         if (idedma_ctl != 0) {
 6199                 /* Add software bits in status register */
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CTL(channel), idedma_ctl);
 6202         }
pciide_print_modes(cp);
 6204 }
 6206 int
pdc202xx_pci_intr(void *arg)
 6208 {
 6209         struct pciide_softc *sc = arg;
 6210         struct pciide_channel *cp;
 6211         struct channel_softc *wdc_cp;
 6212         int i, rv, crv;
u_int32_t scr;
rv = 0;
scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR);
 6217         for (i = 0; i < sc->sc_wdcdev.nchannels; i++) {
cp = &sc->pciide_channels[i];
wdc_cp = &cp->wdc_channel;
 6220                 /* If a compat channel skip. */
 6221                 if (cp->compat)
 6222                         continue;
 6223                 if (scr & PDC2xx_SCR_INT(i)) {
crv = wdcintr(wdc_cp);
 6225                         if (crv == 0)
printf("%s:%d: bogus intr (reg 0x%x)\n",
sc->sc_wdcdev.sc_dev.dv_xname, i, scr);
 6228                         else
rv = 1;
 6230                 }
 6231         }
 6232         return (rv);
 6233 }
 6235 int
pdc20265_pci_intr(void *arg)
 6237 {
 6238         struct pciide_softc *sc = arg;
 6239         struct pciide_channel *cp;
 6240         struct channel_softc *wdc_cp;
 6241         int i, rv, crv;
u_int32_t dmastat;
rv = 0;
 6245         for (i = 0; i < sc->sc_wdcdev.nchannels; i++) {
cp = &sc->pciide_channels[i];
wdc_cp = &cp->wdc_channel;
 6248                 /* If a compat channel skip. */
 6249                 if (cp->compat)
 6250                         continue;
 6252                 /*
 6253                  * In case of shared IRQ check that the interrupt
 6254                  * was actually generated by this channel.
 6255                  * Only check the channel that is enabled.
 6256                  */
 6257                 if (cp->hw_ok && PDC_IS_268(sc)) {
 6258                         if ((pdc268_config_read(wdc_cp,
 6259                             0x0b) & PDC268_INTR) == 0)
 6260                                 continue;
 6261                 }
 6263                 /*
 6264                  * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously,
 6265                  * however it asserts INT in IDEDMA_CTL even for non-DMA ops.
 6266                  * So use it instead (requires 2 reg reads instead of 1,
 6267                  * but we can't do it another way).
 6268                  */
dmastat = bus_space_read_1(sc->sc_dma_iot,
sc->sc_dma_ioh, IDEDMA_CTL(i));
 6271                 if ((dmastat & IDEDMA_CTL_INTR) == 0)
 6272                         continue;
crv = wdcintr(wdc_cp);
 6275                 if (crv == 0)
printf("%s:%d: bogus intr\n",
sc->sc_wdcdev.sc_dev.dv_xname, i);
 6278                 else
rv = 1;
 6280         }
 6281         return (rv);
 6282 }
 6284 void
pdc20262_dma_start(void *v, int channel, int drive)
 6286 {
 6287         struct pciide_softc *sc = v;
 6288         struct pciide_dma_maps *dma_maps =
 6289             &sc->pciide_channels[channel].dma_maps[drive];
u_int8_t clock;
u_int32_t count;
 6293         if (dma_maps->dma_flags & WDC_DMA_LBA48) {
clock = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh,
PDC262_U66);
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
PDC262_U66, clock | PDC262_U66_EN(channel));
count = dma_maps->dmamap_xfer->dm_mapsize >> 1;
count |= dma_maps->dma_flags & WDC_DMA_READ ?
PDC262_ATAPI_LBA48_READ : PDC262_ATAPI_LBA48_WRITE;
bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh,
PDC262_ATAPI(channel), count);
 6303         }
pciide_dma_start(v, channel, drive);
 6306 }
 6308 int
pdc20262_dma_finish(void *v, int channel, int drive, int force)
 6310 {
 6311         struct pciide_softc *sc = v;
 6312         struct pciide_dma_maps *dma_maps =
 6313             &sc->pciide_channels[channel].dma_maps[drive];
u_int8_t clock;
 6316         if (dma_maps->dma_flags & WDC_DMA_LBA48) {
clock = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh,
PDC262_U66);
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
PDC262_U66, clock & ~PDC262_U66_EN(channel));
bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh,
PDC262_ATAPI(channel), 0);
 6323         }
 6325         return (pciide_dma_finish(v, channel, drive, force));
 6326 }
 6328 void
pdcsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
 6330 {
 6331         struct pciide_channel *cp;
 6332         struct channel_softc *wdc_cp;
 6333         struct pciide_pdcsata *ps;
 6334         int channel, i;
bus_size_t dmasize;
pci_intr_handle_t intrhandle;
 6337         const char *intrstr;
 6339         /* Allocate memory for private data */
sc->sc_cookie = malloc(sizeof(struct pciide_pdcsata), M_DEVBUF,
M_NOWAIT);
ps = sc->sc_cookie;
bzero(ps, sizeof(*ps));
 6345         /*
 6346          * Promise SATA controllers have 3 or 4 channels,
 6347          * the usual IDE registers are mapped in I/O space, with offsets.
 6348          */
 6349         if (pci_intr_map(pa, &intrhandle) != 0) {
printf(": couldn't map interrupt\n");
 6351                 return;
 6352         }
intrstr = pci_intr_string(pa->pa_pc, intrhandle);
 6355         switch (sc->sc_pp->ide_product) {
 6356         case PCI_PRODUCT_PROMISE_PDC20318:
 6357         case PCI_PRODUCT_PROMISE_PDC20319:
 6358         case PCI_PRODUCT_PROMISE_PDC20371:
 6359         case PCI_PRODUCT_PROMISE_PDC20375:
 6360         case PCI_PRODUCT_PROMISE_PDC20376:
 6361         case PCI_PRODUCT_PROMISE_PDC20377:
 6362         case PCI_PRODUCT_PROMISE_PDC20378:
 6363         case PCI_PRODUCT_PROMISE_PDC20379:
 6364         default:
sc->sc_pci_ih = pci_intr_establish(pa->pa_pc,
intrhandle, IPL_BIO, pdc203xx_pci_intr, sc,
sc->sc_wdcdev.sc_dev.dv_xname);
 6368                 break;
 6370         case PCI_PRODUCT_PROMISE_PDC40518:
 6371         case PCI_PRODUCT_PROMISE_PDC40519:
 6372         case PCI_PRODUCT_PROMISE_PDC40718:
 6373         case PCI_PRODUCT_PROMISE_PDC40719:
 6374         case PCI_PRODUCT_PROMISE_PDC40779:
 6375         case PCI_PRODUCT_PROMISE_PDC20571:
 6376         case PCI_PRODUCT_PROMISE_PDC20575:
 6377         case PCI_PRODUCT_PROMISE_PDC20579:
 6378         case PCI_PRODUCT_PROMISE_PDC20771:
 6379         case PCI_PRODUCT_PROMISE_PDC20775:
sc->sc_pci_ih = pci_intr_establish(pa->pa_pc,
intrhandle, IPL_BIO, pdc205xx_pci_intr, sc,
sc->sc_wdcdev.sc_dev.dv_xname);
 6383                 break;
 6384         }
 6386         if (sc->sc_pci_ih == NULL) {
printf(": couldn't establish native-PCI interrupt");
 6388                 if (intrstr != NULL)
printf(" at %s", intrstr);
printf("\n");
 6391                 return;
 6392         }
sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA,
PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_dma_iot,
 6396             &sc->sc_dma_ioh, NULL, &dmasize, 0) == 0);
 6397         if (!sc->sc_dma_ok) {
printf(": couldn't map bus-master DMA registers\n");
pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih);
 6400                 return;
 6401         }
sc->sc_dmat = pa->pa_dmat;
 6405         if (pci_mapreg_map(pa, PDC203xx_BAR_IDEREGS,
PCI_MAPREG_MEM_TYPE_32BIT, 0, &ps->ba5_st,
 6407             &ps->ba5_sh, NULL, NULL, 0) != 0) {
printf(": couldn't map IDE registers\n");
bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, dmasize);
pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih);
 6411                 return;
 6412         }
printf(": DMA\n");
sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16;
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
sc->sc_wdcdev.irqack = pdc203xx_irqack;
sc->sc_wdcdev.PIO_cap = 4;
sc->sc_wdcdev.DMA_cap = 2;
sc->sc_wdcdev.UDMA_cap = 6;
sc->sc_wdcdev.set_modes = pdc203xx_setup_channel;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
 6426         switch (sc->sc_pp->ide_product) {
 6427         case PCI_PRODUCT_PROMISE_PDC20318:
 6428         case PCI_PRODUCT_PROMISE_PDC20319:
 6429         case PCI_PRODUCT_PROMISE_PDC20371:
 6430         case PCI_PRODUCT_PROMISE_PDC20375:
 6431         case PCI_PRODUCT_PROMISE_PDC20376:
 6432         case PCI_PRODUCT_PROMISE_PDC20377:
 6433         case PCI_PRODUCT_PROMISE_PDC20378:
 6434         case PCI_PRODUCT_PROMISE_PDC20379:
 6435         default:
bus_space_write_4(ps->ba5_st, ps->ba5_sh, 0x06c, 0x00ff0033);
sc->sc_wdcdev.nchannels =
 6438                     (bus_space_read_4(ps->ba5_st, ps->ba5_sh, 0x48) & 0x02) ?
PDC203xx_NCHANNELS : 3;
 6440                 break;
 6442         case PCI_PRODUCT_PROMISE_PDC40518:
 6443         case PCI_PRODUCT_PROMISE_PDC40519:
 6444         case PCI_PRODUCT_PROMISE_PDC40718:
 6445         case PCI_PRODUCT_PROMISE_PDC40719:
 6446         case PCI_PRODUCT_PROMISE_PDC40779:
 6447         case PCI_PRODUCT_PROMISE_PDC20571:
bus_space_write_4(ps->ba5_st, ps->ba5_sh, 0x60, 0x00ff00ff);
sc->sc_wdcdev.nchannels = PDC40718_NCHANNELS;
sc->sc_wdcdev.reset = pdc205xx_do_reset;
sc->sc_wdcdev.drv_probe = pdc205xx_drv_probe;
 6454                 break;
 6455         case PCI_PRODUCT_PROMISE_PDC20575:
 6456         case PCI_PRODUCT_PROMISE_PDC20579:
 6457         case PCI_PRODUCT_PROMISE_PDC20771:
 6458         case PCI_PRODUCT_PROMISE_PDC20775:
bus_space_write_4(ps->ba5_st, ps->ba5_sh, 0x60, 0x00ff00ff);
sc->sc_wdcdev.nchannels = PDC20575_NCHANNELS;
sc->sc_wdcdev.reset = pdc205xx_do_reset;
sc->sc_wdcdev.drv_probe = pdc205xx_drv_probe;
 6465                 break;
 6466         }
sc->sc_wdcdev.dma_arg = sc;
sc->sc_wdcdev.dma_init = pciide_dma_init;
sc->sc_wdcdev.dma_start = pdc203xx_dma_start;
sc->sc_wdcdev.dma_finish = pdc203xx_dma_finish;
 6473         for (channel = 0; channel < sc->sc_wdcdev.nchannels;
channel++) {
cp = &sc->pciide_channels[channel];
sc->wdc_chanarray[channel] = &cp->wdc_channel;
cp->ih = sc->sc_pci_ih;
cp->name = NULL;
cp->wdc_channel.channel = channel;
cp->wdc_channel.wdc = &sc->sc_wdcdev;
cp->wdc_channel.ch_queue =
malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT);
 6484                 if (cp->wdc_channel.ch_queue == NULL) {
printf("%s: channel %d: "
 6486                             "can't allocate memory for command queue\n",
sc->sc_wdcdev.sc_dev.dv_xname, channel);
 6488                         continue;
 6489                 }
wdc_cp = &cp->wdc_channel;
ps->regs[channel].ctl_iot = ps->ba5_st;
ps->regs[channel].cmd_iot = ps->ba5_st;
 6495                 if (bus_space_subregion(ps->ba5_st, ps->ba5_sh,
 6496                     0x0238 + (channel << 7), 1,
 6497                     &ps->regs[channel].ctl_ioh) != 0) {
printf("%s: couldn't map channel %d ctl regs\n",
sc->sc_wdcdev.sc_dev.dv_xname,
channel);
 6501                         continue;
 6502                 }
 6503                 for (i = 0; i < WDC_NREG; i++) {
 6504                         if (bus_space_subregion(ps->ba5_st, ps->ba5_sh,
 6505                             0x0200 + (i << 2) + (channel << 7), i == 0 ? 4 : 1,
 6506                             &ps->regs[channel].cmd_iohs[i]) != 0) {
printf("%s: couldn't map channel %d cmd "
 6508                                     "regs\n",
sc->sc_wdcdev.sc_dev.dv_xname,
channel);
 6511                                 continue;
 6512                         }
 6513                 }
ps->regs[channel].cmd_iohs[wdr_status & _WDC_REGMASK] =
ps->regs[channel].cmd_iohs[wdr_command & _WDC_REGMASK];
ps->regs[channel].cmd_iohs[wdr_features & _WDC_REGMASK] =
ps->regs[channel].cmd_iohs[wdr_error & _WDC_REGMASK];
wdc_cp->data32iot = wdc_cp->cmd_iot =
ps->regs[channel].cmd_iot;
wdc_cp->data32ioh = wdc_cp->cmd_ioh =
ps->regs[channel].cmd_iohs[0];
wdc_cp->_vtbl = &wdc_pdc203xx_vtbl;
 6524                 /*
 6525                  * Subregion de busmaster registers. They're spread all over
 6526                  * the controller's register space :(. They are also 4 bytes
 6527                  * sized, with some specific extentions in the extra bits.
 6528                  * It also seems that the IDEDMA_CTL register isn't available.
 6529                  */
 6530                 if (bus_space_subregion(ps->ba5_st, ps->ba5_sh,
 6531                     0x260 + (channel << 7), 1,
 6532                     &ps->regs[channel].dma_iohs[IDEDMA_CMD(0)]) != 0) {
printf("%s channel %d: can't subregion DMA "
 6534                             "registers\n",
sc->sc_wdcdev.sc_dev.dv_xname, channel);
 6536                         continue;
 6537                 }
 6538                 if (bus_space_subregion(ps->ba5_st, ps->ba5_sh,
 6539                     0x244 + (channel << 7), 4,
 6540                     &ps->regs[channel].dma_iohs[IDEDMA_TBL(0)]) != 0) {
printf("%s channel %d: can't subregion DMA "
 6542                             "registers\n",
sc->sc_wdcdev.sc_dev.dv_xname, channel);
 6544                         continue;
 6545                 }
wdcattach(wdc_cp);
bus_space_write_4(sc->sc_dma_iot,
ps->regs[channel].dma_iohs[IDEDMA_CMD(0)], 0,
 6550                     (bus_space_read_4(sc->sc_dma_iot,
ps->regs[channel].dma_iohs[IDEDMA_CMD(0)],
 6552                         0) & ~0x00003f9f) | (channel + 1));
bus_space_write_4(ps->ba5_st, ps->ba5_sh,
 6554                     (channel + 1) << 2, 0x00000001);
pdc203xx_setup_channel(&cp->wdc_channel);
 6557         }
printf("%s: using %s for native-PCI interrupt\n",
sc->sc_wdcdev.sc_dev.dv_xname,
intrstr ? intrstr : "unknown interrupt");
 6562 }
 6564 void
pdc203xx_setup_channel(struct channel_softc *chp)
 6566 {
 6567         struct ata_drive_datas *drvp;
 6568         struct pciide_channel *cp = (struct pciide_channel *)chp;
 6569         int drive, s;
pciide_channel_dma_setup(cp);
 6573         for (drive = 0; drive < 2; drive++) {
drvp = &chp->ch_drive[drive];
 6575                 if ((drvp->drive_flags & DRIVE) == 0)
 6576                         continue;
 6577                 if (drvp->drive_flags & DRIVE_UDMA) {
s = splbio();
drvp->drive_flags &= ~DRIVE_DMA;
splx(s);
 6581                 }
 6582         }
pciide_print_modes(cp);
 6584 }
 6586 int
pdc203xx_pci_intr(void *arg)
 6588 {
 6589         struct pciide_softc *sc = arg;
 6590         struct pciide_channel *cp;
 6591         struct channel_softc *wdc_cp;
 6592         struct pciide_pdcsata *ps = sc->sc_cookie;
 6593         int i, rv, crv;
u_int32_t scr;
rv = 0;
scr = bus_space_read_4(ps->ba5_st, ps->ba5_sh, 0x00040);
 6599         for (i = 0; i < sc->sc_wdcdev.nchannels; i++) {
cp = &sc->pciide_channels[i];
wdc_cp = &cp->wdc_channel;
 6602                 if (scr & (1 << (i + 1))) {
crv = wdcintr(wdc_cp);
 6604                         if (crv == 0) {
printf("%s:%d: bogus intr (reg 0x%x)\n",
sc->sc_wdcdev.sc_dev.dv_xname,
i, scr);
 6608                         } else
rv = 1;
 6610                 }
 6611         }
 6613         return (rv);
 6614 }
 6616 int
pdc205xx_pci_intr(void *arg)
 6618 {
 6619         struct pciide_softc *sc = arg;
 6620         struct pciide_channel *cp;
 6621         struct channel_softc *wdc_cp;
 6622         struct pciide_pdcsata *ps = sc->sc_cookie;
 6623         int i, rv, crv;
u_int32_t scr, status;
rv = 0;
scr = bus_space_read_4(ps->ba5_st, ps->ba5_sh, 0x40);
bus_space_write_4(ps->ba5_st, ps->ba5_sh, 0x40, scr & 0x0000ffff);
status = bus_space_read_4(ps->ba5_st, ps->ba5_sh, 0x60);
bus_space_write_4(ps->ba5_st, ps->ba5_sh, 0x60, status & 0x000000ff);
 6633         for (i = 0; i < sc->sc_wdcdev.nchannels; i++) {
cp = &sc->pciide_channels[i];
wdc_cp = &cp->wdc_channel;
 6636                 if (scr & (1 << (i + 1))) {
crv = wdcintr(wdc_cp);
 6638                         if (crv == 0) {
printf("%s:%d: bogus intr (reg 0x%x)\n",
sc->sc_wdcdev.sc_dev.dv_xname,
i, scr);
 6642                         } else
rv = 1;
 6644                 }
 6645         }
 6646         return rv;
 6647 }
 6649 void
pdc203xx_irqack(struct channel_softc *chp)
 6651 {
 6652         struct pciide_channel *cp = (struct pciide_channel *)chp;
 6653         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 6654         struct pciide_pdcsata *ps = sc->sc_cookie;
 6655         int chan = chp->channel;
bus_space_write_4(sc->sc_dma_iot,
ps->regs[chan].dma_iohs[IDEDMA_CMD(0)], 0,
 6659             (bus_space_read_4(sc->sc_dma_iot,
ps->regs[chan].dma_iohs[IDEDMA_CMD(0)],
 6661                 0) & ~0x00003f9f) | (chan + 1));
bus_space_write_4(ps->ba5_st, ps->ba5_sh,
 6663             (chan + 1) << 2, 0x00000001);
 6664 }
 6666 void
pdc203xx_dma_start(void *v, int channel, int drive)
 6668 {
 6669         struct pciide_softc *sc = v;
 6670         struct pciide_channel *cp = &sc->pciide_channels[channel];
 6671         struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive];
 6672         struct pciide_pdcsata *ps = sc->sc_cookie;
 6674         /* Write table address */
bus_space_write_4(sc->sc_dma_iot,
ps->regs[channel].dma_iohs[IDEDMA_TBL(0)], 0,
dma_maps->dmamap_table->dm_segs[0].ds_addr);
 6679         /* Start DMA engine */
bus_space_write_4(sc->sc_dma_iot,
ps->regs[channel].dma_iohs[IDEDMA_CMD(0)], 0,
 6682             (bus_space_read_4(sc->sc_dma_iot,
ps->regs[channel].dma_iohs[IDEDMA_CMD(0)],
 6684             0) & ~0xc0) | ((dma_maps->dma_flags & WDC_DMA_READ) ? 0x80 : 0xc0));
 6685 }
 6687 int
pdc203xx_dma_finish(void *v, int channel, int drive, int force)
 6689 {
 6690         struct pciide_softc *sc = v;
 6691         struct pciide_channel *cp = &sc->pciide_channels[channel];
 6692         struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive];
 6693         struct pciide_pdcsata *ps = sc->sc_cookie;
 6695         /* Stop DMA channel */
bus_space_write_4(sc->sc_dma_iot,
ps->regs[channel].dma_iohs[IDEDMA_CMD(0)], 0,
 6698             (bus_space_read_4(sc->sc_dma_iot,
ps->regs[channel].dma_iohs[IDEDMA_CMD(0)],
 6700             0) & ~0x80));
 6702         /* Unload the map of the data buffer */
bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0,
dma_maps->dmamap_xfer->dm_mapsize,
 6705             (dma_maps->dma_flags & WDC_DMA_READ) ?
BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer);
 6709         return (0);
 6710 }
u_int8_t
pdc203xx_read_reg(struct channel_softc *chp, enum wdc_regs reg)
 6714 {
 6715         struct pciide_channel *cp = (struct pciide_channel *)chp;
 6716         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 6717         struct pciide_pdcsata *ps = sc->sc_cookie;
u_int8_t val;
 6720         if (reg & _WDC_AUX) {
 6721                 return (bus_space_read_1(ps->regs[chp->channel].ctl_iot,
ps->regs[chp->channel].ctl_ioh, reg & _WDC_REGMASK));
 6723         } else {
val = bus_space_read_1(ps->regs[chp->channel].cmd_iot,
ps->regs[chp->channel].cmd_iohs[reg & _WDC_REGMASK], 0);
 6726                 return (val);
 6727         }
 6728 }
 6730 void
pdc203xx_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int8_t val)
 6732 {
 6733         struct pciide_channel *cp = (struct pciide_channel *)chp;
 6734         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 6735         struct pciide_pdcsata *ps = sc->sc_cookie;
 6737         if (reg & _WDC_AUX)
bus_space_write_1(ps->regs[chp->channel].ctl_iot,
ps->regs[chp->channel].ctl_ioh, reg & _WDC_REGMASK, val);
 6740         else
bus_space_write_1(ps->regs[chp->channel].cmd_iot,
ps->regs[chp->channel].cmd_iohs[reg & _WDC_REGMASK],
 6743                     0, val);
 6744 }
 6746 void
pdc205xx_do_reset(struct channel_softc *chp)
 6748 {
 6749         struct pciide_channel *cp = (struct pciide_channel *)chp;
 6750         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 6751         struct pciide_pdcsata *ps = sc->sc_cookie;
u_int32_t scontrol;
wdc_do_reset(chp);
 6756         /* reset SATA */
scontrol = SControl_DET_INIT | SControl_SPD_ANY | SControl_IPM_NONE;
SCONTROL_WRITE(ps, chp->channel, scontrol);
delay(50*1000);
scontrol &= ~SControl_DET_INIT;
SCONTROL_WRITE(ps, chp->channel, scontrol);
delay(50*1000);
 6764 }
 6766 void
pdc205xx_drv_probe(struct channel_softc *chp)
 6768 {
 6769         struct pciide_channel *cp = (struct pciide_channel *)chp;
 6770         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 6771         struct pciide_pdcsata *ps = sc->sc_cookie;
bus_space_handle_t *iohs;
u_int32_t scontrol, sstatus;
u_int16_t scnt, sn, cl, ch;
 6775         int i, s;
 6777         /* XXX This should be done by other code. */
 6778         for (i = 0; i < 2; i++) {
chp->ch_drive[i].chnl_softc = chp;
chp->ch_drive[i].drive = i;
 6781         }
SCONTROL_WRITE(ps, chp->channel, 0);
delay(50*1000);
scontrol = SControl_DET_INIT | SControl_SPD_ANY | SControl_IPM_NONE;
SCONTROL_WRITE(ps,chp->channel,scontrol);
delay(50*1000);
scontrol &= ~SControl_DET_INIT;
SCONTROL_WRITE(ps,chp->channel,scontrol);
delay(50*1000);
sstatus = SSTATUS_READ(ps,chp->channel);
 6796         switch (sstatus & SStatus_DET_mask) {
 6797         case SStatus_DET_NODEV:
 6798                 /* No Device; be silent.  */
 6799                 break;
 6801         case SStatus_DET_DEV_NE:
printf("%s: port %d: device connected, but "
 6803                     "communication not established\n",
sc->sc_wdcdev.sc_dev.dv_xname, chp->channel);
 6805                 break;
 6807         case SStatus_DET_OFFLINE:
printf("%s: port %d: PHY offline\n",
sc->sc_wdcdev.sc_dev.dv_xname, chp->channel);
 6810                 break;
 6812         case SStatus_DET_DEV:
iohs = ps->regs[chp->channel].cmd_iohs;
bus_space_write_1(chp->cmd_iot, iohs[wdr_sdh], 0,
WDSD_IBM);
delay(10);      /* 400ns delay */
scnt = bus_space_read_2(chp->cmd_iot, iohs[wdr_seccnt], 0);
sn = bus_space_read_2(chp->cmd_iot, iohs[wdr_sector], 0);
cl = bus_space_read_2(chp->cmd_iot, iohs[wdr_cyl_lo], 0);
ch = bus_space_read_2(chp->cmd_iot, iohs[wdr_cyl_hi], 0);
 6821 #if 0
printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n",
sc->sc_wdcdev.sc_dev.dv_xname, chp->channel,
scnt, sn, cl, ch);
 6825 #endif
 6826                 /*
 6827                  * scnt and sn are supposed to be 0x1 for ATAPI, but in some
 6828                  * cases we get wrong values here, so ignore it.
 6829                  */
s = splbio();
 6831                 if (cl == 0x14 && ch == 0xeb)
chp->ch_drive[0].drive_flags |= DRIVE_ATAPI;
 6833                 else
chp->ch_drive[0].drive_flags |= DRIVE_ATA;
splx(s);
 6836 #if 0
printf("%s: port %d: device present",
sc->sc_wdcdev.sc_dev.dv_xname, chp->channel);
 6839                 switch ((sstatus & SStatus_SPD_mask) >> SStatus_SPD_shift) {
 6840                 case 1:
printf(", speed: 1.5Gb/s");
 6842                         break;
 6843                 case 2:
printf(", speed: 3.0Gb/s");
 6845                         break;
 6846                 }
printf("\n");
 6848 #endif
 6849                 break;
 6851         default:
printf("%s: port %d: unknown SStatus: 0x%08x\n",
sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus);
 6854         }
 6855 }
 6857 #ifdef notyet
 6858 /*
 6859  * Inline functions for accessing the timing registers of the
 6860  * OPTi controller.
 6861  *
 6862  * These *MUST* disable interrupts as they need atomic access to
 6863  * certain magic registers. Failure to adhere to this *will*
 6864  * break things in subtle ways if the wdc registers are accessed
 6865  * by an interrupt routine while this magic sequence is executing.
 6866  */
 6867 static __inline__ u_int8_t
opti_read_config(struct channel_softc *chp, int reg)
 6869 {
u_int8_t rv;
 6871         int s = splhigh();
 6873         /* Two consecutive 16-bit reads from register #1 (0x1f1/0x171) */
 6874         (void) bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wdr_features);
 6875         (void) bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wdr_features);
 6877         /* Followed by an 8-bit write of 0x3 to register #2 */
bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wdr_seccnt, 0x03u);
 6880         /* Now we can read the required register */
rv = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, reg);
 6883         /* Restore the real registers */
bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wdr_seccnt, 0x83u);
splx(s);
 6888         return (rv);
 6889 }
 6891 static __inline__ void
opti_write_config(struct channel_softc *chp, int reg, u_int8_t val)
 6893 {
 6894         int s = splhigh();
 6896         /* Two consecutive 16-bit reads from register #1 (0x1f1/0x171) */
 6897         (void) bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wdr_features);
 6898         (void) bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wdr_features);
 6900         /* Followed by an 8-bit write of 0x3 to register #2 */
bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wdr_seccnt, 0x03u);
 6903         /* Now we can write the required register */
bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, reg, val);
 6906         /* Restore the real registers */
bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wdr_seccnt, 0x83u);
splx(s);
 6910 }
 6912 void
opti_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
 6914 {
 6915         struct pciide_channel *cp;
bus_size_t cmdsize, ctlsize;
pcireg_t interface;
u_int8_t init_ctrl;
 6919         int channel;
printf(": DMA");
 6922         /*
 6923          * XXXSCW:
 6924          * There seem to be a couple of buggy revisions/implementations
 6925          * of the OPTi pciide chipset. This kludge seems to fix one of
 6926          * the reported problems (NetBSD PR/11644) but still fails for the
 6927          * other (NetBSD PR/13151), although the latter may be due to other
 6928          * issues too...
 6929          */
 6930         if (sc->sc_rev <= 0x12) {
printf(" (disabled)");
sc->sc_dma_ok = 0;
sc->sc_wdcdev.cap = 0;
 6934         } else {
sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32;
pciide_mapreg_dma(sc, pa);
 6937         }
sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_MODE;
sc->sc_wdcdev.PIO_cap = 4;
 6941         if (sc->sc_dma_ok) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK;
sc->sc_wdcdev.irqack = pciide_irqack;
sc->sc_wdcdev.DMA_cap = 2;
 6945         }
sc->sc_wdcdev.set_modes = opti_setup_channel;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag,
OPTI_REG_INIT_CONTROL);
interface = PCI_INTERFACE(pa->pa_class);
pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
 6958         for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
cp = &sc->pciide_channels[channel];
 6960                 if (pciide_chansetup(sc, channel, interface) == 0)
 6961                         continue;
 6962                 if (channel == 1 &&
 6963                     (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) {
printf("%s: %s ignored (disabled)\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
 6966                         continue;
 6967                 }
pciide_map_compat_intr(pa, cp, channel, interface);
 6969                 if (cp->hw_ok == 0)
 6970                         continue;
pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
pciide_pci_intr);
 6973                 if (cp->hw_ok == 0) {
pciide_unmap_compat_intr(pa, cp, channel, interface);
 6975                         continue;
 6976                 }
opti_setup_channel(&cp->wdc_channel);
 6978         }
 6979 }
 6981 void
opti_setup_channel(struct channel_softc *chp)
 6983 {
 6984         struct ata_drive_datas *drvp;
 6985         struct pciide_channel *cp = (struct pciide_channel *)chp;
 6986         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 6987         int drive, spd;
 6988         int mode[2];
u_int8_t rv, mr;
 6991         /*
 6992          * The `Delay' and `Address Setup Time' fields of the
 6993          * Miscellaneous Register are always zero initially.
 6994          */
mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK;
mr &= ~(OPTI_MISC_DELAY_MASK |
OPTI_MISC_ADDR_SETUP_MASK |
OPTI_MISC_INDEX_MASK);
 7000         /* Prime the control register before setting timing values */
opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE);
 7003         /* Determine the clockrate of the PCIbus the chip is attached to */
spd = (int) opti_read_config(chp, OPTI_REG_STRAP);
spd &= OPTI_STRAP_PCI_SPEED_MASK;
 7007         /* setup DMA if needed */
pciide_channel_dma_setup(cp);
 7010         for (drive = 0; drive < 2; drive++) {
drvp = &chp->ch_drive[drive];
 7012                 /* If no drive, skip */
 7013                 if ((drvp->drive_flags & DRIVE) == 0) {
mode[drive] = -1;
 7015                         continue;
 7016                 }
 7018                 if ((drvp->drive_flags & DRIVE_DMA)) {
 7019                         /*
 7020                          * Timings will be used for both PIO and DMA,
 7021                          * so adjust DMA mode if needed
 7022                          */
 7023                         if (drvp->PIO_mode > (drvp->DMA_mode + 2))
drvp->PIO_mode = drvp->DMA_mode + 2;
 7025                         if (drvp->DMA_mode + 2 > (drvp->PIO_mode))
drvp->DMA_mode = (drvp->PIO_mode > 2) ?
drvp->PIO_mode - 2 : 0;
 7028                         if (drvp->DMA_mode == 0)
drvp->PIO_mode = 0;
mode[drive] = drvp->DMA_mode + 5;
 7032                 } else
mode[drive] = drvp->PIO_mode;
 7035                 if (drive && mode[0] >= 0 &&
 7036                     (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) {
 7037                         /*
 7038                          * Can't have two drives using different values
 7039                          * for `Address Setup Time'.
 7040                          * Slow down the faster drive to compensate.
 7041                          */
 7042                         int d = (opti_tim_as[spd][mode[0]] >
opti_tim_as[spd][mode[1]]) ?  0 : 1;
mode[d] = mode[1-d];
chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode;
chp->ch_drive[d].DMA_mode = 0;
chp->ch_drive[d].drive_flags &= DRIVE_DMA;
 7049                 }
 7050         }
 7052         for (drive = 0; drive < 2; drive++) {
 7053                 int m;
 7054                 if ((m = mode[drive]) < 0)
 7055                         continue;
 7057                 /* Set the Address Setup Time and select appropriate index */
rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT;
rv |= OPTI_MISC_INDEX(drive);
opti_write_config(chp, OPTI_REG_MISC, mr | rv);
 7062                 /* Set the pulse width and recovery timing parameters */
rv  = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT;
rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT;
opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv);
opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv);
 7068                 /* Set the Enhanced Mode register appropriately */
rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE);
rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive);
rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]);
pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv);
 7073         }
 7075         /* Finally, enable the timings */
opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE);
pciide_print_modes(cp);
 7079 }
 7080 #endif
 7082 void
serverworks_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
 7084 {
 7085         struct pciide_channel *cp;
pcireg_t interface = PCI_INTERFACE(pa->pa_class);
pcitag_t pcib_tag;
 7088         int channel;
bus_size_t cmdsize, ctlsize;
printf(": DMA");
pciide_mapreg_dma(sc, pa);
printf("\n");
sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
WDC_CAPABILITY_MODE;
 7097         if (sc->sc_dma_ok) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
sc->sc_wdcdev.irqack = pciide_irqack;
 7101         }
sc->sc_wdcdev.PIO_cap = 4;
sc->sc_wdcdev.DMA_cap = 2;
 7104         switch (sc->sc_pp->ide_product) {
 7105         case PCI_PRODUCT_RCC_OSB4_IDE:
sc->sc_wdcdev.UDMA_cap = 2;
 7107                 break;
 7108         case PCI_PRODUCT_RCC_CSB5_IDE:
 7109                 if (sc->sc_rev < 0x92)
sc->sc_wdcdev.UDMA_cap = 4;
 7111                 else
sc->sc_wdcdev.UDMA_cap = 5;
 7113                 break;
 7114         case PCI_PRODUCT_RCC_CSB6_IDE:
sc->sc_wdcdev.UDMA_cap = 4;
 7116                 break;
 7117         case PCI_PRODUCT_RCC_CSB6_RAID_IDE:
sc->sc_wdcdev.UDMA_cap = 5;
 7119                 break;
 7120         }
sc->sc_wdcdev.set_modes = serverworks_setup_channel;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels =
 7125             (sc->sc_pp->ide_product == PCI_PRODUCT_RCC_CSB6_IDE ? 1 : 2);
 7127         for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
cp = &sc->pciide_channels[channel];
 7129                 if (pciide_chansetup(sc, channel, interface) == 0)
 7130                         continue;
pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
serverworks_pci_intr);
 7133                 if (cp->hw_ok == 0)
 7134                         return;
pciide_map_compat_intr(pa, cp, channel, interface);
 7136                 if (cp->hw_ok == 0)
 7137                         return;
serverworks_setup_channel(&cp->wdc_channel);
 7139         }
pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0);
pci_conf_write(pa->pa_pc, pcib_tag, 0x64,
 7143             (pci_conf_read(pa->pa_pc, pcib_tag, 0x64) & ~0x2000) | 0x4000);
 7144 }
 7146 void
serverworks_setup_channel(struct channel_softc *chp)
 7148 {
 7149         struct ata_drive_datas *drvp;
 7150         struct pciide_channel *cp = (struct pciide_channel *)chp;
 7151         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 7152         int channel = chp->channel;
 7153         int drive, unit;
u_int32_t pio_time, dma_time, pio_mode, udma_mode;
u_int32_t idedma_ctl;
 7156         static const u_int8_t pio_modes[5] = {0x5d, 0x47, 0x34, 0x22, 0x20};
 7157         static const u_int8_t dma_modes[3] = {0x77, 0x21, 0x20};
 7159         /* setup DMA if needed */
pciide_channel_dma_setup(cp);
pio_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x40);
dma_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x44);
pio_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x48);
udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54);
pio_time &= ~(0xffff << (16 * channel));
dma_time &= ~(0xffff << (16 * channel));
pio_mode &= ~(0xff << (8 * channel + 16));
udma_mode &= ~(0xff << (8 * channel + 16));
udma_mode &= ~(3 << (2 * channel));
idedma_ctl = 0;
 7175         /* Per drive settings */
 7176         for (drive = 0; drive < 2; drive++) {
drvp = &chp->ch_drive[drive];
 7178                 /* If no drive, skip */
 7179                 if ((drvp->drive_flags & DRIVE) == 0)
 7180                         continue;
unit = drive + 2 * channel;
 7182                 /* add timing values, setup DMA if needed */
pio_time |= pio_modes[drvp->PIO_mode] << (8 * (unit^1));
pio_mode |= drvp->PIO_mode << (4 * unit + 16);
 7185                 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) &&
 7186                     (drvp->drive_flags & DRIVE_UDMA)) {
 7187                         /* use Ultra/DMA, check for 80-pin cable */
 7188                         if (sc->sc_rev <= 0x92 && drvp->UDMA_mode > 2 &&
 7189                             (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag,
PCI_SUBSYS_ID_REG)) &
 7191                             (1 << (14 + channel))) == 0) {
WDCDEBUG_PRINT(("%s(%s:%d:%d): 80-wire "
 7193                                     "cable not detected\n", drvp->drive_name,
sc->sc_wdcdev.sc_dev.dv_xname,
channel, drive), DEBUG_PROBE);
drvp->UDMA_mode = 2;
 7197                         }
dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1));
udma_mode |= drvp->UDMA_mode << (4 * unit + 16);
udma_mode |= 1 << unit;
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
 7202                 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) &&
 7203                     (drvp->drive_flags & DRIVE_DMA)) {
 7204                         /* use Multiword DMA */
drvp->drive_flags &= ~DRIVE_UDMA;
dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1));
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
 7208                 } else {
 7209                         /* PIO only */
drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA);
 7211                 }
 7212         }
pci_conf_write(sc->sc_pc, sc->sc_tag, 0x40, pio_time);
pci_conf_write(sc->sc_pc, sc->sc_tag, 0x44, dma_time);
 7216         if (sc->sc_pp->ide_product != PCI_PRODUCT_RCC_OSB4_IDE)
pci_conf_write(sc->sc_pc, sc->sc_tag, 0x48, pio_mode);
pci_conf_write(sc->sc_pc, sc->sc_tag, 0x54, udma_mode);
 7220         if (idedma_ctl != 0) {
 7221                 /* Add software bits in status register */
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CTL(channel), idedma_ctl);
 7224         }
pciide_print_modes(cp);
 7226 }
 7228 int
serverworks_pci_intr(void *arg)
 7230 {
 7231         struct pciide_softc *sc = arg;
 7232         struct pciide_channel *cp;
 7233         struct channel_softc *wdc_cp;
 7234         int rv = 0;
 7235         int dmastat, i, crv;
 7237         for (i = 0; i < sc->sc_wdcdev.nchannels; i++) {
dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CTL(i));
 7240                 if ((dmastat & (IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) !=
IDEDMA_CTL_INTR)
 7242                         continue;
cp = &sc->pciide_channels[i];
wdc_cp = &cp->wdc_channel;
crv = wdcintr(wdc_cp);
 7246                 if (crv == 0) {
printf("%s:%d: bogus intr\n",
sc->sc_wdcdev.sc_dev.dv_xname, i);
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CTL(i), dmastat);
 7251                 } else
rv = 1;
 7253         }
 7254         return (rv);
 7255 }
 7257 void
svwsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
 7259 {
 7260         struct pciide_channel *cp;
pci_intr_handle_t intrhandle;
 7262         const char *intrstr;
 7263         int channel;
 7264         struct pciide_svwsata *ss;
 7266         /* Allocate memory for private data */
sc->sc_cookie = malloc(sizeof(struct pciide_svwsata), M_DEVBUF,
M_NOWAIT);
ss = sc->sc_cookie;
bzero(ss, sizeof(*ss));
 7272         /* The 4-port version has a dummy second function. */
 7273         if (pci_conf_read(sc->sc_pc, sc->sc_tag,
PCI_MAPREG_START + 0x14) == 0) {
printf("\n");
 7276                 return;
 7277         }
 7279         if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14,
PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
 7281             &ss->ba5_st, &ss->ba5_sh, NULL, NULL, 0) != 0) {
printf(": unable to map BA5 register space\n");
 7283                 return;
 7284         }
printf(": DMA");
svwsata_mapreg_dma(sc, pa);
printf("\n");
 7290         if (sc->sc_dma_ok) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA |
WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK;
sc->sc_wdcdev.irqack = pciide_irqack;
 7294         }
sc->sc_wdcdev.PIO_cap = 4;
sc->sc_wdcdev.DMA_cap = 2;
sc->sc_wdcdev.UDMA_cap = 6;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = 4;
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
WDC_CAPABILITY_MODE | WDC_CAPABILITY_SATA;
sc->sc_wdcdev.set_modes = sata_setup_channel;
 7305         /* We can use SControl and SStatus to probe for drives. */
sc->sc_wdcdev.drv_probe = svwsata_drv_probe;
 7308         /* Map and establish the interrupt handler. */
 7309         if(pci_intr_map(pa, &intrhandle) != 0) {
printf("%s: couldn't map native-PCI interrupt\n",
sc->sc_wdcdev.sc_dev.dv_xname);
 7312                 return;
 7313         }
intrstr = pci_intr_string(pa->pa_pc, intrhandle);
sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO,
pciide_pci_intr, sc, sc->sc_wdcdev.sc_dev.dv_xname);
 7317         if (sc->sc_pci_ih != NULL) {
printf("%s: using %s for native-PCI interrupt\n",
sc->sc_wdcdev.sc_dev.dv_xname,
intrstr ? intrstr : "unknown interrupt");
 7321         } else {
printf("%s: couldn't establish native-PCI interrupt",
sc->sc_wdcdev.sc_dev.dv_xname);
 7324                 if (intrstr != NULL)
printf(" at %s", intrstr);
printf("\n");
 7327                 return;
 7328         }
 7330         for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
cp = &sc->pciide_channels[channel];
 7332                 if (pciide_chansetup(sc, channel, 0) == 0)
 7333                         continue;
svwsata_mapchan(cp);
sata_setup_channel(&cp->wdc_channel);
 7336         }
 7337 }
 7339 void
svwsata_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa)
 7341 {
 7342         struct pciide_svwsata *ss = sc->sc_cookie;
sc->sc_wdcdev.dma_arg = sc;
sc->sc_wdcdev.dma_init = pciide_dma_init;
sc->sc_wdcdev.dma_start = pciide_dma_start;
sc->sc_wdcdev.dma_finish = pciide_dma_finish;
 7349         /* XXX */
sc->sc_dma_iot = ss->ba5_st;
sc->sc_dma_ioh = ss->ba5_sh;
sc->sc_dmacmd_read = svwsata_dmacmd_read;
sc->sc_dmacmd_write = svwsata_dmacmd_write;
sc->sc_dmactl_read = svwsata_dmactl_read;
sc->sc_dmactl_write = svwsata_dmactl_write;
sc->sc_dmatbl_write = svwsata_dmatbl_write;
 7359         /* DMA registers all set up! */
sc->sc_dmat = pa->pa_dmat;
sc->sc_dma_ok = 1;
 7362 }
u_int8_t
svwsata_dmacmd_read(struct pciide_softc *sc, int chan)
 7366 {
 7367         return (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh,
 7368             (chan << 8) + SVWSATA_DMA + IDEDMA_CMD(0)));
 7369 }
 7371 void
svwsata_dmacmd_write(struct pciide_softc *sc, int chan, u_int8_t val)
 7373 {
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
 7375             (chan << 8) + SVWSATA_DMA + IDEDMA_CMD(0), val);
 7376 }
u_int8_t
svwsata_dmactl_read(struct pciide_softc *sc, int chan)
 7380 {
 7381         return (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh,
 7382             (chan << 8) + SVWSATA_DMA + IDEDMA_CTL(0)));
 7383 }
 7385 void
svwsata_dmactl_write(struct pciide_softc *sc, int chan, u_int8_t val)
 7387 {
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
 7389             (chan << 8) + SVWSATA_DMA + IDEDMA_CTL(0), val);
 7390 }
 7392 void
svwsata_dmatbl_write(struct pciide_softc *sc, int chan, u_int32_t val)
 7394 {
bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh,
 7396             (chan << 8) + SVWSATA_DMA + IDEDMA_TBL(0), val);
 7397 }
 7399 void
svwsata_mapchan(struct pciide_channel *cp)
 7401 {
 7402         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 7403         struct channel_softc *wdc_cp = &cp->wdc_channel;
 7404         struct pciide_svwsata *ss = sc->sc_cookie;
cp->compat = 0;
cp->ih = sc->sc_pci_ih;
 7409         if (bus_space_subregion(ss->ba5_st, ss->ba5_sh,
 7410                 (wdc_cp->channel << 8) + SVWSATA_TF0,
SVWSATA_TF8 - SVWSATA_TF0, &wdc_cp->cmd_ioh) != 0) {
printf("%s: couldn't map %s cmd regs\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
 7414                 return;
 7415         }
 7416         if (bus_space_subregion(ss->ba5_st, ss->ba5_sh,
 7417                 (wdc_cp->channel << 8) + SVWSATA_TF8, 4,
 7418                 &wdc_cp->ctl_ioh) != 0) {
printf("%s: couldn't map %s ctl regs\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
 7421                 return;
 7422         }
wdc_cp->cmd_iot = wdc_cp->ctl_iot = ss->ba5_st;
wdc_cp->_vtbl = &wdc_svwsata_vtbl;
wdcattach(wdc_cp);
 7426 }
 7428 void
svwsata_drv_probe(struct channel_softc *chp)
 7430 {
 7431         struct pciide_channel *cp = (struct pciide_channel *)chp;
 7432         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 7433         struct pciide_svwsata *ss = sc->sc_cookie;
 7434         int channel = chp->channel;
uint32_t scontrol, sstatus;
uint8_t scnt, sn, cl, ch;
 7437         int i, s;
 7439         /* XXX This should be done by other code. */
 7440         for (i = 0; i < 2; i++) {
chp->ch_drive[i].chnl_softc = chp;
chp->ch_drive[i].drive = i;
 7443         }
 7445         /*
 7446          * Request communication initialization sequence, any speed.
 7447          * Performing this is the equivalent of an ATA Reset.
 7448          */
scontrol = SControl_DET_INIT | SControl_SPD_ANY;
 7451         /*
 7452          * XXX We don't yet support SATA power management; disable all
 7453          * power management state transitions.
 7454          */
scontrol |= SControl_IPM_NONE;
bus_space_write_4(ss->ba5_st, ss->ba5_sh,
 7458             (channel << 8) + SVWSATA_SCONTROL, scontrol);
delay(50 * 1000);
scontrol &= ~SControl_DET_INIT;
bus_space_write_4(ss->ba5_st, ss->ba5_sh,
 7462             (channel << 8) + SVWSATA_SCONTROL, scontrol);
delay(50 * 1000);
sstatus = bus_space_read_4(ss->ba5_st, ss->ba5_sh,
 7466             (channel << 8) + SVWSATA_SSTATUS);
 7467 #if 0
printf("%s: port %d: SStatus=0x%08x, SControl=0x%08x\n",
sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus,
bus_space_read_4(ss->ba5_st, ss->ba5_sh,
 7471                 (channel << 8) + SVWSATA_SSTATUS));
 7472 #endif
 7473         switch (sstatus & SStatus_DET_mask) {
 7474         case SStatus_DET_NODEV:
 7475                 /* No device; be silent. */
 7476                 break;
 7478         case SStatus_DET_DEV_NE:
printf("%s: port %d: device connected, but "
 7480                     "communication not established\n",
sc->sc_wdcdev.sc_dev.dv_xname, chp->channel);
 7482                 break;
 7484         case SStatus_DET_OFFLINE:
printf("%s: port %d: PHY offline\n",
sc->sc_wdcdev.sc_dev.dv_xname, chp->channel);
 7487                 break;
 7489         case SStatus_DET_DEV:
 7490                 /*
 7491                  * XXX ATAPI detection doesn't currently work.  Don't
 7492                  * XXX know why.  But, it's not like the standard method
 7493                  * XXX can detect an ATAPI device connected via a SATA/PATA
 7494                  * XXX bridge, so at least this is no worse.  --thorpej
 7495                  */
 7496                 if (chp->_vtbl != NULL)
CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (0 << 4));
 7498                 else
bus_space_write_1(chp->cmd_iot, chp->cmd_ioh,
wdr_sdh & _WDC_REGMASK, WDSD_IBM | (0 << 4));
delay(10);      /* 400ns delay */
 7502                 /* Save register contents. */
 7503                 if (chp->_vtbl != NULL) {
scnt = CHP_READ_REG(chp, wdr_seccnt);
sn = CHP_READ_REG(chp, wdr_sector);
cl = CHP_READ_REG(chp, wdr_cyl_lo);
ch = CHP_READ_REG(chp, wdr_cyl_hi);
 7508                 } else {
scnt = bus_space_read_1(chp->cmd_iot,
chp->cmd_ioh, wdr_seccnt & _WDC_REGMASK);
sn = bus_space_read_1(chp->cmd_iot,
chp->cmd_ioh, wdr_sector & _WDC_REGMASK);
cl = bus_space_read_1(chp->cmd_iot,
chp->cmd_ioh, wdr_cyl_lo & _WDC_REGMASK);
ch = bus_space_read_1(chp->cmd_iot,
chp->cmd_ioh, wdr_cyl_hi & _WDC_REGMASK);
 7517                 }
 7518 #if 0
printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n",
sc->sc_wdcdev.sc_dev.dv_xname, chp->channel,
scnt, sn, cl, ch);
 7522 #endif
 7523                 /*
 7524                  * scnt and sn are supposed to be 0x1 for ATAPI, but in some
 7525                  * cases we get wrong values here, so ignore it.
 7526                  */
s = splbio();
 7528                 if (cl == 0x14 && ch == 0xeb)
chp->ch_drive[0].drive_flags |= DRIVE_ATAPI;
 7530                 else
chp->ch_drive[0].drive_flags |= DRIVE_ATA;
splx(s);
printf("%s: port %d: device present",
sc->sc_wdcdev.sc_dev.dv_xname, chp->channel);
 7536                 switch ((sstatus & SStatus_SPD_mask) >> SStatus_SPD_shift) {
 7537                 case 1:
printf(", speed: 1.5Gb/s");
 7539                         break;
 7540                 case 2:
printf(", speed: 3.0Gb/s");
 7542                         break;
 7543                 }
printf("\n");
 7545                 break;
 7547         default:
printf("%s: port %d: unknown SStatus: 0x%08x\n",
sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus);
 7550         }
 7551 }
u_int8_t
svwsata_read_reg(struct channel_softc *chp, enum wdc_regs reg)
 7555 {
 7556         if (reg & _WDC_AUX) {
 7557                 return (bus_space_read_4(chp->ctl_iot, chp->ctl_ioh,
 7558                     (reg & _WDC_REGMASK) << 2));
 7559         } else {
 7560                 return (bus_space_read_4(chp->cmd_iot, chp->cmd_ioh,
 7561                     (reg & _WDC_REGMASK) << 2));
 7562         }
 7563 }
 7565 void
svwsata_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int8_t val)
 7567 {
 7568         if (reg & _WDC_AUX) {
bus_space_write_4(chp->ctl_iot, chp->ctl_ioh,
 7570                     (reg & _WDC_REGMASK) << 2, val);
 7571         } else {
bus_space_write_4(chp->cmd_iot, chp->cmd_ioh,
 7573                     (reg & _WDC_REGMASK) << 2, val);
 7574         }
 7575 }
 7577 void
svwsata_lba48_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int16_t val)
 7579 {
 7580         if (reg & _WDC_AUX) {
bus_space_write_4(chp->ctl_iot, chp->ctl_ioh,
 7582                     (reg & _WDC_REGMASK) << 2, val);
 7583         } else {
bus_space_write_4(chp->cmd_iot, chp->cmd_ioh,
 7585                     (reg & _WDC_REGMASK) << 2, val);
 7586         }
 7587 }
 7589 #define ACARD_IS_850(sc) \
 7590         ((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U)
 7592 void
acard_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
 7594 {
 7595         struct pciide_channel *cp;
 7596         int i;
pcireg_t interface;
bus_size_t cmdsize, ctlsize;
 7600         /*
 7601          * when the chip is in native mode it identifies itself as a
 7602          * 'misc mass storage'. Fake interface in this case.
 7603          */
 7604         if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) {
interface = PCI_INTERFACE(pa->pa_class);
 7606         } else {
interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
 7609         }
printf(": DMA");
pciide_mapreg_dma(sc, pa);
printf("\n");
sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
WDC_CAPABILITY_MODE;
 7617         if (sc->sc_dma_ok) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
sc->sc_wdcdev.irqack = pciide_irqack;
 7621         }
sc->sc_wdcdev.PIO_cap = 4;
sc->sc_wdcdev.DMA_cap = 2;
 7624         switch (sc->sc_pp->ide_product) {
 7625         case PCI_PRODUCT_ACARD_ATP850U:
sc->sc_wdcdev.UDMA_cap = 2;
 7627                 break;
 7628         case PCI_PRODUCT_ACARD_ATP860:
 7629         case PCI_PRODUCT_ACARD_ATP860A:
sc->sc_wdcdev.UDMA_cap = 4;
 7631                 break;
 7632         case PCI_PRODUCT_ACARD_ATP865A:
 7633         case PCI_PRODUCT_ACARD_ATP865R:
sc->sc_wdcdev.UDMA_cap = 6;
 7635                 break;
 7636         }
sc->sc_wdcdev.set_modes = acard_setup_channel;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = 2;
 7642         for (i = 0; i < sc->sc_wdcdev.nchannels; i++) {
cp = &sc->pciide_channels[i];
 7644                 if (pciide_chansetup(sc, i, interface) == 0)
 7645                         continue;
 7646                 if (interface & PCIIDE_INTERFACE_PCI(i)) {
cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize,
 7648                             &ctlsize, pciide_pci_intr);
 7649                 } else {
cp->hw_ok = pciide_mapregs_compat(pa, cp, i,
 7651                             &cmdsize, &ctlsize);
 7652                 }
 7653                 if (cp->hw_ok == 0)
 7654                         return;
cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot;
cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh;
wdcattach(&cp->wdc_channel);
acard_setup_channel(&cp->wdc_channel);
 7659         }
 7660         if (!ACARD_IS_850(sc)) {
u_int32_t reg;
reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL);
reg &= ~ATP860_CTRL_INT;
pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg);
 7665         }
 7666 }
 7668 void
acard_setup_channel(struct channel_softc *chp)
 7670 {
 7671         struct ata_drive_datas *drvp;
 7672         struct pciide_channel *cp = (struct pciide_channel *)chp;
 7673         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 7674         int channel = chp->channel;
 7675         int drive;
u_int32_t idetime, udma_mode;
u_int32_t idedma_ctl;
 7679         /* setup DMA if needed */
pciide_channel_dma_setup(cp);
 7682         if (ACARD_IS_850(sc)) {
idetime = 0;
udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA);
udma_mode &= ~ATP850_UDMA_MASK(channel);
 7686         } else {
idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME);
idetime &= ~ATP860_SETTIME_MASK(channel);
udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA);
udma_mode &= ~ATP860_UDMA_MASK(channel);
 7691         }
idedma_ctl = 0;
 7695         /* Per drive settings */
 7696         for (drive = 0; drive < 2; drive++) {
drvp = &chp->ch_drive[drive];
 7698                 /* If no drive, skip */
 7699                 if ((drvp->drive_flags & DRIVE) == 0)
 7700                         continue;
 7701                 /* add timing values, setup DMA if needed */
 7702                 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) &&
 7703                     (drvp->drive_flags & DRIVE_UDMA)) {
 7704                         /* use Ultra/DMA */
 7705                         if (ACARD_IS_850(sc)) {
idetime |= ATP850_SETTIME(drive,
acard_act_udma[drvp->UDMA_mode],
acard_rec_udma[drvp->UDMA_mode]);
udma_mode |= ATP850_UDMA_MODE(channel, drive,
acard_udma_conf[drvp->UDMA_mode]);
 7711                         } else {
idetime |= ATP860_SETTIME(channel, drive,
acard_act_udma[drvp->UDMA_mode],
acard_rec_udma[drvp->UDMA_mode]);
udma_mode |= ATP860_UDMA_MODE(channel, drive,
acard_udma_conf[drvp->UDMA_mode]);
 7717                         }
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
 7719                 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) &&
 7720                     (drvp->drive_flags & DRIVE_DMA)) {
 7721                         /* use Multiword DMA */
drvp->drive_flags &= ~DRIVE_UDMA;
 7723                         if (ACARD_IS_850(sc)) {
idetime |= ATP850_SETTIME(drive,
acard_act_dma[drvp->DMA_mode],
acard_rec_dma[drvp->DMA_mode]);
 7727                         } else {
idetime |= ATP860_SETTIME(channel, drive,
acard_act_dma[drvp->DMA_mode],
acard_rec_dma[drvp->DMA_mode]);
 7731                         }
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
 7733                 } else {
 7734                         /* PIO only */
drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA);
 7736                         if (ACARD_IS_850(sc)) {
idetime |= ATP850_SETTIME(drive,
acard_act_pio[drvp->PIO_mode],
acard_rec_pio[drvp->PIO_mode]);
 7740                         } else {
idetime |= ATP860_SETTIME(channel, drive,
acard_act_pio[drvp->PIO_mode],
acard_rec_pio[drvp->PIO_mode]);
 7744                         }
pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL,
pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL)
 7747                     | ATP8x0_CTRL_EN(channel));
 7748                 }
 7749         }
 7751         if (idedma_ctl != 0) {
 7752                 /* Add software bits in status register */
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CTL(channel), idedma_ctl);
 7755         }
pciide_print_modes(cp);
 7758         if (ACARD_IS_850(sc)) {
pci_conf_write(sc->sc_pc, sc->sc_tag,
ATP850_IDETIME(channel), idetime);
pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode);
 7762         } else {
pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime);
pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode);
 7765         }
 7766 }
 7768 void
nforce_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
 7770 {
 7771         struct pciide_channel *cp;
 7772         int channel;
pcireg_t interface = PCI_INTERFACE(pa->pa_class);
bus_size_t cmdsize, ctlsize;
u_int32_t conf;
conf = pci_conf_read(sc->sc_pc, sc->sc_tag, NFORCE_CONF);
WDCDEBUG_PRINT(("%s: conf register 0x%x\n",
sc->sc_wdcdev.sc_dev.dv_xname, conf), DEBUG_PROBE);
printf(": DMA");
pciide_mapreg_dma(sc, pa);
sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
WDC_CAPABILITY_MODE;
 7786         if (sc->sc_dma_ok) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
sc->sc_wdcdev.irqack = pciide_irqack;
 7790         }
sc->sc_wdcdev.PIO_cap = 4;
sc->sc_wdcdev.DMA_cap = 2;
 7793         switch (sc->sc_pp->ide_product) {
 7794         case PCI_PRODUCT_NVIDIA_NFORCE_IDE:
sc->sc_wdcdev.UDMA_cap = 5;
 7796                 break;
 7797         default:
sc->sc_wdcdev.UDMA_cap = 6;
 7799         }
sc->sc_wdcdev.set_modes = nforce_setup_channel;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
 7806         for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
cp = &sc->pciide_channels[channel];
 7809                 if (pciide_chansetup(sc, channel, interface) == 0)
 7810                         continue;
 7812                 if ((conf & NFORCE_CHAN_EN(channel)) == 0) {
printf("%s: %s ignored (disabled)\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
 7815                         continue;
 7816                 }
pciide_map_compat_intr(pa, cp, channel, interface);
 7819                 if (cp->hw_ok == 0)
 7820                         continue;
pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
nforce_pci_intr);
 7823                 if (cp->hw_ok == 0) {
pciide_unmap_compat_intr(pa, cp, channel, interface);
 7825                         continue;
 7826                 }
 7828                 if (pciide_chan_candisable(cp)) {
conf &= ~NFORCE_CHAN_EN(channel);
pciide_unmap_compat_intr(pa, cp, channel, interface);
 7831                         continue;
 7832                 }
sc->sc_wdcdev.set_modes(&cp->wdc_channel);
 7835         }
WDCDEBUG_PRINT(("%s: new conf register 0x%x\n",
sc->sc_wdcdev.sc_dev.dv_xname, conf), DEBUG_PROBE);
pci_conf_write(sc->sc_pc, sc->sc_tag, NFORCE_CONF, conf);
 7839 }
 7841 void
nforce_setup_channel(struct channel_softc *chp)
 7843 {
 7844         struct ata_drive_datas *drvp;
 7845         int drive, mode;
u_int32_t idedma_ctl;
 7847         struct pciide_channel *cp = (struct pciide_channel *)chp;
 7848         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 7849         int channel = chp->channel;
u_int32_t conf, piodmatim, piotim, udmatim;
conf = pci_conf_read(sc->sc_pc, sc->sc_tag, NFORCE_CONF);
piodmatim = pci_conf_read(sc->sc_pc, sc->sc_tag, NFORCE_PIODMATIM);
piotim = pci_conf_read(sc->sc_pc, sc->sc_tag, NFORCE_PIOTIM);
udmatim = pci_conf_read(sc->sc_pc, sc->sc_tag, NFORCE_UDMATIM);
WDCDEBUG_PRINT(("%s: %s old timing values: piodmatim=0x%x, "
 7857             "piotim=0x%x, udmatim=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname,
cp->name, piodmatim, piotim, udmatim), DEBUG_PROBE);
 7860         /* Setup DMA if needed */
pciide_channel_dma_setup(cp);
 7863         /* Clear all bits for this channel */
idedma_ctl = 0;
piodmatim &= ~NFORCE_PIODMATIM_MASK(channel);
udmatim &= ~NFORCE_UDMATIM_MASK(channel);
 7868         /* Per channel settings */
 7869         for (drive = 0; drive < 2; drive++) {
drvp = &chp->ch_drive[drive];
 7872                 /* If no drive, skip */
 7873                 if ((drvp->drive_flags & DRIVE) == 0)
 7874                         continue;
 7876                 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) != 0 &&
 7877                     (drvp->drive_flags & DRIVE_UDMA) != 0) {
 7878                         /* Setup UltraDMA mode */
drvp->drive_flags &= ~DRIVE_DMA;
udmatim |= NFORCE_UDMATIM_SET(channel, drive,
nforce_udma[drvp->UDMA_mode]) |
NFORCE_UDMA_EN(channel, drive) |
NFORCE_UDMA_ENM(channel, drive);
mode = drvp->PIO_mode;
 7887                 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) != 0 &&
 7888                     (drvp->drive_flags & DRIVE_DMA) != 0) {
 7889                         /* Setup multiword DMA mode */
drvp->drive_flags &= ~DRIVE_UDMA;
 7892                         /* mode = min(pio, dma + 2) */
 7893                         if (drvp->PIO_mode <= (drvp->DMA_mode + 2))
mode = drvp->PIO_mode;
 7895                         else
mode = drvp->DMA_mode + 2;
 7897                 } else {
mode = drvp->PIO_mode;
 7899                         goto pio;
 7900                 }
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
pio:
 7904                 /* Setup PIO mode */
 7905                 if (mode <= 2) {
drvp->DMA_mode = 0;
drvp->PIO_mode = 0;
mode = 0;
 7909                 } else {
drvp->PIO_mode = mode;
drvp->DMA_mode = mode - 2;
 7912                 }
piodmatim |= NFORCE_PIODMATIM_SET(channel, drive,
nforce_pio[mode]);
 7915         }
 7917         if (idedma_ctl != 0) {
 7918                 /* Add software bits in status register */
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CTL(channel), idedma_ctl);
 7921         }
WDCDEBUG_PRINT(("%s: %s new timing values: piodmatim=0x%x, "
 7924             "piotim=0x%x, udmatim=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname,
cp->name, piodmatim, piotim, udmatim), DEBUG_PROBE);
pci_conf_write(sc->sc_pc, sc->sc_tag, NFORCE_PIODMATIM, piodmatim);
pci_conf_write(sc->sc_pc, sc->sc_tag, NFORCE_UDMATIM, udmatim);
pciide_print_modes(cp);
 7930 }
 7932 int
nforce_pci_intr(void *arg)
 7934 {
 7935         struct pciide_softc *sc = arg;
 7936         struct pciide_channel *cp;
 7937         struct channel_softc *wdc_cp;
 7938         int i, rv, crv;
u_int32_t dmastat;
rv = 0;
 7942         for (i = 0; i < sc->sc_wdcdev.nchannels; i++) {
cp = &sc->pciide_channels[i];
wdc_cp = &cp->wdc_channel;
 7946                 /* Skip compat channel */
 7947                 if (cp->compat)
 7948                         continue;
dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CTL(i));
 7952                 if ((dmastat & IDEDMA_CTL_INTR) == 0)
 7953                         continue;
crv = wdcintr(wdc_cp);
 7956                 if (crv == 0)
printf("%s:%d: bogus intr\n",
sc->sc_wdcdev.sc_dev.dv_xname, i);
 7959                 else
rv = 1;
 7961         }
 7962         return (rv);
 7963 }
 7965 void
artisea_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
 7967 {
 7968         struct pciide_channel *cp;
bus_size_t cmdsize, ctlsize;
pcireg_t interface;
 7971         int channel;
printf(": DMA");
 7974 #ifdef PCIIDE_I31244_DISABLEDMA
 7975         if (sc->sc_rev == 0) {
printf(" disabled due to rev. 0");
sc->sc_dma_ok = 0;
 7978         } else
 7979 #endif
pciide_mapreg_dma(sc, pa);
printf("\n");
 7983         /*
 7984          * XXX Configure LEDs to show activity.
 7985          */
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
WDC_CAPABILITY_MODE | WDC_CAPABILITY_SATA;
sc->sc_wdcdev.PIO_cap = 4;
 7990         if (sc->sc_dma_ok) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
sc->sc_wdcdev.irqack = pciide_irqack;
sc->sc_wdcdev.DMA_cap = 2;
sc->sc_wdcdev.UDMA_cap = 6;
 7996         }
sc->sc_wdcdev.set_modes = sata_setup_channel;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
interface = PCI_INTERFACE(pa->pa_class);
 8004         for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
cp = &sc->pciide_channels[channel];
 8006                 if (pciide_chansetup(sc, channel, interface) == 0)
 8007                         continue;
pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
pciide_pci_intr);
 8010                 if (cp->hw_ok == 0)
 8011                         continue;
pciide_map_compat_intr(pa, cp, channel, interface);
sata_setup_channel(&cp->wdc_channel);
 8014         }
 8015 }
 8017 void
ite_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
 8019 {
 8020         struct pciide_channel *cp;
 8021         int channel;
pcireg_t interface;
bus_size_t cmdsize, ctlsize;
pcireg_t cfg, modectl;
 8026         /*
 8027          * Fake interface since IT8212F is claimed to be a ``RAID'' device.
 8028          */
interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
cfg = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_CFG);
modectl = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_MODE);
WDCDEBUG_PRINT(("%s: cfg=0x%x, modectl=0x%x\n",
sc->sc_wdcdev.sc_dev.dv_xname, cfg & IT_CFG_MASK,
modectl & IT_MODE_MASK), DEBUG_PROBE);
printf(": DMA");
pciide_mapreg_dma(sc, pa);
sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
WDC_CAPABILITY_MODE;
 8043         if (sc->sc_dma_ok) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
sc->sc_wdcdev.irqack = pciide_irqack;
 8047         }
sc->sc_wdcdev.PIO_cap = 4;
sc->sc_wdcdev.DMA_cap = 2;
sc->sc_wdcdev.UDMA_cap = 6;
sc->sc_wdcdev.set_modes = ite_setup_channel;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
 8058         /* Disable RAID */
modectl &= ~IT_MODE_RAID1;
 8060         /* Disable CPU firmware mode */
modectl &= ~IT_MODE_CPU;
pci_conf_write(sc->sc_pc, sc->sc_tag, IT_MODE, modectl);
 8065         for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
cp = &sc->pciide_channels[channel];
 8068                 if (pciide_chansetup(sc, channel, interface) == 0)
 8069                         continue;
pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
pciide_pci_intr);
sc->sc_wdcdev.set_modes(&cp->wdc_channel);
 8073         }
 8075         /* Re-read configuration registers after channels setup */
cfg = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_CFG);
modectl = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_MODE);
WDCDEBUG_PRINT(("%s: cfg=0x%x, modectl=0x%x\n",
sc->sc_wdcdev.sc_dev.dv_xname, cfg & IT_CFG_MASK,
modectl & IT_MODE_MASK), DEBUG_PROBE);
 8081 }
 8083 void
ite_setup_channel(struct channel_softc *chp)
 8085 {
 8086         struct ata_drive_datas *drvp;
 8087         int drive, mode;
u_int32_t idedma_ctl;
 8089         struct pciide_channel *cp = (struct pciide_channel *)chp;
 8090         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 8091         int channel = chp->channel;
pcireg_t cfg, modectl;
pcireg_t tim;
cfg = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_CFG);
modectl = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_MODE);
tim = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_TIM(channel));
WDCDEBUG_PRINT(("%s:%d: tim=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname,
channel, tim), DEBUG_PROBE);
 8101         /* Setup DMA if needed */
pciide_channel_dma_setup(cp);
 8104         /* Clear all bits for this channel */
idedma_ctl = 0;
 8107         /* Per channel settings */
 8108         for (drive = 0; drive < 2; drive++) {
drvp = &chp->ch_drive[drive];
 8111                 /* If no drive, skip */
 8112                 if ((drvp->drive_flags & DRIVE) == 0)
 8113                         continue;
 8115                 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) != 0 &&
 8116                     (drvp->drive_flags & DRIVE_UDMA) != 0) {
 8117                         /* Setup UltraDMA mode */
drvp->drive_flags &= ~DRIVE_DMA;
modectl &= ~IT_MODE_DMA(channel, drive);
 8121 #if 0
 8122                         /* Check cable, works only in CPU firmware mode */
 8123                         if (drvp->UDMA_mode > 2 &&
 8124                             (cfg & IT_CFG_CABLE(channel, drive)) == 0) {
WDCDEBUG_PRINT(("%s(%s:%d:%d): "
 8126                                     "80-wire cable not detected\n",
drvp->drive_name,
sc->sc_wdcdev.sc_dev.dv_xname,
channel, drive), DEBUG_PROBE);
drvp->UDMA_mode = 2;
 8131                         }
 8132 #endif
 8134                         if (drvp->UDMA_mode >= 5)
tim |= IT_TIM_UDMA5(drive);
 8136                         else
tim &= ~IT_TIM_UDMA5(drive);
mode = drvp->PIO_mode;
 8140                 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) != 0 &&
 8141                     (drvp->drive_flags & DRIVE_DMA) != 0) {
 8142                         /* Setup multiword DMA mode */
drvp->drive_flags &= ~DRIVE_UDMA;
modectl |= IT_MODE_DMA(channel, drive);
 8146                         /* mode = min(pio, dma + 2) */
 8147                         if (drvp->PIO_mode <= (drvp->DMA_mode + 2))
mode = drvp->PIO_mode;
 8149                         else
mode = drvp->DMA_mode + 2;
 8151                 } else {
 8152                         goto pio;
 8153                 }
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
pio:
 8157                 /* Setup PIO mode */
 8158                 if (mode <= 2) {
drvp->DMA_mode = 0;
drvp->PIO_mode = 0;
mode = 0;
 8162                 } else {
drvp->PIO_mode = mode;
drvp->DMA_mode = mode - 2;
 8165                 }
 8167                 /* Enable IORDY if PIO mode >= 3 */
 8168                 if (drvp->PIO_mode >= 3)
cfg |= IT_CFG_IORDY(channel);
 8170         }
WDCDEBUG_PRINT(("%s: tim=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname,
tim), DEBUG_PROBE);
pci_conf_write(sc->sc_pc, sc->sc_tag, IT_CFG, cfg);
pci_conf_write(sc->sc_pc, sc->sc_tag, IT_MODE, modectl);
pci_conf_write(sc->sc_pc, sc->sc_tag, IT_TIM(channel), tim);
 8179         if (idedma_ctl != 0) {
 8180                 /* Add software bits in status register */
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CTL(channel), idedma_ctl);
 8183         }
pciide_print_modes(cp);
 8186 }
 8188 void
ixp_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
 8190 {
 8191         struct pciide_channel *cp;
 8192         int channel;
pcireg_t interface = PCI_INTERFACE(pa->pa_class);
bus_size_t cmdsize, ctlsize;
printf(": DMA");
pciide_mapreg_dma(sc, pa);
sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
WDC_CAPABILITY_MODE;
 8201         if (sc->sc_dma_ok) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
sc->sc_wdcdev.irqack = pciide_irqack;
 8205         }
sc->sc_wdcdev.PIO_cap = 4;
sc->sc_wdcdev.DMA_cap = 2;
sc->sc_wdcdev.UDMA_cap = 6;
sc->sc_wdcdev.set_modes = ixp_setup_channel;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
 8216         for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
cp = &sc->pciide_channels[channel];
 8218                 if (pciide_chansetup(sc, channel, interface) == 0)
 8219                         continue;
pciide_map_compat_intr(pa, cp, channel, interface);
 8221                 if (cp->hw_ok == 0)
 8222                         continue;
pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
pciide_pci_intr);
 8225                 if (cp->hw_ok == 0) {
pciide_unmap_compat_intr(pa, cp, channel, interface);
 8227                         continue;
 8228                 }
sc->sc_wdcdev.set_modes(&cp->wdc_channel);
 8230         }
 8231 }
 8233 void
ixp_setup_channel(struct channel_softc *chp)
 8235 {
 8236         struct ata_drive_datas *drvp;
 8237         int drive, mode;
u_int32_t idedma_ctl;
 8239         struct pciide_channel *cp = (struct pciide_channel*)chp;
 8240         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 8241         int channel = chp->channel;
pcireg_t udma, mdma_timing, pio, pio_timing;
pio_timing = pci_conf_read(sc->sc_pc, sc->sc_tag, IXP_PIO_TIMING);
pio = pci_conf_read(sc->sc_pc, sc->sc_tag, IXP_PIO_CTL);
mdma_timing = pci_conf_read(sc->sc_pc, sc->sc_tag, IXP_MDMA_TIMING);
udma = pci_conf_read(sc->sc_pc, sc->sc_tag, IXP_UDMA_CTL);
 8249         /* Setup DMA if needed */
pciide_channel_dma_setup(cp);
idedma_ctl = 0;
 8254         /* Per channel settings */
 8255         for (drive = 0; drive < 2; drive++) {
drvp = &chp->ch_drive[drive];
 8258                 /* If no drive, skip */
 8259                 if ((drvp->drive_flags & DRIVE) == 0)
 8260                         continue;
 8261                 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) != 0 &&
 8262                     (drvp->drive_flags & DRIVE_UDMA) != 0) {
 8263                         /* Setup UltraDMA mode */
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
IXP_UDMA_ENABLE(udma, chp->channel, drive);
IXP_SET_MODE(udma, chp->channel, drive,
drvp->UDMA_mode);
mode = drvp->PIO_mode;
 8269                 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) != 0 &&
 8270                     (drvp->drive_flags & DRIVE_DMA) != 0) {
 8271                         /* Setup multiword DMA mode */
drvp->drive_flags &= ~DRIVE_UDMA;
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
IXP_UDMA_DISABLE(udma, chp->channel, drive);
IXP_SET_TIMING(mdma_timing, chp->channel, drive,
ixp_mdma_timings[drvp->DMA_mode]);
 8278                         /* mode = min(pio, dma + 2) */
 8279                         if (drvp->PIO_mode <= (drvp->DMA_mode + 2))
mode = drvp->PIO_mode;
 8281                         else
mode = drvp->DMA_mode + 2;
 8283                 } else {
mode = drvp->PIO_mode;
 8285                 }
 8287                 /* Setup PIO mode */
drvp->PIO_mode = mode;
 8289                 if (mode < 2)
drvp->DMA_mode = 0;
 8291                 else
drvp->DMA_mode = mode - 2;
 8293                 /*
 8294                  * Set PIO mode and timings
 8295                  * Linux driver avoids PIO mode 1, let's do it too.
 8296                  */
 8297                 if (drvp->PIO_mode == 1)
drvp->PIO_mode = 0;
IXP_SET_MODE(pio, chp->channel, drive, drvp->PIO_mode);
IXP_SET_TIMING(pio_timing, chp->channel, drive,
ixp_pio_timings[drvp->PIO_mode]);
 8303         }
pci_conf_write(sc->sc_pc, sc->sc_tag, IXP_UDMA_CTL, udma);
pci_conf_write(sc->sc_pc, sc->sc_tag, IXP_MDMA_TIMING, mdma_timing);
pci_conf_write(sc->sc_pc, sc->sc_tag, IXP_PIO_CTL, pio);
pci_conf_write(sc->sc_pc, sc->sc_tag, IXP_PIO_TIMING, pio_timing);
 8310         if (idedma_ctl != 0) {
 8311                 /* Add software bits in status register */
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CTL(channel), idedma_ctl);
 8314         }
pciide_print_modes(cp);
 8317 }
 8319 void
jmicron_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
 8321 {
 8322         struct pciide_channel *cp;
 8323         int channel;
pcireg_t interface = PCI_INTERFACE(pa->pa_class);
bus_size_t cmdsize, ctlsize;
u_int32_t conf;
conf = pci_conf_read(sc->sc_pc, sc->sc_tag, JMICRON_CONF);
WDCDEBUG_PRINT(("%s: conf register 0x%x\n",
sc->sc_wdcdev.sc_dev.dv_xname, conf), DEBUG_PROBE);
printf(": DMA");
pciide_mapreg_dma(sc, pa);
sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
WDC_CAPABILITY_MODE;
 8337         if (sc->sc_dma_ok) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
sc->sc_wdcdev.irqack = pciide_irqack;
 8341         }
sc->sc_wdcdev.PIO_cap = 4;
sc->sc_wdcdev.DMA_cap = 2;
sc->sc_wdcdev.UDMA_cap = 6;
sc->sc_wdcdev.set_modes = jmicron_setup_channel;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
 8351         for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
cp = &sc->pciide_channels[channel];
 8354                 if (pciide_chansetup(sc, channel, interface) == 0)
 8355                         continue;
 8357 #if 0
 8358                 if ((conf & JMICRON_CHAN_EN(channel)) == 0) {
printf("%s: %s ignored (disabled)\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
 8361                         continue;
 8362                 }
 8363 #endif
pciide_map_compat_intr(pa, cp, channel, interface);
 8366                 if (cp->hw_ok == 0)
 8367                         continue;
pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
pciide_pci_intr);
 8370                 if (cp->hw_ok == 0) {
pciide_unmap_compat_intr(pa, cp, channel, interface);
 8372                         continue;
 8373                 }
 8375                 if (pciide_chan_candisable(cp)) {
conf &= ~JMICRON_CHAN_EN(channel);
pciide_unmap_compat_intr(pa, cp, channel, interface);
 8378                         continue;
 8379                 }
sc->sc_wdcdev.set_modes(&cp->wdc_channel);
 8382         }
WDCDEBUG_PRINT(("%s: new conf register 0x%x\n",
sc->sc_wdcdev.sc_dev.dv_xname, conf), DEBUG_PROBE);
pci_conf_write(sc->sc_pc, sc->sc_tag, NFORCE_CONF, conf);
 8386 }
 8388 void
jmicron_setup_channel(struct channel_softc *chp)
 8390 {
 8391         struct ata_drive_datas *drvp;
 8392         int drive, mode;
u_int32_t idedma_ctl;
 8394         struct pciide_channel *cp = (struct pciide_channel *)chp;
 8395         struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
 8396         int channel = chp->channel;
u_int32_t conf;
conf = pci_conf_read(sc->sc_pc, sc->sc_tag, JMICRON_CONF);
 8401         /* Setup DMA if needed */
pciide_channel_dma_setup(cp);
 8404         /* Clear all bits for this channel */
idedma_ctl = 0;
 8407         /* Per channel settings */
 8408         for (drive = 0; drive < 2; drive++) {
drvp = &chp->ch_drive[drive];
 8411                 /* If no drive, skip */
 8412                 if ((drvp->drive_flags & DRIVE) == 0)
 8413                         continue;
 8415                 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) != 0 &&
 8416                     (drvp->drive_flags & DRIVE_UDMA) != 0) {
 8417                         /* Setup UltraDMA mode */
drvp->drive_flags &= ~DRIVE_DMA;
 8420                         /* see if cable is up to scratch */
 8421                         if ((conf & JMICRON_CONF_40PIN) &&
 8422                             (drvp->UDMA_mode > 2))
drvp->UDMA_mode = 2;
mode = drvp->PIO_mode;
 8426                 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) != 0 &&
 8427                     (drvp->drive_flags & DRIVE_DMA) != 0) {
 8428                         /* Setup multiword DMA mode */
drvp->drive_flags &= ~DRIVE_UDMA;
 8431                         /* mode = min(pio, dma + 2) */
 8432                         if (drvp->PIO_mode <= (drvp->DMA_mode + 2))
mode = drvp->PIO_mode;
 8434                         else
mode = drvp->DMA_mode + 2;
 8436                 } else {
mode = drvp->PIO_mode;
 8438                         goto pio;
 8439                 }
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
pio:
 8443                 /* Setup PIO mode */
 8444                 if (mode <= 2) {
drvp->DMA_mode = 0;
drvp->PIO_mode = 0;
mode = 0;
 8448                 } else {
drvp->PIO_mode = mode;
drvp->DMA_mode = mode - 2;
 8451                 }
 8452         }
 8454         if (idedma_ctl != 0) {
 8455                 /* Add software bits in status register */
bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_CTL(channel), idedma_ctl);
 8458         }
pciide_print_modes(cp);
 8461 }