root/dev/pci/pciide_hpt_reg.h

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INCLUDED FROM

    1 /*      $OpenBSD: pciide_hpt_reg.h,v 1.10 2004/09/24 07:38:38 grange Exp $      */
    2 /*      $NetBSD: pciide_hpt_reg.h,v 1.4 2001/07/23 14:55:27 bouyer Exp $       */
    3 
    4 /*
    5  * Copyright (c) 2000 Manuel Bouyer.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. All advertising materials mentioning features or use of this software
   16  *    must display the following acknowledgement:
   17  *      This product includes software developed by Manuel Bouyer.
   18  * 4. Neither the name of the University nor the names of its contributors
   19  *    may be used to endorse or promote products derived from this software
   20  *    without specific prior written permission.
   21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   22  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   23  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   31  *
   32  */
   33 
   34 #ifndef _DEV_PCI_PCIIDE_HPT_REG_H_
   35 #define _DEV_PCI_PCIIDE_HPT_REG_H_
   36 
   37 /*
   38  * Register definitions for Highpoint PCI IDE controllers.
   39  *
   40  * The HPT366 has 2 PCI IDE functions, each of them has only one channel.
   41  * The HPT370 and HPT372 has the 2 channels on the same PCI IDE function.
   42  */
   43 
   44 /*
   45  * The HPT366, HPT370 and HPT372 have the same vendor/device ID but not the
   46  * same revision.
   47  */
   48 #define HPT366_REV 0x01
   49 #define HPT370_REV 0x03
   50 #define HPT370A_REV 0x04
   51 #define HPT372_REV 0x05
   52 #define HPT374_REV 0x07
   53 
   54 #define HPT_IDETIM(chan, drive) (0x40 + ((drive) * 4) + ((chan) * 8))
   55 #define HPT_IDETIM_BUFEN                0x80000000
   56 #define HPT_IDETIM_MSTEN                0x40000000
   57 #define HPT_IDETIM_DMAEN                0x20000000
   58 #define HPT_IDETIM_UDMAEN               0x10000000
   59 
   60 #define HPT366_CTRL1            0x50
   61 #define HPT366_CTRL1_BLKDIS(chan)       (0x40 << (chan))
   62 #define HPT366_CTRL1_CHANEN(chan)       (0x10 << (chan))
   63 #define HPT366_CTRL1_CLRBUF(chan)       (0x04 << (chan))
   64 #define HPT366_CTRL1_LEG(chan)          (0x01 << (chan))
   65 
   66 #define HPT366_CTRL2            0x51
   67 #define HPT366_CTRL2_FASTIRQ            0x80
   68 #define HPT366_CTRL2_HOLDIRQ(chan)      (0x20 << (chan))
   69 #define HPT366_CTRL2_SGEN               0x10
   70 #define HPT366_CTRL2_CLEARFIFO(chan)    (0x04 << (chan))
   71 #define HPT366_CTRL2_CLEARBMSM          0x02
   72 #define HPT366_CTRL2_CLEARSG            0x01
   73 
   74 #define HPT366_CTRL3(chan)      (0x52 + ((chan) * 4))
   75 #define HPT366_CTRL3_PDMA               0x8000
   76 #define HPT366_CTRL3_BP                 0x4000
   77 #define HPT366_CTRL3_FASTIRQ_OFFSET     9
   78 #define HPT366_CTRL3_FASTIRQ_MASK       0x3
   79 
   80 #define HPT370_CTRL1(chan)      (0x50 + ((chan) * 4))
   81 #define HPT370_CTRL1_CLRSG              0x80
   82 #define HPT370_CTRL1_READF              0x40
   83 #define HPT370_CTRL1_CLRST              0x20
   84 #define HPT370_CTRL1_CLRSGC             0x10
   85 #define HPT370_CTRL1_BLKDIS             0x08
   86 #define HPT370_CTRL1_EN                 0x04
   87 #define HPT370_CTRL1_CLRDBUF            0x02
   88 #define HPT370_CTRL1_LEGEN              0x01
   89 
   90 #define HPT370_CTRL2(chan)      (0x51 + ((chan) * 4))
   91 #define HPT370_CTRL2_FASTIRQ            0x02
   92 #define HPT370_CTRL2_HIRQ               0x01
   93 
   94 #define HPT370_CTRL3(chan)      (0x52 + ((chan) * 4))
   95 #define HPT370_CTRL3_HIZ                0x8000
   96 #define HPT370_CTRL3_BP                 0x4000
   97 #define HPT370_CTRL3_FASTIRQ_OFFSET     9
   98 #define HPT370_CTRL3_FASTIRQ_MASK       0x3
   99 
  100 #define HPT_STAT1               0x58
  101 #define HPT_STAT1_IRQPOLL(chan)         (0x40 << (chan)) /* 366 only */
  102 #define HPT_STAT1_DMARQ(chan)           (0x04 << ((chan) * 3))
  103 #define HPT_STAT1_DMACK(chan)           (0x02 << ((chan) * 3))
  104 #define HPT_STAT1_IORDY(chan)           (0x01 << ((chan) * 3))
  105 
  106 #define HPT_STAT2               0x59
  107 #define HPT_STAT2_FLT_RST               0x40 /* 366 only */
  108 #define HPT_STAT2_RST(chan)             (0x40 << (chan))  /* 370 only */
  109 #define HPT_STAT2_POLLEN(chan)          (0x04 << ((chan) * 3))
  110 #define HPT_STAT2_IRQD1(chan)           (0x02 << ((chan) * 3))
  111 #define HPT_STAT2_IRQD0_CH1             0x08
  112 #define HPT_STAT2_POLLST                0x01
  113 
  114 #define HPT_CSEL                0x5a
  115 #define HPT_CSEL_IRQDIS                 0x10 /* 370 only */
  116 #define HPT_CSEL_PCIDIS                 0x08 /* 370 only */
  117 #define HPT_CSEL_PCIWR                  0x04 /* 370 only */
  118 #define HPT_CSEL_CBLID(chan)             (0x01 << (1 - (chan)))
  119 
  120 #define HPT_SC2         0x5b
  121 #define HPT_SC2_OSC_OK  0x80
  122 #define HPT_SC2_OSC_EN  0x20
  123 #define HPT_SC2_ECLK    0x10
  124 #define HPT_SC2_BPIO    0x08
  125 #define HPT_SC2_DMARQW  0x04
  126 #define HPT_SC2_SCLK    0x02
  127 #define HPT_SC2_MAEN    0x01
  128 
  129 static u_int32_t hpt366_pio[] =
  130         {0x00d0a7aa, 0x00c8a753, 0x00c8a742, 0x00c8a731};
  131 static u_int32_t hpt366_dma[] =
  132         {0x20c8a797, 0x20c8a742, 0x20c8a731};
  133 static u_int32_t hpt366_udma[] =
  134         {0x10c8a731, 0x10cba731, 0x10caa731, 0x10cfa731, 0x10c9a731};
  135 
  136 static u_int32_t hpt370_pio[] =
  137         {0x06914e8a, 0x06914e65, 0x06514e33, 0x06514e22, 0x06514e21};
  138 static u_int32_t hpt370_dma[] =
  139         {0x26514e97, 0x26514e33, 0x26514e21};
  140 static u_int32_t hpt370_udma[] =
  141         {0x16514e31, 0x164d4e31, 0x16494e31, 0x166d4e31, 0x16454e31,
  142          0x16454e31};
  143 
  144 static u_int32_t hpt372_pio[] =
  145         {0x0d029d5e, 0x0d029d26, 0x0c829ca6, 0x0c829c84, 0x0c829c62};
  146 static u_int32_t hpt372_dma[] =
  147         {0x2c82922e, 0x2c829266, 0x2c829262};
  148 static u_int32_t hpt372_udma[] =
  149         {0x1c82dc62, 0x1c9adc62, 0x1c91dc62, 0x1c8edc62, 0x1c8ddc62,
  150          0x1c6ddc62, 0x1c81dc62};
  151 
  152 static u_int32_t hpt374_pio[] =
  153         {0x0ac1f48a, 0x0ac1f465, 0x0a81f454, 0x0a81f443, 0x0a81f442};
  154 static u_int32_t hpt374_dma[] =
  155         {0x228082ea, 0x22808254, 0x22808242};
  156 static u_int32_t hpt374_udma[] =
  157         {0x121882ea, 0x12148254, 0x120c8242, 0x128c8242, 0x12ac8242,
  158          0x12848242, 0x12808242};
  159 
  160 #endif  /* !_DEV_PCI_PCIIDE_HPT_REG_H_ */
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