1 /* $OpenBSD: pciide_opti_reg.h,v 1.3 2004/09/24 07:38:38 grange Exp $ */
2 /* $NetBSD: pciide_opti_reg.h,v 1.2 2000/06/07 20:42:53 scw Exp $ */
3
4 /*-
5 * Copyright (c) 2000 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Steve C. Woodford.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the NetBSD
22 * Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39
40 #ifndef _DEV_PCI_PCIIDE_OPTI_REG_H_
41 #define _DEV_PCI_PCIIDE_OPTI_REG_H_
42
43 /*
44 * Register definitions for OPTi PCIIDE controllers based on
45 * their 82c621 chip.
46 */
47
48 /* IDE Initialization Control Register */
49 #define OPTI_REG_INIT_CONTROL 0x40
50 #define OPTI_INIT_CONTROL_MODE_PIO_0 0
51 #define OPTI_INIT_CONTROL_MODE_PIO_1 2
52 #define OPTI_INIT_CONTROL_MODE_PIO_2 1
53 #define OPTI_INIT_CONTROL_MODE_PIO_3 3
54 #define OPTI_INIT_CONTROL_ADDR_RELOC (1u << 2)
55 #define OPTI_INIT_CONTROL_CH2_ENABLE 0
56 #define OPTI_INIT_CONTROL_CH2_DISABLE (1u << 3)
57 #define OPTI_INIT_CONTROL_FIFO_16 0
58 #define OPTI_INIT_CONTROL_FIFO_32 (1u << 5)
59 #define OPTI_INIT_CONTROL_FIFO_REQ_32 0
60 #define OPTI_INIT_CONTROL_FIFO_REQ_30 (1u << 6)
61 #define OPTI_INIT_CONTROL_FIFO_REQ_28 (2u << 6)
62 #define OPTI_INIT_CONTROL_FIFO_REQ_26 (3u << 6)
63
64 /* IDE Enhanced Features Register */
65 #define OPTI_REG_ENH_FEAT 0x42
66 #define OPTI_ENH_FEAT_X111_ENABLE (1u << 1)
67 #define OPTI_ENH_FEAT_CONCURRENT_MAST (1u << 2)
68 #define OPTI_ENH_FEAT_PCI_INVALIDATE (1u << 3)
69 #define OPTI_ENH_FEAT_IDE_CONCUR (1u << 4)
70 #define OPTI_ENH_FEAT_SLAVE_FIFO_ISA (1u << 5)
71
72 /* IDE Enhanced Mode Register */
73 #define OPTI_REG_ENH_MODE 0x43
74 #define OPTI_ENH_MODE_MASK(c,d) (3u << (((c) * 4) + ((d) * 2)))
75 #define OPTI_ENH_MODE_USE_TIMING(c,d) 0
76 #define OPTI_ENH_MODE(c,d,m) ((m) << (((c) * 4) + ((d) * 2)))
77
78 /* Timing registers */
79 #define OPTI_REG_READ_CYCLE_TIMING 0x00
80 #define OPTI_REG_WRITE_CYCLE_TIMING 0x01
81 #define OPTI_RECOVERY_TIME_SHIFT 0
82 #define OPTI_PULSE_WIDTH_SHIFT 4
83
84 /*
85 * Control register.
86 */
87 #define OPTI_REG_CONTROL 0x03
88 #define OPTI_CONTROL_DISABLE 0x11
89 #define OPTI_CONTROL_ENABLE 0x95
90
91 /* Strap register */
92 #define OPTI_REG_STRAP 0x05
93 #define OPTI_STRAP_PCI_SPEED_MASK 0x1u
94 #define OPTI_STRAP_PCI_33 0
95 #define OPTI_STRAP_PCI_25 1
96
97 /* Miscellaneous register */
98 #define OPTI_REG_MISC 0x06
99 #define OPTI_MISC_INDEX(d) ((unsigned)(d))
100 #define OPTI_MISC_INDEX_MASK 0x01u
101 #define OPTI_MISC_DELAY_MASK 0x07u
102 #define OPTI_MISC_DELAY_SHIFT 1
103 #define OPTI_MISC_ADDR_SETUP_MASK 0x3u
104 #define OPTI_MISC_ADDR_SETUP_SHIFT 4
105 #define OPTI_MISC_READ_PREFETCH_ENABLE (1u << 6)
106 #define OPTI_MISC_ADDR_SETUP_MASK 0x3u
107 #define OPTI_MISC_WRITE_MASK 0x7fu
108
109 /*
110 * These are the timing register values for the various IDE modes
111 * supported by the OPTi chip. The first index of the two-dimensional
112 * arrays is used for a 33MHz PCIbus, the second for a 25MHz PCIbus.
113 */
114 const static u_int8_t opti_tim_cp[2][8] = { /* Command Pulse */
115 {5, 4, 3, 2, 2, 7, 2, 2},
116 {4, 3, 2, 2, 1, 5, 2, 1}
117 };
118
119 const static u_int8_t opti_tim_rt[2][8] = { /* Recovery Time */
120 {9, 4, 0, 0, 0, 6, 0, 0},
121 {6, 2, 0, 0, 0, 4, 0, 0}
122 };
123
124 const static u_int8_t opti_tim_as[2][8] = { /* Address Setup */
125 {2, 1, 1, 1, 0, 0, 0, 0},
126 {1, 1, 0, 0, 0, 0, 0, 0}
127 };
128
129 const static u_int8_t opti_tim_em[8] = { /* Enhanced Mode */
130 0, 0, 0, 1, 2, 0, 1 ,2
131 };
132
133 #endif /* !_DEV_PCI_PCIIDE_OPTI_REG_H_ */