1 /* $OpenBSD: pciide_amd_reg.h,v 1.8 2004/09/24 07:38:38 grange Exp $ */
2 /* $NetBSD: pciide_amd_reg.h,v 1.2 2000/07/06 15:08:11 bouyer Exp $ */
3
4 /*
5 * Copyright (c) 2000 David Sainty.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by the University of
18 * California, Berkeley and its contributors.
19 * 4. Neither the name of the University nor the names of its contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 *
35 */
36
37 #ifndef _DEV_PCI_PCIIDE_AMD_REG_H_
38 #define _DEV_PCI_PCIIDE_AMD_REG_H_
39
40 /*
41 * Registers definitions for AMD 756 PCI IDE controller. Documentation
42 * available at: http://www.amd.com/products/cpg/athlon/techdocs/pdf/22548.pdf
43 */
44
45 /* Chip revisions */
46 #define AMD756_CHIPREV_D2 3
47
48 /* Chip revision tests */
49
50 /*
51 * The AMD756 chip revision D2 has a bug affecting DMA (but not UDMA)
52 * modes. The workaround documented by AMD is to not use DMA on any
53 * drive which does not support UDMA modes.
54 *
55 * See: http://www.amd.com/products/cpg/athlon/techdocs/pdf/22591.pdf
56 */
57 #define AMD756_CHIPREV_DISABLEDMA(product, rev) \
58 ((product) == PCI_PRODUCT_AMD_PBC756_IDE && (rev) <= AMD756_CHIPREV_D2)
59
60 /* Channel enable */
61 #define AMD756_CHANSTATUS_EN 0x40
62 #define AMD756_CHAN_EN(chan) (0x01 << (1 - (chan)))
63 #define AMD756_CABLE(chan, drive) (0x00010000 << ((chan) * 2 + (drive)))
64
65 /* Data port timing controls */
66 #define AMD756_DATATIM 0x48
67 #define AMD756_DATATIM_MASK(channel) (0xffff << ((1 - (channel)) << 4))
68 #define AMD756_DATATIM_RECOV(channel, drive, x) (((x) & 0xf) << \
69 (((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
70 #define AMD756_DATATIM_PULSE(channel, drive, x) (((x) & 0xf) << \
71 (((1 - (channel)) << 4) + ((1 - (drive)) << 3) + 4))
72
73 static const int8_t amd756_pio_set[] = {0x0a, 0x0a, 0x0a, 0x02, 0x02};
74 static const int8_t amd756_pio_rec[] = {0x08, 0x08, 0x08, 0x02, 0x00};
75
76 /* Ultra-DMA/33 control */
77 #define AMD756_UDMA 0x50
78 #define AMD756_UDMA_MASK(channel) (0xffff << ((1 - (channel)) << 4))
79 #define AMD756_UDMA_TIME(channel, drive, x) (((x) & 0x7) << \
80 (((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
81 #define AMD756_UDMA_EN(channel, drive) (0x40 << \
82 (((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
83 #define AMD756_UDMA_EN_MTH(channel, drive) (0x80 << \
84 (((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
85
86 static const int8_t amd756_udma_tim[] =
87 {0x02, 0x01, 0x00, 0x04, 0x05, 0x06, 0x07};
88
89 #endif /* !_DEV_PCI_PCIIDE_AMD_REG_H_ */