channel 369 arch/i386/isa/ahc_isa.c ahc->channel = 'A';
channel 3375 dev/acpi/dsdt.c printf("dma\t%.2x %.2x\n", crs->sr_dma.channel,
channel 126 dev/acpi/dsdt.h uint8_t channel;
channel 165 dev/ata/ata_wdc.c chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive),
channel 186 dev/ata/ata_wdc.c chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive),
channel 198 dev/ata/ata_wdc.c chp->wdc->sc_dev.dv_xname, chp->channel,
channel 266 dev/ata/ata_wdc.c chp->channel, xfer->drive,
channel 287 dev/ata/ata_wdc.c chp->channel, xfer->drive);
channel 335 dev/ata/ata_wdc.c chp->wdc->sc_dev.dv_xname, chp->channel,
channel 368 dev/ata/ata_wdc.c chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive,
channel 384 dev/ata/ata_wdc.c chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive),
channel 391 dev/ata/ata_wdc.c chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive,
channel 409 dev/ata/ata_wdc.c chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive,
channel 429 dev/ata/ata_wdc.c chp->wdc->sc_dev.dv_xname, chp->channel,
channel 450 dev/ata/ata_wdc.c chp->wdc->sc_dev.dv_xname, chp->channel,
channel 512 dev/ata/ata_wdc.c chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive,
channel 675 dev/ata/ata_wdc.c chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, errstring);
channel 682 dev/ata/ata_wdc.c chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive,
channel 334 dev/atapiscsi/atapiscsi.c chp->wdc->sc_dev.dv_xname, chp->channel, as->drive), DEBUG_XFERS);
channel 359 dev/atapiscsi/atapiscsi.c chp->wdc->sc_dev.dv_xname, chp->channel, as->drive),
channel 766 dev/atapiscsi/atapiscsi.c chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive,
channel 847 dev/atapiscsi/atapiscsi.c chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive
channel 900 dev/atapiscsi/atapiscsi.c chp->channel, xfer->drive, xfer->databuf,
channel 914 dev/atapiscsi/atapiscsi.c chp->channel, xfer->drive);
channel 950 dev/atapiscsi/atapiscsi.c chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive);
channel 1136 dev/atapiscsi/atapiscsi.c (chp->wdc->dma_arg, chp->channel,
channel 1312 dev/atapiscsi/atapiscsi.c chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive,
channel 1402 dev/atapiscsi/atapiscsi.c chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive, drvp->state),
channel 1520 dev/atapiscsi/atapiscsi.c chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, errstring);
channel 1564 dev/atapiscsi/atapiscsi.c chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive,
channel 1622 dev/atapiscsi/atapiscsi.c chp->wdc->sc_dev.dv_xname, chp->channel,
channel 179 dev/eisa/ahc_eisa.c ahc->channel = 'A';
channel 102 dev/i2c/lm87.c u_int8_t cmd, data, data2, channel;
channel 138 dev/i2c/lm87.c sc->sc_addr, &cmd, sizeof cmd, &channel,
channel 139 dev/i2c/lm87.c sizeof channel, 0)) {
channel 210 dev/i2c/lm87.c if (channel & LM87_CHANNEL_AIN1) {
channel 218 dev/i2c/lm87.c if (channel & LM87_CHANNEL_AIN2) {
channel 2507 dev/ic/acx.c bj->channel = ieee80211_chan2ieee(&sc->sc_ic, node->ni_chan);
channel 2512 dev/ic/acx.c bj->channel));
channel 469 dev/ic/acxreg.h uint8_t channel;
channel 2211 dev/ic/advlib.c u_int16_t channel;
channel 2213 dev/ic/advlib.c channel = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0x0003;
channel 2214 dev/ic/advlib.c if (channel == 0x03)
channel 2216 dev/ic/advlib.c else if (channel == 0x00)
channel 2218 dev/ic/advlib.c return (channel + 4);
channel 151 dev/ic/aic79xx.c u_int scsi_id, char channel);
channel 154 dev/ic/aic79xx.c u_int scsi_id, char channel, int force);
channel 229 dev/ic/aic79xx.c char channel, int lun, u_int tag,
channel 1113 dev/ic/aic79xx.c devinfo.channel,
channel 1416 dev/ic/aic79xx.c ahd_name(ahd), devinfo.channel, devinfo.target,
channel 2302 dev/ic/aic79xx.c tinfo = ahd_fetch_transinfo(ahd, devinfo.channel,
channel 2573 dev/ic/aic79xx.c devinfo->channel,
channel 2810 dev/ic/aic79xx.c ahd_alloc_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel)
channel 2852 dev/ic/aic79xx.c ahd_free_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel, int force)
channel 3090 dev/ic/aic79xx.c tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
channel 3120 dev/ic/aic79xx.c ahd_send_async(ahd, devinfo->channel, devinfo->target,
channel 3228 dev/ic/aic79xx.c tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
channel 3244 dev/ic/aic79xx.c ahd_send_async(ahd, devinfo->channel, devinfo->target,
channel 3278 dev/ic/aic79xx.c ahd_send_async(ahd, devinfo->channel, devinfo->target,
channel 3420 dev/ic/aic79xx.c tinfo = ahd_fetch_transinfo(ahd, devinfo.channel,
channel 3539 dev/ic/aic79xx.c u_int lun, char channel, role_t role)
channel 3545 dev/ic/aic79xx.c devinfo->channel = channel;
channel 3547 dev/ic/aic79xx.c if (channel == 'B')
channel 3713 dev/ic/aic79xx.c tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
channel 3806 dev/ic/aic79xx.c ahd_name(ahd), devinfo->channel, devinfo->target,
channel 3826 dev/ic/aic79xx.c ahd_name(ahd), devinfo->channel, devinfo->target,
channel 3861 dev/ic/aic79xx.c devinfo->channel, devinfo->target, devinfo->lun,
channel 4298 dev/ic/aic79xx.c tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
channel 4369 dev/ic/aic79xx.c ahd_name(ahd), devinfo->channel,
channel 4398 dev/ic/aic79xx.c ahd_name(ahd), devinfo->channel,
channel 4440 dev/ic/aic79xx.c ahd_name(ahd), devinfo->channel,
channel 4456 dev/ic/aic79xx.c ahd_name(ahd), devinfo->channel,
channel 4469 dev/ic/aic79xx.c ahd_name(ahd), devinfo->channel,
channel 4581 dev/ic/aic79xx.c ahd_name(ahd), devinfo->channel,
channel 4586 dev/ic/aic79xx.c ahd_name(ahd), devinfo->channel,
channel 4600 dev/ic/aic79xx.c ahd_name(ahd), devinfo->channel,
channel 4647 dev/ic/aic79xx.c ahd_abort_scbs(ahd, devinfo->target, devinfo->channel,
channel 4722 dev/ic/aic79xx.c tinfo = ahd_fetch_transinfo(ahd, devinfo->channel,
channel 4739 dev/ic/aic79xx.c ahd_name(ahd), devinfo->channel,
channel 4754 dev/ic/aic79xx.c ahd_name(ahd), devinfo->channel,
channel 4771 dev/ic/aic79xx.c devinfo->channel, devinfo->target, devinfo->lun);
channel 4799 dev/ic/aic79xx.c ahd_name(ahd), devinfo->channel,
channel 4810 dev/ic/aic79xx.c devinfo->channel, devinfo->target, devinfo->lun);
channel 4816 dev/ic/aic79xx.c ahd_name(ahd), devinfo->channel, devinfo->target,
channel 4866 dev/ic/aic79xx.c ahd_name(ahd), devinfo->channel, devinfo->target,
channel 5117 dev/ic/aic79xx.c found = ahd_abort_scbs(ahd, devinfo->target, devinfo->channel,
channel 5163 dev/ic/aic79xx.c ahd_send_async(ahd, devinfo->channel, devinfo->target,
channel 5170 dev/ic/aic79xx.c message, devinfo->channel, devinfo->target, found);
channel 5275 dev/ic/aic79xx.c ahd->channel = 'A';
channel 6157 dev/ic/aic79xx.c ahd->channel, ahd->our_id, ahd->bus_description,
channel 7113 dev/ic/aic79xx.c char channel, int lun, u_int tag, role_t role)
channel 7120 dev/ic/aic79xx.c match = ((chan == channel) || (channel == ALL_CHANNELS));
channel 7151 dev/ic/aic79xx.c char channel;
channel 7156 dev/ic/aic79xx.c channel = SCB_GET_CHANNEL(ahd, scb);
channel 7158 dev/ic/aic79xx.c ahd_search_qinfifo(ahd, target, channel, lun,
channel 7266 dev/ic/aic79xx.c ahd_search_qinfifo(struct ahd_softc *ahd, int target, char channel,
channel 7329 dev/ic/aic79xx.c if (ahd_match_scb(ahd, scb, target, channel, lun, tag, role)) {
channel 7402 dev/ic/aic79xx.c if (ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD,
channel 7414 dev/ic/aic79xx.c found += ahd_search_scb_list(ahd, target, channel,
channel 7423 dev/ic/aic79xx.c && ahd_match_scb(ahd, mk_msg_scb, target, channel,
channel 7467 dev/ic/aic79xx.c && ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD,
channel 7496 dev/ic/aic79xx.c ahd_search_scb_list(struct ahd_softc *ahd, int target, char channel,
channel 7529 dev/ic/aic79xx.c if (ahd_match_scb(ahd, scb, target, channel,
channel 7652 dev/ic/aic79xx.c ahd_abort_scbs(struct ahd_softc *ahd, int target, char channel,
channel 7668 dev/ic/aic79xx.c found = ahd_search_qinfifo(ahd, target, channel, lun, SCB_LIST_NULL,
channel 7678 dev/ic/aic79xx.c if (channel == 'B')
channel 7703 dev/ic/aic79xx.c || ahd_match_scb(ahd, scbp, target, channel,
channel 7727 dev/ic/aic79xx.c if (ahd_match_scb(ahd, scbp, target, channel, lun, tag, role)) {
channel 7742 dev/ic/aic79xx.c ahd_platform_abort_scbs(ahd, target, channel, lun, tag, role, status);
channel 7778 dev/ic/aic79xx.c ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset)
channel 7794 dev/ic/aic79xx.c channel, ROLE_UNKNOWN);
channel 7853 dev/ic/aic79xx.c found = ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, channel,
channel 7914 dev/ic/aic79xx.c ahd_send_async(ahd, devinfo.channel, CAM_TARGET_WILDCARD,
channel 8164 dev/ic/aic79xx.c devinfo.channel,
channel 9143 dev/ic/aic79xx.c char channel;
channel 9175 dev/ic/aic79xx.c channel = SCB_GET_CHANNEL(ahd, scb);
channel 9176 dev/ic/aic79xx.c found = ahd_reset_channel(ahd, channel, /*Initiate Reset*/TRUE);
channel 9179 dev/ic/aic79xx.c ahd_name(ahd), channel, found);
channel 9501 dev/ic/aic79xx.c char channel;
channel 9571 dev/ic/aic79xx.c channel = SCSI_CHANNEL(ahd, sim);
channel 9573 dev/ic/aic79xx.c if (channel == 'B')
channel 9603 dev/ic/aic79xx.c tstate = ahd_alloc_tstate(ahd, target, channel);
channel 9647 dev/ic/aic79xx.c char channel;
channel 9649 dev/ic/aic79xx.c channel = SCSI_CHANNEL(ahd, sim);
channel 9666 dev/ic/aic79xx.c swap = cur_channel != channel;
channel 9752 dev/ic/aic79xx.c ahd_free_tstate(ahd, target, channel,
channel 10402 dev/ic/aic79xx.c ahd_fetch_transinfo(struct ahd_softc *ahd, char channel, u_int our_id,
channel 10411 dev/ic/aic79xx.c if (channel == 'B')
channel 149 dev/ic/aic79xx.h #define BUILD_TCL_RAW(target, channel, lun) \
channel 1051 dev/ic/aic79xx.h struct ahd_suspend_channel_state channel[2];
channel 1227 dev/ic/aic79xx.h char channel;
channel 1357 dev/ic/aic79xx.h char channel;
channel 1398 dev/ic/aic79xx.h int target, char channel, int lun,
channel 1462 dev/ic/aic79xx.h char channel, int lun, u_int tag,
channel 1466 dev/ic/aic79xx.h char channel, int lun, u_int tag,
channel 1470 dev/ic/aic79xx.h int ahd_reset_channel(struct ahd_softc *ahd, char channel,
channel 1473 dev/ic/aic79xx.h char channel, int lun, u_int tag,
channel 1489 dev/ic/aic79xx.h u_int lun, char channel,
channel 598 dev/ic/aic79xx_openbsd.c ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
channel 237 dev/ic/aic79xx_openbsd.h #define ahd_platform_abort_scbs(ahd, target, channel, lun, tag, role, status)
channel 156 dev/ic/aic7xxx.c u_int scsi_id, char channel);
channel 159 dev/ic/aic7xxx.c u_int scsi_id, char channel, int force);
channel 553 dev/ic/aic7xxx.c devinfo.channel,
channel 661 dev/ic/aic7xxx.c ahc_name(ahc), devinfo.channel, devinfo.target);
channel 696 dev/ic/aic7xxx.c ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte);
channel 717 dev/ic/aic7xxx.c ahc_name(ahc), devinfo.channel, devinfo.target,
channel 728 dev/ic/aic7xxx.c ahc_name(ahc), devinfo.channel, devinfo.target,
channel 862 dev/ic/aic7xxx.c ahc_reset_channel(ahc, devinfo.channel,
channel 952 dev/ic/aic7xxx.c ahc_name(ahc), devinfo.channel, devinfo.target,
channel 1283 dev/ic/aic7xxx.c char channel;
channel 1315 dev/ic/aic7xxx.c channel = SCSIID_CHANNEL(ahc, saved_scsiid);
channel 1317 dev/ic/aic7xxx.c target, saved_lun, channel, ROLE_INITIATOR);
channel 1333 dev/ic/aic7xxx.c ahc_abort_scbs(ahc, target, channel,
channel 1348 dev/ic/aic7xxx.c && ahc_match_scb(ahc, scb, target, channel,
channel 1359 dev/ic/aic7xxx.c channel,
channel 1376 dev/ic/aic7xxx.c devinfo.channel,
channel 1424 dev/ic/aic7xxx.c ahc_abort_scbs(ahc, target, channel,
channel 1474 dev/ic/aic7xxx.c devinfo->channel,
channel 1632 dev/ic/aic7xxx.c ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel)
channel 1639 dev/ic/aic7xxx.c if (channel == 'B') {
channel 1680 dev/ic/aic7xxx.c ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force)
channel 1688 dev/ic/aic7xxx.c if (((channel == 'B' && scsi_id == ahc->our_id_b)
channel 1689 dev/ic/aic7xxx.c || (channel == 'A' && scsi_id == ahc->our_id))
channel 1693 dev/ic/aic7xxx.c if (channel == 'B')
channel 1986 dev/ic/aic7xxx.c tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
channel 2060 dev/ic/aic7xxx.c ahc_send_async(ahc, devinfo->channel, devinfo->target,
channel 2104 dev/ic/aic7xxx.c tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
channel 2130 dev/ic/aic7xxx.c ahc_send_async(ahc, devinfo->channel, devinfo->target,
channel 2153 dev/ic/aic7xxx.c ahc_send_async(ahc, devinfo->channel, devinfo->target,
channel 2183 dev/ic/aic7xxx.c tinfo = ahc_fetch_transinfo(ahc, devinfo.channel,
channel 2292 dev/ic/aic7xxx.c u_int lun, char channel, role_t role)
channel 2298 dev/ic/aic7xxx.c devinfo->channel = channel;
channel 2300 dev/ic/aic7xxx.c if (channel == 'B')
channel 2308 dev/ic/aic7xxx.c printf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel,
channel 2450 dev/ic/aic7xxx.c tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
channel 2544 dev/ic/aic7xxx.c ahc_name(ahc), devinfo->channel, devinfo->target,
channel 2564 dev/ic/aic7xxx.c ahc_name(ahc), devinfo->channel, devinfo->target,
channel 2592 dev/ic/aic7xxx.c devinfo->channel, devinfo->target, devinfo->lun,
channel 3077 dev/ic/aic7xxx.c tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
channel 3152 dev/ic/aic7xxx.c ahc_name(ahc), devinfo->channel,
channel 3182 dev/ic/aic7xxx.c ahc_name(ahc), devinfo->channel,
channel 3224 dev/ic/aic7xxx.c ahc_name(ahc), devinfo->channel,
channel 3240 dev/ic/aic7xxx.c ahc_name(ahc), devinfo->channel,
channel 3253 dev/ic/aic7xxx.c ahc_name(ahc), devinfo->channel,
channel 3371 dev/ic/aic7xxx.c ahc_name(ahc), devinfo->channel,
channel 3376 dev/ic/aic7xxx.c ahc_name(ahc), devinfo->channel,
channel 3390 dev/ic/aic7xxx.c ahc_name(ahc), devinfo->channel,
channel 3437 dev/ic/aic7xxx.c ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
channel 3504 dev/ic/aic7xxx.c tinfo = ahc_fetch_transinfo(ahc, devinfo->channel,
channel 3518 dev/ic/aic7xxx.c ahc_name(ahc), devinfo->channel,
channel 3534 dev/ic/aic7xxx.c devinfo->channel, devinfo->target, devinfo->lun);
channel 3562 dev/ic/aic7xxx.c ahc_name(ahc), devinfo->channel,
channel 3573 dev/ic/aic7xxx.c devinfo->channel, devinfo->target, devinfo->lun);
channel 3579 dev/ic/aic7xxx.c ahc_name(ahc), devinfo->channel, devinfo->target,
channel 3628 dev/ic/aic7xxx.c ahc_name(ahc), devinfo->channel, devinfo->target,
channel 3812 dev/ic/aic7xxx.c found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
channel 3847 dev/ic/aic7xxx.c ahc_send_async(ahc, devinfo->channel, devinfo->target,
channel 3853 dev/ic/aic7xxx.c message, devinfo->channel, devinfo->target, found);
channel 4490 dev/ic/aic7xxx.c speed, type, ahc->channel, ahc->our_id);
channel 4884 dev/ic/aic7xxx.c char channel;
channel 4886 dev/ic/aic7xxx.c channel = 'A';
channel 4890 dev/ic/aic7xxx.c channel = 'B';
channel 4894 dev/ic/aic7xxx.c tinfo = ahc_fetch_transinfo(ahc, channel, our_id,
channel 5068 dev/ic/aic7xxx.c char channel, int lun, u_int tag, role_t role)
channel 5080 dev/ic/aic7xxx.c match = ((chan == channel) || (channel == ALL_CHANNELS));
channel 5111 dev/ic/aic7xxx.c char channel;
channel 5116 dev/ic/aic7xxx.c channel = SCB_GET_CHANNEL(ahc, scb);
channel 5118 dev/ic/aic7xxx.c ahc_search_qinfifo(ahc, target, channel, lun,
channel 5183 dev/ic/aic7xxx.c ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel,
channel 5232 dev/ic/aic7xxx.c if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) {
channel 5343 dev/ic/aic7xxx.c if (ahc_match_scb(ahc, scb, target, channel,
channel 5383 dev/ic/aic7xxx.c channel, lun, status, action);
channel 5392 dev/ic/aic7xxx.c int target, char channel, int lun, uint32_t status,
channel 5416 dev/ic/aic7xxx.c if (channel == 'B')
channel 5447 dev/ic/aic7xxx.c if (ahc_match_scb(ahc, scb, target, channel, lun,
channel 5487 dev/ic/aic7xxx.c ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel,
channel 5527 dev/ic/aic7xxx.c if (ahc_match_scb(ahc, scbp, target, channel, lun,
channel 5650 dev/ic/aic7xxx.c ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel,
channel 5672 dev/ic/aic7xxx.c found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL,
channel 5682 dev/ic/aic7xxx.c if (channel == 'B')
channel 5714 dev/ic/aic7xxx.c || ahc_match_scb(ahc, scbp, target, channel,
channel 5727 dev/ic/aic7xxx.c ahc_search_disc_list(ahc, target, channel, lun, tag,
channel 5747 dev/ic/aic7xxx.c && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)))
channel 5761 dev/ic/aic7xxx.c if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) {
channel 5776 dev/ic/aic7xxx.c ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status);
channel 5801 dev/ic/aic7xxx.c ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset)
channel 5818 dev/ic/aic7xxx.c channel, ROLE_UNKNOWN);
channel 5855 dev/ic/aic7xxx.c if (cur_channel != channel) {
channel 5902 dev/ic/aic7xxx.c found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel,
channel 5934 dev/ic/aic7xxx.c ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD,
channel 5949 dev/ic/aic7xxx.c channel, ROLE_UNKNOWN);
channel 6726 dev/ic/aic7xxx.c char channel;
channel 6840 dev/ic/aic7xxx.c channel = SIM_CHANNEL(ahc, sim);
channel 6842 dev/ic/aic7xxx.c if (channel == 'B')
channel 6872 dev/ic/aic7xxx.c tstate = ahc_alloc_tstate(ahc, target, channel);
channel 6920 dev/ic/aic7xxx.c char channel;
channel 6922 dev/ic/aic7xxx.c channel = SIM_CHANNEL(ahc, sim);
channel 6939 dev/ic/aic7xxx.c swap = cur_channel != channel;
channel 6940 dev/ic/aic7xxx.c if (channel == 'A')
channel 7028 dev/ic/aic7xxx.c ahc_free_tstate(ahc, target, channel,
channel 249 dev/ic/aic7xxx_inline.h char channel, u_int our_id,
channel 296 dev/ic/aic7xxx_inline.h ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id,
channel 637 dev/ic/aic7xxx_openbsd.c char channel;
channel 652 dev/ic/aic7xxx_openbsd.c channel = SCB_GET_CHANNEL(ahc, scb);
channel 663 dev/ic/aic7xxx_openbsd.c found = ahc_reset_channel(ahc, channel, /*Initiate Reset*/TRUE);
channel 666 dev/ic/aic7xxx_openbsd.c ahc_name(ahc), channel, found);
channel 681 dev/ic/aic7xxx_openbsd.c ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
channel 725 dev/ic/aic7xxx_openbsd.c ahc_send_async(struct ahc_softc *ahc, char channel, u_int target, u_int lun,
channel 746 dev/ic/aic7xxx_openbsd.c tinfo = ahc_fetch_transinfo(ahc, devinfo.channel,
channel 310 dev/ic/aic7xxx_openbsd.h char channel, int lun, u_int tag,
channel 140 dev/ic/aic7xxx_seeprom.c start_addr = 32 * (ahc->channel - 'A');
channel 709 dev/ic/aic7xxx_seeprom.c if (ahc->channel == 'B')
channel 743 dev/ic/aic7xxx_seeprom.c if (ahc->channel == 'B')
channel 1056 dev/ic/aic7xxxvar.h char channel;
channel 1165 dev/ic/aic7xxxvar.h char channel;
channel 1220 dev/ic/aic7xxxvar.h int target, char channel, int lun,
channel 1276 dev/ic/aic7xxxvar.h u_int lun, char channel,
channel 1281 dev/ic/ami.c u_int8_t channel = rsc->sc_channel, target = link->target;
channel 1327 dev/ic/ami.c ccb->ccb_pt->apt_channel = channel;
channel 367 dev/ic/ar5210.c ar5k_ar5210_reset(struct ath_hal *hal, HAL_OPMODE op_mode, HAL_CHANNEL *channel,
channel 376 dev/ic/ar5210.c channel->c_channel_flags & IEEE80211_CHAN_T ?
channel 418 dev/ic/ar5210.c if (ar5k_channel(hal, channel) == AH_FALSE)
channel 427 dev/ic/ar5210.c ar5k_ar5210_do_calibrate(hal, channel);
channel 428 dev/ic/ar5210.c if (ar5k_ar5210_noise_floor(hal, channel) == AH_FALSE)
channel 522 dev/ic/ar5210.c ar5k_ar5210_calibrate(struct ath_hal *hal, HAL_CHANNEL *channel)
channel 552 dev/ic/ar5210.c ret = ar5k_channel(hal, channel);
channel 599 dev/ic/ar5210.c ret = ar5k_ar5210_do_calibrate(hal, channel);
channel 609 dev/ic/ar5210.c if (ar5k_ar5210_noise_floor(hal, channel) == AH_FALSE)
channel 626 dev/ic/ar5210.c ar5k_ar5210_do_calibrate(struct ath_hal *hal, HAL_CHANNEL *channel)
channel 637 dev/ic/ar5210.c channel->c_channel);
channel 645 dev/ic/ar5210.c ar5k_ar5210_noise_floor(struct ath_hal *hal, HAL_CHANNEL *channel)
channel 659 dev/ic/ar5210.c channel->c_channel);
channel 676 dev/ic/ar5210.c channel->c_channel);
channel 417 dev/ic/ar5211.c ar5k_ar5211_reset(struct ath_hal *hal, HAL_OPMODE op_mode, HAL_CHANNEL *channel,
channel 441 dev/ic/ar5211.c if (ar5k_ar5211_nic_wakeup(hal, channel->c_channel_flags) == AH_FALSE)
channel 449 dev/ic/ar5211.c switch (channel->c_channel_flags & CHANNEL_MODES) {
channel 472 dev/ic/ar5211.c AR5K_PRINTF("invalid channel: %d\n", channel->c_channel);
channel 482 dev/ic/ar5211.c ar5k_ar5211_rfregs(hal, channel, freq, ee_mode);
channel 520 dev/ic/ar5211.c if (channel->c_channel_flags & IEEE80211_CHAN_B)
channel 603 dev/ic/ar5211.c if (ar5k_channel(hal, channel) == AH_FALSE)
channel 613 dev/ic/ar5211.c data = (channel->c_channel_flags & IEEE80211_CHAN_CCK) ?
channel 625 dev/ic/ar5211.c if (channel->c_channel_flags & IEEE80211_CHAN_B) {
channel 720 dev/ic/ar5211.c ar5k_ar5211_calibrate(struct ath_hal *hal, HAL_CHANNEL *channel)
channel 884 dev/ic/ar5211.c struct ieee80211_channel *channel = (struct ieee80211_channel*)
channel 898 dev/ic/ar5211.c if (IEEE80211_IS_CHAN_B(channel)) {
channel 2519 dev/ic/ar5211.c ar5k_ar5211_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int freq,
channel 2543 dev/ic/ar5211.c obdb = channel->c_channel >= 5725 ? 3 :
channel 2544 dev/ic/ar5211.c (channel->c_channel >= 5500 ? 2 :
channel 2545 dev/ic/ar5211.c (channel->c_channel >= 5260 ? 1 :
channel 2546 dev/ic/ar5211.c (channel->c_channel > 4000 ? 0 : -1)));
channel 434 dev/ic/ar5212.c ar5k_ar5212_reset(struct ath_hal *hal, HAL_OPMODE op_mode, HAL_CHANNEL *channel,
channel 462 dev/ic/ar5212.c if (ar5k_ar5212_nic_wakeup(hal, channel->c_channel_flags) == AH_FALSE)
channel 479 dev/ic/ar5212.c switch (channel->c_channel_flags & CHANNEL_MODES) {
channel 512 dev/ic/ar5212.c AR5K_PRINTF("invalid channel: %d\n", channel->c_channel);
channel 570 dev/ic/ar5212.c channel->c_channel_flags & IEEE80211_CHAN_TURBO ?
channel 579 dev/ic/ar5212.c if ((channel->c_channel_flags & IEEE80211_CHAN_TURBO) == 0) {
channel 600 dev/ic/ar5212.c if (channel->c_channel_flags & IEEE80211_CHAN_OFDM)
channel 610 dev/ic/ar5212.c if (ar5k_ar5212_txpower(hal, channel,
channel 617 dev/ic/ar5212.c if (ar5k_rfregs(hal, channel, mode) == AH_FALSE)
channel 625 dev/ic/ar5212.c if (channel->c_channel_flags & IEEE80211_CHAN_OFDM) {
channel 629 dev/ic/ar5212.c clock = channel->c_channel_flags & IEEE80211_CHAN_T ? 80 : 40;
channel 630 dev/ic/ar5212.c coef_scaled = ((5 * (clock << 24)) / 2) / channel->c_channel;
channel 651 dev/ic/ar5212.c if (channel->c_channel_flags & IEEE80211_CHAN_B)
channel 741 dev/ic/ar5212.c if (ar5k_channel(hal, channel) == AH_FALSE)
channel 751 dev/ic/ar5212.c data = (channel->c_channel_flags & IEEE80211_CHAN_CCK) ?
channel 764 dev/ic/ar5212.c if ((channel->c_channel_flags & IEEE80211_CHAN_B) == 0) {
channel 868 dev/ic/ar5212.c ar5k_ar5212_calibrate(struct ath_hal *hal, HAL_CHANNEL *channel)
channel 903 dev/ic/ar5212.c if (channel->c_channel_flags & IEEE80211_CHAN_5GHZ) {
channel 1040 dev/ic/ar5212.c struct ieee80211_channel *channel = (struct ieee80211_channel*)
channel 1057 dev/ic/ar5212.c if (IEEE80211_IS_CHAN_XR(channel)) {
channel 1061 dev/ic/ar5212.c } else if (IEEE80211_IS_CHAN_B(channel)) {
channel 2894 dev/ic/ar5212.c ar5k_ar5212_txpower(struct ath_hal *hal, HAL_CHANNEL *channel, u_int txpower)
channel 2909 dev/ic/ar5212.c ar5k_txpower_table(hal, channel, txpower);
channel 2953 dev/ic/ar5212.c HAL_CHANNEL *channel = &hal->ah_current_channel;
channel 2956 dev/ic/ar5212.c return (ar5k_ar5212_txpower(hal, channel, power));
channel 475 dev/ic/ar5xxx.c all_channels[c++].channel = ar5k_5ghz_channels[i].rc_channel;
channel 511 dev/ic/ar5xxx.c all_channels[c++].channel = ar5k_2ghz_channels[i].rc_channel;
channel 559 dev/ic/ar5xxx.c if (hal->ah_radar.r_last_channel.channel ==
channel 560 dev/ic/ar5xxx.c hal->ah_current_channel.channel &&
channel 564 dev/ic/ar5xxx.c hal->ah_radar.r_last_channel.channel =
channel 565 dev/ic/ar5xxx.c hal->ah_current_channel.channel;
channel 571 dev/ic/ar5xxx.c hal->ah_radar.r_last_alert, hal->ah_current_channel.channel);
channel 1114 dev/ic/ar5xxx.c ar5k_channel(struct ath_hal *hal, HAL_CHANNEL *channel)
channel 1122 dev/ic/ar5xxx.c if ((channel->channel < hal->ah_capabilities.cap_range.range_2ghz_min ||
channel 1123 dev/ic/ar5xxx.c channel->channel > hal->ah_capabilities.cap_range.range_2ghz_max) &&
channel 1124 dev/ic/ar5xxx.c (channel->channel < hal->ah_capabilities.cap_range.range_5ghz_min ||
channel 1125 dev/ic/ar5xxx.c channel->channel > hal->ah_capabilities.cap_range.range_5ghz_max)) {
channel 1127 dev/ic/ar5xxx.c channel->channel);
channel 1135 dev/ic/ar5xxx.c ret = ar5k_ar5110_channel(hal, channel);
channel 1137 dev/ic/ar5xxx.c ret = ar5k_ar5111_channel(hal, channel);
channel 1139 dev/ic/ar5xxx.c ret = ar5k_ar5112_channel(hal, channel);
channel 1144 dev/ic/ar5xxx.c hal->ah_current_channel.c_channel = channel->c_channel;
channel 1145 dev/ic/ar5xxx.c hal->ah_current_channel.c_channel_flags = channel->c_channel_flags;
channel 1146 dev/ic/ar5xxx.c hal->ah_turbo = channel->c_channel_flags == CHANNEL_T ?
channel 1153 dev/ic/ar5xxx.c ar5k_ar5110_chan2athchan(HAL_CHANNEL *channel)
channel 1163 dev/ic/ar5xxx.c athchan = (ar5k_bitswap((ieee80211_mhz2ieee(channel->c_channel,
channel 1164 dev/ic/ar5xxx.c channel->c_channel_flags) - 24) / 2, 5) << 1) |
channel 1171 dev/ic/ar5xxx.c ar5k_ar5110_channel(struct ath_hal *hal, HAL_CHANNEL *channel)
channel 1178 dev/ic/ar5xxx.c data = ar5k_ar5110_chan2athchan(channel);
channel 1189 dev/ic/ar5xxx.c int channel;
channel 1192 dev/ic/ar5xxx.c channel = (int)ieee;
channel 1197 dev/ic/ar5xxx.c if (channel <= 13) {
channel 1198 dev/ic/ar5xxx.c athchan->a2_athchan = 115 + channel;
channel 1200 dev/ic/ar5xxx.c } else if (channel == 14) {
channel 1203 dev/ic/ar5xxx.c } else if (channel >= 15 && channel <= 26) {
channel 1204 dev/ic/ar5xxx.c athchan->a2_athchan = ((channel - 14) * 4) + 132;
channel 1213 dev/ic/ar5xxx.c ar5k_ar5111_channel(struct ath_hal *hal, HAL_CHANNEL *channel)
channel 1223 dev/ic/ar5xxx.c ath_channel = ieee_channel = ieee80211_mhz2ieee(channel->c_channel,
channel 1224 dev/ic/ar5xxx.c channel->c_channel_flags);
channel 1226 dev/ic/ar5xxx.c if (channel->c_channel_flags & IEEE80211_CHAN_2GHZ) {
channel 1254 dev/ic/ar5xxx.c ar5k_ar5112_channel(struct ath_hal *hal, HAL_CHANNEL *channel)
channel 1260 dev/ic/ar5xxx.c c = channel->c_channel;
channel 1481 dev/ic/ar5xxx.c ar5k_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode)
channel 1507 dev/ic/ar5xxx.c ret = (func)(hal, channel, mode);
channel 1516 dev/ic/ar5xxx.c ar5k_ar5111_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode)
channel 1544 dev/ic/ar5xxx.c if (channel->c_channel_flags & IEEE80211_CHAN_2GHZ) {
channel 1545 dev/ic/ar5xxx.c if (channel->c_channel_flags & IEEE80211_CHAN_B)
channel 1563 dev/ic/ar5xxx.c obdb = channel->c_channel >= 5725 ? 3 :
channel 1564 dev/ic/ar5xxx.c (channel->c_channel >= 5500 ? 2 :
channel 1565 dev/ic/ar5xxx.c (channel->c_channel >= 5260 ? 1 :
channel 1566 dev/ic/ar5xxx.c (channel->c_channel > 4000 ? 0 : -1)));
channel 1611 dev/ic/ar5xxx.c ar5k_ar5112_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode)
channel 1648 dev/ic/ar5xxx.c if (channel->c_channel_flags & IEEE80211_CHAN_2GHZ) {
channel 1649 dev/ic/ar5xxx.c if (channel->c_channel_flags & IEEE80211_CHAN_B)
channel 1665 dev/ic/ar5xxx.c obdb = channel->c_channel >= 5725 ? 3 :
channel 1666 dev/ic/ar5xxx.c (channel->c_channel >= 5500 ? 2 :
channel 1667 dev/ic/ar5xxx.c (channel->c_channel >= 5260 ? 1 :
channel 1668 dev/ic/ar5xxx.c (channel->c_channel > 4000 ? 0 : -1)));
channel 1735 dev/ic/ar5xxx.c ar5k_txpower_table(struct ath_hal *hal, HAL_CHANNEL *channel, int16_t max_power)
channel 445 dev/ic/ar5xxx.h u_int16_t channel; /* MHz */
channel 448 dev/ic/ar5xxx.h #define c_channel channel
channel 735 dev/ic/ath.c hchan.channel = ic->ic_ibss_chan->ic_freq;
channel 866 dev/ic/ath.c hchan.channel = c->ic_freq;
channel 2730 dev/ic/ath.c hchan.channel = chan->ic_freq;
channel 2825 dev/ic/ath.c hchan.channel = c->ic_freq;
channel 3053 dev/ic/ath.c ix = ieee80211_mhz2ieee(c->channel, c->channelFlags);
channel 3056 dev/ic/ath.c ifp->if_xname, ix, c->channel, c->channelFlags);
channel 3061 dev/ic/ath.c sc->sc_dev.dv_xname, i, nchan, c->channel, c->channelFlags,
channel 3065 dev/ic/ath.c ic->ic_channels[ix].ic_freq = c->channel;
channel 1096 dev/ic/dpt.c cp->cp_channel = sc_link->scsipi_scsi.channel;
channel 1111 dev/ic/dpt.c cp->cp_interpret = (sc->sc_hbaid[sc_link->scsipi_scsi.channel] ==
channel 68 dev/ic/gdtvar.h u_int32_t channel; /* device */
channel 352 dev/ic/if_wi_ieee.h int channel; /* Channel */
channel 1039 dev/ic/isp.c isp_scsi_channel_init(struct ispsoftc *isp, int channel)
channel 1046 dev/ic/isp.c sdp += channel;
channel 1052 dev/ic/isp.c mbs.param[1] = (channel << 7) | sdp->isp_initiator_id;
channel 1058 dev/ic/isp.c sdp->isp_initiator_id, channel);
channel 1095 dev/ic/isp.c mbs.param[1] = (channel << 15) | (tgt << 8);
channel 1106 dev/ic/isp.c channel, tgt, mbs.param[2], mbs.param[3] >> 8,
channel 1112 dev/ic/isp.c mbs.param[1] = (tgt << 8) | (channel << 15);
channel 1135 dev/ic/isp.c mbs.param[1] = (channel << 15) | (tgt << 8) | lun;
channel 1146 dev/ic/isp.c isp->isp_sendmarker |= (1 << channel);
channel 1147 dev/ic/isp.c isp->isp_update |= (1 << channel);
channel 5591 dev/ic/isp.c isp_setdfltparm(struct ispsoftc *isp, int channel)
channel 5601 dev/ic/isp.c fcp += channel;
channel 5679 dev/ic/isp.c sdp += channel;
channel 5741 dev/ic/isp.c (mbs.param[1+channel] >> 4) & 0x1;
channel 5743 dev/ic/isp.c (mbs.param[1+channel] >> 5) & 0x1;
channel 5802 dev/ic/isp.c channel, tgt, sdp->isp_devparam[tgt].nvrm_flags,
channel 86 dev/ic/malo.c uint8_t channel;
channel 208 dev/ic/malo.c uint8_t channel;
channel 303 dev/ic/malo.c int malo_cmd_set_channel(struct malo_softc *sc, uint8_t channel);
channel 1685 dev/ic/malo.c desc->channel, letoh16(desc->len), desc->reserved1,
channel 2190 dev/ic/malo.c malo_cmd_set_channel(struct malo_softc *sc, uint8_t channel)
channel 2203 dev/ic/malo.c body->channel = channel;
channel 2575 dev/ic/pgt.c uint32_t mode, bsstype, config, profile, channel, slot, preamble;
channel 2712 dev/ic/pgt.c channel = 0;
channel 2714 dev/ic/pgt.c channel = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan);
channel 2716 dev/ic/pgt.c channel = ieee80211_chan2ieee(ic, ic->ic_des_chan);
channel 2744 dev/ic/pgt.c if (channel != 0 && channel != IEEE80211_CHAN_ANY)
channel 2745 dev/ic/pgt.c SETOID(PGT_OID_CHANNEL, &channel, sizeof(channel));
channel 2872 dev/ic/pgt.c uint32_t channel, noise, ls;
channel 2936 dev/ic/pgt.c if (pgt_oid_get(sc, PGT_OID_CHANNEL, &channel,
channel 2937 dev/ic/pgt.c sizeof(channel)) != 0)
channel 2939 dev/ic/pgt.c channel = min(letoh32(channel), IEEE80211_CHAN_MAX);
channel 2940 dev/ic/pgt.c ic->ic_bss->ni_chan = &ic->ic_channels[channel];
channel 653 dev/ic/rln.c syncp->channel,
channel 657 dev/ic/rln.c sc->sc_param.rp_channel = syncp->channel;
channel 976 dev/ic/rln.c init.channel = sc->sc_param.rp_channel;
channel 34 dev/ic/rlncmd.h u_char channel : 4; /* lower bits */
channel 81 dev/ic/rlncmd.h u_char channel : 4; /* lower bits */
channel 4642 dev/ic/rtw.c u_int channel = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan);
channel 4646 dev/ic/rtw.c rtw_rf_macwrite(sc, 0x0b, channel - 1);
channel 511 dev/ic/wdc.c chp->channel, drive), DEBUG_PROBE);
channel 520 dev/ic/wdc.c chp->channel, drive), DEBUG_PROBE);
channel 529 dev/ic/wdc.c chp->channel, drive), DEBUG_PROBE);
channel 570 dev/ic/wdc.c chp->channel, drive, chp->ch_status),
channel 579 dev/ic/wdc.c chp->channel, drive, chp->ch_status),
channel 587 dev/ic/wdc.c chp->channel, drive, time_to_done), DEBUG_PROBE);
channel 601 dev/ic/wdc.c chp->channel, drive), DEBUG_PROBE);
channel 662 dev/ic/wdc.c chp->channel, st0, WDCS_BITS, st1, WDCS_BITS),
channel 678 dev/ic/wdc.c chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel,
channel 703 dev/ic/wdc.c chp->channel, drive, st0, WDCS_BITS, sc, sn, cl, ch),
channel 860 dev/ic/wdc.c chp->channel, i), DEBUG_PROBE);
channel 868 dev/ic/wdc.c channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff;
channel 888 dev/ic/wdc.c aa_link.aa_channel = chp->channel;
channel 947 dev/ic/wdc.c chp->channel, xfer->drive), DEBUG_XFERS);
channel 1003 dev/ic/wdc.c (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel,
channel 1025 dev/ic/wdc.c chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive),
channel 1050 dev/ic/wdc.c chp->wdc->sc_dev.dv_xname, chp->channel);
channel 1119 dev/ic/wdc.c chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel,
channel 1139 dev/ic/wdc.c :"none", chp->channel), DEBUG_STATUS);
channel 1179 dev/ic/wdc.c chp->wdc->sc_dev.dv_xname, chp->channel,
channel 1183 dev/ic/wdc.c chp->wdc->sc_dev.dv_xname, chp->channel,
channel 1204 dev/ic/wdc.c chp->channel, xfer->drive, 0);
channel 1211 dev/ic/wdc.c chp->channel, xfer->drive, 1);
channel 1243 dev/ic/wdc.c chp->channel, xfer->drive, 1);
channel 1605 dev/ic/wdc.c chp->wdc->sc_dev.dv_xname, chp->channel, drive);
channel 1689 dev/ic/wdc.c chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive),
channel 1744 dev/ic/wdc.c chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive),
channel 1821 dev/ic/wdc.c chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR);
channel 1853 dev/ic/wdc.c chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive,
channel 1905 dev/ic/wdc.c chp->channel, drive, command, cylin, head, sector, count, precomp),
channel 1938 dev/ic/wdc.c chp->channel, drive, command, blkno, count),
channel 1971 dev/ic/wdc.c chp->wdc->sc_dev.dv_xname, chp->channel, drive, command),
channel 1988 dev/ic/wdc.c xfer, xfer->c_flags, chp->channel, xfer->drive), DEBUG_XFERS);
channel 2067 dev/ic/wdc.c printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel,
channel 2073 dev/ic/wdc.c chp->channel, xfer->drive, msg);
channel 58 dev/ic/wdcvar.h int channel;
channel 106 dev/ic/z8530sc.h int channel; /* two serial channels per zsc */
channel 196 dev/ic/z8530tty.c if (cf->cf_loc[0] == args->channel)
channel 218 dev/ic/z8530tty.c int channel, tty_unit;
channel 223 dev/ic/z8530tty.c channel = args->channel;
channel 224 dev/ic/z8530tty.c cs = &zsc->zsc_cs[channel];
channel 284 dev/ic/z8530tty.c reset = (channel == 0) ?
channel 500 dev/isa/gus.c dmarecords[dmarecord_index].channel = 1;
channel 594 dev/isa/gus.c dmarecords[dmarecord_index].channel = 0;
channel 301 dev/isa/gusvar.h u_char channel;
channel 172 dev/isa/wdc_isa.c sc->wdc_channel.channel = 0;
channel 198 dev/isa/wdc_isa.c wdc_isa_dma_init(void *v, int channel, int drive, void *databuf, size_t datalen,
channel 211 dev/isa/wdc_isa.c wdc_isa_dma_start(void *v, int channel, int drive)
channel 217 dev/isa/wdc_isa.c wdc_isa_dma_finish(void *v, int channel, int drive, int force)
channel 143 dev/isa/wdc_isapnp.c sc->wdc_channel.channel = 0;
channel 314 dev/isa/wds.c sc->sc_link.channel = SCSI_CHANNEL_ONLY_ONE;
channel 736 dev/pci/ahc_pci.c ahc->channel = 'A';
channel 1453 dev/pci/ahc_pci.c ahc->channel = 'A';
channel 1469 dev/pci/ahc_pci.c ahc->channel = 'A';
channel 1496 dev/pci/ahc_pci.c ahc->channel = 'A';
channel 1542 dev/pci/ahc_pci.c ahc->channel = 'A';
channel 1591 dev/pci/ahc_pci.c ahc->channel = 'A';
channel 1606 dev/pci/ahc_pci.c ahc->channel = 'A';
channel 1620 dev/pci/ahc_pci.c ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A';
channel 1672 dev/pci/ahc_pci.c ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A';
channel 1684 dev/pci/ahc_pci.c ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A';
channel 1718 dev/pci/ahc_pci.c ahc->channel = 'A';
channel 1721 dev/pci/ahc_pci.c ahc->channel = 'B';
channel 1727 dev/pci/ahc_pci.c ahc->channel = 'A';
channel 1738 dev/pci/ahc_pci.c ahc->channel = 'A';
channel 1741 dev/pci/ahc_pci.c ahc->channel = 'B';
channel 1744 dev/pci/ahc_pci.c ahc->channel = 'C';
channel 1750 dev/pci/ahc_pci.c ahc->channel = 'A';
channel 1763 dev/pci/ahc_pci.c ahc->channel = 'A';
channel 1766 dev/pci/ahc_pci.c ahc->channel = 'B';
channel 1769 dev/pci/ahc_pci.c ahc->channel = 'C';
channel 1772 dev/pci/ahc_pci.c ahc->channel = 'D';
channel 1778 dev/pci/ahc_pci.c ahc->channel = 'A';
channel 672 dev/pci/ahd_pci.c + (sizeof(vpd) * (ahd->channel - 'A'))) / 2;
channel 688 dev/pci/ahd_pci.c start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A');
channel 1102 dev/pci/ahd_pci.c ahd->channel = (pa->pa_function == 1) ? 'B' : 'A';
channel 234 dev/pci/arc.c u_int8_t channel;// channel for SCSI target (0/1)
channel 1311 dev/pci/arc.c bd->bd_channel = diskinfo->scsi_attr.channel;
channel 1262 dev/pci/autri.c int i, ch, channel;
channel 1373 dev/pci/autri.c channel = (ch == 0) ? chst->ch : chst->ch_intr;
channel 1376 dev/pci/autri.c TWRITE4(sc,AUTRI_LFO_GC_CIR, reg | channel);
channel 1384 dev/pci/autri.c if (channel < 0x20) {
channel 1497 dev/pci/autri.c autri_disable_interrupt(sc, sc->sc_play.channel);
channel 1498 dev/pci/autri.c autri_disable_interrupt(sc, sc->sc_rec.channel);
channel 444 dev/pci/bktr/bktr_core.c bktr->tuner.channel = 0;
channel 1755 dev/pci/bktr/bktr_core.c *(unsigned int *)arg = bktr->tuner.channel;
channel 521 dev/pci/bktr/bktr_os.c ri->chan = tv->channel;
channel 583 dev/pci/bktr/bktr_os.c ri->chan = tv->channel;
channel 384 dev/pci/bktr/bktr_reg.h u_char channel;
channel 661 dev/pci/bktr/bktr_tuner.c frequency_lookup( bktr_ptr_t bktr, int channel )
channel 667 dev/pci/bktr/bktr_tuner.c if ( channel > TBL_CHNL )
channel 672 dev/pci/bktr/bktr_tuner.c if ( channel >= TBL_CHNL ) {
channel 674 dev/pci/bktr/bktr_tuner.c ((channel - TBL_CHNL) * TBL_OFFSET) );
channel 973 dev/pci/bktr/bktr_tuner.c tv_channel( bktr_ptr_t bktr, int channel )
channel 978 dev/pci/bktr/bktr_tuner.c if ( (frequency = frequency_lookup( bktr, channel )) < 0 )
channel 986 dev/pci/bktr/bktr_tuner.c return( (bktr->tuner.channel = channel) );
channel 89 dev/pci/bktr/bktr_tuner.h int tv_channel( bktr_ptr_t bktr, int channel );
channel 542 dev/pci/bt8370.c bus_size_t channel;
channel 603 dev/pci/bt8370.c for (channel = 0; channel < 32; channel++) {
channel 604 dev/pci/bt8370.c ebus_write(&ac->art_ebus, Bt8370_SBCn + channel, 0x00);
channel 605 dev/pci/bt8370.c ebus_write(&ac->art_ebus, Bt8370_TPCn + channel, 0x00);
channel 606 dev/pci/bt8370.c ebus_write(&ac->art_ebus, Bt8370_TSIGn + channel, 0x00);
channel 607 dev/pci/bt8370.c ebus_write(&ac->art_ebus, Bt8370_TSLIP_LOn + channel, 0x7e);
channel 608 dev/pci/bt8370.c ebus_write(&ac->art_ebus, Bt8370_RSLIP_LOn + channel, 0x7e);
channel 609 dev/pci/bt8370.c ebus_write(&ac->art_ebus, Bt8370_RPCn + channel, 0x00);
channel 613 dev/pci/bt8370.c for (channel = Bt8370_SBCn; channel < Bt8370_SBCn +
channel 614 dev/pci/bt8370.c nchannels; channel++) {
channel 615 dev/pci/bt8370.c ebus_write(&ac->art_ebus, channel, SBCn_RINDO |
channel 618 dev/pci/bt8370.c if (nchannels == 25 && channel == Bt8370_SBCn)
channel 619 dev/pci/bt8370.c ebus_write(&ac->art_ebus, channel, 0x00);
channel 621 dev/pci/bt8370.c for (channel = Bt8370_TPCn; channel < Bt8370_TPCn +
channel 622 dev/pci/bt8370.c nchannels; channel++) {
channel 623 dev/pci/bt8370.c ebus_write(&ac->art_ebus, channel, TPCn_CLEAR);
channel 625 dev/pci/bt8370.c for (channel = Bt8370_RPCn; channel < Bt8370_RPCn +
channel 626 dev/pci/bt8370.c nchannels; channel++) {
channel 627 dev/pci/bt8370.c ebus_write(&ac->art_ebus, channel, RPCn_CLEAR);
channel 689 dev/pci/cz.c u_int command, channel, param;
channel 696 dev/pci/cz.c channel = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_CHANNEL);
channel 705 dev/pci/cz.c cz->cz_dev.dv_xname, channel);
channel 710 dev/pci/cz.c sc = &cz->cz_ports[channel];
channel 725 dev/pci/cz.c cz->cz_dev.dv_xname, channel);
channel 897 dev/pci/emuxki.c sc->channel[i] = NULL;
channel 1136 dev/pci/emuxki.c chan->voice->sc->channel[num] = chan;
channel 1144 dev/pci/emuxki.c chan->voice->sc->channel[chan->num] = NULL;
channel 1368 dev/pci/emuxki.c struct emuxki_channel **channel = voice->sc->channel;
channel 1373 dev/pci/emuxki.c if ((stereo && (channel[i + 1] != NULL)) ||
channel 1374 dev/pci/emuxki.c (channel[i] != NULL)) /* Looking for free channels */
channel 250 dev/pci/emuxkivar.h struct emuxki_channel *channel[EMU_NUMCHAN];
channel 85 dev/pci/if_san_te1.c #define TEST_RPSC_REG(card,reg,channel,value) \
channel 87 dev/pci/if_san_te1.c unsigned char test_value = ReadRPSCReg(card,channel,reg); \
channel 92 dev/pci/if_san_te1.c __FILE__, __LINE__, reg, channel, value); \
channel 96 dev/pci/if_san_te1.c #define TEST_TPSC_REG(card,reg,channel,value) \
channel 98 dev/pci/if_san_te1.c unsigned char test_value = ReadTPSCReg(card,channel,reg); \
channel 103 dev/pci/if_san_te1.c __FILE__, __LINE__, reg, channel, value); \
channel 110 dev/pci/if_san_te1.c #define TEST_RPSC_REG(card,reg,channel,value)
channel 111 dev/pci/if_san_te1.c #define TEST_TPSC_REG(card,reg,channel,value)
channel 115 dev/pci/if_san_te1.c #define READ_RPSC_REG(reg,channel) ReadRPSCReg(card,reg,channel)
channel 116 dev/pci/if_san_te1.c #define READ_TPSC_REG(reg,channel) ReadTPSCReg(card,reg,channel)
channel 117 dev/pci/if_san_te1.c #define READ_SIGX_REG(reg,channel) ReadSIGXReg(card,reg,channel)
channel 118 dev/pci/if_san_te1.c #define WRITE_RPSC_REG(reg,channel,value) \
channel 120 dev/pci/if_san_te1.c WriteRPSCReg(card,reg,channel,(unsigned char)value); \
channel 121 dev/pci/if_san_te1.c TEST_RPSC_REG(card,reg,channel,(unsigned char)value); \
channel 124 dev/pci/if_san_te1.c #define WRITE_TPSC_REG(reg,channel,value) \
channel 126 dev/pci/if_san_te1.c WriteTPSCReg(card,reg,channel,(unsigned char)value); \
channel 131 dev/pci/if_san_te1.c #define WRITE_SIGX_REG(reg,channel,value) \
channel 133 dev/pci/if_san_te1.c WriteSIGXReg(card,reg,channel,(unsigned char)value); \
channel 134 dev/pci/if_san_te1.c TEST_SIGX_REG(card,reg,channel,(unsigned char)value); \
channel 1501 dev/pci/if_san_te1.c int channel = 0;
channel 1512 dev/pci/if_san_te1.c for (channel = start_channel; channel <= stop_channel; channel++) {
channel 1513 dev/pci/if_san_te1.c WRITE_TPSC_REG(REG_TPSC_DATA_CTRL_BYTE, channel, 0x00);
channel 1514 dev/pci/if_san_te1.c WRITE_TPSC_REG(REG_TPSC_IDLE_CODE_BYTE, channel, 0x00);
channel 1515 dev/pci/if_san_te1.c WRITE_TPSC_REG(REG_TPSC_SIGNALING_BYTE, channel, 0x00);
channel 1523 dev/pci/if_san_te1.c int channel = 0;
channel 1534 dev/pci/if_san_te1.c for (channel = start_channel; channel <= stop_channel; channel++) {
channel 1535 dev/pci/if_san_te1.c WRITE_RPSC_REG(REG_RPSC_DATA_CTRL_BYTE, channel, 0x00);
channel 1536 dev/pci/if_san_te1.c WRITE_RPSC_REG(REG_RPSC_DATA_COND_BYTE, channel, 0x00);
channel 1537 dev/pci/if_san_te1.c WRITE_RPSC_REG(REG_RPSC_SIGNALING_BYTE, channel, 0x00);
channel 1551 dev/pci/if_san_te1.c WriteTPSCReg(sdla_t *card, int reg, int channel, unsigned char value)
channel 1557 dev/pci/if_san_te1.c reg += channel;
channel 1605 dev/pci/if_san_te1.c ReadTPSCReg(sdla_t *card, int reg, int channel)
channel 1610 dev/pci/if_san_te1.c reg += channel;
channel 1656 dev/pci/if_san_te1.c WriteRPSCReg(sdla_t* card, int reg, int channel, unsigned char value)
channel 1662 dev/pci/if_san_te1.c reg += channel;
channel 1707 dev/pci/if_san_te1.c static unsigned char ReadRPSCReg(sdla_t* card, int reg, int channel)
channel 1712 dev/pci/if_san_te1.c reg += channel;
channel 1807 dev/pci/if_san_te1.c static int EnableTxChannel(sdla_t* card, int channel)
channel 1813 dev/pci/if_san_te1.c WRITE_TPSC_REG(REG_TPSC_DATA_CTRL_BYTE, channel,
channel 1814 dev/pci/if_san_te1.c (((READ_TPSC_REG(REG_TPSC_DATA_CTRL_BYTE, channel) &
channel 1819 dev/pci/if_san_te1.c WRITE_TPSC_REG(REG_TPSC_DATA_CTRL_BYTE, channel,
channel 1820 dev/pci/if_san_te1.c ((READ_TPSC_REG(REG_TPSC_DATA_CTRL_BYTE, channel) &
channel 1829 dev/pci/if_san_te1.c WRITE_TPSC_REG(REG_TPSC_E1_CTRL_BYTE, channel,
channel 1830 dev/pci/if_san_te1.c (READ_TPSC_REG(REG_TPSC_E1_CTRL_BYTE, channel) &
channel 1835 dev/pci/if_san_te1.c WRITE_TPSC_REG(REG_TPSC_SIGNALING_BYTE, channel, 0x00);
channel 1839 dev/pci/if_san_te1.c WRITE_TPSC_REG(REG_TPSC_IDLE_CODE_BYTE, channel, 0x00);
channel 1849 dev/pci/if_san_te1.c static int EnableRxChannel(sdla_t* card, int channel)
channel 1852 dev/pci/if_san_te1.c WRITE_RPSC_REG(REG_RPSC_DATA_CTRL_BYTE, channel,
channel 1853 dev/pci/if_san_te1.c ((READ_RPSC_REG(REG_RPSC_DATA_CTRL_BYTE, channel) &
channel 1865 dev/pci/if_san_te1.c static int DisableTxChannel(sdla_t* card, int channel)
channel 1870 dev/pci/if_san_te1.c WRITE_TPSC_REG(REG_RPSC_DATA_CTRL_BYTE, channel,
channel 1871 dev/pci/if_san_te1.c ((READ_TPSC_REG(REG_TPSC_DATA_CTRL_BYTE, channel) &
channel 1876 dev/pci/if_san_te1.c WRITE_TPSC_REG(REG_TPSC_E1_CTRL_BYTE, channel,
channel 1877 dev/pci/if_san_te1.c ((READ_TPSC_REG(REG_TPSC_E1_CTRL_BYTE, channel) &
channel 1880 dev/pci/if_san_te1.c WRITE_TPSC_REG(REG_TPSC_SIGNALING_BYTE, channel, 0x00);
channel 1883 dev/pci/if_san_te1.c WRITE_TPSC_REG(REG_TPSC_IDLE_CODE_BYTE, channel, 0x55);
channel 1893 dev/pci/if_san_te1.c static int DisableRxChannel(sdla_t* card, int channel)
channel 1897 dev/pci/if_san_te1.c WRITE_RPSC_REG(REG_RPSC_DATA_CTRL_BYTE, channel,
channel 1898 dev/pci/if_san_te1.c ((READ_RPSC_REG(REG_RPSC_DATA_CTRL_BYTE, channel) &
channel 2727 dev/pci/if_san_te1.c SetLoopBackChannel(sdla_t *card, int channel, unsigned char mode)
channel 2737 dev/pci/if_san_te1.c WRITE_TPSC_REG(REG_TPSC_DATA_CTRL_BYTE, channel,
channel 2738 dev/pci/if_san_te1.c ((READ_TPSC_REG(REG_TPSC_DATA_CTRL_BYTE, channel) &
channel 2742 dev/pci/if_san_te1.c WRITE_TPSC_REG(REG_TPSC_DATA_CTRL_BYTE, channel,
channel 2743 dev/pci/if_san_te1.c ((READ_TPSC_REG(REG_TPSC_DATA_CTRL_BYTE, channel) &
channel 3101 dev/pci/if_san_te1.c int channel;
channel 3103 dev/pci/if_san_te1.c channel = status & LINELB_DS1LINE_MASK;
channel 3109 dev/pci/if_san_te1.c channel);
channel 3110 dev/pci/if_san_te1.c SetLoopBackChannel(card, channel,
channel 1151 dev/pci/musycc.c musycc_rxeom(struct musycc_group *mg, int channel, int forcekick)
channel 1161 dev/pci/musycc.c ifp = mg->mg_channels[channel]->cc_ifp;
channel 1163 dev/pci/musycc.c start_rx = cur_rx = mg->mg_dma_d[channel].rx_prod;
channel 1223 dev/pci/musycc.c mg->mg_dma_d[channel].rx_prod = cur_rx;
channel 1228 dev/pci/musycc.c mg->mg_channels[channel]->cc_ifp->if_xname, consumed));
channel 1229 dev/pci/musycc.c mg->mg_group->rx_headp[channel] = htole32(
channel 1232 dev/pci/musycc.c musycc_sreq(mg, channel, MUSYCC_SREQ_SET(8),
channel 1242 dev/pci/musycc.c musycc_txeom(struct musycc_group *mg, int channel, int forcekick)
channel 1249 dev/pci/musycc.c ifp = mg->mg_channels[channel]->cc_ifp;
channel 1257 dev/pci/musycc.c for (dd = mg->mg_dma_d[channel].tx_pend;
channel 1258 dev/pci/musycc.c dd != mg->mg_dma_d[channel].tx_cur;
channel 1268 dev/pci/musycc.c mg->mg_dma_d[channel].tx_use--;
channel 1281 dev/pci/musycc.c mg->mg_dma_d[channel].tx_pkts--;
channel 1286 dev/pci/musycc.c dd_pend = mg->mg_dma_d[channel].tx_pend;
channel 1287 dev/pci/musycc.c mg->mg_dma_d[channel].tx_pend = dd;
channel 1297 dev/pci/musycc.c mg->mg_channels[channel]->cc_ifp->if_xname));
channel 1298 dev/pci/musycc.c mg->mg_group->tx_headp[channel] =
channel 1300 dev/pci/musycc.c (caddr_t)mg->mg_dma_d[channel].tx_pend - mg->mg_listkva);
channel 1302 dev/pci/musycc.c musycc_sreq(mg, channel, MUSYCC_SREQ_SET(8), MUSYCC_SREQ_TX,
channel 1471 dev/pci/musycc.c musycc_sreq(struct musycc_group *mg, int channel, u_int32_t req, int dir,
channel 1489 dev/pci/musycc.c mg->mg_gnum, channel, req, dir));
channel 1493 dev/pci/musycc.c req |= MUSYCC_SREQ_CHSET(channel);
channel 1506 dev/pci/musycc.c req |= MUSYCC_SREQ_CHSET(channel);
channel 1358 dev/pci/pciide.c PCIIDE_REG_CMD_BASE(wdc_cp->channel));
channel 1362 dev/pci/pciide.c if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel),
channel 1371 dev/pci/pciide.c PCIIDE_REG_CTL_BASE(wdc_cp->channel));
channel 1375 dev/pci/pciide.c if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel),
channel 1467 dev/pci/pciide.c int chan = cp->wdc_channel.channel;
channel 1593 dev/pci/pciide.c if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive)
channel 1603 dev/pci/pciide.c pciide_dma_table_setup(struct pciide_softc *sc, int channel, int drive)
channel 1610 dev/pci/pciide.c &sc->pciide_channels[channel].dma_maps[drive];
channel 1622 dev/pci/pciide.c channel, drive, error);
channel 1632 dev/pci/pciide.c channel, drive, error);
channel 1646 dev/pci/pciide.c channel, drive, error);
channel 1655 dev/pci/pciide.c channel, drive, error);
channel 1667 dev/pci/pciide.c channel, drive, error);
channel 1674 dev/pci/pciide.c pciide_dma_init(void *v, int channel, int drive, void *databuf,
channel 1679 dev/pci/pciide.c struct pciide_channel *cp = &sc->pciide_channels[channel];
channel 1681 dev/pci/pciide.c &sc->pciide_channels[channel].dma_maps[drive];
channel 1692 dev/pci/pciide.c channel, drive, error);
channel 1743 dev/pci/pciide.c PCIIDE_DMACTL_WRITE(sc, channel, PCIIDE_DMACTL_READ(sc, channel));
channel 1745 dev/pci/pciide.c PCIIDE_DMATBL_WRITE(sc, channel,
channel 1748 dev/pci/pciide.c PCIIDE_DMACMD_WRITE(sc, channel,
channel 1756 dev/pci/pciide.c pciide_dma_start(void *v, int channel, int drive)
channel 1761 dev/pci/pciide.c PCIIDE_DMACMD_WRITE(sc, channel, PCIIDE_DMACMD_READ(sc, channel) |
channel 1764 dev/pci/pciide.c sc->pciide_channels[channel].dma_in_progress = 1;
channel 1768 dev/pci/pciide.c pciide_dma_finish(void *v, int channel, int drive, int force)
channel 1771 dev/pci/pciide.c struct pciide_channel *cp = &sc->pciide_channels[channel];
channel 1775 dev/pci/pciide.c &sc->pciide_channels[channel].dma_maps[drive];
channel 1777 dev/pci/pciide.c status = PCIIDE_DMACTL_READ(sc, channel);
channel 1787 dev/pci/pciide.c PCIIDE_DMACMD_WRITE(sc, channel,
channel 1799 dev/pci/pciide.c PCIIDE_DMACTL_WRITE(sc, channel, status);
channel 1803 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status);
channel 1809 dev/pci/pciide.c "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel,
channel 1820 dev/pci/pciide.c sc->pciide_channels[channel].dma_in_progress = 0;
channel 1829 dev/pci/pciide.c int chan = chp->channel;
channel 1837 dev/pci/pciide.c pciide_chansetup(struct pciide_softc *sc, int channel, pcireg_t interface)
channel 1839 dev/pci/pciide.c struct pciide_channel *cp = &sc->pciide_channels[channel];
channel 1840 dev/pci/pciide.c sc->wdc_chanarray[channel] = &cp->wdc_channel;
channel 1841 dev/pci/pciide.c cp->name = PCIIDE_CHANNEL_NAME(channel);
channel 1842 dev/pci/pciide.c cp->wdc_channel.channel = channel;
channel 1865 dev/pci/pciide.c if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel))
channel 1870 dev/pci/pciide.c wdc_cp->channel, cmdsizep, ctlsizep);
channel 1909 dev/pci/pciide.c if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0)
channel 1932 dev/pci/pciide.c if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0)
channel 1966 dev/pci/pciide.c int channel, drive;
channel 2000 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
channel 2001 dev/pci/pciide.c cp = &sc->pciide_channels[channel];
channel 2002 dev/pci/pciide.c if (pciide_chansetup(sc, channel, interface) == 0)
channel 2004 dev/pci/pciide.c if (interface & PCIIDE_INTERFACE_PCI(channel)) {
channel 2009 dev/pci/pciide.c channel, &cmdsize, &ctlsize);
channel 2017 dev/pci/pciide.c pciide_map_compat_intr(pa, cp, channel, interface);
channel 2045 dev/pci/pciide.c pciide_unmap_compat_intr(pa, cp, channel, interface);
channel 2048 dev/pci/pciide.c if (interface & PCIIDE_INTERFACE_PCI(channel))
channel 2066 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
channel 2068 dev/pci/pciide.c cp = &sc->pciide_channels[channel];
channel 2076 dev/pci/pciide.c if (pciide_dma_table_setup(sc, channel, drive) != 0) {
channel 2081 dev/pci/pciide.c channel, drive);
channel 2086 dev/pci/pciide.c channel, drive);
channel 2091 dev/pci/pciide.c PCIIDE_DMACTL_WRITE(sc, channel, idedma_ctl);
channel 2101 dev/pci/pciide.c int channel;
channel 2130 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
channel 2131 dev/pci/pciide.c cp = &sc->pciide_channels[channel];
channel 2132 dev/pci/pciide.c if (pciide_chansetup(sc, channel, interface) == 0)
channel 2175 dev/pci/pciide.c PCIIDE_DMACTL_WRITE(sc, chp->channel, idedma_ctl);
channel 2224 dev/pci/pciide.c int channel;
channel 2301 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
channel 2302 dev/pci/pciide.c cp = &sc->pciide_channels[channel];
channel 2305 dev/pci/pciide.c if (pciide_chansetup(sc, channel, 0) == 0)
channel 2308 dev/pci/pciide.c if ((PIIX_IDETIM_READ(idetim, channel) &
channel 2315 dev/pci/pciide.c pciide_map_compat_intr(pa, cp, channel, 0);
channel 2323 dev/pci/pciide.c channel);
channel 2332 dev/pci/pciide.c pciide_unmap_compat_intr(pa, cp, channel, 0);
channel 2343 dev/pci/pciide.c int channel;
channel 2430 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
channel 2431 dev/pci/pciide.c cp = &sc->pciide_channels[channel];
channel 2432 dev/pci/pciide.c if (pciide_chansetup(sc, channel, interface) == 0)
channel 2435 dev/pci/pciide.c pciide_map_compat_intr(pa, cp, channel, interface);
channel 2445 dev/pci/pciide.c pciide_unmap_compat_intr(pa, cp, channel, interface);
channel 2459 dev/pci/pciide.c idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel);
channel 2464 dev/pci/pciide.c chp->channel);
channel 2524 dev/pci/pciide.c mode[drive], 1, chp->channel);
channel 2531 dev/pci/pciide.c mode[0], 0, chp->channel);
channel 2534 dev/pci/pciide.c mode[1], 0, chp->channel);
channel 2550 dev/pci/pciide.c IDEDMA_CTL(chp->channel),
channel 2565 dev/pci/pciide.c int channel = chp->channel;
channel 2571 dev/pci/pciide.c idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel);
channel 2572 dev/pci/pciide.c sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) |
channel 2573 dev/pci/pciide.c PIIX_SIDETIM_RTC_MASK(channel));
channel 2577 dev/pci/pciide.c if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0)
channel 2580 dev/pci/pciide.c idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel);
channel 2586 dev/pci/pciide.c udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) |
channel 2587 dev/pci/pciide.c PIIX_UDMATIM_SET(0x3, channel, drive));
channel 2629 dev/pci/pciide.c (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0)
channel 2632 dev/pci/pciide.c ideconf |= PIIX_CONFIG_UDMA100(channel, drive);
channel 2634 dev/pci/pciide.c ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive);
channel 2636 dev/pci/pciide.c ideconf |= PIIX_CONFIG_UDMA66(channel,
channel 2639 dev/pci/pciide.c ideconf &= ~PIIX_CONFIG_UDMA66(channel,
channel 2648 dev/pci/pciide.c (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0)
channel 2651 dev/pci/pciide.c ideconf |= PIIX_CONFIG_UDMA66(channel, drive);
channel 2653 dev/pci/pciide.c ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive);
channel 2660 dev/pci/pciide.c udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive);
channel 2662 dev/pci/pciide.c piix4_sct_udma[drvp->UDMA_mode], channel, drive);
channel 2668 dev/pci/pciide.c drvp->DMA_mode, 1, channel);
channel 2671 dev/pci/pciide.c drvp->DMA_mode, 1, channel);
channel 2673 dev/pci/pciide.c PIIX_IDETIM_SITRE, channel);
channel 2682 dev/pci/pciide.c drvp->PIO_mode, 0, channel);
channel 2685 dev/pci/pciide.c drvp->PIO_mode, 0, channel);
channel 2687 dev/pci/pciide.c PIIX_IDETIM_SITRE, channel);
channel 2693 dev/pci/pciide.c IDEDMA_CTL(channel),
channel 2706 dev/pci/pciide.c piix_setup_idetim_timings(u_int8_t mode, u_int8_t dma, u_int8_t channel)
channel 2713 dev/pci/pciide.c channel));
channel 2718 dev/pci/pciide.c channel));
channel 2727 dev/pci/pciide.c u_int8_t channel = chp->channel;
channel 2741 dev/pci/pciide.c ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel);
channel 2754 dev/pci/pciide.c channel);
channel 2768 dev/pci/pciide.c ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel);
channel 2770 dev/pci/pciide.c ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel);
channel 2771 dev/pci/pciide.c ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel);
channel 2778 dev/pci/pciide.c piix_setup_sidetim_timings(u_int8_t mode, u_int8_t dma, u_int8_t channel)
channel 2781 dev/pci/pciide.c return (PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) |
channel 2782 dev/pci/pciide.c PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel));
channel 2784 dev/pci/pciide.c return (PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) |
channel 2785 dev/pci/pciide.c PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel));
channel 2793 dev/pci/pciide.c int channel;
channel 2827 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
channel 2828 dev/pci/pciide.c cp = &sc->pciide_channels[channel];
channel 2829 dev/pci/pciide.c if (pciide_chansetup(sc, channel, interface) == 0)
channel 2832 dev/pci/pciide.c if ((chanenable & AMD756_CHAN_EN(channel)) == 0) {
channel 2837 dev/pci/pciide.c pciide_map_compat_intr(pa, cp, channel, interface);
channel 2845 dev/pci/pciide.c chanenable &= ~AMD756_CHAN_EN(channel);
channel 2848 dev/pci/pciide.c pciide_unmap_compat_intr(pa, cp, channel, interface);
channel 2877 dev/pci/pciide.c datatim_reg &= ~AMD756_DATATIM_MASK(chp->channel);
channel 2878 dev/pci/pciide.c udmatim_reg &= ~AMD756_UDMA_MASK(chp->channel);
channel 2902 dev/pci/pciide.c if ((chanenable & AMD756_CABLE(chp->channel,
channel 2907 dev/pci/pciide.c chp->channel, drive), DEBUG_PROBE);
channel 2911 dev/pci/pciide.c udmatim_reg |= AMD756_UDMA_EN(chp->channel, drive) |
channel 2912 dev/pci/pciide.c AMD756_UDMA_EN_MTH(chp->channel, drive) |
channel 2913 dev/pci/pciide.c AMD756_UDMA_TIME(chp->channel, drive,
channel 2931 dev/pci/pciide.c chp->channel, drive);
channel 2955 dev/pci/pciide.c AMD756_DATATIM_PULSE(chp->channel, drive,
channel 2957 dev/pci/pciide.c AMD756_DATATIM_RECOV(chp->channel, drive,
channel 2963 dev/pci/pciide.c IDEDMA_CTL(chp->channel),
channel 2976 dev/pci/pciide.c int channel;
channel 3088 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
channel 3089 dev/pci/pciide.c cp = &sc->pciide_channels[channel];
channel 3090 dev/pci/pciide.c if (pciide_chansetup(sc, channel, interface) == 0)
channel 3094 dev/pci/pciide.c if ((ideconf & APO_IDECONF_EN(channel)) == 0) {
channel 3099 dev/pci/pciide.c pciide_map_compat_intr(pa, cp, channel, interface);
channel 3109 dev/pci/pciide.c ideconf &= ~APO_IDECONF_EN(channel);
channel 3116 dev/pci/pciide.c apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel);
channel 3119 dev/pci/pciide.c pciide_unmap_compat_intr(pa, cp, channel, interface);
channel 3139 dev/pci/pciide.c datatim_reg &= ~APO_DATATIM_MASK(chp->channel);
channel 3140 dev/pci/pciide.c udmatim_reg &= ~APO_UDMA_MASK(chp->channel);
channel 3178 dev/pci/pciide.c udmatim_reg |= APO_UDMA_EN(chp->channel, drive) |
channel 3179 dev/pci/pciide.c APO_UDMA_EN_MTH(chp->channel, drive);
channel 3181 dev/pci/pciide.c udmatim_reg |= APO_UDMA_TIME(chp->channel,
channel 3185 dev/pci/pciide.c udmatim_reg |= APO_UDMA_TIME(chp->channel,
channel 3189 dev/pci/pciide.c udmatim_reg |= APO_UDMA_CLK66(chp->channel);
channel 3190 dev/pci/pciide.c udmatim_reg |= APO_UDMA_TIME(chp->channel,
channel 3194 dev/pci/pciide.c udmatim_reg |= APO_UDMA_TIME(chp->channel,
channel 3220 dev/pci/pciide.c APO_DATATIM_PULSE(chp->channel, drive,
channel 3222 dev/pci/pciide.c APO_DATATIM_RECOV(chp->channel, drive,
channel 3228 dev/pci/pciide.c IDEDMA_CTL(chp->channel),
channel 3238 dev/pci/pciide.c int channel)
channel 3240 dev/pci/pciide.c struct pciide_channel *cp = &sc->pciide_channels[channel];
channel 3261 dev/pci/pciide.c sc->wdc_chanarray[channel] = &cp->wdc_channel;
channel 3262 dev/pci/pciide.c cp->name = PCIIDE_CHANNEL_NAME(channel);
channel 3263 dev/pci/pciide.c cp->wdc_channel.channel = channel;
channel 3278 dev/pci/pciide.c if (channel > 0 && one_channel) {
channel 3297 dev/pci/pciide.c if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) {
channel 3303 dev/pci/pciide.c pciide_map_compat_intr(pa, cp, channel, interface);
channel 3308 dev/pci/pciide.c pciide_unmap_compat_intr(pa, cp, channel, interface);
channel 3312 dev/pci/pciide.c if (channel == 1) {
channel 3316 dev/pci/pciide.c pciide_unmap_compat_intr(pa, cp, channel, interface);
channel 3357 dev/pci/pciide.c int channel;
channel 3369 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
channel 3370 dev/pci/pciide.c cmd_channel_map(pa, sc, channel);
channel 3378 dev/pci/pciide.c int channel;
channel 3453 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
channel 3454 dev/pci/pciide.c cp = &sc->pciide_channels[channel];
channel 3455 dev/pci/pciide.c cmd_channel_map(pa, sc, channel);
channel 3497 dev/pci/pciide.c sc->sc_tag, CMD_UDMATIM(chp->channel));
channel 3501 dev/pci/pciide.c CMD_BICSR_80(chp->channel)) == 0) {
channel 3506 dev/pci/pciide.c chp->channel, drive), DEBUG_PROBE);
channel 3520 dev/pci/pciide.c CMD_UDMATIM(chp->channel), udma_reg);
channel 3531 dev/pci/pciide.c CMD_UDMATIM(chp->channel));
channel 3534 dev/pci/pciide.c CMD_UDMATIM(chp->channel),
channel 3546 dev/pci/pciide.c CMD_DATA_TIM(chp->channel, drive), tim);
channel 3551 dev/pci/pciide.c IDEDMA_CTL(chp->channel),
channel 3574 dev/pci/pciide.c if (chp->channel == 0) {
channel 3588 dev/pci/pciide.c int channel;
channel 3613 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
channel 3614 dev/pci/pciide.c cp = &sc->pciide_channels[channel];
channel 3615 dev/pci/pciide.c cmd680_channel_map(pa, sc, channel);
channel 3624 dev/pci/pciide.c int channel)
channel 3626 dev/pci/pciide.c struct pciide_channel *cp = &sc->pciide_channels[channel];
channel 3642 dev/pci/pciide.c sc->wdc_chanarray[channel] = &cp->wdc_channel;
channel 3643 dev/pci/pciide.c cp->name = PCIIDE_CHANNEL_NAME(channel);
channel 3644 dev/pci/pciide.c cp->wdc_channel.channel = channel;
channel 3657 dev/pci/pciide.c reg = 0xa2 + channel * 16;
channel 3663 dev/pci/pciide.c (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ?
channel 3665 dev/pci/pciide.c (interface & PCIIDE_INTERFACE_PCI(channel)) ?
channel 3671 dev/pci/pciide.c pciide_map_compat_intr(pa, cp, channel, interface);
channel 3697 dev/pci/pciide.c mode = pciide_pci_read(pc, pa, 0x80 + chp->channel * 4);
channel 3707 dev/pci/pciide.c off = 0xa0 + chp->channel * 16;
channel 3719 dev/pci/pciide.c off = 0xac + chp->channel * 16 + drive * 2;
channel 3729 dev/pci/pciide.c off = 0xa8 + chp->channel * 16 + drive * 2;
channel 3736 dev/pci/pciide.c off = 0xa4 + chp->channel * 16 + drive * 2;
channel 3743 dev/pci/pciide.c pciide_pci_write(pc, pa, 0x80 + chp->channel * 4, mode);
channel 3747 dev/pci/pciide.c IDEDMA_CTL(chp->channel),
channel 3795 dev/pci/pciide.c int channel;
channel 3882 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
channel 3883 dev/pci/pciide.c cp = &sc->pciide_channels[channel];
channel 3884 dev/pci/pciide.c if (pciide_chansetup(sc, channel, interface) == 0)
channel 3934 dev/pci/pciide.c PCIIDE_DMACTL_WRITE(sc, chp->channel, idedma_ctl);
channel 3936 dev/pci/pciide.c BA5_WRITE_4(sc, chp->channel, ba5_IDE_DTM, dtm);
channel 3974 dev/pci/pciide.c BA5_WRITE_4(sc, chp->channel, ba5_SControl, scontrol);
channel 3977 dev/pci/pciide.c BA5_WRITE_4(sc, chp->channel, ba5_SControl, scontrol);
channel 3980 dev/pci/pciide.c sstatus = BA5_READ_4(sc, chp->channel, ba5_SStatus);
channel 3983 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus,
channel 3984 dev/pci/pciide.c BA5_READ_4(sc, chp->channel, ba5_SControl));
channel 3994 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel);
channel 3999 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel);
channel 4033 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel,
channel 4048 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel);
channel 4062 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus);
channel 4073 dev/pci/pciide.c int channel;
channel 4175 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
channel 4176 dev/pci/pciide.c cp = &sc->pciide_channels[channel];
channel 4177 dev/pci/pciide.c if (sii3114_chansetup(sc, channel) == 0)
channel 4238 dev/pci/pciide.c sii3114_chansetup(struct pciide_softc *sc, int channel)
channel 4246 dev/pci/pciide.c struct pciide_channel *cp = &sc->pciide_channels[channel];
channel 4248 dev/pci/pciide.c sc->wdc_chanarray[channel] = &cp->wdc_channel;
channel 4254 dev/pci/pciide.c if (channel == 2)
channel 4257 dev/pci/pciide.c cp->name = channel_names[channel];
channel 4258 dev/pci/pciide.c cp->wdc_channel.channel = channel;
channel 4277 dev/pci/pciide.c int chan = wdc_cp->channel;
channel 4333 dev/pci/pciide.c return (bus_space_read_1(sl->regs[chp->channel].ctl_iot,
channel 4334 dev/pci/pciide.c sl->regs[chp->channel].ctl_ioh, reg & _WDC_REGMASK));
channel 4336 dev/pci/pciide.c return (bus_space_read_1(sl->regs[chp->channel].cmd_iot,
channel 4337 dev/pci/pciide.c sl->regs[chp->channel].cmd_iohs[reg & _WDC_REGMASK], 0));
channel 4348 dev/pci/pciide.c bus_space_write_1(sl->regs[chp->channel].ctl_iot,
channel 4349 dev/pci/pciide.c sl->regs[chp->channel].ctl_ioh, reg & _WDC_REGMASK, val);
channel 4351 dev/pci/pciide.c bus_space_write_1(sl->regs[chp->channel].cmd_iot,
channel 4352 dev/pci/pciide.c sl->regs[chp->channel].cmd_iohs[reg & _WDC_REGMASK],
channel 4459 dev/pci/pciide.c cp->wdc_channel.channel = 0;
channel 4560 dev/pci/pciide.c IDEDMA_CTL(chp->channel), idedma_ctl);
channel 4657 dev/pci/pciide.c int channel;
channel 4770 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
channel 4771 dev/pci/pciide.c cp = &sc->pciide_channels[channel];
channel 4772 dev/pci/pciide.c if (pciide_chansetup(sc, channel, interface) == 0)
channel 4774 dev/pci/pciide.c if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) ||
channel 4775 dev/pci/pciide.c (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) {
channel 4780 dev/pci/pciide.c pciide_map_compat_intr(pa, cp, channel, interface);
channel 4786 dev/pci/pciide.c pciide_unmap_compat_intr(pa, cp, channel, interface);
channel 4790 dev/pci/pciide.c if (channel == 0)
channel 4798 dev/pci/pciide.c pciide_unmap_compat_intr(pa, cp, channel, interface);
channel 4824 dev/pci/pciide.c chp->channel, drive);
channel 4834 dev/pci/pciide.c SIS96x_REG_CBL(chp->channel)) & SIS96x_REG_CBL_33) {
channel 4859 dev/pci/pciide.c chp->channel, drive, sis_tim, regtim), DEBUG_PROBE);
channel 4865 dev/pci/pciide.c IDEDMA_CTL(chp->channel), idedma_ctl);
channel 4882 dev/pci/pciide.c "channel %d 0x%x\n", chp->channel,
channel 4883 dev/pci/pciide.c pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))),
channel 4904 dev/pci/pciide.c SIS_REG_CBL) & SIS_REG_CBL_33(chp->channel)) {
channel 4965 dev/pci/pciide.c "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE);
channel 4966 dev/pci/pciide.c pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim);
channel 4970 dev/pci/pciide.c IDEDMA_CTL(chp->channel), idedma_ctl);
channel 4979 dev/pci/pciide.c int channel;
channel 5021 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
channel 5022 dev/pci/pciide.c cp = &sc->pciide_channels[channel];
channel 5023 dev/pci/pciide.c if (pciide_chansetup(sc, channel, interface) == 0)
channel 5026 dev/pci/pciide.c pciide_map_compat_intr(pa, cp, channel, interface);
channel 5033 dev/pci/pciide.c pciide_unmap_compat_intr(pa, cp, channel, interface);
channel 5080 dev/pci/pciide.c NATSEMI_RTREG(chp->channel, drive), tim);
channel 5082 dev/pci/pciide.c NATSEMI_WTREG(chp->channel, drive), tim);
channel 5087 dev/pci/pciide.c IDEDMA_CTL(chp->channel), idedma_ctl);
channel 5093 dev/pci/pciide.c ~(NATSEMI_CHMASK(chp->channel)));
channel 5100 dev/pci/pciide.c IDEDMA_CTL(chp->channel),
channel 5102 dev/pci/pciide.c IDEDMA_CTL(chp->channel)));
channel 5114 dev/pci/pciide.c IDEDMA_CMD(chp->channel));
channel 5116 dev/pci/pciide.c IDEDMA_CTL(chp->channel)) &
channel 5119 dev/pci/pciide.c IDEDMA_CMD(chp->channel), clr);
channel 5163 dev/pci/pciide.c int channel;
channel 5208 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
channel 5209 dev/pci/pciide.c cp = &sc->pciide_channels[channel];
channel 5210 dev/pci/pciide.c if (pciide_chansetup(sc, channel, interface) == 0)
channel 5212 dev/pci/pciide.c pciide_map_compat_intr(pa, cp, channel, interface);
channel 5218 dev/pci/pciide.c pciide_unmap_compat_intr(pa, cp, channel, interface);
channel 5233 dev/pci/pciide.c int channel = chp->channel;
channel 5256 dev/pci/pciide.c SCx200_TIM_PIO(channel, drive));
channel 5258 dev/pci/pciide.c SCx200_TIM_DMA(channel, drive));
channel 5260 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, channel, drive,
channel 5296 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, channel, drive,
channel 5300 dev/pci/pciide.c SCx200_TIM_PIO(channel, drive), piotim);
channel 5302 dev/pci/pciide.c SCx200_TIM_DMA(channel, drive), dmatim);
channel 5308 dev/pci/pciide.c IDEDMA_CTL(channel), idedma_ctl);
channel 5318 dev/pci/pciide.c int channel;
channel 5377 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
channel 5378 dev/pci/pciide.c cp = &sc->pciide_channels[channel];
channel 5379 dev/pci/pciide.c if (pciide_chansetup(sc, channel, interface) == 0)
channel 5381 dev/pci/pciide.c if ((interface & PCIIDE_CHAN_EN(channel)) == 0) {
channel 5386 dev/pci/pciide.c pciide_map_compat_intr(pa, cp, channel, interface);
channel 5392 dev/pci/pciide.c pciide_unmap_compat_intr(pa, cp, channel, interface);
channel 5396 dev/pci/pciide.c cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT);
channel 5401 dev/pci/pciide.c pciide_unmap_compat_intr(pa, cp, channel, interface);
channel 5428 dev/pci/pciide.c ACER_0x4A_80PIN(chp->channel)) {
channel 5430 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel),
channel 5445 dev/pci/pciide.c "channel %d drive %d 0x%x\n", chp->channel, drive,
channel 5447 dev/pci/pciide.c ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE);
channel 5449 dev/pci/pciide.c acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) |
channel 5450 dev/pci/pciide.c ACER_UDMA_EN(chp->channel, drive) |
channel 5451 dev/pci/pciide.c ACER_UDMA_TIM(chp->channel, drive, 0x7));
channel 5457 dev/pci/pciide.c ACER_FTH_OPL(chp->channel, drive, 0x1);
channel 5461 dev/pci/pciide.c acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2);
channel 5465 dev/pci/pciide.c acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive);
channel 5467 dev/pci/pciide.c ACER_UDMA_TIM(chp->channel, drive,
channel 5492 dev/pci/pciide.c ACER_IDETIM(chp->channel, drive),
channel 5501 dev/pci/pciide.c IDEDMA_CTL(chp->channel), idedma_ctl);
channel 5739 dev/pci/pciide.c HPT_IDETIM(chp->channel, drive));
channel 5745 dev/pci/pciide.c if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 &&
channel 5750 dev/pci/pciide.c chp->channel, drive), DEBUG_PROBE);
channel 5772 dev/pci/pciide.c HPT_IDETIM(chp->channel, drive), after);
channel 5781 dev/pci/pciide.c IDEDMA_CTL(chp->channel), idedma_ctl);
channel 5850 dev/pci/pciide.c int channel = chp->channel;
channel 5853 dev/pci/pciide.c PDC268_INDEX(channel), index);
channel 5855 dev/pci/pciide.c PDC268_DATA(channel)));
channel 5864 dev/pci/pciide.c int channel = chp->channel;
channel 5867 dev/pci/pciide.c PDC268_INDEX(channel), index);
channel 5869 dev/pci/pciide.c PDC268_DATA(channel), value);
channel 5876 dev/pci/pciide.c int channel;
channel 5939 dev/pci/pciide.c for (channel = 0;
channel 5940 dev/pci/pciide.c channel < sc->sc_wdcdev.nchannels;
channel 5941 dev/pci/pciide.c channel++) {
channel 5944 dev/pci/pciide.c channel, pci_conf_read(sc->sc_pc, sc->sc_tag,
channel 5945 dev/pci/pciide.c PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp),
channel 5948 dev/pci/pciide.c PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp);
channel 5951 dev/pci/pciide.c channel, pci_conf_read(sc->sc_pc, sc->sc_tag,
channel 5952 dev/pci/pciide.c PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE);
channel 5954 dev/pci/pciide.c PDC2xx_TIM(channel, 1), mode);
channel 5989 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
channel 5990 dev/pci/pciide.c cp = &sc->pciide_channels[channel];
channel 5991 dev/pci/pciide.c if (pciide_chansetup(sc, channel, interface) == 0)
channel 5994 dev/pci/pciide.c PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) {
channel 5999 dev/pci/pciide.c pciide_map_compat_intr(pa, cp, channel, interface);
channel 6009 dev/pci/pciide.c pciide_unmap_compat_intr(pa, cp, channel, interface);
channel 6014 dev/pci/pciide.c PDC262_STATE_EN(channel):PDC246_STATE_EN(channel));
channel 6015 dev/pci/pciide.c pciide_unmap_compat_intr(pa, cp, channel, interface);
channel 6039 dev/pci/pciide.c int channel = chp->channel;
channel 6056 dev/pci/pciide.c if ((st & PDC262_STATE_80P(channel)) != 0 &&
channel 6062 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, channel),
channel 6084 dev/pci/pciide.c scr |= PDC262_U66_EN(channel);
channel 6086 dev/pci/pciide.c scr &= ~PDC262_U66_EN(channel);
channel 6090 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, channel,
channel 6092 dev/pci/pciide.c PDC262_ATAPI(channel))), DEBUG_PROBE);
channel 6105 dev/pci/pciide.c PDC262_ATAPI(channel), atapi);
channel 6147 dev/pci/pciide.c chp->channel, drive, mode), DEBUG_PROBE);
channel 6149 dev/pci/pciide.c PDC2xx_TIM(chp->channel, drive), mode);
channel 6154 dev/pci/pciide.c IDEDMA_CTL(channel), idedma_ctl);
channel 6167 dev/pci/pciide.c int channel = chp->channel;
channel 6190 dev/pci/pciide.c channel, drive), DEBUG_PROBE);
channel 6201 dev/pci/pciide.c IDEDMA_CTL(channel), idedma_ctl);
channel 6285 dev/pci/pciide.c pdc20262_dma_start(void *v, int channel, int drive)
channel 6289 dev/pci/pciide.c &sc->pciide_channels[channel].dma_maps[drive];
channel 6297 dev/pci/pciide.c PDC262_U66, clock | PDC262_U66_EN(channel));
channel 6302 dev/pci/pciide.c PDC262_ATAPI(channel), count);
channel 6305 dev/pci/pciide.c pciide_dma_start(v, channel, drive);
channel 6309 dev/pci/pciide.c pdc20262_dma_finish(void *v, int channel, int drive, int force)
channel 6313 dev/pci/pciide.c &sc->pciide_channels[channel].dma_maps[drive];
channel 6320 dev/pci/pciide.c PDC262_U66, clock & ~PDC262_U66_EN(channel));
channel 6322 dev/pci/pciide.c PDC262_ATAPI(channel), 0);
channel 6325 dev/pci/pciide.c return (pciide_dma_finish(v, channel, drive, force));
channel 6334 dev/pci/pciide.c int channel, i;
channel 6473 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels;
channel 6474 dev/pci/pciide.c channel++) {
channel 6475 dev/pci/pciide.c cp = &sc->pciide_channels[channel];
channel 6476 dev/pci/pciide.c sc->wdc_chanarray[channel] = &cp->wdc_channel;
channel 6480 dev/pci/pciide.c cp->wdc_channel.channel = channel;
channel 6487 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, channel);
channel 6492 dev/pci/pciide.c ps->regs[channel].ctl_iot = ps->ba5_st;
channel 6493 dev/pci/pciide.c ps->regs[channel].cmd_iot = ps->ba5_st;
channel 6496 dev/pci/pciide.c 0x0238 + (channel << 7), 1,
channel 6497 dev/pci/pciide.c &ps->regs[channel].ctl_ioh) != 0) {
channel 6500 dev/pci/pciide.c channel);
channel 6505 dev/pci/pciide.c 0x0200 + (i << 2) + (channel << 7), i == 0 ? 4 : 1,
channel 6506 dev/pci/pciide.c &ps->regs[channel].cmd_iohs[i]) != 0) {
channel 6510 dev/pci/pciide.c channel);
channel 6514 dev/pci/pciide.c ps->regs[channel].cmd_iohs[wdr_status & _WDC_REGMASK] =
channel 6515 dev/pci/pciide.c ps->regs[channel].cmd_iohs[wdr_command & _WDC_REGMASK];
channel 6516 dev/pci/pciide.c ps->regs[channel].cmd_iohs[wdr_features & _WDC_REGMASK] =
channel 6517 dev/pci/pciide.c ps->regs[channel].cmd_iohs[wdr_error & _WDC_REGMASK];
channel 6519 dev/pci/pciide.c ps->regs[channel].cmd_iot;
channel 6521 dev/pci/pciide.c ps->regs[channel].cmd_iohs[0];
channel 6531 dev/pci/pciide.c 0x260 + (channel << 7), 1,
channel 6532 dev/pci/pciide.c &ps->regs[channel].dma_iohs[IDEDMA_CMD(0)]) != 0) {
channel 6535 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, channel);
channel 6539 dev/pci/pciide.c 0x244 + (channel << 7), 4,
channel 6540 dev/pci/pciide.c &ps->regs[channel].dma_iohs[IDEDMA_TBL(0)]) != 0) {
channel 6543 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, channel);
channel 6549 dev/pci/pciide.c ps->regs[channel].dma_iohs[IDEDMA_CMD(0)], 0,
channel 6551 dev/pci/pciide.c ps->regs[channel].dma_iohs[IDEDMA_CMD(0)],
channel 6552 dev/pci/pciide.c 0) & ~0x00003f9f) | (channel + 1));
channel 6554 dev/pci/pciide.c (channel + 1) << 2, 0x00000001);
channel 6655 dev/pci/pciide.c int chan = chp->channel;
channel 6667 dev/pci/pciide.c pdc203xx_dma_start(void *v, int channel, int drive)
channel 6670 dev/pci/pciide.c struct pciide_channel *cp = &sc->pciide_channels[channel];
channel 6676 dev/pci/pciide.c ps->regs[channel].dma_iohs[IDEDMA_TBL(0)], 0,
channel 6681 dev/pci/pciide.c ps->regs[channel].dma_iohs[IDEDMA_CMD(0)], 0,
channel 6683 dev/pci/pciide.c ps->regs[channel].dma_iohs[IDEDMA_CMD(0)],
channel 6688 dev/pci/pciide.c pdc203xx_dma_finish(void *v, int channel, int drive, int force)
channel 6691 dev/pci/pciide.c struct pciide_channel *cp = &sc->pciide_channels[channel];
channel 6697 dev/pci/pciide.c ps->regs[channel].dma_iohs[IDEDMA_CMD(0)], 0,
channel 6699 dev/pci/pciide.c ps->regs[channel].dma_iohs[IDEDMA_CMD(0)],
channel 6721 dev/pci/pciide.c return (bus_space_read_1(ps->regs[chp->channel].ctl_iot,
channel 6722 dev/pci/pciide.c ps->regs[chp->channel].ctl_ioh, reg & _WDC_REGMASK));
channel 6724 dev/pci/pciide.c val = bus_space_read_1(ps->regs[chp->channel].cmd_iot,
channel 6725 dev/pci/pciide.c ps->regs[chp->channel].cmd_iohs[reg & _WDC_REGMASK], 0);
channel 6738 dev/pci/pciide.c bus_space_write_1(ps->regs[chp->channel].ctl_iot,
channel 6739 dev/pci/pciide.c ps->regs[chp->channel].ctl_ioh, reg & _WDC_REGMASK, val);
channel 6741 dev/pci/pciide.c bus_space_write_1(ps->regs[chp->channel].cmd_iot,
channel 6742 dev/pci/pciide.c ps->regs[chp->channel].cmd_iohs[reg & _WDC_REGMASK],
channel 6758 dev/pci/pciide.c SCONTROL_WRITE(ps, chp->channel, scontrol);
channel 6762 dev/pci/pciide.c SCONTROL_WRITE(ps, chp->channel, scontrol);
channel 6783 dev/pci/pciide.c SCONTROL_WRITE(ps, chp->channel, 0);
channel 6787 dev/pci/pciide.c SCONTROL_WRITE(ps,chp->channel,scontrol);
channel 6791 dev/pci/pciide.c SCONTROL_WRITE(ps,chp->channel,scontrol);
channel 6794 dev/pci/pciide.c sstatus = SSTATUS_READ(ps,chp->channel);
channel 6804 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel);
channel 6809 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel);
channel 6813 dev/pci/pciide.c iohs = ps->regs[chp->channel].cmd_iohs;
channel 6823 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel,
channel 6838 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel);
channel 6853 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus);
channel 6919 dev/pci/pciide.c int channel;
channel 6958 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
channel 6959 dev/pci/pciide.c cp = &sc->pciide_channels[channel];
channel 6960 dev/pci/pciide.c if (pciide_chansetup(sc, channel, interface) == 0)
channel 6962 dev/pci/pciide.c if (channel == 1 &&
channel 6968 dev/pci/pciide.c pciide_map_compat_intr(pa, cp, channel, interface);
channel 6974 dev/pci/pciide.c pciide_unmap_compat_intr(pa, cp, channel, interface);
channel 7070 dev/pci/pciide.c rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive);
channel 7071 dev/pci/pciide.c rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]);
channel 7088 dev/pci/pciide.c int channel;
channel 7127 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
channel 7128 dev/pci/pciide.c cp = &sc->pciide_channels[channel];
channel 7129 dev/pci/pciide.c if (pciide_chansetup(sc, channel, interface) == 0)
channel 7135 dev/pci/pciide.c pciide_map_compat_intr(pa, cp, channel, interface);
channel 7152 dev/pci/pciide.c int channel = chp->channel;
channel 7167 dev/pci/pciide.c pio_time &= ~(0xffff << (16 * channel));
channel 7168 dev/pci/pciide.c dma_time &= ~(0xffff << (16 * channel));
channel 7169 dev/pci/pciide.c pio_mode &= ~(0xff << (8 * channel + 16));
channel 7170 dev/pci/pciide.c udma_mode &= ~(0xff << (8 * channel + 16));
channel 7171 dev/pci/pciide.c udma_mode &= ~(3 << (2 * channel));
channel 7181 dev/pci/pciide.c unit = drive + 2 * channel;
channel 7191 dev/pci/pciide.c (1 << (14 + channel))) == 0) {
channel 7195 dev/pci/pciide.c channel, drive), DEBUG_PROBE);
channel 7223 dev/pci/pciide.c IDEDMA_CTL(channel), idedma_ctl);
channel 7263 dev/pci/pciide.c int channel;
channel 7330 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
channel 7331 dev/pci/pciide.c cp = &sc->pciide_channels[channel];
channel 7332 dev/pci/pciide.c if (pciide_chansetup(sc, channel, 0) == 0)
channel 7410 dev/pci/pciide.c (wdc_cp->channel << 8) + SVWSATA_TF0,
channel 7417 dev/pci/pciide.c (wdc_cp->channel << 8) + SVWSATA_TF8, 4,
channel 7434 dev/pci/pciide.c int channel = chp->channel;
channel 7458 dev/pci/pciide.c (channel << 8) + SVWSATA_SCONTROL, scontrol);
channel 7462 dev/pci/pciide.c (channel << 8) + SVWSATA_SCONTROL, scontrol);
channel 7466 dev/pci/pciide.c (channel << 8) + SVWSATA_SSTATUS);
channel 7469 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus,
channel 7471 dev/pci/pciide.c (channel << 8) + SVWSATA_SSTATUS));
channel 7481 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel);
channel 7486 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel);
channel 7520 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel,
channel 7535 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel);
channel 7549 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus);
channel 7674 dev/pci/pciide.c int channel = chp->channel;
channel 7685 dev/pci/pciide.c udma_mode &= ~ATP850_UDMA_MASK(channel);
channel 7688 dev/pci/pciide.c idetime &= ~ATP860_SETTIME_MASK(channel);
channel 7690 dev/pci/pciide.c udma_mode &= ~ATP860_UDMA_MASK(channel);
channel 7709 dev/pci/pciide.c udma_mode |= ATP850_UDMA_MODE(channel, drive,
channel 7712 dev/pci/pciide.c idetime |= ATP860_SETTIME(channel, drive,
channel 7715 dev/pci/pciide.c udma_mode |= ATP860_UDMA_MODE(channel, drive,
channel 7728 dev/pci/pciide.c idetime |= ATP860_SETTIME(channel, drive,
channel 7741 dev/pci/pciide.c idetime |= ATP860_SETTIME(channel, drive,
channel 7747 dev/pci/pciide.c | ATP8x0_CTRL_EN(channel));
channel 7754 dev/pci/pciide.c IDEDMA_CTL(channel), idedma_ctl);
channel 7760 dev/pci/pciide.c ATP850_IDETIME(channel), idetime);
channel 7772 dev/pci/pciide.c int channel;
channel 7806 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
channel 7807 dev/pci/pciide.c cp = &sc->pciide_channels[channel];
channel 7809 dev/pci/pciide.c if (pciide_chansetup(sc, channel, interface) == 0)
channel 7812 dev/pci/pciide.c if ((conf & NFORCE_CHAN_EN(channel)) == 0) {
channel 7818 dev/pci/pciide.c pciide_map_compat_intr(pa, cp, channel, interface);
channel 7824 dev/pci/pciide.c pciide_unmap_compat_intr(pa, cp, channel, interface);
channel 7829 dev/pci/pciide.c conf &= ~NFORCE_CHAN_EN(channel);
channel 7830 dev/pci/pciide.c pciide_unmap_compat_intr(pa, cp, channel, interface);
channel 7849 dev/pci/pciide.c int channel = chp->channel;
channel 7865 dev/pci/pciide.c piodmatim &= ~NFORCE_PIODMATIM_MASK(channel);
channel 7866 dev/pci/pciide.c udmatim &= ~NFORCE_UDMATIM_MASK(channel);
channel 7881 dev/pci/pciide.c udmatim |= NFORCE_UDMATIM_SET(channel, drive,
channel 7883 dev/pci/pciide.c NFORCE_UDMA_EN(channel, drive) |
channel 7884 dev/pci/pciide.c NFORCE_UDMA_ENM(channel, drive);
channel 7913 dev/pci/pciide.c piodmatim |= NFORCE_PIODMATIM_SET(channel, drive,
channel 7920 dev/pci/pciide.c IDEDMA_CTL(channel), idedma_ctl);
channel 7971 dev/pci/pciide.c int channel;
channel 8004 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
channel 8005 dev/pci/pciide.c cp = &sc->pciide_channels[channel];
channel 8006 dev/pci/pciide.c if (pciide_chansetup(sc, channel, interface) == 0)
channel 8012 dev/pci/pciide.c pciide_map_compat_intr(pa, cp, channel, interface);
channel 8021 dev/pci/pciide.c int channel;
channel 8065 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
channel 8066 dev/pci/pciide.c cp = &sc->pciide_channels[channel];
channel 8068 dev/pci/pciide.c if (pciide_chansetup(sc, channel, interface) == 0)
channel 8091 dev/pci/pciide.c int channel = chp->channel;
channel 8097 dev/pci/pciide.c tim = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_TIM(channel));
channel 8099 dev/pci/pciide.c channel, tim), DEBUG_PROBE);
channel 8119 dev/pci/pciide.c modectl &= ~IT_MODE_DMA(channel, drive);
channel 8124 dev/pci/pciide.c (cfg & IT_CFG_CABLE(channel, drive)) == 0) {
channel 8129 dev/pci/pciide.c channel, drive), DEBUG_PROBE);
channel 8144 dev/pci/pciide.c modectl |= IT_MODE_DMA(channel, drive);
channel 8169 dev/pci/pciide.c cfg |= IT_CFG_IORDY(channel);
channel 8177 dev/pci/pciide.c pci_conf_write(sc->sc_pc, sc->sc_tag, IT_TIM(channel), tim);
channel 8182 dev/pci/pciide.c IDEDMA_CTL(channel), idedma_ctl);
channel 8192 dev/pci/pciide.c int channel;
channel 8216 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
channel 8217 dev/pci/pciide.c cp = &sc->pciide_channels[channel];
channel 8218 dev/pci/pciide.c if (pciide_chansetup(sc, channel, interface) == 0)
channel 8220 dev/pci/pciide.c pciide_map_compat_intr(pa, cp, channel, interface);
channel 8226 dev/pci/pciide.c pciide_unmap_compat_intr(pa, cp, channel, interface);
channel 8241 dev/pci/pciide.c int channel = chp->channel;
channel 8265 dev/pci/pciide.c IXP_UDMA_ENABLE(udma, chp->channel, drive);
channel 8266 dev/pci/pciide.c IXP_SET_MODE(udma, chp->channel, drive,
channel 8274 dev/pci/pciide.c IXP_UDMA_DISABLE(udma, chp->channel, drive);
channel 8275 dev/pci/pciide.c IXP_SET_TIMING(mdma_timing, chp->channel, drive,
channel 8300 dev/pci/pciide.c IXP_SET_MODE(pio, chp->channel, drive, drvp->PIO_mode);
channel 8301 dev/pci/pciide.c IXP_SET_TIMING(pio_timing, chp->channel, drive,
channel 8313 dev/pci/pciide.c IDEDMA_CTL(channel), idedma_ctl);
channel 8323 dev/pci/pciide.c int channel;
channel 8351 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
channel 8352 dev/pci/pciide.c cp = &sc->pciide_channels[channel];
channel 8354 dev/pci/pciide.c if (pciide_chansetup(sc, channel, interface) == 0)
channel 8358 dev/pci/pciide.c if ((conf & JMICRON_CHAN_EN(channel)) == 0) {
channel 8365 dev/pci/pciide.c pciide_map_compat_intr(pa, cp, channel, interface);
channel 8371 dev/pci/pciide.c pciide_unmap_compat_intr(pa, cp, channel, interface);
channel 8376 dev/pci/pciide.c conf &= ~JMICRON_CHAN_EN(channel);
channel 8377 dev/pci/pciide.c pciide_unmap_compat_intr(pa, cp, channel, interface);
channel 8396 dev/pci/pciide.c int channel = chp->channel;
channel 8457 dev/pci/pciide.c IDEDMA_CTL(channel), idedma_ctl);
channel 34 dev/pci/pciide_acard_reg.h #define ATP850_IDETIME(channel) (0x40 + (channel) * 4)
channel 39 dev/pci/pciide_acard_reg.h #define ATP860_SETTIME(channel, drive, act, rec) \
channel 41 dev/pci/pciide_acard_reg.h ((channel) * 16 + (drive) * 8))
channel 42 dev/pci/pciide_acard_reg.h #define ATP860_SETTIME_MASK(channel) (0xffff << ((channel) * 16))
channel 54 dev/pci/pciide_acard_reg.h #define ATP850_UDMA_MODE(channel, drive, x) \
channel 55 dev/pci/pciide_acard_reg.h (((x) & 0x3) << ((channel) * 4 + (drive) * 2))
channel 56 dev/pci/pciide_acard_reg.h #define ATP860_UDMA_MODE(channel, drive, x) \
channel 57 dev/pci/pciide_acard_reg.h (((x) & 0xf) << ((channel) * 8 + (drive) * 4))
channel 58 dev/pci/pciide_acard_reg.h #define ATP850_UDMA_MASK(channel) (0xf << ((channel) * 4))
channel 59 dev/pci/pciide_acard_reg.h #define ATP860_UDMA_MASK(channel) (0xff << ((channel) * 8))
channel 90 dev/pci/pciide_acer_reg.h #define ACER_CHIDS_DRV(channel) ((0x4) << (channel))
channel 91 dev/pci/pciide_acer_reg.h #define ACER_CHIDS_INT(channel) ((0x1) << (channel))
channel 67 dev/pci/pciide_amd_reg.h #define AMD756_DATATIM_MASK(channel) (0xffff << ((1 - (channel)) << 4))
channel 68 dev/pci/pciide_amd_reg.h #define AMD756_DATATIM_RECOV(channel, drive, x) (((x) & 0xf) << \
channel 69 dev/pci/pciide_amd_reg.h (((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
channel 70 dev/pci/pciide_amd_reg.h #define AMD756_DATATIM_PULSE(channel, drive, x) (((x) & 0xf) << \
channel 71 dev/pci/pciide_amd_reg.h (((1 - (channel)) << 4) + ((1 - (drive)) << 3) + 4))
channel 78 dev/pci/pciide_amd_reg.h #define AMD756_UDMA_MASK(channel) (0xffff << ((1 - (channel)) << 4))
channel 79 dev/pci/pciide_amd_reg.h #define AMD756_UDMA_TIME(channel, drive, x) (((x) & 0x7) << \
channel 80 dev/pci/pciide_amd_reg.h (((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
channel 81 dev/pci/pciide_amd_reg.h #define AMD756_UDMA_EN(channel, drive) (0x40 << \
channel 82 dev/pci/pciide_amd_reg.h (((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
channel 83 dev/pci/pciide_amd_reg.h #define AMD756_UDMA_EN_MTH(channel, drive) (0x80 << \
channel 84 dev/pci/pciide_amd_reg.h (((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
channel 53 dev/pci/pciide_apollo_reg.h #define APO_IDECONF_EN(channel) (0x00000001 << (1 - (channel)))
channel 58 dev/pci/pciide_apollo_reg.h #define APO_IDECONF_WR_BUFF_EN(channel) (0x00001000 << ((1 - (channel)) << 1))
channel 59 dev/pci/pciide_apollo_reg.h #define APO_IDECONF_RD_PREF_EN(channel) (0x00002000 << ((1 - (channel)) << 1))
channel 62 dev/pci/pciide_apollo_reg.h #define APO_IDECONF_IO_NAT(channel) \
channel 63 dev/pci/pciide_apollo_reg.h (0x00400000 << (1 - (channel))) /* 580 only */
channel 64 dev/pci/pciide_apollo_reg.h #define APO_IDECONF_FIFO_TRSH(channel, x) \
channel 65 dev/pci/pciide_apollo_reg.h ((x) & 0x3) << ((1 - (channel)) << 1 + 24)
channel 76 dev/pci/pciide_apollo_reg.h #define APO_CTLMISC_FIFO_FLSH_RD(channel) (0x00100000 << (1 - (channel)))
channel 77 dev/pci/pciide_apollo_reg.h #define APO_CTLMISC_FIFO_FLSH_DMA(channel) (0x00400000 << (1 - (channel)))
channel 81 dev/pci/pciide_apollo_reg.h #define APO_DATATIM_MASK(channel) (0xffff << ((1 - (channel)) << 4))
channel 82 dev/pci/pciide_apollo_reg.h #define APO_DATATIM_RECOV(channel, drive, x) (((x) & 0xf) << \
channel 83 dev/pci/pciide_apollo_reg.h (((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
channel 84 dev/pci/pciide_apollo_reg.h #define APO_DATATIM_PULSE(channel, drive, x) (((x) & 0xf) << \
channel 85 dev/pci/pciide_apollo_reg.h (((1 - (channel)) << 4) + ((1 - (drive)) << 3) + 4))
channel 92 dev/pci/pciide_apollo_reg.h #define APO_UDMA_MASK(channel) (0xffff << ((1 - (channel)) << 4))
channel 93 dev/pci/pciide_apollo_reg.h #define APO_UDMA_TIME(channel, drive, x) (((x) & 0xf) << \
channel 94 dev/pci/pciide_apollo_reg.h (((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
channel 95 dev/pci/pciide_apollo_reg.h #define APO_UDMA_PIO_MODE(channel, drive) (0x20 << \
channel 96 dev/pci/pciide_apollo_reg.h (((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
channel 97 dev/pci/pciide_apollo_reg.h #define APO_UDMA_EN(channel, drive) (0x40 << \
channel 98 dev/pci/pciide_apollo_reg.h (((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
channel 99 dev/pci/pciide_apollo_reg.h #define APO_UDMA_EN_MTH(channel, drive) (0x80 << \
channel 100 dev/pci/pciide_apollo_reg.h (((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
channel 101 dev/pci/pciide_apollo_reg.h #define APO_UDMA_CLK66(channel) (0x08 << ((1 - (channel)) << 4))
channel 98 dev/pci/pciide_cmd_reg.h #define CMD_UDMATIM(channel) (0x73 + (8 * (channel)))
channel 51 dev/pci/pciide_pdc202xx_reg.h #define PDC246_STATE_LBA(channel) (0x0100 << (channel))
channel 53 dev/pci/pciide_pdc202xx_reg.h #define PDC246_STATE_EN(channel) (0x0002 << (channel))
channel 59 dev/pci/pciide_pdc202xx_reg.h #define PDC2xx_TIM(channel, drive) (0x60 + 4 * (drive) + 8 * (channel))
channel 85 dev/pci/pciide_pdc202xx_reg.h #define PDC2xx_SCR_EMPTY(channel) (0x00000100 << (4 * channel))
channel 86 dev/pci/pciide_pdc202xx_reg.h #define PDC2xx_SCR_FULL(channel) (0x00000200 << (4 * channel))
channel 87 dev/pci/pciide_pdc202xx_reg.h #define PDC2xx_SCR_INT(channel) (0x00000400 << (4 * channel))
channel 88 dev/pci/pciide_pdc202xx_reg.h #define PDC2xx_SCR_ERR(channel) (0x00000800 << (4 * channel))
channel 147 dev/pci/pciide_pdc202xx_reg.h #define SCONTROL_WRITE(ps,channel,scontrol) \
channel 149 dev/pci/pciide_pdc202xx_reg.h PDC205_SCONTROL(channel), scontrol)
channel 151 dev/pci/pciide_pdc202xx_reg.h #define SSTATUS_READ(sc,channel) \
channel 153 dev/pci/pciide_pdc202xx_reg.h PDC205_SSTATUS(channel))
channel 60 dev/pci/pciide_piix_reg.h #define PIIX_IDETIM_READ(x, channel) (((x) >> (16 * (channel))) & 0x0000FFFF)
channel 61 dev/pci/pciide_piix_reg.h #define PIIX_IDETIM_SET(x, bytes, channel) \
channel 62 dev/pci/pciide_piix_reg.h ((x) | ((bytes) << (16 * (channel))))
channel 63 dev/pci/pciide_piix_reg.h #define PIIX_IDETIM_CLEAR(x, bytes, channel) \
channel 64 dev/pci/pciide_piix_reg.h ((x) & ~((bytes) << (16 * (channel))))
channel 84 dev/pci/pciide_piix_reg.h #define PIIX_SIDETIM_ISP_MASK(channel) (0x0c << ((channel) * 4))
channel 86 dev/pci/pciide_piix_reg.h #define PIIX_SIDETIM_ISP_SET(x, channel) \
channel 87 dev/pci/pciide_piix_reg.h (x << (PIIX_SIDETIM_ISP_SHIFT + ((channel) * 4)))
channel 88 dev/pci/pciide_piix_reg.h #define PIIX_SIDETIM_RTC_MASK(channel) (0x03 << ((channel) * 4))
channel 90 dev/pci/pciide_piix_reg.h #define PIIX_SIDETIM_RTC_SET(x, channel) \
channel 91 dev/pci/pciide_piix_reg.h (x << (PIIX_SIDETIM_RTC_SHIFT + ((channel) * 4)))
channel 98 dev/pci/pciide_piix_reg.h #define PIIX_UDMACTL_DRV_EN(channel, drive) (0x01 << ((channel) * 2 + (drive)))
channel 101 dev/pci/pciide_piix_reg.h #define PIIX_UDMATIM_SET(x, channel, drive) \
channel 102 dev/pci/pciide_piix_reg.h (((x) << ((channel * 8) + (drive * 4))) << PIIX_UDMATIM_SHIFT)
channel 110 dev/pci/pciide_piix_reg.h #define PIIX_CONFIG_CR(channel, drive) (0x0010 << ((channel) * 2 + (drive)))
channel 111 dev/pci/pciide_piix_reg.h #define PIIX_CONFIG_UDMA66(channel, drive) (0x0001 << ((channel) * 2 + (drive)))
channel 113 dev/pci/pciide_piix_reg.h #define PIIX_CONFIG_UDMA100(channel, drive) (0x1000 << ((channel) * 2 + (drive)))
channel 44 dev/pci/pciide_sis_reg.h #define SIS_TIM(channel) (0x40 + (channel * 4))
channel 59 dev/pci/pciide_sis_reg.h #define SIS_TIM133(reg57, channel, drive) \
channel 60 dev/pci/pciide_sis_reg.h ((((reg57) & 0x40) ? 0x70 : 0x40) + ((channel) << 3) + ((drive) << 2))
channel 90 dev/pci/pciide_sis_reg.h #define SIS_REG_CBL_33(channel) (0x10 << (channel))
channel 91 dev/pci/pciide_sis_reg.h #define SIS96x_REG_CBL(channel) (0x51 + (channel) * 2)
channel 394 dev/pcmcia/if_malo.c nr->nr_channel = sc->sc_net[i].channel;
channel 1095 dev/pcmcia/if_malo.c chan = sc->sc_net[sc->sc_net_cur].channel;
channel 1346 dev/pcmcia/if_malo.c sc->sc_net[pos].channel = *(uint8_t *)(buf + i);
channel 1347 dev/pcmcia/if_malo.c DPRINTF(2, "chnl=%d\n", sc->sc_net[pos].channel);
channel 1535 dev/pcmcia/if_malo.c cmalo_cmd_set_channel(struct malo_softc *sc, uint16_t channel)
channel 1551 dev/pcmcia/if_malo.c body->channel = htole16(channel);
channel 1695 dev/pcmcia/if_malo.c bcopy(&sc->sc_net[sc->sc_net_cur].channel, body_phy->data, 1);
channel 142 dev/pcmcia/if_malovar.h uint16_t channel;
channel 322 dev/pcmcia/if_malovar.h uint8_t channel;
channel 353 dev/pcmcia/wdc_pcmcia.c sc->wdc_channel.channel = 0;
channel 246 dev/sbus/magma.c cd1400_enable_transmitter(struct cd1400 *cd, int channel)
channel 251 dev/sbus/magma.c CD1400_WRITE_REG(cd, CD1400_CAR, channel);
channel 769 dev/sbus/spif.c u_int8_t channel, *ptr;
channel 771 dev/sbus/spif.c channel = CD180_GSCR_CHANNEL(STC_READ(sc, STC_GSCR1));
channel 772 dev/sbus/spif.c sp = &sc->sc_ttys->sc_port[channel];
channel 796 dev/sbus/spif.c u_int8_t channel, *ptr, cnt, rcsr;
channel 799 dev/sbus/spif.c channel = CD180_GSCR_CHANNEL(STC_READ(sc, STC_GSCR1));
channel 800 dev/sbus/spif.c sp = &sc->sc_ttys->sc_port[channel];
channel 831 dev/sbus/spif.c u_int8_t channel, ch;
channel 834 dev/sbus/spif.c channel = CD180_GSCR_CHANNEL(STC_READ(sc, STC_GSCR1));
channel 835 dev/sbus/spif.c sp = &sc->sc_ttys->sc_port[channel];
channel 884 dev/sbus/spif.c u_int8_t channel, mcr;
channel 886 dev/sbus/spif.c channel = CD180_GSCR_CHANNEL(STC_READ(sc, STC_GSCR1));
channel 887 dev/sbus/spif.c sp = &sc->sc_ttys->sc_port[channel];
channel 811 dev/usb/if_atu.c join.channel = ieee80211_chan2ieee(&sc->sc_ic, node->ni_chan);
channel 1261 dev/usb/if_atu.c u_int8_t mode, channel;
channel 1349 dev/usb/if_atu.c err = atu_get_mib(sc, MIB_PHY__CHANNEL, &channel);
channel 352 dev/usb/if_atureg.h uByte channel;
channel 327 net80211/ieee80211.h u_int8_t channel;
channel 222 netbt/rfcomm.h #define RFCOMM_MKDLCI(dir, channel) ((((channel) & 0x1f) << 1) | (dir))
channel 215 sys/midiio.h int32_t channel;