1 /* $OpenBSD: pciide_apollo_reg.h,v 1.9 2004/09/24 07:38:38 grange Exp $ */
2 /* $NetBSD: pciide_apollo_reg.h,v 1.8 2001/01/05 18:04:43 bouyer Exp $ */
3
4 /*
5 * Copyright (c) 1998 Manuel Bouyer.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Manuel Bouyer.
18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35 #ifndef _DEV_PCI_PCIIDE_APOLLO_REG_H_
36 #define _DEV_PCI_PCIIDE_APOLLO_REG_H_
37
38 /*
39 * Registers definitions for VIA technologies's Apollo controllers (VT82V580VO,
40 * VT82C586A and VT82C586B).
41 *
42 * UDMA1/2/3/4 capable
43 * http://www.via.com.tw/pdf/productinfo/686a.pdf
44 * http://www.via.com.tw/pdf/productinfo/596b.pdf
45 *
46 * UDMA1/2 capable
47 * http://www.via.com.tw/pdf/productinfo/586b.pdf
48 * http://www.via.com.tw/pdf/productinfo/586a.pdf
49 */
50
51 /* misc. configuration registers */
52 #define APO_IDECONF 0x40
53 #define APO_IDECONF_EN(channel) (0x00000001 << (1 - (channel)))
54 #define APO_IDECONF_SERR_EN 0x00000100 /* 580 only */
55 #define APO_IDECONF_DS_SOURCE 0x00000200 /* 580 only */
56 #define APO_IDECONF_ALT_INTR_EN 0x00000400 /* 580 only */
57 #define APO_IDECONF_PERR_EN 0x00000800 /* 580 only */
58 #define APO_IDECONF_WR_BUFF_EN(channel) (0x00001000 << ((1 - (channel)) << 1))
59 #define APO_IDECONF_RD_PREF_EN(channel) (0x00002000 << ((1 - (channel)) << 1))
60 #define APO_IDECONF_DEVSEL_TME 0x00010000 /* 580 only */
61 #define APO_IDECONF_MAS_CMD_MON 0x00020000 /* 580 only */
62 #define APO_IDECONF_IO_NAT(channel) \
63 (0x00400000 << (1 - (channel))) /* 580 only */
64 #define APO_IDECONF_FIFO_TRSH(channel, x) \
65 ((x) & 0x3) << ((1 - (channel)) << 1 + 24)
66 #define APO_IDECONF_FIFO_CONF_MASK 0x60000000
67
68 /* Misc. controls register */
69 #define APO_CTLMISC 0x44
70 #define APO_CTLMISC_BM_STS_RTY 0x00000008
71 #define APO_CTLMISC_FIFO_HWS 0x00000010
72 #define APO_CTLMISC_WR_IRDY_WS 0x00000020
73 #define APO_CTLMISC_RD_IRDY_WS 0x00000040
74 #define APO_CTLMISC_INTR_SWP 0x00004000
75 #define APO_CTLMISC_DRDY_TIME_MASK 0x00030000
76 #define APO_CTLMISC_FIFO_FLSH_RD(channel) (0x00100000 << (1 - (channel)))
77 #define APO_CTLMISC_FIFO_FLSH_DMA(channel) (0x00400000 << (1 - (channel)))
78
79 /* data port timings controls */
80 #define APO_DATATIM 0x48
81 #define APO_DATATIM_MASK(channel) (0xffff << ((1 - (channel)) << 4))
82 #define APO_DATATIM_RECOV(channel, drive, x) (((x) & 0xf) << \
83 (((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
84 #define APO_DATATIM_PULSE(channel, drive, x) (((x) & 0xf) << \
85 (((1 - (channel)) << 4) + ((1 - (drive)) << 3) + 4))
86
87 /* misc timings control */
88 #define APO_MISCTIM 0x4c
89
90 /* UltraDMA control (586A/B and higher only) */
91 #define APO_UDMA 0x50
92 #define APO_UDMA_MASK(channel) (0xffff << ((1 - (channel)) << 4))
93 #define APO_UDMA_TIME(channel, drive, x) (((x) & 0xf) << \
94 (((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
95 #define APO_UDMA_PIO_MODE(channel, drive) (0x20 << \
96 (((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
97 #define APO_UDMA_EN(channel, drive) (0x40 << \
98 (((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
99 #define APO_UDMA_EN_MTH(channel, drive) (0x80 << \
100 (((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
101 #define APO_UDMA_CLK66(channel) (0x08 << ((1 - (channel)) << 4))
102
103 static int8_t apollo_udma133_tim[] = {0x07, 0x07, 0x06, 0x04, 0x02, 0x01, 0x00};
104 static int8_t apollo_udma100_tim[] = {0x07, 0x07, 0x04, 0x02, 0x01, 0x00};
105 static int8_t apollo_udma66_tim[] = {0x03, 0x03, 0x02, 0x01, 0x00};
106 static int8_t apollo_udma33_tim[] = {0x03, 0x02, 0x00};
107 static int8_t apollo_pio_set[] = {0x0a, 0x0a, 0x0a, 0x02, 0x02};
108 static int8_t apollo_pio_rec[] = {0x08, 0x08, 0x08, 0x02, 0x00};
109
110 #endif /* !_DEV_PCI_PCIIDE_APOLLO_REG_H_ */