1 /* $OpenBSD: aic79xx.h,v 1.21 2006/12/21 02:28:47 krw Exp $ */
2
3 /*
4 * Copyright (c) 2004 Milos Urbanek, Kenneth R. Westerback & Marco Peereboom
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE FOR
20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 */
29
30 /*
31 * Core definitions and data structures shareable across OS platforms.
32 *
33 * Copyright (c) 1994-2002 Justin T. Gibbs.
34 * Copyright (c) 2000-2002 Adaptec Inc.
35 * All rights reserved.
36 *
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
39 * are met:
40 * 1. Redistributions of source code must retain the above copyright
41 * notice, this list of conditions, and the following disclaimer,
42 * without modification.
43 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
44 * substantially similar to the "NO WARRANTY" disclaimer below
45 * ("Disclaimer") and any redistribution must be conditioned upon
46 * including a substantially similar Disclaimer requirement for further
47 * binary redistribution.
48 * 3. Neither the names of the above-listed copyright holders nor the names
49 * of any contributors may be used to endorse or promote products derived
50 * from this software without specific prior written permission.
51 *
52 * Alternatively, this software may be distributed under the terms of the
53 * GNU General Public License ("GPL") version 2 as published by the Free
54 * Software Foundation.
55 *
56 * NO WARRANTY
57 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
58 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
59 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
60 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
61 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
62 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
63 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
64 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
65 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
66 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
67 * POSSIBILITY OF SUCH DAMAGES.
68 *
69 * Id: //depot/aic7xxx/aic7xxx/aic79xx.h#107
70 *
71 * FreeBSD: src/sys/dev/aic7xxx/aic79xx.h,v 1.23 2004/11/18 20:22:31 gibbs Exp
72 */
73
74 #ifndef _AIC79XX_H_
75 #define _AIC79XX_H_
76
77 /* #define AHD_DEBUG */
78
79 /* Register Definitions */
80 #include <dev/microcode/aic7xxx/aic79xx_reg.h>
81
82 #include <dev/ic/aic7xxx_cam.h>
83
84 /************************* Forward Declarations *******************************/
85 struct ahd_platform_data;
86 struct scb_platform_data;
87
88 /****************************** Useful Macros *********************************/
89 #ifndef MAX
90 #define MAX(a,b) (((a) > (b)) ? (a) : (b))
91 #endif
92
93 #ifndef MIN
94 #define MIN(a,b) (((a) < (b)) ? (a) : (b))
95 #endif
96
97 #ifndef TRUE
98 #define TRUE 1
99 #endif
100 #ifndef FALSE
101 #define FALSE 0
102 #endif
103
104 #define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array))
105
106 #define ALL_CHANNELS '\0'
107 #define ALL_TARGETS_MASK 0xFFFF
108 #define INITIATOR_WILDCARD (~0)
109 #define SCB_LIST_NULL 0xFF00
110 #define SCB_LIST_NULL_LE (aic_htole16(SCB_LIST_NULL))
111 #define QOUTFIFO_ENTRY_VALID 0x80
112 #define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL)
113
114 #define SCSIID_TARGET(ahd, scsiid) \
115 (((scsiid) & TID) >> TID_SHIFT)
116 #define SCSIID_OUR_ID(scsiid) \
117 ((scsiid) & OID)
118 #define SCSIID_CHANNEL(ahd, scsiid) ('A')
119 #define SCB_IS_SCSIBUS_B(ahd, scb) (0)
120 #define SCB_GET_OUR_ID(scb) \
121 SCSIID_OUR_ID((scb)->hscb->scsiid)
122 #define SCB_GET_TARGET(ahd, scb) \
123 SCSIID_TARGET((ahd), (scb)->hscb->scsiid)
124 #define SCB_GET_CHANNEL(ahd, scb) \
125 SCSIID_CHANNEL(ahd, (scb)->hscb->scsiid)
126 #define SCB_GET_LUN(scb) \
127 ((scb)->hscb->lun)
128 #define SCB_GET_TARGET_OFFSET(ahd, scb) \
129 SCB_GET_TARGET(ahd, scb)
130 #define SCB_GET_TARGET_MASK(ahd, scb) \
131 (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb)))
132 #ifdef AHD_DEBUG
133 #define SCB_IS_SILENT(scb) \
134 ((ahd_debug & AHD_SHOW_MASKED_ERRORS) == 0 \
135 && (((scb)->flags & SCB_SILENT) != 0))
136 #else
137 #define SCB_IS_SILENT(scb) \
138 (((scb)->flags & SCB_SILENT) != 0)
139 #endif
140 /*
141 * TCLs have the following format: TTTTLLLLLLLL
142 */
143 #define TCL_TARGET_OFFSET(tcl) \
144 ((((tcl) >> 4) & TID) >> 4)
145 #define TCL_LUN(tcl) \
146 (tcl & (AHD_NUM_LUNS - 1))
147 #define BUILD_TCL(scsiid, lun) \
148 ((lun) | (((scsiid) & TID) << 4))
149 #define BUILD_TCL_RAW(target, channel, lun) \
150 ((lun) | ((target) << 8))
151
152 #define SCB_GET_TAG(scb) \
153 aic_le16toh(scb->hscb->tag)
154
155 #ifndef AHD_TARGET_MODE
156 #undef AHD_TMODE_ENABLE
157 #define AHD_TMODE_ENABLE 0
158 #endif
159
160 #define AHD_BUILD_COL_IDX(target, lun) \
161 (((lun) << 4) | target)
162
163 #define AHD_GET_SCB_COL_IDX(ahd, scb) \
164 ((SCB_GET_LUN(scb) << 4) | SCB_GET_TARGET(ahd, scb))
165
166 #define AHD_SET_SCB_COL_IDX(scb, col_idx) \
167 do { \
168 (scb)->hscb->scsiid = ((col_idx) << TID_SHIFT) & TID; \
169 (scb)->hscb->lun = ((col_idx) >> 4) & (AHD_NUM_LUNS_NONPKT-1); \
170 } while (0)
171
172 #define AHD_COPY_SCB_COL_IDX(dst, src) \
173 do { \
174 dst->hscb->scsiid = src->hscb->scsiid; \
175 dst->hscb->lun = src->hscb->lun; \
176 } while (0)
177
178 #define AHD_NEVER_COL_IDX 0xFFFF
179
180 /**************************** Driver Constants ********************************/
181 /*
182 * The maximum number of supported targets.
183 */
184 #define AHD_NUM_TARGETS 16
185
186 /*
187 * The maximum number of supported luns.
188 * The identify message only supports 64 luns in non-packetized transfers.
189 * You can have 2^64 luns when information unit transfers are enabled,
190 * but until we see a need to support that many, we support 256.
191 */
192 #define AHD_NUM_LUNS_NONPKT 64
193 #define AHD_NUM_LUNS 256
194
195 /*
196 * The maximum transfer per S/G segment.
197 */
198 #define AHD_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */
199
200 /*
201 * The maximum amount of SCB storage in hardware on a controller.
202 * This value represents an upper bound. Due to software design,
203 * we may not be able to use this number.
204 */
205 #define AHD_SCB_MAX 512
206
207 /*
208 * The maximum number of concurrent transactions supported per driver instance.
209 * Sequencer Control Blocks (SCBs) store per-transaction information.
210 */
211 #define AHD_MAX_QUEUE AHD_SCB_MAX
212
213 /*
214 * Define the size of our QIN and QOUT FIFOs. They must be a power of 2
215 * in size and accommodate as many transactions as can be queued concurrently.
216 */
217 #define AHD_QIN_SIZE AHD_MAX_QUEUE
218 #define AHD_QOUT_SIZE AHD_MAX_QUEUE
219
220 #define AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1))
221 /*
222 * The maximum amount of SCB storage we allocate in host memory.
223 */
224 #define AHD_SCB_MAX_ALLOC AHD_MAX_QUEUE
225
226 /*
227 * Ring Buffer of incoming target commands.
228 * We allocate 256 to simplify the logic in the sequencer
229 * by using the natural wrap point of an 8bit counter.
230 */
231 #define AHD_TMODE_CMDS 256
232
233 /* Reset line assertion time in us */
234 #define AHD_BUSRESET_DELAY 25
235
236 /******************* Chip Characteristics/Operating Settings *****************/
237 extern uint32_t ahd_attach_to_HostRAID_controllers;
238
239 /*
240 * Chip Type
241 * The chip order is from least sophisticated to most sophisticated.
242 */
243 typedef enum {
244 AHD_NONE = 0x0000,
245 AHD_CHIPID_MASK = 0x00FF,
246 AHD_AIC7901 = 0x0001,
247 AHD_AIC7902 = 0x0002,
248 AHD_AIC7901A = 0x0003,
249 AHD_PCI = 0x0100, /* Bus type PCI */
250 AHD_PCIX = 0x0200, /* Bus type PCIX */
251 AHD_BUS_MASK = 0x0F00
252 } ahd_chip;
253
254 /*
255 * Features available in each chip type.
256 */
257 typedef enum {
258 AHD_FENONE = 0x00000,
259 AHD_WIDE = 0x00001,/* Wide Channel */
260 AHD_MULTI_FUNC = 0x00100,/* Multi-Function/Channel Device */
261 AHD_TARGETMODE = 0x01000,/* Has tested target mode support */
262 AHD_MULTIROLE = 0x02000,/* Space for two roles at a time */
263 AHD_RTI = 0x04000,/* Retained Training Support */
264 AHD_NEW_IOCELL_OPTS = 0x08000,/* More Signal knobs in the IOCELL */
265 AHD_NEW_DFCNTRL_OPTS = 0x10000,/* SCSIENWRDIS bit */
266 AHD_FAST_CDB_DELIVERY = 0x20000,/* CDB acks released to Output Sync */
267 AHD_REMOVABLE = 0x00000,/* Hot-Swap supported - None so far*/
268 AHD_AIC7901_FE = AHD_FENONE,
269 AHD_AIC7901A_FE = AHD_FENONE,
270 AHD_AIC7902_FE = AHD_MULTI_FUNC
271 } ahd_feature;
272
273 /*
274 * Bugs in the silicon that we work around in software.
275 */
276 typedef enum {
277 AHD_BUGNONE = 0x0000,
278 /*
279 * Rev A hardware fails to update LAST/CURR/NEXTSCB
280 * correctly in certain packetized selection cases.
281 */
282 AHD_SENT_SCB_UPDATE_BUG = 0x0001,
283 /* The wrong SCB is accessed to check the abort pending bit. */
284 AHD_ABORT_LQI_BUG = 0x0002,
285 /* Packetized bitbucket crosses packet boundaries. */
286 AHD_PKT_BITBUCKET_BUG = 0x0004,
287 /* The selection timer runs twice as long as its setting. */
288 AHD_LONG_SETIMO_BUG = 0x0008,
289 /* The Non-LQ CRC error status is delayed until phase change. */
290 AHD_NLQICRC_DELAYED_BUG = 0x0010,
291 /* The chip must be reset for all outgoing bus resets. */
292 AHD_SCSIRST_BUG = 0x0020,
293 /* Some PCIX fields must be saved and restored across chip reset. */
294 AHD_PCIX_CHIPRST_BUG = 0x0040,
295 /* MMAPIO is not functional in PCI-X mode. */
296 AHD_PCIX_MMAPIO_BUG = 0x0080,
297 /* Reads to SCBRAM fail to reset the discard timer. */
298 AHD_PCIX_SCBRAM_RD_BUG = 0x0100,
299 /* Bug workarounds that can be disabled on non-PCIX busses. */
300 AHD_PCIX_BUG_MASK = AHD_PCIX_CHIPRST_BUG
301 | AHD_PCIX_MMAPIO_BUG
302 | AHD_PCIX_SCBRAM_RD_BUG,
303 /*
304 * LQOSTOP0 status set even for forced selections with ATN
305 * to perform non-packetized message delivery.
306 */
307 AHD_LQO_ATNO_BUG = 0x0200,
308 /* FIFO auto-flush does not always trigger. */
309 AHD_AUTOFLUSH_BUG = 0x0400,
310 /* The CLRLQO registers are not self-clearing. */
311 AHD_CLRLQO_AUTOCLR_BUG = 0x0800,
312 /* The PACKETIZED status bit refers to the previous connection. */
313 AHD_PKTIZED_STATUS_BUG = 0x1000,
314 /* "Short Luns" are not placed into outgoing LQ packets correctly. */
315 AHD_PKT_LUN_BUG = 0x2000,
316 /*
317 * Only the FIFO allocated to the non-packetized connection may
318 * be in use during a non-packetzied connection.
319 */
320 AHD_NONPACKFIFO_BUG = 0x4000,
321 /*
322 * Writing to a DFF SCBPTR register may fail if concurent with
323 * a hardware write to the other DFF SCBPTR register. This is
324 * not currently a concern in our sequencer since all chips with
325 * this bug have the AHD_NONPACKFIFO_BUG and all writes of concern
326 * occur in non-packetized connections.
327 */
328 AHD_MDFF_WSCBPTR_BUG = 0x8000,
329 /* SGHADDR updates are slow. */
330 AHD_REG_SLOW_SETTLE_BUG = 0x10000,
331 /*
332 * Changing the MODE_PTR coincident with an interrupt that
333 * switches to a different mode will cause the interrupt to
334 * be in the mode written outside of interrupt context.
335 */
336 AHD_SET_MODE_BUG = 0x20000,
337 /* Non-packetized busfree revision does not work. */
338 AHD_BUSFREEREV_BUG = 0x40000,
339 /*
340 * Paced transfers are indicated with a non-standard PPR
341 * option bit in the neg table, 160MHz is indicated by
342 * sync factor 0x7, and the offset if off by a factor of 2.
343 */
344 AHD_PACED_NEGTABLE_BUG = 0x80000,
345 /* LQOOVERRUN false positives. */
346 AHD_LQOOVERRUN_BUG = 0x100000,
347 /*
348 * Controller write to INTSTAT will lose to a host
349 * write to CLRINT.
350 */
351 AHD_INTCOLLISION_BUG = 0x200000,
352 /*
353 * The GEM318 violates the SCSI spec by not waiting
354 * the mandated bus settle delay between phase changes
355 * in some situations. Some aic79xx chip revs. are more
356 * strict in this regard and will treat REQ assertions
357 * that fall within the bus settle delay window as
358 * glitches. This flag tells the firmware to tolerate
359 * early REQ assertions.
360 */
361 AHD_EARLY_REQ_BUG = 0x400000,
362 /*
363 * The LED does not stay on long enough in packetized modes.
364 */
365 AHD_FAINT_LED_BUG = 0x800000
366 } ahd_bug;
367
368 /*
369 * Configuration specific settings.
370 * The driver determines these settings by probing the
371 * chip/controller's configuration.
372 */
373 typedef enum {
374 AHD_FNONE = 0x00000,
375 AHD_BOOT_CHANNEL = 0x00001,/* We were set as the boot channel. */
376 AHD_USEDEFAULTS = 0x00004,/*
377 * For cards without an seeprom
378 * or a BIOS to initialize the chip's
379 * SRAM, we use the default target
380 * settings.
381 */
382 AHD_SEQUENCER_DEBUG = 0x00008,
383 AHD_RESET_BUS_A = 0x00010,
384 AHD_EXTENDED_TRANS_A = 0x00020,
385 AHD_TERM_ENB_A = 0x00040,
386 AHD_SPCHK_ENB_A = 0x00080,
387 AHD_STPWLEVEL_A = 0x00100,
388 AHD_INITIATORROLE = 0x00200,/*
389 * Allow initiator operations on
390 * this controller.
391 */
392 AHD_TARGETROLE = 0x00400,/*
393 * Allow target operations on this
394 * controller.
395 */
396 AHD_RESOURCE_SHORTAGE = 0x00800,
397 AHD_TQINFIFO_BLOCKED = 0x01000,/* Blocked waiting for ATIOs */
398 AHD_INT50_SPEEDFLEX = 0x02000,/*
399 * Internal 50pin connector
400 * sits behind an aic3860
401 */
402 AHD_BIOS_ENABLED = 0x04000,
403 AHD_ALL_INTERRUPTS = 0x08000,
404 AHD_39BIT_ADDRESSING = 0x10000,/* Use 39 bit addressing scheme. */
405 AHD_64BIT_ADDRESSING = 0x20000,/* Use 64 bit addressing scheme. */
406 AHD_CURRENT_SENSING = 0x40000,
407 AHD_SCB_CONFIG_USED = 0x80000,/* No SEEPROM but SCB had info. */
408 AHD_HP_BOARD = 0x100000,
409 AHD_RESET_POLL_ACTIVE = 0x200000,
410 AHD_UPDATE_PEND_CMDS = 0x400000,
411 AHD_RUNNING_QOUTFIFO = 0x800000,
412 AHD_HAD_FIRST_SEL = 0x1000000,
413 AHD_SHUTDOWN_RECOVERY = 0x2000000, /* Terminate recovery thread. */
414 AHD_HOSTRAID_BOARD = 0x4000000
415 } ahd_flag;
416
417 /************************* Hardware SCB Definition ***************************/
418
419 /*
420 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB
421 * consists of a "hardware SCB" mirroring the fields available on the card
422 * and additional information the kernel stores for each transaction.
423 *
424 * To minimize space utilization, a portion of the hardware scb stores
425 * different data during different portions of a SCSI transaction.
426 * As initialized by the host driver for the initiator role, this area
427 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After
428 * the cdb has been presented to the target, this area serves to store
429 * residual transfer information and the SCSI status byte.
430 * For the target role, the contents of this area do not change, but
431 * still serve a different purpose than for the initiator role. See
432 * struct target_data for details.
433 */
434
435 /*
436 * Status information embedded in the shared poriton of
437 * an SCB after passing the cdb to the target. The kernel
438 * driver will only read this data for transactions that
439 * complete abnormally.
440 */
441 struct initiator_status {
442 uint32_t residual_datacnt; /* Residual in the current S/G seg */
443 uint32_t residual_sgptr; /* The next S/G for this transfer */
444 uint8_t scsi_status; /* Standard SCSI status byte */
445 };
446
447 struct target_status {
448 uint32_t residual_datacnt; /* Residual in the current S/G seg */
449 uint32_t residual_sgptr; /* The next S/G for this transfer */
450 uint8_t scsi_status; /* SCSI status to give to initiator */
451 uint8_t target_phases; /* Bitmap of phases to execute */
452 uint8_t data_phase; /* Data-In or Data-Out */
453 uint8_t initiator_tag; /* Initiator's transaction tag */
454 };
455
456 /*
457 * Initiator mode SCB shared data area.
458 * If the embedded CDB is 12 bytes or less, we embed
459 * the sense buffer address in the SCB. This allows
460 * us to retrieve sense information without interrupting
461 * the host in packetized mode.
462 */
463 typedef uint32_t sense_addr_t;
464 #define MAX_CDB_LEN 16
465 #define MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t))
466 union initiator_data {
467 struct {
468 uint64_t cdbptr;
469 uint8_t cdblen;
470 } cdb_from_host;
471 uint8_t cdb[MAX_CDB_LEN];
472 struct {
473 uint8_t cdb[MAX_CDB_LEN_WITH_SENSE_ADDR];
474 sense_addr_t sense_addr;
475 } cdb_plus_saddr;
476 };
477
478 /*
479 * Target mode version of the shared data SCB segment.
480 */
481 struct target_data {
482 uint32_t spare[2];
483 uint8_t scsi_status; /* SCSI status to give to initiator */
484 uint8_t target_phases; /* Bitmap of phases to execute */
485 uint8_t data_phase; /* Data-In or Data-Out */
486 uint8_t initiator_tag; /* Initiator's transaction tag */
487 };
488
489 struct hardware_scb {
490 /*0*/ union {
491 union initiator_data idata;
492 struct target_data tdata;
493 struct initiator_status istatus;
494 struct target_status tstatus;
495 } shared_data;
496 /*
497 * A word about residuals.
498 * The scb is presented to the sequencer with the dataptr and datacnt
499 * fields initialized to the contents of the first S/G element to
500 * transfer. The sgptr field is initialized to the bus address for
501 * the S/G element that follows the first in the in core S/G array
502 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid
503 * S/G entry for this transfer (single S/G element transfer with the
504 * first elements address and length preloaded in the dataptr/datacnt
505 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL.
506 * The SG_FULL_RESID flag ensures that the residual will be correctly
507 * noted even if no data transfers occur. Once the data phase is entered,
508 * the residual sgptr and datacnt are loaded from the sgptr and the
509 * datacnt fields. After each S/G element's dataptr and length are
510 * loaded into the hardware, the residual sgptr is advanced. After
511 * each S/G element is expired, its datacnt field is checked to see
512 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the
513 * residual sg ptr and the transfer is considered complete. If the
514 * sequencer determines that there is a residual in the transfer, or
515 * there is non-zero status, it will set the SG_STATUS_VALID flag in
516 * sgptr and dma the scb back into host memory. To sumarize:
517 *
518 * Sequencer:
519 * o A residual has occurred if SG_FULL_RESID is set in sgptr,
520 * or residual_sgptr does not have SG_LIST_NULL set.
521 *
522 * o We are transfering the last segment if residual_datacnt has
523 * the SG_LAST_SEG flag set.
524 *
525 * Host:
526 * o A residual can only have occurred if a completed scb has the
527 * SG_STATUS_VALID flag set. Inspection of the SCSI status field,
528 * the residual_datacnt, and the residual_sgptr field will tell
529 * for sure.
530 *
531 * o residual_sgptr and sgptr refer to the "next" sg entry
532 * and so may point beyond the last valid sg entry for the
533 * transfer.
534 */
535 #define SG_PTR_MASK 0xFFFFFFF8
536 /*16*/ uint16_t tag; /* Reused by Sequencer. */
537 /*18*/ uint8_t control; /* See SCB_CONTROL in aic79xx.reg for details */
538 /*19*/ uint8_t scsiid; /*
539 * Selection out Id
540 * Our Id (bits 0-3) Their ID (bits 4-7)
541 */
542 /*20*/ uint8_t lun;
543 /*21*/ uint8_t task_attribute;
544 /*22*/ uint8_t cdb_len;
545 /*23*/ uint8_t task_management;
546 /*24*/ uint64_t dataptr;
547 /*32*/ uint32_t datacnt; /* Byte 3 is spare. */
548 /*36*/ uint32_t sgptr;
549 /*40*/ uint32_t hscb_busaddr;
550 /*44*/ uint32_t next_hscb_busaddr;
551 /********** Long lun field only downloaded for full 8 byte lun support ********/
552 /*48*/ uint8_t pkt_long_lun[8];
553 /******* Fields below are not Downloaded (Sequencer may use for scratch) ******/
554 /*56*/ uint8_t spare[8];
555 };
556
557 /************************ Kernel SCB Definitions ******************************/
558 /*
559 * Some fields of the SCB are OS dependent. Here we collect the
560 * definitions for elements that all OS platforms need to include
561 * in there SCB definition.
562 */
563
564 /*
565 * Definition of a scatter/gather element as transfered to the controller.
566 * The aic7xxx chips only support a 24bit length. We use the top byte of
567 * the length to store additional address bits and a flag to indicate
568 * that a given segment terminates the transfer. This gives us an
569 * addressable range of 512GB on machines with 64bit PCI or with chips
570 * that can support dual address cycles on 32bit PCI busses.
571 */
572 struct ahd_dma_seg {
573 uint32_t addr;
574 uint32_t len;
575 #define AHD_DMA_LAST_SEG 0x80000000
576 #define AHD_SG_HIGH_ADDR_MASK 0x7F000000
577 #define AHD_SG_LEN_MASK 0x00FFFFFF
578 };
579
580 struct ahd_dma64_seg {
581 uint64_t addr;
582 uint32_t len;
583 uint32_t pad;
584 };
585
586 struct map_node {
587 bus_dmamap_t dmamap;
588 bus_addr_t busaddr;
589 uint8_t *vaddr;
590 bus_dma_segment_t dmaseg;
591 size_t size;
592 SLIST_ENTRY(map_node) links;
593 };
594
595 /*
596 * The current state of this SCB.
597 */
598 typedef enum {
599 SCB_FLAG_NONE = 0x00000,
600 SCB_TRANSMISSION_ERROR = 0x00001,/*
601 * We detected a parity or CRC
602 * error that has effected the
603 * payload of the command. This
604 * flag is checked when normal
605 * status is returned to catch
606 * the case of a target not
607 * responding to our attempt
608 * to report the error.
609 */
610 SCB_OTHERTCL_TIMEOUT = 0x00002,/*
611 * Another device was active
612 * during the first timeout for
613 * this SCB so we gave ourselves
614 * an additional timeout period
615 * in case it was hogging the
616 * bus.
617 */
618 SCB_DEVICE_RESET = 0x00004,
619 SCB_SENSE = 0x00008,
620 SCB_CDB32_PTR = 0x00010,
621 SCB_AUTO_NEGOTIATE = 0x00040,/* Negotiate to achieve goal. */
622 SCB_NEGOTIATE = 0x00080,/* Negotiation forced for command. */
623 SCB_ABORT = 0x00100,
624 SCB_ACTIVE = 0x00200,
625 SCB_TARGET_IMMEDIATE = 0x00400,
626 SCB_PACKETIZED = 0x00800,
627 SCB_EXPECT_PPR_BUSFREE = 0x01000,
628 SCB_PKT_SENSE = 0x02000,
629 SCB_CMDPHASE_ABORT = 0x04000,
630 SCB_ON_COL_LIST = 0x08000,
631 SCB_SILENT = 0x10000,/*
632 * Be quiet about transmission type
633 * errors. They are expected and we
634 * don't want to upset the user. This
635 * flag is typically used during DV.
636 */
637 } scb_flag;
638
639 struct scb {
640 struct hardware_scb *hscb;
641 union {
642 SLIST_ENTRY(scb) sle;
643 LIST_ENTRY(scb) le;
644 TAILQ_ENTRY(scb) tqe;
645 } links;
646 union {
647 SLIST_ENTRY(scb) sle;
648 LIST_ENTRY(scb) le;
649 TAILQ_ENTRY(scb) tqe;
650 } links2;
651 #define pending_links links2.le
652 #define collision_links links2.le
653 LIST_ENTRY(scb) timedout_links;
654 struct scb *col_scb;
655 struct scsi_xfer *xs;
656
657 struct ahd_softc *ahd_softc;
658 scb_flag flags;
659 #ifndef __linux__
660 bus_dmamap_t dmamap;
661 #endif
662 struct scb_platform_data *platform_data;
663 struct map_node *hscb_map;
664 struct map_node *sg_map;
665 struct map_node *sense_map;
666 void *sg_list;
667 uint8_t *sense_data;
668 bus_addr_t sg_list_busaddr;
669 bus_addr_t sense_busaddr;
670 u_int sg_count;/* How full ahd_dma_seg is */
671 #define AHD_MAX_LQ_CRC_ERRORS 5
672 u_int crc_retry_count;
673 };
674
675 TAILQ_HEAD(scb_tailq, scb);
676 LIST_HEAD(scb_list, scb);
677
678 struct scb_data {
679 /*
680 * TAILQ of lists of free SCBs grouped by device
681 * collision domains.
682 */
683 struct scb_tailq free_scbs;
684
685 /*
686 * Per-device lists of SCBs whose tag ID would collide
687 * with an already active tag on the device.
688 */
689 struct scb_list free_scb_lists[AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT];
690
691 /*
692 * SCBs that will not collide with any active device.
693 */
694 struct scb_list any_dev_free_scb_list;
695
696 /*
697 * Mapping from tag to SCB.
698 */
699 struct scb *scbindex[AHD_SCB_MAX];
700
701 u_int recovery_scbs; /* Transactions currently in recovery */
702
703 SLIST_HEAD(, map_node) hscb_maps;
704 SLIST_HEAD(, map_node) sg_maps;
705 SLIST_HEAD(, map_node) sense_maps;
706 int scbs_left; /* unallocated scbs in head map_node */
707 int sgs_left; /* unallocated sgs in head map_node */
708 int sense_left; /* unallocated sense in head map_node */
709 uint16_t numscbs;
710 uint16_t maxhscbs; /* Number of SCBs on the card */
711 uint8_t init_level; /*
712 * How far we've initialized
713 * this structure.
714 */
715 };
716
717 /************************ Target Mode Definitions *****************************/
718
719 /*
720 * Connection desciptor for select-in requests in target mode.
721 */
722 struct target_cmd {
723 uint8_t scsiid; /* Our ID and the initiator's ID */
724 uint8_t identify; /* Identify message */
725 uint8_t bytes[22]; /*
726 * Bytes contains any additional message
727 * bytes terminated by 0xFF. The remainder
728 * is the cdb to execute.
729 */
730 uint8_t cmd_valid; /*
731 * When a command is complete, the firmware
732 * will set cmd_valid to all bits set.
733 * After the host has seen the command,
734 * the bits are cleared. This allows us
735 * to just peek at host memory to determine
736 * if more work is complete. cmd_valid is on
737 * an 8 byte boundary to simplify setting
738 * it on aic7880 hardware which only has
739 * limited direct access to the DMA FIFO.
740 */
741 uint8_t pad[7];
742 };
743
744 /*
745 * Number of events we can buffer up if we run out
746 * of immediate notify ccbs.
747 */
748 #define AHD_TMODE_EVENT_BUFFER_SIZE 8
749 struct ahd_tmode_event {
750 uint8_t initiator_id;
751 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */
752 #define EVENT_TYPE_BUS_RESET 0xFF
753 uint8_t event_arg;
754 };
755
756 /*
757 * Per enabled lun target mode state.
758 * As this state is directly influenced by the host OS'es target mode
759 * environment, we let the OS module define it. Forward declare the
760 * structure here so we can store arrays of them, etc. in OS neutral
761 * data structures.
762 */
763 #ifdef AHD_TARGET_MODE
764 struct ahd_tmode_lstate {
765 struct ahd_tmode_event event_buffer[AHD_TMODE_EVENT_BUFFER_SIZE];
766 uint8_t event_r_idx;
767 uint8_t event_w_idx;
768 };
769 #else
770 struct ahd_tmode_lstate;
771 #endif
772
773 /******************** Transfer Negotiation Datastructures *********************/
774 #define AHD_TRANS_CUR 0x01 /* Modify current neogtiation status */
775 #define AHD_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */
776 #define AHD_TRANS_GOAL 0x04 /* Modify negotiation goal */
777 #define AHD_TRANS_USER 0x08 /* Modify user negotiation settings */
778 #define AHD_PERIOD_10MHz 0x19
779
780 #define AHD_WIDTH_UNKNOWN 0xFF
781 #define AHD_PERIOD_UNKNOWN 0xFF
782 #define AHD_OFFSET_UNKNOWN 0xFF
783 #define AHD_PPR_OPTS_UNKNOWN 0xFF
784
785 /*
786 * Transfer Negotiation Information.
787 */
788 struct ahd_transinfo {
789 uint8_t protocol_version; /* SCSI Revision level */
790 uint8_t transport_version; /* SPI Revision level */
791 uint8_t width; /* Bus width */
792 uint8_t period; /* Sync rate factor */
793 uint8_t offset; /* Sync offset */
794 uint8_t ppr_options; /* Parallel Protocol Request options */
795 };
796
797 /*
798 * Per-initiator current, goal and user transfer negotiation information. */
799 struct ahd_initiator_tinfo {
800 struct ahd_transinfo curr;
801 struct ahd_transinfo goal;
802 struct ahd_transinfo user;
803 };
804
805 /*
806 * Per enabled target ID state.
807 * Pointers to lun target state as well as sync/wide negotiation information
808 * for each initiator<->target mapping. For the initiator role we pretend
809 * that we are the target and the targets are the initiators since the
810 * negotiation is the same regardless of role.
811 */
812 struct ahd_tmode_tstate {
813 struct ahd_tmode_lstate* enabled_luns[AHD_NUM_LUNS];
814 struct ahd_initiator_tinfo transinfo[AHD_NUM_TARGETS];
815
816 /*
817 * Per initiator state bitmasks.
818 */
819 uint16_t auto_negotiate;/* Auto Negotiation Required */
820 uint16_t discenable; /* Disconnection allowed */
821 uint16_t tagenable; /* Tagged Queuing allowed */
822 };
823
824 /*
825 * Points of interest along the negotiated transfer scale.
826 */
827 #define AHD_SYNCRATE_160 0x8
828 #define AHD_SYNCRATE_PACED 0x8
829 #define AHD_SYNCRATE_DT 0x9
830 #define AHD_SYNCRATE_ULTRA2 0xa
831 #define AHD_SYNCRATE_ULTRA 0xc
832 #define AHD_SYNCRATE_FAST 0x19
833 #define AHD_SYNCRATE_MIN_DT AHD_SYNCRATE_FAST
834 #define AHD_SYNCRATE_SYNC 0x32
835 #define AHD_SYNCRATE_MIN 0x60
836 #define AHD_SYNCRATE_ASYNC 0xFF
837 #define AHD_SYNCRATE_MAX AHD_SYNCRATE_160
838
839 /* Safe and valid period for async negotiations. */
840 #define AHD_ASYNC_XFER_PERIOD 0x44
841
842 /*
843 * In RevA, the synctable uses a 120MHz rate for the period
844 * factor 8 and 160MHz for the period factor 7. The 120MHz
845 * rate never made it into the official SCSI spec, so we must
846 * compensate when setting the negotiation table for Rev A
847 * parts.
848 */
849 #define AHD_SYNCRATE_REVA_120 0x8
850 #define AHD_SYNCRATE_REVA_160 0x7
851
852 /***************************** Lookup Tables **********************************/
853 /*
854 * Phase -> name and message out response
855 * to parity errors in each phase table.
856 */
857 struct ahd_phase_table_entry {
858 uint8_t phase;
859 uint8_t mesg_out; /* Message response to parity errors */
860 char *phasemsg;
861 };
862
863 /************************** Serial EEPROM Format ******************************/
864
865 struct seeprom_config {
866 /*
867 * Per SCSI ID Configuration Flags
868 */
869 uint16_t device_flags[16]; /* words 0-15 */
870 #define CFXFER 0x003F /* synchronous transfer rate */
871 #define CFXFER_ASYNC 0x3F
872 #define CFQAS 0x0040 /* Negotiate QAS */
873 #define CFPACKETIZED 0x0080 /* Negotiate Packetized Transfers */
874 #define CFSTART 0x0100 /* send start unit SCSI command */
875 #define CFINCBIOS 0x0200 /* include in BIOS scan */
876 #define CFDISC 0x0400 /* enable disconnection */
877 #define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */
878 #define CFWIDEB 0x1000 /* wide bus device */
879 #define CFHOSTMANAGED 0x8000 /* Managed by a RAID controller */
880
881 /*
882 * BIOS Control Bits
883 */
884 uint16_t bios_control; /* word 16 */
885 #define CFSUPREM 0x0001 /* support all removeable drives */
886 #define CFSUPREMB 0x0002 /* support removeable boot drives */
887 #define CFBIOSSTATE 0x000C /* BIOS Action State */
888 #define CFBS_DISABLED 0x00
889 #define CFBS_ENABLED 0x04
890 #define CFBS_DISABLED_SCAN 0x08
891 #define CFENABLEDV 0x0010 /* Perform Domain Validation */
892 #define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */
893 #define CFSPARITY 0x0040 /* SCSI parity */
894 #define CFEXTEND 0x0080 /* extended translation enabled */
895 #define CFBOOTCD 0x0100 /* Support Bootable CD-ROM */
896 #define CFMSG_LEVEL 0x0600 /* BIOS Message Level */
897 #define CFMSG_VERBOSE 0x0000
898 #define CFMSG_SILENT 0x0200
899 #define CFMSG_DIAG 0x0400
900 #define CFRESETB 0x0800 /* reset SCSI bus at boot */
901 /* UNUSED 0xf000 */
902
903 /*
904 * Host Adapter Control Bits
905 */
906 uint16_t adapter_control; /* word 17 */
907 #define CFAUTOTERM 0x0001 /* Perform Auto termination */
908 #define CFSTERM 0x0002 /* SCSI low byte termination */
909 #define CFWSTERM 0x0004 /* SCSI high byte termination */
910 #define CFSEAUTOTERM 0x0008 /* Ultra2 Perform secondary Auto Term*/
911 #define CFSELOWTERM 0x0010 /* Ultra2 secondary low term */
912 #define CFSEHIGHTERM 0x0020 /* Ultra2 secondary high term */
913 #define CFSTPWLEVEL 0x0040 /* Termination level control */
914 #define CFBIOSAUTOTERM 0x0080 /* Perform Auto termination */
915 #define CFTERM_MENU 0x0100 /* BIOS displays termination menu */
916 #define CFCLUSTERENB 0x8000 /* Cluster Enable */
917
918 /*
919 * Bus Release Time, Host Adapter ID
920 */
921 uint16_t brtime_id; /* word 18 */
922 #define CFSCSIID 0x000f /* host adapter SCSI ID */
923 /* UNUSED 0x00f0 */
924 #define CFBRTIME 0xff00 /* bus release time/PCI Latency Time */
925
926 /*
927 * Maximum targets
928 */
929 uint16_t max_targets; /* word 19 */
930 #define CFMAXTARG 0x00ff /* maximum targets */
931 #define CFBOOTLUN 0x0f00 /* Lun to boot from */
932 #define CFBOOTID 0xf000 /* Target to boot from */
933 uint16_t res_1[10]; /* words 20-29 */
934 uint16_t signature; /* BIOS Signature */
935 #define CFSIGNATURE 0x400
936 uint16_t checksum; /* word 31 */
937 };
938
939 /*
940 * Vital Product Data used during POST and by the BIOS.
941 */
942 struct vpd_config {
943 uint8_t bios_flags;
944 #define VPDMASTERBIOS 0x0001
945 #define VPDBOOTHOST 0x0002
946 uint8_t reserved_1[21];
947 uint8_t resource_type;
948 uint8_t resource_len[2];
949 uint8_t resource_data[8];
950 uint8_t vpd_tag;
951 uint16_t vpd_len;
952 uint8_t vpd_keyword[2];
953 uint8_t length;
954 uint8_t revision;
955 uint8_t device_flags;
956 uint8_t termnation_menus[2];
957 uint8_t fifo_threshold;
958 uint8_t end_tag;
959 uint8_t vpd_checksum;
960 uint16_t default_target_flags;
961 uint16_t default_bios_flags;
962 uint16_t default_ctrl_flags;
963 uint8_t default_irq;
964 uint8_t pci_lattime;
965 uint8_t max_target;
966 uint8_t boot_lun;
967 uint16_t signature;
968 uint8_t reserved_2;
969 uint8_t checksum;
970 uint8_t reserved_3[4];
971 };
972
973 /****************************** Flexport Logic ********************************/
974 #define FLXADDR_TERMCTL 0x0
975 #define FLX_TERMCTL_ENSECHIGH 0x8
976 #define FLX_TERMCTL_ENSECLOW 0x4
977 #define FLX_TERMCTL_ENPRIHIGH 0x2
978 #define FLX_TERMCTL_ENPRILOW 0x1
979 #define FLXADDR_ROMSTAT_CURSENSECTL 0x1
980 #define FLX_ROMSTAT_SEECFG 0xF0
981 #define FLX_ROMSTAT_EECFG 0x0F
982 #define FLX_ROMSTAT_SEE_93C66 0x00
983 #define FLX_ROMSTAT_SEE_NONE 0xF0
984 #define FLX_ROMSTAT_EE_512x8 0x0
985 #define FLX_ROMSTAT_EE_1MBx8 0x1
986 #define FLX_ROMSTAT_EE_2MBx8 0x2
987 #define FLX_ROMSTAT_EE_4MBx8 0x3
988 #define FLX_ROMSTAT_EE_16MBx8 0x4
989 #define CURSENSE_ENB 0x1
990 #define FLXADDR_FLEXSTAT 0x2
991 #define FLX_FSTAT_BUSY 0x1
992 #define FLXADDR_CURRENT_STAT 0x4
993 #define FLX_CSTAT_SEC_HIGH 0xC0
994 #define FLX_CSTAT_SEC_LOW 0x30
995 #define FLX_CSTAT_PRI_HIGH 0x0C
996 #define FLX_CSTAT_PRI_LOW 0x03
997 #define FLX_CSTAT_MASK 0x03
998 #define FLX_CSTAT_SHIFT 2
999 #define FLX_CSTAT_OKAY 0x0
1000 #define FLX_CSTAT_OVER 0x1
1001 #define FLX_CSTAT_UNDER 0x2
1002 #define FLX_CSTAT_INVALID 0x3
1003
1004 int ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf,
1005 u_int start_addr, u_int count, int bstream);
1006
1007 int ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf,
1008 u_int start_addr, u_int count);
1009 int ahd_wait_seeprom(struct ahd_softc *ahd);
1010 int ahd_verify_vpd_cksum(struct vpd_config *vpd);
1011 int ahd_verify_cksum(struct seeprom_config *sc);
1012 int ahd_acquire_seeprom(struct ahd_softc *ahd);
1013 void ahd_release_seeprom(struct ahd_softc *ahd);
1014
1015 /**************************** Message Buffer *********************************/
1016 typedef enum {
1017 MSG_FLAG_NONE = 0x00,
1018 MSG_FLAG_EXPECT_PPR_BUSFREE = 0x01,
1019 MSG_FLAG_IU_REQ_CHANGED = 0x02,
1020 MSG_FLAG_EXPECT_IDE_BUSFREE = 0x04,
1021 MSG_FLAG_EXPECT_QASREJ_BUSFREE = 0x08,
1022 MSG_FLAG_PACKETIZED = 0x10
1023 } ahd_msg_flags;
1024
1025 typedef enum {
1026 MSG_TYPE_NONE = 0x00,
1027 MSG_TYPE_INITIATOR_MSGOUT = 0x01,
1028 MSG_TYPE_INITIATOR_MSGIN = 0x02,
1029 MSG_TYPE_TARGET_MSGOUT = 0x03,
1030 MSG_TYPE_TARGET_MSGIN = 0x04
1031 } ahd_msg_type;
1032
1033 typedef enum {
1034 MSGLOOP_IN_PROG,
1035 MSGLOOP_MSGCOMPLETE,
1036 MSGLOOP_TERMINATED
1037 } msg_loop_stat;
1038
1039 /*********************** Software Configuration Structure *********************/
1040 struct ahd_suspend_channel_state {
1041 uint8_t scsiseq;
1042 uint8_t sxfrctl0;
1043 uint8_t sxfrctl1;
1044 uint8_t simode0;
1045 uint8_t simode1;
1046 uint8_t seltimer;
1047 uint8_t seqctl;
1048 };
1049
1050 struct ahd_suspend_state {
1051 struct ahd_suspend_channel_state channel[2];
1052 uint8_t optionmode;
1053 uint8_t dscommand0;
1054 uint8_t dspcistatus;
1055 /* hsmailbox */
1056 uint8_t crccontrol1;
1057 uint8_t scbbaddr;
1058 /* Host and sequencer SCB counts */
1059 uint8_t dff_thrsh;
1060 uint8_t *scratch_ram;
1061 uint8_t *btt;
1062 };
1063
1064 typedef void (*ahd_bus_intr_t)(struct ahd_softc *);
1065
1066 typedef enum {
1067 AHD_MODE_DFF0,
1068 AHD_MODE_DFF1,
1069 AHD_MODE_CCHAN,
1070 AHD_MODE_SCSI,
1071 AHD_MODE_CFG,
1072 AHD_MODE_UNKNOWN
1073 } ahd_mode;
1074
1075 #define AHD_MK_MSK(x) (0x01 << (x))
1076 #define AHD_MODE_DFF0_MSK AHD_MK_MSK(AHD_MODE_DFF0)
1077 #define AHD_MODE_DFF1_MSK AHD_MK_MSK(AHD_MODE_DFF1)
1078 #define AHD_MODE_CCHAN_MSK AHD_MK_MSK(AHD_MODE_CCHAN)
1079 #define AHD_MODE_SCSI_MSK AHD_MK_MSK(AHD_MODE_SCSI)
1080 #define AHD_MODE_CFG_MSK AHD_MK_MSK(AHD_MODE_CFG)
1081 #define AHD_MODE_UNKNOWN_MSK AHD_MK_MSK(AHD_MODE_UNKNOWN)
1082 #define AHD_MODE_ANY_MSK (~0)
1083
1084 typedef uint8_t ahd_mode_state;
1085
1086 typedef void ahd_callback_t (void *);
1087
1088 struct ahd_completion
1089 {
1090 uint16_t tag;
1091 uint8_t sg_status;
1092 uint8_t valid_tag;
1093 };
1094
1095 #define AIC_SCB_DATA(softc) (&(softc)->scb_data)
1096
1097 struct ahd_softc {
1098 struct device sc_dev;
1099 struct scsi_link sc_channel;
1100 struct device * sc_child;
1101
1102 bus_space_tag_t tags[2];
1103 bus_space_handle_t bshs[2];
1104
1105 #ifndef __linux__
1106 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */
1107 #endif
1108 void *shutdown_hook;
1109 struct scb_data scb_data;
1110
1111 struct hardware_scb *next_queued_hscb;
1112 struct map_node *next_queued_hscb_map;
1113
1114 /*
1115 * SCBs that have been sent to the controller
1116 */
1117 LIST_HEAD(, scb) pending_scbs;
1118
1119 /*
1120 * SCBs whose timeout routine has been called.
1121 */
1122 LIST_HEAD(, scb) timedout_scbs;
1123
1124 /*
1125 * Current register window mode information.
1126 */
1127 ahd_mode dst_mode;
1128 ahd_mode src_mode;
1129
1130 /*
1131 * Saved register window mode information
1132 * used for restore on next unpause.
1133 */
1134 ahd_mode saved_dst_mode;
1135 ahd_mode saved_src_mode;
1136
1137 /*
1138 * Platform specific data.
1139 */
1140 struct ahd_platform_data *platform_data;
1141
1142 /*
1143 * Platform specific device information.
1144 */
1145 ahd_dev_softc_t dev_softc;
1146
1147 /*
1148 * Bus specific device information.
1149 */
1150 ahd_bus_intr_t bus_intr;
1151
1152 /*
1153 * Target mode related state kept on a per enabled lun basis.
1154 * Targets that are not enabled will have null entries.
1155 * As an initiator, we keep one target entry for our initiator
1156 * ID to store our sync/wide transfer settings.
1157 */
1158 struct ahd_tmode_tstate *enabled_targets[AHD_NUM_TARGETS];
1159
1160 char inited_target[AHD_NUM_TARGETS];
1161
1162 /*
1163 * The black hole device responsible for handling requests for
1164 * disabled luns on enabled targets.
1165 */
1166 struct ahd_tmode_lstate *black_hole;
1167
1168 /*
1169 * Device instance currently on the bus awaiting a continue TIO
1170 * for a command that was not given the disconnect priveledge.
1171 */
1172 struct ahd_tmode_lstate *pending_device;
1173
1174 /*
1175 * Timer handles for timer driven callbacks.
1176 */
1177 aic_timer_t reset_timer;
1178 aic_timer_t stat_timer;
1179
1180 /*
1181 * Statistics.
1182 */
1183 #define AHD_STAT_UPDATE_MS 250
1184 #define AHD_STAT_BUCKETS 4
1185 u_int cmdcmplt_bucket;
1186 uint32_t cmdcmplt_counts[AHD_STAT_BUCKETS];
1187 uint32_t cmdcmplt_total;
1188
1189 /*
1190 * Card characteristics
1191 */
1192 ahd_chip chip;
1193 ahd_feature features;
1194 ahd_bug bugs;
1195 ahd_flag flags;
1196 struct seeprom_config *seep_config;
1197
1198 /* Command Queues */
1199 struct ahd_completion *qoutfifo;
1200 uint16_t qoutfifonext;
1201 uint16_t qoutfifonext_valid_tag;
1202 uint16_t qinfifonext;
1203 uint16_t qinfifo[AHD_SCB_MAX];
1204
1205 /*
1206 * Our qfreeze count. The sequencer compares
1207 * this value with its own counter to determine
1208 * whether to allow selections to occur.
1209 */
1210 uint16_t qfreeze_cnt;
1211
1212 /* Values to store in the SEQCTL register for pause and unpause */
1213 uint8_t unpause;
1214 uint8_t pause;
1215
1216 /* Critical Section Data */
1217 struct cs *critical_sections;
1218 u_int num_critical_sections;
1219
1220 /* Buffer for handling packetized bitbucket. */
1221 uint8_t *overrun_buf;
1222
1223 /* Links for chaining softcs */
1224 TAILQ_ENTRY(ahd_softc) links;
1225
1226 /* Channel Names ('A', 'B', etc.) */
1227 char channel;
1228
1229 /* Initiator Bus ID */
1230 uint8_t our_id;
1231
1232 /*
1233 * Target incoming command FIFO.
1234 */
1235 struct target_cmd *targetcmds;
1236 uint8_t tqinfifonext;
1237
1238 /*
1239 * Cached verson of the hs_mailbox so we can avoid
1240 * pausing the sequencer during mailbox updates.
1241 */
1242 uint8_t hs_mailbox;
1243
1244 /*
1245 * Incoming and outgoing message handling.
1246 */
1247 uint8_t send_msg_perror;
1248 ahd_msg_flags msg_flags;
1249 ahd_msg_type msg_type;
1250 uint8_t msgout_buf[12];/* Message we are sending */
1251 uint8_t msgin_buf[12];/* Message we are receiving */
1252 u_int msgout_len; /* Length of message to send */
1253 u_int msgout_index; /* Current index in msgout */
1254 u_int msgin_index; /* Current index in msgin */
1255
1256 /*
1257 * Mapping information for data structures shared
1258 * between the sequencer and kernel.
1259 */
1260 bus_dma_tag_t parent_dmat;
1261 struct map_node shared_data_map;
1262
1263 /* Information saved through suspend/resume cycles */
1264 struct ahd_suspend_state suspend_state;
1265
1266 /* Number of enabled target mode device on this card */
1267 u_int enabled_luns;
1268
1269 /* Initialization level of this data structure */
1270 u_int init_level;
1271
1272 /* PCI cacheline size. */
1273 u_int pci_cachesize;
1274
1275 /* IO Cell Parameters */
1276 uint8_t iocell_opts[AHD_NUM_PER_DEV_ANNEXCOLS];
1277
1278 u_int stack_size;
1279 uint16_t *saved_stack;
1280
1281 /* Per-Unit descriptive information */
1282 const char *bus_description;
1283 char *name;
1284 int unit;
1285
1286 /* Selection Timer settings */
1287 int seltime;
1288
1289 /*
1290 * Interrupt coalescing settings.
1291 */
1292 #define AHD_INT_COALESCING_TIMER_DEFAULT 250 /*us*/
1293 #define AHD_INT_COALESCING_MAXCMDS_DEFAULT 10
1294 #define AHD_INT_COALESCING_MAXCMDS_MAX 127
1295 #define AHD_INT_COALESCING_MINCMDS_DEFAULT 5
1296 #define AHD_INT_COALESCING_MINCMDS_MAX 127
1297 #define AHD_INT_COALESCING_THRESHOLD_DEFAULT 2000
1298 #define AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT 1000
1299 u_int int_coalescing_timer;
1300 u_int int_coalescing_maxcmds;
1301 u_int int_coalescing_mincmds;
1302 u_int int_coalescing_threshold;
1303 u_int int_coalescing_stop_threshold;
1304
1305 uint16_t user_discenable;/* Disconnection allowed */
1306 uint16_t user_tagenable;/* Tagged Queuing allowed */
1307
1308 /* Adapter interrupt routine */
1309 void *ih;
1310 int pcix_off;
1311 };
1312
1313 TAILQ_HEAD(ahd_softc_tailq, ahd_softc);
1314 extern struct ahd_softc_tailq ahd_tailq;
1315
1316 /*************************** IO Cell Configuration ****************************/
1317 #define AHD_PRECOMP_SLEW_INDEX \
1318 (AHD_ANNEXCOL_PRECOMP_SLEW - AHD_ANNEXCOL_PER_DEV0)
1319
1320 #define AHD_AMPLITUDE_INDEX \
1321 (AHD_ANNEXCOL_AMPLITUDE - AHD_ANNEXCOL_PER_DEV0)
1322
1323 #define AHD_SET_SLEWRATE(ahd, new_slew) \
1324 do { \
1325 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_SLEWRATE_MASK; \
1326 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \
1327 (((new_slew) << AHD_SLEWRATE_SHIFT) & AHD_SLEWRATE_MASK); \
1328 } while (0)
1329
1330 #define AHD_SET_PRECOMP(ahd, new_pcomp) \
1331 do { \
1332 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; \
1333 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \
1334 (((new_pcomp) << AHD_PRECOMP_SHIFT) & AHD_PRECOMP_MASK); \
1335 } while (0)
1336
1337 #define AHD_SET_AMPLITUDE(ahd, new_amp) \
1338 do { \
1339 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] &= ~AHD_AMPLITUDE_MASK; \
1340 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] |= \
1341 (((new_amp) << AHD_AMPLITUDE_SHIFT) & AHD_AMPLITUDE_MASK); \
1342 } while (0)
1343
1344 /************************ Active Device Information ***************************/
1345 typedef enum {
1346 ROLE_UNKNOWN,
1347 ROLE_INITIATOR,
1348 ROLE_TARGET
1349 } role_t;
1350
1351 struct ahd_devinfo {
1352 int our_scsiid;
1353 int target_offset;
1354 uint16_t target_mask;
1355 u_int target;
1356 u_int lun;
1357 char channel;
1358 role_t role; /*
1359 * Only guaranteed to be correct if not
1360 * in the busfree state.
1361 */
1362 };
1363
1364 /****************************** PCI Structures ********************************/
1365 #define AHD_PCI_IOADDR PCI_MAPREG_START /* I/O BAR*/
1366 #define AHD_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Memory BAR */
1367 #define AHD_PCI_IOADDR1 (PCI_MAPREG_START + 12)/* Second I/O BAR */
1368
1369 typedef int (ahd_device_setup_t)(struct ahd_softc *, struct pci_attach_args *pa);
1370
1371 struct ahd_pci_identity {
1372 uint64_t full_id;
1373 uint64_t id_mask;
1374 ahd_device_setup_t *setup;
1375 };
1376 extern struct ahd_pci_identity ahd_pci_ident_table [];
1377 extern const u_int ahd_num_pci_devs;
1378
1379 /*************************** Function Declarations ****************************/
1380 /******************************************************************************/
1381 void ahd_reset_cmds_pending(struct ahd_softc *ahd);
1382 u_int ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl);
1383 void ahd_busy_tcl(struct ahd_softc *ahd,
1384 u_int tcl, u_int busyid);
1385 void ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl);
1386
1387 /***************************** PCI Front End *********************************/
1388 const struct ahd_pci_identity * ahd_find_pci_device(pcireg_t, pcireg_t);
1389 int ahd_pci_config(struct ahd_softc *,
1390 struct ahd_pci_identity *);
1391 int ahd_pci_test_register_access(struct ahd_softc *);
1392
1393 /************************** SCB and SCB queue management **********************/
1394 int ahd_probe_scbs(struct ahd_softc *);
1395 void ahd_qinfifo_requeue_tail(struct ahd_softc *ahd,
1396 struct scb *scb);
1397 int ahd_match_scb(struct ahd_softc *ahd, struct scb *scb,
1398 int target, char channel, int lun,
1399 u_int tag, role_t role);
1400
1401 /****************************** Initialization ********************************/
1402 struct ahd_softc *ahd_alloc(void *platform_arg, char *name);
1403 int ahd_softc_init(struct ahd_softc *);
1404 void ahd_controller_info(struct ahd_softc *ahd, char *buf,
1405 size_t bufsz);
1406 int ahd_init(struct ahd_softc *ahd);
1407 int ahd_default_config(struct ahd_softc *ahd);
1408 int ahd_parse_vpddata(struct ahd_softc *ahd,
1409 struct vpd_config *vpd);
1410 int ahd_parse_cfgdata(struct ahd_softc *ahd,
1411 struct seeprom_config *sc);
1412 void ahd_intr_enable(struct ahd_softc *ahd, int enable);
1413 void ahd_update_coalescing_values(struct ahd_softc *ahd,
1414 u_int timer,
1415 u_int maxcmds,
1416 u_int mincmds);
1417 void ahd_enable_coalescing(struct ahd_softc *ahd,
1418 int enable);
1419 void ahd_pause_and_flushwork(struct ahd_softc *ahd);
1420 int ahd_suspend(struct ahd_softc *ahd);
1421 int ahd_resume(struct ahd_softc *ahd);
1422 void ahd_softc_insert(struct ahd_softc *);
1423 struct ahd_softc *ahd_find_softc(struct ahd_softc *ahd);
1424 void ahd_set_unit(struct ahd_softc *, int);
1425 void ahd_set_name(struct ahd_softc *, char *);
1426 struct scb *ahd_get_scb(struct ahd_softc *ahd, u_int col_idx);
1427 void ahd_free_scb(struct ahd_softc *ahd, struct scb *scb);
1428 void ahd_alloc_scbs(struct ahd_softc *ahd);
1429 void ahd_free(struct ahd_softc *ahd);
1430 int ahd_reset(struct ahd_softc *ahd, int reinit);
1431 void ahd_shutdown(void *arg);
1432 int ahd_write_flexport(struct ahd_softc *ahd,
1433 u_int addr, u_int value);
1434 int ahd_read_flexport(struct ahd_softc *ahd, u_int addr,
1435 uint8_t *value);
1436 int ahd_wait_flexport(struct ahd_softc *ahd);
1437
1438 /*************************** Interrupt Services *******************************/
1439 void ahd_pci_intr(struct ahd_softc *ahd);
1440 void ahd_clear_intstat(struct ahd_softc *ahd);
1441 void ahd_flush_qoutfifo(struct ahd_softc *ahd);
1442 void ahd_run_qoutfifo(struct ahd_softc *ahd);
1443 #ifdef AHD_TARGET_MODE
1444 void ahd_run_tqinfifo(struct ahd_softc *ahd, int paused);
1445 #endif
1446 void ahd_handle_hwerrint(struct ahd_softc *ahd);
1447 void ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat);
1448 void ahd_handle_scsiint(struct ahd_softc *ahd,
1449 u_int intstat);
1450 void ahd_clear_critical_section(struct ahd_softc *ahd);
1451
1452 /***************************** Error Recovery *********************************/
1453 typedef enum {
1454 SEARCH_COMPLETE,
1455 SEARCH_COUNT,
1456 SEARCH_REMOVE,
1457 SEARCH_PRINT
1458 } ahd_search_action;
1459 void ahd_done_with_status(struct ahd_softc *ahd,
1460 struct scb *scb, uint32_t status);
1461 int ahd_search_qinfifo(struct ahd_softc *ahd, int target,
1462 char channel, int lun, u_int tag,
1463 role_t role, uint32_t status,
1464 ahd_search_action action);
1465 int ahd_search_disc_list(struct ahd_softc *ahd, int target,
1466 char channel, int lun, u_int tag,
1467 int stop_on_first, int remove,
1468 int save_state);
1469 void ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb);
1470 int ahd_reset_channel(struct ahd_softc *ahd, char channel,
1471 int initiate_reset);
1472 int ahd_abort_scbs(struct ahd_softc *ahd, int target,
1473 char channel, int lun, u_int tag,
1474 role_t role, uint32_t status);
1475 void ahd_restart(struct ahd_softc *ahd);
1476 void ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo);
1477 void ahd_handle_scb_status(struct ahd_softc *ahd,
1478 struct scb *scb);
1479 void ahd_handle_scsi_status(struct ahd_softc *ahd,
1480 struct scb *scb);
1481 void ahd_calc_residual(struct ahd_softc *ahd,
1482 struct scb *scb);
1483 void ahd_timeout(void *);
1484 /*************************** Utility Functions ********************************/
1485 struct ahd_phase_table_entry*
1486 ahd_lookup_phase_entry(int phase);
1487 void ahd_compile_devinfo(struct ahd_devinfo *devinfo,
1488 u_int our_id, u_int target,
1489 u_int lun, char channel,
1490 role_t role);
1491 /************************** Transfer Negotiation ******************************/
1492 void ahd_find_syncrate(struct ahd_softc *ahd, u_int *period,
1493 u_int *ppr_options, u_int maxsync);
1494 void ahd_validate_offset(struct ahd_softc *ahd,
1495 struct ahd_initiator_tinfo *tinfo,
1496 u_int period, u_int *offset,
1497 int wide, role_t role);
1498 void ahd_validate_width(struct ahd_softc *ahd,
1499 struct ahd_initiator_tinfo *tinfo,
1500 u_int *bus_width,
1501 role_t role);
1502 void ahd_scb_devinfo(struct ahd_softc *,
1503 struct ahd_devinfo *, struct scb *);
1504
1505 /*
1506 * Negotiation types. These are used to qualify if we should renegotiate
1507 * even if our goal and current transport parameters are identical.
1508 */
1509 typedef enum {
1510 AHD_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */
1511 AHD_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */
1512 AHD_NEG_ALWAYS /* Renegotiat even if goal is async. */
1513 } ahd_neg_type;
1514 int ahd_update_neg_request(struct ahd_softc*,
1515 struct ahd_devinfo*,
1516 struct ahd_tmode_tstate*,
1517 struct ahd_initiator_tinfo*,
1518 ahd_neg_type);
1519 void ahd_set_width(struct ahd_softc *ahd,
1520 struct ahd_devinfo *devinfo,
1521 u_int width, u_int type, int paused);
1522 void ahd_set_syncrate(struct ahd_softc *ahd,
1523 struct ahd_devinfo *devinfo,
1524 u_int period, u_int offset,
1525 u_int ppr_options,
1526 u_int type, int paused);
1527 typedef enum {
1528 AHD_QUEUE_NONE,
1529 AHD_QUEUE_BASIC,
1530 AHD_QUEUE_TAGGED
1531 } ahd_queue_alg;
1532
1533 void ahd_set_tags(struct ahd_softc *ahd,
1534 struct ahd_devinfo *devinfo,
1535 ahd_queue_alg alg);
1536
1537 /**************************** Target Mode *************************************/
1538 #ifdef AHD_TARGET_MODE
1539 void ahd_send_lstate_events(struct ahd_softc *,
1540 struct ahd_tmode_lstate *);
1541 void ahd_handle_en_lun(struct ahd_softc *ahd,
1542 struct cam_sim *sim, union ccb *ccb);
1543 cam_status ahd_find_tmode_devs(struct ahd_softc *ahd,
1544 struct cam_sim *sim, union ccb *ccb,
1545 struct ahd_tmode_tstate **tstate,
1546 struct ahd_tmode_lstate **lstate,
1547 int notfound_failure);
1548 #ifndef AHD_TMODE_ENABLE
1549 #define AHD_TMODE_ENABLE 0
1550 #endif
1551 #endif
1552 /******************************* Debug ***************************************/
1553 #ifdef AHD_DEBUG
1554 extern uint32_t ahd_debug;
1555 #define AHD_DEBUG_OPTS 0
1556 #define AHD_SHOW_MISC 0x00001
1557 #define AHD_SHOW_SENSE 0x00002
1558 #define AHD_SHOW_RECOVERY 0x00004
1559 #define AHD_DUMP_SEEPROM 0x00008
1560 #define AHD_SHOW_TERMCTL 0x00010
1561 #define AHD_SHOW_MEMORY 0x00020
1562 #define AHD_SHOW_MESSAGES 0x00040
1563 #define AHD_SHOW_MODEPTR 0x00080
1564 #define AHD_SHOW_SELTO 0x00100
1565 #define AHD_SHOW_FIFOS 0x00200
1566 #define AHD_SHOW_QFULL 0x00400
1567 #define AHD_SHOW_DV 0x00800
1568 #define AHD_SHOW_MASKED_ERRORS 0x01000
1569 #define AHD_SHOW_QUEUE 0x02000
1570 #define AHD_SHOW_TQIN 0x04000
1571 #define AHD_SHOW_SG 0x08000
1572 #define AHD_SHOW_INT_COALESCING 0x10000
1573 #define AHD_DEBUG_SEQUENCER 0x20000
1574 #endif
1575 void ahd_print_scb(struct scb *scb);
1576 void ahd_print_devinfo(struct ahd_softc *ahd,
1577 struct ahd_devinfo *devinfo);
1578 void ahd_dump_sglist(struct scb *scb);
1579 void ahd_dump_all_cards_state(void);
1580 void ahd_dump_card_state(struct ahd_softc *ahd);
1581 int ahd_print_register(ahd_reg_parse_entry_t *table,
1582 u_int num_entries,
1583 const char *name,
1584 u_int address,
1585 u_int value,
1586 u_int *cur_column,
1587 u_int wrap_point);
1588 void ahd_dump_scbs(struct ahd_softc *ahd);
1589
1590 #endif /* _AIC79XX_H_ */