enable 105 arch/i386/isa/pccomvar.h int (*enable)(struct com_softc *);
enable 221 arch/i386/pci/pci_machdep.c tag.mode2.enable = 0xf0 | (function << 1);
enable 250 arch/i386/pci/pci_machdep.c *fp = (tag.mode2.enable >> 1) & 0x7;
enable 269 arch/i386/pci/pci_machdep.c outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable);
enable 292 arch/i386/pci/pci_machdep.c outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable);
enable 53 arch/i386/pci/pci_machdep.h u_int8_t enable;
enable 976 dev/acpi/acpi.c acpi_enable_onegpe(struct acpi_softc *sc, int gpe, int enable)
enable 984 dev/acpi/acpi.c enable ? "en" : "dis", gpe, (en & mask) ? "en" : "dis", en);
enable 985 dev/acpi/acpi.c if (enable)
enable 280 dev/cardbus/com_cardbus.c sc->enable = com_cardbus_enable;
enable 185 dev/cardbus/if_rtw_cardbus.c rtw_cardbus_funcregen(struct rtw_regs *regs, int enable)
enable 190 dev/cardbus/if_rtw_cardbus.c if (enable) {
enable 184 dev/i2o/ioprbs.c int enable;
enable 269 dev/i2o/ioprbs.c enable = 1;
enable 273 dev/i2o/ioprbs.c enable = 0;
enable 277 dev/i2o/ioprbs.c enable = 0;
enable 281 dev/i2o/ioprbs.c enable = 0;
enable 285 dev/i2o/ioprbs.c enable = 0;
enable 293 dev/i2o/ioprbs.c enable = 0;
enable 348 dev/i2o/ioprbs.c if (enable)
enable 2320 dev/ic/aac.c aac_sa_set_interrupts(struct aac_softc *sc, int enable)
enable 2323 dev/ic/aac.c sc->aac_dev.dv_xname, enable ? "en" : "dis"));
enable 2325 dev/ic/aac.c if (enable)
enable 2332 dev/ic/aac.c aac_rx_set_interrupts(struct aac_softc *sc, int enable)
enable 2335 dev/ic/aac.c sc->aac_dev.dv_xname, enable ? "en" : "dis"));
enable 2337 dev/ic/aac.c if (enable)
enable 2344 dev/ic/aac.c aac_fa_set_interrupts(struct aac_softc *sc, int enable)
enable 2347 dev/ic/aac.c sc->aac_dev.dv_xname, enable ? "en" : "dis"));
enable 2349 dev/ic/aac.c if (enable) {
enable 2359 dev/ic/aac.c aac_rkt_set_interrupts(struct aac_softc *sc, int enable)
enable 2362 dev/ic/aac.c sc->aac_dev.dv_xname, enable ? "en" : "dis"));
enable 2364 dev/ic/aac.c if (enable)
enable 6925 dev/ic/aic79xx.c ahd_intr_enable(struct ahd_softc *ahd, int enable)
enable 6933 dev/ic/aic79xx.c if (enable) {
enable 6960 dev/ic/aic79xx.c ahd_enable_coalescing(struct ahd_softc *ahd, int enable)
enable 6964 dev/ic/aic79xx.c if (enable)
enable 9576 dev/ic/aic79xx.c if (cel->enable != 0) {
enable 1412 dev/ic/aic79xx.h void ahd_intr_enable(struct ahd_softc *ahd, int enable);
enable 1418 dev/ic/aic79xx.h int enable);
enable 4987 dev/ic/aic7xxx.c ahc_intr_enable(struct ahc_softc *ahc, int enable)
enable 4995 dev/ic/aic7xxx.c if (enable) {
enable 6845 dev/ic/aic7xxx.c if (cel->enable != 0) {
enable 1230 dev/ic/aic7xxxvar.h void ahc_intr_enable(struct ahc_softc *ahc, int enable);
enable 2296 dev/ic/ar5210.c ar5k_ar5210_radar_alert(struct ath_hal *hal, HAL_BOOL enable)
enable 2304 dev/ic/ar5210.c if (enable == AH_TRUE) {
enable 2425 dev/ic/ar5211.c ar5k_ar5211_radar_alert(struct ath_hal *hal, HAL_BOOL enable)
enable 2432 dev/ic/ar5211.c if (enable == AH_TRUE) {
enable 2800 dev/ic/ar5212.c ar5k_ar5212_radar_alert(struct ath_hal *hal, HAL_BOOL enable)
enable 2807 dev/ic/ar5212.c if (enable == AH_TRUE) {
enable 1072 dev/ic/ar5xxx.h _t void (_a _n##_radar_alert)(struct ath_hal *, HAL_BOOL enable); \
enable 1509 dev/ic/atw.c atw_bbp_io_enable(struct atw_softc *sc, int enable)
enable 1511 dev/ic/atw.c if (enable) {
enable 500 dev/ic/bha.c toggle.cmd.enable = 0;
enable 736 dev/ic/bha.c toggle.cmd.enable = 1;
enable 1084 dev/ic/bha.c toggle.cmd.enable = 1;
enable 354 dev/ic/bhareg.h u_char enable;
enable 375 dev/ic/bt485.c data->curenb = cursorp->enable;
enable 434 dev/ic/bt485.c cursorp->enable = data->curenb; /* DOCUR */
enable 390 dev/ic/com_subr.c if (!sc->enable)
enable 135 dev/ic/comvar.h int (*enable)(struct com_softc *);
enable 461 dev/ic/lemac.c lemac_multicast_op(u_int16_t *mctbl, const u_char *mca, int enable)
enable 483 dev/ic/lemac.c if (enable) {
enable 178 dev/ic/malo.c uint16_t enable;
enable 2237 dev/ic/malo.c malo_cmd_set_radio(struct malo_softc *sc, uint16_t enable,
enable 2252 dev/ic/malo.c body->enable = htole16(enable);
enable 1064 dev/ic/rln.c rln_multicast(sc, enable)
enable 1066 dev/ic/rln.c int enable;
enable 1073 dev/ic/rln.c mcast.enable = enable;
enable 1078 dev/ic/rln.c if (enable)
enable 118 dev/ic/rlncmd.h u_int8_t enable;
enable 49 dev/ic/rlnsubr.c rln_enable(sc, enable)
enable 51 dev/ic/rlnsubr.c int enable;
enable 58 dev/ic/rlnsubr.c if (enable != was_enabled) {
enable 59 dev/ic/rlnsubr.c if (enable)
enable 275 dev/ic/rtw.c rtw_continuous_tx_enable(struct rtw_softc *sc, int enable)
enable 282 dev/ic/rtw.c if (enable)
enable 289 dev/ic/rtw.c rtw_txdac_enable(sc, !enable);
enable 376 dev/ic/rtw.c rtw_config0123_enable(struct rtw_regs *regs, int enable)
enable 381 dev/ic/rtw.c if (enable)
enable 393 dev/ic/rtw.c rtw_anaparm_enable(struct rtw_regs *regs, int enable)
enable 399 dev/ic/rtw.c if (enable)
enable 409 dev/ic/rtw.c rtw_txdac_enable(struct rtw_softc *sc, int enable)
enable 415 dev/ic/rtw.c if (enable)
enable 1100 dev/ic/rtw.c rtw_io_enable(struct rtw_regs *regs, u_int8_t flags, int enable)
enable 1105 dev/ic/rtw.c enable ? "enable" : "disable", flags));
enable 1116 dev/ic/rtw.c if (enable)
enable 4579 dev/ic/rtw.c uint32_t enable;
enable 4585 dev/ic/rtw.c enable = 0x0;
enable 4588 dev/ic/rtw.c enable = MAX2820_ENABLE_DEFAULT;
enable 4591 dev/ic/rtw.c return rtw_rf_hostwrite(sc, MAX2820_ENABLE, enable);
enable 547 dev/isa/aha.c toggle.cmd.enable = 0;
enable 793 dev/isa/aha.c toggle.cmd.enable = 1;
enable 194 dev/isa/ahareg.h u_char enable;
enable 53 dev/pci/agpvar.h int (*enable)(struct vga_pci_softc *, u_int32_t mode);
enable 67 dev/pci/agpvar.h #define AGP_ENABLE(sc,m) ((sc)->sc_methods->enable((sc),(m)))
enable 640 dev/pci/ahc_pci.c static void ahc_scbram_config(struct ahc_softc *ahc, int enable,
enable 1149 dev/pci/ahc_pci.c ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck,
enable 1170 dev/pci/ahc_pci.c if (enable)
enable 1184 dev/pci/ahc_pci.c if (enable)
enable 1211 dev/pci/ahc_pci.c int enable;
enable 1216 dev/pci/ahc_pci.c enable = FALSE;
enable 1234 dev/pci/ahc_pci.c enable = TRUE;
enable 1246 dev/pci/ahc_pci.c ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large);
enable 1257 dev/pci/ahc_pci.c ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large);
enable 1269 dev/pci/ahc_pci.c ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE);
enable 1294 dev/pci/ahc_pci.c if (1/*bootverbose*/ && enable) {
enable 1300 dev/pci/ahc_pci.c ahc_scbram_config(ahc, enable, pcheck, fast, large);
enable 1047 dev/pci/auixp.c u_int32_t status, enable, detected_codecs;
enable 1091 dev/pci/auixp.c enable = bus_space_read_4(iot, ioh, ATI_REG_IER);
enable 1092 dev/pci/auixp.c enable &= ~detected_codecs;
enable 1093 dev/pci/auixp.c bus_space_write_4(iot, ioh, ATI_REG_IER, enable);
enable 662 dev/pci/noct.c int enable = 1;
enable 670 dev/pci/noct.c enable = 0;
enable 680 dev/pci/noct.c enable = 0;
enable 684 dev/pci/noct.c enable = 0;
enable 688 dev/pci/noct.c enable = 0;
enable 692 dev/pci/noct.c if (!enable)
enable 2008 dev/pci/pccbb.c u_int8_t ioctl, enable;
enable 2026 dev/pci/pccbb.c enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE);
enable 2033 dev/pci/pccbb.c enable |= PCIC_ADDRWIN_ENABLE_IO0;
enable 2040 dev/pci/pccbb.c enable |= PCIC_ADDRWIN_ENABLE_IO1;
enable 2044 dev/pci/pccbb.c Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable);
enable 2057 dev/pci/pccbb.c start_low, start_high, stop_low, stop_high, ioctl, enable);
enable 310 dev/pci/sv.c goto enable;
enable 330 dev/pci/sv.c goto enable;
enable 339 dev/pci/sv.c enable:
enable 897 dev/pci/tga.c if (cursorp->enable)
enable 936 dev/pci/tga.c cursorp->enable = (TGARREG(dc, TGA_REG_VVVR) & 0x04) != 0;
enable 324 dev/pcmcia/com_pcmcia.c sc->enable = com_pcmcia_enable;
enable 371 dev/pcmcia/if_ep_pcmcia.c sc->enable = ep_pcmcia_enable;
enable 832 dev/pcmcia/if_malo.c cmalo_intr_mask(struct malo_softc *sc, int enable)
enable 841 dev/pcmcia/if_malo.c if (enable)
enable 1814 dev/pcmcia/if_malo.c body->enable = 1;
enable 190 dev/pcmcia/if_malovar.h uint8_t enable;
enable 197 dev/pcmcia/if_rln_pcmcia.c sc->enable = rln_pcmcia_enable;
enable 313 dev/sbus/cgsix.c curs->enable = sc->sc_curs_enabled;
enable 426 dev/sbus/cgsix.c sc->sc_curs_enabled = curs->enable;
enable 520 dev/sdmmc/sdhc.c sdhc_card_intr_mask(sdmmc_chipset_handle_t sch, int enable)
enable 524 dev/sdmmc/sdhc.c if (enable) {
enable 66 dev/sdmmc/sdmmcchip.h #define sdmmc_chip_card_intr_mask(tag, handle, enable) \
enable 67 dev/sdmmc/sdmmcchip.h ((tag)->card_intr_mask((handle), (enable)))
enable 334 dev/wscons/wsconsio.h u_int enable; /* enable/disable */
enable 762 dev/wscons/wskbd.c error = (*sc->sc_accessops->enable)(sc->sc_accesscookie, on);
enable 45 dev/wscons/wskbdvar.h int (*enable)(void *, int);
enable 557 dev/wscons/wsmouse.c return (*sc->sc_accessops->enable)(sc->sc_accesscookie);
enable 45 dev/wscons/wsmousevar.h int (*enable)(void *);