root/dev/ic/ar5210.c

DEFINITIONS

1. ar5k_ar5210_fill
2. ar5k_ar5210_attach
3. ar5k_ar5210_nic_reset
4. ar5k_ar5210_nic_wakeup
5. ar5k_ar5210_get_rate_table
6. ar5k_ar5210_detach
7. ar5k_ar5210_phy_disable
8. ar5k_ar5210_reset
9. ar5k_ar5210_set_def_antenna
10. ar5k_ar5210_get_def_antenna
11. ar5k_ar5210_set_opmode
12. ar5k_ar5210_calibrate
13. ar5k_ar5210_do_calibrate
14. ar5k_ar5210_noise_floor
15. ar5k_ar5210_update_tx_triglevel
16. ar5k_ar5210_setup_tx_queue
17. ar5k_ar5210_setup_tx_queueprops
18. ar5k_ar5210_get_tx_queueprops
19. ar5k_ar5210_release_tx_queue
20. ar5k_ar5210_init_tx_queue
21. ar5k_ar5210_reset_tx_queue
22. ar5k_ar5210_get_tx_buf
23. ar5k_ar5210_put_tx_buf
24. ar5k_ar5210_num_tx_pending
25. ar5k_ar5210_tx_start
26. ar5k_ar5210_stop_tx_dma
27. ar5k_ar5210_setup_tx_desc
28. ar5k_ar5210_fill_tx_desc
29. ar5k_ar5210_setup_xtx_desc
30. ar5k_ar5210_proc_tx_desc
31. ar5k_ar5210_has_veol
32. ar5k_ar5210_get_rx_buf
33. ar5k_ar5210_put_rx_buf
34. ar5k_ar5210_start_rx
35. ar5k_ar5210_stop_rx_dma
36. ar5k_ar5210_start_rx_pcu
37. ar5k_ar5210_stop_pcu_recv
38. ar5k_ar5210_set_mcast_filter
39. ar5k_ar5210_set_mcast_filterindex
40. ar5k_ar5210_clear_mcast_filter_idx
41. ar5k_ar5210_get_rx_filter
42. ar5k_ar5210_set_rx_filter
43. ar5k_ar5210_setup_rx_desc
44. ar5k_ar5210_proc_rx_desc
45. ar5k_ar5210_set_rx_signal
46. ar5k_ar5210_dump_state
47. ar5k_ar5210_get_diag_state
48. ar5k_ar5210_get_lladdr
49. ar5k_ar5210_set_lladdr
50. ar5k_ar5210_set_regdomain
51. ar5k_ar5210_set_ledstate
52. ar5k_ar5210_set_associd
53. ar5k_ar5210_set_bssid_mask
54. ar5k_ar5210_set_gpio_output
55. ar5k_ar5210_set_gpio_input
56. ar5k_ar5210_get_gpio
57. ar5k_ar5210_set_gpio
58. ar5k_ar5210_set_gpio_intr
59. ar5k_ar5210_get_tsf32
60. ar5k_ar5210_get_tsf64
61. ar5k_ar5210_reset_tsf
62. ar5k_ar5210_get_regdomain
63. ar5k_ar5210_detect_card_present
64. ar5k_ar5210_update_mib_counters
65. ar5k_ar5210_get_rf_gain
66. ar5k_ar5210_set_slot_time
67. ar5k_ar5210_get_slot_time
68. ar5k_ar5210_set_ack_timeout
69. ar5k_ar5210_get_ack_timeout
70. ar5k_ar5210_set_cts_timeout
71. ar5k_ar5210_get_cts_timeout
72. ar5k_ar5210_is_cipher_supported
73. ar5k_ar5210_get_keycache_size
74. ar5k_ar5210_reset_key
75. ar5k_ar5210_is_key_valid
76. ar5k_ar5210_set_key
77. ar5k_ar5210_set_key_lladdr
78. ar5k_ar5210_set_power
79. ar5k_ar5210_get_power_mode
80. ar5k_ar5210_query_pspoll_support
81. ar5k_ar5210_init_pspoll
82. ar5k_ar5210_enable_pspoll
83. ar5k_ar5210_disable_pspoll
84. ar5k_ar5210_init_beacon
85. ar5k_ar5210_set_beacon_timers
86. ar5k_ar5210_reset_beacon
87. ar5k_ar5210_wait_for_beacon
88. ar5k_ar5210_is_intr_pending
89. ar5k_ar5210_get_isr
90. ar5k_ar5210_get_intr
91. ar5k_ar5210_set_intr
92. ar5k_ar5210_get_capabilities
93. ar5k_ar5210_radar_alert
94. ar5k_ar5210_eeprom_is_busy
95. ar5k_ar5210_eeprom_read
96. ar5k_ar5210_eeprom_write
97. ar5k_ar5210_set_txpower_limit

    1 /*     $OpenBSD: ar5210.c,v 1.39 2007/04/10 17:47:55 miod Exp $        */
    3 /*
    4  * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org>
    5  *
    6  * Permission to use, copy, modify, and distribute this software for any
    7  * purpose with or without fee is hereby granted, provided that the above
    8  * copyright notice and this permission notice appear in all copies.
    9  *
   10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
   13  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
   14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
   15  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
   16  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
   17  */
   19 /*
   20  * HAL interface for the Atheros AR5000 Wireless LAN chipset
   21  * (AR5210 + AR5110).
   22  */
   24 #include <dev/ic/ar5xxx.h>
   25 #include <dev/ic/ar5210reg.h>
   26 #include <dev/ic/ar5210var.h>
HAL_BOOL         ar5k_ar5210_nic_reset(struct ath_hal *, u_int32_t);
HAL_BOOL         ar5k_ar5210_nic_wakeup(struct ath_hal *, HAL_BOOL, HAL_BOOL);
   30 void             ar5k_ar5210_init_tx_queue(struct ath_hal *, u_int, HAL_BOOL);
   31 const void       ar5k_ar5210_fill(struct ath_hal *);
HAL_BOOL         ar5k_ar5210_do_calibrate(struct ath_hal *, HAL_CHANNEL *);
HAL_BOOL         ar5k_ar5210_noise_floor(struct ath_hal *, HAL_CHANNEL *);
   35 /*
   36  * Initial register setting for the AR5210
   37  */
   38 static const struct ar5k_ini ar5210_ini[] =
AR5K_AR5210_INI;
AR5K_HAL_FUNCTIONS(extern, ar5k_ar5210,);
   43 const void
ar5k_ar5210_fill(struct ath_hal *hal)
   45 {
hal->ah_magic = AR5K_AR5210_MAGIC;
   48         /*
   49          * Init/Exit functions
   50          */
AR5K_HAL_FUNCTION(hal, ar5210, get_rate_table);
AR5K_HAL_FUNCTION(hal, ar5210, detach);
   54         /*
   55          * Reset functions
   56          */
AR5K_HAL_FUNCTION(hal, ar5210, reset);
AR5K_HAL_FUNCTION(hal, ar5210, set_opmode);
AR5K_HAL_FUNCTION(hal, ar5210, calibrate);
   61         /*
   62          * TX functions
   63          */
AR5K_HAL_FUNCTION(hal, ar5210, update_tx_triglevel);
AR5K_HAL_FUNCTION(hal, ar5210, setup_tx_queue);
AR5K_HAL_FUNCTION(hal, ar5210, setup_tx_queueprops);
AR5K_HAL_FUNCTION(hal, ar5210, release_tx_queue);
AR5K_HAL_FUNCTION(hal, ar5210, reset_tx_queue);
AR5K_HAL_FUNCTION(hal, ar5210, get_tx_buf);
AR5K_HAL_FUNCTION(hal, ar5210, put_tx_buf);
AR5K_HAL_FUNCTION(hal, ar5210, tx_start);
AR5K_HAL_FUNCTION(hal, ar5210, stop_tx_dma);
AR5K_HAL_FUNCTION(hal, ar5210, setup_tx_desc);
AR5K_HAL_FUNCTION(hal, ar5210, setup_xtx_desc);
AR5K_HAL_FUNCTION(hal, ar5210, fill_tx_desc);
AR5K_HAL_FUNCTION(hal, ar5210, proc_tx_desc);
AR5K_HAL_FUNCTION(hal, ar5210, has_veol);
   79         /*
   80          * RX functions
   81          */
AR5K_HAL_FUNCTION(hal, ar5210, get_rx_buf);
AR5K_HAL_FUNCTION(hal, ar5210, put_rx_buf);
AR5K_HAL_FUNCTION(hal, ar5210, start_rx);
AR5K_HAL_FUNCTION(hal, ar5210, stop_rx_dma);
AR5K_HAL_FUNCTION(hal, ar5210, start_rx_pcu);
AR5K_HAL_FUNCTION(hal, ar5210, stop_pcu_recv);
AR5K_HAL_FUNCTION(hal, ar5210, set_mcast_filter);
AR5K_HAL_FUNCTION(hal, ar5210, set_mcast_filterindex);
AR5K_HAL_FUNCTION(hal, ar5210, clear_mcast_filter_idx);
AR5K_HAL_FUNCTION(hal, ar5210, get_rx_filter);
AR5K_HAL_FUNCTION(hal, ar5210, set_rx_filter);
AR5K_HAL_FUNCTION(hal, ar5210, setup_rx_desc);
AR5K_HAL_FUNCTION(hal, ar5210, proc_rx_desc);
AR5K_HAL_FUNCTION(hal, ar5210, set_rx_signal);
   97         /*
   98          * Misc functions
   99          */
AR5K_HAL_FUNCTION(hal, ar5210, dump_state);
AR5K_HAL_FUNCTION(hal, ar5210, get_diag_state);
AR5K_HAL_FUNCTION(hal, ar5210, get_lladdr);
AR5K_HAL_FUNCTION(hal, ar5210, set_lladdr);
AR5K_HAL_FUNCTION(hal, ar5210, set_regdomain);
AR5K_HAL_FUNCTION(hal, ar5210, set_ledstate);
AR5K_HAL_FUNCTION(hal, ar5210, set_associd);
AR5K_HAL_FUNCTION(hal, ar5210, set_gpio_input);
AR5K_HAL_FUNCTION(hal, ar5210, set_gpio_output);
AR5K_HAL_FUNCTION(hal, ar5210, get_gpio);
AR5K_HAL_FUNCTION(hal, ar5210, set_gpio);
AR5K_HAL_FUNCTION(hal, ar5210, set_gpio_intr);
AR5K_HAL_FUNCTION(hal, ar5210, get_tsf32);
AR5K_HAL_FUNCTION(hal, ar5210, get_tsf64);
AR5K_HAL_FUNCTION(hal, ar5210, reset_tsf);
AR5K_HAL_FUNCTION(hal, ar5210, get_regdomain);
AR5K_HAL_FUNCTION(hal, ar5210, detect_card_present);
AR5K_HAL_FUNCTION(hal, ar5210, update_mib_counters);
AR5K_HAL_FUNCTION(hal, ar5210, get_rf_gain);
AR5K_HAL_FUNCTION(hal, ar5210, set_slot_time);
AR5K_HAL_FUNCTION(hal, ar5210, get_slot_time);
AR5K_HAL_FUNCTION(hal, ar5210, set_ack_timeout);
AR5K_HAL_FUNCTION(hal, ar5210, get_ack_timeout);
AR5K_HAL_FUNCTION(hal, ar5210, set_cts_timeout);
AR5K_HAL_FUNCTION(hal, ar5210, get_cts_timeout);
  126         /*
  127          * Key table (WEP) functions
  128          */
AR5K_HAL_FUNCTION(hal, ar5210, is_cipher_supported);
AR5K_HAL_FUNCTION(hal, ar5210, get_keycache_size);
AR5K_HAL_FUNCTION(hal, ar5210, reset_key);
AR5K_HAL_FUNCTION(hal, ar5210, is_key_valid);
AR5K_HAL_FUNCTION(hal, ar5210, set_key);
AR5K_HAL_FUNCTION(hal, ar5210, set_key_lladdr);
  136         /*
  137          * Power management functions
  138          */
AR5K_HAL_FUNCTION(hal, ar5210, set_power);
AR5K_HAL_FUNCTION(hal, ar5210, get_power_mode);
AR5K_HAL_FUNCTION(hal, ar5210, query_pspoll_support);
AR5K_HAL_FUNCTION(hal, ar5210, init_pspoll);
AR5K_HAL_FUNCTION(hal, ar5210, enable_pspoll);
AR5K_HAL_FUNCTION(hal, ar5210, disable_pspoll);
  146         /*
  147          * Beacon functions
  148          */
AR5K_HAL_FUNCTION(hal, ar5210, init_beacon);
AR5K_HAL_FUNCTION(hal, ar5210, set_beacon_timers);
AR5K_HAL_FUNCTION(hal, ar5210, reset_beacon);
AR5K_HAL_FUNCTION(hal, ar5210, wait_for_beacon);
  154         /*
  155          * Interrupt functions
  156          */
AR5K_HAL_FUNCTION(hal, ar5210, is_intr_pending);
AR5K_HAL_FUNCTION(hal, ar5210, get_isr);
AR5K_HAL_FUNCTION(hal, ar5210, get_intr);
AR5K_HAL_FUNCTION(hal, ar5210, set_intr);
  162         /*
  163          * Chipset functions (ar5k-specific, non-HAL)
  164          */
AR5K_HAL_FUNCTION(hal, ar5210, get_capabilities);
AR5K_HAL_FUNCTION(hal, ar5210, radar_alert);
  168         /*
  169          * EEPROM access
  170          */
AR5K_HAL_FUNCTION(hal, ar5210, eeprom_is_busy);
AR5K_HAL_FUNCTION(hal, ar5210, eeprom_read);
AR5K_HAL_FUNCTION(hal, ar5210, eeprom_write);
  175         /*
  176          * Unused functions or functions not implemented
  177          */
AR5K_HAL_FUNCTION(hal, ar5210, set_bssid_mask);
AR5K_HAL_FUNCTION(hal, ar5210, get_tx_queueprops);
AR5K_HAL_FUNCTION(hal, ar5210, num_tx_pending);
AR5K_HAL_FUNCTION(hal, ar5210, phy_disable);
AR5K_HAL_FUNCTION(hal, ar5210, set_txpower_limit);
AR5K_HAL_FUNCTION(hal, ar5210, set_def_antenna);
AR5K_HAL_FUNCTION(hal, ar5210, get_def_antenna);
  185 #ifdef notyet
AR5K_HAL_FUNCTION(hal, ar5210, set_capability);
AR5K_HAL_FUNCTION(hal, ar5210, proc_mib_event);
AR5K_HAL_FUNCTION(hal, ar5210, get_tx_inter_queue);
  189 #endif
  190 }
  192 struct ath_hal *
ar5k_ar5210_attach(u_int16_t device, void *sc, bus_space_tag_t st,
bus_space_handle_t sh, int *status)
  195 {
  196         int i;
  197         struct ath_hal *hal = (struct ath_hal*) sc;
u_int8_t mac[IEEE80211_ADDR_LEN];
u_int32_t srev;
ar5k_ar5210_fill(hal);
  203         /* Bring device out of sleep and reset its units */
  204         if (ar5k_ar5210_nic_wakeup(hal, AH_FALSE, AH_TRUE) != AH_TRUE)
  205                 return (NULL);
  207         /* Get MAC, PHY and RADIO revisions */
srev = AR5K_REG_READ(AR5K_AR5210_SREV);
hal->ah_mac_srev = srev;
hal->ah_mac_version = AR5K_REG_MS(srev, AR5K_AR5210_SREV_VER);
hal->ah_mac_revision = AR5K_REG_MS(srev, AR5K_AR5210_SREV_REV);
hal->ah_phy_revision = AR5K_REG_READ(AR5K_AR5210_PHY_CHIP_ID) &
  213             0x00ffffffff;
  215         /* ...wait until PHY is ready and read RADIO revision */
AR5K_REG_WRITE(AR5K_AR5210_PHY(0x34), 0x00001c16);
  217         for (i = 0; i < 4; i++)
AR5K_REG_WRITE(AR5K_AR5210_PHY(0x20), 0x00010000);
hal->ah_radio_5ghz_revision = (u_int16_t)
  220             (ar5k_bitswap((AR5K_REG_READ(AR5K_AR5210_PHY(256) >> 28) & 0xf), 4)
  221                 + 1);
hal->ah_radio_2ghz_revision = 0;
  224         /* Identify the chipset */
hal->ah_version = AR5K_AR5210;
hal->ah_radio = AR5K_AR5110;
hal->ah_phy = AR5K_AR5210_PHY(0);
bcopy(etherbroadcastaddr, mac, IEEE80211_ADDR_LEN);
ar5k_ar5210_set_associd(hal, mac, 0, 0);
ar5k_ar5210_get_lladdr(hal, mac);
ar5k_ar5210_set_opmode(hal);
  234         return (hal);
  235 }
HAL_BOOL
ar5k_ar5210_nic_reset(struct ath_hal *hal, u_int32_t val)
  239 {
HAL_BOOL ret = AH_FALSE;
u_int32_t mask = val ? val : ~0;
  243         /*
  244          * Reset the device and wait until success
  245          */
AR5K_REG_WRITE(AR5K_AR5210_RC, val);
  248         /* Wait at least 128 PCI clocks */
AR5K_DELAY(15);
val &=
AR5K_AR5210_RC_PCU | AR5K_AR5210_RC_MAC |
AR5K_AR5210_RC_PHY | AR5K_AR5210_RC_DMA;
mask &=
AR5K_AR5210_RC_PCU | AR5K_AR5210_RC_MAC |
AR5K_AR5210_RC_PHY | AR5K_AR5210_RC_DMA;
ret = ar5k_register_timeout(hal, AR5K_AR5210_RC, mask, val, AH_FALSE);
  261         /*
  262          * Reset configuration register
  263          */
  264         if ((val & AR5K_AR5210_RC_MAC) == 0) {
AR5K_REG_WRITE(AR5K_AR5210_CFG, AR5K_AR5210_INIT_CFG);
  266         }
  268         return (ret);
  269 }
HAL_BOOL
ar5k_ar5210_nic_wakeup(struct ath_hal *hal, HAL_BOOL turbo, HAL_BOOL initial)
  273 {
  274         /*
  275          * Reset and wakeup the device
  276          */
  278         if (initial == AH_TRUE) {
  279                 /* ...reset hardware */
  280                 if (ar5k_ar5210_nic_reset(hal,
AR5K_AR5210_RC_PCI) == AH_FALSE) {
AR5K_PRINT("failed to reset the PCI chipset\n");
  283                         return (AH_FALSE);
  284                 }
AR5K_DELAY(1000);
  287         }
  289         /* ...wakeup the device */
  290         if (ar5k_ar5210_set_power(hal,
HAL_PM_AWAKE, AH_TRUE, 0) == AH_FALSE) {
AR5K_PRINT("failed to resume the AR5210 chipset\n");
  293                 return (AH_FALSE);
  294         }
  296         /* ...enable Atheros turbo mode if requested */
AR5K_REG_WRITE(AR5K_AR5210_PHY_FC,
turbo == AH_TRUE ? AR5K_AR5210_PHY_FC_TURBO_MODE : 0);
  300         /* ...reset chipset */
  301         if (ar5k_ar5210_nic_reset(hal, AR5K_AR5210_RC_CHIP) == AH_FALSE) {
AR5K_PRINT("failed to reset the AR5210 chipset\n");
  303                 return (AH_FALSE);
  304         }
AR5K_DELAY(1000);
  308         /* ...reset chipset and PCI device */
  309         if (ar5k_ar5210_nic_reset(hal,
AR5K_AR5210_RC_CHIP | AR5K_AR5210_RC_PCI) == AH_FALSE) {
AR5K_PRINT("failed to reset the AR5210 + PCI chipset\n");
  312                 return (AH_FALSE);
  313         }
AR5K_DELAY(2300);
  317         /* ...wakeup (again) */
  318         if (ar5k_ar5210_set_power(hal,
HAL_PM_AWAKE, AH_TRUE, 0) == AH_FALSE) {
AR5K_PRINT("failed to resume the AR5210 (again)\n");
  321                 return (AH_FALSE);
  322         }
  324         /* ...final warm reset */
  325         if (ar5k_ar5210_nic_reset(hal, 0) == AH_FALSE) {
AR5K_PRINT("failed to warm reset the AR5210\n");
  327                 return (AH_FALSE);
  328         }
  330         return (AH_TRUE);
  331 }
  333 const HAL_RATE_TABLE *
  334 ar5k_ar5210_get_rate_table(struct ath_hal *hal, u_int mode)
  335 {
  336         switch (mode) {
  337         case HAL_MODE_11A:
  338                 return (&hal->ah_rt_11a);
  339         case HAL_MODE_TURBO:
  340                 return (&hal->ah_rt_turbo);
  341         case HAL_MODE_11B:
  342         case HAL_MODE_11G:
  343         default:
  344                 return (NULL);
  345         }
  347         return (NULL);
  348 }
  350 void
  351 ar5k_ar5210_detach(struct ath_hal *hal)
  352 {
  353         /*
  354          * Free HAL structure, assume interrupts are down
  355          */
free(hal, M_DEVBUF);
  357 }
HAL_BOOL
  360 ar5k_ar5210_phy_disable(struct ath_hal *hal)
  361 {
AR5K_REG_WRITE(AR5K_AR5210_PHY_ACTIVE, AR5K_AR5210_PHY_DISABLE);
  363         return (AH_TRUE);
  364 }
HAL_BOOL
  367 ar5k_ar5210_reset(struct ath_hal *hal, HAL_OPMODE op_mode, HAL_CHANNEL *channel,
HAL_BOOL change_channel, HAL_STATUS *status)
  369 {
  370         int i;
  372         /* Not used, keep for HAL compatibility */
  373         *status = HAL_OK;
  375         if (ar5k_ar5210_nic_wakeup(hal,
channel->c_channel_flags & IEEE80211_CHAN_T ?
AH_TRUE : AH_FALSE, AH_FALSE) == AH_FALSE)
  378                 return (AH_FALSE);
  380         /*
  381          * Initialize operating mode
  382          */
hal->ah_op_mode = op_mode;
ar5k_ar5210_set_opmode(hal);
  386         /*
  387          * Write initial mode register settings
  388          */
  389         for (i = 0; i < AR5K_ELEMENTS(ar5210_ini); i++) {
  390                 if (change_channel == AH_TRUE &&
ar5210_ini[i].ini_register >= AR5K_AR5210_PCU_MIN &&
ar5210_ini[i].ini_register <= AR5K_AR5210_PCU_MAX)
  393                         continue;
  395                 switch (ar5210_ini[i].ini_mode) {
  396                 case AR5K_INI_READ:
  397                         /* Cleared on read */
AR5K_REG_READ(ar5210_ini[i].ini_register);
  399                         break;
  401                 case AR5K_INI_WRITE:
  402                 default:
AR5K_REG_WRITE(ar5210_ini[i].ini_register,
ar5210_ini[i].ini_value);
  405                 }
  406         }
AR5K_DELAY(1000);
  410         /*
  411          * Set channel and calibrate the PHY
  412          */
  414         /* Disable phy and wait */
AR5K_REG_WRITE(AR5K_AR5210_PHY_ACTIVE, AR5K_AR5210_PHY_DISABLE);
AR5K_DELAY(1000);
  418         if (ar5k_channel(hal, channel) == AH_FALSE)
  419                 return (AH_FALSE);
  421         /*
  422          * Activate phy and wait
  423          */
AR5K_REG_WRITE(AR5K_AR5210_PHY_ACTIVE, AR5K_AR5210_PHY_ENABLE);
AR5K_DELAY(1000);
ar5k_ar5210_do_calibrate(hal, channel);
  428         if (ar5k_ar5210_noise_floor(hal, channel) == AH_FALSE)
  429                 return (AH_FALSE);
  431         /*
  432          * Set RF kill flags if supported by the device (read from the EEPROM)
  433          */
  434         if (AR5K_EEPROM_HDR_RFKILL(hal->ah_capabilities.cap_eeprom.ee_header)) {
ar5k_ar5210_set_gpio_input(hal, 0);
  436                 if ((hal->ah_gpio[0] = ar5k_ar5210_get_gpio(hal, 0)) == 0) {
ar5k_ar5210_set_gpio_intr(hal, 0, 1);
  438                 } else {
ar5k_ar5210_set_gpio_intr(hal, 0, 0);
  440                 }
  441         }
  443         /*
  444          * Reset queues and start beacon timers at the end of the reset routine
  445          */
  446         for (i = 0; i < hal->ah_capabilities.cap_queues.q_tx_num; i++) {
  447                 if (ar5k_ar5210_reset_tx_queue(hal, i) == AH_FALSE) {
AR5K_PRINTF("failed to reset TX queue #%d\n", i);
  449                         return (AH_FALSE);
  450                 }
  451         }
AR5K_REG_DISABLE_BITS(AR5K_AR5210_BEACON,
AR5K_AR5210_BEACON_EN | AR5K_AR5210_BEACON_RESET_TSF);
  456         return (AH_TRUE);
  457 }
  459 void
  460 ar5k_ar5210_set_def_antenna(struct ath_hal *hal, u_int ant)
  461 {
  462         /* Not available */
  463         return;
  464 }
u_int
  467 ar5k_ar5210_get_def_antenna(struct ath_hal *hal)
  468 {
  469         return (0);
  470 }
  472 void
ar5k_ar5210_set_opmode(struct ath_hal *hal)
  474 {
u_int32_t pcu_reg, beacon_reg, low_id, high_id;
beacon_reg = 0;
pcu_reg = 0;
  480         switch (hal->ah_op_mode) {
  481         case IEEE80211_M_STA:
pcu_reg |= AR5K_AR5210_STA_ID1_NO_PSPOLL |
AR5K_AR5210_STA_ID1_DESC_ANTENNA |
AR5K_AR5210_STA_ID1_PWR_SV;
  485                 break;
  487         case IEEE80211_M_IBSS:
pcu_reg |= AR5K_AR5210_STA_ID1_ADHOC |
AR5K_AR5210_STA_ID1_NO_PSPOLL |
AR5K_AR5210_STA_ID1_DESC_ANTENNA;
beacon_reg |= AR5K_AR5210_BCR_ADHOC;
  492                 break;
  494         case IEEE80211_M_HOSTAP:
pcu_reg |= AR5K_AR5210_STA_ID1_AP |
AR5K_AR5210_STA_ID1_NO_PSPOLL |
AR5K_AR5210_STA_ID1_DESC_ANTENNA;
beacon_reg |= AR5K_AR5210_BCR_AP;
  499                 break;
  501         case IEEE80211_M_MONITOR:
pcu_reg |= AR5K_AR5210_STA_ID1_NO_PSPOLL;
  503                 break;
  505         default:
  506                 return;
  507         }
  509         /*
  510          * Set PCU and BCR registers
  511          */
low_id = AR5K_LOW_ID(hal->ah_sta_id);
high_id = AR5K_HIGH_ID(hal->ah_sta_id);
AR5K_REG_WRITE(AR5K_AR5210_STA_ID0, low_id);
AR5K_REG_WRITE(AR5K_AR5210_STA_ID1, pcu_reg | high_id);
AR5K_REG_WRITE(AR5K_AR5210_BCR, beacon_reg);
  518         return;
  519 }
HAL_BOOL
  522 ar5k_ar5210_calibrate(struct ath_hal *hal, HAL_CHANNEL *channel)
  523 {
HAL_BOOL ret = AH_TRUE;
u_int32_t phy_sig, phy_agc, phy_sat, beacon;
  527 #define AGC_DISABLE     {                                               \
AR5K_REG_ENABLE_BITS(AR5K_AR5210_PHY_AGC,                       \
AR5K_AR5210_PHY_AGC_DISABLE);                               \
AR5K_DELAY(10);                                                 \
  531 }
  533 #define AGC_ENABLE      {                                               \
AR5K_REG_DISABLE_BITS(AR5K_AR5210_PHY_AGC,                      \
AR5K_AR5210_PHY_AGC_DISABLE);                               \
  536 }
  538         /*
  539          * Disable beacons and RX/TX queues, wait
  540          */
AR5K_REG_ENABLE_BITS(AR5K_AR5210_DIAG_SW,
AR5K_AR5210_DIAG_SW_DIS_TX | AR5K_AR5210_DIAG_SW_DIS_RX);
beacon = AR5K_REG_READ(AR5K_AR5210_BEACON);
AR5K_REG_WRITE(AR5K_AR5210_BEACON, beacon & ~AR5K_AR5210_BEACON_EN);
AR5K_DELAY(2300);
  548         /*
  549          * Set the channel (with AGC turned off)
  550          */
AGC_DISABLE;
ret = ar5k_channel(hal, channel);
  554         /*
  555          * Activate PHY and wait
  556          */
AR5K_REG_WRITE(AR5K_AR5210_PHY_ACTIVE, AR5K_AR5210_PHY_ENABLE);
AR5K_DELAY(1000);
AGC_ENABLE;
  562         if (ret == AH_FALSE)
  563                 return (ret);
  565         /*
  566          * Calibrate the radio chip
  567          */
  569         /* Remember normal state */
phy_sig = AR5K_REG_READ(AR5K_AR5210_PHY_SIG);
phy_agc = AR5K_REG_READ(AR5K_AR5210_PHY_AGCCOARSE);
phy_sat = AR5K_REG_READ(AR5K_AR5210_PHY_ADCSAT);
  574         /* Update radio registers */
AR5K_REG_WRITE(AR5K_AR5210_PHY_SIG,
  576             (phy_sig & ~(AR5K_AR5210_PHY_SIG_FIRPWR)) |
AR5K_REG_SM(-1, AR5K_AR5210_PHY_SIG_FIRPWR));
AR5K_REG_WRITE(AR5K_AR5210_PHY_AGCCOARSE,
  580             (phy_agc & ~(AR5K_AR5210_PHY_AGCCOARSE_HI |
AR5K_AR5210_PHY_AGCCOARSE_LO)) |
AR5K_REG_SM(-1, AR5K_AR5210_PHY_AGCCOARSE_HI) |
AR5K_REG_SM(-127, AR5K_AR5210_PHY_AGCCOARSE_LO));
AR5K_REG_WRITE(AR5K_AR5210_PHY_ADCSAT,
  586             (phy_sat & ~(AR5K_AR5210_PHY_ADCSAT_ICNT |
AR5K_AR5210_PHY_ADCSAT_THR)) |
AR5K_REG_SM(2, AR5K_AR5210_PHY_ADCSAT_ICNT) |
AR5K_REG_SM(12, AR5K_AR5210_PHY_ADCSAT_THR));
AR5K_DELAY(20);
AGC_DISABLE;
AR5K_REG_WRITE(AR5K_AR5210_PHY_RFSTG, AR5K_AR5210_PHY_RFSTG_DISABLE);
AGC_ENABLE;
AR5K_DELAY(1000);
ret = ar5k_ar5210_do_calibrate(hal, channel);
  601         /* Reset to normal state */
AR5K_REG_WRITE(AR5K_AR5210_PHY_SIG, phy_sig);
AR5K_REG_WRITE(AR5K_AR5210_PHY_AGCCOARSE, phy_agc);
AR5K_REG_WRITE(AR5K_AR5210_PHY_ADCSAT, phy_sat);
  606         if (ret == AH_FALSE)
  607                 return (AH_FALSE);
  609         if (ar5k_ar5210_noise_floor(hal, channel) == AH_FALSE)
  610                 return (AH_FALSE);
  612         /*
  613          * Re-enable RX/TX and beacons
  614          */
AR5K_REG_DISABLE_BITS(AR5K_AR5210_DIAG_SW,
AR5K_AR5210_DIAG_SW_DIS_TX | AR5K_AR5210_DIAG_SW_DIS_RX);
AR5K_REG_WRITE(AR5K_AR5210_BEACON, beacon);
  619 #undef AGC_ENABLE
  620 #undef AGC_DISABLE
  622         return (AH_TRUE);
  623 }
HAL_BOOL
ar5k_ar5210_do_calibrate(struct ath_hal *hal, HAL_CHANNEL *channel)
  627 {
  628         /*
  629          * Enable calibration and wait until completion
  630          */
AR5K_REG_ENABLE_BITS(AR5K_AR5210_PHY_AGCCTL,
AR5K_AR5210_PHY_AGCCTL_CAL);
  634         if (ar5k_register_timeout(hal, AR5K_AR5210_PHY_AGCCTL,
AR5K_AR5210_PHY_AGCCTL_CAL, 0, AH_FALSE) == AH_FALSE) {
AR5K_PRINTF("calibration timeout (%uMHz)\n",
channel->c_channel);
  638                 return (AH_FALSE);
  639         }
  641         return (AH_TRUE);
  642 }
HAL_BOOL
ar5k_ar5210_noise_floor(struct ath_hal *hal, HAL_CHANNEL *channel)
  646 {
  647         int i;
u_int32_t noise_floor;
  650         /*
  651          * Enable noise floor calibration and wait until completion
  652          */
AR5K_REG_ENABLE_BITS(AR5K_AR5210_PHY_AGCCTL,
AR5K_AR5210_PHY_AGCCTL_NF);
  656         if (ar5k_register_timeout(hal, AR5K_AR5210_PHY_AGCCTL,
AR5K_AR5210_PHY_AGCCTL_NF, 0, AH_FALSE) == AH_FALSE) {
AR5K_PRINTF("noise floor calibration timeout (%uMHz)\n",
channel->c_channel);
  660                 return (AH_FALSE);
  661         }
  663         /* wait until the noise floor is calibrated */
  664         for (i = 20; i > 0; i--) {
AR5K_DELAY(1000);
noise_floor = AR5K_REG_READ(AR5K_AR5210_PHY_NF);
  667                 if (AR5K_AR5210_PHY_NF_RVAL(noise_floor) &
AR5K_AR5210_PHY_NF_ACTIVE)
noise_floor = AR5K_AR5210_PHY_NF_AVAL(noise_floor);
  670                 if (noise_floor <= AR5K_TUNE_NOISE_FLOOR)
  671                         break;
  672         }
  674         if (noise_floor > AR5K_TUNE_NOISE_FLOOR) {
AR5K_PRINTF("noise floor calibration failed (%uMHz)\n",
channel->c_channel);
  677                 return (AH_FALSE);
  678         }
  680         return (AH_TRUE);
  681 }
  683 /*
  684  * Transmit functions
  685  */
HAL_BOOL
  688 ar5k_ar5210_update_tx_triglevel(struct ath_hal *hal, HAL_BOOL increase)
  689 {
u_int32_t trigger_level;
HAL_BOOL status = AH_FALSE;
  693         /*
  694          * Disable interrupts by setting the mask
  695          */
AR5K_REG_DISABLE_BITS(AR5K_AR5210_IMR, HAL_INT_GLOBAL);
trigger_level = AR5K_REG_READ(AR5K_AR5210_TRIG_LVL);
  700         if (increase == AH_FALSE) {
  701                 if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES)
  702                         goto done;
  703         } else {
trigger_level +=
  705                     ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2);
  706         }
  708         /*
  709          * Update trigger level on success
  710          */
AR5K_REG_WRITE(AR5K_AR5210_TRIG_LVL, trigger_level);
status = AH_TRUE;
done:
  715         /*
  716          * Restore interrupt mask
  717          */
AR5K_REG_ENABLE_BITS(AR5K_AR5210_IMR, HAL_INT_GLOBAL);
  720         return (status);
  721 }
  723 int
  724 ar5k_ar5210_setup_tx_queue(struct ath_hal *hal, HAL_TX_QUEUE queue_type,
  725     const HAL_TXQ_INFO *queue_info)
  726 {
u_int queue;
  729         /*
  730          * Get queue by type
  731          */
  732         switch (queue_type) {
  733         case HAL_TX_QUEUE_DATA:
queue = 0;
  735                 break;
  736         case HAL_TX_QUEUE_BEACON:
  737         case HAL_TX_QUEUE_CAB:
queue = 1;
  739                 break;
  740         default:
  741                 return (-1);
  742         }
  744         /*
  745          * Setup internal queue structure
  746          */
bzero(&hal->ah_txq[queue], sizeof(HAL_TXQ_INFO));
hal->ah_txq[queue].tqi_type = queue_type;
  750         if (queue_info != NULL) {
  751                 if (ar5k_ar5210_setup_tx_queueprops(hal,
queue, queue_info) != AH_TRUE)
  753                         return (-1);
  754         }
  756         return (queue);
  757 }
HAL_BOOL
ar5k_ar5210_setup_tx_queueprops(struct ath_hal *hal, int queue,
  761     const HAL_TXQ_INFO *queue_info)
  762 {
AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
  765         if (hal->ah_txq[queue].tqi_type == HAL_TX_QUEUE_INACTIVE)
  766                 return (AH_FALSE);
hal->ah_txq[queue].tqi_aifs = queue_info->tqi_aifs;
hal->ah_txq[queue].tqi_cw_max = queue_info->tqi_cw_max;
hal->ah_txq[queue].tqi_cw_min = queue_info->tqi_cw_min;
hal->ah_txq[queue].tqi_flags = queue_info->tqi_flags;
  773         return (AH_TRUE);
  774 }
HAL_BOOL
  777 ar5k_ar5210_get_tx_queueprops(struct ath_hal *hal, int queue,
HAL_TXQ_INFO *queue_info)
  779 {
AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
bcopy(&hal->ah_txq[queue], queue_info, sizeof(HAL_TXQ_INFO));
  782         return (AH_TRUE);
  783 }
HAL_BOOL
  786 ar5k_ar5210_release_tx_queue(struct ath_hal *hal, u_int queue)
  787 {
AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
  790         /* This queue will be skipped in further operations */
hal->ah_txq[queue].tqi_type = HAL_TX_QUEUE_INACTIVE;
  793         return (AH_FALSE);
  794 }
  796 void
ar5k_ar5210_init_tx_queue(struct ath_hal *hal, u_int aifs, HAL_BOOL turbo)
  798 {
  799         int i;
  800         struct {
u_int16_t mode_register;
u_int32_t mode_base, mode_turbo;
  803         } initial[] = AR5K_AR5210_INI_MODE(aifs);
  805         /*
  806          * Write initial mode register settings
  807          */
  808         for (i = 0; i < AR5K_ELEMENTS(initial); i++)
AR5K_REG_WRITE((u_int32_t)initial[i].mode_register,
turbo == AH_TRUE ?
initial[i].mode_turbo : initial[i].mode_base);
  812 }
HAL_BOOL
ar5k_ar5210_reset_tx_queue(struct ath_hal *hal, u_int queue)
  816 {
u_int32_t cw_min, retry_lg, retry_sh;
HAL_TXQ_INFO *tq;
AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
tq = &hal->ah_txq[queue];
  824         /* Only handle data queues, others will be ignored */
  825         if (tq->tqi_type != HAL_TX_QUEUE_DATA)
  826                 return (AH_TRUE);
  828         /* Set turbo/base mode parameters */
ar5k_ar5210_init_tx_queue(hal, hal->ah_aifs + tq->tqi_aifs,
hal->ah_turbo == AH_TRUE ? AH_TRUE : AH_FALSE);
  832         /*
  833          * Set retry limits
  834          */
  835         if (hal->ah_software_retry == AH_TRUE) {
  836                 /* XXX Need to test this */
retry_lg = hal->ah_limit_tx_retries;
retry_sh = retry_lg =
retry_lg > AR5K_AR5210_RETRY_LMT_SH_RETRY ?
AR5K_AR5210_RETRY_LMT_SH_RETRY : retry_lg;
  841         } else {
retry_lg = AR5K_INIT_LG_RETRY;
retry_sh = AR5K_INIT_SH_RETRY;
  844         }
  846         /*
  847          * Set initial content window (cw_min/cw_max)
  848          */
cw_min = 1;
  850         while (cw_min < hal->ah_cw_min)
cw_min = (cw_min << 1) | 1;
cw_min = tq->tqi_cw_min < 0 ?
  854             (cw_min >> (-tq->tqi_cw_min)) :
  855             ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1);
  857         /* Commit values */
AR5K_REG_WRITE(AR5K_AR5210_RETRY_LMT,
  859             (cw_min << AR5K_AR5210_RETRY_LMT_CW_MIN_S)
  860             | AR5K_REG_SM(AR5K_INIT_SLG_RETRY, AR5K_AR5210_RETRY_LMT_SLG_RETRY)
  861             | AR5K_REG_SM(AR5K_INIT_SSH_RETRY, AR5K_AR5210_RETRY_LMT_SSH_RETRY)
  862             | AR5K_REG_SM(retry_lg, AR5K_AR5210_RETRY_LMT_LG_RETRY)
  863             | AR5K_REG_SM(retry_sh, AR5K_AR5210_RETRY_LMT_SH_RETRY));
  865         return (AH_TRUE);
  866 }
u_int32_t
  869 ar5k_ar5210_get_tx_buf(struct ath_hal *hal, u_int queue)
  870 {
u_int16_t tx_reg;
AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
  875         /*
  876          * Get the transmit queue descriptor pointer register by type
  877          */
  878         switch (hal->ah_txq[queue].tqi_type) {
  879         case HAL_TX_QUEUE_DATA:
tx_reg = AR5K_AR5210_TXDP0;
  881                 break;
  882         case HAL_TX_QUEUE_BEACON:
  883         case HAL_TX_QUEUE_CAB:
tx_reg = AR5K_AR5210_TXDP1;
  885                 break;
  886         default:
  887                 return (0xffffffff);
  888         }
  890         return (AR5K_REG_READ(tx_reg));
  891 }
HAL_BOOL
  894 ar5k_ar5210_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr)
  895 {
u_int16_t tx_reg;
AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
  900         /*
  901          * Get the transmit queue descriptor pointer register by type
  902          */
  903         switch (hal->ah_txq[queue].tqi_type) {
  904         case HAL_TX_QUEUE_DATA:
tx_reg = AR5K_AR5210_TXDP0;
  906                 break;
  907         case HAL_TX_QUEUE_BEACON:
  908         case HAL_TX_QUEUE_CAB:
tx_reg = AR5K_AR5210_TXDP1;
  910                 break;
  911         default:
  912                 return (AH_FALSE);
  913         }
  915         /* Set descriptor pointer */
AR5K_REG_WRITE(tx_reg, phys_addr);
  918         return (AH_TRUE);
  919 }
u_int32_t
  922 ar5k_ar5210_num_tx_pending(struct ath_hal *hal, u_int queue)
  923 {
  924         return (AH_FALSE);
  925 }
HAL_BOOL
  928 ar5k_ar5210_tx_start(struct ath_hal *hal, u_int queue)
  929 {
u_int32_t tx_queue;
AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
tx_queue = AR5K_REG_READ(AR5K_AR5210_CR);
  936         /*
  937          * Set the queue type
  938          */
  939         switch (hal->ah_txq[queue].tqi_type) {
  940         case HAL_TX_QUEUE_DATA:
tx_queue |= AR5K_AR5210_CR_TXE0 & ~AR5K_AR5210_CR_TXD0;
  942                 break;
  944         case HAL_TX_QUEUE_BEACON:
tx_queue |= AR5K_AR5210_CR_TXE1 & ~AR5K_AR5210_CR_TXD1;
AR5K_REG_WRITE(AR5K_AR5210_BSR,
AR5K_AR5210_BCR_TQ1V | AR5K_AR5210_BCR_BDMAE);
  948                 break;
  950         case HAL_TX_QUEUE_CAB:
tx_queue |= AR5K_AR5210_CR_TXE1 & ~AR5K_AR5210_CR_TXD1;
AR5K_REG_WRITE(AR5K_AR5210_BSR,
AR5K_AR5210_BCR_TQ1FV | AR5K_AR5210_BCR_TQ1V |
AR5K_AR5210_BCR_BDMAE);
  955                 break;
  957         default:
  958                 return (AH_FALSE);
  959         }
  961         /* Start queue */
AR5K_REG_WRITE(AR5K_AR5210_CR, tx_queue);
  964         return (AH_TRUE);
  965 }
HAL_BOOL
  968 ar5k_ar5210_stop_tx_dma(struct ath_hal *hal, u_int queue)
  969 {
u_int32_t tx_queue;
AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
tx_queue = AR5K_REG_READ(AR5K_AR5210_CR);
  976         /*
  977          * Set by queue type
  978          */
  979         switch (hal->ah_txq[queue].tqi_type) {
  980         case HAL_TX_QUEUE_DATA:
tx_queue |= AR5K_AR5210_CR_TXD0 & ~AR5K_AR5210_CR_TXE0;
  982                 break;
  984         case HAL_TX_QUEUE_BEACON:
  985         case HAL_TX_QUEUE_CAB:
  986                 /* XXX Fix me... */
tx_queue |= AR5K_AR5210_CR_TXD1 & ~AR5K_AR5210_CR_TXD1;
AR5K_REG_WRITE(AR5K_AR5210_BSR, 0);
  989                 break;
  991         default:
  992                 return (AH_FALSE);
  993         }
  995         /* Stop queue */
AR5K_REG_WRITE(AR5K_AR5210_CR, tx_queue);
  998         return (AH_TRUE);
  999 }
HAL_BOOL
 1002 ar5k_ar5210_setup_tx_desc(struct ath_hal *hal, struct ath_desc *desc,
u_int packet_length, u_int header_length, HAL_PKT_TYPE type, u_int tx_power,
u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode,
u_int flags, u_int rtscts_rate, u_int rtscts_duration)
 1006 {
u_int32_t frame_type;
 1008         struct ar5k_ar5210_tx_desc *tx_desc;
tx_desc = (struct ar5k_ar5210_tx_desc*)&desc->ds_ctl0;
 1012         /*
 1013          * Validate input
 1014          */
 1015         if (tx_tries0 == 0)
 1016                 return (AH_FALSE);
 1018         if ((tx_desc->tx_control_0 = (packet_length &
AR5K_AR5210_DESC_TX_CTL0_FRAME_LEN)) != packet_length)
 1020                 return (AH_FALSE);
 1022         if ((tx_desc->tx_control_0 = (header_length &
AR5K_AR5210_DESC_TX_CTL0_HEADER_LEN)) != header_length)
 1024                 return (AH_FALSE);
 1026         if (type == HAL_PKT_TYPE_BEACON || type == HAL_PKT_TYPE_PROBE_RESP)
frame_type = AR5K_AR5210_DESC_TX_FRAME_TYPE_NO_DELAY;
 1028         else if (type == HAL_PKT_TYPE_PIFS)
frame_type = AR5K_AR5210_DESC_TX_FRAME_TYPE_PIFS;
 1030         else
frame_type = type;
tx_desc->tx_control_0 =
AR5K_REG_SM(frame_type, AR5K_AR5210_DESC_TX_CTL0_FRAME_TYPE);
tx_desc->tx_control_0 |=
AR5K_REG_SM(tx_rate0, AR5K_AR5210_DESC_TX_CTL0_XMIT_RATE);
 1038 #define _TX_FLAGS(_c, _flag)                                            \
 1039         if (flags & HAL_TXDESC_##_flag)                                 \
tx_desc->tx_control_##_c |=                             \
AR5K_AR5210_DESC_TX_CTL##_c##_##_flag
_TX_FLAGS(0, CLRDMASK);
_TX_FLAGS(0, INTREQ);
_TX_FLAGS(0, RTSENA);
 1047 #undef _TX_FLAGS
 1049         /*
 1050          * WEP crap
 1051          */
 1052         if (key_index != HAL_TXKEYIX_INVALID) {
tx_desc->tx_control_0 |=
AR5K_AR5210_DESC_TX_CTL0_ENCRYPT_KEY_VALID;
tx_desc->tx_control_1 |=
AR5K_REG_SM(key_index,
AR5K_AR5210_DESC_TX_CTL1_ENCRYPT_KEY_INDEX);
 1058         }
 1060         /*
 1061          * RTS/CTS
 1062          */
 1063         if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
tx_desc->tx_control_1 |=
rtscts_duration & AR5K_AR5210_DESC_TX_CTL1_RTS_DURATION;
 1066         }
 1068         return (AH_TRUE);
 1069 }
HAL_BOOL
 1072 ar5k_ar5210_fill_tx_desc(struct ath_hal *hal, struct ath_desc *desc,
u_int segment_length, HAL_BOOL first_segment, HAL_BOOL last_segment)
 1074 {
 1075         struct ar5k_ar5210_tx_desc *tx_desc;
tx_desc = (struct ar5k_ar5210_tx_desc*)&desc->ds_ctl0;
 1079         /* Clear status descriptor */
bzero(desc->ds_hw, sizeof(desc->ds_hw));
 1082         /* Validate segment length and initialize the descriptor */
 1083         if ((tx_desc->tx_control_1 = (segment_length &
AR5K_AR5210_DESC_TX_CTL1_BUF_LEN)) != segment_length)
 1085                 return (AH_FALSE);
 1087         if (first_segment != AH_TRUE)
tx_desc->tx_control_0 &= ~AR5K_AR5210_DESC_TX_CTL0_FRAME_LEN;
 1090         if (last_segment != AH_TRUE)
tx_desc->tx_control_1 |= AR5K_AR5210_DESC_TX_CTL1_MORE;
 1093         return (AH_TRUE);
 1094 }
HAL_BOOL
 1097 ar5k_ar5210_setup_xtx_desc(struct ath_hal *hal, struct ath_desc *desc,
u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2,
u_int tx_rate3, u_int tx_tries3)
 1100 {
 1101         /*
 1102          * Does this function is for setting up XR? Not sure...
 1103          * Nevertheless, I didn't find any information about XR support
 1104          * by the AR5210. This seems to be a slightly new feature.
 1105          */
 1106         return (AH_FALSE);
 1107 }
HAL_STATUS
 1110 ar5k_ar5210_proc_tx_desc(struct ath_hal *hal, struct ath_desc *desc)
 1111 {
 1112         struct ar5k_ar5210_tx_status *tx_status;
 1113         struct ar5k_ar5210_tx_desc *tx_desc;
tx_desc = (struct ar5k_ar5210_tx_desc*)&desc->ds_ctl0;
tx_status = (struct ar5k_ar5210_tx_status*)&desc->ds_hw[0];
 1118         /* No frame has been send or error */
 1119         if ((tx_status->tx_status_1 & AR5K_AR5210_DESC_TX_STATUS1_DONE) == 0)
 1120                 return (HAL_EINPROGRESS);
 1122         /*
 1123          * Get descriptor status
 1124          */
desc->ds_us.tx.ts_tstamp =
AR5K_REG_MS(tx_status->tx_status_0,
AR5K_AR5210_DESC_TX_STATUS0_SEND_TIMESTAMP);
desc->ds_us.tx.ts_shortretry =
AR5K_REG_MS(tx_status->tx_status_0,
AR5K_AR5210_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
desc->ds_us.tx.ts_longretry =
AR5K_REG_MS(tx_status->tx_status_0,
AR5K_AR5210_DESC_TX_STATUS0_LONG_RETRY_COUNT);
desc->ds_us.tx.ts_seqnum =
AR5K_REG_MS(tx_status->tx_status_1,
AR5K_AR5210_DESC_TX_STATUS1_SEQ_NUM);
desc->ds_us.tx.ts_rssi =
AR5K_REG_MS(tx_status->tx_status_1,
AR5K_AR5210_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
desc->ds_us.tx.ts_antenna = 1;
desc->ds_us.tx.ts_status = 0;
desc->ds_us.tx.ts_rate =
AR5K_REG_MS(tx_desc->tx_control_0,
AR5K_AR5210_DESC_TX_CTL0_XMIT_RATE);
 1146         if ((tx_status->tx_status_0 &
AR5K_AR5210_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0) {
 1148                 if (tx_status->tx_status_0 &
AR5K_AR5210_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
desc->ds_us.tx.ts_status |= HAL_TXERR_XRETRY;
 1152                 if (tx_status->tx_status_0 &
AR5K_AR5210_DESC_TX_STATUS0_FIFO_UNDERRUN)
desc->ds_us.tx.ts_status |= HAL_TXERR_FIFO;
 1156                 if (tx_status->tx_status_0 &
AR5K_AR5210_DESC_TX_STATUS0_FILTERED)
desc->ds_us.tx.ts_status |= HAL_TXERR_FILT;
 1159         }
 1161         return (HAL_OK);
 1162 }
HAL_BOOL
 1165 ar5k_ar5210_has_veol(struct ath_hal *hal)
 1166 {
 1167         return (AH_FALSE);
 1168 }
 1170 /*
 1171  * Receive functions
 1172  */
u_int32_t
 1175 ar5k_ar5210_get_rx_buf(struct ath_hal *hal)
 1176 {
 1177         return (AR5K_REG_READ(AR5K_AR5210_RXDP));
 1178 }
 1180 void
 1181 ar5k_ar5210_put_rx_buf(struct ath_hal *hal, u_int32_t phys_addr)
 1182 {
AR5K_REG_WRITE(AR5K_AR5210_RXDP, phys_addr);
 1184 }
 1186 void
 1187 ar5k_ar5210_start_rx(struct ath_hal *hal)
 1188 {
AR5K_REG_WRITE(AR5K_AR5210_CR, AR5K_AR5210_CR_RXE);
 1190 }
HAL_BOOL
 1193 ar5k_ar5210_stop_rx_dma(struct ath_hal *hal)
 1194 {
 1195         int i;
AR5K_REG_WRITE(AR5K_AR5210_CR, AR5K_AR5210_CR_RXD);
 1199         /*
 1200          * It may take some time to disable the DMA receive unit
 1201          */
 1202         for (i = 2000;
i > 0 && (AR5K_REG_READ(AR5K_AR5210_CR) & AR5K_AR5210_CR_RXE) != 0;
i--)
AR5K_DELAY(10);
 1207         return (i > 0 ? AH_TRUE : AH_FALSE);
 1208 }
 1210 void
 1211 ar5k_ar5210_start_rx_pcu(struct ath_hal *hal)
 1212 {
AR5K_REG_DISABLE_BITS(AR5K_AR5210_DIAG_SW, AR5K_AR5210_DIAG_SW_DIS_RX);
 1214 }
 1216 void
 1217 ar5k_ar5210_stop_pcu_recv(struct ath_hal *hal)
 1218 {
AR5K_REG_ENABLE_BITS(AR5K_AR5210_DIAG_SW, AR5K_AR5210_DIAG_SW_DIS_RX);
 1220 }
 1222 void
 1223 ar5k_ar5210_set_mcast_filter(struct ath_hal *hal, u_int32_t filter0,
u_int32_t filter1)
 1225 {
 1226         /* Set the multicat filter */
AR5K_REG_WRITE(AR5K_AR5210_MCAST_FIL0, filter0);
AR5K_REG_WRITE(AR5K_AR5210_MCAST_FIL1, filter1);
 1229 }
HAL_BOOL
 1232 ar5k_ar5210_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index)
 1233 {
 1234         if (index >= 64) {
 1235                 return (AH_FALSE);
 1236         } else if (index >= 32) {
AR5K_REG_ENABLE_BITS(AR5K_AR5210_MCAST_FIL1,
 1238                     (1 << (index - 32)));
 1239         } else {
AR5K_REG_ENABLE_BITS(AR5K_AR5210_MCAST_FIL0,
 1241                     (1 << index));
 1242         }
 1244         return (AH_TRUE);
 1245 }
HAL_BOOL
 1248 ar5k_ar5210_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index)
 1249 {
 1250         if (index >= 64) {
 1251                 return (AH_FALSE);
 1252         } else if (index >= 32) {
AR5K_REG_DISABLE_BITS(AR5K_AR5210_MCAST_FIL1,
 1254                     (1 << (index - 32)));
 1255         } else {
AR5K_REG_DISABLE_BITS(AR5K_AR5210_MCAST_FIL0,
 1257                     (1 << index));
 1258         }
 1260         return (AH_TRUE);
 1261 }
u_int32_t
 1264 ar5k_ar5210_get_rx_filter(struct ath_hal *hal)
 1265 {
 1266         return (AR5K_REG_READ(AR5K_AR5210_RX_FILTER));
 1267 }
 1269 void
 1270 ar5k_ar5210_set_rx_filter(struct ath_hal *hal, u_int32_t filter)
 1271 {
 1272         /*
 1273          * The AR5210 uses promiscous mode to detect radar activity
 1274          */
 1275         if (filter & HAL_RX_FILTER_PHYRADAR) {
filter &= ~HAL_RX_FILTER_PHYRADAR;
filter |= AR5K_AR5210_RX_FILTER_PROMISC;
 1278         }
AR5K_REG_WRITE(AR5K_AR5210_RX_FILTER, filter);
 1281 }
HAL_BOOL
 1284 ar5k_ar5210_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc,
u_int32_t size, u_int flags)
 1286 {
 1287         struct ar5k_ar5210_rx_desc *rx_desc;
rx_desc = (struct ar5k_ar5210_rx_desc*)&desc->ds_ctl0;
 1291         if ((rx_desc->rx_control_1 = (size &
AR5K_AR5210_DESC_RX_CTL1_BUF_LEN)) != size)
 1293                 return (AH_FALSE);
 1295         if (flags & HAL_RXDESC_INTREQ)
rx_desc->rx_control_1 |= AR5K_AR5210_DESC_RX_CTL1_INTREQ;
 1298         return (AH_TRUE);
 1299 }
HAL_STATUS
 1302 ar5k_ar5210_proc_rx_desc(struct ath_hal *hal, struct ath_desc *desc,
u_int32_t phys_addr, struct ath_desc *next)
 1304 {
 1305         struct ar5k_ar5210_rx_status *rx_status;
rx_status = (struct ar5k_ar5210_rx_status*)&desc->ds_hw[0];
 1309         /* No frame received / not ready */
 1310         if ((rx_status->rx_status_1 & AR5K_AR5210_DESC_RX_STATUS1_DONE) == 0)
 1311                 return (HAL_EINPROGRESS);
 1313         /*
 1314          * Frame receive status
 1315          */
desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 &
AR5K_AR5210_DESC_RX_STATUS0_DATA_LEN;
desc->ds_us.rx.rs_rssi =
AR5K_REG_MS(rx_status->rx_status_0,
AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_SIGNAL);
desc->ds_us.rx.rs_rate =
AR5K_REG_MS(rx_status->rx_status_0,
AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_RATE);
desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 &
AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_ANTENNA;
desc->ds_us.rx.rs_more = rx_status->rx_status_0 &
AR5K_AR5210_DESC_RX_STATUS0_MORE;
desc->ds_us.rx.rs_tstamp =
AR5K_REG_MS(rx_status->rx_status_1,
AR5K_AR5210_DESC_RX_STATUS1_RECEIVE_TIMESTAMP);
desc->ds_us.rx.rs_status = 0;
 1333         /*
 1334          * Key table status
 1335          */
 1336         if (rx_status->rx_status_1 &
AR5K_AR5210_DESC_RX_STATUS1_KEY_INDEX_VALID) {
desc->ds_us.rx.rs_keyix =
AR5K_REG_MS(rx_status->rx_status_1,
AR5K_AR5210_DESC_RX_STATUS1_KEY_INDEX);
 1341         } else {
desc->ds_us.rx.rs_keyix = HAL_RXKEYIX_INVALID;
 1343         }
 1345         /*
 1346          * Receive/descriptor errors
 1347          */
 1348         if ((rx_status->rx_status_1 &
AR5K_AR5210_DESC_RX_STATUS1_FRAME_RECEIVE_OK) == 0) {
 1350                 if (rx_status->rx_status_1 &
AR5K_AR5210_DESC_RX_STATUS1_CRC_ERROR)
desc->ds_us.rx.rs_status |= HAL_RXERR_CRC;
 1354                 if (rx_status->rx_status_1 &
AR5K_AR5210_DESC_RX_STATUS1_FIFO_OVERRUN)
desc->ds_us.rx.rs_status |= HAL_RXERR_FIFO;
 1358                 if (rx_status->rx_status_1 &
AR5K_AR5210_DESC_RX_STATUS1_PHY_ERROR) {
desc->ds_us.rx.rs_status |= HAL_RXERR_PHY;
desc->ds_us.rx.rs_phyerr =
AR5K_REG_MS(rx_status->rx_status_1,
AR5K_AR5210_DESC_RX_STATUS1_PHY_ERROR);
 1364                 }
 1366                 if (rx_status->rx_status_1 &
AR5K_AR5210_DESC_RX_STATUS1_DECRYPT_CRC_ERROR)
desc->ds_us.rx.rs_status |= HAL_RXERR_DECRYPT;
 1369         }
 1371         return (HAL_OK);
 1372 }
 1374 void
 1375 ar5k_ar5210_set_rx_signal(struct ath_hal *hal)
 1376 {
 1377         /* Signal state monitoring is not yet supported */
 1378 }
 1380 /*
 1381  * Misc functions
 1382  */
 1384 void
 1385 ar5k_ar5210_dump_state(struct ath_hal *hal)
 1386 {
 1387 #ifdef AR5K_DEBUG
 1388 #define AR5K_PRINT_REGISTER(_x)                                         \
printf("(%s: %08x) ", #_x, AR5K_REG_READ(AR5K_AR5210_##_x));
printf("DMA registers:\n");
AR5K_PRINT_REGISTER(TXDP0);
AR5K_PRINT_REGISTER(TXDP1);
AR5K_PRINT_REGISTER(CR);
AR5K_PRINT_REGISTER(RXDP);
AR5K_PRINT_REGISTER(CFG);
AR5K_PRINT_REGISTER(ISR);
AR5K_PRINT_REGISTER(IMR);
AR5K_PRINT_REGISTER(IER);
AR5K_PRINT_REGISTER(BCR);
AR5K_PRINT_REGISTER(BSR);
AR5K_PRINT_REGISTER(TXCFG);
AR5K_PRINT_REGISTER(RXCFG);
AR5K_PRINT_REGISTER(MIBC);
AR5K_PRINT_REGISTER(TOPS);
AR5K_PRINT_REGISTER(RXNOFRM);
AR5K_PRINT_REGISTER(TXNOFRM);
AR5K_PRINT_REGISTER(RPGTO);
AR5K_PRINT_REGISTER(RFCNT);
AR5K_PRINT_REGISTER(MISC);
AR5K_PRINT_REGISTER(RC);
AR5K_PRINT_REGISTER(SCR);
AR5K_PRINT_REGISTER(INTPEND);
AR5K_PRINT_REGISTER(SFR);
AR5K_PRINT_REGISTER(PCICFG);
AR5K_PRINT_REGISTER(GPIOCR);
AR5K_PRINT_REGISTER(GPIODO);
AR5K_PRINT_REGISTER(GPIODI);
AR5K_PRINT_REGISTER(SREV);
printf("\n");
printf("PCU registers:\n");
AR5K_PRINT_REGISTER(STA_ID0);
AR5K_PRINT_REGISTER(STA_ID1);
AR5K_PRINT_REGISTER(BSS_ID0);
AR5K_PRINT_REGISTER(BSS_ID1);
AR5K_PRINT_REGISTER(SLOT_TIME);
AR5K_PRINT_REGISTER(TIME_OUT);
AR5K_PRINT_REGISTER(RSSI_THR);
AR5K_PRINT_REGISTER(RETRY_LMT);
AR5K_PRINT_REGISTER(USEC);
AR5K_PRINT_REGISTER(BEACON);
AR5K_PRINT_REGISTER(CFP_PERIOD);
AR5K_PRINT_REGISTER(TIMER0);
AR5K_PRINT_REGISTER(TIMER1);
AR5K_PRINT_REGISTER(TIMER2);
AR5K_PRINT_REGISTER(TIMER3);
AR5K_PRINT_REGISTER(IFS0);
AR5K_PRINT_REGISTER(IFS1);
AR5K_PRINT_REGISTER(CFP_DUR);
AR5K_PRINT_REGISTER(RX_FILTER);
AR5K_PRINT_REGISTER(MCAST_FIL0);
AR5K_PRINT_REGISTER(MCAST_FIL1);
AR5K_PRINT_REGISTER(TX_MASK0);
AR5K_PRINT_REGISTER(TX_MASK1);
AR5K_PRINT_REGISTER(CLR_TMASK);
AR5K_PRINT_REGISTER(TRIG_LVL);
AR5K_PRINT_REGISTER(DIAG_SW);
AR5K_PRINT_REGISTER(TSF_L32);
AR5K_PRINT_REGISTER(TSF_U32);
AR5K_PRINT_REGISTER(LAST_TSTP);
AR5K_PRINT_REGISTER(RETRY_CNT);
AR5K_PRINT_REGISTER(BACKOFF);
AR5K_PRINT_REGISTER(NAV);
AR5K_PRINT_REGISTER(RTS_OK);
AR5K_PRINT_REGISTER(RTS_FAIL);
AR5K_PRINT_REGISTER(ACK_FAIL);
AR5K_PRINT_REGISTER(FCS_FAIL);
AR5K_PRINT_REGISTER(BEACON_CNT);
AR5K_PRINT_REGISTER(KEYTABLE_0);
printf("\n");
printf("PHY registers:\n");
AR5K_PRINT_REGISTER(PHY(0));
AR5K_PRINT_REGISTER(PHY_FC);
AR5K_PRINT_REGISTER(PHY_AGC);
AR5K_PRINT_REGISTER(PHY_CHIP_ID);
AR5K_PRINT_REGISTER(PHY_ACTIVE);
AR5K_PRINT_REGISTER(PHY_AGCCTL);
printf("\n");
 1471 #endif
 1472 }
HAL_BOOL
 1475 ar5k_ar5210_get_diag_state(struct ath_hal *hal, int id, void **device,
u_int *size)
 1477 {
 1478         /*
 1479          * We'll ignore this right now. This seems to be some kind of an obscure
 1480          * debugging interface for the binary-only HAL.
 1481          */
 1482         return (AH_FALSE);
 1483 }
 1485 void
ar5k_ar5210_get_lladdr(struct ath_hal *hal, u_int8_t *mac)
 1487 {
bcopy(hal->ah_sta_id, mac, IEEE80211_ADDR_LEN);
 1489 }
HAL_BOOL
 1492 ar5k_ar5210_set_lladdr(struct ath_hal *hal, const u_int8_t *mac)
 1493 {
u_int32_t low_id, high_id;
 1496         /* Set new station ID */
bcopy(mac, hal->ah_sta_id, IEEE80211_ADDR_LEN);
low_id = AR5K_LOW_ID(mac);
high_id = 0x0000ffff & AR5K_HIGH_ID(mac);
AR5K_REG_WRITE(AR5K_AR5210_STA_ID0, low_id);
AR5K_REG_WRITE(AR5K_AR5210_STA_ID1, high_id);
 1505         return (AH_TRUE);
 1506 }
HAL_BOOL
 1509 ar5k_ar5210_set_regdomain(struct ath_hal *hal, u_int16_t regdomain,
HAL_STATUS *status)
 1511 {
ieee80211_regdomain_t ieee_regdomain;
ieee_regdomain = ar5k_regdomain_to_ieee(regdomain);
 1516         if (ar5k_eeprom_regulation_domain(hal, AH_TRUE,
 1517                 &ieee_regdomain) == AH_TRUE) {
 1518                 *status = HAL_OK;
 1519                 return (AH_TRUE);
 1520         }
 1522         *status = EIO;
 1524         return (AH_FALSE);
 1525 }
 1527 void
 1528 ar5k_ar5210_set_ledstate(struct ath_hal *hal, HAL_LED_STATE state)
 1529 {
u_int32_t led;
led = AR5K_REG_READ(AR5K_AR5210_PCICFG);
 1534         /*
 1535          * Some blinking values, define at your wish
 1536          */
 1537         switch (state) {
 1538         case IEEE80211_S_SCAN:
 1539         case IEEE80211_S_INIT:
led |=
AR5K_AR5210_PCICFG_LED_PEND |
AR5K_AR5210_PCICFG_LED_BCTL;
 1543                 break;
 1544         case IEEE80211_S_RUN:
led |=
AR5K_AR5210_PCICFG_LED_ACT;
 1547                 break;
 1548         default:
led |=
AR5K_AR5210_PCICFG_LED_ACT |
AR5K_AR5210_PCICFG_LED_BCTL;
 1552                 break;
 1553         }
AR5K_REG_WRITE(AR5K_AR5210_PCICFG, led);
 1556 }
 1558 void
ar5k_ar5210_set_associd(struct ath_hal *hal, const u_int8_t *bssid,
u_int16_t assoc_id, u_int16_t tim_offset)
 1561 {
u_int32_t low_id, high_id;
 1564         /*
 1565          * Set BSSID which triggers the "SME Join" operation
 1566          */
low_id = AR5K_LOW_ID(bssid);
high_id = AR5K_HIGH_ID(bssid);
AR5K_REG_WRITE(AR5K_AR5210_BSS_ID0, low_id);
AR5K_REG_WRITE(AR5K_AR5210_BSS_ID1, high_id |
 1571             ((assoc_id & 0x3fff) << AR5K_AR5210_BSS_ID1_AID_S));
bcopy(bssid, &hal->ah_bssid, IEEE80211_ADDR_LEN);
 1574         if (assoc_id == 0) {
ar5k_ar5210_disable_pspoll(hal);
 1576                 return;
 1577         }
AR5K_REG_WRITE_BITS(AR5K_AR5210_BEACON, AR5K_AR5210_BEACON_TIM,
tim_offset ? tim_offset + 4 : 0);
ar5k_ar5210_enable_pspoll(hal, NULL, 0);
 1583 }
HAL_BOOL
 1586 ar5k_ar5210_set_bssid_mask(struct ath_hal *hal, const u_int8_t* mask)
 1587 {
 1588         /* Not supported in 5210 */
 1589         return (AH_FALSE);
 1590 }
HAL_BOOL
 1593 ar5k_ar5210_set_gpio_output(struct ath_hal *hal, u_int32_t gpio)
 1594 {
 1595         if (gpio > AR5K_AR5210_NUM_GPIO)
 1596                 return (AH_FALSE);
AR5K_REG_WRITE(AR5K_AR5210_GPIOCR,
 1599             (AR5K_REG_READ(AR5K_AR5210_GPIOCR) &~ AR5K_AR5210_GPIOCR_ALL(gpio))
 1600             | AR5K_AR5210_GPIOCR_OUT1(gpio));
 1602         return (AH_TRUE);
 1603 }
HAL_BOOL
ar5k_ar5210_set_gpio_input(struct ath_hal *hal, u_int32_t gpio)
 1607 {
 1608         if (gpio > AR5K_AR5210_NUM_GPIO)
 1609                 return (AH_FALSE);
AR5K_REG_WRITE(AR5K_AR5210_GPIOCR,
 1612             (AR5K_REG_READ(AR5K_AR5210_GPIOCR) &~ AR5K_AR5210_GPIOCR_ALL(gpio))
 1613             | AR5K_AR5210_GPIOCR_IN(gpio));
 1615         return (AH_TRUE);
 1616 }
u_int32_t
ar5k_ar5210_get_gpio(struct ath_hal *hal, u_int32_t gpio)
 1620 {
 1621         if (gpio > AR5K_AR5210_NUM_GPIO)
 1622                 return (0xffffffff);
 1624         /* GPIO input magic */
 1625         return (((AR5K_REG_READ(AR5K_AR5210_GPIODI) &
AR5K_AR5210_GPIOD_MASK) >> gpio) & 0x1);
 1627 }
HAL_BOOL
 1630 ar5k_ar5210_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val)
 1631 {
u_int32_t data;
 1634         if (gpio > AR5K_AR5210_NUM_GPIO)
 1635                 return (0xffffffff);
 1637         /* GPIO output magic */
data =  AR5K_REG_READ(AR5K_AR5210_GPIODO);
data &= ~(1 << gpio);
data |= (val&1) << gpio;
AR5K_REG_WRITE(AR5K_AR5210_GPIODO, data);
 1645         return (AH_TRUE);
 1646 }
 1648 void
ar5k_ar5210_set_gpio_intr(struct ath_hal *hal, u_int gpio,
u_int32_t interrupt_level)
 1651 {
u_int32_t data;
 1654         if (gpio > AR5K_AR5210_NUM_GPIO)
 1655                 return;
 1657         /*
 1658          * Set the GPIO interrupt
 1659          */
data = (AR5K_REG_READ(AR5K_AR5210_GPIOCR) &
 1661             ~(AR5K_AR5210_GPIOCR_INT_SEL(gpio) | AR5K_AR5210_GPIOCR_INT_SELH |
AR5K_AR5210_GPIOCR_INT_ENA | AR5K_AR5210_GPIOCR_ALL(gpio))) |
 1663             (AR5K_AR5210_GPIOCR_INT_SEL(gpio) | AR5K_AR5210_GPIOCR_INT_ENA);
AR5K_REG_WRITE(AR5K_AR5210_GPIOCR,
interrupt_level ? data : (data | AR5K_AR5210_GPIOCR_INT_SELH));
hal->ah_imr |= AR5K_AR5210_IMR_GPIO;
 1670         /* Enable GPIO interrupts */
AR5K_REG_ENABLE_BITS(AR5K_AR5210_IMR, AR5K_AR5210_IMR_GPIO);
 1672 }
u_int32_t
 1675 ar5k_ar5210_get_tsf32(struct ath_hal *hal)
 1676 {
 1677         return (AR5K_REG_READ(AR5K_AR5210_TSF_L32));
 1678 }
u_int64_t
 1681 ar5k_ar5210_get_tsf64(struct ath_hal *hal)
 1682 {
u_int64_t tsf = AR5K_REG_READ(AR5K_AR5210_TSF_U32);
 1684         return (AR5K_REG_READ(AR5K_AR5210_TSF_L32) | (tsf << 32));
 1685 }
 1687 void
 1688 ar5k_ar5210_reset_tsf(struct ath_hal *hal)
 1689 {
AR5K_REG_ENABLE_BITS(AR5K_AR5210_BEACON,
AR5K_AR5210_BEACON_RESET_TSF);
 1692 }
u_int16_t
 1695 ar5k_ar5210_get_regdomain(struct ath_hal *hal)
 1696 {
 1697         return (ar5k_get_regdomain(hal));
 1698 }
HAL_BOOL
 1701 ar5k_ar5210_detect_card_present(struct ath_hal *hal)
 1702 {
u_int16_t magic;
 1705         /*
 1706          * Checking the EEPROM's magic value could be an indication
 1707          * if the card is still present. I didn't find another suitable
 1708          * way to do this.
 1709          */
 1710         if (ar5k_ar5210_eeprom_read(hal, AR5K_EEPROM_MAGIC, &magic) != 0)
 1711                 return (AH_FALSE);
 1713         return (magic == AR5K_EEPROM_MAGIC_VALUE ? AH_TRUE : AH_FALSE);
 1714 }
 1716 void
 1717 ar5k_ar5210_update_mib_counters(struct ath_hal *hal, HAL_MIB_STATS *statistics)
 1718 {
statistics->ackrcv_bad += AR5K_REG_READ(AR5K_AR5210_ACK_FAIL);
statistics->rts_bad += AR5K_REG_READ(AR5K_AR5210_RTS_FAIL);
statistics->rts_good += AR5K_REG_READ(AR5K_AR5210_RTS_OK);
statistics->fcs_bad += AR5K_REG_READ(AR5K_AR5210_FCS_FAIL);
statistics->beacons += AR5K_REG_READ(AR5K_AR5210_BEACON_CNT);
 1724 }
HAL_RFGAIN
 1727 ar5k_ar5210_get_rf_gain(struct ath_hal *hal)
 1728 {
 1729         return (HAL_RFGAIN_INACTIVE);
 1730 }
HAL_BOOL
 1733 ar5k_ar5210_set_slot_time(struct ath_hal *hal, u_int slot_time)
 1734 {
 1735         if (slot_time < HAL_SLOT_TIME_9 || slot_time > HAL_SLOT_TIME_MAX)
 1736                 return (AH_FALSE);
AR5K_REG_WRITE(AR5K_AR5210_SLOT_TIME,
ar5k_htoclock(slot_time, hal->ah_turbo));
 1741         return (AH_TRUE);
 1742 }
u_int
 1745 ar5k_ar5210_get_slot_time(struct ath_hal *hal)
 1746 {
 1747         return (ar5k_clocktoh(AR5K_REG_READ(AR5K_AR5210_SLOT_TIME) &
 1748                     0xffff, hal->ah_turbo));
 1749 }
HAL_BOOL
 1752 ar5k_ar5210_set_ack_timeout(struct ath_hal *hal, u_int timeout)
 1753 {
 1754         if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5210_TIME_OUT_ACK),
hal->ah_turbo) <= timeout)
 1756                 return (AH_FALSE);
AR5K_REG_WRITE_BITS(AR5K_AR5210_TIME_OUT, AR5K_AR5210_TIME_OUT_ACK,
ar5k_htoclock(timeout, hal->ah_turbo));
 1761         return (AH_TRUE);
 1762 }
u_int
 1765 ar5k_ar5210_get_ack_timeout(struct ath_hal *hal)
 1766 {
 1767         return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5210_TIME_OUT),
AR5K_AR5210_TIME_OUT_ACK), hal->ah_turbo));
 1769 }
HAL_BOOL
 1772 ar5k_ar5210_set_cts_timeout(struct ath_hal *hal, u_int timeout)
 1773 {
 1774         if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5210_TIME_OUT_CTS),
hal->ah_turbo) <= timeout)
 1776                 return (AH_FALSE);
AR5K_REG_WRITE_BITS(AR5K_AR5210_TIME_OUT, AR5K_AR5210_TIME_OUT_CTS,
ar5k_htoclock(timeout, hal->ah_turbo));
 1781         return (AH_TRUE);
 1782 }
u_int
 1785 ar5k_ar5210_get_cts_timeout(struct ath_hal *hal)
 1786 {
 1787         return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5210_TIME_OUT),
AR5K_AR5210_TIME_OUT_CTS), hal->ah_turbo));
 1789 }
 1791 /*
 1792  * Key table (WEP) functions
 1793  */
HAL_BOOL
 1796 ar5k_ar5210_is_cipher_supported(struct ath_hal *hal, HAL_CIPHER cipher)
 1797 {
 1798         /*
 1799          * The AR5210 only supports WEP
 1800          */
 1801         if (cipher == HAL_CIPHER_WEP)
 1802                 return (AH_TRUE);
 1804         return (AH_FALSE);
 1805 }
u_int32_t
 1808 ar5k_ar5210_get_keycache_size(struct ath_hal *hal)
 1809 {
 1810         return (AR5K_AR5210_KEYCACHE_SIZE);
 1811 }
HAL_BOOL
 1814 ar5k_ar5210_reset_key(struct ath_hal *hal, u_int16_t entry)
 1815 {
 1816         int i;
AR5K_ASSERT_ENTRY(entry, AR5K_AR5210_KEYTABLE_SIZE);
 1820         for (i = 0; i < AR5K_AR5210_KEYCACHE_SIZE; i++)
AR5K_REG_WRITE(AR5K_AR5210_KEYTABLE_OFF(entry, i), 0);
 1823         return (AH_FALSE);
 1824 }
HAL_BOOL
 1827 ar5k_ar5210_is_key_valid(struct ath_hal *hal, u_int16_t entry)
 1828 {
AR5K_ASSERT_ENTRY(entry, AR5K_AR5210_KEYTABLE_SIZE);
 1831         /*
 1832          * Check the validation flag at the end of the entry
 1833          */
 1834         if (AR5K_REG_READ(AR5K_AR5210_KEYTABLE_MAC1(entry)) &
AR5K_AR5210_KEYTABLE_VALID)
 1836                 return (AH_TRUE);
 1838         return (AH_FALSE);
 1839 }
HAL_BOOL
 1842 ar5k_ar5210_set_key(struct ath_hal *hal, u_int16_t entry,
 1843     const HAL_KEYVAL *keyval, const u_int8_t *mac, int xor_notused)
 1844 {
 1845         int i;
u_int32_t key_v[AR5K_AR5210_KEYCACHE_SIZE - 2];
AR5K_ASSERT_ENTRY(entry, AR5K_AR5210_KEYTABLE_SIZE);
bzero(&key_v, sizeof(key_v));
 1852         switch (keyval->wk_len) {
 1853         case AR5K_KEYVAL_LENGTH_40:
bcopy(keyval->wk_key, &key_v[0], 4);
bcopy(keyval->wk_key + 4, &key_v[1], 1);
key_v[5] = AR5K_AR5210_KEYTABLE_TYPE_40;
 1857                 break;
 1859         case AR5K_KEYVAL_LENGTH_104:
bcopy(keyval->wk_key, &key_v[0], 4);
bcopy(keyval->wk_key + 4, &key_v[1], 2);
bcopy(keyval->wk_key + 6, &key_v[2], 4);
bcopy(keyval->wk_key + 10, &key_v[3], 2);
bcopy(keyval->wk_key + 12, &key_v[4], 1);
key_v[5] = AR5K_AR5210_KEYTABLE_TYPE_104;
 1866                 break;
 1868         case AR5K_KEYVAL_LENGTH_128:
bcopy(keyval->wk_key, &key_v[0], 4);
bcopy(keyval->wk_key + 4, &key_v[1], 2);
bcopy(keyval->wk_key + 6, &key_v[2], 4);
bcopy(keyval->wk_key + 10, &key_v[3], 2);
bcopy(keyval->wk_key + 12, &key_v[4], 4);
key_v[5] = AR5K_AR5210_KEYTABLE_TYPE_128;
 1875                 break;
 1877         default:
 1878                 /* Unsupported key length (not WEP40/104/128) */
 1879                 return (AH_FALSE);
 1880         }
 1882         for (i = 0; i < AR5K_ELEMENTS(key_v); i++)
AR5K_REG_WRITE(AR5K_AR5210_KEYTABLE_OFF(entry, i), key_v[i]);
 1885         return (ar5k_ar5210_set_key_lladdr(hal, entry, mac));
 1886 }
HAL_BOOL
ar5k_ar5210_set_key_lladdr(struct ath_hal *hal, u_int16_t entry,
 1890     const u_int8_t *mac)
 1891 {
u_int32_t low_id, high_id;
 1893         const u_int8_t *mac_v;
 1895         /*
 1896          * Invalid entry (key table overflow)
 1897          */
AR5K_ASSERT_ENTRY(entry, AR5K_AR5210_KEYTABLE_SIZE);
 1900         /* MAC may be NULL if it's a broadcast key */
mac_v = mac == NULL ? etherbroadcastaddr : mac;
low_id = AR5K_LOW_ID(mac_v);
high_id = AR5K_HIGH_ID(mac_v) | AR5K_AR5210_KEYTABLE_VALID;
AR5K_REG_WRITE(AR5K_AR5210_KEYTABLE_MAC0(entry), low_id);
AR5K_REG_WRITE(AR5K_AR5210_KEYTABLE_MAC1(entry), high_id);
 1909         return (AH_TRUE);
 1910 }
 1912 /*
 1913  * Power management functions
 1914  */
HAL_BOOL
ar5k_ar5210_set_power(struct ath_hal *hal, HAL_POWER_MODE mode,
HAL_BOOL set_chip, u_int16_t sleep_duration)
 1919 {
u_int32_t staid;
 1921         int i;
staid = AR5K_REG_READ(AR5K_AR5210_STA_ID1);
 1925         switch (mode) {
 1926         case HAL_PM_AUTO:
staid &= ~AR5K_AR5210_STA_ID1_DEFAULT_ANTENNA;
 1928                 /* FALLTHROUGH */
 1929         case HAL_PM_NETWORK_SLEEP:
 1930                 if (set_chip == AH_TRUE) {
AR5K_REG_WRITE(AR5K_AR5210_SCR,
AR5K_AR5210_SCR_SLE | sleep_duration);
 1933                 }
staid |= AR5K_AR5210_STA_ID1_PWR_SV;
 1935                 break;
 1937         case HAL_PM_FULL_SLEEP:
 1938                 if (set_chip == AH_TRUE) {
AR5K_REG_WRITE(AR5K_AR5210_SCR,
AR5K_AR5210_SCR_SLE_SLP);
 1941                 }
staid |= AR5K_AR5210_STA_ID1_PWR_SV;
 1943                 break;
 1945         case HAL_PM_AWAKE:
 1946                 if (set_chip == AH_FALSE)
 1947                         goto commit;
AR5K_REG_WRITE(AR5K_AR5210_SCR, AR5K_AR5210_SCR_SLE_WAKE);
 1951                 for (i = 5000; i > 0; i--) {
 1952                         /* Check if the AR5210 did wake up */
 1953                         if ((AR5K_REG_READ(AR5K_AR5210_PCICFG) &
AR5K_AR5210_PCICFG_SPWR_DN) == 0)
 1955                                 break;
 1957                         /* Wait a bit and retry */
AR5K_DELAY(200);
AR5K_REG_WRITE(AR5K_AR5210_SCR,
AR5K_AR5210_SCR_SLE_WAKE);
 1961                 }
 1963                 /* Fail if the AR5210 didn't wake up */
 1964                 if (i <= 0)
 1965                         return (AH_FALSE);
staid &= ~AR5K_AR5210_STA_ID1_PWR_SV;
 1968                 break;
 1970         default:
 1971                 return (AH_FALSE);
 1972         }
commit:
hal->ah_power_mode = mode;
AR5K_REG_WRITE(AR5K_AR5210_STA_ID1, staid);
 1979         return (AH_TRUE);
 1980 }
HAL_POWER_MODE
 1983 ar5k_ar5210_get_power_mode(struct ath_hal *hal)
 1984 {
 1985         return (hal->ah_power_mode);
 1986 }
HAL_BOOL
 1989 ar5k_ar5210_query_pspoll_support(struct ath_hal *hal)
 1990 {
 1991         /* I think so, why not? */
 1992         return (AH_TRUE);
 1993 }
HAL_BOOL
 1996 ar5k_ar5210_init_pspoll(struct ath_hal *hal)
 1997 {
 1998         /*
 1999          * Not used on the AR5210
 2000          */
 2001         return (AH_FALSE);
 2002 }
HAL_BOOL
ar5k_ar5210_enable_pspoll(struct ath_hal *hal, u_int8_t *bssid,
u_int16_t assoc_id)
 2007 {
AR5K_REG_DISABLE_BITS(AR5K_AR5210_STA_ID1,
AR5K_AR5210_STA_ID1_NO_PSPOLL |
AR5K_AR5210_STA_ID1_DEFAULT_ANTENNA);
 2012         return (AH_TRUE);
 2013 }
HAL_BOOL
ar5k_ar5210_disable_pspoll(struct ath_hal *hal)
 2017 {
AR5K_REG_ENABLE_BITS(AR5K_AR5210_STA_ID1,
AR5K_AR5210_STA_ID1_NO_PSPOLL |
AR5K_AR5210_STA_ID1_DEFAULT_ANTENNA);
 2022         return (AH_TRUE);
 2023 }
 2025 /*
 2026  * Beacon functions
 2027  */
 2029 void
 2030 ar5k_ar5210_init_beacon(struct ath_hal *hal, u_int32_t next_beacon,
u_int32_t interval)
 2032 {
u_int32_t timer1, timer2, timer3;
 2035         /*
 2036          * Set the additional timers by mode
 2037          */
 2038         switch (hal->ah_op_mode) {
 2039         case HAL_M_STA:
timer1 = 0xffffffff;
timer2 = 0xffffffff;
timer3 = 1;
 2043                 break;
 2045         default:
timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3;
timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3;
timer3 = next_beacon + hal->ah_atim_window;
 2049                 break;
 2050         }
 2052         /*
 2053          * Enable all timers and set the beacon register
 2054          * (next beacon, DMA beacon, software beacon, ATIM window time)
 2055          */
AR5K_REG_WRITE(AR5K_AR5210_TIMER0, next_beacon);
AR5K_REG_WRITE(AR5K_AR5210_TIMER1, timer1);
AR5K_REG_WRITE(AR5K_AR5210_TIMER2, timer2);
AR5K_REG_WRITE(AR5K_AR5210_TIMER3, timer3);
AR5K_REG_WRITE(AR5K_AR5210_BEACON, interval &
 2062             (AR5K_AR5210_BEACON_PERIOD | AR5K_AR5210_BEACON_RESET_TSF |
AR5K_AR5210_BEACON_EN));
 2064 }
 2066 void
 2067 ar5k_ar5210_set_beacon_timers(struct ath_hal *hal,
 2068     const HAL_BEACON_STATE *state, u_int32_t tsf, u_int32_t dtim_count,
u_int32_t cfp_count)
 2070 {
u_int32_t cfp_period, next_cfp;
 2073         /* Return on an invalid beacon state */
 2074         if (state->bs_interval < 1)
 2075                 return;
 2077         /*
 2078          * PCF support?
 2079          */
 2080         if (state->bs_cfp_period > 0) {
 2081                 /* Enable CFP mode and set the CFP and timer registers */
cfp_period = state->bs_cfp_period * state->bs_dtim_period *
state->bs_interval;
next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) *
state->bs_interval;
AR5K_REG_DISABLE_BITS(AR5K_AR5210_STA_ID1,
AR5K_AR5210_STA_ID1_DEFAULT_ANTENNA |
AR5K_AR5210_STA_ID1_PCF);
AR5K_REG_WRITE(AR5K_AR5210_CFP_PERIOD, cfp_period);
AR5K_REG_WRITE(AR5K_AR5210_CFP_DUR, state->bs_cfp_max_duration);
AR5K_REG_WRITE(AR5K_AR5210_TIMER2,
 2093                     (tsf + (next_cfp == 0 ? cfp_period : next_cfp)) << 3);
 2094         } else {
 2095                 /* Disable PCF mode */
AR5K_REG_DISABLE_BITS(AR5K_AR5210_STA_ID1,
AR5K_AR5210_STA_ID1_DEFAULT_ANTENNA |
AR5K_AR5210_STA_ID1_PCF);
 2099         }
 2101         /*
 2102          * Enable the beacon timer register
 2103          */
AR5K_REG_WRITE(AR5K_AR5210_TIMER0, state->bs_next_beacon);
 2106         /*
 2107          * Start the beacon timers
 2108          */
AR5K_REG_WRITE(AR5K_AR5210_BEACON,
 2110             (AR5K_REG_READ(AR5K_AR5210_BEACON) &~
 2111                 (AR5K_AR5210_BEACON_PERIOD | AR5K_AR5210_BEACON_TIM)) |
AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0,
AR5K_AR5210_BEACON_TIM) |
AR5K_REG_SM(state->bs_interval, AR5K_AR5210_BEACON_PERIOD));
 2116         /*
 2117          * Write new beacon miss threshold, if it appears to be valid
 2118          */
 2119         if (state->bs_bmiss_threshold <=
 2120             (AR5K_AR5210_RSSI_THR_BM_THR >> AR5K_AR5210_RSSI_THR_BM_THR_S)) {
AR5K_REG_WRITE_BITS(AR5K_AR5210_RSSI_THR,
AR5K_AR5210_RSSI_THR_BM_THR, state->bs_bmiss_threshold);
 2123         }
 2124 }
 2126 void
 2127 ar5k_ar5210_reset_beacon(struct ath_hal *hal)
 2128 {
 2129         /*
 2130          * Disable beacon timer
 2131          */
AR5K_REG_WRITE(AR5K_AR5210_TIMER0, 0);
 2134         /*
 2135          * Disable some beacon register values
 2136          */
AR5K_REG_DISABLE_BITS(AR5K_AR5210_STA_ID1,
AR5K_AR5210_STA_ID1_DEFAULT_ANTENNA | AR5K_AR5210_STA_ID1_PCF);
AR5K_REG_WRITE(AR5K_AR5210_BEACON, AR5K_AR5210_BEACON_PERIOD);
 2140 }
HAL_BOOL
 2143 ar5k_ar5210_wait_for_beacon(struct ath_hal *hal, bus_addr_t phys_addr)
 2144 {
 2145         int i;
 2147         /*
 2148          * Wait for beaconn queue to be done
 2149          */
 2150         for (i = (AR5K_TUNE_BEACON_INTERVAL / 2); i > 0 &&
 2151                  (AR5K_REG_READ(AR5K_AR5210_BSR) &
AR5K_AR5210_BSR_TXQ1F) != 0 &&
 2153                  (AR5K_REG_READ(AR5K_AR5210_CR) &
AR5K_AR5210_CR_TXE1) != 0; i--);
 2156         /* Timeout... */
 2157         if (i <= 0) {
 2158                 /*
 2159                  * Re-schedule the beacon queue
 2160                  */
AR5K_REG_WRITE(AR5K_AR5210_TXDP1, (u_int32_t)phys_addr);
AR5K_REG_WRITE(AR5K_AR5210_BCR,
AR5K_AR5210_BCR_TQ1V | AR5K_AR5210_BCR_BDMAE);
 2165                 return (AH_FALSE);
 2166         }
 2168         return (AH_TRUE);
 2169 }
 2171 /*
 2172  * Interrupt handling
 2173  */
HAL_BOOL
 2176 ar5k_ar5210_is_intr_pending(struct ath_hal *hal)
 2177 {
 2178         return (AR5K_REG_READ(AR5K_AR5210_INTPEND) == 0 ? AH_FALSE : AH_TRUE);
 2179 }
HAL_BOOL
 2182 ar5k_ar5210_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask)
 2183 {
u_int32_t data;
 2186         if ((data = AR5K_REG_READ(AR5K_AR5210_ISR)) == HAL_INT_NOCARD) {
 2187                 *interrupt_mask = data;
 2188                 return (AH_FALSE);
 2189         }
 2191         /*
 2192          * Get abstract interrupt mask (HAL-compatible)
 2193          */
 2194         *interrupt_mask = (data & HAL_INT_COMMON) & hal->ah_imr;
 2196         if (data & (AR5K_AR5210_ISR_RXOK | AR5K_AR5210_ISR_RXERR))
 2197                 *interrupt_mask |= HAL_INT_RX;
 2198         if (data & (AR5K_AR5210_ISR_TXOK | AR5K_AR5210_ISR_TXERR))
 2199                 *interrupt_mask |= HAL_INT_TX;
 2200         if (data & AR5K_AR5210_ISR_FATAL)
 2201                 *interrupt_mask |= HAL_INT_FATAL;
 2203         /*
 2204          * Special interrupt handling (not caught by the driver)
 2205          */
 2206         if (((*interrupt_mask) & AR5K_AR5210_ISR_RXPHY) &&
hal->ah_radar.r_enabled == AH_TRUE)
ar5k_radar_alert(hal);
 2210         /* XXX BMISS interrupts may occur after association */
 2211         *interrupt_mask &= ~HAL_INT_BMISS;
 2213         return (AH_TRUE);
 2214 }
u_int32_t
 2217 ar5k_ar5210_get_intr(struct ath_hal *hal)
 2218 {
 2219         /* Return the interrupt mask stored previously */
 2220         return (hal->ah_imr);
 2221 }
HAL_INT
 2224 ar5k_ar5210_set_intr(struct ath_hal *hal, HAL_INT new_mask)
 2225 {
HAL_INT old_mask, int_mask;
 2228         /*
 2229          * Disable card interrupts to prevent any race conditions
 2230          * (they will be re-enabled afterwards).
 2231          */
AR5K_REG_WRITE(AR5K_AR5210_IER, AR5K_AR5210_IER_DISABLE);
old_mask = hal->ah_imr;
 2236         /*
 2237          * Add additional, chipset-dependent interrupt mask flags
 2238          * and write them to the IMR (interrupt mask register).
 2239          */
int_mask = new_mask & HAL_INT_COMMON;
 2242         if (new_mask & HAL_INT_RX)
int_mask |=
AR5K_AR5210_IMR_RXOK |
AR5K_AR5210_IMR_RXERR |
AR5K_AR5210_IMR_RXORN;
 2248         if (new_mask & HAL_INT_TX)
int_mask |=
AR5K_AR5210_IMR_TXOK |
AR5K_AR5210_IMR_TXERR |
AR5K_AR5210_IMR_TXURN;
AR5K_REG_WRITE(AR5K_AR5210_IMR, int_mask);
 2256         /* Store new interrupt mask */
hal->ah_imr = new_mask;
 2259         /* ..re-enable interrupts */
 2260         if (int_mask) {
AR5K_REG_WRITE(AR5K_AR5210_IER, AR5K_AR5210_IER_ENABLE);
 2262         }
 2264         return (old_mask);
 2265 }
 2267 /*
 2268  * Misc internal functions
 2269  */
HAL_BOOL
 2272 ar5k_ar5210_get_capabilities(struct ath_hal *hal)
 2273 {
 2274         /* Set number of supported TX queues */
hal->ah_capabilities.cap_queues.q_tx_num = AR5K_AR5210_TX_NUM_QUEUES;
 2277         /*
 2278          * Set radio capabilities
 2279          * (The AR5210 only supports the middle 5GHz band)
 2280          */
hal->ah_capabilities.cap_range.range_5ghz_min = 5120;
hal->ah_capabilities.cap_range.range_5ghz_max = 5430;
hal->ah_capabilities.cap_range.range_2ghz_min = 0;
hal->ah_capabilities.cap_range.range_2ghz_max = 0;
 2286         /* Set supported modes */
hal->ah_capabilities.cap_mode = HAL_MODE_11A | HAL_MODE_TURBO;
 2289         /* Set number of GPIO pins */
hal->ah_gpio_npins = AR5K_AR5210_NUM_GPIO;
 2292         return (AH_TRUE);
 2293 }
 2295 void
 2296 ar5k_ar5210_radar_alert(struct ath_hal *hal, HAL_BOOL enable)
 2297 {
 2298         /*
 2299          * Set the RXPHY interrupt to be able to detect
 2300          * possible radar activity.
 2301          */
AR5K_REG_WRITE(AR5K_AR5210_IER, AR5K_AR5210_IER_DISABLE);
 2304         if (enable == AH_TRUE) {
AR5K_REG_ENABLE_BITS(AR5K_AR5210_IMR,
AR5K_AR5210_IMR_RXPHY);
 2307         } else {
AR5K_REG_DISABLE_BITS(AR5K_AR5210_IMR,
AR5K_AR5210_IMR_RXPHY);
 2310         }
AR5K_REG_WRITE(AR5K_AR5210_IER, AR5K_AR5210_IER_ENABLE);
 2313 }
 2315 /*
 2316  * EEPROM access functions
 2317  */
HAL_BOOL
 2320 ar5k_ar5210_eeprom_is_busy(struct ath_hal *hal)
 2321 {
 2322         return (AR5K_REG_READ(AR5K_AR5210_CFG) & AR5K_AR5210_CFG_EEBS ?
AH_TRUE : AH_FALSE);
 2324 }
 2326 int
ar5k_ar5210_eeprom_read(struct ath_hal *hal, u_int32_t offset, u_int16_t *data)
 2328 {
u_int32_t status, timeout;
 2331         /* Enable eeprom access */
AR5K_REG_ENABLE_BITS(AR5K_AR5210_PCICFG, AR5K_AR5210_PCICFG_EEAE);
 2334         /*
 2335          * Prime read pump
 2336          */
 2337         (void)AR5K_REG_READ(AR5K_AR5210_EEPROM_BASE + (4 * offset));
 2339         for (timeout = 10000; timeout > 0; timeout--) {
AR5K_DELAY(1);
status = AR5K_REG_READ(AR5K_AR5210_EEPROM_STATUS);
 2342                 if (status & AR5K_AR5210_EEPROM_STAT_RDDONE) {
 2343                         if (status & AR5K_AR5210_EEPROM_STAT_RDERR)
 2344                                 return (EIO);
 2345                         *data = (u_int16_t)
 2346                             (AR5K_REG_READ(AR5K_AR5210_EEPROM_RDATA) & 0xffff);
 2347                         return (0);
 2348                 }
 2349         }
 2351         return (ETIMEDOUT);
 2352 }
 2354 int
 2355 ar5k_ar5210_eeprom_write(struct ath_hal *hal, u_int32_t offset, u_int16_t data)
 2356 {
u_int32_t status, timeout;
 2359         /* Enable eeprom access */
AR5K_REG_ENABLE_BITS(AR5K_AR5210_PCICFG, AR5K_AR5210_PCICFG_EEAE);
 2362         /*
 2363          * Prime write pump
 2364          */
AR5K_REG_WRITE(AR5K_AR5210_EEPROM_BASE + (4 * offset), data);
 2367         for (timeout = 10000; timeout > 0; timeout--) {
AR5K_DELAY(1);
status = AR5K_REG_READ(AR5K_AR5210_EEPROM_STATUS);
 2370                 if (status & AR5K_AR5210_EEPROM_STAT_WRDONE) {
 2371                         if (status & AR5K_AR5210_EEPROM_STAT_WRERR)
 2372                                 return (EIO);
 2373                         return (0);
 2374                 }
 2375         }
 2377         return (ETIMEDOUT);
 2378 }
HAL_BOOL
 2381 ar5k_ar5210_set_txpower_limit(struct ath_hal *hal, u_int power)
 2382 {
 2383         /* Not implemented */
 2384         return (AH_FALSE);
 2385 }