_x 1388 dev/ic/ar5210.c #define AR5K_PRINT_REGISTER(_x) \ _x 1389 dev/ic/ar5210.c printf("(%s: %08x) ", #_x, AR5K_REG_READ(AR5K_AR5210_##_x)); _x 1484 dev/ic/ar5211.c #define AR5K_PRINT_REGISTER(_x) \ _x 1485 dev/ic/ar5211.c printf("(%s: %08x) ", #_x, AR5K_REG_READ(AR5K_AR5211_##_x)); _x 1751 dev/ic/ar5212.c #define AR5K_PRINT_REGISTER(_x) \ _x 1752 dev/ic/ar5212.c printf("(%s: %08x) ", #_x, AR5K_REG_READ(AR5K_AR5212_##_x)); _x 724 dev/ic/ar5xxx.h #define AR5K_EEPROM_SCALE_OC_DELTA(_x) (((_x) * 2) / 10) _x 5863 dev/ic/isp.c u_int8_t _x[ISP2100_NVRAM_SIZE]; _x 5866 dev/ic/isp.c #define nvram_data _n._x _x 73 dev/ic/silireg.h #define SILI_PREG_PCS_ACTIVE(_x) (((_x)>>16) & 0x1f) /* Active Slot */ _x 85 dev/pci/if_che.c #define CHE_I2C_CLKDIV(_x) ((_x) && 0xfff) _x 95 dev/pci/if_che.c #define CHE_MI1_CLKDIV(_x) ((_x) << 5) _x 96 dev/pci/if_che.c #define CHE_MI1_PHYADDR(_x) ((_x) << 5) _x 97 dev/pci/if_che.c #define CHE_MI1_OP(_x) ((_x) & 0x3) _x 107 dev/pci/if_che.c #define CHE_XGM_PORTSPEED(_x) ((_x) << 1) _x 124 dev/pci/if_che.c #define CHE_SF_CONT(_x) ((_x) << 3) _x 126 dev/pci/if_che.c #define CHE_SF_BYTECNT(_x) (((_x) & CHE_SF_BYTECNT_MASK) << 1) _x 132 dev/pci/if_che.c #define FW_VERS_TYPE(_x) (((_x) >> 28) & 0xf) _x 133 dev/pci/if_che.c #define FW_VERS_MAJOR(_x) (((_x) >> 16) & 0xfff) _x 134 dev/pci/if_che.c #define FW_VERS_MINOR(_x) (((_x) >> 8) & 0xff) _x 135 dev/pci/if_che.c #define FW_VERS_MICRO(_x) ((_x) & 0xff) _x 342 dev/pci/if_nxe.c #define NXE_1_SW_TEMP_STATE(_x) ((_x)&0xffff) /* Temp state */ _x 347 dev/pci/if_nxe.c #define NXE_1_SW_TEMP_VAL(_x) (((_x)>>16)&0xffff) /* Temp value */ _x 233 dev/pci/if_vic.c #define VIC_INC(_x, _y) (_x) = ((_x) + 1) % (_y) _x 118 dev/pci/safe.c #define DPRINTF(_x) if (safe_debug) printf _x _x 127 dev/pci/safe.c #define DPRINTF(_x) _x 88 kern/kern_sysctl.c #define PTRTOINT64(_x) ((u_int64_t)(u_long)(_x)) _x 1261 net80211/ieee80211_output.c #define senderr(_x, _v) do { ic->ic_stats._v++; ret = _x; goto bad; } while (0)