hal 44 dev/ic/ar5210.c ar5k_ar5210_fill(struct ath_hal *hal)
hal 46 dev/ic/ar5210.c hal->ah_magic = AR5K_AR5210_MAGIC;
hal 51 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, get_rate_table);
hal 52 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, detach);
hal 57 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, reset);
hal 58 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, set_opmode);
hal 59 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, calibrate);
hal 64 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, update_tx_triglevel);
hal 65 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, setup_tx_queue);
hal 66 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, setup_tx_queueprops);
hal 67 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, release_tx_queue);
hal 68 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, reset_tx_queue);
hal 69 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, get_tx_buf);
hal 70 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, put_tx_buf);
hal 71 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, tx_start);
hal 72 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, stop_tx_dma);
hal 73 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, setup_tx_desc);
hal 74 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, setup_xtx_desc);
hal 75 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, fill_tx_desc);
hal 76 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, proc_tx_desc);
hal 77 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, has_veol);
hal 82 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, get_rx_buf);
hal 83 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, put_rx_buf);
hal 84 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, start_rx);
hal 85 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, stop_rx_dma);
hal 86 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, start_rx_pcu);
hal 87 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, stop_pcu_recv);
hal 88 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, set_mcast_filter);
hal 89 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, set_mcast_filterindex);
hal 90 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, clear_mcast_filter_idx);
hal 91 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, get_rx_filter);
hal 92 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, set_rx_filter);
hal 93 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, setup_rx_desc);
hal 94 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, proc_rx_desc);
hal 95 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, set_rx_signal);
hal 100 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, dump_state);
hal 101 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, get_diag_state);
hal 102 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, get_lladdr);
hal 103 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, set_lladdr);
hal 104 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, set_regdomain);
hal 105 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, set_ledstate);
hal 106 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, set_associd);
hal 107 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, set_gpio_input);
hal 108 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, set_gpio_output);
hal 109 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, get_gpio);
hal 110 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, set_gpio);
hal 111 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, set_gpio_intr);
hal 112 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, get_tsf32);
hal 113 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, get_tsf64);
hal 114 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, reset_tsf);
hal 115 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, get_regdomain);
hal 116 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, detect_card_present);
hal 117 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, update_mib_counters);
hal 118 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, get_rf_gain);
hal 119 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, set_slot_time);
hal 120 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, get_slot_time);
hal 121 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, set_ack_timeout);
hal 122 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, get_ack_timeout);
hal 123 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, set_cts_timeout);
hal 124 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, get_cts_timeout);
hal 129 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, is_cipher_supported);
hal 130 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, get_keycache_size);
hal 131 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, reset_key);
hal 132 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, is_key_valid);
hal 133 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, set_key);
hal 134 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, set_key_lladdr);
hal 139 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, set_power);
hal 140 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, get_power_mode);
hal 141 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, query_pspoll_support);
hal 142 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, init_pspoll);
hal 143 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, enable_pspoll);
hal 144 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, disable_pspoll);
hal 149 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, init_beacon);
hal 150 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, set_beacon_timers);
hal 151 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, reset_beacon);
hal 152 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, wait_for_beacon);
hal 157 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, is_intr_pending);
hal 158 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, get_isr);
hal 159 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, get_intr);
hal 160 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, set_intr);
hal 165 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, get_capabilities);
hal 166 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, radar_alert);
hal 171 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, eeprom_is_busy);
hal 172 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, eeprom_read);
hal 173 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, eeprom_write);
hal 178 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, set_bssid_mask);
hal 179 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, get_tx_queueprops);
hal 180 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, num_tx_pending);
hal 181 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, phy_disable);
hal 182 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, set_txpower_limit);
hal 183 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, set_def_antenna);
hal 184 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, get_def_antenna);
hal 186 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, set_capability);
hal 187 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, proc_mib_event);
hal 188 dev/ic/ar5210.c AR5K_HAL_FUNCTION(hal, ar5210, get_tx_inter_queue);
hal 197 dev/ic/ar5210.c struct ath_hal *hal = (struct ath_hal*) sc;
hal 201 dev/ic/ar5210.c ar5k_ar5210_fill(hal);
hal 204 dev/ic/ar5210.c if (ar5k_ar5210_nic_wakeup(hal, AH_FALSE, AH_TRUE) != AH_TRUE)
hal 209 dev/ic/ar5210.c hal->ah_mac_srev = srev;
hal 210 dev/ic/ar5210.c hal->ah_mac_version = AR5K_REG_MS(srev, AR5K_AR5210_SREV_VER);
hal 211 dev/ic/ar5210.c hal->ah_mac_revision = AR5K_REG_MS(srev, AR5K_AR5210_SREV_REV);
hal 212 dev/ic/ar5210.c hal->ah_phy_revision = AR5K_REG_READ(AR5K_AR5210_PHY_CHIP_ID) &
hal 219 dev/ic/ar5210.c hal->ah_radio_5ghz_revision = (u_int16_t)
hal 222 dev/ic/ar5210.c hal->ah_radio_2ghz_revision = 0;
hal 225 dev/ic/ar5210.c hal->ah_version = AR5K_AR5210;
hal 226 dev/ic/ar5210.c hal->ah_radio = AR5K_AR5110;
hal 227 dev/ic/ar5210.c hal->ah_phy = AR5K_AR5210_PHY(0);
hal 230 dev/ic/ar5210.c ar5k_ar5210_set_associd(hal, mac, 0, 0);
hal 231 dev/ic/ar5210.c ar5k_ar5210_get_lladdr(hal, mac);
hal 232 dev/ic/ar5210.c ar5k_ar5210_set_opmode(hal);
hal 234 dev/ic/ar5210.c return (hal);
hal 238 dev/ic/ar5210.c ar5k_ar5210_nic_reset(struct ath_hal *hal, u_int32_t val)
hal 259 dev/ic/ar5210.c ret = ar5k_register_timeout(hal, AR5K_AR5210_RC, mask, val, AH_FALSE);
hal 272 dev/ic/ar5210.c ar5k_ar5210_nic_wakeup(struct ath_hal *hal, HAL_BOOL turbo, HAL_BOOL initial)
hal 280 dev/ic/ar5210.c if (ar5k_ar5210_nic_reset(hal,
hal 290 dev/ic/ar5210.c if (ar5k_ar5210_set_power(hal,
hal 301 dev/ic/ar5210.c if (ar5k_ar5210_nic_reset(hal, AR5K_AR5210_RC_CHIP) == AH_FALSE) {
hal 309 dev/ic/ar5210.c if (ar5k_ar5210_nic_reset(hal,
hal 318 dev/ic/ar5210.c if (ar5k_ar5210_set_power(hal,
hal 325 dev/ic/ar5210.c if (ar5k_ar5210_nic_reset(hal, 0) == AH_FALSE) {
hal 334 dev/ic/ar5210.c ar5k_ar5210_get_rate_table(struct ath_hal *hal, u_int mode)
hal 338 dev/ic/ar5210.c return (&hal->ah_rt_11a);
hal 340 dev/ic/ar5210.c return (&hal->ah_rt_turbo);
hal 351 dev/ic/ar5210.c ar5k_ar5210_detach(struct ath_hal *hal)
hal 356 dev/ic/ar5210.c free(hal, M_DEVBUF);
hal 360 dev/ic/ar5210.c ar5k_ar5210_phy_disable(struct ath_hal *hal)
hal 367 dev/ic/ar5210.c ar5k_ar5210_reset(struct ath_hal *hal, HAL_OPMODE op_mode, HAL_CHANNEL *channel,
hal 375 dev/ic/ar5210.c if (ar5k_ar5210_nic_wakeup(hal,
hal 383 dev/ic/ar5210.c hal->ah_op_mode = op_mode;
hal 384 dev/ic/ar5210.c ar5k_ar5210_set_opmode(hal);
hal 418 dev/ic/ar5210.c if (ar5k_channel(hal, channel) == AH_FALSE)
hal 427 dev/ic/ar5210.c ar5k_ar5210_do_calibrate(hal, channel);
hal 428 dev/ic/ar5210.c if (ar5k_ar5210_noise_floor(hal, channel) == AH_FALSE)
hal 434 dev/ic/ar5210.c if (AR5K_EEPROM_HDR_RFKILL(hal->ah_capabilities.cap_eeprom.ee_header)) {
hal 435 dev/ic/ar5210.c ar5k_ar5210_set_gpio_input(hal, 0);
hal 436 dev/ic/ar5210.c if ((hal->ah_gpio[0] = ar5k_ar5210_get_gpio(hal, 0)) == 0) {
hal 437 dev/ic/ar5210.c ar5k_ar5210_set_gpio_intr(hal, 0, 1);
hal 439 dev/ic/ar5210.c ar5k_ar5210_set_gpio_intr(hal, 0, 0);
hal 446 dev/ic/ar5210.c for (i = 0; i < hal->ah_capabilities.cap_queues.q_tx_num; i++) {
hal 447 dev/ic/ar5210.c if (ar5k_ar5210_reset_tx_queue(hal, i) == AH_FALSE) {
hal 460 dev/ic/ar5210.c ar5k_ar5210_set_def_antenna(struct ath_hal *hal, u_int ant)
hal 467 dev/ic/ar5210.c ar5k_ar5210_get_def_antenna(struct ath_hal *hal)
hal 473 dev/ic/ar5210.c ar5k_ar5210_set_opmode(struct ath_hal *hal)
hal 480 dev/ic/ar5210.c switch (hal->ah_op_mode) {
hal 512 dev/ic/ar5210.c low_id = AR5K_LOW_ID(hal->ah_sta_id);
hal 513 dev/ic/ar5210.c high_id = AR5K_HIGH_ID(hal->ah_sta_id);
hal 522 dev/ic/ar5210.c ar5k_ar5210_calibrate(struct ath_hal *hal, HAL_CHANNEL *channel)
hal 552 dev/ic/ar5210.c ret = ar5k_channel(hal, channel);
hal 599 dev/ic/ar5210.c ret = ar5k_ar5210_do_calibrate(hal, channel);
hal 609 dev/ic/ar5210.c if (ar5k_ar5210_noise_floor(hal, channel) == AH_FALSE)
hal 626 dev/ic/ar5210.c ar5k_ar5210_do_calibrate(struct ath_hal *hal, HAL_CHANNEL *channel)
hal 634 dev/ic/ar5210.c if (ar5k_register_timeout(hal, AR5K_AR5210_PHY_AGCCTL,
hal 645 dev/ic/ar5210.c ar5k_ar5210_noise_floor(struct ath_hal *hal, HAL_CHANNEL *channel)
hal 656 dev/ic/ar5210.c if (ar5k_register_timeout(hal, AR5K_AR5210_PHY_AGCCTL,
hal 688 dev/ic/ar5210.c ar5k_ar5210_update_tx_triglevel(struct ath_hal *hal, HAL_BOOL increase)
hal 724 dev/ic/ar5210.c ar5k_ar5210_setup_tx_queue(struct ath_hal *hal, HAL_TX_QUEUE queue_type,
hal 747 dev/ic/ar5210.c bzero(&hal->ah_txq[queue], sizeof(HAL_TXQ_INFO));
hal 748 dev/ic/ar5210.c hal->ah_txq[queue].tqi_type = queue_type;
hal 751 dev/ic/ar5210.c if (ar5k_ar5210_setup_tx_queueprops(hal,
hal 760 dev/ic/ar5210.c ar5k_ar5210_setup_tx_queueprops(struct ath_hal *hal, int queue,
hal 763 dev/ic/ar5210.c AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
hal 765 dev/ic/ar5210.c if (hal->ah_txq[queue].tqi_type == HAL_TX_QUEUE_INACTIVE)
hal 768 dev/ic/ar5210.c hal->ah_txq[queue].tqi_aifs = queue_info->tqi_aifs;
hal 769 dev/ic/ar5210.c hal->ah_txq[queue].tqi_cw_max = queue_info->tqi_cw_max;
hal 770 dev/ic/ar5210.c hal->ah_txq[queue].tqi_cw_min = queue_info->tqi_cw_min;
hal 771 dev/ic/ar5210.c hal->ah_txq[queue].tqi_flags = queue_info->tqi_flags;
hal 777 dev/ic/ar5210.c ar5k_ar5210_get_tx_queueprops(struct ath_hal *hal, int queue,
hal 780 dev/ic/ar5210.c AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
hal 781 dev/ic/ar5210.c bcopy(&hal->ah_txq[queue], queue_info, sizeof(HAL_TXQ_INFO));
hal 786 dev/ic/ar5210.c ar5k_ar5210_release_tx_queue(struct ath_hal *hal, u_int queue)
hal 788 dev/ic/ar5210.c AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
hal 791 dev/ic/ar5210.c hal->ah_txq[queue].tqi_type = HAL_TX_QUEUE_INACTIVE;
hal 797 dev/ic/ar5210.c ar5k_ar5210_init_tx_queue(struct ath_hal *hal, u_int aifs, HAL_BOOL turbo)
hal 815 dev/ic/ar5210.c ar5k_ar5210_reset_tx_queue(struct ath_hal *hal, u_int queue)
hal 820 dev/ic/ar5210.c AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
hal 822 dev/ic/ar5210.c tq = &hal->ah_txq[queue];
hal 829 dev/ic/ar5210.c ar5k_ar5210_init_tx_queue(hal, hal->ah_aifs + tq->tqi_aifs,
hal 830 dev/ic/ar5210.c hal->ah_turbo == AH_TRUE ? AH_TRUE : AH_FALSE);
hal 835 dev/ic/ar5210.c if (hal->ah_software_retry == AH_TRUE) {
hal 837 dev/ic/ar5210.c retry_lg = hal->ah_limit_tx_retries;
hal 850 dev/ic/ar5210.c while (cw_min < hal->ah_cw_min)
hal 869 dev/ic/ar5210.c ar5k_ar5210_get_tx_buf(struct ath_hal *hal, u_int queue)
hal 873 dev/ic/ar5210.c AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
hal 878 dev/ic/ar5210.c switch (hal->ah_txq[queue].tqi_type) {
hal 894 dev/ic/ar5210.c ar5k_ar5210_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr)
hal 898 dev/ic/ar5210.c AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
hal 903 dev/ic/ar5210.c switch (hal->ah_txq[queue].tqi_type) {
hal 922 dev/ic/ar5210.c ar5k_ar5210_num_tx_pending(struct ath_hal *hal, u_int queue)
hal 928 dev/ic/ar5210.c ar5k_ar5210_tx_start(struct ath_hal *hal, u_int queue)
hal 932 dev/ic/ar5210.c AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
hal 939 dev/ic/ar5210.c switch (hal->ah_txq[queue].tqi_type) {
hal 968 dev/ic/ar5210.c ar5k_ar5210_stop_tx_dma(struct ath_hal *hal, u_int queue)
hal 972 dev/ic/ar5210.c AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
hal 979 dev/ic/ar5210.c switch (hal->ah_txq[queue].tqi_type) {
hal 1002 dev/ic/ar5210.c ar5k_ar5210_setup_tx_desc(struct ath_hal *hal, struct ath_desc *desc,
hal 1072 dev/ic/ar5210.c ar5k_ar5210_fill_tx_desc(struct ath_hal *hal, struct ath_desc *desc,
hal 1097 dev/ic/ar5210.c ar5k_ar5210_setup_xtx_desc(struct ath_hal *hal, struct ath_desc *desc,
hal 1110 dev/ic/ar5210.c ar5k_ar5210_proc_tx_desc(struct ath_hal *hal, struct ath_desc *desc)
hal 1165 dev/ic/ar5210.c ar5k_ar5210_has_veol(struct ath_hal *hal)
hal 1175 dev/ic/ar5210.c ar5k_ar5210_get_rx_buf(struct ath_hal *hal)
hal 1181 dev/ic/ar5210.c ar5k_ar5210_put_rx_buf(struct ath_hal *hal, u_int32_t phys_addr)
hal 1187 dev/ic/ar5210.c ar5k_ar5210_start_rx(struct ath_hal *hal)
hal 1193 dev/ic/ar5210.c ar5k_ar5210_stop_rx_dma(struct ath_hal *hal)
hal 1211 dev/ic/ar5210.c ar5k_ar5210_start_rx_pcu(struct ath_hal *hal)
hal 1217 dev/ic/ar5210.c ar5k_ar5210_stop_pcu_recv(struct ath_hal *hal)
hal 1223 dev/ic/ar5210.c ar5k_ar5210_set_mcast_filter(struct ath_hal *hal, u_int32_t filter0,
hal 1232 dev/ic/ar5210.c ar5k_ar5210_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index)
hal 1248 dev/ic/ar5210.c ar5k_ar5210_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index)
hal 1264 dev/ic/ar5210.c ar5k_ar5210_get_rx_filter(struct ath_hal *hal)
hal 1270 dev/ic/ar5210.c ar5k_ar5210_set_rx_filter(struct ath_hal *hal, u_int32_t filter)
hal 1284 dev/ic/ar5210.c ar5k_ar5210_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc,
hal 1302 dev/ic/ar5210.c ar5k_ar5210_proc_rx_desc(struct ath_hal *hal, struct ath_desc *desc,
hal 1375 dev/ic/ar5210.c ar5k_ar5210_set_rx_signal(struct ath_hal *hal)
hal 1385 dev/ic/ar5210.c ar5k_ar5210_dump_state(struct ath_hal *hal)
hal 1475 dev/ic/ar5210.c ar5k_ar5210_get_diag_state(struct ath_hal *hal, int id, void **device,
hal 1486 dev/ic/ar5210.c ar5k_ar5210_get_lladdr(struct ath_hal *hal, u_int8_t *mac)
hal 1488 dev/ic/ar5210.c bcopy(hal->ah_sta_id, mac, IEEE80211_ADDR_LEN);
hal 1492 dev/ic/ar5210.c ar5k_ar5210_set_lladdr(struct ath_hal *hal, const u_int8_t *mac)
hal 1497 dev/ic/ar5210.c bcopy(mac, hal->ah_sta_id, IEEE80211_ADDR_LEN);
hal 1509 dev/ic/ar5210.c ar5k_ar5210_set_regdomain(struct ath_hal *hal, u_int16_t regdomain,
hal 1516 dev/ic/ar5210.c if (ar5k_eeprom_regulation_domain(hal, AH_TRUE,
hal 1528 dev/ic/ar5210.c ar5k_ar5210_set_ledstate(struct ath_hal *hal, HAL_LED_STATE state)
hal 1559 dev/ic/ar5210.c ar5k_ar5210_set_associd(struct ath_hal *hal, const u_int8_t *bssid,
hal 1572 dev/ic/ar5210.c bcopy(bssid, &hal->ah_bssid, IEEE80211_ADDR_LEN);
hal 1575 dev/ic/ar5210.c ar5k_ar5210_disable_pspoll(hal);
hal 1582 dev/ic/ar5210.c ar5k_ar5210_enable_pspoll(hal, NULL, 0);
hal 1586 dev/ic/ar5210.c ar5k_ar5210_set_bssid_mask(struct ath_hal *hal, const u_int8_t* mask)
hal 1593 dev/ic/ar5210.c ar5k_ar5210_set_gpio_output(struct ath_hal *hal, u_int32_t gpio)
hal 1606 dev/ic/ar5210.c ar5k_ar5210_set_gpio_input(struct ath_hal *hal, u_int32_t gpio)
hal 1619 dev/ic/ar5210.c ar5k_ar5210_get_gpio(struct ath_hal *hal, u_int32_t gpio)
hal 1630 dev/ic/ar5210.c ar5k_ar5210_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val)
hal 1649 dev/ic/ar5210.c ar5k_ar5210_set_gpio_intr(struct ath_hal *hal, u_int gpio,
hal 1668 dev/ic/ar5210.c hal->ah_imr |= AR5K_AR5210_IMR_GPIO;
hal 1675 dev/ic/ar5210.c ar5k_ar5210_get_tsf32(struct ath_hal *hal)
hal 1681 dev/ic/ar5210.c ar5k_ar5210_get_tsf64(struct ath_hal *hal)
hal 1688 dev/ic/ar5210.c ar5k_ar5210_reset_tsf(struct ath_hal *hal)
hal 1695 dev/ic/ar5210.c ar5k_ar5210_get_regdomain(struct ath_hal *hal)
hal 1697 dev/ic/ar5210.c return (ar5k_get_regdomain(hal));
hal 1701 dev/ic/ar5210.c ar5k_ar5210_detect_card_present(struct ath_hal *hal)
hal 1710 dev/ic/ar5210.c if (ar5k_ar5210_eeprom_read(hal, AR5K_EEPROM_MAGIC, &magic) != 0)
hal 1717 dev/ic/ar5210.c ar5k_ar5210_update_mib_counters(struct ath_hal *hal, HAL_MIB_STATS *statistics)
hal 1727 dev/ic/ar5210.c ar5k_ar5210_get_rf_gain(struct ath_hal *hal)
hal 1733 dev/ic/ar5210.c ar5k_ar5210_set_slot_time(struct ath_hal *hal, u_int slot_time)
hal 1739 dev/ic/ar5210.c ar5k_htoclock(slot_time, hal->ah_turbo));
hal 1745 dev/ic/ar5210.c ar5k_ar5210_get_slot_time(struct ath_hal *hal)
hal 1748 dev/ic/ar5210.c 0xffff, hal->ah_turbo));
hal 1752 dev/ic/ar5210.c ar5k_ar5210_set_ack_timeout(struct ath_hal *hal, u_int timeout)
hal 1755 dev/ic/ar5210.c hal->ah_turbo) <= timeout)
hal 1759 dev/ic/ar5210.c ar5k_htoclock(timeout, hal->ah_turbo));
hal 1765 dev/ic/ar5210.c ar5k_ar5210_get_ack_timeout(struct ath_hal *hal)
hal 1768 dev/ic/ar5210.c AR5K_AR5210_TIME_OUT_ACK), hal->ah_turbo));
hal 1772 dev/ic/ar5210.c ar5k_ar5210_set_cts_timeout(struct ath_hal *hal, u_int timeout)
hal 1775 dev/ic/ar5210.c hal->ah_turbo) <= timeout)
hal 1779 dev/ic/ar5210.c ar5k_htoclock(timeout, hal->ah_turbo));
hal 1785 dev/ic/ar5210.c ar5k_ar5210_get_cts_timeout(struct ath_hal *hal)
hal 1788 dev/ic/ar5210.c AR5K_AR5210_TIME_OUT_CTS), hal->ah_turbo));
hal 1796 dev/ic/ar5210.c ar5k_ar5210_is_cipher_supported(struct ath_hal *hal, HAL_CIPHER cipher)
hal 1808 dev/ic/ar5210.c ar5k_ar5210_get_keycache_size(struct ath_hal *hal)
hal 1814 dev/ic/ar5210.c ar5k_ar5210_reset_key(struct ath_hal *hal, u_int16_t entry)
hal 1827 dev/ic/ar5210.c ar5k_ar5210_is_key_valid(struct ath_hal *hal, u_int16_t entry)
hal 1842 dev/ic/ar5210.c ar5k_ar5210_set_key(struct ath_hal *hal, u_int16_t entry,
hal 1885 dev/ic/ar5210.c return (ar5k_ar5210_set_key_lladdr(hal, entry, mac));
hal 1889 dev/ic/ar5210.c ar5k_ar5210_set_key_lladdr(struct ath_hal *hal, u_int16_t entry,
hal 1917 dev/ic/ar5210.c ar5k_ar5210_set_power(struct ath_hal *hal, HAL_POWER_MODE mode,
hal 1975 dev/ic/ar5210.c hal->ah_power_mode = mode;
hal 1983 dev/ic/ar5210.c ar5k_ar5210_get_power_mode(struct ath_hal *hal)
hal 1985 dev/ic/ar5210.c return (hal->ah_power_mode);
hal 1989 dev/ic/ar5210.c ar5k_ar5210_query_pspoll_support(struct ath_hal *hal)
hal 1996 dev/ic/ar5210.c ar5k_ar5210_init_pspoll(struct ath_hal *hal)
hal 2005 dev/ic/ar5210.c ar5k_ar5210_enable_pspoll(struct ath_hal *hal, u_int8_t *bssid,
hal 2016 dev/ic/ar5210.c ar5k_ar5210_disable_pspoll(struct ath_hal *hal)
hal 2030 dev/ic/ar5210.c ar5k_ar5210_init_beacon(struct ath_hal *hal, u_int32_t next_beacon,
hal 2038 dev/ic/ar5210.c switch (hal->ah_op_mode) {
hal 2048 dev/ic/ar5210.c timer3 = next_beacon + hal->ah_atim_window;
hal 2067 dev/ic/ar5210.c ar5k_ar5210_set_beacon_timers(struct ath_hal *hal,
hal 2127 dev/ic/ar5210.c ar5k_ar5210_reset_beacon(struct ath_hal *hal)
hal 2143 dev/ic/ar5210.c ar5k_ar5210_wait_for_beacon(struct ath_hal *hal, bus_addr_t phys_addr)
hal 2176 dev/ic/ar5210.c ar5k_ar5210_is_intr_pending(struct ath_hal *hal)
hal 2182 dev/ic/ar5210.c ar5k_ar5210_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask)
hal 2194 dev/ic/ar5210.c *interrupt_mask = (data & HAL_INT_COMMON) & hal->ah_imr;
hal 2207 dev/ic/ar5210.c hal->ah_radar.r_enabled == AH_TRUE)
hal 2208 dev/ic/ar5210.c ar5k_radar_alert(hal);
hal 2217 dev/ic/ar5210.c ar5k_ar5210_get_intr(struct ath_hal *hal)
hal 2220 dev/ic/ar5210.c return (hal->ah_imr);
hal 2224 dev/ic/ar5210.c ar5k_ar5210_set_intr(struct ath_hal *hal, HAL_INT new_mask)
hal 2234 dev/ic/ar5210.c old_mask = hal->ah_imr;
hal 2257 dev/ic/ar5210.c hal->ah_imr = new_mask;
hal 2272 dev/ic/ar5210.c ar5k_ar5210_get_capabilities(struct ath_hal *hal)
hal 2275 dev/ic/ar5210.c hal->ah_capabilities.cap_queues.q_tx_num = AR5K_AR5210_TX_NUM_QUEUES;
hal 2281 dev/ic/ar5210.c hal->ah_capabilities.cap_range.range_5ghz_min = 5120;
hal 2282 dev/ic/ar5210.c hal->ah_capabilities.cap_range.range_5ghz_max = 5430;
hal 2283 dev/ic/ar5210.c hal->ah_capabilities.cap_range.range_2ghz_min = 0;
hal 2284 dev/ic/ar5210.c hal->ah_capabilities.cap_range.range_2ghz_max = 0;
hal 2287 dev/ic/ar5210.c hal->ah_capabilities.cap_mode = HAL_MODE_11A | HAL_MODE_TURBO;
hal 2290 dev/ic/ar5210.c hal->ah_gpio_npins = AR5K_AR5210_NUM_GPIO;
hal 2296 dev/ic/ar5210.c ar5k_ar5210_radar_alert(struct ath_hal *hal, HAL_BOOL enable)
hal 2320 dev/ic/ar5210.c ar5k_ar5210_eeprom_is_busy(struct ath_hal *hal)
hal 2327 dev/ic/ar5210.c ar5k_ar5210_eeprom_read(struct ath_hal *hal, u_int32_t offset, u_int16_t *data)
hal 2355 dev/ic/ar5210.c ar5k_ar5210_eeprom_write(struct ath_hal *hal, u_int32_t offset, u_int16_t data)
hal 2381 dev/ic/ar5210.c ar5k_ar5210_set_txpower_limit(struct ath_hal *hal, u_int power)
hal 48 dev/ic/ar5211.c ar5k_ar5211_fill(struct ath_hal *hal)
hal 50 dev/ic/ar5211.c hal->ah_magic = AR5K_AR5211_MAGIC;
hal 55 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, get_rate_table);
hal 56 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, detach);
hal 61 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, reset);
hal 62 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, set_opmode);
hal 63 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, calibrate);
hal 68 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, update_tx_triglevel);
hal 69 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, setup_tx_queue);
hal 70 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, setup_tx_queueprops);
hal 71 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, release_tx_queue);
hal 72 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, reset_tx_queue);
hal 73 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, get_tx_buf);
hal 74 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, put_tx_buf);
hal 75 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, tx_start);
hal 76 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, stop_tx_dma);
hal 77 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, setup_tx_desc);
hal 78 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, setup_xtx_desc);
hal 79 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, fill_tx_desc);
hal 80 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, proc_tx_desc);
hal 81 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, has_veol);
hal 86 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, get_rx_buf);
hal 87 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, put_rx_buf);
hal 88 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, start_rx);
hal 89 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, stop_rx_dma);
hal 90 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, start_rx_pcu);
hal 91 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, stop_pcu_recv);
hal 92 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, set_mcast_filter);
hal 93 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, set_mcast_filterindex);
hal 94 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, clear_mcast_filter_idx);
hal 95 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, get_rx_filter);
hal 96 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, set_rx_filter);
hal 97 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, setup_rx_desc);
hal 98 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, proc_rx_desc);
hal 99 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, set_rx_signal);
hal 104 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, dump_state);
hal 105 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, get_diag_state);
hal 106 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, get_lladdr);
hal 107 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, set_lladdr);
hal 108 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, set_regdomain);
hal 109 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, set_ledstate);
hal 110 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, set_associd);
hal 111 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, set_gpio_input);
hal 112 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, set_gpio_output);
hal 113 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, get_gpio);
hal 114 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, set_gpio);
hal 115 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, set_gpio_intr);
hal 116 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, get_tsf32);
hal 117 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, get_tsf64);
hal 118 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, reset_tsf);
hal 119 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, get_regdomain);
hal 120 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, detect_card_present);
hal 121 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, update_mib_counters);
hal 122 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, get_rf_gain);
hal 123 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, set_slot_time);
hal 124 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, get_slot_time);
hal 125 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, set_ack_timeout);
hal 126 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, get_ack_timeout);
hal 127 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, set_cts_timeout);
hal 128 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, get_cts_timeout);
hal 133 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, is_cipher_supported);
hal 134 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, get_keycache_size);
hal 135 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, reset_key);
hal 136 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, is_key_valid);
hal 137 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, set_key);
hal 138 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, set_key_lladdr);
hal 143 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, set_power);
hal 144 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, get_power_mode);
hal 145 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, query_pspoll_support);
hal 146 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, init_pspoll);
hal 147 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, enable_pspoll);
hal 148 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, disable_pspoll);
hal 153 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, init_beacon);
hal 154 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, set_beacon_timers);
hal 155 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, reset_beacon);
hal 156 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, wait_for_beacon);
hal 161 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, is_intr_pending);
hal 162 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, get_isr);
hal 163 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, get_intr);
hal 164 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, set_intr);
hal 169 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, get_capabilities);
hal 170 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, radar_alert);
hal 175 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, eeprom_is_busy);
hal 176 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, eeprom_read);
hal 177 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, eeprom_write);
hal 182 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, get_tx_queueprops);
hal 183 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, num_tx_pending);
hal 184 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, phy_disable);
hal 185 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, set_txpower_limit);
hal 186 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, set_def_antenna);
hal 187 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, get_def_antenna);
hal 188 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, set_bssid_mask);
hal 190 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, set_capability);
hal 191 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, proc_mib_event);
hal 192 dev/ic/ar5211.c AR5K_HAL_FUNCTION(hal, ar5211, get_tx_inter_queue);
hal 200 dev/ic/ar5211.c struct ath_hal *hal = (struct ath_hal*) sc;
hal 204 dev/ic/ar5211.c ar5k_ar5211_fill(hal);
hal 207 dev/ic/ar5211.c if (ar5k_ar5211_nic_wakeup(hal, AR5K_INIT_MODE) != AH_TRUE)
hal 212 dev/ic/ar5211.c hal->ah_mac_srev = srev;
hal 213 dev/ic/ar5211.c hal->ah_mac_version = AR5K_REG_MS(srev, AR5K_AR5211_SREV_VER);
hal 214 dev/ic/ar5211.c hal->ah_mac_revision = AR5K_REG_MS(srev, AR5K_AR5211_SREV_REV);
hal 215 dev/ic/ar5211.c hal->ah_phy_revision = AR5K_REG_READ(AR5K_AR5211_PHY_CHIP_ID) &
hal 217 dev/ic/ar5211.c hal->ah_radio_5ghz_revision =
hal 218 dev/ic/ar5211.c ar5k_ar5211_radio_revision(hal, HAL_CHIP_5GHZ);
hal 219 dev/ic/ar5211.c hal->ah_radio_2ghz_revision = 0;
hal 222 dev/ic/ar5211.c hal->ah_version = AR5K_AR5211;
hal 223 dev/ic/ar5211.c hal->ah_radio = AR5K_AR5111;
hal 224 dev/ic/ar5211.c hal->ah_phy = AR5K_AR5211_PHY(0);
hal 227 dev/ic/ar5211.c ar5k_ar5211_set_associd(hal, mac, 0, 0);
hal 228 dev/ic/ar5211.c ar5k_ar5211_get_lladdr(hal, mac);
hal 229 dev/ic/ar5211.c ar5k_ar5211_set_opmode(hal);
hal 231 dev/ic/ar5211.c return (hal);
hal 235 dev/ic/ar5211.c ar5k_ar5211_nic_reset(struct ath_hal *hal, u_int32_t val)
hal 257 dev/ic/ar5211.c ret = ar5k_register_timeout(hal, AR5K_AR5211_RC, mask, val, AH_FALSE);
hal 269 dev/ic/ar5211.c ar5k_ar5211_nic_wakeup(struct ath_hal *hal, u_int16_t flags)
hal 313 dev/ic/ar5211.c if (ar5k_ar5211_nic_reset(hal,
hal 320 dev/ic/ar5211.c if (ar5k_ar5211_set_power(hal,
hal 327 dev/ic/ar5211.c if (ar5k_ar5211_nic_reset(hal, 0) == AH_FALSE) {
hal 343 dev/ic/ar5211.c ar5k_ar5211_radio_revision(struct ath_hal *hal, HAL_CHIP chip)
hal 381 dev/ic/ar5211.c ar5k_ar5211_get_rate_table(struct ath_hal *hal, u_int mode)
hal 385 dev/ic/ar5211.c return (&hal->ah_rt_11a);
hal 387 dev/ic/ar5211.c return (&hal->ah_rt_turbo);
hal 389 dev/ic/ar5211.c return (&hal->ah_rt_11b);
hal 392 dev/ic/ar5211.c return (&hal->ah_rt_11g);
hal 401 dev/ic/ar5211.c ar5k_ar5211_detach(struct ath_hal *hal)
hal 406 dev/ic/ar5211.c free(hal, M_DEVBUF);
hal 410 dev/ic/ar5211.c ar5k_ar5211_phy_disable(struct ath_hal *hal)
hal 417 dev/ic/ar5211.c ar5k_ar5211_reset(struct ath_hal *hal, HAL_OPMODE op_mode, HAL_CHANNEL *channel,
hal 420 dev/ic/ar5211.c struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
hal 441 dev/ic/ar5211.c if (ar5k_ar5211_nic_wakeup(hal, channel->c_channel_flags) == AH_FALSE)
hal 447 dev/ic/ar5211.c hal->ah_op_mode = op_mode;
hal 482 dev/ic/ar5211.c ar5k_ar5211_rfregs(hal, channel, freq, ee_mode);
hal 510 dev/ic/ar5211.c if (ar5k_rfgain(hal, AR5K_INI_PHY_5111, freq) == AH_FALSE)
hal 519 dev/ic/ar5211.c if (hal->ah_radio == AR5K_AR5111) {
hal 530 dev/ic/ar5211.c hal->ah_antenna[ee_mode][0], 0xfffffc06);
hal 538 dev/ic/ar5211.c hal->ah_antenna[ee_mode][ant[0]]);
hal 540 dev/ic/ar5211.c hal->ah_antenna[ee_mode][ant[1]]);
hal 587 dev/ic/ar5211.c ar5k_ar5211_set_associd(hal, mac, 0, 0);
hal 588 dev/ic/ar5211.c ar5k_ar5211_set_opmode(hal);
hal 603 dev/ic/ar5211.c if (ar5k_channel(hal, channel) == AH_FALSE)
hal 626 dev/ic/ar5211.c hal->ah_calibration = AH_FALSE;
hal 628 dev/ic/ar5211.c hal->ah_calibration = AH_TRUE;
hal 638 dev/ic/ar5211.c for (i = 0; i < hal->ah_capabilities.cap_queues.q_tx_num; i++) {
hal 640 dev/ic/ar5211.c if (ar5k_ar5211_reset_tx_queue(hal, i) == AH_FALSE) {
hal 647 dev/ic/ar5211.c ar5k_ar5211_set_intr(hal, HAL_INT_RX | HAL_INT_TX | HAL_INT_FATAL);
hal 652 dev/ic/ar5211.c if (AR5K_EEPROM_HDR_RFKILL(hal->ah_capabilities.cap_eeprom.ee_header)) {
hal 653 dev/ic/ar5211.c ar5k_ar5211_set_gpio_input(hal, 0);
hal 654 dev/ic/ar5211.c if ((hal->ah_gpio[0] = ar5k_ar5211_get_gpio(hal, 0)) == 0)
hal 655 dev/ic/ar5211.c ar5k_ar5211_set_gpio_intr(hal, 0, 1);
hal 657 dev/ic/ar5211.c ar5k_ar5211_set_gpio_intr(hal, 0, 0);
hal 670 dev/ic/ar5211.c ar5k_ar5211_set_def_antenna(struct ath_hal *hal, u_int ant)
hal 676 dev/ic/ar5211.c ar5k_ar5211_get_def_antenna(struct ath_hal *hal)
hal 682 dev/ic/ar5211.c ar5k_ar5211_set_opmode(struct ath_hal *hal)
hal 688 dev/ic/ar5211.c switch (hal->ah_op_mode) {
hal 711 dev/ic/ar5211.c low_id = AR5K_LOW_ID(hal->ah_sta_id);
hal 712 dev/ic/ar5211.c high_id = AR5K_HIGH_ID(hal->ah_sta_id);
hal 720 dev/ic/ar5211.c ar5k_ar5211_calibrate(struct ath_hal *hal, HAL_CHANNEL *channel)
hal 725 dev/ic/ar5211.c if (hal->ah_calibration == AH_FALSE ||
hal 729 dev/ic/ar5211.c hal->ah_calibration = AH_FALSE;
hal 762 dev/ic/ar5211.c ar5k_ar5211_update_tx_triglevel(struct ath_hal *hal, HAL_BOOL increase)
hal 770 dev/ic/ar5211.c imr = ar5k_ar5211_set_intr(hal, hal->ah_imr & ~HAL_INT_GLOBAL);
hal 793 dev/ic/ar5211.c ar5k_ar5211_set_intr(hal, imr);
hal 799 dev/ic/ar5211.c ar5k_ar5211_setup_tx_queue(struct ath_hal *hal, HAL_TX_QUEUE queue_type,
hal 809 dev/ic/ar5211.c hal->ah_txq[queue].tqi_type != HAL_TX_QUEUE_INACTIVE;
hal 825 dev/ic/ar5211.c bzero(&hal->ah_txq[queue], sizeof(HAL_TXQ_INFO));
hal 826 dev/ic/ar5211.c hal->ah_txq[queue].tqi_type = queue_type;
hal 829 dev/ic/ar5211.c if (ar5k_ar5211_setup_tx_queueprops(hal, queue, queue_info)
hal 834 dev/ic/ar5211.c AR5K_Q_ENABLE_BITS(hal->ah_txq_interrupts, queue);
hal 840 dev/ic/ar5211.c ar5k_ar5211_setup_tx_queueprops(struct ath_hal *hal, int queue,
hal 843 dev/ic/ar5211.c AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
hal 845 dev/ic/ar5211.c if (hal->ah_txq[queue].tqi_type == HAL_TX_QUEUE_INACTIVE)
hal 848 dev/ic/ar5211.c bcopy(queue_info, &hal->ah_txq[queue], sizeof(HAL_TXQ_INFO));
hal 853 dev/ic/ar5211.c hal->ah_txq[queue].tqi_flags |=
hal 860 dev/ic/ar5211.c ar5k_ar5211_get_tx_queueprops(struct ath_hal *hal, int queue,
hal 863 dev/ic/ar5211.c AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
hal 864 dev/ic/ar5211.c bcopy(&hal->ah_txq[queue], queue_info, sizeof(HAL_TXQ_INFO));
hal 869 dev/ic/ar5211.c ar5k_ar5211_release_tx_queue(struct ath_hal *hal, u_int queue)
hal 871 dev/ic/ar5211.c AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
hal 874 dev/ic/ar5211.c hal->ah_txq[queue].tqi_type = HAL_TX_QUEUE_INACTIVE;
hal 875 dev/ic/ar5211.c AR5K_Q_DISABLE_BITS(hal->ah_txq_interrupts, queue);
hal 881 dev/ic/ar5211.c ar5k_ar5211_reset_tx_queue(struct ath_hal *hal, u_int queue)
hal 885 dev/ic/ar5211.c &hal->ah_current_channel;
hal 888 dev/ic/ar5211.c AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
hal 890 dev/ic/ar5211.c tq = &hal->ah_txq[queue];
hal 899 dev/ic/ar5211.c hal->ah_cw_min = AR5K_TUNE_CWMIN_11B;
hal 900 dev/ic/ar5211.c cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_11B;
hal 901 dev/ic/ar5211.c hal->ah_aifs = AR5K_TUNE_AIFS_11B;
hal 903 dev/ic/ar5211.c hal->ah_cw_min = AR5K_TUNE_CWMIN;
hal 904 dev/ic/ar5211.c cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX;
hal 905 dev/ic/ar5211.c hal->ah_aifs = AR5K_TUNE_AIFS;
hal 911 dev/ic/ar5211.c if (hal->ah_software_retry == AH_TRUE) {
hal 913 dev/ic/ar5211.c retry_lg = hal->ah_limit_tx_retries;
hal 934 dev/ic/ar5211.c while (cw_min < hal->ah_cw_min)
hal 947 dev/ic/ar5211.c AR5K_REG_SM(hal->ah_aifs + tq->tqi_aifs,
hal 1046 dev/ic/ar5211.c AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR0_QCU_TXOK) |
hal 1047 dev/ic/ar5211.c AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR0_QCU_TXDESC));
hal 1049 dev/ic/ar5211.c AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR1_QCU_TXERR));
hal 1051 dev/ic/ar5211.c AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR2_QCU_TXURN));
hal 1057 dev/ic/ar5211.c ar5k_ar5211_get_tx_buf(struct ath_hal *hal, u_int queue)
hal 1059 dev/ic/ar5211.c AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
hal 1068 dev/ic/ar5211.c ar5k_ar5211_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr)
hal 1070 dev/ic/ar5211.c AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
hal 1085 dev/ic/ar5211.c ar5k_ar5211_num_tx_pending(struct ath_hal *hal, u_int queue)
hal 1087 dev/ic/ar5211.c AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
hal 1092 dev/ic/ar5211.c ar5k_ar5211_tx_start(struct ath_hal *hal, u_int queue)
hal 1094 dev/ic/ar5211.c AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
hal 1107 dev/ic/ar5211.c ar5k_ar5211_stop_tx_dma(struct ath_hal *hal, u_int queue)
hal 1111 dev/ic/ar5211.c AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
hal 1131 dev/ic/ar5211.c ar5k_ar5211_setup_tx_desc(struct ath_hal *hal, struct ath_desc *desc,
hal 1184 dev/ic/ar5211.c ar5k_ar5211_fill_tx_desc(struct ath_hal *hal, struct ath_desc *desc,
hal 1209 dev/ic/ar5211.c ar5k_ar5211_setup_xtx_desc(struct ath_hal *hal, struct ath_desc *desc,
hal 1217 dev/ic/ar5211.c ar5k_ar5211_proc_tx_desc(struct ath_hal *hal, struct ath_desc *desc)
hal 1272 dev/ic/ar5211.c ar5k_ar5211_has_veol(struct ath_hal *hal)
hal 1282 dev/ic/ar5211.c ar5k_ar5211_get_rx_buf(struct ath_hal *hal)
hal 1288 dev/ic/ar5211.c ar5k_ar5211_put_rx_buf(struct ath_hal *hal, u_int32_t phys_addr)
hal 1294 dev/ic/ar5211.c ar5k_ar5211_start_rx(struct ath_hal *hal)
hal 1300 dev/ic/ar5211.c ar5k_ar5211_stop_rx_dma(struct ath_hal *hal)
hal 1318 dev/ic/ar5211.c ar5k_ar5211_start_rx_pcu(struct ath_hal *hal)
hal 1324 dev/ic/ar5211.c ar5k_ar5211_stop_pcu_recv(struct ath_hal *hal)
hal 1330 dev/ic/ar5211.c ar5k_ar5211_set_mcast_filter(struct ath_hal *hal, u_int32_t filter0,
hal 1339 dev/ic/ar5211.c ar5k_ar5211_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index)
hal 1355 dev/ic/ar5211.c ar5k_ar5211_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index)
hal 1372 dev/ic/ar5211.c ar5k_ar5211_get_rx_filter(struct ath_hal *hal)
hal 1378 dev/ic/ar5211.c ar5k_ar5211_set_rx_filter(struct ath_hal *hal, u_int32_t filter)
hal 1384 dev/ic/ar5211.c ar5k_ar5211_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc,
hal 1402 dev/ic/ar5211.c ar5k_ar5211_proc_rx_desc(struct ath_hal *hal, struct ath_desc *desc,
hal 1471 dev/ic/ar5211.c ar5k_ar5211_set_rx_signal(struct ath_hal *hal)
hal 1481 dev/ic/ar5211.c ar5k_ar5211_dump_state(struct ath_hal *hal)
hal 1570 dev/ic/ar5211.c ar5k_ar5211_get_diag_state(struct ath_hal *hal, int id, void **device,
hal 1581 dev/ic/ar5211.c ar5k_ar5211_get_lladdr(struct ath_hal *hal, u_int8_t *mac)
hal 1583 dev/ic/ar5211.c bcopy(hal->ah_sta_id, mac, IEEE80211_ADDR_LEN);
hal 1587 dev/ic/ar5211.c ar5k_ar5211_set_lladdr(struct ath_hal *hal, const u_int8_t *mac)
hal 1592 dev/ic/ar5211.c bcopy(mac, hal->ah_sta_id, IEEE80211_ADDR_LEN);
hal 1604 dev/ic/ar5211.c ar5k_ar5211_set_regdomain(struct ath_hal *hal, u_int16_t regdomain,
hal 1611 dev/ic/ar5211.c if (ar5k_eeprom_regulation_domain(hal, AH_TRUE,
hal 1623 dev/ic/ar5211.c ar5k_ar5211_set_ledstate(struct ath_hal *hal, HAL_LED_STATE state)
hal 1661 dev/ic/ar5211.c ar5k_ar5211_set_associd(struct ath_hal *hal, const u_int8_t *bssid,
hal 1674 dev/ic/ar5211.c bcopy(bssid, hal->ah_bssid, IEEE80211_ADDR_LEN);
hal 1677 dev/ic/ar5211.c ar5k_ar5211_disable_pspoll(hal);
hal 1688 dev/ic/ar5211.c ar5k_ar5211_enable_pspoll(hal, NULL, 0);
hal 1692 dev/ic/ar5211.c ar5k_ar5211_set_bssid_mask(struct ath_hal *hal, const u_int8_t* mask)
hal 1699 dev/ic/ar5211.c ar5k_ar5211_set_gpio_output(struct ath_hal *hal, u_int32_t gpio)
hal 1712 dev/ic/ar5211.c ar5k_ar5211_set_gpio_input(struct ath_hal *hal, u_int32_t gpio)
hal 1725 dev/ic/ar5211.c ar5k_ar5211_get_gpio(struct ath_hal *hal, u_int32_t gpio)
hal 1736 dev/ic/ar5211.c ar5k_ar5211_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val)
hal 1755 dev/ic/ar5211.c ar5k_ar5211_set_gpio_intr(struct ath_hal *hal, u_int gpio,
hal 1774 dev/ic/ar5211.c hal->ah_imr |= AR5K_AR5211_PIMR_GPIO;
hal 1781 dev/ic/ar5211.c ar5k_ar5211_get_tsf32(struct ath_hal *hal)
hal 1787 dev/ic/ar5211.c ar5k_ar5211_get_tsf64(struct ath_hal *hal)
hal 1795 dev/ic/ar5211.c ar5k_ar5211_reset_tsf(struct ath_hal *hal)
hal 1802 dev/ic/ar5211.c ar5k_ar5211_get_regdomain(struct ath_hal *hal)
hal 1804 dev/ic/ar5211.c return (ar5k_get_regdomain(hal));
hal 1808 dev/ic/ar5211.c ar5k_ar5211_detect_card_present(struct ath_hal *hal)
hal 1817 dev/ic/ar5211.c if (ar5k_ar5211_eeprom_read(hal, AR5K_EEPROM_MAGIC, &magic) != 0)
hal 1824 dev/ic/ar5211.c ar5k_ar5211_update_mib_counters(struct ath_hal *hal, HAL_MIB_STATS *statistics)
hal 1834 dev/ic/ar5211.c ar5k_ar5211_get_rf_gain(struct ath_hal *hal)
hal 1840 dev/ic/ar5211.c ar5k_ar5211_set_slot_time(struct ath_hal *hal, u_int slot_time)
hal 1851 dev/ic/ar5211.c ar5k_ar5211_get_slot_time(struct ath_hal *hal)
hal 1857 dev/ic/ar5211.c ar5k_ar5211_set_ack_timeout(struct ath_hal *hal, u_int timeout)
hal 1860 dev/ic/ar5211.c hal->ah_turbo) <= timeout)
hal 1864 dev/ic/ar5211.c ar5k_htoclock(timeout, hal->ah_turbo));
hal 1870 dev/ic/ar5211.c ar5k_ar5211_get_ack_timeout(struct ath_hal *hal)
hal 1873 dev/ic/ar5211.c AR5K_AR5211_TIME_OUT_ACK), hal->ah_turbo));
hal 1877 dev/ic/ar5211.c ar5k_ar5211_set_cts_timeout(struct ath_hal *hal, u_int timeout)
hal 1880 dev/ic/ar5211.c hal->ah_turbo) <= timeout)
hal 1884 dev/ic/ar5211.c ar5k_htoclock(timeout, hal->ah_turbo));
hal 1890 dev/ic/ar5211.c ar5k_ar5211_get_cts_timeout(struct ath_hal *hal)
hal 1893 dev/ic/ar5211.c AR5K_AR5211_TIME_OUT_CTS), hal->ah_turbo));
hal 1901 dev/ic/ar5211.c ar5k_ar5211_is_cipher_supported(struct ath_hal *hal, HAL_CIPHER cipher)
hal 1913 dev/ic/ar5211.c ar5k_ar5211_get_keycache_size(struct ath_hal *hal)
hal 1919 dev/ic/ar5211.c ar5k_ar5211_reset_key(struct ath_hal *hal, u_int16_t entry)
hal 1932 dev/ic/ar5211.c ar5k_ar5211_is_key_valid(struct ath_hal *hal, u_int16_t entry)
hal 1947 dev/ic/ar5211.c ar5k_ar5211_set_key(struct ath_hal *hal, u_int16_t entry,
hal 1990 dev/ic/ar5211.c return (ar5k_ar5211_set_key_lladdr(hal, entry, mac));
hal 1994 dev/ic/ar5211.c ar5k_ar5211_set_key_lladdr(struct ath_hal *hal, u_int16_t entry,
hal 2022 dev/ic/ar5211.c ar5k_ar5211_set_power(struct ath_hal *hal, HAL_POWER_MODE mode,
hal 2080 dev/ic/ar5211.c hal->ah_power_mode = mode;
hal 2088 dev/ic/ar5211.c ar5k_ar5211_get_power_mode(struct ath_hal *hal)
hal 2090 dev/ic/ar5211.c return (hal->ah_power_mode);
hal 2094 dev/ic/ar5211.c ar5k_ar5211_query_pspoll_support(struct ath_hal *hal)
hal 2101 dev/ic/ar5211.c ar5k_ar5211_init_pspoll(struct ath_hal *hal)
hal 2110 dev/ic/ar5211.c ar5k_ar5211_enable_pspoll(struct ath_hal *hal, u_int8_t *bssid,
hal 2117 dev/ic/ar5211.c ar5k_ar5211_disable_pspoll(struct ath_hal *hal)
hal 2127 dev/ic/ar5211.c ar5k_ar5211_init_beacon(struct ath_hal *hal, u_int32_t next_beacon,
hal 2135 dev/ic/ar5211.c switch (hal->ah_op_mode) {
hal 2149 dev/ic/ar5211.c (hal->ah_atim_window ? hal->ah_atim_window : 1);
hal 2166 dev/ic/ar5211.c ar5k_ar5211_set_beacon_timers(struct ath_hal *hal,
hal 2229 dev/ic/ar5211.c ar5k_ar5211_reset_beacon(struct ath_hal *hal)
hal 2245 dev/ic/ar5211.c ar5k_ar5211_wait_for_beacon(struct ath_hal *hal, bus_addr_t phys_addr)
hal 2252 dev/ic/ar5211.c ret = ar5k_register_timeout(hal,
hal 2267 dev/ic/ar5211.c ar5k_ar5211_is_intr_pending(struct ath_hal *hal)
hal 2273 dev/ic/ar5211.c ar5k_ar5211_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask)
hal 2285 dev/ic/ar5211.c *interrupt_mask = (data & HAL_INT_COMMON) & hal->ah_imr;
hal 2303 dev/ic/ar5211.c hal->ah_radar.r_enabled == AH_TRUE)
hal 2304 dev/ic/ar5211.c ar5k_radar_alert(hal);
hal 2310 dev/ic/ar5211.c ar5k_ar5211_get_intr(struct ath_hal *hal)
hal 2313 dev/ic/ar5211.c return (hal->ah_imr);
hal 2317 dev/ic/ar5211.c ar5k_ar5211_set_intr(struct ath_hal *hal, HAL_INT new_mask)
hal 2327 dev/ic/ar5211.c old_mask = hal->ah_imr;
hal 2360 dev/ic/ar5211.c hal->ah_imr = new_mask;
hal 2373 dev/ic/ar5211.c ar5k_ar5211_get_capabilities(struct ath_hal *hal)
hal 2378 dev/ic/ar5211.c ee_header = hal->ah_capabilities.cap_eeprom.ee_header;
hal 2395 dev/ic/ar5211.c hal->ah_capabilities.cap_range.range_5ghz_min = 5005; /* 4920 */
hal 2396 dev/ic/ar5211.c hal->ah_capabilities.cap_range.range_5ghz_max = 6100;
hal 2399 dev/ic/ar5211.c hal->ah_capabilities.cap_mode = HAL_MODE_11A | HAL_MODE_TURBO;
hal 2404 dev/ic/ar5211.c hal->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */
hal 2405 dev/ic/ar5211.c hal->ah_capabilities.cap_range.range_2ghz_max = 2732;
hal 2408 dev/ic/ar5211.c hal->ah_capabilities.cap_mode |= HAL_MODE_11B;
hal 2411 dev/ic/ar5211.c hal->ah_capabilities.cap_mode |= HAL_MODE_11G;
hal 2416 dev/ic/ar5211.c hal->ah_gpio_npins = AR5K_AR5211_NUM_GPIO;
hal 2419 dev/ic/ar5211.c hal->ah_capabilities.cap_queues.q_tx_num = AR5K_AR5211_TX_NUM_QUEUES;
hal 2425 dev/ic/ar5211.c ar5k_ar5211_radar_alert(struct ath_hal *hal, HAL_BOOL enable)
hal 2452 dev/ic/ar5211.c ar5k_ar5211_eeprom_is_busy(struct ath_hal *hal)
hal 2459 dev/ic/ar5211.c ar5k_ar5211_eeprom_read(struct ath_hal *hal, u_int32_t offset, u_int16_t *data)
hal 2486 dev/ic/ar5211.c ar5k_ar5211_eeprom_write(struct ath_hal *hal, u_int32_t offset, u_int16_t data)
hal 2519 dev/ic/ar5211.c ar5k_ar5211_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int freq,
hal 2522 dev/ic/ar5211.c struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
hal 2531 dev/ic/ar5211.c hal->ah_ee_version >= AR5K_EEPROM_VERSION_3_1) {
hal 2574 dev/ic/ar5211.c hal->ah_rf_gain = HAL_RFGAIN_INACTIVE;
hal 2578 dev/ic/ar5211.c ar5k_ar5211_set_txpower_limit(struct ath_hal *hal, u_int power)
hal 45 dev/ic/ar5212.c ar5k_ar5212_fill(struct ath_hal *hal)
hal 47 dev/ic/ar5212.c hal->ah_magic = AR5K_AR5212_MAGIC;
hal 52 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, get_rate_table);
hal 53 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, detach);
hal 58 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, reset);
hal 59 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, set_opmode);
hal 60 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, calibrate);
hal 65 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, update_tx_triglevel);
hal 66 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, setup_tx_queue);
hal 67 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, setup_tx_queueprops);
hal 68 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, release_tx_queue);
hal 69 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, reset_tx_queue);
hal 70 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, get_tx_buf);
hal 71 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, put_tx_buf);
hal 72 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, tx_start);
hal 73 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, stop_tx_dma);
hal 74 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, setup_tx_desc);
hal 75 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, setup_xtx_desc);
hal 76 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, fill_tx_desc);
hal 77 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, proc_tx_desc);
hal 78 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, has_veol);
hal 83 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, get_rx_buf);
hal 84 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, put_rx_buf);
hal 85 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, start_rx);
hal 86 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, stop_rx_dma);
hal 87 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, start_rx_pcu);
hal 88 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, stop_pcu_recv);
hal 89 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, set_mcast_filter);
hal 90 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, set_mcast_filterindex);
hal 91 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, clear_mcast_filter_idx);
hal 92 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, get_rx_filter);
hal 93 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, set_rx_filter);
hal 94 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, setup_rx_desc);
hal 95 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, proc_rx_desc);
hal 96 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, set_rx_signal);
hal 101 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, dump_state);
hal 102 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, get_diag_state);
hal 103 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, get_lladdr);
hal 104 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, set_lladdr);
hal 105 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, set_regdomain);
hal 106 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, set_ledstate);
hal 107 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, set_associd);
hal 108 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, set_gpio_input);
hal 109 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, set_gpio_output);
hal 110 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, get_gpio);
hal 111 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, set_gpio);
hal 112 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, set_gpio_intr);
hal 113 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, get_tsf32);
hal 114 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, get_tsf64);
hal 115 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, reset_tsf);
hal 116 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, get_regdomain);
hal 117 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, detect_card_present);
hal 118 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, update_mib_counters);
hal 119 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, get_rf_gain);
hal 120 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, set_slot_time);
hal 121 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, get_slot_time);
hal 122 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, set_ack_timeout);
hal 123 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, get_ack_timeout);
hal 124 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, set_cts_timeout);
hal 125 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, get_cts_timeout);
hal 130 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, is_cipher_supported);
hal 131 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, get_keycache_size);
hal 132 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, reset_key);
hal 133 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, is_key_valid);
hal 134 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, set_key);
hal 135 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, set_key_lladdr);
hal 140 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, set_power);
hal 141 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, get_power_mode);
hal 142 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, query_pspoll_support);
hal 143 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, init_pspoll);
hal 144 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, enable_pspoll);
hal 145 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, disable_pspoll);
hal 150 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, init_beacon);
hal 151 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, set_beacon_timers);
hal 152 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, reset_beacon);
hal 153 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, wait_for_beacon);
hal 158 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, is_intr_pending);
hal 159 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, get_isr);
hal 160 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, get_intr);
hal 161 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, set_intr);
hal 166 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, get_capabilities);
hal 167 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, radar_alert);
hal 172 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, eeprom_is_busy);
hal 173 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, eeprom_read);
hal 174 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, eeprom_write);
hal 179 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, set_bssid_mask);
hal 180 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, get_tx_queueprops);
hal 181 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, num_tx_pending);
hal 182 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, phy_disable);
hal 183 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, set_txpower_limit);
hal 184 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, set_def_antenna);
hal 185 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, get_def_antenna);
hal 187 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, set_capability);
hal 188 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, proc_mib_event);
hal 189 dev/ic/ar5212.c AR5K_HAL_FUNCTION(hal, ar5212, get_tx_inter_queue);
hal 197 dev/ic/ar5212.c struct ath_hal *hal = (struct ath_hal*) sc;
hal 201 dev/ic/ar5212.c ar5k_ar5212_fill(hal);
hal 204 dev/ic/ar5212.c if (ar5k_ar5212_nic_wakeup(hal, AR5K_INIT_MODE) != AH_TRUE)
hal 209 dev/ic/ar5212.c hal->ah_mac_srev = srev;
hal 210 dev/ic/ar5212.c hal->ah_mac_version = AR5K_REG_MS(srev, AR5K_AR5212_SREV_VER);
hal 211 dev/ic/ar5212.c hal->ah_mac_revision = AR5K_REG_MS(srev, AR5K_AR5212_SREV_REV);
hal 212 dev/ic/ar5212.c hal->ah_phy_revision = AR5K_REG_READ(AR5K_AR5212_PHY_CHIP_ID) &
hal 214 dev/ic/ar5212.c hal->ah_radio_5ghz_revision =
hal 215 dev/ic/ar5212.c ar5k_ar5212_radio_revision(hal, HAL_CHIP_5GHZ);
hal 216 dev/ic/ar5212.c hal->ah_radio_2ghz_revision =
hal 217 dev/ic/ar5212.c ar5k_ar5212_radio_revision(hal, HAL_CHIP_2GHZ);
hal 220 dev/ic/ar5212.c if (hal->ah_radio_2ghz_revision == hal->ah_radio_5ghz_revision)
hal 221 dev/ic/ar5212.c hal->ah_radio_2ghz_revision = 0;
hal 224 dev/ic/ar5212.c hal->ah_version = AR5K_AR5212;
hal 225 dev/ic/ar5212.c hal->ah_radio = hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112 ?
hal 227 dev/ic/ar5212.c hal->ah_phy = AR5K_AR5212_PHY(0);
hal 230 dev/ic/ar5212.c ar5k_ar5212_set_associd(hal, mac, 0, 0);
hal 231 dev/ic/ar5212.c ar5k_ar5212_get_lladdr(hal, mac);
hal 232 dev/ic/ar5212.c ar5k_ar5212_set_opmode(hal);
hal 234 dev/ic/ar5212.c return (hal);
hal 238 dev/ic/ar5212.c ar5k_ar5212_nic_reset(struct ath_hal *hal, u_int32_t val)
hal 260 dev/ic/ar5212.c ret = ar5k_register_timeout(hal, AR5K_AR5212_RC, mask, val, AH_FALSE);
hal 272 dev/ic/ar5212.c ar5k_ar5212_nic_wakeup(struct ath_hal *hal, u_int16_t flags)
hal 284 dev/ic/ar5212.c if (hal->ah_radio >= AR5K_AR5112) {
hal 324 dev/ic/ar5212.c if (hal->ah_single_chip == AH_FALSE &&
hal 325 dev/ic/ar5212.c ar5k_ar5212_nic_reset(hal,
hal 332 dev/ic/ar5212.c if (ar5k_ar5212_set_power(hal,
hal 339 dev/ic/ar5212.c if (ar5k_ar5212_nic_reset(hal, 0) == AH_FALSE) {
hal 355 dev/ic/ar5212.c ar5k_ar5212_radio_revision(struct ath_hal *hal, HAL_CHIP chip)
hal 393 dev/ic/ar5212.c ar5k_ar5212_get_rate_table(struct ath_hal *hal, u_int mode)
hal 397 dev/ic/ar5212.c return (&hal->ah_rt_11a);
hal 399 dev/ic/ar5212.c return (&hal->ah_rt_turbo);
hal 401 dev/ic/ar5212.c return (&hal->ah_rt_11b);
hal 404 dev/ic/ar5212.c return (&hal->ah_rt_11g);
hal 406 dev/ic/ar5212.c return (&hal->ah_rt_xr);
hal 415 dev/ic/ar5212.c ar5k_ar5212_detach(struct ath_hal *hal)
hal 417 dev/ic/ar5212.c if (hal->ah_rf_banks != NULL)
hal 418 dev/ic/ar5212.c free(hal->ah_rf_banks, M_DEVBUF);
hal 423 dev/ic/ar5212.c free(hal, M_DEVBUF);
hal 427 dev/ic/ar5212.c ar5k_ar5212_phy_disable(struct ath_hal *hal)
hal 434 dev/ic/ar5212.c ar5k_ar5212_reset(struct ath_hal *hal, HAL_OPMODE op_mode, HAL_CHANNEL *channel,
hal 437 dev/ic/ar5212.c struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
hal 459 dev/ic/ar5212.c if (change_channel == AH_TRUE && hal->ah_rf_banks != NULL)
hal 460 dev/ic/ar5212.c ar5k_ar5212_get_rf_gain(hal);
hal 462 dev/ic/ar5212.c if (ar5k_ar5212_nic_wakeup(hal, channel->c_channel_flags) == AH_FALSE)
hal 468 dev/ic/ar5212.c hal->ah_op_mode = op_mode;
hal 470 dev/ic/ar5212.c if (hal->ah_radio == AR5K_AR5111) {
hal 472 dev/ic/ar5212.c } else if (hal->ah_radio == AR5K_AR5112) {
hal 475 dev/ic/ar5212.c AR5K_PRINTF("invalid phy radio: %u\n", hal->ah_radio);
hal 526 dev/ic/ar5212.c hal->ah_radio == AR5K_AR5111)
hal 529 dev/ic/ar5212.c hal->ah_radio == AR5K_AR5112)
hal 548 dev/ic/ar5212.c if ((hal->ah_radio == AR5K_AR5111 &&
hal 550 dev/ic/ar5212.c (hal->ah_radio == AR5K_AR5112 &&
hal 561 dev/ic/ar5212.c if (ar5k_rfgain(hal, phy, freq) == AH_FALSE)
hal 569 dev/ic/ar5212.c rt = ar5k_ar5212_get_rate_table(hal,
hal 575 dev/ic/ar5212.c ath_hal_computetxtime(hal, rt, 14,
hal 580 dev/ic/ar5212.c rt = ar5k_ar5212_get_rate_table(hal, HAL_MODE_11B);
hal 584 dev/ic/ar5212.c ath_hal_computetxtime(hal, rt, 14,
hal 589 dev/ic/ar5212.c ath_hal_computetxtime(hal, rt, 14,
hal 596 dev/ic/ar5212.c if (hal->ah_radio >= AR5K_AR5112 &&
hal 597 dev/ic/ar5212.c hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) {
hal 610 dev/ic/ar5212.c if (ar5k_ar5212_txpower(hal, channel,
hal 617 dev/ic/ar5212.c if (ar5k_rfregs(hal, channel, mode) == AH_FALSE)
hal 650 dev/ic/ar5212.c if (hal->ah_radio == AR5K_AR5111) {
hal 661 dev/ic/ar5212.c hal->ah_antenna[ee_mode][0], 0xfffffc06);
hal 669 dev/ic/ar5212.c hal->ah_antenna[ee_mode][ant[0]]);
hal 671 dev/ic/ar5212.c hal->ah_antenna[ee_mode][ant[1]]);
hal 674 dev/ic/ar5212.c if (hal->ah_radio == AR5K_AR5111)
hal 706 dev/ic/ar5212.c if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) {
hal 725 dev/ic/ar5212.c ar5k_ar5212_set_associd(hal, mac, 0, 0);
hal 726 dev/ic/ar5212.c ar5k_ar5212_set_opmode(hal);
hal 741 dev/ic/ar5212.c if (ar5k_channel(hal, channel) == AH_FALSE)
hal 763 dev/ic/ar5212.c hal->ah_calibration = AH_FALSE;
hal 765 dev/ic/ar5212.c hal->ah_calibration = AH_TRUE;
hal 775 dev/ic/ar5212.c for (i = 0; i < hal->ah_capabilities.cap_queues.q_tx_num; i++) {
hal 777 dev/ic/ar5212.c if (ar5k_ar5212_reset_tx_queue(hal, i) == AH_FALSE) {
hal 784 dev/ic/ar5212.c ar5k_ar5212_set_intr(hal, HAL_INT_RX | HAL_INT_TX | HAL_INT_FATAL);
hal 789 dev/ic/ar5212.c if (AR5K_EEPROM_HDR_RFKILL(hal->ah_capabilities.cap_eeprom.ee_header)) {
hal 790 dev/ic/ar5212.c ar5k_ar5212_set_gpio_input(hal, 0);
hal 791 dev/ic/ar5212.c if ((hal->ah_gpio[0] = ar5k_ar5212_get_gpio(hal, 0)) == 0)
hal 792 dev/ic/ar5212.c ar5k_ar5212_set_gpio_intr(hal, 0, 1);
hal 794 dev/ic/ar5212.c ar5k_ar5212_set_gpio_intr(hal, 0, 0);
hal 805 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY_SPENDING, hal->ah_radio == AR5K_AR5111 ?
hal 818 dev/ic/ar5212.c ar5k_ar5212_set_def_antenna(struct ath_hal *hal, u_int ant)
hal 824 dev/ic/ar5212.c ar5k_ar5212_get_def_antenna(struct ath_hal *hal)
hal 830 dev/ic/ar5212.c ar5k_ar5212_set_opmode(struct ath_hal *hal)
hal 836 dev/ic/ar5212.c switch (hal->ah_op_mode) {
hal 859 dev/ic/ar5212.c low_id = AR5K_LOW_ID(hal->ah_sta_id);
hal 860 dev/ic/ar5212.c high_id = AR5K_HIGH_ID(hal->ah_sta_id);
hal 868 dev/ic/ar5212.c ar5k_ar5212_calibrate(struct ath_hal *hal, HAL_CHANNEL *channel)
hal 873 dev/ic/ar5212.c if (hal->ah_calibration == AH_FALSE ||
hal 877 dev/ic/ar5212.c hal->ah_calibration = AH_FALSE;
hal 905 dev/ic/ar5212.c AR5K_REG_SM(hal->ah_txpower.txp_max,
hal 908 dev/ic/ar5212.c hal->ah_rf_gain = HAL_RFGAIN_READ_REQUESTED;
hal 919 dev/ic/ar5212.c ar5k_ar5212_update_tx_triglevel(struct ath_hal *hal, HAL_BOOL increase)
hal 927 dev/ic/ar5212.c imr = ar5k_ar5212_set_intr(hal, hal->ah_imr & ~HAL_INT_GLOBAL);
hal 950 dev/ic/ar5212.c ar5k_ar5212_set_intr(hal, imr);
hal 956 dev/ic/ar5212.c ar5k_ar5212_setup_tx_queue(struct ath_hal *hal, HAL_TX_QUEUE queue_type,
hal 966 dev/ic/ar5212.c hal->ah_txq[queue].tqi_type != HAL_TX_QUEUE_INACTIVE;
hal 982 dev/ic/ar5212.c bzero(&hal->ah_txq[queue], sizeof(HAL_TXQ_INFO));
hal 984 dev/ic/ar5212.c if (ar5k_ar5212_setup_tx_queueprops(hal, queue, queue_info)
hal 988 dev/ic/ar5212.c hal->ah_txq[queue].tqi_type = queue_type;
hal 990 dev/ic/ar5212.c AR5K_Q_ENABLE_BITS(hal->ah_txq_interrupts, queue);
hal 996 dev/ic/ar5212.c ar5k_ar5212_setup_tx_queueprops(struct ath_hal *hal, int queue,
hal 999 dev/ic/ar5212.c AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
hal 1001 dev/ic/ar5212.c if (hal->ah_txq[queue].tqi_type != HAL_TX_QUEUE_INACTIVE)
hal 1004 dev/ic/ar5212.c bcopy(queue_info, &hal->ah_txq[queue], sizeof(HAL_TXQ_INFO));
hal 1009 dev/ic/ar5212.c hal->ah_txq[queue].tqi_flags |=
hal 1016 dev/ic/ar5212.c ar5k_ar5212_get_tx_queueprops(struct ath_hal *hal, int queue,
hal 1019 dev/ic/ar5212.c AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
hal 1020 dev/ic/ar5212.c bcopy(&hal->ah_txq[queue], queue_info, sizeof(HAL_TXQ_INFO));
hal 1025 dev/ic/ar5212.c ar5k_ar5212_release_tx_queue(struct ath_hal *hal, u_int queue)
hal 1027 dev/ic/ar5212.c AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
hal 1030 dev/ic/ar5212.c hal->ah_txq[queue].tqi_type = HAL_TX_QUEUE_INACTIVE;
hal 1031 dev/ic/ar5212.c AR5K_Q_DISABLE_BITS(hal->ah_txq_interrupts, queue);
hal 1037 dev/ic/ar5212.c ar5k_ar5212_reset_tx_queue(struct ath_hal *hal, u_int queue)
hal 1041 dev/ic/ar5212.c &hal->ah_current_channel;
hal 1044 dev/ic/ar5212.c AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
hal 1046 dev/ic/ar5212.c tq = &hal->ah_txq[queue];
hal 1054 dev/ic/ar5212.c cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN;
hal 1055 dev/ic/ar5212.c cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX;
hal 1056 dev/ic/ar5212.c hal->ah_aifs = AR5K_TUNE_AIFS;
hal 1058 dev/ic/ar5212.c cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN_XR;
hal 1059 dev/ic/ar5212.c cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_XR;
hal 1060 dev/ic/ar5212.c hal->ah_aifs = AR5K_TUNE_AIFS_XR;
hal 1062 dev/ic/ar5212.c cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN_11B;
hal 1063 dev/ic/ar5212.c cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_11B;
hal 1064 dev/ic/ar5212.c hal->ah_aifs = AR5K_TUNE_AIFS_11B;
hal 1070 dev/ic/ar5212.c if (hal->ah_software_retry == AH_TRUE) {
hal 1072 dev/ic/ar5212.c retry_lg = hal->ah_limit_tx_retries;
hal 1093 dev/ic/ar5212.c while (cw_min < hal->ah_cw_min)
hal 1106 dev/ic/ar5212.c AR5K_REG_SM(hal->ah_aifs + tq->tqi_aifs,
hal 1205 dev/ic/ar5212.c AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR0_QCU_TXOK) |
hal 1206 dev/ic/ar5212.c AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR0_QCU_TXDESC));
hal 1208 dev/ic/ar5212.c AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR1_QCU_TXERR));
hal 1210 dev/ic/ar5212.c AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR2_QCU_TXURN));
hal 1216 dev/ic/ar5212.c ar5k_ar5212_get_tx_buf(struct ath_hal *hal, u_int queue)
hal 1218 dev/ic/ar5212.c AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
hal 1227 dev/ic/ar5212.c ar5k_ar5212_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr)
hal 1229 dev/ic/ar5212.c AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
hal 1244 dev/ic/ar5212.c ar5k_ar5212_num_tx_pending(struct ath_hal *hal, u_int queue)
hal 1246 dev/ic/ar5212.c AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
hal 1251 dev/ic/ar5212.c ar5k_ar5212_tx_start(struct ath_hal *hal, u_int queue)
hal 1253 dev/ic/ar5212.c AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
hal 1266 dev/ic/ar5212.c ar5k_ar5212_stop_tx_dma(struct ath_hal *hal, u_int queue)
hal 1270 dev/ic/ar5212.c AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
hal 1290 dev/ic/ar5212.c ar5k_ar5212_setup_tx_desc(struct ath_hal *hal, struct ath_desc *desc,
hal 1363 dev/ic/ar5212.c ar5k_ar5212_fill_tx_desc(struct ath_hal *hal, struct ath_desc *desc,
hal 1390 dev/ic/ar5212.c ar5k_ar5212_setup_xtx_desc(struct ath_hal *hal, struct ath_desc *desc,
hal 1418 dev/ic/ar5212.c ar5k_ar5212_proc_tx_desc(struct ath_hal *hal, struct ath_desc *desc)
hal 1503 dev/ic/ar5212.c ar5k_ar5212_has_veol(struct ath_hal *hal)
hal 1513 dev/ic/ar5212.c ar5k_ar5212_get_rx_buf(struct ath_hal *hal)
hal 1519 dev/ic/ar5212.c ar5k_ar5212_put_rx_buf(struct ath_hal *hal, u_int32_t phys_addr)
hal 1525 dev/ic/ar5212.c ar5k_ar5212_start_rx(struct ath_hal *hal)
hal 1531 dev/ic/ar5212.c ar5k_ar5212_stop_rx_dma(struct ath_hal *hal)
hal 1549 dev/ic/ar5212.c ar5k_ar5212_start_rx_pcu(struct ath_hal *hal)
hal 1555 dev/ic/ar5212.c ar5k_ar5212_stop_pcu_recv(struct ath_hal *hal)
hal 1561 dev/ic/ar5212.c ar5k_ar5212_set_mcast_filter(struct ath_hal *hal, u_int32_t filter0,
hal 1570 dev/ic/ar5212.c ar5k_ar5212_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index)
hal 1586 dev/ic/ar5212.c ar5k_ar5212_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index)
hal 1603 dev/ic/ar5212.c ar5k_ar5212_get_rx_filter(struct ath_hal *hal)
hal 1620 dev/ic/ar5212.c ar5k_ar5212_set_rx_filter(struct ath_hal *hal, u_int32_t filter)
hal 1643 dev/ic/ar5212.c ar5k_ar5212_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc,
hal 1661 dev/ic/ar5212.c ar5k_ar5212_proc_rx_desc(struct ath_hal *hal, struct ath_desc *desc,
hal 1738 dev/ic/ar5212.c ar5k_ar5212_set_rx_signal(struct ath_hal *hal)
hal 1748 dev/ic/ar5212.c ar5k_ar5212_dump_state(struct ath_hal *hal)
hal 1852 dev/ic/ar5212.c ar5k_ar5212_get_diag_state(struct ath_hal *hal, int id, void **device,
hal 1863 dev/ic/ar5212.c ar5k_ar5212_get_lladdr(struct ath_hal *hal, u_int8_t *mac)
hal 1865 dev/ic/ar5212.c bcopy(hal->ah_sta_id, mac, IEEE80211_ADDR_LEN);
hal 1869 dev/ic/ar5212.c ar5k_ar5212_set_lladdr(struct ath_hal *hal, const u_int8_t *mac)
hal 1874 dev/ic/ar5212.c bcopy(mac, hal->ah_sta_id, IEEE80211_ADDR_LEN);
hal 1886 dev/ic/ar5212.c ar5k_ar5212_set_regdomain(struct ath_hal *hal, u_int16_t regdomain,
hal 1893 dev/ic/ar5212.c if (ar5k_eeprom_regulation_domain(hal, AH_TRUE,
hal 1905 dev/ic/ar5212.c ar5k_ar5212_set_ledstate(struct ath_hal *hal, HAL_LED_STATE state)
hal 1943 dev/ic/ar5212.c ar5k_ar5212_set_associd(struct ath_hal *hal, const u_int8_t *bssid,
hal 1962 dev/ic/ar5212.c bcopy(bssid, &hal->ah_bssid, IEEE80211_ADDR_LEN);
hal 1965 dev/ic/ar5212.c ar5k_ar5212_disable_pspoll(hal);
hal 1976 dev/ic/ar5212.c ar5k_ar5212_enable_pspoll(hal, NULL, 0);
hal 1980 dev/ic/ar5212.c ar5k_ar5212_set_bssid_mask(struct ath_hal *hal, const u_int8_t* mask)
hal 1994 dev/ic/ar5212.c ar5k_ar5212_set_gpio_output(struct ath_hal *hal, u_int32_t gpio)
hal 2007 dev/ic/ar5212.c ar5k_ar5212_set_gpio_input(struct ath_hal *hal, u_int32_t gpio)
hal 2020 dev/ic/ar5212.c ar5k_ar5212_get_gpio(struct ath_hal *hal, u_int32_t gpio)
hal 2031 dev/ic/ar5212.c ar5k_ar5212_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val)
hal 2050 dev/ic/ar5212.c ar5k_ar5212_set_gpio_intr(struct ath_hal *hal, u_int gpio,
hal 2069 dev/ic/ar5212.c hal->ah_imr |= AR5K_AR5212_PIMR_GPIO;
hal 2076 dev/ic/ar5212.c ar5k_ar5212_get_tsf32(struct ath_hal *hal)
hal 2082 dev/ic/ar5212.c ar5k_ar5212_get_tsf64(struct ath_hal *hal)
hal 2090 dev/ic/ar5212.c ar5k_ar5212_reset_tsf(struct ath_hal *hal)
hal 2097 dev/ic/ar5212.c ar5k_ar5212_get_regdomain(struct ath_hal *hal)
hal 2099 dev/ic/ar5212.c return (ar5k_get_regdomain(hal));
hal 2103 dev/ic/ar5212.c ar5k_ar5212_detect_card_present(struct ath_hal *hal)
hal 2112 dev/ic/ar5212.c if (ar5k_ar5212_eeprom_read(hal, AR5K_EEPROM_MAGIC, &magic) != 0)
hal 2119 dev/ic/ar5212.c ar5k_ar5212_update_mib_counters(struct ath_hal *hal, HAL_MIB_STATS *statistics)
hal 2136 dev/ic/ar5212.c ar5k_ar5212_get_rf_gain(struct ath_hal *hal)
hal 2140 dev/ic/ar5212.c if ((hal->ah_rf_banks == NULL) || (!hal->ah_gain.g_active))
hal 2143 dev/ic/ar5212.c if (hal->ah_rf_gain != HAL_RFGAIN_READ_REQUESTED)
hal 2149 dev/ic/ar5212.c hal->ah_gain.g_current =
hal 2154 dev/ic/ar5212.c hal->ah_gain.g_current += AR5K_GAIN_CCK_PROBE_CORR;
hal 2156 dev/ic/ar5212.c if (hal->ah_radio == AR5K_AR5112) {
hal 2157 dev/ic/ar5212.c ar5k_rfregs_gainf_corr(hal);
hal 2158 dev/ic/ar5212.c hal->ah_gain.g_current =
hal 2159 dev/ic/ar5212.c hal->ah_gain.g_current >= hal->ah_gain.g_f_corr ?
hal 2160 dev/ic/ar5212.c (hal->ah_gain.g_current - hal->ah_gain.g_f_corr) :
hal 2164 dev/ic/ar5212.c if (ar5k_rfregs_gain_readback(hal) &&
hal 2165 dev/ic/ar5212.c AR5K_GAIN_CHECK_ADJUST(&hal->ah_gain) &&
hal 2166 dev/ic/ar5212.c ar5k_rfregs_gain_adjust(hal))
hal 2167 dev/ic/ar5212.c hal->ah_rf_gain = HAL_RFGAIN_NEED_CHANGE;
hal 2171 dev/ic/ar5212.c return (hal->ah_rf_gain);
hal 2175 dev/ic/ar5212.c ar5k_ar5212_set_slot_time(struct ath_hal *hal, u_int slot_time)
hal 2186 dev/ic/ar5212.c ar5k_ar5212_get_slot_time(struct ath_hal *hal)
hal 2192 dev/ic/ar5212.c ar5k_ar5212_set_ack_timeout(struct ath_hal *hal, u_int timeout)
hal 2195 dev/ic/ar5212.c hal->ah_turbo) <= timeout)
hal 2199 dev/ic/ar5212.c ar5k_htoclock(timeout, hal->ah_turbo));
hal 2205 dev/ic/ar5212.c ar5k_ar5212_get_ack_timeout(struct ath_hal *hal)
hal 2208 dev/ic/ar5212.c AR5K_AR5212_TIME_OUT_ACK), hal->ah_turbo));
hal 2212 dev/ic/ar5212.c ar5k_ar5212_set_cts_timeout(struct ath_hal *hal, u_int timeout)
hal 2215 dev/ic/ar5212.c hal->ah_turbo) <= timeout)
hal 2219 dev/ic/ar5212.c ar5k_htoclock(timeout, hal->ah_turbo));
hal 2225 dev/ic/ar5212.c ar5k_ar5212_get_cts_timeout(struct ath_hal *hal)
hal 2228 dev/ic/ar5212.c AR5K_AR5212_TIME_OUT_CTS), hal->ah_turbo));
hal 2236 dev/ic/ar5212.c ar5k_ar5212_is_cipher_supported(struct ath_hal *hal, HAL_CIPHER cipher)
hal 2248 dev/ic/ar5212.c ar5k_ar5212_get_keycache_size(struct ath_hal *hal)
hal 2254 dev/ic/ar5212.c ar5k_ar5212_reset_key(struct ath_hal *hal, u_int16_t entry)
hal 2271 dev/ic/ar5212.c ar5k_ar5212_is_key_valid(struct ath_hal *hal, u_int16_t entry)
hal 2286 dev/ic/ar5212.c ar5k_ar5212_set_key(struct ath_hal *hal, u_int16_t entry,
hal 2329 dev/ic/ar5212.c return (ar5k_ar5212_set_key_lladdr(hal, entry, mac));
hal 2333 dev/ic/ar5212.c ar5k_ar5212_set_key_lladdr(struct ath_hal *hal, u_int16_t entry,
hal 2361 dev/ic/ar5212.c ar5k_ar5212_set_power(struct ath_hal *hal, HAL_POWER_MODE mode,
hal 2419 dev/ic/ar5212.c hal->ah_power_mode = mode;
hal 2427 dev/ic/ar5212.c ar5k_ar5212_get_power_mode(struct ath_hal *hal)
hal 2429 dev/ic/ar5212.c return (hal->ah_power_mode);
hal 2433 dev/ic/ar5212.c ar5k_ar5212_query_pspoll_support(struct ath_hal *hal)
hal 2440 dev/ic/ar5212.c ar5k_ar5212_init_pspoll(struct ath_hal *hal)
hal 2449 dev/ic/ar5212.c ar5k_ar5212_enable_pspoll(struct ath_hal *hal, u_int8_t *bssid,
hal 2456 dev/ic/ar5212.c ar5k_ar5212_disable_pspoll(struct ath_hal *hal)
hal 2466 dev/ic/ar5212.c ar5k_ar5212_init_beacon(struct ath_hal *hal, u_int32_t next_beacon,
hal 2474 dev/ic/ar5212.c switch (hal->ah_op_mode) {
hal 2488 dev/ic/ar5212.c (hal->ah_atim_window ? hal->ah_atim_window : 1);
hal 2505 dev/ic/ar5212.c ar5k_ar5212_set_beacon_timers(struct ath_hal *hal,
hal 2600 dev/ic/ar5212.c ar5k_ar5212_reset_beacon(struct ath_hal *hal)
hal 2616 dev/ic/ar5212.c ar5k_ar5212_wait_for_beacon(struct ath_hal *hal, bus_addr_t phys_addr)
hal 2623 dev/ic/ar5212.c ret = ar5k_register_timeout(hal,
hal 2638 dev/ic/ar5212.c ar5k_ar5212_is_intr_pending(struct ath_hal *hal)
hal 2644 dev/ic/ar5212.c ar5k_ar5212_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask)
hal 2656 dev/ic/ar5212.c *interrupt_mask = (data & HAL_INT_COMMON) & hal->ah_imr;
hal 2674 dev/ic/ar5212.c hal->ah_radar.r_enabled == AH_TRUE)
hal 2675 dev/ic/ar5212.c ar5k_radar_alert(hal);
hal 2684 dev/ic/ar5212.c ar5k_ar5212_get_intr(struct ath_hal *hal)
hal 2687 dev/ic/ar5212.c return (hal->ah_imr);
hal 2691 dev/ic/ar5212.c ar5k_ar5212_set_intr(struct ath_hal *hal, HAL_INT new_mask)
hal 2701 dev/ic/ar5212.c old_mask = hal->ah_imr;
hal 2734 dev/ic/ar5212.c hal->ah_imr = new_mask;
hal 2747 dev/ic/ar5212.c ar5k_ar5212_get_capabilities(struct ath_hal *hal)
hal 2752 dev/ic/ar5212.c ee_header = hal->ah_capabilities.cap_eeprom.ee_header;
hal 2769 dev/ic/ar5212.c hal->ah_capabilities.cap_range.range_5ghz_min = 5005; /* 4920 */
hal 2770 dev/ic/ar5212.c hal->ah_capabilities.cap_range.range_5ghz_max = 6100;
hal 2773 dev/ic/ar5212.c hal->ah_capabilities.cap_mode =
hal 2779 dev/ic/ar5212.c hal->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */
hal 2780 dev/ic/ar5212.c hal->ah_capabilities.cap_range.range_2ghz_max = 2732;
hal 2783 dev/ic/ar5212.c hal->ah_capabilities.cap_mode |= HAL_MODE_11B;
hal 2786 dev/ic/ar5212.c hal->ah_capabilities.cap_mode |= HAL_MODE_11G;
hal 2791 dev/ic/ar5212.c hal->ah_gpio_npins = AR5K_AR5212_NUM_GPIO;
hal 2794 dev/ic/ar5212.c hal->ah_capabilities.cap_queues.q_tx_num = AR5K_AR5212_TX_NUM_QUEUES;
hal 2800 dev/ic/ar5212.c ar5k_ar5212_radar_alert(struct ath_hal *hal, HAL_BOOL enable)
hal 2827 dev/ic/ar5212.c ar5k_ar5212_eeprom_is_busy(struct ath_hal *hal)
hal 2834 dev/ic/ar5212.c ar5k_ar5212_eeprom_read(struct ath_hal *hal, u_int32_t offset, u_int16_t *data)
hal 2861 dev/ic/ar5212.c ar5k_ar5212_eeprom_write(struct ath_hal *hal, u_int32_t offset, u_int16_t data)
hal 2894 dev/ic/ar5212.c ar5k_ar5212_txpower(struct ath_hal *hal, HAL_CHANNEL *channel, u_int txpower)
hal 2896 dev/ic/ar5212.c HAL_BOOL tpc = hal->ah_txpower.txp_tpc;
hal 2905 dev/ic/ar5212.c bzero(&hal->ah_txpower, sizeof(hal->ah_txpower));
hal 2906 dev/ic/ar5212.c hal->ah_txpower.txp_tpc = tpc;
hal 2909 dev/ic/ar5212.c ar5k_txpower_table(hal, channel, txpower);
hal 2916 dev/ic/ar5212.c ((((hal->ah_txpower.txp_pcdac[(i << 1) + 1] << 8) | 0xff) &
hal 2917 dev/ic/ar5212.c 0xffff) << 16) | (((hal->ah_txpower.txp_pcdac[i << 1] << 8)
hal 2937 dev/ic/ar5212.c if (hal->ah_txpower.txp_tpc == AH_TRUE) {
hal 2951 dev/ic/ar5212.c ar5k_ar5212_set_txpower_limit(struct ath_hal *hal, u_int power)
hal 2953 dev/ic/ar5212.c HAL_CHANNEL *channel = &hal->ah_current_channel;
hal 2956 dev/ic/ar5212.c return (ar5k_ar5212_txpower(hal, channel, power));
hal 154 dev/ic/ar5xxx.c struct ath_hal *hal = NULL;
hal 176 dev/ic/ar5xxx.c if ((hal = malloc(sizeof(struct ath_hal),
hal 183 dev/ic/ar5xxx.c bzero(hal, sizeof(struct ath_hal));
hal 185 dev/ic/ar5xxx.c hal->ah_sc = sc;
hal 186 dev/ic/ar5xxx.c hal->ah_st = st;
hal 187 dev/ic/ar5xxx.c hal->ah_sh = sh;
hal 188 dev/ic/ar5xxx.c hal->ah_device = device;
hal 189 dev/ic/ar5xxx.c hal->ah_sub_vendor = 0; /* XXX unknown?! */
hal 194 dev/ic/ar5xxx.c hal->ah_abi = HAL_ABI_VERSION;
hal 195 dev/ic/ar5xxx.c hal->ah_op_mode = HAL_M_STA;
hal 196 dev/ic/ar5xxx.c hal->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
hal 197 dev/ic/ar5xxx.c hal->ah_turbo = AH_FALSE;
hal 198 dev/ic/ar5xxx.c hal->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
hal 199 dev/ic/ar5xxx.c hal->ah_imr = 0;
hal 200 dev/ic/ar5xxx.c hal->ah_atim_window = 0;
hal 201 dev/ic/ar5xxx.c hal->ah_aifs = AR5K_TUNE_AIFS;
hal 202 dev/ic/ar5xxx.c hal->ah_cw_min = AR5K_TUNE_CWMIN;
hal 203 dev/ic/ar5xxx.c hal->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
hal 204 dev/ic/ar5xxx.c hal->ah_software_retry = AH_FALSE;
hal 205 dev/ic/ar5xxx.c hal->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY;
hal 214 dev/ic/ar5xxx.c hal->ah_single_chip = AH_TRUE;
hal 226 dev/ic/ar5xxx.c hal->ah_single_chip = AH_TRUE;
hal 229 dev/ic/ar5xxx.c hal->ah_single_chip = AH_FALSE;
hal 236 dev/ic/ar5xxx.c hal->ah_single_chip = AH_FALSE;
hal 240 dev/ic/ar5xxx.c if ((attach)(device, hal, st, sh, status) == NULL)
hal 244 dev/ic/ar5xxx.c hal->ah_dump_state(hal);
hal 251 dev/ic/ar5xxx.c if (ar5k_eeprom_init(hal) != 0) {
hal 257 dev/ic/ar5xxx.c if (hal->ah_get_capabilities(hal) != AH_TRUE) {
hal 264 dev/ic/ar5xxx.c if ((*status = ar5k_eeprom_read_mac(hal, mac)) != 0) {
hal 270 dev/ic/ar5xxx.c hal->ah_set_lladdr(hal, mac);
hal 273 dev/ic/ar5xxx.c if (hal->ah_capabilities.cap_mode & HAL_MODE_11A)
hal 274 dev/ic/ar5xxx.c ar5k_rt_copy(&hal->ah_rt_11a, &ar5k_rt_11a);
hal 275 dev/ic/ar5xxx.c if (hal->ah_capabilities.cap_mode & HAL_MODE_11B)
hal 276 dev/ic/ar5xxx.c ar5k_rt_copy(&hal->ah_rt_11b, &ar5k_rt_11b);
hal 277 dev/ic/ar5xxx.c if (hal->ah_capabilities.cap_mode & HAL_MODE_11G)
hal 278 dev/ic/ar5xxx.c ar5k_rt_copy(&hal->ah_rt_11g, &ar5k_rt_11g);
hal 279 dev/ic/ar5xxx.c if (hal->ah_capabilities.cap_mode & HAL_MODE_TURBO)
hal 280 dev/ic/ar5xxx.c ar5k_rt_copy(&hal->ah_rt_turbo, &ar5k_rt_turbo);
hal 281 dev/ic/ar5xxx.c if (hal->ah_capabilities.cap_mode & HAL_MODE_XR)
hal 282 dev/ic/ar5xxx.c ar5k_rt_copy(&hal->ah_rt_xr, &ar5k_rt_xr);
hal 285 dev/ic/ar5xxx.c if (hal->ah_radio == AR5K_AR5111) {
hal 286 dev/ic/ar5xxx.c hal->ah_gain.g_step_idx = ar5111_gain_opt.go_default;
hal 287 dev/ic/ar5xxx.c hal->ah_gain.g_step =
hal 288 dev/ic/ar5xxx.c &ar5111_gain_opt.go_step[hal->ah_gain.g_step_idx];
hal 289 dev/ic/ar5xxx.c hal->ah_gain.g_low = 20;
hal 290 dev/ic/ar5xxx.c hal->ah_gain.g_high = 35;
hal 291 dev/ic/ar5xxx.c hal->ah_gain.g_active = 1;
hal 292 dev/ic/ar5xxx.c } else if (hal->ah_radio == AR5K_AR5112) {
hal 293 dev/ic/ar5xxx.c hal->ah_gain.g_step_idx = ar5112_gain_opt.go_default;
hal 294 dev/ic/ar5xxx.c hal->ah_gain.g_step =
hal 295 dev/ic/ar5xxx.c &ar5111_gain_opt.go_step[hal->ah_gain.g_step_idx];
hal 296 dev/ic/ar5xxx.c hal->ah_gain.g_low = 20;
hal 297 dev/ic/ar5xxx.c hal->ah_gain.g_high = 85;
hal 298 dev/ic/ar5xxx.c hal->ah_gain.g_active = 1;
hal 303 dev/ic/ar5xxx.c return (hal);
hal 306 dev/ic/ar5xxx.c free(hal, M_DEVBUF);
hal 311 dev/ic/ar5xxx.c ath_hal_computetxtime(struct ath_hal *hal, const HAL_RATE_TABLE *rates,
hal 373 dev/ic/ar5xxx.c ar5k_check_channel(struct ath_hal *hal, u_int16_t freq, u_int flags)
hal 377 dev/ic/ar5xxx.c if ((freq >= hal->ah_capabilities.cap_range.range_2ghz_min) &&
hal 378 dev/ic/ar5xxx.c (freq <= hal->ah_capabilities.cap_range.range_2ghz_max))
hal 381 dev/ic/ar5xxx.c if ((freq >= hal->ah_capabilities.cap_range.range_5ghz_min) &&
hal 382 dev/ic/ar5xxx.c (freq <= hal->ah_capabilities.cap_range.range_5ghz_max))
hal 390 dev/ic/ar5xxx.c ath_hal_init_channels(struct ath_hal *hal, HAL_CHANNEL *channels,
hal 404 dev/ic/ar5xxx.c domain_current = hal->ah_regdomain;
hal 418 dev/ic/ar5xxx.c (hal->ah_version == AR5K_AR5211 ?
hal 424 dev/ic/ar5xxx.c if (ar5k_check_channel(hal, freq, flags) == AH_FALSE)
hal 451 dev/ic/ar5xxx.c for (i = 0; (hal->ah_capabilities.cap_range.range_5ghz_max > 0) &&
hal 455 dev/ic/ar5xxx.c if (ar5k_check_channel(hal,
hal 481 dev/ic/ar5xxx.c for (i = 0; (hal->ah_capabilities.cap_range.range_2ghz_max > 0) &&
hal 485 dev/ic/ar5xxx.c if (ar5k_check_channel(hal,
hal 496 dev/ic/ar5xxx.c if ((hal->ah_capabilities.cap_mode & HAL_MODE_11B) &&
hal 500 dev/ic/ar5xxx.c if ((hal->ah_capabilities.cap_mode & HAL_MODE_11G) &&
hal 503 dev/ic/ar5xxx.c hal->ah_version == AR5K_AR5211 ?
hal 554 dev/ic/ar5xxx.c ar5k_radar_alert(struct ath_hal *hal)
hal 559 dev/ic/ar5xxx.c if (hal->ah_radar.r_last_channel.channel ==
hal 560 dev/ic/ar5xxx.c hal->ah_current_channel.channel &&
hal 561 dev/ic/ar5xxx.c tick < (hal->ah_radar.r_last_alert + hz))
hal 564 dev/ic/ar5xxx.c hal->ah_radar.r_last_channel.channel =
hal 565 dev/ic/ar5xxx.c hal->ah_current_channel.channel;
hal 566 dev/ic/ar5xxx.c hal->ah_radar.r_last_channel.c_channel_flags =
hal 567 dev/ic/ar5xxx.c hal->ah_current_channel.c_channel_flags;
hal 568 dev/ic/ar5xxx.c hal->ah_radar.r_last_alert = tick;
hal 571 dev/ic/ar5xxx.c hal->ah_radar.r_last_alert, hal->ah_current_channel.channel);
hal 600 dev/ic/ar5xxx.c ar5k_get_regdomain(struct ath_hal *hal)
hal 608 dev/ic/ar5xxx.c ar5k_eeprom_regulation_domain(hal, AH_FALSE, &ieee_regdomain);
hal 609 dev/ic/ar5xxx.c hal->ah_capabilities.cap_regdomain.reg_hw = ieee_regdomain;
hal 621 dev/ic/ar5xxx.c hal->ah_capabilities.cap_regdomain.reg_current = regdomain;
hal 668 dev/ic/ar5xxx.c ar5k_register_timeout(struct ath_hal *hal, u_int32_t reg, u_int32_t flag,
hal 694 dev/ic/ar5xxx.c ar5k_eeprom_bin2freq(struct ath_hal *hal, u_int16_t bin, u_int mode)
hal 702 dev/ic/ar5xxx.c if (hal->ah_ee_version > AR5K_EEPROM_VERSION_3_2)
hal 709 dev/ic/ar5xxx.c if (hal->ah_ee_version > AR5K_EEPROM_VERSION_3_2)
hal 719 dev/ic/ar5xxx.c ar5k_eeprom_read_ants(struct ath_hal *hal, u_int32_t *offset, u_int mode)
hal 721 dev/ic/ar5xxx.c struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
hal 753 dev/ic/ar5xxx.c hal->ah_antenna[mode][0] =
hal 755 dev/ic/ar5xxx.c hal->ah_antenna[mode][HAL_ANT_FIXED_A] =
hal 761 dev/ic/ar5xxx.c hal->ah_antenna[mode][HAL_ANT_FIXED_B] =
hal 775 dev/ic/ar5xxx.c ar5k_eeprom_read_modes(struct ath_hal *hal, u_int32_t *offset, u_int mode)
hal 777 dev/ic/ar5xxx.c struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
hal 786 dev/ic/ar5xxx.c if (hal->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
hal 802 dev/ic/ar5xxx.c if (hal->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
hal 811 dev/ic/ar5xxx.c if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0)
hal 814 dev/ic/ar5xxx.c if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) {
hal 826 dev/ic/ar5xxx.c if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_4) {
hal 839 dev/ic/ar5xxx.c if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
hal 845 dev/ic/ar5xxx.c if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_6 &&
hal 856 dev/ic/ar5xxx.c ar5k_eeprom_init(struct ath_hal *hal)
hal 858 dev/ic/ar5xxx.c struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
hal 879 dev/ic/ar5xxx.c if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_0)
hal 897 dev/ic/ar5xxx.c AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(hal->ah_ee_version),
hal 900 dev/ic/ar5xxx.c if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
hal 905 dev/ic/ar5xxx.c if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_3) {
hal 918 dev/ic/ar5xxx.c offset = AR5K_EEPROM_CTL(hal->ah_ee_version);
hal 919 dev/ic/ar5xxx.c ee->ee_ctls = AR5K_EEPROM_N_CTLS(hal->ah_ee_version);
hal 935 dev/ic/ar5xxx.c offset = AR5K_EEPROM_MODES_11A(hal->ah_ee_version);
hal 937 dev/ic/ar5xxx.c if ((ret = ar5k_eeprom_read_ants(hal, &offset, mode)) != 0)
hal 954 dev/ic/ar5xxx.c if ((ret = ar5k_eeprom_read_modes(hal, &offset, mode)) != 0)
hal 957 dev/ic/ar5xxx.c if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) {
hal 966 dev/ic/ar5xxx.c offset = AR5K_EEPROM_MODES_11B(hal->ah_ee_version);
hal 968 dev/ic/ar5xxx.c if ((ret = ar5k_eeprom_read_ants(hal, &offset, mode)) != 0)
hal 976 dev/ic/ar5xxx.c if ((ret = ar5k_eeprom_read_modes(hal, &offset, mode)) != 0)
hal 979 dev/ic/ar5xxx.c if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
hal 982 dev/ic/ar5xxx.c ar5k_eeprom_bin2freq(hal, val & 0xff, mode);
hal 984 dev/ic/ar5xxx.c ar5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode);
hal 988 dev/ic/ar5xxx.c ar5k_eeprom_bin2freq(hal, val & 0xff, mode);
hal 991 dev/ic/ar5xxx.c if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) {
hal 999 dev/ic/ar5xxx.c offset = AR5K_EEPROM_MODES_11G(hal->ah_ee_version);
hal 1001 dev/ic/ar5xxx.c if ((ret = ar5k_eeprom_read_ants(hal, &offset, mode)) != 0)
hal 1009 dev/ic/ar5xxx.c if ((ret = ar5k_eeprom_read_modes(hal, &offset, mode)) != 0)
hal 1012 dev/ic/ar5xxx.c if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
hal 1015 dev/ic/ar5xxx.c ar5k_eeprom_bin2freq(hal, val & 0xff, mode);
hal 1017 dev/ic/ar5xxx.c ar5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode);
hal 1025 dev/ic/ar5xxx.c ar5k_eeprom_bin2freq(hal, val & 0xff, mode);
hal 1027 dev/ic/ar5xxx.c if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) {
hal 1035 dev/ic/ar5xxx.c if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) {
hal 1049 dev/ic/ar5xxx.c ar5k_eeprom_read_mac(struct ath_hal *hal, u_int8_t *mac)
hal 1059 dev/ic/ar5xxx.c if (hal->ah_eeprom_read(hal, 0x20, &data) != 0)
hal 1064 dev/ic/ar5xxx.c if (hal->ah_eeprom_read(hal, offset, &data) != 0)
hal 1082 dev/ic/ar5xxx.c ar5k_eeprom_regulation_domain(struct ath_hal *hal, HAL_BOOL write,
hal 1089 dev/ic/ar5xxx.c ee_regdomain = hal->ah_capabilities.cap_eeprom.ee_regdomain;
hal 1097 dev/ic/ar5xxx.c if (hal->ah_capabilities.cap_eeprom.ee_protect &
hal 1100 dev/ic/ar5xxx.c if (hal->ah_eeprom_write(hal, AR5K_EEPROM_REG_DOMAIN,
hal 1104 dev/ic/ar5xxx.c hal->ah_capabilities.cap_eeprom.ee_regdomain = ee_regdomain;
hal 1114 dev/ic/ar5xxx.c ar5k_channel(struct ath_hal *hal, HAL_CHANNEL *channel)
hal 1122 dev/ic/ar5xxx.c if ((channel->channel < hal->ah_capabilities.cap_range.range_2ghz_min ||
hal 1123 dev/ic/ar5xxx.c channel->channel > hal->ah_capabilities.cap_range.range_2ghz_max) &&
hal 1124 dev/ic/ar5xxx.c (channel->channel < hal->ah_capabilities.cap_range.range_5ghz_min ||
hal 1125 dev/ic/ar5xxx.c channel->channel > hal->ah_capabilities.cap_range.range_5ghz_max)) {
hal 1134 dev/ic/ar5xxx.c if (hal->ah_radio == AR5K_AR5110)
hal 1135 dev/ic/ar5xxx.c ret = ar5k_ar5110_channel(hal, channel);
hal 1136 dev/ic/ar5xxx.c else if (hal->ah_radio == AR5K_AR5111)
hal 1137 dev/ic/ar5xxx.c ret = ar5k_ar5111_channel(hal, channel);
hal 1139 dev/ic/ar5xxx.c ret = ar5k_ar5112_channel(hal, channel);
hal 1144 dev/ic/ar5xxx.c hal->ah_current_channel.c_channel = channel->c_channel;
hal 1145 dev/ic/ar5xxx.c hal->ah_current_channel.c_channel_flags = channel->c_channel_flags;
hal 1146 dev/ic/ar5xxx.c hal->ah_turbo = channel->c_channel_flags == CHANNEL_T ?
hal 1171 dev/ic/ar5xxx.c ar5k_ar5110_channel(struct ath_hal *hal, HAL_CHANNEL *channel)
hal 1213 dev/ic/ar5xxx.c ar5k_ar5111_channel(struct ath_hal *hal, HAL_CHANNEL *channel)
hal 1254 dev/ic/ar5xxx.c ar5k_ar5112_channel(struct ath_hal *hal, HAL_CHANNEL *channel)
hal 1346 dev/ic/ar5xxx.c ar5k_rfregs_gainf_corr(struct ath_hal *hal)
hal 1351 dev/ic/ar5xxx.c if (hal->ah_rf_banks == NULL)
hal 1354 dev/ic/ar5xxx.c rf = hal->ah_rf_banks;
hal 1355 dev/ic/ar5xxx.c hal->ah_gain.g_f_corr = 0;
hal 1357 dev/ic/ar5xxx.c if (ar5k_rfregs_op(rf, hal->ah_offset[7], 0, 1, 36, 0, AH_FALSE) != 1)
hal 1360 dev/ic/ar5xxx.c step = ar5k_rfregs_op(rf, hal->ah_offset[7], 0, 4, 32, 0, AH_FALSE);
hal 1361 dev/ic/ar5xxx.c mix = hal->ah_gain.g_step->gos_param[0];
hal 1365 dev/ic/ar5xxx.c hal->ah_gain.g_f_corr = step * 2;
hal 1368 dev/ic/ar5xxx.c hal->ah_gain.g_f_corr = (step - 5) * 2;
hal 1371 dev/ic/ar5xxx.c hal->ah_gain.g_f_corr = step;
hal 1374 dev/ic/ar5xxx.c hal->ah_gain.g_f_corr = 0;
hal 1378 dev/ic/ar5xxx.c return (hal->ah_gain.g_f_corr);
hal 1382 dev/ic/ar5xxx.c ar5k_rfregs_gain_readback(struct ath_hal *hal)
hal 1387 dev/ic/ar5xxx.c if (hal->ah_rf_banks == NULL)
hal 1390 dev/ic/ar5xxx.c rf = hal->ah_rf_banks;
hal 1392 dev/ic/ar5xxx.c if (hal->ah_radio == AR5K_AR5111) {
hal 1393 dev/ic/ar5xxx.c step = ar5k_rfregs_op(rf, hal->ah_offset[7],
hal 1400 dev/ic/ar5xxx.c hal->ah_gain.g_high = level[3] -
hal 1402 dev/ic/ar5xxx.c hal->ah_gain.g_low = level[0] +
hal 1405 dev/ic/ar5xxx.c mix = ar5k_rfregs_op(rf, hal->ah_offset[7],
hal 1413 dev/ic/ar5xxx.c hal->ah_gain.g_high = 55;
hal 1417 dev/ic/ar5xxx.c return ((hal->ah_gain.g_current >= level[0] &&
hal 1418 dev/ic/ar5xxx.c hal->ah_gain.g_current <= level[1]) ||
hal 1419 dev/ic/ar5xxx.c (hal->ah_gain.g_current >= level[2] &&
hal 1420 dev/ic/ar5xxx.c hal->ah_gain.g_current <= level[3]));
hal 1424 dev/ic/ar5xxx.c ar5k_rfregs_gain_adjust(struct ath_hal *hal)
hal 1429 dev/ic/ar5xxx.c go = hal->ah_radio == AR5K_AR5111 ?
hal 1432 dev/ic/ar5xxx.c hal->ah_gain.g_step = &go->go_step[hal->ah_gain.g_step_idx];
hal 1434 dev/ic/ar5xxx.c if (hal->ah_gain.g_current >= hal->ah_gain.g_high) {
hal 1435 dev/ic/ar5xxx.c if (hal->ah_gain.g_step_idx == 0)
hal 1437 dev/ic/ar5xxx.c for (hal->ah_gain.g_target = hal->ah_gain.g_current;
hal 1438 dev/ic/ar5xxx.c hal->ah_gain.g_target >= hal->ah_gain.g_high &&
hal 1439 dev/ic/ar5xxx.c hal->ah_gain.g_step_idx > 0;
hal 1440 dev/ic/ar5xxx.c hal->ah_gain.g_step =
hal 1441 dev/ic/ar5xxx.c &go->go_step[hal->ah_gain.g_step_idx]) {
hal 1442 dev/ic/ar5xxx.c hal->ah_gain.g_target -= 2 *
hal 1443 dev/ic/ar5xxx.c (go->go_step[--(hal->ah_gain.g_step_idx)].gos_gain -
hal 1444 dev/ic/ar5xxx.c hal->ah_gain.g_step->gos_gain);
hal 1451 dev/ic/ar5xxx.c if (hal->ah_gain.g_current <= hal->ah_gain.g_low) {
hal 1452 dev/ic/ar5xxx.c if (hal->ah_gain.g_step_idx == (go->go_steps_count - 1))
hal 1454 dev/ic/ar5xxx.c for (hal->ah_gain.g_target = hal->ah_gain.g_current;
hal 1455 dev/ic/ar5xxx.c hal->ah_gain.g_target <= hal->ah_gain.g_low &&
hal 1456 dev/ic/ar5xxx.c hal->ah_gain.g_step_idx < (go->go_steps_count - 1);
hal 1457 dev/ic/ar5xxx.c hal->ah_gain.g_step =
hal 1458 dev/ic/ar5xxx.c &go->go_step[hal->ah_gain.g_step_idx]) {
hal 1459 dev/ic/ar5xxx.c hal->ah_gain.g_target -= 2 *
hal 1460 dev/ic/ar5xxx.c (go->go_step[++(hal->ah_gain.g_step_idx)].gos_gain -
hal 1461 dev/ic/ar5xxx.c hal->ah_gain.g_step->gos_gain);
hal 1472 dev/ic/ar5xxx.c hal->ah_gain.g_step_idx,
hal 1473 dev/ic/ar5xxx.c hal->ah_gain.g_current,
hal 1474 dev/ic/ar5xxx.c hal->ah_gain.g_target);
hal 1481 dev/ic/ar5xxx.c ar5k_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode)
hal 1486 dev/ic/ar5xxx.c if (hal->ah_radio == AR5K_AR5111) {
hal 1487 dev/ic/ar5xxx.c hal->ah_rf_banks_size = sizeof(ar5111_rf);
hal 1489 dev/ic/ar5xxx.c } else if (hal->ah_radio == AR5K_AR5112) {
hal 1490 dev/ic/ar5xxx.c if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
hal 1491 dev/ic/ar5xxx.c hal->ah_rf_banks_size = sizeof(ar5112a_rf);
hal 1493 dev/ic/ar5xxx.c hal->ah_rf_banks_size = sizeof(ar5112_rf);
hal 1498 dev/ic/ar5xxx.c if (hal->ah_rf_banks == NULL) {
hal 1500 dev/ic/ar5xxx.c if ((hal->ah_rf_banks = malloc(hal->ah_rf_banks_size,
hal 1507 dev/ic/ar5xxx.c ret = (func)(hal, channel, mode);
hal 1510 dev/ic/ar5xxx.c hal->ah_rf_gain = HAL_RFGAIN_INACTIVE;
hal 1516 dev/ic/ar5xxx.c ar5k_ar5111_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode)
hal 1518 dev/ic/ar5xxx.c struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
hal 1526 dev/ic/ar5xxx.c rf = hal->ah_rf_banks;
hal 1538 dev/ic/ar5xxx.c hal->ah_offset[bank] = i;
hal 1551 dev/ic/ar5xxx.c if (!ar5k_rfregs_op(rf, hal->ah_offset[0],
hal 1555 dev/ic/ar5xxx.c if (!ar5k_rfregs_op(rf, hal->ah_offset[0],
hal 1568 dev/ic/ar5xxx.c if (!ar5k_rfregs_op(rf, hal->ah_offset[6],
hal 1572 dev/ic/ar5xxx.c if (!ar5k_rfregs_op(rf, hal->ah_offset[6],
hal 1577 dev/ic/ar5xxx.c if (!ar5k_rfregs_op(rf, hal->ah_offset[6],
hal 1581 dev/ic/ar5xxx.c if (!ar5k_rfregs_op(rf, hal->ah_offset[6],
hal 1585 dev/ic/ar5xxx.c if (!ar5k_rfregs_op(rf, hal->ah_offset[6],
hal 1589 dev/ic/ar5xxx.c if (!ar5k_rfregs_op(rf, hal->ah_offset[6],
hal 1593 dev/ic/ar5xxx.c if (!ar5k_rfregs_op(rf, hal->ah_offset[7],
hal 1597 dev/ic/ar5xxx.c if (!ar5k_rfregs_op(rf, hal->ah_offset[7],
hal 1611 dev/ic/ar5xxx.c ar5k_ar5112_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode)
hal 1613 dev/ic/ar5xxx.c struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
hal 1622 dev/ic/ar5xxx.c rf = hal->ah_rf_banks;
hal 1624 dev/ic/ar5xxx.c if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
hal 1642 dev/ic/ar5xxx.c hal->ah_offset[bank] = i;
hal 1655 dev/ic/ar5xxx.c if (!ar5k_rfregs_op(rf, hal->ah_offset[6],
hal 1659 dev/ic/ar5xxx.c if (!ar5k_rfregs_op(rf, hal->ah_offset[6],
hal 1670 dev/ic/ar5xxx.c if (!ar5k_rfregs_op(rf, hal->ah_offset[6],
hal 1674 dev/ic/ar5xxx.c if (!ar5k_rfregs_op(rf, hal->ah_offset[6],
hal 1680 dev/ic/ar5xxx.c ar5k_rfregs_op(rf, hal->ah_offset[6],
hal 1682 dev/ic/ar5xxx.c ar5k_rfregs_op(rf, hal->ah_offset[6],
hal 1686 dev/ic/ar5xxx.c if (!ar5k_rfregs_op(rf, hal->ah_offset[6],
hal 1690 dev/ic/ar5xxx.c if (!ar5k_rfregs_op(rf, hal->ah_offset[7],
hal 1702 dev/ic/ar5xxx.c ar5k_rfgain(struct ath_hal *hal, u_int phy, u_int freq)
hal 1735 dev/ic/ar5xxx.c ar5k_txpower_table(struct ath_hal *hal, HAL_CHANNEL *channel, int16_t max_power)
hal 1740 dev/ic/ar5xxx.c rates = hal->ah_txpower.txp_rates;
hal 1753 dev/ic/ar5xxx.c hal->ah_txpower.txp_min = rates[7];
hal 1754 dev/ic/ar5xxx.c hal->ah_txpower.txp_max = rates[0];
hal 1755 dev/ic/ar5xxx.c hal->ah_txpower.txp_ofdm = rates[0];
hal 1758 dev/ic/ar5xxx.c n = AR5K_ELEMENTS(hal->ah_txpower.txp_pcdac);
hal 1762 dev/ic/ar5xxx.c hal->ah_txpower.txp_pcdac[i] =
hal 839 dev/ic/ar5xxx.h (((hal->ah_txpower.txp_rates[(_r)]) & 0x3f) << (_v)) \
hal 843 dev/ic/ar5xxx.h (hal->ah_txpower.txp_rates[(_r)] & 0x3f) << (_v) \
hal 1363 dev/ic/ar5xxx.h bus_space_write_4(hal->ah_st, hal->ah_sh, (_reg), (_val))
hal 1365 dev/ic/ar5xxx.h bus_space_read_4(hal->ah_st, hal->ah_sh, (_reg))
hal 1382 dev/ic/ar5xxx.h AR5K_REG_WRITE(hal->ah_phy + ((_reg) << 2), _val)
hal 1384 dev/ic/ar5xxx.h AR5K_REG_READ(hal->ah_phy + ((_reg) << 2))
hal 1391 dev/ic/ar5xxx.h if ((ret = hal->ah_eeprom_read(hal, (_o), \
hal 1396 dev/ic/ar5xxx.h AR5K_EEPROM_READ(_o, hal->ah_capabilities.cap_eeprom._v); \