root/dev/ic/ar5xxx.c

DEFINITIONS

1. ath_hal_probe
2. ath_hal_attach
3. ath_hal_computetxtime
4. ar5k_check_channel
5. ath_hal_init_channels
6. ar5k_printver
7. ar5k_radar_alert
8. ar5k_regdomain_from_ieee
9. ar5k_regdomain_to_ieee
10. ar5k_get_regdomain
11. ar5k_bitswap
12. ar5k_htoclock
13. ar5k_clocktoh
14. ar5k_rt_copy
15. ar5k_register_timeout
16. ar5k_eeprom_bin2freq
17. ar5k_eeprom_read_ants
18. ar5k_eeprom_read_modes
19. ar5k_eeprom_init
20. ar5k_eeprom_read_mac
21. ar5k_eeprom_regulation_domain
22. ar5k_channel
23. ar5k_ar5110_chan2athchan
24. ar5k_ar5110_channel
25. ar5k_ar5111_chan2athchan
26. ar5k_ar5111_channel
27. ar5k_ar5112_channel
28. ar5k_rfregs_op
29. ar5k_rfregs_gainf_corr
30. ar5k_rfregs_gain_readback
31. ar5k_rfregs_gain_adjust
32. ar5k_rfregs
33. ar5k_ar5111_rfregs
34. ar5k_ar5112_rfregs
35. ar5k_rfgain
36. ar5k_txpower_table

    1 /*      $OpenBSD: ar5xxx.c,v 1.42 2007/06/26 10:53:01 tom Exp $ */
    3 /*
    4  * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org>
    5  *
    6  * Permission to use, copy, modify, and distribute this software for any
    7  * purpose with or without fee is hereby granted, provided that the above
    8  * copyright notice and this permission notice appear in all copies.
    9  *
   10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
   13  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
   14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
   15  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
   16  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
   17  */
   19 /*
   20  * HAL interface for Atheros Wireless LAN devices.
   21  * (Please have a look at ar5xxx.h for further information)
   22  */
   24 #include <dev/pci/pcidevs.h>
   25 #include <dev/ic/ar5xxx.h>
   27 extern ar5k_attach_t ar5k_ar5210_attach;
   28 extern ar5k_attach_t ar5k_ar5211_attach;
   29 extern ar5k_attach_t ar5k_ar5212_attach;
   31 static const struct {
u_int16_t       vendor;
u_int16_t       device;
ar5k_attach_t   (*attach);
   35 } ar5k_known_products[] = {
   36         /*
   37          * From pcidevs_data.h
   38          */
   39         { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5210,
ar5k_ar5210_attach },
   41         { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5210_AP,
ar5k_ar5210_attach },
   43         { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5210_DEFAULT,
ar5k_ar5210_attach },
   45         { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5211,
ar5k_ar5211_attach },
   47         { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5211_DEFAULT,
ar5k_ar5211_attach },
   49         { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5311,
ar5k_ar5211_attach },
   51         { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5211_FPGA11B,
ar5k_ar5211_attach },
   53         { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5211_LEGACY,
ar5k_ar5211_attach },
   55         { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212,
ar5k_ar5212_attach },
   57         { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_DEFAULT,
ar5k_ar5212_attach },
   59         { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_FPGA,
ar5k_ar5212_attach },
   61         { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_IBM,
ar5k_ar5212_attach },
   63         { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR2413,
ar5k_ar5212_attach },
   65         { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5413,
ar5k_ar5212_attach },
   67         { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5424,
ar5k_ar5212_attach },
   69         { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CRDAG675,
ar5k_ar5212_attach },
   71         { PCI_VENDOR_3COM2, PCI_PRODUCT_3COM2_3CRPAG175,
ar5k_ar5212_attach }
   73 };
   75 static const HAL_RATE_TABLE ar5k_rt_11a = AR5K_RATES_11A;
   76 static const HAL_RATE_TABLE ar5k_rt_11b = AR5K_RATES_11B;
   77 static const HAL_RATE_TABLE ar5k_rt_11g = AR5K_RATES_11G;
   78 static const HAL_RATE_TABLE ar5k_rt_turbo = AR5K_RATES_TURBO;
   79 static const HAL_RATE_TABLE ar5k_rt_xr = AR5K_RATES_XR;
   81 int              ar5k_eeprom_read_ants(struct ath_hal *, u_int32_t *, u_int);
   82 int              ar5k_eeprom_read_modes(struct ath_hal *, u_int32_t *, u_int);
u_int16_t        ar5k_eeprom_bin2freq(struct ath_hal *, u_int16_t, u_int);
HAL_BOOL         ar5k_ar5110_channel(struct ath_hal *, HAL_CHANNEL *);
u_int32_t        ar5k_ar5110_chan2athchan(HAL_CHANNEL *);
HAL_BOOL         ar5k_ar5111_channel(struct ath_hal *, HAL_CHANNEL *);
HAL_BOOL         ar5k_ar5111_chan2athchan(u_int, struct ar5k_athchan_2ghz *);
HAL_BOOL         ar5k_ar5112_channel(struct ath_hal *, HAL_CHANNEL *);
HAL_BOOL         ar5k_check_channel(struct ath_hal *, u_int16_t, u_int flags);
HAL_BOOL         ar5k_ar5111_rfregs(struct ath_hal *, HAL_CHANNEL *, u_int);
HAL_BOOL         ar5k_ar5112_rfregs(struct ath_hal *, HAL_CHANNEL *, u_int);
u_int            ar5k_rfregs_op(u_int32_t *, u_int32_t, u_int32_t, u_int32_t,
u_int32_t, u_int32_t, HAL_BOOL);
   97 /*
   98  * Supported channels
   99  */
  100 static const struct
ieee80211_regchannel ar5k_5ghz_channels[] = IEEE80211_CHANNELS_5GHZ;
  102 static const struct
ieee80211_regchannel ar5k_2ghz_channels[] = IEEE80211_CHANNELS_2GHZ;
  105 /*
  106  * Initial gain optimization values
  107  */
  108 static const struct ar5k_gain_opt ar5111_gain_opt = AR5K_AR5111_GAIN_OPT;
  109 static const struct ar5k_gain_opt ar5112_gain_opt = AR5K_AR5112_GAIN_OPT;
  111 /*
  112  * Initial register for the radio chipsets
  113  */
  114 static const struct ar5k_ini_rf ar5111_rf[] = AR5K_AR5111_INI_RF;
  115 static const struct ar5k_ini_rf ar5112_rf[] = AR5K_AR5112_INI_RF;
  116 static const struct ar5k_ini_rf ar5112a_rf[] = AR5K_AR5112A_INI_RF;
  117 static const struct ar5k_ini_rfgain ar5k_rfg[] = AR5K_INI_RFGAIN;
  119 /*
  120  * Enable to overwrite the country code (use "00" for debug)
  121  */
  122 #if 0
  123 #define COUNTRYCODE "00"
  124 #endif
  126 /*
  127  * Perform a lookup if the device is supported by the HAL
  128  */
  129 const char *
ath_hal_probe(u_int16_t vendor, u_int16_t device)
  131 {
  132         int i;
  134         /*
  135          * Perform a linear search on the table of supported devices
  136          */
  137         for (i = 0; i < AR5K_ELEMENTS(ar5k_known_products); i++) {
  138                 if (vendor == ar5k_known_products[i].vendor &&
device == ar5k_known_products[i].device)
  140                         return ("");
  141         }
  143         return (NULL);
  144 }
  146 /*
  147  * Fills in the HAL structure and initialises the device
  148  */
  149 struct ath_hal *
ath_hal_attach(u_int16_t device, void *arg, bus_space_tag_t st,
bus_space_handle_t sh, u_int is_64bit, int *status)
  152 {
  153         struct ath_softc *sc = (struct ath_softc *)arg;
  154         struct ath_hal *hal = NULL;
ar5k_attach_t *attach = NULL;
u_int8_t mac[IEEE80211_ADDR_LEN];
  157         int i;
  159         *status = EINVAL;
  161         /*
  162          * Call the chipset-dependent attach routine by device id
  163          */
  164         for (i = 0; i < AR5K_ELEMENTS(ar5k_known_products); i++) {
  165                 if (device == ar5k_known_products[i].device &&
ar5k_known_products[i].attach != NULL)
attach = ar5k_known_products[i].attach;
  168         }
  170         if (attach == NULL) {
  171                 *status = ENXIO;
AR5K_PRINTF("device not supported: 0x%04x\n", device);
  173                 return (NULL);
  174         }
  176         if ((hal = malloc(sizeof(struct ath_hal),
M_DEVBUF, M_NOWAIT)) == NULL) {
  178                 *status = ENOMEM;
AR5K_PRINT("out of memory\n");
  180                 return (NULL);
  181         }
bzero(hal, sizeof(struct ath_hal));
hal->ah_sc = sc;
hal->ah_st = st;
hal->ah_sh = sh;
hal->ah_device = device;
hal->ah_sub_vendor = 0; /* XXX unknown?! */
  191         /*
  192          * HAL information
  193          */
hal->ah_abi = HAL_ABI_VERSION;
hal->ah_op_mode = HAL_M_STA;
hal->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
hal->ah_turbo = AH_FALSE;
hal->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
hal->ah_imr = 0;
hal->ah_atim_window = 0;
hal->ah_aifs = AR5K_TUNE_AIFS;
hal->ah_cw_min = AR5K_TUNE_CWMIN;
hal->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
hal->ah_software_retry = AH_FALSE;
hal->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY;
  207         switch (device) {
  208         case PCI_PRODUCT_ATHEROS_AR2413:
  209         case PCI_PRODUCT_ATHEROS_AR5413:
  210         case PCI_PRODUCT_ATHEROS_AR5424:
  211                 /*
  212                  * Known single chip solutions
  213                  */
hal->ah_single_chip = AH_TRUE;
  215                 break;
  216         case PCI_PRODUCT_ATHEROS_AR5212_IBM:
  217                 /*
  218                  * IBM ThinkPads use the same device ID for different
  219                  * chipset versions. Ugh.
  220                  */
  221                 if (is_64bit) {
  222                         /*
  223                          * PCI Express "Mini Card" interface based on the
  224                          * AR5424 chipset
  225                          */
hal->ah_single_chip = AH_TRUE;
  227                 } else {
  228                         /* Classic Mini PCI interface based on AR5212 */
hal->ah_single_chip = AH_FALSE;
  230                 }
  231                 break;
  232         default:
  233                 /*
  234                  * Multi chip solutions
  235                  */
hal->ah_single_chip = AH_FALSE;
  237                 break;
  238         }
  240         if ((attach)(device, hal, st, sh, status) == NULL)
  241                 goto failed;
  243 #ifdef AR5K_DEBUG
hal->ah_dump_state(hal);
  245 #endif
  247         /*
  248          * Get card capabilities, values, ...
  249          */
  251         if (ar5k_eeprom_init(hal) != 0) {
AR5K_PRINT("unable to init EEPROM\n");
  253                 goto failed;
  254         }
  256         /* Get misc capabilities */
  257         if (hal->ah_get_capabilities(hal) != AH_TRUE) {
AR5K_PRINTF("unable to get device capabilities: 0x%04x\n",
device);
  260                 goto failed;
  261         }
  263         /* Get MAC address */
  264         if ((*status = ar5k_eeprom_read_mac(hal, mac)) != 0) {
AR5K_PRINTF("unable to read address from EEPROM: 0x%04x\n",
device);
  267                 goto failed;
  268         }
hal->ah_set_lladdr(hal, mac);
  272         /* Get rate tables */
  273         if (hal->ah_capabilities.cap_mode & HAL_MODE_11A)
ar5k_rt_copy(&hal->ah_rt_11a, &ar5k_rt_11a);
  275         if (hal->ah_capabilities.cap_mode & HAL_MODE_11B)
ar5k_rt_copy(&hal->ah_rt_11b, &ar5k_rt_11b);
  277         if (hal->ah_capabilities.cap_mode & HAL_MODE_11G)
ar5k_rt_copy(&hal->ah_rt_11g, &ar5k_rt_11g);
  279         if (hal->ah_capabilities.cap_mode & HAL_MODE_TURBO)
ar5k_rt_copy(&hal->ah_rt_turbo, &ar5k_rt_turbo);
  281         if (hal->ah_capabilities.cap_mode & HAL_MODE_XR)
ar5k_rt_copy(&hal->ah_rt_xr, &ar5k_rt_xr);
  284         /* Initialize the gain optimization values */
  285         if (hal->ah_radio == AR5K_AR5111) {
hal->ah_gain.g_step_idx = ar5111_gain_opt.go_default;
hal->ah_gain.g_step =
  288                     &ar5111_gain_opt.go_step[hal->ah_gain.g_step_idx];
hal->ah_gain.g_low = 20;
hal->ah_gain.g_high = 35;
hal->ah_gain.g_active = 1;
  292         } else if (hal->ah_radio == AR5K_AR5112) {
hal->ah_gain.g_step_idx = ar5112_gain_opt.go_default;
hal->ah_gain.g_step =
  295                     &ar5111_gain_opt.go_step[hal->ah_gain.g_step_idx];
hal->ah_gain.g_low = 20;
hal->ah_gain.g_high = 85;
hal->ah_gain.g_active = 1;
  299         }
  301         *status = HAL_OK;
  303         return (hal);
failed:
free(hal, M_DEVBUF);
  307         return (NULL);
  308 }
u_int16_t
ath_hal_computetxtime(struct ath_hal *hal, const HAL_RATE_TABLE *rates,
u_int32_t frame_length, u_int16_t rate_index, HAL_BOOL short_preamble)
  313 {
  314         const HAL_RATE *rate;
u_int32_t value;
AR5K_ASSERT_ENTRY(rate_index, rates->rateCount);
  319         /*
  320          * Get rate by index
  321          */
rate = &rates->info[rate_index];
  324         /*
  325          * Calculate the transmission time by operation (PHY) mode
  326          */
  327         switch (rate->phy) {
  328         case IEEE80211_T_CCK:
  329                 /*
  330                  * CCK / DS mode (802.11b)
  331                  */
value = AR5K_CCK_TX_TIME(rate->rateKbps, frame_length,
  333                     (short_preamble && rate->shortPreamble));
  334                 break;
  336         case IEEE80211_T_OFDM:
  337                 /*
  338                  * Orthogonal Frequency Division Multiplexing
  339                  */
  340                 if (AR5K_OFDM_NUM_BITS_PER_SYM(rate->rateKbps) == 0)
  341                         return (0);
value = AR5K_OFDM_TX_TIME(rate->rateKbps, frame_length);
  343                 break;
  345         case IEEE80211_T_TURBO:
  346                 /*
  347                  * Orthogonal Frequency Division Multiplexing
  348                  * Atheros "Turbo Mode" (doubled rates)
  349                  */
  350                 if (AR5K_TURBO_NUM_BITS_PER_SYM(rate->rateKbps) == 0)
  351                         return (0);
value = AR5K_TURBO_TX_TIME(rate->rateKbps, frame_length);
  353                 break;
  355         case IEEE80211_T_XR:
  356                 /*
  357                  * Orthogonal Frequency Division Multiplexing
  358                  * Atheros "eXtended Range" (XR)
  359                  */
  360                 if (AR5K_XR_NUM_BITS_PER_SYM(rate->rateKbps) == 0)
  361                         return (0);
value = AR5K_XR_TX_TIME(rate->rateKbps, frame_length);
  363                 break;
  365         default:
  366                 return (0);
  367         }
  369         return (value);
  370 }
HAL_BOOL
ar5k_check_channel(struct ath_hal *hal, u_int16_t freq, u_int flags)
  374 {
  375         /* Check if the channel is in our supported range */
  376         if (flags & IEEE80211_CHAN_2GHZ) {
  377                 if ((freq >= hal->ah_capabilities.cap_range.range_2ghz_min) &&
  378                     (freq <= hal->ah_capabilities.cap_range.range_2ghz_max))
  379                         return (AH_TRUE);
  380         } else if (flags & IEEE80211_CHAN_5GHZ) {
  381                 if ((freq >= hal->ah_capabilities.cap_range.range_5ghz_min) &&
  382                     (freq <= hal->ah_capabilities.cap_range.range_5ghz_max))
  383                         return (AH_TRUE);
  384         }
  386         return (AH_FALSE);
  387 }
HAL_BOOL
ath_hal_init_channels(struct ath_hal *hal, HAL_CHANNEL *channels,
u_int max_channels, u_int *channels_size, u_int16_t mode,
HAL_BOOL outdoor, HAL_BOOL extended)
  393 {
u_int i, c;
u_int32_t domain_current;
u_int domain_5ghz, domain_2ghz;
HAL_CHANNEL *all_channels;
  399         if ((all_channels = malloc(sizeof(HAL_CHANNEL) * max_channels,
M_TEMP, M_NOWAIT)) == NULL)
  401                 return (AH_FALSE);
i = c = 0;
domain_current = hal->ah_regdomain;
  406         /*
  407          * In debugging mode, enable all channels supported by the chipset
  408          */
  409         if (domain_current == DMN_DEFAULT) {
  410                 int min, max, freq;
u_int flags;
min = ieee80211_mhz2ieee(IEEE80211_CHANNELS_2GHZ_MIN,
IEEE80211_CHAN_2GHZ);
max = ieee80211_mhz2ieee(IEEE80211_CHANNELS_2GHZ_MAX,
IEEE80211_CHAN_2GHZ);
flags = CHANNEL_B | CHANNEL_TG |
  418                     (hal->ah_version == AR5K_AR5211 ?
CHANNEL_PUREG : CHANNEL_G);
debugchan:
  422                 for (i = min; i <= max && c < max_channels; i++) {
freq = ieee80211_ieee2mhz(i, flags);
  424                         if (ar5k_check_channel(hal, freq, flags) == AH_FALSE)
  425                                 continue;
all_channels[c].c_channel = freq;
all_channels[c++].c_channel_flags = flags;
  428                 }
  430                 if (flags & IEEE80211_CHAN_2GHZ) {
min = ieee80211_mhz2ieee(IEEE80211_CHANNELS_5GHZ_MIN,
IEEE80211_CHAN_5GHZ);
max = ieee80211_mhz2ieee(IEEE80211_CHANNELS_5GHZ_MAX,
IEEE80211_CHAN_5GHZ);
flags = CHANNEL_A | CHANNEL_T | CHANNEL_XR;
  436                         goto debugchan;
  437                 }
  439                 goto done;
  440         }
domain_5ghz = ieee80211_regdomain2flag(domain_current,
IEEE80211_CHANNELS_5GHZ_MIN);
domain_2ghz = ieee80211_regdomain2flag(domain_current,
IEEE80211_CHANNELS_2GHZ_MIN);
  447         /*
  448          * Create channel list based on chipset capabilities, regulation domain
  449          * and mode. 5GHz...
  450          */
  451         for (i = 0; (hal->ah_capabilities.cap_range.range_5ghz_max > 0) &&
  452                  (i < AR5K_ELEMENTS(ar5k_5ghz_channels)) &&
  453                  (c < max_channels); i++) {
  454                 /* Check if channel is supported by the chipset */
  455                 if (ar5k_check_channel(hal,
ar5k_5ghz_channels[i].rc_channel,
IEEE80211_CHAN_5GHZ) == AH_FALSE)
  458                         continue;
  460                 /* Match regulation domain */
  461                 if ((IEEE80211_DMN(ar5k_5ghz_channels[i].rc_domain) &
IEEE80211_DMN(domain_5ghz)) == 0)
  463                         continue;
  465                 /* Match modes */
  466                 if (ar5k_5ghz_channels[i].rc_mode & IEEE80211_CHAN_TURBO) {
all_channels[c].c_channel_flags = CHANNEL_T;
  468                 } else if (ar5k_5ghz_channels[i].rc_mode &
IEEE80211_CHAN_OFDM) {
all_channels[c].c_channel_flags = CHANNEL_A;
  471                 } else
  472                         continue;
  474                 /* Write channel and increment counter */
all_channels[c++].channel = ar5k_5ghz_channels[i].rc_channel;
  476         }
  478         /*
  479          * ...and 2GHz.
  480          */
  481         for (i = 0; (hal->ah_capabilities.cap_range.range_2ghz_max > 0) &&
  482                  (i < AR5K_ELEMENTS(ar5k_2ghz_channels)) &&
  483                  (c < max_channels); i++) {
  484                 /* Check if channel is supported by the chipset */
  485                 if (ar5k_check_channel(hal,
ar5k_2ghz_channels[i].rc_channel,
IEEE80211_CHAN_2GHZ) == AH_FALSE)
  488                         continue;
  490                 /* Match regulation domain */
  491                 if ((IEEE80211_DMN(ar5k_2ghz_channels[i].rc_domain) &
IEEE80211_DMN(domain_2ghz)) == 0)
  493                         continue;
  495                 /* Match modes */
  496                 if ((hal->ah_capabilities.cap_mode & HAL_MODE_11B) &&
  497                     (ar5k_2ghz_channels[i].rc_mode & IEEE80211_CHAN_CCK))
all_channels[c].c_channel_flags = CHANNEL_B;
  500                 if ((hal->ah_capabilities.cap_mode & HAL_MODE_11G) &&
  501                     (ar5k_2ghz_channels[i].rc_mode & IEEE80211_CHAN_OFDM)) {
all_channels[c].c_channel_flags |=
hal->ah_version == AR5K_AR5211 ?
CHANNEL_PUREG : CHANNEL_G;
  505                         if (ar5k_2ghz_channels[i].rc_mode &
IEEE80211_CHAN_TURBO)
all_channels[c].c_channel_flags |= CHANNEL_TG;
  508                 }
  510                 /* Write channel and increment counter */
all_channels[c++].channel = ar5k_2ghz_channels[i].rc_channel;
  512         }
done:
bcopy(all_channels, channels, sizeof(HAL_CHANNEL) * max_channels);
  516         *channels_size = c;
free(all_channels, M_TEMP);
  518         return (AH_TRUE);
  519 }
  521 /*
  522  * Common internal functions
  523  */
  525 const char *
ar5k_printver(enum ar5k_srev_type type, u_int32_t val)
  527 {
  528         struct ar5k_srev_name names[] = AR5K_SREV_NAME;
  529         const char *name = "xxxx";
  530         int i;
  532         for (i = 0; i < AR5K_ELEMENTS(names); i++) {
  533                 if (type == AR5K_VERSION_DEV) {
  534                         if (names[i].sr_type == type &&
names[i].sr_val == val) {
name = names[i].sr_name;
  537                                 break;
  538                         }
  539                         continue;
  540                 }
  541                 if (names[i].sr_type != type ||
names[i].sr_val == AR5K_SREV_UNKNOWN)
  543                         continue;
  544                 if ((val & 0xff) < names[i + 1].sr_val) {
name = names[i].sr_name;
  546                         break;
  547                 }
  548         }
  550         return (name);
  551 }
  553 void
ar5k_radar_alert(struct ath_hal *hal)
  555 {
  556         /*
  557          * Limit ~1/s
  558          */
  559         if (hal->ah_radar.r_last_channel.channel ==
hal->ah_current_channel.channel &&
tick < (hal->ah_radar.r_last_alert + hz))
  562                 return;
hal->ah_radar.r_last_channel.channel =
hal->ah_current_channel.channel;
hal->ah_radar.r_last_channel.c_channel_flags =
hal->ah_current_channel.c_channel_flags;
hal->ah_radar.r_last_alert = tick;
AR5K_PRINTF("Possible radar activity detected at %u MHz (tick %u)\n",
hal->ah_radar.r_last_alert, hal->ah_current_channel.channel);
  572 }
u_int16_t
ar5k_regdomain_from_ieee(ieee80211_regdomain_t ieee)
  576 {
u_int32_t regdomain = (u_int32_t)ieee;
  579         /*
  580          * Use the default regulation domain if the value is empty
  581          * or not supported by the net80211 regulation code.
  582          */
  583         if (ieee80211_regdomain2flag(regdomain,
IEEE80211_CHANNELS_5GHZ_MIN) == DMN_DEBUG)
  585                 return ((u_int16_t)AR5K_TUNE_REGDOMAIN);
  587         /* It is supported, just return the value */
  588         return (regdomain);
  589 }
ieee80211_regdomain_t
ar5k_regdomain_to_ieee(u_int16_t regdomain)
  593 {
ieee80211_regdomain_t ieee = (ieee80211_regdomain_t)regdomain;
  596         return (ieee);
  597 }
u_int16_t
ar5k_get_regdomain(struct ath_hal *hal)
  601 {
u_int16_t regdomain;
ieee80211_regdomain_t ieee_regdomain;
  604 #ifdef COUNTRYCODE
u_int16_t code;
  606 #endif
ar5k_eeprom_regulation_domain(hal, AH_FALSE, &ieee_regdomain);
hal->ah_capabilities.cap_regdomain.reg_hw = ieee_regdomain;
  611 #ifdef COUNTRYCODE
  612         /*
  613          * Get the regulation domain by country code. This will ignore
  614          * the settings found in the EEPROM.
  615          */
code = ieee80211_name2countrycode(COUNTRYCODE);
ieee_regdomain = ieee80211_countrycode2regdomain(code);
  618 #endif
regdomain = ar5k_regdomain_from_ieee(ieee_regdomain);
hal->ah_capabilities.cap_regdomain.reg_current = regdomain;
  623         return (regdomain);
  624 }
u_int32_t
ar5k_bitswap(u_int32_t val, u_int bits)
  628 {
  629         if (bits == 8) {
val = ((val & 0xF0) >>  4) | ((val & 0x0F) <<  4);
val = ((val & 0xCC) >>  2) | ((val & 0x33) <<  2);
val = ((val & 0xAA) >>  1) | ((val & 0x55) <<  1);
  634                 return val;
  635         } else {
u_int32_t retval = 0, bit, i;
  638                 for (i = 0; i < bits; i++) {
bit = (val >> i) & 1;
retval = (retval << 1) | bit;
  641                 }
  643                 return retval;
  644         }
  645 }
u_int
ar5k_htoclock(u_int usec, HAL_BOOL turbo)
  649 {
  650         return (turbo == AH_TRUE ? (usec * 80) : (usec * 40));
  651 }
u_int
ar5k_clocktoh(u_int clock, HAL_BOOL turbo)
  655 {
  656         return (turbo == AH_TRUE ? (clock / 80) : (clock / 40));
  657 }
  659 void
ar5k_rt_copy(HAL_RATE_TABLE *dst, const HAL_RATE_TABLE *src)
  661 {
bzero(dst, sizeof(HAL_RATE_TABLE));
dst->rateCount = src->rateCount;
bcopy(src->info, dst->info, sizeof(dst->info));
  665 }
HAL_BOOL
ar5k_register_timeout(struct ath_hal *hal, u_int32_t reg, u_int32_t flag,
u_int32_t val, HAL_BOOL is_set)
  670 {
  671         int i;
u_int32_t data;
  674         for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
data = AR5K_REG_READ(reg);
  676                 if ((is_set == AH_TRUE) && (data & flag))
  677                         break;
  678                 else if ((data & flag) == val)
  679                         break;
AR5K_DELAY(15);
  681         }
  683         if (i <= 0)
  684                 return (AH_FALSE);
  686         return (AH_TRUE);
  687 }
  689 /*
  690  * Common ar5xx EEPROM access functions
  691  */
u_int16_t
ar5k_eeprom_bin2freq(struct ath_hal *hal, u_int16_t bin, u_int mode)
  695 {
u_int16_t val;
  698         if (bin == AR5K_EEPROM_CHANNEL_DIS)
  699                 return (bin);
  701         if (mode == AR5K_EEPROM_MODE_11A) {
  702                 if (hal->ah_ee_version > AR5K_EEPROM_VERSION_3_2)
val = (5 * bin) + 4800;
  704                 else
val = bin > 62 ?
  706                             (10 * 62) + (5 * (bin - 62)) + 5100 :
  707                             (bin * 10) + 5100;
  708         } else {
  709                 if (hal->ah_ee_version > AR5K_EEPROM_VERSION_3_2)
val = bin + 2300;
  711                 else
val = bin + 2400;
  713         }
  715         return (val);
  716 }
  718 int
ar5k_eeprom_read_ants(struct ath_hal *hal, u_int32_t *offset, u_int mode)
  720 {
  721         struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
u_int32_t o = *offset;
u_int16_t val;
  724         int ret, i = 0;
AR5K_EEPROM_READ(o++, val);
ee->ee_switch_settling[mode]    = (val >> 8) & 0x7f;
ee->ee_ant_tx_rx[mode]          = (val >> 2) & 0x3f;
ee->ee_ant_control[mode][i]     = (val << 4) & 0x3f;
AR5K_EEPROM_READ(o++, val);
ee->ee_ant_control[mode][i++]   |= (val >> 12) & 0xf;
ee->ee_ant_control[mode][i++]   = (val >> 6) & 0x3f;
ee->ee_ant_control[mode][i++]   = val & 0x3f;
AR5K_EEPROM_READ(o++, val);
ee->ee_ant_control[mode][i++]   = (val >> 10) & 0x3f;
ee->ee_ant_control[mode][i++]   = (val >> 4) & 0x3f;
ee->ee_ant_control[mode][i]     = (val << 2) & 0x3f;
AR5K_EEPROM_READ(o++, val);
ee->ee_ant_control[mode][i++]   |= (val >> 14) & 0x3;
ee->ee_ant_control[mode][i++]   = (val >> 8) & 0x3f;
ee->ee_ant_control[mode][i++]   = (val >> 2) & 0x3f;
ee->ee_ant_control[mode][i]     = (val << 4) & 0x3f;
AR5K_EEPROM_READ(o++, val);
ee->ee_ant_control[mode][i++]   |= (val >> 12) & 0xf;
ee->ee_ant_control[mode][i++]   = (val >> 6) & 0x3f;
ee->ee_ant_control[mode][i++]   = val & 0x3f;
  752         /* Get antenna modes */
hal->ah_antenna[mode][0] =
  754             (ee->ee_ant_control[mode][0] << 4) | 0x1;
hal->ah_antenna[mode][HAL_ANT_FIXED_A] =
ee->ee_ant_control[mode][1] |
  757             (ee->ee_ant_control[mode][2] << 6) |
  758             (ee->ee_ant_control[mode][3] << 12) |
  759             (ee->ee_ant_control[mode][4] << 18) |
  760             (ee->ee_ant_control[mode][5] << 24);
hal->ah_antenna[mode][HAL_ANT_FIXED_B] =
ee->ee_ant_control[mode][6] |
  763             (ee->ee_ant_control[mode][7] << 6) |
  764             (ee->ee_ant_control[mode][8] << 12) |
  765             (ee->ee_ant_control[mode][9] << 18) |
  766             (ee->ee_ant_control[mode][10] << 24);
  768         /* return new offset */
  769         *offset = o;
  771         return (0);
  772 }
  774 int
ar5k_eeprom_read_modes(struct ath_hal *hal, u_int32_t *offset, u_int mode)
  776 {
  777         struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
u_int32_t o = *offset;
u_int16_t val;
  780         int ret;
AR5K_EEPROM_READ(o++, val);
ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff;
ee->ee_thr_62[mode]             = val & 0xff;
  786         if (hal->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
ee->ee_thr_62[mode] =
mode == AR5K_EEPROM_MODE_11A ? 15 : 28;
AR5K_EEPROM_READ(o++, val);
ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff;
ee->ee_tx_frm2xpa_enable[mode]  = val & 0xff;
AR5K_EEPROM_READ(o++, val);
ee->ee_pga_desired_size[mode]   = (val >> 8) & 0xff;
  797         if ((val & 0xff) & 0x80)
ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1);
  799         else
ee->ee_noise_floor_thr[mode] = val & 0xff;
  802         if (hal->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
ee->ee_noise_floor_thr[mode] =
mode == AR5K_EEPROM_MODE_11A ? -54 : -1;
AR5K_EEPROM_READ(o++, val);
ee->ee_xlna_gain[mode]          = (val >> 5) & 0xff;
ee->ee_x_gain[mode]             = (val >> 1) & 0xf;
ee->ee_xpd[mode]                = val & 0x1;
  811         if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0)
ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
  814         if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) {
AR5K_EEPROM_READ(o++, val);
ee->ee_false_detect[mode] = (val >> 6) & 0x7f;
  818                 if (mode == AR5K_EEPROM_MODE_11A)
ee->ee_xr_power[mode] = val & 0x3f;
  820                 else {
ee->ee_ob[mode][0] = val & 0x7;
ee->ee_db[mode][0] = (val >> 3) & 0x7;
  823                 }
  824         }
  826         if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_4) {
ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN;
ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA;
  829         } else {
ee->ee_i_gain[mode] = (val >> 13) & 0x7;
AR5K_EEPROM_READ(o++, val);
ee->ee_i_gain[mode] |= (val << 3) & 0x38;
  835                 if (mode == AR5K_EEPROM_MODE_11G)
ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff;
  837         }
  839         if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
mode == AR5K_EEPROM_MODE_11A) {
ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
  843         }
  845         if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_6 &&
mode == AR5K_EEPROM_MODE_11G)
ee->ee_scaled_cck_delta = (val >> 11) & 0x1f;
  849         /* return new offset */
  850         *offset = o;
  852         return (0);
  853 }
  855 int
ar5k_eeprom_init(struct ath_hal *hal)
  857 {
  858         struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
u_int32_t offset;
u_int16_t val;
  861         int ret, i;
u_int mode;
  864         /* Initial TX thermal adjustment values */
ee->ee_tx_clip = 4;
ee->ee_pwd_84 = ee->ee_pwd_90 = 1;
ee->ee_gain_select = 1;
  869         /*
  870          * Read values from EEPROM and store them in the capability structure
  871          */
AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic);
AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect);
AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain);
AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version);
AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header);
  878         /* Return if we have an old EEPROM */
  879         if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_0)
  880                 return (0);
  882 #ifdef notyet
  883         /*
  884          * Validate the checksum of the EEPROM date. There are some
  885          * devices with invalid EEPROMs.
  886          */
  887         for (cksum = 0, offset = 0; offset < AR5K_EEPROM_INFO_MAX; offset++) {
AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val);
cksum ^= val;
  890         }
  891         if (cksum != AR5K_EEPROM_INFO_CKSUM) {
AR5K_PRINTF("Invalid EEPROM checksum 0x%04x\n", cksum);
  893                 return (EINVAL);
  894         }
  895 #endif
AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(hal->ah_ee_version),
ee_ant_gain);
  900         if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0);
AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1);
  903         }
  905         if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_3) {
AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val);
ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7;
ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7;
AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val);
ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7;
ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
  913         }
  915         /*
  916          * Get conformance test limit values
  917          */
offset = AR5K_EEPROM_CTL(hal->ah_ee_version);
ee->ee_ctls = AR5K_EEPROM_N_CTLS(hal->ah_ee_version);
  921         for (i = 0; i < ee->ee_ctls; i++) {
AR5K_EEPROM_READ(offset++, val);
ee->ee_ctl[i] = (val >> 8) & 0xff;
ee->ee_ctl[i + 1] = val & 0xff;
  925         }
  927         /*
  928          * Get values for 802.11a (5GHz)
  929          */
mode = AR5K_EEPROM_MODE_11A;
ee->ee_turbo_max_power[mode] =
AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header);
offset = AR5K_EEPROM_MODES_11A(hal->ah_ee_version);
  937         if ((ret = ar5k_eeprom_read_ants(hal, &offset, mode)) != 0)
  938                 return (ret);
AR5K_EEPROM_READ(offset++, val);
ee->ee_adc_desired_size[mode]   = (int8_t)((val >> 8) & 0xff);
ee->ee_ob[mode][3]              = (val >> 5) & 0x7;
ee->ee_db[mode][3]              = (val >> 2) & 0x7;
ee->ee_ob[mode][2]              = (val << 1) & 0x7;
AR5K_EEPROM_READ(offset++, val);
ee->ee_ob[mode][2]              |= (val >> 15) & 0x1;
ee->ee_db[mode][2]              = (val >> 12) & 0x7;
ee->ee_ob[mode][1]              = (val >> 9) & 0x7;
ee->ee_db[mode][1]              = (val >> 6) & 0x7;
ee->ee_ob[mode][0]              = (val >> 3) & 0x7;
ee->ee_db[mode][0]              = val & 0x7;
  954         if ((ret = ar5k_eeprom_read_modes(hal, &offset, mode)) != 0)
  955                 return (ret);
  957         if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) {
AR5K_EEPROM_READ(offset++, val);
ee->ee_margin_tx_rx[mode] = val & 0x3f;
  960         }
  962         /*
  963          * Get values for 802.11b (2.4GHz)
  964          */
mode = AR5K_EEPROM_MODE_11B;
offset = AR5K_EEPROM_MODES_11B(hal->ah_ee_version);
  968         if ((ret = ar5k_eeprom_read_ants(hal, &offset, mode)) != 0)
  969                 return (ret);
AR5K_EEPROM_READ(offset++, val);
ee->ee_adc_desired_size[mode]   = (int8_t)((val >> 8) & 0xff);
ee->ee_ob[mode][1]              = (val >> 4) & 0x7;
ee->ee_db[mode][1]              = val & 0x7;
  976         if ((ret = ar5k_eeprom_read_modes(hal, &offset, mode)) != 0)
  977                 return (ret);
  979         if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
AR5K_EEPROM_READ(offset++, val);
ee->ee_cal_pier[mode][0] =
ar5k_eeprom_bin2freq(hal, val & 0xff, mode);
ee->ee_cal_pier[mode][1] =
ar5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode);
AR5K_EEPROM_READ(offset++, val);
ee->ee_cal_pier[mode][2] =
ar5k_eeprom_bin2freq(hal, val & 0xff, mode);
  989         }
  991         if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) {
ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
  993         }
  995         /*
  996          * Get values for 802.11g (2.4GHz)
  997          */
mode = AR5K_EEPROM_MODE_11G;
offset = AR5K_EEPROM_MODES_11G(hal->ah_ee_version);
 1001         if ((ret = ar5k_eeprom_read_ants(hal, &offset, mode)) != 0)
 1002                 return (ret);
AR5K_EEPROM_READ(offset++, val);
ee->ee_adc_desired_size[mode]   = (int8_t)((val >> 8) & 0xff);
ee->ee_ob[mode][1]              = (val >> 4) & 0x7;
ee->ee_db[mode][1]              = val & 0x7;
 1009         if ((ret = ar5k_eeprom_read_modes(hal, &offset, mode)) != 0)
 1010                 return (ret);
 1012         if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
AR5K_EEPROM_READ(offset++, val);
ee->ee_cal_pier[mode][0] =
ar5k_eeprom_bin2freq(hal, val & 0xff, mode);
ee->ee_cal_pier[mode][1] =
ar5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode);
AR5K_EEPROM_READ(offset++, val);
ee->ee_turbo_max_power[mode] = val & 0x7f;
ee->ee_xr_power[mode] = (val >> 7) & 0x3f;
AR5K_EEPROM_READ(offset++, val);
ee->ee_cal_pier[mode][2] =
ar5k_eeprom_bin2freq(hal, val & 0xff, mode);
 1027                 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) {
ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
 1029                 }
AR5K_EEPROM_READ(offset++, val);
ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
 1035                 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) {
AR5K_EEPROM_READ(offset++, val);
ee->ee_cck_ofdm_gain_delta = val & 0xff;
 1038                 }
 1039         }
 1041         /*
 1042          * Read 5GHz EEPROM channels
 1043          */
 1045         return (0);
 1046 }
 1048 int
ar5k_eeprom_read_mac(struct ath_hal *hal, u_int8_t *mac)
 1050 {
u_int32_t total, offset;
u_int16_t data;
 1053         int octet;
u_int8_t mac_d[IEEE80211_ADDR_LEN];
bzero(mac, IEEE80211_ADDR_LEN);
bzero(&mac_d, IEEE80211_ADDR_LEN);
 1059         if (hal->ah_eeprom_read(hal, 0x20, &data) != 0)
 1060                 return (EIO);
 1062         for (offset = 0x1f, octet = 0, total = 0;
offset >= 0x1d; offset--) {
 1064                 if (hal->ah_eeprom_read(hal, offset, &data) != 0)
 1065                         return (EIO);
total += data;
mac_d[octet + 1] = data & 0xff;
mac_d[octet] = data >> 8;
octet += 2;
 1071         }
bcopy(mac_d, mac, IEEE80211_ADDR_LEN);
 1075         if ((!total) || total == (3 * 0xffff))
 1076                 return (EINVAL);
 1078         return (0);
 1079 }
HAL_BOOL
ar5k_eeprom_regulation_domain(struct ath_hal *hal, HAL_BOOL write,
ieee80211_regdomain_t *regdomain)
 1084 {
u_int16_t ee_regdomain;
 1087         /* Read current value */
 1088         if (write != AH_TRUE) {
ee_regdomain = hal->ah_capabilities.cap_eeprom.ee_regdomain;
 1090                 *regdomain = ar5k_regdomain_to_ieee(ee_regdomain);
 1091                 return (AH_TRUE);
 1092         }
ee_regdomain = ar5k_regdomain_from_ieee(*regdomain);
 1096         /* Try to write a new value */
 1097         if (hal->ah_capabilities.cap_eeprom.ee_protect &
AR5K_EEPROM_PROTECT_WR_128_191)
 1099                 return (AH_FALSE);
 1100         if (hal->ah_eeprom_write(hal, AR5K_EEPROM_REG_DOMAIN,
ee_regdomain) != 0)
 1102                 return (AH_FALSE);
hal->ah_capabilities.cap_eeprom.ee_regdomain = ee_regdomain;
 1106         return (AH_TRUE);
 1107 }
 1109 /*
 1110  * PHY/RF access functions
 1111  */
HAL_BOOL
ar5k_channel(struct ath_hal *hal, HAL_CHANNEL *channel)
 1115 {
HAL_BOOL ret;
 1118         /*
 1119          * Check bounds supported by the PHY
 1120          * (don't care about regulation restrictions at this point)
 1121          */
 1122         if ((channel->channel < hal->ah_capabilities.cap_range.range_2ghz_min ||
channel->channel > hal->ah_capabilities.cap_range.range_2ghz_max) &&
 1124             (channel->channel < hal->ah_capabilities.cap_range.range_5ghz_min ||
channel->channel > hal->ah_capabilities.cap_range.range_5ghz_max)) {
AR5K_PRINTF("channel out of supported range (%u MHz)\n",
channel->channel);
 1128                 return (AH_FALSE);
 1129         }
 1131         /*
 1132          * Set the channel and wait
 1133          */
 1134         if (hal->ah_radio == AR5K_AR5110)
ret = ar5k_ar5110_channel(hal, channel);
 1136         else if (hal->ah_radio == AR5K_AR5111)
ret = ar5k_ar5111_channel(hal, channel);
 1138         else
ret = ar5k_ar5112_channel(hal, channel);
 1141         if (ret == AH_FALSE)
 1142                 return (ret);
hal->ah_current_channel.c_channel = channel->c_channel;
hal->ah_current_channel.c_channel_flags = channel->c_channel_flags;
hal->ah_turbo = channel->c_channel_flags == CHANNEL_T ?
AH_TRUE : AH_FALSE;
 1149         return (AH_TRUE);
 1150 }
u_int32_t
ar5k_ar5110_chan2athchan(HAL_CHANNEL *channel)
 1154 {
u_int32_t athchan;
 1157         /*
 1158          * Convert IEEE channel/MHz to an internal channel value used
 1159          * by the AR5210 chipset. This has not been verified with
 1160          * newer chipsets like the AR5212A who have a completely
 1161          * different RF/PHY part.
 1162          */
athchan = (ar5k_bitswap((ieee80211_mhz2ieee(channel->c_channel,
channel->c_channel_flags) - 24) / 2, 5) << 1) |
 1165             (1 << 6) | 0x1;
 1167         return (athchan);
 1168 }
HAL_BOOL
ar5k_ar5110_channel(struct ath_hal *hal, HAL_CHANNEL *channel)
 1172 {
u_int32_t data;
 1175         /*
 1176          * Set the channel and wait
 1177          */
data = ar5k_ar5110_chan2athchan(channel);
AR5K_PHY_WRITE(0x27, data);
AR5K_PHY_WRITE(0x30, 0);
AR5K_DELAY(1000);
 1183         return (AH_TRUE);
 1184 }
HAL_BOOL
ar5k_ar5111_chan2athchan(u_int ieee, struct ar5k_athchan_2ghz *athchan)
 1188 {
 1189         int channel;
 1191         /* Cast this value to catch negative channel numbers (>= -19) */ 
channel = (int)ieee;
 1194         /*
 1195          * Map 2GHz IEEE channel to 5GHz Atheros channel
 1196          */
 1197         if (channel <= 13) {
athchan->a2_athchan = 115 + channel;
athchan->a2_flags = 0x46;
 1200         } else if (channel == 14) {
athchan->a2_athchan = 124;
athchan->a2_flags = 0x44;
 1203         } else if (channel >= 15 && channel <= 26) {
athchan->a2_athchan = ((channel - 14) * 4) + 132;
athchan->a2_flags = 0x46;
 1206         } else
 1207                 return (AH_FALSE);
 1209         return (AH_TRUE);
 1210 }
HAL_BOOL
ar5k_ar5111_channel(struct ath_hal *hal, HAL_CHANNEL *channel)
 1214 {
u_int ieee_channel, ath_channel;
u_int32_t data0, data1, clock;
 1217         struct ar5k_athchan_2ghz ath_channel_2ghz;
 1219         /*
 1220          * Set the channel on the AR5111 radio
 1221          */
data0 = data1 = 0;
ath_channel = ieee_channel = ieee80211_mhz2ieee(channel->c_channel,
channel->c_channel_flags);
 1226         if (channel->c_channel_flags & IEEE80211_CHAN_2GHZ) {
 1227                 /* Map 2GHz channel to 5GHz Atheros channel ID */
 1228                 if (ar5k_ar5111_chan2athchan(ieee_channel,
 1229                         &ath_channel_2ghz) == AH_FALSE)
 1230                         return (AH_FALSE);
ath_channel = ath_channel_2ghz.a2_athchan;
data0 = ((ar5k_bitswap(ath_channel_2ghz.a2_flags, 8) & 0xff)
 1234                     << 5) | (1 << 4);
 1235         }
 1237         if (ath_channel < 145 || !(ath_channel & 1)) {
clock = 1;
data1 = ((ar5k_bitswap(ath_channel - 24, 8) & 0xff) << 2)
 1240                     | (clock << 1) | (1 << 10) | 1;
 1241         } else {
clock = 0;
data1 = ((ar5k_bitswap((ath_channel - 24) / 2, 8) & 0xff) << 2)
 1244                     | (clock << 1) | (1 << 10) | 1;
 1245         }
AR5K_PHY_WRITE(0x27, (data1 & 0xff) | ((data0 & 0xff) << 8));
AR5K_PHY_WRITE(0x34, ((data1 >> 8) & 0xff) | (data0 & 0xff00));
 1250         return (AH_TRUE);
 1251 }
HAL_BOOL
ar5k_ar5112_channel(struct ath_hal *hal, HAL_CHANNEL *channel)
 1255 {
u_int32_t data, data0, data1, data2;
u_int16_t c;
data = data0 = data1 = data2 = 0;
c = channel->c_channel;
 1262         /*
 1263          * Set the channel on the AR5112 or newer
 1264          */
 1265         if (c < 4800) {
 1266                 if (!((c - 2224) % 5)) {
data0 = ((2 * (c - 704)) - 3040) / 10;
data1 = 1;
 1269                 } else if (!((c - 2192) % 5)) {
data0 = ((2 * (c - 672)) - 3040) / 10;
data1 = 0;
 1272                 } else
 1273                         return (AH_FALSE);
data0 = ar5k_bitswap((data0 << 2) & 0xff, 8);
 1276         } else {
 1277                 if (!(c % 20) && c >= 5120) {
data0 = ar5k_bitswap(((c - 4800) / 20 << 2), 8);
data2 = ar5k_bitswap(3, 2);
 1280                 } else if (!(c % 10)) {
data0 = ar5k_bitswap(((c - 4800) / 10 << 1), 8);
data2 = ar5k_bitswap(2, 2);
 1283                 } else if (!(c % 5)) {
data0 = ar5k_bitswap((c - 4800) / 5, 8);
data2 = ar5k_bitswap(1, 2);
 1286                 } else
 1287                         return (AH_FALSE);
 1288         }
data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
AR5K_PHY_WRITE(0x27, data & 0xff);
AR5K_PHY_WRITE(0x36, (data >> 8) & 0x7f);
 1295         return (AH_TRUE);
 1296 }
u_int
ar5k_rfregs_op(u_int32_t *rf, u_int32_t offset, u_int32_t reg, u_int32_t bits,
u_int32_t first, u_int32_t col, HAL_BOOL set)
 1301 {
u_int32_t mask, entry, last, data, shift, position;
int32_t left;
 1304         int i;
 1306         if (rf == NULL) {
 1307                 /* should not happen */
 1308                 return (0);
 1309         }
 1311         if (!(col <= 3 && bits <= 32 && first + bits <= 319)) {
AR5K_PRINTF("invalid values at offset %u\n", offset);
 1313                 return (0);
 1314         }
entry = ((first - 1) / 8) + offset;
position = (first - 1) % 8;
 1319         if (set == AH_TRUE)
data = ar5k_bitswap(reg, bits);
 1322         for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) {
last = (position + left > 8) ? 8 : position + left;
mask = (((1 << last) - 1) ^ ((1 << position) - 1)) <<
 1325                     (col * 8);
 1327                 if (set == AH_TRUE) {
rf[entry] &= ~mask;
rf[entry] |= ((data << position) << (col * 8)) & mask;
data >>= (8 - position);
 1331                 } else {
data = (((rf[entry] & mask) >> (col * 8)) >>
position) << shift;
shift += last - position;
 1335                 }
left -= 8 - position;
 1338         }
data = set == AH_TRUE ? 1 : ar5k_bitswap(data, bits);
 1342         return (data);
 1343 }
u_int32_t
ar5k_rfregs_gainf_corr(struct ath_hal *hal)
 1347 {
u_int32_t mix, step;
u_int32_t *rf;
 1351         if (hal->ah_rf_banks == NULL)
 1352                 return (0);
rf = hal->ah_rf_banks;
hal->ah_gain.g_f_corr = 0;
 1357         if (ar5k_rfregs_op(rf, hal->ah_offset[7], 0, 1, 36, 0, AH_FALSE) != 1)
 1358                 return (0);
step = ar5k_rfregs_op(rf, hal->ah_offset[7], 0, 4, 32, 0, AH_FALSE);
mix = hal->ah_gain.g_step->gos_param[0];
 1363         switch (mix) {
 1364         case 3:
hal->ah_gain.g_f_corr = step * 2;
 1366                 break;
 1367         case 2:
hal->ah_gain.g_f_corr = (step - 5) * 2;
 1369                 break;
 1370         case 1:
hal->ah_gain.g_f_corr = step;
 1372                 break;
 1373         default:
hal->ah_gain.g_f_corr = 0;
 1375                 break;
 1376         }
 1378         return (hal->ah_gain.g_f_corr);
 1379 }
HAL_BOOL
ar5k_rfregs_gain_readback(struct ath_hal *hal)
 1383 {
u_int32_t step, mix, level[4];
u_int32_t *rf;
 1387         if (hal->ah_rf_banks == NULL)
 1388                 return (0);
rf = hal->ah_rf_banks;
 1392         if (hal->ah_radio == AR5K_AR5111) {
step = ar5k_rfregs_op(rf, hal->ah_offset[7],
 1394                     0, 6, 37, 0, AH_FALSE);
level[0] = 0;
level[1] = (step == 0x3f) ? 0x32 : step + 4;
level[2] = (step != 0x3f) ? 0x40 : level[0];
level[3] = level[2] + 0x32;
hal->ah_gain.g_high = level[3] -
 1401                     (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
hal->ah_gain.g_low = level[0] +
 1403                     (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
 1404         } else {
mix = ar5k_rfregs_op(rf, hal->ah_offset[7],
 1406                     0, 1, 36, 0, AH_FALSE);
level[0] = level[2] = 0;
 1409                 if (mix == 1) {
level[1] = level[3] = 83;
 1411                 } else {
level[1] = level[3] = 107;
hal->ah_gain.g_high = 55;
 1414                 }
 1415         }
 1417         return ((hal->ah_gain.g_current >= level[0] &&
hal->ah_gain.g_current <= level[1]) ||
 1419             (hal->ah_gain.g_current >= level[2] &&
hal->ah_gain.g_current <= level[3]));
 1421 }
int32_t
ar5k_rfregs_gain_adjust(struct ath_hal *hal)
 1425 {
 1426         int ret = 0;
 1427         const struct ar5k_gain_opt *go;
go = hal->ah_radio == AR5K_AR5111 ?
 1430             &ar5111_gain_opt : &ar5112_gain_opt;
hal->ah_gain.g_step = &go->go_step[hal->ah_gain.g_step_idx];
 1434         if (hal->ah_gain.g_current >= hal->ah_gain.g_high) {
 1435                 if (hal->ah_gain.g_step_idx == 0)
 1436                         return (-1);
 1437                 for (hal->ah_gain.g_target = hal->ah_gain.g_current;
hal->ah_gain.g_target >=  hal->ah_gain.g_high &&
hal->ah_gain.g_step_idx > 0;
hal->ah_gain.g_step =
 1441                     &go->go_step[hal->ah_gain.g_step_idx]) {
hal->ah_gain.g_target -= 2 *
 1443                             (go->go_step[--(hal->ah_gain.g_step_idx)].gos_gain -
hal->ah_gain.g_step->gos_gain);
 1445                 }
ret = 1;
 1448                 goto done;
 1449         }
 1451         if (hal->ah_gain.g_current <= hal->ah_gain.g_low) {
 1452                 if (hal->ah_gain.g_step_idx == (go->go_steps_count - 1))
 1453                         return (-2);
 1454                 for (hal->ah_gain.g_target = hal->ah_gain.g_current;
hal->ah_gain.g_target <=  hal->ah_gain.g_low &&
hal->ah_gain.g_step_idx < (go->go_steps_count - 1);
hal->ah_gain.g_step =
 1458                     &go->go_step[hal->ah_gain.g_step_idx]) {
hal->ah_gain.g_target -= 2 *
 1460                             (go->go_step[++(hal->ah_gain.g_step_idx)].gos_gain -
hal->ah_gain.g_step->gos_gain);
 1462                 }
ret = 2;
 1465                 goto done;
 1466         }
done:
 1469 #ifdef AR5K_DEBUG
AR5K_PRINTF("ret %d, gain step %u, current gain %u, target gain %u\n",
ret,
hal->ah_gain.g_step_idx,
hal->ah_gain.g_current,
hal->ah_gain.g_target);
 1475 #endif
 1477         return (ret);
 1478 }
HAL_BOOL
ar5k_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode)
 1482 {
ar5k_rfgain_t *func = NULL;
HAL_BOOL ret;
 1486         if (hal->ah_radio == AR5K_AR5111) {
hal->ah_rf_banks_size = sizeof(ar5111_rf);
func = ar5k_ar5111_rfregs;
 1489         } else if (hal->ah_radio == AR5K_AR5112) {
 1490                 if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
hal->ah_rf_banks_size = sizeof(ar5112a_rf);
 1492                 else
hal->ah_rf_banks_size = sizeof(ar5112_rf);
func = ar5k_ar5112_rfregs;
 1495         } else
 1496                 return (AH_FALSE);
 1498         if (hal->ah_rf_banks == NULL) {
 1499                 /* XXX do extra checks? */
 1500                 if ((hal->ah_rf_banks = malloc(hal->ah_rf_banks_size,
M_DEVBUF, M_NOWAIT)) == NULL) {
AR5K_PRINT("out of memory\n");
 1503                         return (AH_FALSE);
 1504                 }
 1505         }
ret = (func)(hal, channel, mode);
 1509         if (ret == AH_TRUE)
hal->ah_rf_gain = HAL_RFGAIN_INACTIVE;
 1512         return (ret);
 1513 }
HAL_BOOL
ar5k_ar5111_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode)
 1517 {
 1518         struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
 1519         const u_int rf_size = AR5K_ELEMENTS(ar5111_rf);
u_int32_t *rf;
 1521         int i, obdb = -1, bank = -1;
u_int32_t ee_mode;
AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX);
rf = hal->ah_rf_banks;
 1528         /* Copy values to modify them */
 1529         for (i = 0; i < rf_size; i++) {
 1530                 if (ar5111_rf[i].rf_bank >=
AR5K_AR5111_INI_RF_MAX_BANKS) {
AR5K_PRINT("invalid bank\n");
 1533                         return (AH_FALSE);
 1534                 }
 1536                 if (bank != ar5111_rf[i].rf_bank) {
bank = ar5111_rf[i].rf_bank;
hal->ah_offset[bank] = i;
 1539                 }
rf[i] = ar5111_rf[i].rf_value[mode];
 1542         }
 1544         if (channel->c_channel_flags & IEEE80211_CHAN_2GHZ) {
 1545                 if (channel->c_channel_flags & IEEE80211_CHAN_B)
ee_mode = AR5K_EEPROM_MODE_11B;
 1547                 else
ee_mode = AR5K_EEPROM_MODE_11G;
obdb = 0;
 1551                 if (!ar5k_rfregs_op(rf, hal->ah_offset[0],
ee->ee_ob[ee_mode][obdb], 3, 119, 0, AH_TRUE))
 1553                         return (AH_FALSE);
 1555                 if (!ar5k_rfregs_op(rf, hal->ah_offset[0],
ee->ee_ob[ee_mode][obdb], 3, 122, 0, AH_TRUE))
 1557                         return (AH_FALSE);
obdb = 1;
 1560         } else {
 1561                 /* For 11a, Turbo and XR */
ee_mode = AR5K_EEPROM_MODE_11A;
obdb = channel->c_channel >= 5725 ? 3 :
 1564                     (channel->c_channel >= 5500 ? 2 :
 1565                         (channel->c_channel >= 5260 ? 1 :
 1566                             (channel->c_channel > 4000 ? 0 : -1)));
 1568                 if (!ar5k_rfregs_op(rf, hal->ah_offset[6],
ee->ee_pwd_84, 1, 51, 3, AH_TRUE))
 1570                         return (AH_FALSE);
 1572                 if (!ar5k_rfregs_op(rf, hal->ah_offset[6],
ee->ee_pwd_90, 1, 45, 3, AH_TRUE))
 1574                         return (AH_FALSE);
 1575         }
 1577         if (!ar5k_rfregs_op(rf, hal->ah_offset[6],
 1578                 !ee->ee_xpd[ee_mode], 1, 95, 0, AH_TRUE))
 1579                 return (AH_FALSE);
 1581         if (!ar5k_rfregs_op(rf, hal->ah_offset[6],
ee->ee_x_gain[ee_mode], 4, 96, 0, AH_TRUE))
 1583                 return (AH_FALSE);
 1585         if (!ar5k_rfregs_op(rf, hal->ah_offset[6],
obdb >= 0 ? ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, AH_TRUE))
 1587                 return (AH_FALSE);
 1589         if (!ar5k_rfregs_op(rf, hal->ah_offset[6],
obdb >= 0 ? ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, AH_TRUE))
 1591                 return (AH_FALSE);
 1593         if (!ar5k_rfregs_op(rf, hal->ah_offset[7],
ee->ee_i_gain[ee_mode], 6, 29, 0, AH_TRUE))
 1595                 return (AH_FALSE);
 1597         if (!ar5k_rfregs_op(rf, hal->ah_offset[7],
ee->ee_xpd[ee_mode], 1, 4, 0, AH_TRUE))
 1599                 return (AH_FALSE);
 1601         /* Write RF values */
 1602         for (i = 0; i < rf_size; i++) {
AR5K_REG_WAIT(i);
AR5K_REG_WRITE(ar5111_rf[i].rf_register, rf[i]);
 1605         }
 1607         return (AH_TRUE);
 1608 }
HAL_BOOL
ar5k_ar5112_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode)
 1612 {
 1613         struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
u_int rf_size;
u_int32_t *rf;
 1616         int i, obdb = -1, bank = -1;
u_int32_t ee_mode;
 1618         const struct ar5k_ini_rf *rf_ini;
AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX);
rf = hal->ah_rf_banks;
 1624         if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
rf_ini = ar5112a_rf;
rf_size = AR5K_ELEMENTS(ar5112a_rf);
 1627         } else {
rf_ini = ar5112_rf;
rf_size = AR5K_ELEMENTS(ar5112_rf);
 1630         }
 1632         /* Copy values to modify them */
 1633         for (i = 0; i < rf_size; i++) {
 1634                 if (rf_ini[i].rf_bank >=
AR5K_AR5112_INI_RF_MAX_BANKS) {
AR5K_PRINT("invalid bank\n");
 1637                         return (AH_FALSE);
 1638                 }
 1640                 if (bank != rf_ini[i].rf_bank) {
bank = rf_ini[i].rf_bank;
hal->ah_offset[bank] = i;
 1643                 }
rf[i] = rf_ini[i].rf_value[mode];
 1646         }
 1648         if (channel->c_channel_flags & IEEE80211_CHAN_2GHZ) {
 1649                 if (channel->c_channel_flags & IEEE80211_CHAN_B)
ee_mode = AR5K_EEPROM_MODE_11B;
 1651                 else
ee_mode = AR5K_EEPROM_MODE_11G;
obdb = 0;
 1655                 if (!ar5k_rfregs_op(rf, hal->ah_offset[6],
ee->ee_ob[ee_mode][obdb], 3, 287, 0, AH_TRUE))
 1657                         return (AH_FALSE);
 1659                 if (!ar5k_rfregs_op(rf, hal->ah_offset[6],
ee->ee_ob[ee_mode][obdb], 3, 290, 0, AH_TRUE))
 1661                         return (AH_FALSE);
 1662         } else {
 1663                 /* For 11a, Turbo and XR */
ee_mode = AR5K_EEPROM_MODE_11A;
obdb = channel->c_channel >= 5725 ? 3 :
 1666                     (channel->c_channel >= 5500 ? 2 :
 1667                         (channel->c_channel >= 5260 ? 1 :
 1668                             (channel->c_channel > 4000 ? 0 : -1)));
 1670                 if (!ar5k_rfregs_op(rf, hal->ah_offset[6],
ee->ee_ob[ee_mode][obdb], 3, 279, 0, AH_TRUE))
 1672                         return (AH_FALSE);
 1674                 if (!ar5k_rfregs_op(rf, hal->ah_offset[6],
ee->ee_ob[ee_mode][obdb], 3, 282, 0, AH_TRUE))
 1676                         return (AH_FALSE);
 1677         }
 1679 #ifdef notyet
ar5k_rfregs_op(rf, hal->ah_offset[6],
ee->ee_x_gain[ee_mode], 2, 270, 0, AH_TRUE);
ar5k_rfregs_op(rf, hal->ah_offset[6],
ee->ee_x_gain[ee_mode], 2, 257, 0, AH_TRUE);
 1684 #endif
 1686         if (!ar5k_rfregs_op(rf, hal->ah_offset[6],
ee->ee_xpd[ee_mode], 1, 302, 0, AH_TRUE))
 1688                 return (AH_FALSE);
 1690         if (!ar5k_rfregs_op(rf, hal->ah_offset[7],
ee->ee_i_gain[ee_mode], 6, 14, 0, AH_TRUE))
 1692                 return (AH_FALSE);
 1694         /* Write RF values */
 1695         for (i = 0; i < rf_size; i++)
AR5K_REG_WRITE(ar5112_rf[i].rf_register, rf[i]);
 1698         return (AH_TRUE);
 1699 }
HAL_BOOL
ar5k_rfgain(struct ath_hal *hal, u_int phy, u_int freq)
 1703 {
 1704         int i;
 1706         switch (phy) {
 1707         case AR5K_INI_PHY_5111:
 1708         case AR5K_INI_PHY_5112:
 1709                 break;
 1710         default:
 1711                 return (AH_FALSE);
 1712         }
 1714         switch (freq) {
 1715         case AR5K_INI_RFGAIN_2GHZ:
 1716         case AR5K_INI_RFGAIN_5GHZ:
 1717                 break;
 1718         default:
 1719                 return (AH_FALSE);
 1720         }
 1722         for (i = 0; i < AR5K_ELEMENTS(ar5k_rfg); i++) {
AR5K_REG_WAIT(i);
AR5K_REG_WRITE((u_int32_t)ar5k_rfg[i].rfg_register,
ar5k_rfg[i].rfg_value[phy][freq]);
 1726         }
 1728         return (AH_TRUE);
 1729 }
 1731 /*
 1732  * Common TX power setup
 1733  */
 1734 void
ar5k_txpower_table(struct ath_hal *hal, HAL_CHANNEL *channel, int16_t max_power)
 1736 {
u_int16_t txpower, *rates;
 1738         int i, min, max, n;
rates = hal->ah_txpower.txp_rates;
txpower = AR5K_TUNE_DEFAULT_TXPOWER * 2;
 1743         if (max_power > txpower) {
txpower = max_power > AR5K_TUNE_MAX_TXPOWER ?
AR5K_TUNE_MAX_TXPOWER : max_power;
 1746         }
 1748         for (i = 0; i < AR5K_MAX_RATES; i++)
rates[i] = txpower;
 1751         /* XXX setup target powers by rate */
hal->ah_txpower.txp_min = rates[7];
hal->ah_txpower.txp_max = rates[0];
hal->ah_txpower.txp_ofdm = rates[0];
 1757         /* Calculate the power table */
n = AR5K_ELEMENTS(hal->ah_txpower.txp_pcdac);
min = AR5K_EEPROM_PCDAC_START;
max = AR5K_EEPROM_PCDAC_STOP;
 1761         for (i = 0; i < n; i += AR5K_EEPROM_PCDAC_STEP)
hal->ah_txpower.txp_pcdac[i] =
 1763 #ifdef notyet
min + ((i * (max - min)) / n);
 1765 #else
min;
 1767 #endif
 1768 }