ah_offset 1357 dev/ic/ar5xxx.c if (ar5k_rfregs_op(rf, hal->ah_offset[7], 0, 1, 36, 0, AH_FALSE) != 1) ah_offset 1360 dev/ic/ar5xxx.c step = ar5k_rfregs_op(rf, hal->ah_offset[7], 0, 4, 32, 0, AH_FALSE); ah_offset 1393 dev/ic/ar5xxx.c step = ar5k_rfregs_op(rf, hal->ah_offset[7], ah_offset 1405 dev/ic/ar5xxx.c mix = ar5k_rfregs_op(rf, hal->ah_offset[7], ah_offset 1538 dev/ic/ar5xxx.c hal->ah_offset[bank] = i; ah_offset 1551 dev/ic/ar5xxx.c if (!ar5k_rfregs_op(rf, hal->ah_offset[0], ah_offset 1555 dev/ic/ar5xxx.c if (!ar5k_rfregs_op(rf, hal->ah_offset[0], ah_offset 1568 dev/ic/ar5xxx.c if (!ar5k_rfregs_op(rf, hal->ah_offset[6], ah_offset 1572 dev/ic/ar5xxx.c if (!ar5k_rfregs_op(rf, hal->ah_offset[6], ah_offset 1577 dev/ic/ar5xxx.c if (!ar5k_rfregs_op(rf, hal->ah_offset[6], ah_offset 1581 dev/ic/ar5xxx.c if (!ar5k_rfregs_op(rf, hal->ah_offset[6], ah_offset 1585 dev/ic/ar5xxx.c if (!ar5k_rfregs_op(rf, hal->ah_offset[6], ah_offset 1589 dev/ic/ar5xxx.c if (!ar5k_rfregs_op(rf, hal->ah_offset[6], ah_offset 1593 dev/ic/ar5xxx.c if (!ar5k_rfregs_op(rf, hal->ah_offset[7], ah_offset 1597 dev/ic/ar5xxx.c if (!ar5k_rfregs_op(rf, hal->ah_offset[7], ah_offset 1642 dev/ic/ar5xxx.c hal->ah_offset[bank] = i; ah_offset 1655 dev/ic/ar5xxx.c if (!ar5k_rfregs_op(rf, hal->ah_offset[6], ah_offset 1659 dev/ic/ar5xxx.c if (!ar5k_rfregs_op(rf, hal->ah_offset[6], ah_offset 1670 dev/ic/ar5xxx.c if (!ar5k_rfregs_op(rf, hal->ah_offset[6], ah_offset 1674 dev/ic/ar5xxx.c if (!ar5k_rfregs_op(rf, hal->ah_offset[6], ah_offset 1680 dev/ic/ar5xxx.c ar5k_rfregs_op(rf, hal->ah_offset[6], ah_offset 1682 dev/ic/ar5xxx.c ar5k_rfregs_op(rf, hal->ah_offset[6], ah_offset 1686 dev/ic/ar5xxx.c if (!ar5k_rfregs_op(rf, hal->ah_offset[6], ah_offset 1690 dev/ic/ar5xxx.c if (!ar5k_rfregs_op(rf, hal->ah_offset[7], ah_offset 1162 dev/ic/ar5xxx.h u_int32_t ah_offset[AR5K_MAX_RF_BANKS];