tsf 1683 dev/ic/ar5210.c u_int64_t tsf = AR5K_REG_READ(AR5K_AR5210_TSF_U32); tsf 1684 dev/ic/ar5210.c return (AR5K_REG_READ(AR5K_AR5210_TSF_L32) | (tsf << 32)); tsf 2068 dev/ic/ar5210.c const HAL_BEACON_STATE *state, u_int32_t tsf, u_int32_t dtim_count, tsf 2093 dev/ic/ar5210.c (tsf + (next_cfp == 0 ? cfp_period : next_cfp)) << 3); tsf 1789 dev/ic/ar5211.c u_int64_t tsf = AR5K_REG_READ(AR5K_AR5211_TSF_U32); tsf 1791 dev/ic/ar5211.c return (AR5K_REG_READ(AR5K_AR5211_TSF_L32) | (tsf << 32)); tsf 2167 dev/ic/ar5211.c const HAL_BEACON_STATE *state, u_int32_t tsf, u_int32_t dtim_count, tsf 2192 dev/ic/ar5211.c (tsf + (next_cfp == 0 ? cfp_period : next_cfp)) << 3); tsf 2084 dev/ic/ar5212.c u_int64_t tsf = AR5K_REG_READ(AR5K_AR5212_TSF_U32); tsf 2086 dev/ic/ar5212.c return (AR5K_REG_READ(AR5K_AR5212_TSF_L32) | (tsf << 32)); tsf 2506 dev/ic/ar5212.c const HAL_BEACON_STATE *state, u_int32_t tsf, u_int32_t dtim_count, tsf 2533 dev/ic/ar5212.c (tsf + (next_cfp == 0 ? cfp_period : next_cfp)) << 3); tsf 1059 dev/ic/ar5xxx.h const HAL_BEACON_STATE *, u_int32_t tsf, u_int32_t dtimCount, \ tsf 983 dev/ic/ath.c u_int64_t tsf; tsf 986 dev/ic/ath.c tsf = ath_hal_get_tsf64(ah); tsf 988 dev/ic/ath.c tsf += 100; tsf 990 dev/ic/ath.c tstamp[0] = htole32(tsf & 0xffffffff); tsf 991 dev/ic/ath.c tstamp[1] = htole32(tsf >> 32); tsf 2125 dev/pci/if_wpi.c struct wpi_cmd_tsf tsf; tsf 2128 dev/pci/if_wpi.c memset(&tsf, 0, sizeof tsf); tsf 2129 dev/pci/if_wpi.c memcpy(&tsf.tstamp, ni->ni_tstamp, sizeof (uint64_t)); tsf 2130 dev/pci/if_wpi.c tsf.bintval = htole16(ni->ni_intval); tsf 2131 dev/pci/if_wpi.c tsf.lintval = htole16(10); tsf 2135 dev/pci/if_wpi.c mod = letoh64(tsf.tstamp) % val; tsf 2136 dev/pci/if_wpi.c tsf.binitval = htole32((uint32_t)(val - mod)); tsf 2139 dev/pci/if_wpi.c ni->ni_intval, letoh64(tsf.tstamp), (uint32_t)(val - mod))); tsf 2141 dev/pci/if_wpi.c if (wpi_cmd(sc, WPI_CMD_TSF, &tsf, sizeof tsf, 1) != 0) tsf 572 dev/pci/if_wpireg.h uint64_t tsf;