tx_status        1112 dev/ic/ar5210.c 	struct ar5k_ar5210_tx_status *tx_status;
tx_status        1116 dev/ic/ar5210.c 	tx_status = (struct ar5k_ar5210_tx_status*)&desc->ds_hw[0];
tx_status        1119 dev/ic/ar5210.c 	if ((tx_status->tx_status_1 & AR5K_AR5210_DESC_TX_STATUS1_DONE) == 0)
tx_status        1126 dev/ic/ar5210.c 	    AR5K_REG_MS(tx_status->tx_status_0,
tx_status        1129 dev/ic/ar5210.c 	    AR5K_REG_MS(tx_status->tx_status_0,
tx_status        1132 dev/ic/ar5210.c 	    AR5K_REG_MS(tx_status->tx_status_0,
tx_status        1135 dev/ic/ar5210.c 	    AR5K_REG_MS(tx_status->tx_status_1,
tx_status        1138 dev/ic/ar5210.c 	    AR5K_REG_MS(tx_status->tx_status_1,
tx_status        1146 dev/ic/ar5210.c 	if ((tx_status->tx_status_0 &
tx_status        1148 dev/ic/ar5210.c 		if (tx_status->tx_status_0 &
tx_status        1152 dev/ic/ar5210.c 		if (tx_status->tx_status_0 &
tx_status        1156 dev/ic/ar5210.c 		if (tx_status->tx_status_0 &
tx_status        1219 dev/ic/ar5211.c 	struct ar5k_ar5211_tx_status *tx_status;
tx_status        1223 dev/ic/ar5211.c 	tx_status = (struct ar5k_ar5211_tx_status*)&desc->ds_hw[0];
tx_status        1226 dev/ic/ar5211.c 	if ((tx_status->tx_status_1 & AR5K_AR5211_DESC_TX_STATUS1_DONE) == 0)
tx_status        1233 dev/ic/ar5211.c 	    AR5K_REG_MS(tx_status->tx_status_0,
tx_status        1236 dev/ic/ar5211.c 	    AR5K_REG_MS(tx_status->tx_status_0,
tx_status        1239 dev/ic/ar5211.c 	    AR5K_REG_MS(tx_status->tx_status_0,
tx_status        1242 dev/ic/ar5211.c 	    AR5K_REG_MS(tx_status->tx_status_1,
tx_status        1245 dev/ic/ar5211.c 	    AR5K_REG_MS(tx_status->tx_status_1,
tx_status        1253 dev/ic/ar5211.c 	if ((tx_status->tx_status_0 &
tx_status        1255 dev/ic/ar5211.c 		if (tx_status->tx_status_0 &
tx_status        1259 dev/ic/ar5211.c 		if (tx_status->tx_status_0 &
tx_status        1263 dev/ic/ar5211.c 		if (tx_status->tx_status_0 &
tx_status        1367 dev/ic/ar5212.c 	struct ar5k_ar5212_tx_status *tx_status;
tx_status        1370 dev/ic/ar5212.c 	tx_status = (struct ar5k_ar5212_tx_status*)&desc->ds_hw[2];
tx_status        1373 dev/ic/ar5212.c 	bzero(tx_status, sizeof(struct ar5k_ar5212_tx_status));
tx_status        1420 dev/ic/ar5212.c 	struct ar5k_ar5212_tx_status *tx_status;
tx_status        1424 dev/ic/ar5212.c 	tx_status = (struct ar5k_ar5212_tx_status*)&desc->ds_hw[2];
tx_status        1427 dev/ic/ar5212.c 	if ((tx_status->tx_status_1 & AR5K_AR5212_DESC_TX_STATUS1_DONE) == 0)
tx_status        1434 dev/ic/ar5212.c 	    AR5K_REG_MS(tx_status->tx_status_0,
tx_status        1437 dev/ic/ar5212.c 	    AR5K_REG_MS(tx_status->tx_status_0,
tx_status        1440 dev/ic/ar5212.c 	    AR5K_REG_MS(tx_status->tx_status_0,
tx_status        1443 dev/ic/ar5212.c 	    AR5K_REG_MS(tx_status->tx_status_1,
tx_status        1446 dev/ic/ar5212.c 	    AR5K_REG_MS(tx_status->tx_status_1,
tx_status        1448 dev/ic/ar5212.c 	desc->ds_us.tx.ts_antenna = (tx_status->tx_status_1 &
tx_status        1452 dev/ic/ar5212.c 	switch (AR5K_REG_MS(tx_status->tx_status_1,
tx_status        1484 dev/ic/ar5212.c 	if ((tx_status->tx_status_0 &
tx_status        1486 dev/ic/ar5212.c 		if (tx_status->tx_status_0 &
tx_status        1490 dev/ic/ar5212.c 		if (tx_status->tx_status_0 &
tx_status        1494 dev/ic/ar5212.c 		if (tx_status->tx_status_0 &
tx_status         739 dev/ic/smc91cxx.c 	u_int16_t packetno, tx_status, card_stats;
tx_status         837 dev/ic/smc91cxx.c 		tx_status = bus_space_read_2(bst, bsh, DATA_REG_W);
tx_status         839 dev/ic/smc91cxx.c 		if (tx_status & EPHSR_TX_SUC)
tx_status         845 dev/ic/smc91cxx.c 		if (tx_status & EPHSR_LATCOL)
tx_status         642 dev/isa/if_ex.c 	int tx_status;
tx_status         656 dev/isa/if_ex.c 		tx_status = ISA_GET_2(IO_PORT_REG);
tx_status         658 dev/isa/if_ex.c 		if (tx_status & TX_OK_bit)
tx_status         662 dev/isa/if_ex.c 		ifp->if_collisions += tx_status & No_Collisions_bits;
tx_status        2562 dev/pci/if_san_xilinx.c 	u_int32_t rx_status, tx_status;
tx_status        2572 dev/pci/if_san_xilinx.c 	sdla_bus_read_4(card->hw, XILINX_HDLC_TX_INTR_PENDING_REG, &tx_status);
tx_status        2581 dev/pci/if_san_xilinx.c 	tx_status &= card->u.xilinx.active_ch_map;
tx_status        2584 dev/pci/if_san_xilinx.c 	if (tx_status != 0) {
tx_status        2586 dev/pci/if_san_xilinx.c 			if (bit_test((u_int8_t *)&tx_status, i) &&
tx_status         640 dev/pcmcia/if_xe.c 	u_int16_t tx_status, recvcount = 0, tempint;
tx_status         667 dev/pcmcia/if_xe.c 	tx_status =
tx_status         732 dev/pcmcia/if_xe.c 	if ((tx_status & EXCESSIVE_COLL) && ifp->if_opackets > 0) {
tx_status         740 dev/pcmcia/if_xe.c 	if ((tx_status & TX_ABORT) && ifp->if_opackets > 0)