root/dev/pci/ahc_pci.c

DEFINITIONS

1. ahc_compose_id
2. ahc_find_pci_device
3. ahc_pci_probe
4. ahc_pci_attach
5. ahc_9005_subdevinfo_valid
6. ahc_ext_scbram_present
7. ahc_scbram_config
8. ahc_probe_ext_scbram
9. ahc_pci_test_register_access
10. ahc_pci_intr
11. ahc_pci_chip_init
12. ahc_aic785X_setup
13. ahc_aic7860_setup
14. ahc_apa1480_setup
15. ahc_aic7870_setup
16. ahc_aha394X_setup
17. ahc_aha398X_setup
18. ahc_aha494X_setup
19. ahc_aic7880_setup
20. ahc_aha2940Pro_setup
21. ahc_aha394XU_setup
22. ahc_aha398XU_setup
23. ahc_aic7890_setup
24. ahc_aic7892_setup
25. ahc_aic7895_setup
26. ahc_aic7896_setup
27. ahc_aic7899_setup
28. ahc_aha29160C_setup
29. ahc_raid_setup
30. ahc_aha394XX_setup
31. ahc_aha398XX_setup
32. ahc_aha494XX_setup

    1 /*      $OpenBSD: ahc_pci.c,v 1.51 2007/05/14 01:37:50 deraadt Exp $    */
    2 /*
    3  * Product specific probe and attach routines for:
    4  *      3940, 2940, aic7895, aic7890, aic7880,
    5  *      aic7870, aic7860 and aic7850 SCSI controllers
    6  *
    7  * Copyright (c) 1994-2001 Justin T. Gibbs.
    8  * Copyright (c) 2000-2001 Adaptec Inc.
    9  * All rights reserved.
   10  *
   11  * Redistribution and use in source and binary forms, with or without
   12  * modification, are permitted provided that the following conditions
   13  * are met:
   14  * 1. Redistributions of source code must retain the above copyright
   15  *    notice, this list of conditions, and the following disclaimer,
   16  *    without modification.
   17  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
   18  *    substantially similar to the "NO WARRANTY" disclaimer below
   19  *    ("Disclaimer") and any redistribution must be conditioned upon
   20  *    including a substantially similar Disclaimer requirement for further
   21  *    binary redistribution.
   22  * 3. Neither the names of the above-listed copyright holders nor the names
   23  *    of any contributors may be used to endorse or promote products derived
   24  *    from this software without specific prior written permission.
   25  *
   26  * Alternatively, this software may be distributed under the terms of the
   27  * GNU General Public License ("GPL") version 2 as published by the Free
   28  * Software Foundation.
   29  *
   30  * NO WARRANTY
   31  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
   32  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
   33  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
   34  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
   35  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   36  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   37  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   38  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
   39  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
   40  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   41  * POSSIBILITY OF SUCH DAMAGES.
   42  *
   43  * $Id: ahc_pci.c,v 1.51 2007/05/14 01:37:50 deraadt Exp $
   44  *
   45  * //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#57 $
   46  *
   47  * $FreeBSD: /repoman/r/ncvs/src/sys/dev/aic7xxx/aic7xxx_pci.c,v 1.22 2003/01/20 20:44:55 gibbs Exp $
   48  */
   49 /*
   50  * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003
   51  */
   53 #include <sys/cdefs.h>
   54 /* __KERNEL_RCSID(0, "$NetBSD: ahc_pci.c,v 1.43 2003/08/18 09:16:22 taca Exp $"); */
   56 #include <sys/param.h>
   57 #include <sys/systm.h>
   58 #include <sys/malloc.h>
   59 #include <sys/kernel.h>
   60 #include <sys/queue.h>
   61 #include <sys/device.h>
   62 #include <sys/reboot.h>
   64 #include <machine/bus.h>
   65 #include <machine/intr.h>
   67 #include <dev/pci/pcireg.h>
   68 #include <dev/pci/pcivar.h>
   70 #define AHC_PCI_IOADDR  PCI_MAPREG_START        /* I/O Address */
   71 #define AHC_PCI_MEMADDR (PCI_MAPREG_START + 4)  /* Mem I/O Address */
   73 #include <dev/ic/aic7xxx_openbsd.h>
   74 #include <dev/ic/aic7xxx_inline.h>
   76 #include <dev/ic/smc93cx6var.h>
   78 #ifndef __i386__
   79 #define AHC_ALLOW_MEMIO
   80 #endif
   82 static __inline uint64_t
ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
   84 {
uint64_t id;
id = subvendor
   88            | (subdevice << 16)
   89            | ((uint64_t)vendor << 32)
   90            | ((uint64_t)device << 48);
   92         return (id);
   93 }
   95 #define ID_ALL_MASK                     0xFFFFFFFFFFFFFFFFull
   96 #define ID_DEV_VENDOR_MASK              0xFFFFFFFF00000000ull
   97 #define ID_9005_GENERIC_MASK            0xFFF0FFFF00000000ull
   98 #define ID_9005_SISL_MASK               0x000FFFFF00000000ull
   99 #define ID_9005_SISL_ID                 0x0005900500000000ull
  100 #define ID_AIC7850                      0x5078900400000000ull
  101 #define ID_AHA_2902_04_10_15_20_30C     0x5078900478509004ull
  102 #define ID_AIC7855                      0x5578900400000000ull
  103 #define ID_AIC7859                      0x3860900400000000ull
  104 #define ID_AHA_2930CU                   0x3860900438699004ull
  105 #define ID_AIC7860                      0x6078900400000000ull
  106 #define ID_AIC7860C                     0x6078900478609004ull
  107 #define ID_AHA_1480A                    0x6075900400000000ull
  108 #define ID_AHA_2940AU_0                 0x6178900400000000ull
  109 #define ID_AHA_2940AU_1                 0x6178900478619004ull
  110 #define ID_AHA_2940AU_CN                0x2178900478219004ull
  111 #define ID_AHA_2930C_VAR                0x6038900438689004ull
  113 #define ID_AIC7870                      0x7078900400000000ull
  114 #define ID_AHA_2940                     0x7178900400000000ull
  115 #define ID_AHA_3940                     0x7278900400000000ull
  116 #define ID_AHA_398X                     0x7378900400000000ull
  117 #define ID_AHA_2944                     0x7478900400000000ull
  118 #define ID_AHA_3944                     0x7578900400000000ull
  119 #define ID_AHA_4944                     0x7678900400000000ull
  121 #define ID_AIC7880                      0x8078900400000000ull
  122 #define ID_AIC7880_B                    0x8078900478809004ull
  123 #define ID_AHA_2940U                    0x8178900400000000ull
  124 #define ID_AHA_3940U                    0x8278900400000000ull
  125 #define ID_AHA_2944U                    0x8478900400000000ull
  126 #define ID_AHA_3944U                    0x8578900400000000ull
  127 #define ID_AHA_398XU                    0x8378900400000000ull
  128 #define ID_AHA_4944U                    0x8678900400000000ull
  129 #define ID_AHA_2940UB                   0x8178900478819004ull
  130 #define ID_AHA_2930U                    0x8878900478889004ull
  131 #define ID_AHA_2940U_PRO                0x8778900478879004ull
  132 #define ID_AHA_2940U_CN                 0x0078900478009004ull
  134 #define ID_AIC7895                      0x7895900478959004ull
  135 #define ID_AIC7895_ARO                  0x7890900478939004ull
  136 #define ID_AIC7895_ARO_MASK             0xFFF0FFFFFFFFFFFFull
  137 #define ID_AHA_2940U_DUAL               0x7895900478919004ull
  138 #define ID_AHA_3940AU                   0x7895900478929004ull
  139 #define ID_AHA_3944AU                   0x7895900478949004ull
  141 #define ID_AIC7890                      0x001F9005000F9005ull
  142 #define ID_AIC7890_ARO                  0x00139005000F9005ull
  143 #define ID_AAA_131U2                    0x0013900500039005ull
  144 #define ID_AHA_2930U2                   0x0011900501819005ull
  145 #define ID_AHA_2940U2B                  0x00109005A1009005ull
  146 #define ID_AHA_2940U2_OEM               0x0010900521809005ull
  147 #define ID_AHA_2940U2                   0x00109005A1809005ull
  148 #define ID_AHA_2950U2B                  0x00109005E1009005ull
  150 #define ID_AIC7892                      0x008F9005FFFF9005ull
  151 #define ID_AIC7892_ARO                  0x00839005FFFF9005ull
  152 #define ID_AHA_2915LP                   0x0082900502109005ull
  153 #define ID_AHA_29160                    0x00809005E2A09005ull
  154 #define ID_AHA_29160_CPQ                0x00809005E2A00E11ull
  155 #define ID_AHA_29160N                   0x0080900562A09005ull
  156 #define ID_AHA_29160C                   0x0080900562209005ull
  157 #define ID_AHA_29160B                   0x00809005E2209005ull
  158 #define ID_AHA_19160B                   0x0081900562A19005ull
  160 #define ID_AIC7896                      0x005F9005FFFF9005ull
  161 #define ID_AIC7896_ARO                  0x00539005FFFF9005ull
  162 #define ID_AHA_3950U2B_0                0x00509005FFFF9005ull
  163 #define ID_AHA_3950U2B_1                0x00509005F5009005ull
  164 #define ID_AHA_3950U2D_0                0x00519005FFFF9005ull
  165 #define ID_AHA_3950U2D_1                0x00519005B5009005ull
  167 #define ID_AIC7899                      0x00CF9005FFFF9005ull
  168 #define ID_AIC7899_ARO                  0x00C39005FFFF9005ull
  169 #define ID_AHA_3960D                    0x00C09005F6209005ull
  170 #define ID_AHA_3960D_CPQ                0x00C09005F6200E11ull
  172 #define ID_AIC7810                      0x1078900400000000ull
  173 #define ID_AIC7815                      0x7815900400000000ull
  175 #define DEVID_9005_TYPE(id) ((id) & 0xF)
  176 #define         DEVID_9005_TYPE_HBA             0x0     /* Standard Card */
  177 #define         DEVID_9005_TYPE_AAA             0x3     /* RAID Card */
  178 #define         DEVID_9005_TYPE_SISL            0x5     /* Container ROMB */
  179 #define         DEVID_9005_TYPE_MB              0xF     /* On Motherboard */
  181 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
  182 #define         DEVID_9005_MAXRATE_U160         0x0
  183 #define         DEVID_9005_MAXRATE_ULTRA2       0x1
  184 #define         DEVID_9005_MAXRATE_ULTRA        0x2
  185 #define         DEVID_9005_MAXRATE_FAST         0x3
  187 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6)
  189 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8)
  190 #define         DEVID_9005_CLASS_SPI            0x0     /* Parallel SCSI */
  192 #define SUBID_9005_TYPE(id) ((id) & 0xF)
  193 #define         SUBID_9005_TYPE_MB              0xF     /* On Motherboard */
  194 #define         SUBID_9005_TYPE_CARD            0x0     /* Standard Card */
  195 #define         SUBID_9005_TYPE_LCCARD          0x1     /* Low Cost Card */
  196 #define         SUBID_9005_TYPE_RAID            0x3     /* Combined with Raid */
  198 #define SUBID_9005_TYPE_KNOWN(id)                       \
  199           ((((id) & 0xF) == SUBID_9005_TYPE_MB)         \
  200         || (((id) & 0xF) == SUBID_9005_TYPE_CARD)       \
  201         || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD)     \
  202         || (((id) & 0xF) == SUBID_9005_TYPE_RAID))
  204 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
  205 #define         SUBID_9005_MAXRATE_ULTRA2       0x0
  206 #define         SUBID_9005_MAXRATE_ULTRA        0x1
  207 #define         SUBID_9005_MAXRATE_U160         0x2
  208 #define         SUBID_9005_MAXRATE_RESERVED     0x3
  210 #define SUBID_9005_SEEPTYPE(id)                                         \
  211         ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB)                    \
  212          ? ((id) & 0xC0) >> 6                                           \
  213          : ((id) & 0x300) >> 8)
  214 #define         SUBID_9005_SEEPTYPE_NONE        0x0
  215 #define         SUBID_9005_SEEPTYPE_1K          0x1
  216 #define         SUBID_9005_SEEPTYPE_2K_4K       0x2
  217 #define         SUBID_9005_SEEPTYPE_RESERVED    0x3
  218 #define SUBID_9005_AUTOTERM(id)                                         \
  219         ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB)                    \
  220          ? (((id) & 0x400) >> 10) == 0                                  \
  221          : (((id) & 0x40) >> 6) == 0)
  223 #define SUBID_9005_NUMCHAN(id)                                          \
  224         ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB)                    \
  225          ? ((id) & 0x300) >> 8                                          \
  226          : ((id) & 0xC00) >> 10)
  228 #define SUBID_9005_LEGACYCONN(id)                                       \
  229         ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB)                    \
  230          ? 0                                                            \
  231          : ((id) & 0x80) >> 7)
  233 #define SUBID_9005_MFUNCENB(id)                                         \
  234         ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB)                    \
  235          ? ((id) & 0x800) >> 11                                         \
  236          : ((id) & 0x1000) >> 12)
  237 /*
  238  * Informational only. Should use chip register to be
  239  * certain, but may be use in identification strings.
  240  */
  241 #define SUBID_9005_CARD_SCSIWIDTH_MASK  0x2000
  242 #define SUBID_9005_CARD_PCIWIDTH_MASK   0x4000
  243 #define SUBID_9005_CARD_SEDIFF_MASK     0x8000
  245 static ahc_device_setup_t ahc_aic785X_setup;
  246 static ahc_device_setup_t ahc_aic7860_setup;
  247 static ahc_device_setup_t ahc_apa1480_setup;
  248 static ahc_device_setup_t ahc_aic7870_setup;
  249 static ahc_device_setup_t ahc_aha394X_setup;
  250 static ahc_device_setup_t ahc_aha494X_setup;
  251 static ahc_device_setup_t ahc_aha398X_setup;
  252 static ahc_device_setup_t ahc_aic7880_setup;
  253 static ahc_device_setup_t ahc_aha2940Pro_setup;
  254 static ahc_device_setup_t ahc_aha394XU_setup;
  255 static ahc_device_setup_t ahc_aha398XU_setup;
  256 static ahc_device_setup_t ahc_aic7890_setup;
  257 static ahc_device_setup_t ahc_aic7892_setup;
  258 static ahc_device_setup_t ahc_aic7895_setup;
  259 static ahc_device_setup_t ahc_aic7896_setup;
  260 static ahc_device_setup_t ahc_aic7899_setup;
  261 static ahc_device_setup_t ahc_aha29160C_setup;
  262 static ahc_device_setup_t ahc_raid_setup;
  263 static ahc_device_setup_t ahc_aha394XX_setup;
  264 static ahc_device_setup_t ahc_aha494XX_setup;
  265 static ahc_device_setup_t ahc_aha398XX_setup;
  267 struct ahc_pci_identity ahc_pci_ident_table [] =
  268 {
  269         /* aic7850 based controllers */
  270         {
ID_AHA_2902_04_10_15_20_30C,
ID_ALL_MASK,
ahc_aic785X_setup
  274         },
  275         /* aic7860 based controllers */
  276         {
ID_AHA_2930CU,
ID_ALL_MASK,
ahc_aic7860_setup
  280         },
  281         {
ID_AHA_1480A & ID_DEV_VENDOR_MASK,
ID_DEV_VENDOR_MASK,
ahc_apa1480_setup
  285         },
  286         {
ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK,
ID_DEV_VENDOR_MASK,
ahc_aic7860_setup
  290         },
  291         {
ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK,
ID_DEV_VENDOR_MASK,
ahc_aic7860_setup
  295         },
  296         {
ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK,
ID_DEV_VENDOR_MASK,
ahc_aic7860_setup
  300         },
  301         /* aic7870 based controllers */
  302         {
ID_AHA_2940,
ID_ALL_MASK,
ahc_aic7870_setup
  306         },
  307         {
ID_AHA_3940,
ID_ALL_MASK,
ahc_aha394X_setup
  311         },
  312         {
ID_AHA_398X,
ID_ALL_MASK,
ahc_aha398X_setup
  316         },
  317         {
ID_AHA_2944,
ID_ALL_MASK,
ahc_aic7870_setup
  321         },
  322         {
ID_AHA_3944,
ID_ALL_MASK,
ahc_aha394X_setup
  326         },
  327         {
ID_AHA_4944,
ID_ALL_MASK,
ahc_aha494X_setup
  331         },
  332         /* aic7880 based controllers */
  333         {
ID_AHA_2940U & ID_DEV_VENDOR_MASK,
ID_DEV_VENDOR_MASK,
ahc_aic7880_setup
  337         },
  338         {
ID_AHA_3940U & ID_DEV_VENDOR_MASK,
ID_DEV_VENDOR_MASK,
ahc_aha394XU_setup
  342         },
  343         {
ID_AHA_2944U & ID_DEV_VENDOR_MASK,
ID_DEV_VENDOR_MASK,
ahc_aic7880_setup
  347         },
  348         {
ID_AHA_3944U & ID_DEV_VENDOR_MASK,
ID_DEV_VENDOR_MASK,
ahc_aha394XU_setup
  352         },
  353         {
ID_AHA_398XU & ID_DEV_VENDOR_MASK,
ID_DEV_VENDOR_MASK,
ahc_aha398XU_setup
  357         },
  358         {
  359                 /*
  360                  * XXX Don't know the slot numbers
  361                  * so we can't identify channels
  362                  */
ID_AHA_4944U & ID_DEV_VENDOR_MASK,
ID_DEV_VENDOR_MASK,
ahc_aic7880_setup
  366         },
  367         {
ID_AHA_2930U & ID_DEV_VENDOR_MASK,
ID_DEV_VENDOR_MASK,
ahc_aic7880_setup
  371         },
  372         {
ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK,
ID_DEV_VENDOR_MASK,
ahc_aha2940Pro_setup
  376         },
  377         {
ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK,
ID_DEV_VENDOR_MASK,
ahc_aic7880_setup
  381         },
  382         /* Ignore all SISL (AAC on MB) based controllers. */
  383         {
ID_9005_SISL_ID,
ID_9005_SISL_MASK,
NULL
  387         },
  388         /* aic7890 based controllers */
  389         {
ID_AHA_2930U2,
ID_ALL_MASK,
ahc_aic7890_setup
  393         },
  394         {
ID_AHA_2940U2B,
ID_ALL_MASK,
ahc_aic7890_setup
  398         },
  399         {
ID_AHA_2940U2_OEM,
ID_ALL_MASK,
ahc_aic7890_setup
  403         },
  404         {
ID_AHA_2940U2,
ID_ALL_MASK,
ahc_aic7890_setup
  408         },
  409         {
ID_AHA_2950U2B,
ID_ALL_MASK,
ahc_aic7890_setup
  413         },
  414         {
ID_AIC7890_ARO,
ID_ALL_MASK,
ahc_aic7890_setup
  418         },
  419         {
ID_AAA_131U2,
ID_ALL_MASK,
ahc_aic7890_setup
  423         },
  424         /* aic7892 based controllers */
  425         {
ID_AHA_29160,
ID_ALL_MASK,
ahc_aic7892_setup
  429         },
  430         {
ID_AHA_29160_CPQ,
ID_ALL_MASK,
ahc_aic7892_setup
  434         },
  435         {
ID_AHA_29160N,
ID_ALL_MASK,
ahc_aic7892_setup
  439         },
  440         {
ID_AHA_29160C,
ID_ALL_MASK,
ahc_aha29160C_setup
  444         },
  445         {
ID_AHA_29160B,
ID_ALL_MASK,
ahc_aic7892_setup
  449         },
  450         {
ID_AHA_19160B,
ID_ALL_MASK,
ahc_aic7892_setup
  454         },
  455         {
ID_AIC7892_ARO,
ID_ALL_MASK,
ahc_aic7892_setup
  459         },
  460         {
ID_AHA_2915LP,
ID_ALL_MASK,
ahc_aic7892_setup
  464         },
  465         /* aic7895 based controllers */ 
  466         {
ID_AHA_2940U_DUAL,
ID_ALL_MASK,
ahc_aic7895_setup
  470         },
  471         {
ID_AHA_3940AU,
ID_ALL_MASK,
ahc_aic7895_setup
  475         },
  476         {
ID_AHA_3944AU,
ID_ALL_MASK,
ahc_aic7895_setup
  480         },
  481         {
ID_AIC7895_ARO,
ID_AIC7895_ARO_MASK,
ahc_aic7895_setup
  485         },
  486         /* aic7896/97 based controllers */      
  487         {
ID_AHA_3950U2B_0,
ID_ALL_MASK,
ahc_aic7896_setup
  491         },
  492         {
ID_AHA_3950U2B_1,
ID_ALL_MASK,
ahc_aic7896_setup
  496         },
  497         {
ID_AHA_3950U2D_0,
ID_ALL_MASK,
ahc_aic7896_setup
  501         },
  502         {
ID_AHA_3950U2D_1,
ID_ALL_MASK,
ahc_aic7896_setup
  506         },
  507         {
ID_AIC7896_ARO,
ID_ALL_MASK,
ahc_aic7896_setup
  511         },
  512         /* aic7899 based controllers */ 
  513         {
ID_AHA_3960D,
ID_ALL_MASK,
ahc_aic7899_setup
  517         },
  518         {
ID_AHA_3960D_CPQ,
ID_ALL_MASK,
ahc_aic7899_setup
  522         },
  523         {
ID_AIC7899_ARO,
ID_ALL_MASK,
ahc_aic7899_setup
  527         },
  528         /* Generic chip probes for devices we don't know 'exactly' */
  529         {
ID_AIC7850 & ID_DEV_VENDOR_MASK,
ID_DEV_VENDOR_MASK,
ahc_aic785X_setup
  533         },
  534         {
ID_AIC7855 & ID_DEV_VENDOR_MASK,
ID_DEV_VENDOR_MASK,
ahc_aic785X_setup
  538         },
  539         {
ID_AIC7859 & ID_DEV_VENDOR_MASK,
ID_DEV_VENDOR_MASK,
ahc_aic7860_setup
  543         },
  544         {
ID_AIC7860 & ID_DEV_VENDOR_MASK,
ID_DEV_VENDOR_MASK,
ahc_aic7860_setup
  548         },
  549         {
ID_AIC7870 & ID_DEV_VENDOR_MASK,
ID_DEV_VENDOR_MASK,
ahc_aic7870_setup
  553         },
  554         {
ID_AIC7880 & ID_DEV_VENDOR_MASK,
ID_DEV_VENDOR_MASK,
ahc_aic7880_setup
  558         },
  559         {
ID_AIC7890 & ID_9005_GENERIC_MASK,
ID_9005_GENERIC_MASK,
ahc_aic7890_setup
  563         },
  564         {
ID_AIC7892 & ID_9005_GENERIC_MASK,
ID_9005_GENERIC_MASK,
ahc_aic7892_setup
  568         },
  569         {
ID_AIC7895 & ID_DEV_VENDOR_MASK,
ID_DEV_VENDOR_MASK,
ahc_aic7895_setup
  573         },
  574         {
ID_AIC7896 & ID_9005_GENERIC_MASK,
ID_9005_GENERIC_MASK,
ahc_aic7896_setup
  578         },
  579         {
ID_AIC7899 & ID_9005_GENERIC_MASK,
ID_9005_GENERIC_MASK,
ahc_aic7899_setup
  583         },
  584         {
ID_AIC7810 & ID_DEV_VENDOR_MASK,
ID_DEV_VENDOR_MASK,
ahc_raid_setup
  588         },
  589         {
ID_AIC7815 & ID_DEV_VENDOR_MASK,
ID_DEV_VENDOR_MASK,
ahc_raid_setup
  593         }
  594 };
  596 #define AHC_394X_SLOT_CHANNEL_A 4
  597 #define AHC_394X_SLOT_CHANNEL_B 5
  599 #define AHC_398X_SLOT_CHANNEL_A 4
  600 #define AHC_398X_SLOT_CHANNEL_B 8
  601 #define AHC_398X_SLOT_CHANNEL_C 12
  603 #define AHC_494X_SLOT_CHANNEL_A 4
  604 #define AHC_494X_SLOT_CHANNEL_B 5
  605 #define AHC_494X_SLOT_CHANNEL_C 6
  606 #define AHC_494X_SLOT_CHANNEL_D 7
  608 #define DEVCONFIG               0x40
  609 #define         PCIERRGENDIS    0x80000000ul
  610 #define         SCBSIZE32       0x00010000ul    /* aic789X only */
  611 #define         REXTVALID       0x00001000ul    /* ultra cards only */
  612 #define         MPORTMODE       0x00000400ul    /* aic7870+ only */
  613 #define         RAMPSM          0x00000200ul    /* aic7870+ only */
  614 #define         VOLSENSE        0x00000100ul
  615 #define         PCI64BIT        0x00000080ul    /* 64Bit PCI bus (Ultra2 Only)*/
  616 #define         SCBRAMSEL       0x00000080ul
  617 #define         MRDCEN          0x00000040ul
  618 #define         EXTSCBTIME      0x00000020ul    /* aic7870 only */
  619 #define         EXTSCBPEN       0x00000010ul    /* aic7870 only */
  620 #define         BERREN          0x00000008ul
  621 #define         DACEN           0x00000004ul
  622 #define         STPWLEVEL       0x00000002ul
  623 #define         DIFACTNEGEN     0x00000001ul    /* aic7870 only */
  625 #define CSIZE_LATTIME           0x0c
  626 #define         CACHESIZE       0x0000003ful    /* only 5 bits */
  627 #define         LATTIME         0x0000ff00ul
  629 /* PCI STATUS definitions */
  630 #define DPE     0x80
  631 #define SSE     0x40
  632 #define RMA     0x20
  633 #define RTA     0x10
  634 #define STA     0x08
  635 #define DPR     0x01
  637 static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device,
uint16_t subvendor, uint16_t subdevice);
  639 static int ahc_ext_scbram_present(struct ahc_softc *ahc);
  640 static void ahc_scbram_config(struct ahc_softc *ahc, int enable,
  641                                   int pcheck, int fast, int large);
  642 static void ahc_probe_ext_scbram(struct ahc_softc *ahc);
  643 static int  ahc_pci_chip_init(struct ahc_softc *ahc);
  645 int ahc_pci_probe(struct device *, void *, void *);
  646 void ahc_pci_attach(struct device *, struct device *, void *);
  649 struct cfattach ahc_pci_ca = {
  650         sizeof(struct ahc_softc), ahc_pci_probe, ahc_pci_attach
  651 };
  653 const struct ahc_pci_identity *
ahc_find_pci_device(id, subid, func)
pcireg_t id, subid;
u_int func;
  657 {
u_int64_t  full_id;
  659         const struct       ahc_pci_identity *entry;
u_int      i;
full_id = ahc_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id),
PCI_PRODUCT(subid), PCI_VENDOR(subid));
  665         /*
  666          * If the second function is not hooked up, ignore it.
  667          * Unfortunately, not all MB vendors implement the
  668          * subdevice ID as per the Adaptec spec, so do our best
  669          * to sanity check it prior to accepting the subdevice
  670          * ID as valid.
  671          */
  672         if (func > 0
  673             && ahc_9005_subdevinfo_valid(PCI_VENDOR(id), PCI_PRODUCT(id), 
PCI_VENDOR(subid), PCI_PRODUCT(subid))
  675             && SUBID_9005_MFUNCENB(PCI_PRODUCT(subid)) == 0)
  676                 return (NULL);
  678         for (i = 0; i < NUM_ELEMENTS(ahc_pci_ident_table); i++) {
entry = &ahc_pci_ident_table[i];
  680                 if (entry->full_id == (full_id & entry->id_mask))
  681                         return (entry);
  682         }
  683         return (NULL);
  684 }
  686 int
ahc_pci_probe(parent, match, aux)
  688         struct device *parent;
  689         void *match, *aux;
  690 {
  691         struct pci_attach_args *pa = aux;
  692         const struct       ahc_pci_identity *entry;
pcireg_t   subid;
subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
entry = ahc_find_pci_device(pa->pa_id, subid, pa->pa_function);
  697         return (entry != NULL && entry->setup != NULL) ? 1 : 0;
  698 }
  700 void
ahc_pci_attach(parent, self, aux)
  702         struct device *parent, *self;
  703         void *aux;
  704 {
  705         struct pci_attach_args *pa = aux;
  706         const struct       ahc_pci_identity *entry;
  707         struct             ahc_softc *ahc = (void *)self;
pcireg_t           command;
u_int              our_id = 0;
u_int              sxfrctl1;
u_int              scsiseq;
u_int              sblkctl;
uint8_t            dscommand0;
uint32_t           devconfig;
  715         int                error;
pcireg_t           subid;
  717         int                ioh_valid;
bus_space_tag_t    st, iot;
bus_space_handle_t sh, ioh;
  720 #ifdef AHC_ALLOW_MEMIO
  721         int                memh_valid;
bus_space_tag_t    memt;
bus_space_handle_t memh;
pcireg_t memtype;
  725 #endif
pci_intr_handle_t  ih;
  727         const char        *intrstr;
  728         struct ahc_pci_busdata *bd;
  729         int i;
  731         /*
  732          * Instead of ahc_alloc() as in FreeBSD, do the few relevant
  733          * initializations manually.
  734          */
LIST_INIT(&ahc->pending_scbs);
ahc->channel = 'A';
ahc->seqctl = FASTMODE;
  738         for (i = 0; i < AHC_NUM_TARGETS; i++)
TAILQ_INIT(&ahc->untagged_queues[i]);
  741         /*
  742          * SCSI_IS_SCSIBUS_B() must returns false until sc_channel_b
  743          * has been properly initialized. XXX Breaks if >254 scsi buses.
  744          */
ahc->sc_channel_b.scsibus = 0xff;
ahc->dev_softc = pa;
ahc_set_name(ahc, ahc->sc_dev.dv_xname);
ahc->parent_dmat = pa->pa_dmat;
subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
entry = ahc_find_pci_device(pa->pa_id, subid, pa->pa_function);
  754         if (entry == NULL)
  755                 return;
  757         /* Keep information about the PCI bus */
bd = malloc(sizeof (struct ahc_pci_busdata), M_DEVBUF, M_NOWAIT);
  759         if (bd == NULL) {
printf("%s: unable to allocate bus-specific data\n", ahc_name(ahc));
  761                 return;
  762         }
memset(bd, 0, sizeof(struct ahc_pci_busdata));
bd->pc = pa->pa_pc;
bd->tag = pa->pa_tag;
bd->func = pa->pa_function;
bd->dev = pa->pa_device;
bd->class = pa->pa_class;
ahc->bd = bd;
error = entry->setup(ahc);
  774         if (error != 0)
  775                 return;
ioh_valid = 0;
  779 #ifdef AHC_ALLOW_MEMIO
memh_valid = 0;
memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHC_PCI_MEMADDR);
  782         switch (memtype) {
  783         case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
  784         case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
memh_valid = (pci_mapreg_map(pa, AHC_PCI_MEMADDR,
memtype, 0, &memt, &memh, NULL, NULL, 0) == 0);
  787                 break;
  788         default:
memh_valid = 0;
  790         }
  791         if (memh_valid == 0)
  792 #endif
ioh_valid = (pci_mapreg_map(pa, AHC_PCI_IOADDR,
PCI_MAPREG_TYPE_IO, 0, &iot, &ioh, NULL, NULL, 0) == 0);
  795 #if 0
printf("%s: mem mapping: memt 0x%x, memh 0x%x, iot 0x%x, ioh 0x%lx\n",
ahc_name(ahc), memt, (u_int32_t)memh, (u_int32_t)iot, ioh);
  798 #endif
  800         if (ioh_valid) {
st = iot;
sh = ioh;
  803 #ifdef AHC_ALLOW_MEMIO
  804         } else if (memh_valid) {
st = memt;
sh = memh;
  807 #endif
  808         } else {
printf(": unable to map registers\n");
  810                 return;
  811         }
ahc->tag = st;
ahc->bsh = sh;
ahc->chip |= AHC_PCI;
  816         /*
  817          * Before we continue probing the card, ensure that
  818          * its interrupts are *disabled*.  We don't want
  819          * a misstep to hang the machine in an interrupt
  820          * storm.
  821          */
ahc_intr_enable(ahc, FALSE);
  824         /*
  825          * XXX somehow reading this once fails on some sparc64 systems.
  826          *     This may be a problem in the sparc64 PCI code. Doing it
  827          *     twice works around it.
  828          */
devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG);
devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG);
  832         /*
  833          * If we need to support high memory, enable dual
  834          * address cycles.  This bit must be set to enable
  835          * high address bit generation even if we are on a
  836          * 64bit bus (PCI64BIT set in devconfig).
  837          */
  838         if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
  840                 if (1/*bootverbose*/)
printf("%s: Enabling 39Bit Addressing\n",
ahc_name(ahc));
devconfig |= DACEN;
  844         }
  846         /* Ensure that pci error generation, a test feature, is disabled. */
devconfig |= PCIERRGENDIS;
pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig);
  851         /*
  852          * Disable PCI parity error reporting.  Users typically
  853          * do this to work around broken PCI chipsets that get
  854          * the parity timing wrong and thus generate lots of spurious
  855          * errors.
  856          */
  857         if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0) {
command = pci_conf_read(pa->pa_pc, pa->pa_tag,
PCI_COMMAND_STATUS_REG);
pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
command & ~PCI_COMMAND_PARITY_ENABLE);
  862         }
  864         /* On all PCI adapters, we allow SCB paging */
ahc->flags |= AHC_PAGESCBS;
error = ahc_softc_init(ahc);
  867         if (error != 0)
  868                 goto error_out;
ahc->bus_intr = ahc_pci_intr;
ahc->bus_chip_init = ahc_pci_chip_init;
  873         /* Remember how the card was setup in case there is no SEEPROM */
  874         if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) {
ahc_pause(ahc);
  876                 if ((ahc->features & AHC_ULTRA2) != 0)
our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
  878                 else
our_id = ahc_inb(ahc, SCSIID) & OID;
sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN;
scsiseq = ahc_inb(ahc, SCSISEQ);
  882         } else {
sxfrctl1 = STPWEN;
our_id = 7;
scsiseq = 0;
  886         }
error = ahc_reset(ahc, /*reinit*/FALSE);
  889         if (error != 0)
  890                 goto error_out;
  892         if ((ahc->features & AHC_DT) != 0) {
u_int sfunct;
  895                 /* Perform ALT-Mode Setup */
sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
ahc_outb(ahc, OPTIONMODE,
OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS);
ahc_outb(ahc, SFUNCT, sfunct);
  902                 /* Normal mode setup */
ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN
  904                                           |TARGCRCENDEN);
  905         }
  907         if (pci_intr_map(pa, &ih)) {
printf("%s: couldn't map interrupt\n", ahc_name(ahc));
ahc_free(ahc);
  910                 return;
  911         }
intrstr = pci_intr_string(pa->pa_pc, ih);
ahc->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO,
ahc_platform_intr, ahc, ahc->sc_dev.dv_xname);
  915         if (ahc->ih == NULL) {
printf(": couldn't establish interrupt");
  917                 if (intrstr != NULL)
printf(" at %s", intrstr);
printf("\n");
ahc_free(ahc);
  921                 return;
  922         } else
printf(": %s\n", intrstr ? intrstr : "?");
dscommand0 = ahc_inb(ahc, DSCOMMAND0);
dscommand0 |= MPARCKEN|CACHETHEN;
  927         if ((ahc->features & AHC_ULTRA2) != 0) {
  929                 /*
  930                  * DPARCKEN doesn't work correctly on
  931                  * some MBs so don't use it.
  932                  */
dscommand0 &= ~DPARCKEN;
  934         }
  936         /*
  937          * Handle chips that must have cache line
  938          * streaming (dis/en)abled.
  939          */
  940         if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0)
dscommand0 |= CACHETHEN;
  943         if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0)
dscommand0 &= ~CACHETHEN;
ahc_outb(ahc, DSCOMMAND0, dscommand0);
ahc->pci_cachesize =
pci_conf_read(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME) & CACHESIZE;
ahc->pci_cachesize *= 4;
  952         if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0
  953             && ahc->pci_cachesize == 4) {
pci_conf_write(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME, 0);
ahc->pci_cachesize = 0;
  956         }
  958         /*
  959          * We cannot perform ULTRA speeds without the presence
  960          * of the external precision resistor.
  961          */
  962         if ((ahc->features & AHC_ULTRA) != 0) {
uint32_t devconfig;
devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG);
  966                 if ((devconfig & REXTVALID) == 0)
ahc->features &= ~AHC_ULTRA;
  968         }
ahc->seep_config = malloc(sizeof(*ahc->seep_config),
M_DEVBUF, M_NOWAIT);
  972         if (ahc->seep_config == NULL)
  973                 goto error_out;
memset(ahc->seep_config, 0, sizeof(*ahc->seep_config));
  977         /* See if we have a SEEPROM and perform auto-term */
ahc_check_extport(ahc, &sxfrctl1);
  980         /*
  981          * Take the LED out of diagnostic mode
  982          */
sblkctl = ahc_inb(ahc, SBLKCTL);
ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
  986         if ((ahc->features & AHC_ULTRA2) != 0) {
ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX);
  988         } else {
ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100);
  990         }
  992         if (ahc->flags & AHC_USEDEFAULTS) {
  993                 /*
  994                  * PCI Adapter default setup
  995                  * Should only be used if the adapter does not have
  996                  * a SEEPROM.
  997                  */
  998                 /* See if someone else set us up already */
  999                 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0
 1000                  && scsiseq != 0) {
printf("%s: Using left over BIOS settings\n",
ahc_name(ahc));
ahc->flags &= ~AHC_USEDEFAULTS;
ahc->flags |= AHC_BIOS_ENABLED;
 1005                 } else {
 1006                         /*
 1007                          * Assume only one connector and always turn
 1008                          * on termination.
 1009                          */
our_id = 0x07;
sxfrctl1 = STPWEN;
 1012                 }
ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI);
ahc->our_id = our_id;
 1016         }
 1018         /*
 1019          * Take a look to see if we have external SRAM.
 1020          * We currently do not attempt to use SRAM that is
 1021          * shared among multiple controllers.
 1022          */
ahc_probe_ext_scbram(ahc);
 1025         /*
 1026          * Record our termination setting for the
 1027          * generic initialization routine.
 1028          */
 1029         if ((sxfrctl1 & STPWEN) != 0)
ahc->flags |= AHC_TERM_ENB_A;
 1032         /*
 1033          * Save chip register configuration data for chip resets
 1034          * that occur during runtime and resume events.
 1035          */
ahc->bus_softc.pci_softc.devconfig =
pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG);
ahc->bus_softc.pci_softc.command =
pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
ahc->bus_softc.pci_softc.csize_lattime =
pci_conf_read(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME);
ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0);
ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS);
 1044         if ((ahc->features & AHC_DT) != 0) {
u_int sfunct;
sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE);
ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT);
ahc_outb(ahc, SFUNCT, sfunct);
ahc->bus_softc.pci_softc.crccontrol1 =
ahc_inb(ahc, CRCCONTROL1);
 1054         }
 1055         if ((ahc->features & AHC_MULTI_FUNC) != 0)
ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR);
 1058         if ((ahc->features & AHC_ULTRA2) != 0)
ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH);
 1061         /* Core initialization */
 1062         if (ahc_init(ahc))
 1063                 goto error_out;
ahc_attach(ahc);
 1067         return;
error_out:
ahc_free(ahc);
 1071         return;
 1072 }
 1074 static int
ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor,
uint16_t subdevice, uint16_t subvendor)
 1077 {
 1078         int result;
 1080         /* Default to invalid. */
result = 0;
 1082         if (vendor == 0x9005
 1083          && subvendor == 0x9005
 1084          && subdevice != device
 1085          && SUBID_9005_TYPE_KNOWN(subdevice) != 0) {
 1087                 switch (SUBID_9005_TYPE(subdevice)) {
 1088                 case SUBID_9005_TYPE_MB:
 1089                         break;
 1090                 case SUBID_9005_TYPE_CARD:
 1091                 case SUBID_9005_TYPE_LCCARD:
 1092                         /*
 1093                          * Currently only trust Adaptec cards to
 1094                          * get the sub device info correct.
 1095                          */
 1096                         if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA)
result = 1;
 1098                         break;
 1099                 case SUBID_9005_TYPE_RAID:
 1100                         break;
 1101                 default:
 1102                         break;
 1103                 }
 1104         }
 1105         return (result);
 1106 }
 1109 /*
 1110  * Test for the presense of external sram in an
 1111  * "unshared" configuration.
 1112  */
 1113 static int
ahc_ext_scbram_present(struct ahc_softc *ahc)
 1115 {
u_int chip;
 1117         int ramps;
 1118         int single_user;
uint32_t devconfig;
chip = ahc->chip & AHC_CHIPID_MASK;
devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG);
single_user = (devconfig & MPORTMODE) != 0;
 1125         if ((ahc->features & AHC_ULTRA2) != 0)
ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0;
 1127         else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C)
 1128                 /*
 1129                  * External SCBRAM arbitration is flakey
 1130                  * on these chips.  Unfortunately this means
 1131                  * we don't use the extra SCB ram space on the
 1132                  * 3940AUW.
 1133                  */
ramps = 0;
 1135         else if (chip >= AHC_AIC7870)
ramps = (devconfig & RAMPSM) != 0;
 1137         else
ramps = 0;
 1140         if (ramps && single_user)
 1141                 return (1);
 1142         return (0);
 1143 }
 1145 /*
 1146  * Enable external scbram.
 1147  */
 1148 static void
ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck,
 1150                   int fast, int large)
 1151 {
uint32_t devconfig;
 1154         if (ahc->features & AHC_MULTI_FUNC) {
 1155                 /*
 1156                  * Set the SCB Base addr (highest address bit)
 1157                  * depending on which channel we are.
 1158                  */
ahc_outb(ahc, SCBBADDR, ahc->bd->func);
 1160         }
ahc->flags &= ~AHC_LSCBS_ENABLED;
 1163         if (large)
ahc->flags |= AHC_LSCBS_ENABLED;
devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG);
 1166         if ((ahc->features & AHC_ULTRA2) != 0) {
u_int dscommand0;
dscommand0 = ahc_inb(ahc, DSCOMMAND0);
 1170                 if (enable)
dscommand0 &= ~INTSCBRAMSEL;
 1172                 else
dscommand0 |= INTSCBRAMSEL;
 1174                 if (large)
dscommand0 &= ~USCBSIZE32;
 1176                 else
dscommand0 |= USCBSIZE32;
ahc_outb(ahc, DSCOMMAND0, dscommand0);
 1179         } else {
 1180                 if (fast)
devconfig &= ~EXTSCBTIME;
 1182                 else
devconfig |= EXTSCBTIME;
 1184                 if (enable)
devconfig &= ~SCBRAMSEL;
 1186                 else
devconfig |= SCBRAMSEL;
 1188                 if (large)
devconfig &= ~SCBSIZE32;
 1190                 else
devconfig |= SCBSIZE32;
 1192         }
 1193         if (pcheck)
devconfig |= EXTSCBPEN;
 1195         else
devconfig &= ~EXTSCBPEN;
pci_conf_write(ahc->bd->pc, ahc->bd->tag, DEVCONFIG, devconfig);
 1199 }
 1201 /*
 1202  * Take a look to see if we have external SRAM.
 1203  * We currently do not attempt to use SRAM that is
 1204  * shared among multiple controllers.
 1205  */
 1206 static void
ahc_probe_ext_scbram(struct ahc_softc *ahc)
 1208 {
 1209         int num_scbs;
 1210         int test_num_scbs;
 1211         int enable;
 1212         int pcheck;
 1213         int fast;
 1214         int large;
enable = FALSE;
pcheck = FALSE;
fast = FALSE;
large = FALSE;
num_scbs = 0;
 1222         if (ahc_ext_scbram_present(ahc) == 0)
 1223                 goto done;
 1225         /*
 1226          * Probe for the best parameters to use.
 1227          */
ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large);
num_scbs = ahc_probe_scbs(ahc);
 1230         if (num_scbs == 0) {
 1231                 /* The SRAM wasn't really present. */
 1232                 goto done;
 1233         }
enable = TRUE;
 1236         /*
 1237          * Clear any outstanding parity error
 1238          * and ensure that parity error reporting
 1239          * is enabled.
 1240          */
ahc_outb(ahc, SEQCTL, 0);
ahc_outb(ahc, CLRINT, CLRPARERR);
ahc_outb(ahc, CLRINT, CLRBRKADRINT);
 1245         /* Now see if we can do parity */
ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large);
num_scbs = ahc_probe_scbs(ahc);
 1248         if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
 1249          || (ahc_inb(ahc, ERROR) & MPARERR) == 0)
pcheck = TRUE;
 1252         /* Clear any resulting parity error */
ahc_outb(ahc, CLRINT, CLRPARERR);
ahc_outb(ahc, CLRINT, CLRBRKADRINT);
 1256         /* Now see if we can do fast timing */
ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large);
test_num_scbs = ahc_probe_scbs(ahc);
 1259         if (test_num_scbs == num_scbs
 1260          && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
 1261           || (ahc_inb(ahc, ERROR) & MPARERR) == 0))
fast = TRUE;
 1264         /*
 1265          * See if we can use large SCBs and still maintain
 1266          * the same overall count of SCBs.
 1267          */
 1268         if ((ahc->features & AHC_LARGE_SCBS) != 0) {
ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE);
test_num_scbs = ahc_probe_scbs(ahc);
 1271                 if (test_num_scbs >= num_scbs) {
large = TRUE;
num_scbs = test_num_scbs;
 1274                         if (num_scbs >= 64) {
 1275                                 /*
 1276                                  * We have enough space to move the
 1277                                  * "busy targets table" into SCB space
 1278                                  * and make it qualify all the way to the
 1279                                  * lun level.
 1280                                  */
ahc->flags |= AHC_SCB_BTT;
 1282                         }
 1283                 }
 1284         }
done:
 1286         /*
 1287          * Disable parity error reporting until we
 1288          * can load instruction ram.
 1289          */
ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
 1291         /* Clear any latched parity error */
ahc_outb(ahc, CLRINT, CLRPARERR);
ahc_outb(ahc, CLRINT, CLRBRKADRINT);
 1294         if (1/*bootverbose*/ && enable) {
printf("%s: External SRAM, %s access%s, %dbytes/SCB\n",
ahc_name(ahc), fast ? "fast" : "slow", 
pcheck ? ", parity checking enabled" : "",
large ? 64 : 32);
 1299         }
ahc_scbram_config(ahc, enable, pcheck, fast, large);
 1301 }
 1303 #if 0
 1304 /*
 1305  * Perform some simple tests that should catch situations where
 1306  * our registers are invalidly mapped.
 1307  */
 1308 int
ahc_pci_test_register_access(struct ahc_softc *ahc)
 1310 {
 1311         int      error;
u_int    status1;
uint32_t cmd;
uint8_t  hcntrl;
error = EIO;
 1318         /*
 1319          * Enable PCI error interrupt status, but suppress NMIs
 1320          * generated by SERR raised due to target aborts.
 1321          */
cmd = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCIR_COMMAND);
pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCIR_COMMAND,
cmd & ~PCIM_CMD_SERRESPEN);
 1326         /*
 1327          * First a simple test to see if any
 1328          * registers can be read.  Reading
 1329          * HCNTRL has no side effects and has
 1330          * at least one bit that is guaranteed to
 1331          * be zero so it is a good register to
 1332          * use for this test.
 1333          */
hcntrl = ahc_inb(ahc, HCNTRL);
 1335         if (hcntrl == 0xFF)
 1336                 goto fail;
 1338         /*
 1339          * Next create a situation where write combining
 1340          * or read prefetching could be initiated by the
 1341          * CPU or host bridge.  Our device does not support
 1342          * either, so look for data corruption and/or flagged
 1343          * PCI errors.
 1344          */
ahc_outb(ahc, HCNTRL, hcntrl|PAUSE);
 1346         while (ahc_is_paused(ahc) == 0)
 1347                 ;
ahc_outb(ahc, SEQCTL, PERRORDIS);
ahc_outb(ahc, SCBPTR, 0);
ahc_outl(ahc, SCB_BASE, 0x5aa555aa);
 1351         if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa)
 1352                 goto fail;
status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag,
PCI_COMMAND_STATUS_REG + 1);
 1356         if ((status1 & STA) != 0)
 1357                 goto fail;
error = 0;
fail:
 1362         /* Silently clear any latched errors. */
status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG + 1);
ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
status1, /*bytes*/1);
ahc_outb(ahc, CLRINT, CLRPARERR);
ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
 1369         return (error);
 1370 }
 1371 #endif
 1373 void
ahc_pci_intr(struct ahc_softc *ahc)
 1375 {
u_int error;
u_int status1;
error = ahc_inb(ahc, ERROR);
 1380         if ((error & PCIERRSTAT) == 0)
 1381                 return;
status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG);
printf("%s: PCI error Interrupt at seqaddr = 0x%x\n",
ahc_name(ahc),
ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
 1389         if (status1 & DPE) {
printf("%s: Data Parity Error Detected during address "
 1391                        "or write data phase\n", ahc_name(ahc));
 1392         }
 1393         if (status1 & SSE) {
printf("%s: Signal System Error Detected\n", ahc_name(ahc));
 1395         }
 1396         if (status1 & RMA) {
printf("%s: Received a Master Abort\n", ahc_name(ahc));
 1398         }
 1399         if (status1 & RTA) {
printf("%s: Received a Target Abort\n", ahc_name(ahc));
 1401         }
 1402         if (status1 & STA) {
printf("%s: Signaled a Target Abort\n", ahc_name(ahc));
 1404         }
 1405         if (status1 & DPR) {
printf("%s: Data Parity Error has been reported via PERR#\n",
ahc_name(ahc));
 1408         }
 1410         /* Clear latched errors. */
pci_conf_write(ahc->bd->pc, ahc->bd->tag,  PCI_COMMAND_STATUS_REG, status1);
 1413         if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) {
printf("%s: Latched PCIERR interrupt with "
 1415                        "no status bits set\n", ahc_name(ahc)); 
 1416         } else {
ahc_outb(ahc, CLRINT, CLRPARERR);
 1418         }
ahc_unpause(ahc);
 1421 }
 1423 static int
ahc_pci_chip_init(struct ahc_softc *ahc)
 1425 {
ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0);
ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus);
 1428         if ((ahc->features & AHC_DT) != 0) {
u_int sfunct;
sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode);
ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt);
ahc_outb(ahc, SFUNCT, sfunct);
ahc_outb(ahc, CRCCONTROL1,
ahc->bus_softc.pci_softc.crccontrol1);
 1438         }
 1439         if ((ahc->features & AHC_MULTI_FUNC) != 0)
ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr);
 1442         if ((ahc->features & AHC_ULTRA2) != 0)
ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh);
 1445         return (ahc_chip_init(ahc));
 1446 }
 1448 static int
ahc_aic785X_setup(struct ahc_softc *ahc)
 1450 {
uint8_t rev;
ahc->channel = 'A';
ahc->chip = AHC_AIC7850;
ahc->features = AHC_AIC7850_FE;
ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
rev = PCI_REVISION(ahc->bd->class);
 1458         if (rev >= 1)
ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
ahc->instruction_ram_size = 512;
 1461         return (0);
 1462 }
 1464 static int
ahc_aic7860_setup(struct ahc_softc *ahc)
 1466 {
uint8_t rev;
ahc->channel = 'A';
ahc->chip = AHC_AIC7860;
ahc->features = AHC_AIC7860_FE;
ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
rev = PCI_REVISION(ahc->bd->class);
 1474         if (rev >= 1)
ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
ahc->instruction_ram_size = 512;
 1477         return (0);
 1478 }
 1480 static int
ahc_apa1480_setup(struct ahc_softc *ahc)
 1482 {
 1483         int error;
error = ahc_aic7860_setup(ahc);
 1486         if (error != 0)
 1487                 return (error);
ahc->features |= AHC_REMOVABLE;
 1489         return (0);
 1490 }
 1492 static int
ahc_aic7870_setup(struct ahc_softc *ahc)
 1494 {
ahc->channel = 'A';
ahc->chip = AHC_AIC7870;
ahc->features = AHC_AIC7870_FE;
ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
ahc->instruction_ram_size = 512;
 1501         return (0);
 1502 }
 1504 static int
ahc_aha394X_setup(struct ahc_softc *ahc)
 1506 {
 1507         int error;
error = ahc_aic7870_setup(ahc);
 1510         if (error == 0)
error = ahc_aha394XX_setup(ahc);
 1512         return (error);
 1513 }
 1515 static int
ahc_aha398X_setup(struct ahc_softc *ahc)
 1517 {
 1518         int error;
error = ahc_aic7870_setup(ahc);
 1521         if (error == 0)
error = ahc_aha398XX_setup(ahc);
 1523         return (error);
 1524 }
 1526 static int
ahc_aha494X_setup(struct ahc_softc *ahc)
 1528 {
 1529         int error;
error = ahc_aic7870_setup(ahc);
 1532         if (error == 0)
error = ahc_aha494XX_setup(ahc);
 1534         return (error);
 1535 }
 1537 static int
ahc_aic7880_setup(struct ahc_softc *ahc)
 1539 {
uint8_t rev;
ahc->channel = 'A';
ahc->chip = AHC_AIC7880;
ahc->features = AHC_AIC7880_FE;
ahc->bugs |= AHC_TMODE_WIDEODD_BUG;
rev = PCI_REVISION(ahc->bd->class);
 1547         if (rev >= 1) {
ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
 1549         } else {
ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
 1551         }
ahc->instruction_ram_size = 512;
 1553         return (0);
 1554 }
 1556 static int
ahc_aha2940Pro_setup(struct ahc_softc *ahc)
 1558 {
ahc->flags |= AHC_INT50_SPEEDFLEX;
 1561         return (ahc_aic7880_setup(ahc));
 1562 }
 1564 static int
ahc_aha394XU_setup(struct ahc_softc *ahc)
 1566 {
 1567         int error;
error = ahc_aic7880_setup(ahc);
 1570         if (error == 0)
error = ahc_aha394XX_setup(ahc);
 1572         return (error);
 1573 }
 1575 static int
ahc_aha398XU_setup(struct ahc_softc *ahc)
 1577 {
 1578         int error;
error = ahc_aic7880_setup(ahc);
 1581         if (error == 0)
error = ahc_aha398XX_setup(ahc);
 1583         return (error);
 1584 }
 1586 static int
ahc_aic7890_setup(struct ahc_softc *ahc)
 1588 {
uint8_t rev;
ahc->channel = 'A';
ahc->chip = AHC_AIC7890;
ahc->features = AHC_AIC7890_FE;
ahc->flags |= AHC_NEWEEPROM_FMT;
rev = PCI_REVISION(ahc->bd->class);
 1596         if (rev == 0)
ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG;
ahc->instruction_ram_size = 768;
 1599         return (0);
 1600 }
 1602 static int
ahc_aic7892_setup(struct ahc_softc *ahc)
 1604 {
ahc->channel = 'A';
ahc->chip = AHC_AIC7892;
ahc->features = AHC_AIC7892_FE;
ahc->flags |= AHC_NEWEEPROM_FMT;
ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
ahc->instruction_ram_size = 1024;
 1612         return (0);
 1613 }
 1615 static int
ahc_aic7895_setup(struct ahc_softc *ahc)
 1617 {
uint8_t rev;
ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A';
 1621         /*
 1622          * The 'C' revision of the aic7895 has a few additional features.
 1623          */
rev = PCI_REVISION(ahc->bd->class);
 1625         if (rev >= 4) {
ahc->chip = AHC_AIC7895C;
ahc->features = AHC_AIC7895C_FE;
 1628         } else  {
u_int command;
ahc->chip = AHC_AIC7895;
ahc->features = AHC_AIC7895_FE;
 1634                 /*
 1635                  * The BIOS disables the use of MWI transactions
 1636                  * since it does not have the MWI bug work around
 1637                  * we have.  Disabling MWI reduces performance, so
 1638                  * turn it on again.
 1639                  */
command = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG);
command |=  PCI_COMMAND_INVALIDATE_ENABLE;
pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG, command);
ahc->bugs |= AHC_PCI_MWI_BUG;
 1644         }
 1645         /*
 1646          * XXX Does CACHETHEN really not work???  What about PCI retry?
 1647          * on C level chips.  Need to test, but for now, play it safe.
 1648          */
ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG
 1650                   |  AHC_CACHETHEN_BUG;
 1652 #if 0
uint32_t devconfig;
 1655         /*
 1656          * Cachesize must also be zero due to stray DAC
 1657          * problem when sitting behind some bridges.
 1658          */
pci_conf_write(ahc->bd->pc, ahc->bd->tag, CSIZE_LATTIME, 0);
devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG);
devconfig |= MRDCEN;
pci_conf_write(ahc->bd->pc, ahc->bd->tag, DEVCONFIG, devconfig);
 1663 #endif
ahc->flags |= AHC_NEWEEPROM_FMT;
ahc->instruction_ram_size = 512;
 1666         return (0);
 1667 }
 1669 static int
ahc_aic7896_setup(struct ahc_softc *ahc)
 1671 {
ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A';
ahc->chip = AHC_AIC7896;
ahc->features = AHC_AIC7896_FE;
ahc->flags |= AHC_NEWEEPROM_FMT;
ahc->bugs |= AHC_CACHETHEN_DIS_BUG;
ahc->instruction_ram_size = 768;
 1678         return (0);
 1679 }
 1681 static int
ahc_aic7899_setup(struct ahc_softc *ahc)
 1683 {
ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A';
ahc->chip = AHC_AIC7899;
ahc->features = AHC_AIC7899_FE;
ahc->flags |= AHC_NEWEEPROM_FMT;
ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
ahc->instruction_ram_size = 1024;
 1690         return (0);
 1691 }
 1693 static int
ahc_aha29160C_setup(struct ahc_softc *ahc)
 1695 {
 1696         int error;
error = ahc_aic7899_setup(ahc);
 1699         if (error != 0)
 1700                 return (error);
ahc->features |= AHC_REMOVABLE;
 1702         return (0);
 1703 }
 1705 static int
ahc_raid_setup(struct ahc_softc *ahc)
 1707 {
printf("RAID functionality unsupported\n");
 1709         return (ENXIO);
 1710 }
 1712 static int
ahc_aha394XX_setup(struct ahc_softc *ahc)
 1714 {
 1716         switch (ahc->bd->dev) {
 1717         case AHC_394X_SLOT_CHANNEL_A:
ahc->channel = 'A';
 1719                 break;
 1720         case AHC_394X_SLOT_CHANNEL_B:
ahc->channel = 'B';
 1722                 break;
 1723         default:
printf("adapter at unexpected slot %d\n"
 1725                        "unable to map to a channel\n",
ahc->bd->dev);
ahc->channel = 'A';
 1728         }
 1729         return (0);
 1730 }
 1732 static int
ahc_aha398XX_setup(struct ahc_softc *ahc)
 1734 {
 1736         switch (ahc->bd->dev) {
 1737         case AHC_398X_SLOT_CHANNEL_A:
ahc->channel = 'A';
 1739                 break;
 1740         case AHC_398X_SLOT_CHANNEL_B:
ahc->channel = 'B';
 1742                 break;
 1743         case AHC_398X_SLOT_CHANNEL_C:
ahc->channel = 'C';
 1745                 break;
 1746         default:
printf("adapter at unexpected slot %d\n"
 1748                        "unable to map to a channel\n",
ahc->bd->dev);
ahc->channel = 'A';
 1751                 break;
 1752         }
ahc->flags |= AHC_LARGE_SEEPROM;
 1754         return (0);
 1755 }
 1757 static int
ahc_aha494XX_setup(struct ahc_softc *ahc)
 1759 {
 1761         switch (ahc->bd->dev) {
 1762         case AHC_494X_SLOT_CHANNEL_A:
ahc->channel = 'A';
 1764                 break;
 1765         case AHC_494X_SLOT_CHANNEL_B:
ahc->channel = 'B';
 1767                 break;
 1768         case AHC_494X_SLOT_CHANNEL_C:
ahc->channel = 'C';
 1770                 break;
 1771         case AHC_494X_SLOT_CHANNEL_D:
ahc->channel = 'D';
 1773                 break;
 1774         default:
printf("adapter at unexpected slot %d\n"
 1776                        "unable to map to a channel\n",
ahc->bd->dev);
ahc->channel = 'A';
 1779         }
ahc->flags |= AHC_LARGE_SEEPROM;
 1781         return (0);
 1782 }