1 /* $OpenBSD: aic7xxxvar.h,v 1.24 2007/08/04 14:37:34 krw Exp $ */
2 /*
3 * Core definitions and data structures shareable across OS platforms.
4 *
5 * Copyright (c) 1994-2001 Justin T. Gibbs.
6 * Copyright (c) 2000-2001 Adaptec Inc.
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
16 * substantially similar to the "NO WARRANTY" disclaimer below
17 * ("Disclaimer") and any redistribution must be conditioned upon
18 * including a substantially similar Disclaimer requirement for further
19 * binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
38 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39 * POSSIBILITY OF SUCH DAMAGES.
40 *
41 * $Id: aic7xxxvar.h,v 1.24 2007/08/04 14:37:34 krw Exp $
42 *
43 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.h,v 1.50 2003/12/17 00:02:09 gibbs Exp $
44 */
45 /*
46 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003
47 */
48
49 #ifndef _AIC7XXXVAR_H_
50 #define _AIC7XXXVAR_H_
51
52 #undef AHC_DEBUG
53
54 /* Register Definitions */
55 #include <dev/microcode/aic7xxx/aic7xxx_reg.h>
56
57 #include <dev/ic/aic7xxx_cam.h>
58 /************************* Forward Declarations *******************************/
59 struct ahc_platform_data;
60 struct scb_platform_data;
61 struct seeprom_descriptor;
62
63 /****************************** Useful Macros *********************************/
64 #ifndef MAX
65 #define MAX(a,b) (((a) > (b)) ? (a) : (b))
66 #endif
67
68 #ifndef MIN
69 #define MIN(a,b) (((a) < (b)) ? (a) : (b))
70 #endif
71
72 #ifndef TRUE
73 #define TRUE 1
74 #endif
75 #ifndef FALSE
76 #define FALSE 0
77 #endif
78
79 #define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array))
80
81 #define ALL_CHANNELS '\0'
82 #define ALL_TARGETS_MASK 0xFFFF
83 #define INITIATOR_WILDCARD (~0)
84
85 #define SCSIID_TARGET(ahc, scsiid) \
86 (((scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? TWIN_TID : TID)) \
87 >> TID_SHIFT)
88 #define SCSIID_OUR_ID(scsiid) \
89 ((scsiid) & OID)
90 #define SCSIID_CHANNEL(ahc, scsiid) \
91 ((((ahc)->features & AHC_TWIN) != 0) \
92 ? ((((scsiid) & TWIN_CHNLB) != 0) ? 'B' : 'A') \
93 : 'A')
94 #define SCB_IS_SCSIBUS_B(ahc, scb) \
95 (SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B')
96 #define SCB_GET_OUR_ID(scb) \
97 SCSIID_OUR_ID((scb)->hscb->scsiid)
98 #define SCB_GET_TARGET(ahc, scb) \
99 SCSIID_TARGET((ahc), (scb)->hscb->scsiid)
100 #define SCB_GET_CHANNEL(ahc, scb) \
101 SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid)
102 #define SCB_GET_LUN(scb) \
103 ((scb)->hscb->lun & LID)
104 #define SCB_GET_TARGET_OFFSET(ahc, scb) \
105 (SCB_GET_TARGET(ahc, scb))
106 #define SCB_GET_TARGET_MASK(ahc, scb) \
107 (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb)))
108 #ifdef AHC_DEBUG
109 #define SCB_IS_SILENT(scb) \
110 ((ahc_debug & AHC_SHOW_MASKED_ERRORS) == 0 \
111 && (((scb)->flags & SCB_SILENT) != 0))
112 #else
113 #define SCB_IS_SILENT(scb) \
114 (((scb)->flags & SCB_SILENT) != 0)
115 #endif
116 #define TCL_TARGET_OFFSET(tcl) \
117 ((((tcl) >> 4) & TID) >> 4)
118 #define TCL_LUN(tcl) \
119 (tcl & (AHC_NUM_LUNS - 1))
120 #define BUILD_TCL(scsiid, lun) \
121 ((lun) | (((scsiid) & TID) << 4))
122
123 #ifndef AHC_TARGET_MODE
124 #undef AHC_TMODE_ENABLE
125 #define AHC_TMODE_ENABLE 0
126 #endif
127
128 /**************************** Driver Constants ********************************/
129 /*
130 * The maximum number of supported targets.
131 */
132 #define AHC_NUM_TARGETS 16
133
134 /*
135 * The maximum number of supported luns.
136 * The identify message only supports 64 luns in SPI3.
137 * You can have 2^64 luns when information unit transfers are enabled,
138 * but it is doubtful this driver will ever support IUTs.
139 */
140 #define AHC_NUM_LUNS 64
141
142 /*
143 * The maximum transfer per S/G segment.
144 * Limited by MAXPHYS or a 24-bit counter.
145 */
146 #define AHC_MAXTRANSFER_SIZE MIN(MAXPHYS,0x00ffffff)
147
148 /*
149 * The maximum amount of SCB storage in hardware on a controller.
150 * This value represents an upper bound. Controllers vary in the number
151 * they actually support.
152 */
153 #define AHC_SCB_MAX 255
154
155 /*
156 * The maximum number of concurrent transactions supported per driver instance.
157 * Sequencer Control Blocks (SCBs) store per-transaction information. Although
158 * the space for SCBs on the host adapter varies by model, the driver will
159 * page the SCBs between host and controller memory as needed. We are limited
160 * to 253 because:
161 * 1) The 8bit nature of the RISC engine holds us to an 8bit value.
162 * 2) We reserve one value, 255, to represent the invalid element.
163 * 3) Our input queue scheme requires one SCB to always be reserved
164 * in advance of queuing any SCBs. This takes us down to 254.
165 * 4) To handle our output queue correctly on machines that only
166 * support 32bit stores, we must clear the array 4 bytes at a
167 * time. To avoid colliding with a DMA write from the sequencer,
168 * we must be sure that 4 slots are empty when we write to clear
169 * the queue. This reduces us to 253 SCBs: 1 that just completed
170 * and the known three additional empty slots in the queue that
171 * precede it.
172 */
173 #define AHC_MAX_QUEUE 253
174
175 /*
176 * The maximum amount of SCB storage we allocate in host memory. This
177 * number should reflect the 1 additional SCB we require to handle our
178 * qinfifo mechanism.
179 */
180 #define AHC_SCB_MAX_ALLOC (AHC_MAX_QUEUE+1)
181
182 /*
183 * Ring Buffer of incoming target commands.
184 * We allocate 256 to simplify the logic in the sequencer
185 * by using the natural wrap point of an 8bit counter.
186 */
187 #define AHC_TMODE_CMDS 256
188
189 /* Reset line assertion time in us */
190 #define AHC_BUSRESET_DELAY 25
191
192 /******************* Chip Characteristics/Operating Settings *****************/
193 /*
194 * Chip Type
195 * The chip order is from least sophisticated to most sophisticated.
196 */
197 typedef enum {
198 AHC_NONE = 0x0000,
199 AHC_CHIPID_MASK = 0x00FF,
200 AHC_AIC7770 = 0x0001,
201 AHC_AIC7850 = 0x0002,
202 AHC_AIC7855 = 0x0003,
203 AHC_AIC7859 = 0x0004,
204 AHC_AIC7860 = 0x0005,
205 AHC_AIC7870 = 0x0006,
206 AHC_AIC7880 = 0x0007,
207 AHC_AIC7895 = 0x0008,
208 AHC_AIC7895C = 0x0009,
209 AHC_AIC7890 = 0x000a,
210 AHC_AIC7896 = 0x000b,
211 AHC_AIC7892 = 0x000c,
212 AHC_AIC7899 = 0x000d,
213 AHC_VL = 0x0100, /* Bus type VL */
214 AHC_EISA = 0x0200, /* Bus type EISA */
215 AHC_PCI = 0x0400, /* Bus type PCI */
216 AHC_BUS_MASK = 0x0F00
217 } ahc_chip;
218
219 /*
220 * Features available in each chip type.
221 */
222 typedef enum {
223 AHC_FENONE = 0x00000,
224 AHC_ULTRA = 0x00001, /* Supports 20MHz Transfers */
225 AHC_ULTRA2 = 0x00002, /* Supports 40MHz Transfers */
226 AHC_WIDE = 0x00004, /* Wide Channel */
227 AHC_TWIN = 0x00008, /* Twin Channel */
228 AHC_MORE_SRAM = 0x00010, /* 80 bytes instead of 64 */
229 AHC_CMD_CHAN = 0x00020, /* Has a Command DMA Channel */
230 AHC_QUEUE_REGS = 0x00040, /* Has Queue management registers */
231 AHC_SG_PRELOAD = 0x00080, /* Can perform auto-SG preload */
232 AHC_SPIOCAP = 0x00100, /* Has a Serial Port I/O Cap Register */
233 AHC_MULTI_TID = 0x00200, /* Has bitmask of TIDs for select-in */
234 AHC_HS_MAILBOX = 0x00400, /* Has HS_MAILBOX register */
235 AHC_DT = 0x00800, /* Double Transition transfers */
236 AHC_NEW_TERMCTL = 0x01000, /* Newer termination scheme */
237 AHC_MULTI_FUNC = 0x02000, /* Multi-Function Twin Channel Device */
238 AHC_LARGE_SCBS = 0x04000, /* 64byte SCBs */
239 AHC_AUTORATE = 0x08000, /* Automatic update of SCSIRATE/OFFSET*/
240 AHC_AUTOPAUSE = 0x10000, /* Automatic pause on register access */
241 AHC_TARGETMODE = 0x20000, /* Has tested target mode support */
242 AHC_MULTIROLE = 0x40000, /* Space for two roles at a time */
243 AHC_REMOVABLE = 0x80000, /* Hot-Swap supported */
244 AHC_AIC7770_FE = AHC_FENONE,
245 /*
246 * The real 7850 does not support Ultra modes, but there are
247 * several cards that use the generic 7850 PCI ID even though
248 * they are using an Ultra capable chip (7859/7860). We start
249 * out with the AHC_ULTRA feature set and then check the DEVSTATUS
250 * register to determine if the capability is really present.
251 */
252 AHC_AIC7850_FE = AHC_SPIOCAP|AHC_AUTOPAUSE|AHC_TARGETMODE|AHC_ULTRA,
253 AHC_AIC7860_FE = AHC_AIC7850_FE,
254 AHC_AIC7870_FE = AHC_TARGETMODE|AHC_AUTOPAUSE,
255 AHC_AIC7880_FE = AHC_AIC7870_FE|AHC_ULTRA,
256 /*
257 * Although we have space for both the initiator and
258 * target roles on ULTRA2 chips, we currently disable
259 * the initiator role to allow multi-scsi-id target mode
260 * configurations. We can only respond on the same SCSI
261 * ID as our initiator role if we allow initiator operation.
262 * At some point, we should add a configuration knob to
263 * allow both roles to be loaded.
264 */
265 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2
266 |AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID
267 |AHC_HS_MAILBOX|AHC_NEW_TERMCTL|AHC_LARGE_SCBS
268 |AHC_TARGETMODE,
269 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT|AHC_AUTORATE|AHC_AUTOPAUSE,
270 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM|AHC_AUTOPAUSE
271 |AHC_CMD_CHAN|AHC_MULTI_FUNC|AHC_LARGE_SCBS,
272 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID,
273 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC,
274 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC
275 } ahc_feature;
276
277 /*
278 * Bugs in the silicon that we work around in software.
279 */
280 typedef enum {
281 AHC_BUGNONE = 0x00,
282 /*
283 * On all chips prior to the U2 product line,
284 * the WIDEODD S/G segment feature does not
285 * work during scsi->HostBus transfers.
286 */
287 AHC_TMODE_WIDEODD_BUG = 0x01,
288 /*
289 * On the aic7890/91 Rev 0 chips, the autoflush
290 * feature does not work. A manual flush of
291 * the DMA FIFO is required.
292 */
293 AHC_AUTOFLUSH_BUG = 0x02,
294 /*
295 * On many chips, cacheline streaming does not work.
296 */
297 AHC_CACHETHEN_BUG = 0x04,
298 /*
299 * On the aic7896/97 chips, cacheline
300 * streaming must be enabled.
301 */
302 AHC_CACHETHEN_DIS_BUG = 0x08,
303 /*
304 * PCI 2.1 Retry failure on non-empty data fifo.
305 */
306 AHC_PCI_2_1_RETRY_BUG = 0x10,
307 /*
308 * Controller does not handle cacheline residuals
309 * properly on S/G segments if PCI MWI instructions
310 * are allowed.
311 */
312 AHC_PCI_MWI_BUG = 0x20,
313 /*
314 * An SCB upload using the SCB channel's
315 * auto array entry copy feature may
316 * corrupt data. This appears to only
317 * occur on 66MHz systems.
318 */
319 AHC_SCBCHAN_UPLOAD_BUG = 0x40
320 } ahc_bug;
321
322 /*
323 * Configuration specific settings.
324 * The driver determines these settings by probing the
325 * chip/controller's configuration.
326 */
327 typedef enum {
328 AHC_FNONE = 0x000,
329 AHC_PRIMARY_CHANNEL = 0x003, /*
330 * The channel that should
331 * be probed first.
332 */
333 AHC_USEDEFAULTS = 0x004, /*
334 * For cards without an seeprom
335 * or a BIOS to initialize the chip's
336 * SRAM, we use the default target
337 * settings.
338 */
339 AHC_SEQUENCER_DEBUG = 0x008,
340 AHC_SHARED_SRAM = 0x010,
341 AHC_LARGE_SEEPROM = 0x020, /* Uses C56_66 not C46 */
342 AHC_RESET_BUS_A = 0x040,
343 AHC_RESET_BUS_B = 0x080,
344 AHC_EXTENDED_TRANS_A = 0x100,
345 AHC_EXTENDED_TRANS_B = 0x200,
346 AHC_TERM_ENB_A = 0x400,
347 AHC_TERM_ENB_B = 0x800,
348 AHC_INITIATORROLE = 0x1000, /*
349 * Allow initiator operations on
350 * this controller.
351 */
352 AHC_TARGETROLE = 0x2000, /*
353 * Allow target operations on this
354 * controller.
355 */
356 AHC_NEWEEPROM_FMT = 0x4000,
357 AHC_RESOURCE_SHORTAGE = 0x8000,
358 AHC_TQINFIFO_BLOCKED = 0x10000, /* Blocked waiting for ATIOs */
359 AHC_INT50_SPEEDFLEX = 0x20000, /*
360 * Internal 50pin connector
361 * sits behind an aic3860
362 */
363 AHC_SCB_BTT = 0x40000, /*
364 * The busy targets table is
365 * stored in SCB space rather
366 * than SRAM.
367 */
368 AHC_BIOS_ENABLED = 0x80000,
369 AHC_ALL_INTERRUPTS = 0x100000,
370 AHC_PAGESCBS = 0x400000, /* Enable SCB paging */
371 AHC_EDGE_INTERRUPT = 0x800000, /* Device uses edge triggered ints */
372 AHC_39BIT_ADDRESSING = 0x1000000, /* Use 39 bit addressing scheme. */
373 AHC_LSCBS_ENABLED = 0x2000000, /* 64Byte SCBs enabled */
374 AHC_SCB_CONFIG_USED = 0x4000000, /* No SEEPROM but SCB2 had info. */
375 AHC_NO_BIOS_INIT = 0x8000000, /* No BIOS left over settings. */
376 AHC_DISABLE_PCI_PERR = 0x10000000,
377 AHC_HAS_TERM_LOGIC = 0x20000000,
378 AHC_SHUTDOWN_RECOVERY = 0x40000000 /* Terminate recovery thread. */
379 } ahc_flag;
380
381 /************************* Hardware SCB Definition ***************************/
382
383 /*
384 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB
385 * consists of a "hardware SCB" mirroring the fields available on the card
386 * and additional information the kernel stores for each transaction.
387 *
388 * To minimize space utilization, a portion of the hardware scb stores
389 * different data during different portions of a SCSI transaction.
390 * As initialized by the host driver for the initiator role, this area
391 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After
392 * the cdb has been presented to the target, this area serves to store
393 * residual transfer information and the SCSI status byte.
394 * For the target role, the contents of this area do not change, but
395 * still serve a different purpose than for the initiator role. See
396 * struct target_data for details.
397 */
398
399 /*
400 * Status information embedded in the shared portion of
401 * an SCB after passing the cdb to the target. The kernel
402 * driver will only read this data for transactions that
403 * complete abnormally (non-zero status byte).
404 */
405 struct status_pkt {
406 uint32_t residual_datacnt; /* Residual in the current S/G seg */
407 uint32_t residual_sg_ptr; /* The next S/G for this transfer */
408 uint8_t scsi_status; /* Standard SCSI status byte */
409 };
410
411 /*
412 * Target mode version of the shared data SCB segment.
413 */
414 struct target_data {
415 uint32_t residual_datacnt; /* Residual in the current S/G seg */
416 uint32_t residual_sg_ptr; /* The next S/G for this transfer */
417 uint8_t scsi_status; /* SCSI status to give to initiator */
418 uint8_t target_phases; /* Bitmap of phases to execute */
419 uint8_t data_phase; /* Data-In or Data-Out */
420 uint8_t initiator_tag; /* Initiator's transaction tag */
421 };
422
423 struct hardware_scb {
424 /*0*/ union {
425 /*
426 * If the cdb is 12 bytes or less, we embed it directly
427 * in the SCB. For longer cdbs, we embed the address
428 * of the cdb payload as seen by the chip and a DMA
429 * is used to pull it in.
430 */
431 uint8_t cdb[12];
432 uint32_t cdb_ptr;
433 struct status_pkt status;
434 struct target_data tdata;
435 } shared_data;
436 /*
437 * A word about residuals.
438 * The scb is presented to the sequencer with the dataptr and datacnt
439 * fields initialized to the contents of the first S/G element to
440 * transfer. The sgptr field is initialized to the bus address for
441 * the S/G element that follows the first in the in core S/G array
442 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid
443 * S/G entry for this transfer (single S/G element transfer with the
444 * first elements address and length preloaded in the dataptr/datacnt
445 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL.
446 * The SG_FULL_RESID flag ensures that the residual will be correctly
447 * noted even if no data transfers occur. Once the data phase is entered,
448 * the residual sgptr and datacnt are loaded from the sgptr and the
449 * datacnt fields. After each S/G element's dataptr and length are
450 * loaded into the hardware, the residual sgptr is advanced. After
451 * each S/G element is expired, its datacnt field is checked to see
452 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the
453 * residual sg ptr and the transfer is considered complete. If the
454 * sequencer determines that there is a residual in the transfer, it
455 * will set the SG_RESID_VALID flag in sgptr and DMA the scb back into
456 * host memory. To summarize:
457 *
458 * Sequencer:
459 * o A residual has occurred if SG_FULL_RESID is set in sgptr,
460 * or residual_sgptr does not have SG_LIST_NULL set.
461 *
462 * o We are transfering the last segment if residual_datacnt has
463 * the SG_LAST_SEG flag set.
464 *
465 * Host:
466 * o A residual has occurred if a completed scb has the
467 * SG_RESID_VALID flag set.
468 *
469 * o residual_sgptr and sgptr refer to the "next" sg entry
470 * and so may point beyond the last valid sg entry for the
471 * transfer.
472 */
473 /*12*/ uint32_t dataptr;
474 /*16*/ uint32_t datacnt; /*
475 * Byte 3 (numbered from 0) of
476 * the datacnt is really the
477 * 4th byte in that data address.
478 */
479 /*20*/ uint32_t sgptr;
480 #define SG_PTR_MASK 0xFFFFFFF8
481 /*24*/ uint8_t control; /* See SCB_CONTROL in aic7xxx.reg for details */
482 /*25*/ uint8_t scsiid; /* what to load in the SCSIID register */
483 /*26*/ uint8_t lun;
484 /*27*/ uint8_t tag; /*
485 * Index into our kernel SCB array.
486 * Also used as the tag for tagged I/O
487 */
488 /*28*/ uint8_t cdb_len;
489 /*29*/ uint8_t scsirate; /* Value for SCSIRATE register */
490 /*30*/ uint8_t scsioffset; /* Value for SCSIOFFSET register */
491 /*31*/ uint8_t next; /*
492 * Used for threading SCBs in the
493 * "Waiting for Selection" and
494 * "Disconnected SCB" lists down
495 * in the sequencer.
496 */
497 /*32*/ uint8_t cdb32[32]; /*
498 * CDB storage for cdbs of size
499 * 13->32. We store them here
500 * because hardware scbs are
501 * allocated from DMA safe
502 * memory so we are guaranteed
503 * the controller can access
504 * this data.
505 */
506 };
507
508 /************************ Kernel SCB Definitions ******************************/
509 /*
510 * Some fields of the SCB are OS dependent. Here we collect the
511 * definitions for elements that all OS platforms need to include
512 * in there SCB definition.
513 */
514
515 /*
516 * Definition of a scatter/gather element as transferred to the controller.
517 * The aic7xxx chips only support a 24bit length. We use the top byte of
518 * the length to store additional address bits and a flag to indicate
519 * that a given segment terminates the transfer. This gives us an
520 * addressable range of 512GB on machines with 64bit PCI or with chips
521 * that can support dual address cycles on 32bit PCI busses.
522 */
523 struct ahc_dma_seg {
524 uint32_t addr;
525 uint32_t len;
526 #define AHC_DMA_LAST_SEG 0x80000000
527 #define AHC_SG_HIGH_ADDR_MASK 0x7F000000
528 #define AHC_SG_LEN_MASK 0x00FFFFFF
529 };
530
531 struct sg_map_node {
532 bus_dmamap_t sg_dmamap;
533 bus_addr_t sg_physaddr;
534 bus_dma_segment_t sg_dmasegs;
535 int sg_nseg;
536 struct ahc_dma_seg* sg_vaddr;
537 SLIST_ENTRY(sg_map_node) links;
538 };
539
540 struct ahc_pci_busdata {
541 pci_chipset_tag_t pc;
542 pcitag_t tag;
543 u_int dev;
544 u_int func;
545 pcireg_t class;
546 };
547
548 /*
549 * The current state of this SCB.
550 */
551 typedef enum {
552 SCB_FLAG_NONE = 0x0000,
553 SCB_OTHERTCL_TIMEOUT = 0x0002,/*
554 * Another device was active
555 * during the first timeout for
556 * this SCB so we gave ourselves
557 * an additional timeout period
558 * in case it was hogging the
559 * bus.
560 */
561 SCB_DEVICE_RESET = 0x0004,
562 SCB_SENSE = 0x0008,
563 SCB_CDB32_PTR = 0x0010,
564 SCB_AUTO_NEGOTIATE = 0x0040,/* Negotiate to achieve goal. */
565 SCB_NEGOTIATE = 0x0080,/* Negotiation forced for command. */
566 SCB_ABORT = 0x0100,
567 SCB_UNTAGGEDQ = 0x0200,
568 SCB_ACTIVE = 0x0400,
569 SCB_TARGET_IMMEDIATE = 0x0800,
570 SCB_TRANSMISSION_ERROR = 0x1000,/*
571 * We detected a parity or CRC
572 * error that has effected the
573 * payload of the command. This
574 * flag is checked when normal
575 * status is returned to catch
576 * the case of a target not
577 * responding to our attempt
578 * to report the error.
579 */
580 SCB_TARGET_SCB = 0x2000,
581 SCB_SILENT = 0x4000 /*
582 * Be quiet about transmission type
583 * errors. They are expected and we
584 * don't want to upset the user. This
585 * flag is typically used during DV.
586 */
587 } scb_flag;
588
589 struct scb {
590 struct hardware_scb *hscb;
591 union {
592 SLIST_ENTRY(scb) sle;
593 TAILQ_ENTRY(scb) tqe;
594 } links;
595 LIST_ENTRY(scb) pending_links;
596
597 struct scsipi_xfer *xs;
598 struct ahc_softc *ahc_softc;
599 scb_flag flags;
600 #ifndef __linux__
601 bus_dmamap_t dmamap;
602 #endif
603 struct scb_platform_data *platform_data;
604 struct sg_map_node *sg_map;
605 struct ahc_dma_seg *sg_list;
606 bus_addr_t sg_list_phys;
607 u_int sg_count;/* How full ahc_dma_seg is */
608 };
609
610 struct scb_data {
611 SLIST_HEAD(, scb) free_scbs; /*
612 * Pool of SCBs ready to be assigned
613 * commands to execute.
614 */
615 struct scb *scbindex[256]; /*
616 * Mapping from tag to SCB.
617 * As tag identifiers are an
618 * 8bit value, we provide space
619 * for all possible tag values.
620 * Any lookups to entries at or
621 * above AHC_SCB_MAX_ALLOC will
622 * always fail.
623 */
624 struct hardware_scb *hscbs; /* Array of hardware SCBs */
625 struct scb *scbarray; /* Array of kernel SCBs */
626 struct scsipi_sense_data *sense; /* Per SCB sense data */
627
628 /*
629 * "Bus" addresses of our data structures.
630 */
631 bus_dmamap_t hscb_dmamap;
632 bus_addr_t hscb_busaddr;
633 bus_dma_segment_t hscb_seg;
634 int hscb_nseg;
635 int hscb_size;
636
637 bus_dmamap_t sense_dmamap;
638 bus_addr_t sense_busaddr;
639 bus_dma_segment_t sense_seg;
640 int sense_nseg;
641 int sense_size;
642
643 SLIST_HEAD(, sg_map_node) sg_maps;
644 uint8_t numscbs;
645 uint8_t maxhscbs; /* Number of SCBs on the card */
646 uint8_t init_level; /*
647 * How far we've initialized
648 * this structure.
649 */
650 };
651
652 /************************ Target Mode Definitions *****************************/
653
654 /*
655 * Connection desciptor for select-in requests in target mode.
656 */
657 struct target_cmd {
658 uint8_t scsiid; /* Our ID and the initiator's ID */
659 uint8_t identify; /* Identify message */
660 uint8_t bytes[22]; /*
661 * Bytes contains any additional message
662 * bytes terminated by 0xFF. The remainder
663 * is the cdb to execute.
664 */
665 uint8_t cmd_valid; /*
666 * When a command is complete, the firmware
667 * will set cmd_valid to all bits set.
668 * After the host has seen the command,
669 * the bits are cleared. This allows us
670 * to just peek at host memory to determine
671 * if more work is complete. cmd_valid is on
672 * an 8 byte boundary to simplify setting
673 * it on aic7880 hardware which only has
674 * limited direct access to the DMA FIFO.
675 */
676 uint8_t pad[7];
677 };
678
679 /*
680 * Number of events we can buffer up if we run out
681 * of immediate notify ccbs.
682 */
683 #define AHC_TMODE_EVENT_BUFFER_SIZE 8
684 struct ahc_tmode_event {
685 uint8_t initiator_id;
686 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */
687 #define EVENT_TYPE_BUS_RESET 0xFF
688 uint8_t event_arg;
689 };
690
691 /*
692 * Per enabled lun target mode state.
693 * As this state is directly influenced by the host OS'es target mode
694 * environment, we let the OS module define it. Forward declare the
695 * structure here so we can store arrays of them, etc. in OS neutral
696 * data structures.
697 */
698 #ifdef AHC_TARGET_MODE
699 struct ahc_tmode_lstate {
700 #if 0
701 struct cam_path *path;
702 struct ccb_hdr_slist accept_tios;
703 struct ccb_hdr_slist immed_notifies;
704 #endif
705 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE];
706 uint8_t event_r_idx;
707 uint8_t event_w_idx;
708 };
709 #else
710 struct ahc_tmode_lstate;
711 #endif
712
713 /******************** Transfer Negotiation Datastructures *********************/
714 #define AHC_TRANS_CUR 0x01 /* Modify current negotiation status */
715 #define AHC_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */
716 #define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */
717 #define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */
718
719 #define AHC_WIDTH_UNKNOWN 0xFF
720 #define AHC_PERIOD_UNKNOWN 0xFF
721 #define AHC_OFFSET_UNKNOWN 0xFF
722 #define AHC_PPR_OPTS_UNKNOWN 0xFF
723
724 /*
725 * Transfer Negotiation Information.
726 */
727 struct ahc_transinfo {
728 uint8_t protocol_version; /* SCSI Revision level */
729 uint8_t transport_version; /* SPI Revision level */
730 uint8_t width; /* Bus width */
731 uint8_t period; /* Sync rate factor */
732 uint8_t offset; /* Sync offset */
733 uint8_t ppr_options; /* Parallel Protocol Request options */
734 };
735
736 /*
737 * Per-initiator current, goal and user transfer negotiation information. */
738 struct ahc_initiator_tinfo {
739 uint8_t scsirate; /* Computed value for SCSIRATE reg */
740 struct ahc_transinfo curr;
741 struct ahc_transinfo goal;
742 struct ahc_transinfo user;
743 };
744
745 /*
746 * Per enabled target ID state.
747 * Pointers to lun target state as well as sync/wide negotiation information
748 * for each initiator<->target mapping. For the initiator role we pretend
749 * that we are the target and the targets are the initiators since the
750 * negotiation is the same regardless of role.
751 */
752 struct ahc_tmode_tstate {
753 struct ahc_tmode_lstate* enabled_luns[AHC_NUM_LUNS];
754 struct ahc_initiator_tinfo transinfo[AHC_NUM_TARGETS];
755
756 /*
757 * Per initiator state bitmasks.
758 */
759 uint16_t auto_negotiate;/* Auto Negotiation Required */
760 uint16_t ultraenb; /* Using ultra sync rate */
761 uint16_t discenable; /* Disconnection allowed */
762 uint16_t tagenable; /* Tagged Queuing allowed */
763 };
764
765 /*
766 * Data structure for our table of allowed synchronous transfer rates.
767 */
768 struct ahc_syncrate {
769 u_int sxfr_u2; /* Value of the SXFR parameter for Ultra2+ Chips */
770 u_int sxfr; /* Value of the SXFR parameter for <= Ultra Chips */
771 #define ULTRA_SXFR 0x100 /* Rate Requires Ultra Mode set */
772 #define ST_SXFR 0x010 /* Rate Single Transition Only */
773 #define DT_SXFR 0x040 /* Rate Double Transition Only */
774 uint8_t period; /* Period to send to SCSI target */
775 char *rate;
776 };
777
778 /* Safe and valid period for async negotiations. */
779 #define AHC_ASYNC_XFER_PERIOD 0x45
780 #define AHC_ULTRA2_XFER_PERIOD 0x0a
781
782 /*
783 * Indexes into our table of syncronous transfer rates.
784 */
785 #define AHC_SYNCRATE_DT 0
786 #define AHC_SYNCRATE_ULTRA2 1
787 #define AHC_SYNCRATE_ULTRA 3
788 #define AHC_SYNCRATE_FAST 6
789 #define AHC_SYNCRATE_MAX AHC_SYNCRATE_DT
790 #define AHC_SYNCRATE_MIN 13
791
792 /***************************** Lookup Tables **********************************/
793 /*
794 * Phase -> name and message out response
795 * to parity errors in each phase table.
796 */
797 struct ahc_phase_table_entry {
798 uint8_t phase;
799 uint8_t mesg_out; /* Message response to parity errors */
800 char *phasemsg;
801 };
802
803 /************************** Serial EEPROM Format ******************************/
804
805 struct seeprom_config {
806 /*
807 * Per SCSI ID Configuration Flags
808 */
809 uint16_t device_flags[16]; /* words 0-15 */
810 #define CFXFER 0x0007 /* synchronous transfer rate */
811 #define CFSYNCH 0x0008 /* enable synchronous transfer */
812 #define CFDISC 0x0010 /* enable disconnection */
813 #define CFWIDEB 0x0020 /* wide bus device */
814 #define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/
815 #define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */
816 #define CFSTART 0x0100 /* send start unit SCSI command */
817 #define CFINCBIOS 0x0200 /* include in BIOS scan */
818 #define CFRNFOUND 0x0400 /* report even if not found */
819 #define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */
820 #define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */
821 #define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */
822
823 /*
824 * BIOS Control Bits
825 */
826 uint16_t bios_control; /* word 16 */
827 #define CFSUPREM 0x0001 /* support all removable drives */
828 #define CFSUPREMB 0x0002 /* support removable boot drives */
829 #define CFBIOSEN 0x0004 /* BIOS enabled */
830 #define CFBIOS_BUSSCAN 0x0008 /* Have the BIOS Scan the Bus */
831 #define CFSM2DRV 0x0010 /* support more than two drives */
832 #define CFSTPWLEVEL 0x0010 /* Termination level control */
833 #define CF284XEXTEND 0x0020 /* extended translation (284x cards) */
834 #define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */
835 #define CFTERM_MENU 0x0040 /* BIOS displays termination menu */
836 #define CFEXTEND 0x0080 /* extended translation enabled */
837 #define CFSCAMEN 0x0100 /* SCAM enable */
838 #define CFMSG_LEVEL 0x0600 /* BIOS Message Level */
839 #define CFMSG_VERBOSE 0x0000
840 #define CFMSG_SILENT 0x0200
841 #define CFMSG_DIAG 0x0400
842 #define CFBOOTCD 0x0800 /* Support Bootable CD-ROM */
843 /* UNUSED 0xff00 */
844
845 /*
846 * Host Adapter Control Bits
847 */
848 uint16_t adapter_control; /* word 17 */
849 #define CFAUTOTERM 0x0001 /* Perform Auto termination */
850 #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */
851 #define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */
852 #define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */
853 #define CFSTERM 0x0004 /* SCSI low byte termination */
854 #define CFWSTERM 0x0008 /* SCSI high byte termination */
855 #define CFSPARITY 0x0010 /* SCSI parity */
856 #define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */
857 #define CFMULTILUN 0x0020
858 #define CFRESETB 0x0040 /* reset SCSI bus at boot */
859 #define CFCLUSTERENB 0x0080 /* Cluster Enable */
860 #define CFBOOTCHAN 0x0300 /* probe this channel first */
861 #define CFBOOTCHANSHIFT 8
862 #define CFSEAUTOTERM 0x0400 /* Ultra2 Perform secondary Auto Term*/
863 #define CFSELOWTERM 0x0800 /* Ultra2 secondary low term */
864 #define CFSEHIGHTERM 0x1000 /* Ultra2 secondary high term */
865 #define CFENABLEDV 0x4000 /* Perform Domain Validation*/
866
867 /*
868 * Bus Release Time, Host Adapter ID
869 */
870 uint16_t brtime_id; /* word 18 */
871 #define CFSCSIID 0x000f /* host adapter SCSI ID */
872 /* UNUSED 0x00f0 */
873 #define CFBRTIME 0xff00 /* bus release time */
874
875 /*
876 * Maximum targets
877 */
878 uint16_t max_targets; /* word 19 */
879 #define CFMAXTARG 0x00ff /* maximum targets */
880 #define CFBOOTLUN 0x0f00 /* Lun to boot from */
881 #define CFBOOTID 0xf000 /* Target to boot from */
882 uint16_t res_1[10]; /* words 20-29 */
883 uint16_t signature; /* Signature == 0x250 */
884 #define CFSIGNATURE 0x250
885 #define CFSIGNATURE2 0x300
886 uint16_t checksum; /* word 31 */
887 };
888
889 /**************************** Message Buffer *********************************/
890 typedef enum {
891 MSG_TYPE_NONE = 0x00,
892 MSG_TYPE_INITIATOR_MSGOUT = 0x01,
893 MSG_TYPE_INITIATOR_MSGIN = 0x02,
894 MSG_TYPE_TARGET_MSGOUT = 0x03,
895 MSG_TYPE_TARGET_MSGIN = 0x04
896 } ahc_msg_type;
897
898 typedef enum {
899 MSGLOOP_IN_PROG,
900 MSGLOOP_MSGCOMPLETE,
901 MSGLOOP_TERMINATED
902 } msg_loop_stat;
903
904 /*********************** Software Configuration Structure *********************/
905 TAILQ_HEAD(scb_tailq, scb);
906
907 struct ahc_aic7770_softc {
908 /*
909 * Saved register state used for chip_init().
910 */
911 uint8_t busspd;
912 uint8_t bustime;
913 };
914
915 struct ahc_pci_softc {
916 /*
917 * Saved register state used for chip_init().
918 */
919 uint32_t devconfig;
920 uint16_t targcrccnt;
921 uint8_t command;
922 uint8_t csize_lattime;
923 uint8_t optionmode;
924 uint8_t crccontrol1;
925 uint8_t dscommand0;
926 uint8_t dspcistatus;
927 uint8_t scbbaddr;
928 uint8_t dff_thrsh;
929 };
930
931 union ahc_bus_softc {
932 struct ahc_aic7770_softc aic7770_softc;
933 struct ahc_pci_softc pci_softc;
934 };
935
936 typedef void (*ahc_bus_intr_t)(struct ahc_softc *);
937 typedef int (*ahc_bus_chip_init_t)(struct ahc_softc *);
938 typedef void ahc_callback_t (void *);
939
940 struct ahc_softc {
941 struct device sc_dev;
942
943 struct scsipi_channel sc_channel;
944 struct scsipi_channel sc_channel_b;
945 struct device * sc_child;
946 struct device * sc_child_b;
947 struct scsipi_adapter sc_adapter;
948
949 bus_space_tag_t tag;
950 bus_space_handle_t bsh;
951
952 #ifndef __linux__
953 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */
954 #endif
955 struct scb_data *scb_data;
956
957 struct scb *next_queued_scb;
958
959 /*
960 * SCBs that have been sent to the controller
961 */
962 LIST_HEAD(, scb) pending_scbs;
963
964 /*
965 * Counting lock for deferring the release of additional
966 * untagged transactions from the untagged_queues. When
967 * the lock is decremented to 0, all queues in the
968 * untagged_queues array are run.
969 */
970 u_int untagged_queue_lock;
971
972 /*
973 * Per-target queue of untagged-transactions. The
974 * transaction at the head of the queue is the
975 * currently pending untagged transaction for the
976 * target. The driver only allows a single untagged
977 * transaction per target.
978 */
979 struct scb_tailq untagged_queues[AHC_NUM_TARGETS];
980
981 /*
982 * Bus attachment specific data.
983 */
984 union ahc_bus_softc bus_softc;
985
986 /*
987 * Platform specific data.
988 */
989 struct ahc_platform_data *platform_data;
990
991 /*
992 * Platform specific device information.
993 */
994 ahc_dev_softc_t dev_softc;
995
996 /*
997 * Bus specific device information.
998 */
999 ahc_bus_intr_t bus_intr;
1000
1001 /*
1002 * Bus specific initialization required
1003 * after a chip reset.
1004 */
1005 ahc_bus_chip_init_t bus_chip_init;
1006
1007 /*
1008 * Target mode related state kept on a per enabled lun basis.
1009 * Targets that are not enabled will have null entries.
1010 * As an initiator, we keep one target entry for our initiator
1011 * ID to store our sync/wide transfer settings.
1012 */
1013 struct ahc_tmode_tstate *enabled_targets[AHC_NUM_TARGETS];
1014
1015 char inited_target[AHC_NUM_TARGETS];
1016
1017 /*
1018 * The black hole device responsible for handling requests for
1019 * disabled luns on enabled targets.
1020 */
1021 struct ahc_tmode_lstate *black_hole;
1022
1023 /*
1024 * Device instance currently on the bus awaiting a continue TIO
1025 * for a command that was not given the disconnect privilege.
1026 */
1027 struct ahc_tmode_lstate *pending_device;
1028
1029 /*
1030 * Card characteristics
1031 */
1032 ahc_chip chip;
1033 ahc_feature features;
1034 ahc_bug bugs;
1035 ahc_flag flags;
1036 struct seeprom_config *seep_config;
1037
1038 /* Values to store in the SEQCTL register for pause and unpause */
1039 uint8_t unpause;
1040 uint8_t pause;
1041
1042 /* Command Queues */
1043 uint8_t qoutfifonext;
1044 uint8_t qinfifonext;
1045 uint8_t *qoutfifo;
1046 uint8_t *qinfifo;
1047
1048 /* Critical Section Data */
1049 struct cs *critical_sections;
1050 u_int num_critical_sections;
1051
1052 /* Links for chaining softcs */
1053 TAILQ_ENTRY(ahc_softc) links;
1054
1055 /* Channel Names ('A', 'B', etc.) */
1056 char channel;
1057 char channel_b;
1058
1059 /* Initiator Bus ID */
1060 uint8_t our_id;
1061 uint8_t our_id_b;
1062
1063 /*
1064 * PCI error detection.
1065 */
1066 int unsolicited_ints;
1067
1068 /*
1069 * Target incoming command FIFO.
1070 */
1071 struct target_cmd *targetcmds;
1072 uint8_t tqinfifonext;
1073
1074 /*
1075 * Cached copy of the sequencer control register.
1076 */
1077 uint8_t seqctl;
1078
1079 /*
1080 * Incoming and outgoing message handling.
1081 */
1082 uint8_t send_msg_perror;
1083 ahc_msg_type msg_type;
1084 uint8_t msgout_buf[12];/* Message we are sending */
1085 uint8_t msgin_buf[12];/* Message we are receiving */
1086 u_int msgout_len; /* Length of message to send */
1087 u_int msgout_index; /* Current index in msgout */
1088 u_int msgin_index; /* Current index in msgin */
1089
1090 /* Interrupt routine */
1091 void *ih;
1092
1093 /*
1094 * Mapping information for data structures shared
1095 * between the sequencer and kernel.
1096 */
1097 bus_dma_tag_t parent_dmat;
1098 bus_dmamap_t shared_data_dmamap;
1099 bus_addr_t shared_data_busaddr;
1100
1101 bus_dma_segment_t shared_data_seg;
1102 int shared_data_nseg;
1103 int shared_data_size;
1104 int sc_dmaflags;
1105
1106 /*
1107 * Bus address of the one byte buffer used to
1108 * work-around a DMA bug for chips <= aic7880
1109 * in target mode.
1110 */
1111 bus_addr_t dma_bug_buf;
1112
1113 /* Number of enabled target mode device on this card */
1114 u_int enabled_luns;
1115
1116 /* Initialization level of this data structure */
1117 u_int init_level;
1118
1119 /* PCI cacheline size. */
1120 u_int pci_cachesize;
1121
1122 /*
1123 * Count of parity errors we have seen as a target.
1124 * We auto-disable parity error checking after seeing
1125 * AHC_PCI_TARGET_PERR_THRESH number of errors.
1126 */
1127 u_int pci_target_perr_count;
1128 #define AHC_PCI_TARGET_PERR_THRESH 10
1129
1130 /* Maximum number of sequencer instructions supported. */
1131 u_int instruction_ram_size;
1132
1133 /* Per-Unit descriptive information */
1134 char *name;
1135 int unit;
1136
1137 /* Selection Timer settings */
1138 int seltime;
1139 int seltime_b;
1140
1141 uint16_t user_discenable;/* Disconnection allowed */
1142 uint16_t user_tagenable;/* Tagged Queuing allowed */
1143
1144 struct ahc_pci_busdata *bd;
1145
1146 void *shutdown_hook;
1147 };
1148
1149 TAILQ_HEAD(ahc_softc_tailq, ahc_softc);
1150 extern struct ahc_softc_tailq ahc_tailq;
1151
1152 /************************ Active Device Information ***************************/
1153 typedef enum {
1154 ROLE_UNKNOWN,
1155 ROLE_INITIATOR,
1156 ROLE_TARGET
1157 } role_t;
1158
1159 struct ahc_devinfo {
1160 int our_scsiid;
1161 int target_offset;
1162 uint16_t target_mask;
1163 u_int target;
1164 u_int lun;
1165 char channel;
1166 role_t role; /*
1167 * Only guaranteed to be correct if not
1168 * in the busfree state.
1169 */
1170 };
1171
1172 /****************************** PCI Structures ********************************/
1173 typedef int (ahc_device_setup_t)(struct ahc_softc *);
1174
1175 struct ahc_pci_identity {
1176 uint64_t full_id;
1177 uint64_t id_mask;
1178 ahc_device_setup_t *setup;
1179 };
1180 extern struct ahc_pci_identity ahc_pci_ident_table[];
1181
1182 /***************************** VL/EISA Declarations ***************************/
1183 struct aic7770_identity {
1184 uint32_t full_id;
1185 uint32_t id_mask;
1186 const char *name;
1187 ahc_device_setup_t *setup;
1188 };
1189 extern struct aic7770_identity aic7770_ident_table[];
1190 extern const int ahc_num_aic7770_devs;
1191
1192 #define AHC_EISA_SLOT_OFFSET 0xc00
1193 #define AHC_EISA_IOSIZE 0x100
1194
1195 /*************************** Function Declarations ****************************/
1196 /******************************************************************************/
1197 u_int ahc_index_busy_tcl(struct ahc_softc *, u_int);
1198 void ahc_unbusy_tcl(struct ahc_softc *, u_int);
1199 void ahc_busy_tcl(struct ahc_softc *, u_int, u_int);
1200
1201 /***************************** PCI Front End *********************************/
1202 const struct ahc_pci_identity *ahc_find_pci_device(pcireg_t, pcireg_t, u_int);
1203 int ahc_pci_config(struct ahc_softc *,
1204 struct ahc_pci_identity *);
1205 int ahc_pci_test_register_access(struct ahc_softc *);
1206
1207 /*************************** EISA/VL Front End ********************************/
1208 struct aic7770_identity *aic7770_find_device(uint32_t);
1209 int aic7770_config(struct ahc_softc *,
1210 struct aic7770_identity *, u_int);
1211
1212 /************************** SCB and SCB queue management **********************/
1213 int ahc_probe_scbs(struct ahc_softc *);
1214 void ahc_run_untagged_queues(struct ahc_softc *ahc);
1215 void ahc_run_untagged_queue(struct ahc_softc *ahc,
1216 struct scb_tailq *queue);
1217 void ahc_qinfifo_requeue_tail(struct ahc_softc *ahc,
1218 struct scb *scb);
1219 int ahc_match_scb(struct ahc_softc *ahc, struct scb *scb,
1220 int target, char channel, int lun,
1221 u_int tag, role_t role);
1222
1223 /****************************** Initialization ********************************/
1224 int ahc_softc_init(struct ahc_softc *);
1225 #ifndef DEBUG
1226 void ahc_controller_info(struct ahc_softc *, char *, size_t);
1227 #endif
1228 int ahc_chip_init(struct ahc_softc *ahc);
1229 int ahc_init(struct ahc_softc *ahc);
1230 void ahc_intr_enable(struct ahc_softc *ahc, int enable);
1231 void ahc_softc_insert(struct ahc_softc *);
1232 void ahc_set_unit(struct ahc_softc *, int);
1233 void ahc_set_name(struct ahc_softc *, char *);
1234 void ahc_alloc_scbs(struct ahc_softc *ahc);
1235 void ahc_free(struct ahc_softc *ahc);
1236 int ahc_reset(struct ahc_softc *ahc, int reinit);
1237 void ahc_shutdown(void *arg);
1238
1239 /*************************** Interrupt Services *******************************/
1240 void ahc_pci_intr(struct ahc_softc *);
1241 void ahc_clear_intstat(struct ahc_softc *);
1242 void ahc_run_qoutfifo(struct ahc_softc *);
1243 #ifdef AHC_TARGET_MODE
1244 void ahc_run_tqinfifo(struct ahc_softc *ahc, int paused);
1245 #endif
1246 void ahc_handle_brkadrint(struct ahc_softc *ahc);
1247 void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat);
1248 void ahc_handle_scsiint(struct ahc_softc *ahc,
1249 u_int intstat);
1250 void ahc_clear_critical_section(struct ahc_softc *ahc);
1251
1252 /***************************** Error Recovery *********************************/
1253 typedef enum {
1254 SEARCH_COMPLETE,
1255 SEARCH_COUNT,
1256 SEARCH_REMOVE
1257 } ahc_search_action;
1258 int ahc_search_qinfifo(struct ahc_softc *, int, char,
1259 int, u_int, role_t, uint32_t, ahc_search_action);
1260 int ahc_search_untagged_queues(struct ahc_softc *,
1261 struct scsipi_xfer *, int, char, int, uint32_t,
1262 ahc_search_action);
1263 int ahc_search_disc_list(struct ahc_softc *, int, char,
1264 int, u_int, int, int, int);
1265 void ahc_freeze_devq(struct ahc_softc *, struct scb *);
1266 int ahc_reset_channel(struct ahc_softc *, char, int);
1267 int ahc_abort_scbs(struct ahc_softc *, int, char, int,
1268 u_int, role_t, uint32_t);
1269 void ahc_restart(struct ahc_softc *);
1270 void ahc_calc_residual(struct ahc_softc *, struct scb *);
1271 /*************************** Utility Functions ********************************/
1272 struct ahc_phase_table_entry*
1273 ahc_lookup_phase_entry(int phase);
1274 void ahc_compile_devinfo(struct ahc_devinfo *devinfo,
1275 u_int our_id, u_int target,
1276 u_int lun, char channel,
1277 role_t role);
1278 /************************** Transfer Negotiation ******************************/
1279 struct ahc_syncrate* ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
1280 u_int *ppr_options, u_int maxsync);
1281 u_int ahc_find_period(struct ahc_softc *ahc,
1282 u_int scsirate, u_int maxsync);
1283 void ahc_validate_offset(struct ahc_softc *ahc,
1284 struct ahc_initiator_tinfo *tinfo,
1285 struct ahc_syncrate *syncrate,
1286 u_int *offset, int wide,
1287 role_t role);
1288 void ahc_validate_width(struct ahc_softc *ahc,
1289 struct ahc_initiator_tinfo *tinfo,
1290 u_int *bus_width,
1291 role_t role);
1292 /*
1293 * Negotiation types. These are used to qualify if we should renegotiate
1294 * even if our goal and current transport parameters are identical.
1295 */
1296 typedef enum {
1297 AHC_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */
1298 AHC_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */
1299 AHC_NEG_ALWAYS /* Renegotiate even if goal is async. */
1300 } ahc_neg_type;
1301 int ahc_update_neg_request(struct ahc_softc *,
1302 struct ahc_devinfo *, struct ahc_tmode_tstate *,
1303 struct ahc_initiator_tinfo*, ahc_neg_type);
1304 void ahc_set_width(struct ahc_softc *, struct ahc_devinfo *,
1305 u_int, u_int, int);
1306 void ahc_set_syncrate(struct ahc_softc *,
1307 struct ahc_devinfo *, struct ahc_syncrate *,
1308 u_int, u_int, u_int, u_int, int);
1309 void ahc_scb_devinfo(struct ahc_softc *,
1310 struct ahc_devinfo *, struct scb *);
1311
1312
1313 typedef enum {
1314 AHC_QUEUE_NONE,
1315 AHC_QUEUE_BASIC,
1316 AHC_QUEUE_TAGGED
1317 } ahc_queue_alg;
1318
1319 void ahc_set_tags(struct ahc_softc *ahc,
1320 struct ahc_devinfo *devinfo,
1321 ahc_queue_alg alg);
1322
1323 /**************************** Target Mode *************************************/
1324 #ifdef AHC_TARGET_MODE
1325 void ahc_send_lstate_events(struct ahc_softc *,
1326 struct ahc_tmode_lstate *);
1327 void ahc_handle_en_lun(struct ahc_softc *, struct scsipi_xfer *);
1328 cam_status ahc_find_tmode_devs(struct ahc_softc *,
1329 struct ahc_tmode_tstate **, struct ahc_tmode_lstate **,
1330 int);
1331 #ifndef AHC_TMODE_ENABLE
1332 #define AHC_TMODE_ENABLE 0
1333 #endif
1334 #endif
1335 /******************************* Debug ***************************************/
1336 #ifdef AHC_DEBUG
1337 extern uint32_t ahc_debug;
1338 #define AHC_SHOW_MISC 0x0001
1339 #define AHC_SHOW_SENSE 0x0002
1340 #define AHC_DUMP_SEEPROM 0x0004
1341 #define AHC_SHOW_TERMCTL 0x0008
1342 #define AHC_SHOW_MEMORY 0x0010
1343 #define AHC_SHOW_MESSAGES 0x0020
1344 #define AHC_SHOW_DV 0x0040
1345 #define AHC_SHOW_SELTO 0x0080
1346 #define AHC_SHOW_QFULL 0x0200
1347 #define AHC_SHOW_QUEUE 0x0400
1348 #define AHC_SHOW_TQIN 0x0800
1349 #define AHC_SHOW_MASKED_ERRORS 0x1000
1350 #define AHC_DEBUG_SEQUENCER 0x2000
1351 #endif
1352 void ahc_print_scb(struct scb *scb);
1353 void ahc_print_devinfo(struct ahc_softc *ahc,
1354 struct ahc_devinfo *dev);
1355 void ahc_dump_card_state(struct ahc_softc *ahc);
1356 int ahc_print_register(ahc_reg_parse_entry_t *table,
1357 u_int num_entries,
1358 const char *name,
1359 u_int address,
1360 u_int value,
1361 u_int *cur_column,
1362 u_int wrap_point);
1363 /******************************* SEEPROM *************************************/
1364 int ahc_acquire_seeprom(struct ahc_softc *ahc,
1365 struct seeprom_descriptor *sd);
1366 void ahc_release_seeprom(struct seeprom_descriptor *sd);
1367
1368 void ahc_check_extport(struct ahc_softc *, u_int *);
1369 #endif /* _AIC7XXXVAR_H_ */