root/dev/ic/aic7xxx.c

DEFINITIONS

1. AHCMSG_1B
2. AHCMSG_2B
3. AHCMSG_EXT
4. ahc_msgtype
5. ahc_restart
6. ahc_run_qoutfifo
7. ahc_run_untagged_queues
8. ahc_run_untagged_queue
9. ahc_handle_brkadrint
10. ahc_handle_seqint
11. ahc_handle_scsiint
12. ahc_force_renegotiation
13. ahc_clear_critical_section
14. ahc_clear_intstat
15. ahc_print_scb
16. ahc_alloc_tstate
17. ahc_free_tstate
18. ahc_devlimited_syncrate
19. ahc_find_syncrate
20. ahc_find_period
21. ahc_validate_offset
22. ahc_validate_width
23. ahc_update_neg_request
24. ahc_set_syncrate
25. ahc_set_width
26. ahc_set_tags
27. ahc_update_pending_scbs
28. ahc_fetch_devinfo
29. ahc_lookup_phase_entry
30. ahc_compile_devinfo
31. ahc_print_devinfo
32. ahc_scb_devinfo
33. ahc_assert_atn
34. ahc_setup_initiator_msgout
35. ahc_build_transfer_msg
36. ahc_construct_sdtr
37. ahc_construct_wdtr
38. ahc_construct_ppr
39. ahc_clear_msg_state
40. ahc_handle_proto_violation
41. ahc_handle_message_phase
42. ahc_sent_msg
43. ahc_parse_msg
44. ahc_handle_msg_reject
45. ahc_handle_ign_wide_residue
46. ahc_reinitialize_dataptrs
47. ahc_handle_devreset
48. ahc_setup_target_msgin
49. ahc_softc_init
50. ahc_softc_insert
51. ahc_set_unit
52. ahc_set_name
53. ahc_free
54. ahc_shutdown
55. ahc_reset
56. ahc_probe_scbs
57. ahc_dmamap_cb
58. ahc_build_free_scb_list
59. ahc_init_scbdata
60. ahc_fini_scbdata
61. ahc_alloc_scbs
62. ahc_controller_info
63. ahc_chip_init
64. ahc_init
65. ahc_intr_enable
66. ahc_index_busy_tcl
67. ahc_unbusy_tcl
68. ahc_busy_tcl
69. ahc_match_scb
70. ahc_freeze_devq
71. ahc_qinfifo_requeue_tail
72. ahc_qinfifo_requeue
73. ahc_qinfifo_count
74. ahc_search_qinfifo
75. ahc_search_untagged_queues
76. ahc_search_disc_list
77. ahc_rem_scb_from_disc_list
78. ahc_add_curscb_to_free_list
79. ahc_rem_wscb
80. ahc_abort_scbs
81. ahc_reset_current_bus
82. ahc_reset_channel
83. ahc_calc_residual
84. ahc_queue_lstate_event
85. ahc_send_lstate_events
86. ahc_dumpseq
87. ahc_loadseq
88. ahc_check_patch
89. ahc_download_instr
90. ahc_print_register
91. ahc_dump_card_state
92. ahc_find_tmode_devs
93. ahc_handle_en_lun
94. ahc_update_scsiid
95. ahc_run_tqinfifo
96. ahc_handle_target_cmd
97. ahc_createdmamem
98. ahc_freedmamem

    1 /*      $OpenBSD: aic7xxx.c,v 1.76 2007/05/26 21:53:16 krw Exp $        */
    2 /*      $NetBSD: aic7xxx.c,v 1.108 2003/11/02 11:07:44 wiz Exp $        */
    4 /*
    5  * Core routines and tables shareable across OS platforms.
    6  *
    7  * Copyright (c) 1994-2002 Justin T. Gibbs.
    8  * Copyright (c) 2000-2002 Adaptec Inc.
    9  * All rights reserved.
   10  *
   11  * Redistribution and use in source and binary forms, with or without
   12  * modification, are permitted provided that the following conditions
   13  * are met:
   14  * 1. Redistributions of source code must retain the above copyright
   15  *    notice, this list of conditions, and the following disclaimer,
   16  *    without modification.
   17  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
   18  *    substantially similar to the "NO WARRANTY" disclaimer below
   19  *    ("Disclaimer") and any redistribution must be conditioned upon
   20  *    including a substantially similar Disclaimer requirement for further
   21  *    binary redistribution.
   22  * 3. Neither the names of the above-listed copyright holders nor the names
   23  *    of any contributors may be used to endorse or promote products derived
   24  *    from this software without specific prior written permission.
   25  *
   26  * Alternatively, this software may be distributed under the terms of the
   27  * GNU General Public License ("GPL") version 2 as published by the Free
   28  * Software Foundation.
   29  *
   30  * NO WARRANTY
   31  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
   32  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
   33  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
   34  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
   35  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   36  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   37  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   38  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
   39  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
   40  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   41  * POSSIBILITY OF SUCH DAMAGES.
   42  *
   43  * $Id: aic7xxx.c,v 1.76 2007/05/26 21:53:16 krw Exp $
   44  */
   45 /*
   46  * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003
   47  */
   49 #include <sys/cdefs.h>
   50 /* __FBSDID("$FreeBSD: src/sys/dev/aic7xxx/aic7xxx.c,v 1.100 2004/05/11 20:39:46 gibbs Exp $"); */
   52 #include <dev/ic/aic7xxx_openbsd.h>
   53 #ifdef SMALL_KERNEL
   54 #define IO_EXPAND
   55 #endif
   56 #include <dev/ic/aic7xxx_inline.h>
   57 #include <dev/microcode/aic7xxx/aicasm_insformat.h>
   59 /****************************** Softc Data ************************************/
   60 struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq);
   62 /***************************** Lookup Tables **********************************/
   63 char *ahc_chip_names[] =
   64 {
   65         "NONE",
   66         "aic7770",
   67         "aic7850",
   68         "aic7855",
   69         "aic7859",
   70         "aic7860",
   71         "aic7870",
   72         "aic7880",
   73         "aic7895",
   74         "aic7895C",
   75         "aic7890/91",
   76         "aic7896/97",
   77         "aic7892",
   78         "aic7899"
   79 };
   81 /*
   82  * Hardware error codes.
   83  */
   84 struct ahc_hard_error_entry {
uint8_t errno;
   86         char *errmesg;
   87 };
   89 #if !defined(SMALL_KERNEL)
   90 static struct ahc_hard_error_entry ahc_hard_errors[] = {
   91         { ILLHADDR,     "Illegal Host Access" },
   92         { ILLSADDR,     "Illegal Sequencer Address referrenced" },
   93         { ILLOPCODE,    "Illegal Opcode in sequencer program" },
   94         { SQPARERR,     "Sequencer Parity Error" },
   95         { DPARERR,      "Data-path Parity Error" },
   96         { MPARERR,      "Scratch or SCB Memory Parity Error" },
   97         { PCIERRSTAT,   "PCI Error detected" },
   98         { CIOPARERR,    "CIOBUS Parity Error" },
   99 };
  100 static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors);
  101 #endif /* !defined(SMALL_KERNEL) */
  103 static struct ahc_phase_table_entry ahc_phase_table[] =
  104 {
  105         { P_DATAOUT,    MSG_NOOP,               "in Data-out phase"     },
  106         { P_DATAIN,     MSG_INITIATOR_DET_ERR,  "in Data-in phase"      },
  107         { P_DATAOUT_DT, MSG_NOOP,               "in DT Data-out phase"  },
  108         { P_DATAIN_DT,  MSG_INITIATOR_DET_ERR,  "in DT Data-in phase"   },
  109         { P_COMMAND,    MSG_NOOP,               "in Command phase"      },
  110         { P_MESGOUT,    MSG_NOOP,               "in Message-out phase"  },
  111         { P_STATUS,     MSG_INITIATOR_DET_ERR,  "in Status phase"       },
  112         { P_MESGIN,     MSG_PARITY_ERROR,       "in Message-in phase"   },
  113         { P_BUSFREE,    MSG_NOOP,               "while idle"            },
  114         { 0,            MSG_NOOP,               "in unknown phase"      }
  115 };
  117 /*
  118  * In most cases we only wish to itterate over real phases, so
  119  * exclude the last element from the count.
  120  */
  121 static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1;
  123 /*
  124  * Valid SCSIRATE values.  (p. 3-17)
  125  * Provides a mapping of transfer periods in ns to the proper value to
  126  * stick in the scsixfer reg.
  127  */
  128 static struct ahc_syncrate ahc_syncrates[] =
  129 {
  130       /* ultra2    fast/ultra  period     rate */
  131         { 0x42,      0x000,      9,      "80.0" },
  132         { 0x03,      0x000,     10,      "40.0" },
  133         { 0x04,      0x000,     11,      "33.0" },
  134         { 0x05,      0x100,     12,      "20.0" },
  135         { 0x06,      0x110,     15,      "16.0" },
  136         { 0x07,      0x120,     18,      "13.4" },
  137         { 0x08,      0x000,     25,      "10.0" },
  138         { 0x19,      0x010,     31,      "8.0"  },
  139         { 0x1a,      0x020,     37,      "6.67" },
  140         { 0x1b,      0x030,     43,      "5.7"  },
  141         { 0x1c,      0x040,     50,      "5.0"  },
  142         { 0x00,      0x050,     56,      "4.4"  },
  143         { 0x00,      0x060,     62,      "4.0"  },
  144         { 0x00,      0x070,     68,      "3.6"  },
  145         { 0x00,      0x000,      0,      NULL   }
  146 };
  148 /* Our Sequencer Program */
  149 #include <dev/microcode/aic7xxx/aic7xxx_seq.h>
  151 /**************************** Function Declarations ***************************/
  152 static void             ahc_force_renegotiation(struct ahc_softc *ahc,
  153                                                 struct ahc_devinfo *devinfo);
  154 static struct ahc_tmode_tstate*
ahc_alloc_tstate(struct ahc_softc *ahc,
u_int scsi_id, char channel);
  157 #ifdef AHC_TARGET_MODE
  158 static void             ahc_free_tstate(struct ahc_softc *ahc,
u_int scsi_id, char channel, int force);
  160 #endif
  161 static struct ahc_syncrate*
ahc_devlimited_syncrate(struct ahc_softc *ahc,
  163                                                 struct ahc_initiator_tinfo *,
u_int *period,
u_int *ppr_options,
role_t role);
  167 static void             ahc_update_pending_scbs(struct ahc_softc *ahc);
  168 static void             ahc_fetch_devinfo(struct ahc_softc *ahc,
  169                                           struct ahc_devinfo *devinfo);
  170 static void             ahc_assert_atn(struct ahc_softc *ahc);
  171 static void             ahc_setup_initiator_msgout(struct ahc_softc *ahc,
  172                                                    struct ahc_devinfo *devinfo,
  173                                                    struct scb *scb);
  174 static void             ahc_build_transfer_msg(struct ahc_softc *ahc,
  175                                                struct ahc_devinfo *devinfo);
  176 static void             ahc_construct_sdtr(struct ahc_softc *ahc,
  177                                            struct ahc_devinfo *devinfo,
u_int period, u_int offset);
  179 static void             ahc_construct_wdtr(struct ahc_softc *ahc,
  180                                            struct ahc_devinfo *devinfo,
u_int bus_width);
  182 static void             ahc_construct_ppr(struct ahc_softc *ahc,
  183                                           struct ahc_devinfo *devinfo,
u_int period, u_int offset,
u_int bus_width, u_int ppr_options);
  186 static void             ahc_clear_msg_state(struct ahc_softc *ahc);
  187 static void             ahc_handle_proto_violation(struct ahc_softc *ahc);
  188 static void             ahc_handle_message_phase(struct ahc_softc *ahc);
  189 typedef enum {
AHCMSG_1B,
  191         AHCMSG_2B,
AHCMSG_EXT
  193 } ahc_msgtype;
  194 static int              ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type,
u_int msgval, int full);
  196 static int              ahc_parse_msg(struct ahc_softc *ahc,
  197                                       struct ahc_devinfo *devinfo);
  198 static int              ahc_handle_msg_reject(struct ahc_softc *ahc,
  199                                               struct ahc_devinfo *devinfo);
  200 static void             ahc_handle_ign_wide_residue(struct ahc_softc *ahc,
  201                                                 struct ahc_devinfo *devinfo);
  202 static void             ahc_reinitialize_dataptrs(struct ahc_softc *ahc);
  203 static void             ahc_handle_devreset(struct ahc_softc *ahc,
  204                                             struct ahc_devinfo *devinfo,
cam_status status, char *message,
  206                                             int verbose_level);
  207 #ifdef AHC_TARGET_MODE
  208 static void             ahc_setup_target_msgin(struct ahc_softc *ahc,
  209                                                struct ahc_devinfo *devinfo,
  210                                                struct scb *scb);
  211 #endif
  213 //static bus_dmamap_callback_t  ahc_dmamap_cb; 
  214 static void                     ahc_build_free_scb_list(struct ahc_softc *ahc);
  215 static int                      ahc_init_scbdata(struct ahc_softc *ahc);
  216 static void                     ahc_fini_scbdata(struct ahc_softc *ahc);
  217 static void             ahc_qinfifo_requeue(struct ahc_softc *ahc,
  218                                             struct scb *prev_scb,
  219                                             struct scb *scb);
  220 static int              ahc_qinfifo_count(struct ahc_softc *ahc);
  221 static u_int            ahc_rem_scb_from_disc_list(struct ahc_softc *ahc,
u_int prev, u_int scbptr);
  223 static void             ahc_add_curscb_to_free_list(struct ahc_softc *ahc);
  224 static u_int            ahc_rem_wscb(struct ahc_softc *ahc,
u_int scbpos, u_int prev);
  226 static void             ahc_reset_current_bus(struct ahc_softc *ahc);
  227 #ifdef AHC_DUMP_SEQ
  228 static void             ahc_dumpseq(struct ahc_softc *ahc);
  229 #endif
  230 static int              ahc_loadseq(struct ahc_softc *ahc);
  231 static int              ahc_check_patch(struct ahc_softc *ahc,
  232                                         const struct patch **start_patch,
u_int start_instr, u_int *skip_addr);
  234 static void             ahc_download_instr(struct ahc_softc *ahc,
u_int instrptr, uint8_t *dconsts);
  236 #ifdef AHC_TARGET_MODE
  237 static void             ahc_queue_lstate_event(struct ahc_softc *ahc,
  238                                                struct ahc_tmode_lstate *lstate,
u_int initiator_id,
u_int event_type,
u_int event_arg);
  242 static void             ahc_update_scsiid(struct ahc_softc *ahc,
u_int targid_mask);
  244 static int              ahc_handle_target_cmd(struct ahc_softc *ahc,
  245                                               struct target_cmd *cmd);
  246 #endif
  248 /************************** Added for porting to NetBSD ***********************/
  249 static int ahc_createdmamem(bus_dma_tag_t tag,
  250                             int size,
  251                             int flags,
bus_dmamap_t *mapp,
caddr_t *vaddr,
bus_addr_t *baddr,
bus_dma_segment_t *seg,
  256                             int *nseg,
  257                             const char *myname, const char *what);
  258 static void ahc_freedmamem(bus_dma_tag_t tag,
  259                            int size,
bus_dmamap_t map,
caddr_t vaddr,
bus_dma_segment_t *seg,
  263                            int nseg);
  265 /************************* Sequencer Execution Control ************************/
  266 /*
  267  * Restart the sequencer program from address zero
  268  */
  269 void
ahc_restart(struct ahc_softc *ahc)
  271 {
ahc_pause(ahc);
  275         /* No more pending messages. */
ahc_clear_msg_state(ahc);
ahc_outb(ahc, SCSISIGO, 0);             /* De-assert BSY */
ahc_outb(ahc, MSG_OUT, MSG_NOOP);       /* No message to send */
ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
ahc_outb(ahc, LASTPHASE, P_BUSFREE);
ahc_outb(ahc, SAVED_SCSIID, 0xFF);
ahc_outb(ahc, SAVED_LUN, 0xFF);
  285         /*
  286          * Ensure that the sequencer's idea of TQINPOS
  287          * matches our own.  The sequencer increments TQINPOS
  288          * only after it sees a DMA complete and a reset could
  289          * occur before the increment leaving the kernel to believe
  290          * the command arrived but the sequencer to not.
  291          */
ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
  294         /* Always allow reselection */
ahc_outb(ahc, SCSISEQ,
ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
  297         if ((ahc->features & AHC_CMD_CHAN) != 0) {
  298                 /* Ensure that no DMA operations are in progress */
ahc_outb(ahc, CCSCBCNT, 0);
ahc_outb(ahc, CCSGCTL, 0);
ahc_outb(ahc, CCSCBCTL, 0);
  302         }
  303         /*
  304          * If we were in the process of DMA'ing SCB data into
  305          * an SCB, replace that SCB on the free list.  This prevents
  306          * an SCB leak.
  307          */
  308         if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) {
ahc_add_curscb_to_free_list(ahc);
ahc_outb(ahc, SEQ_FLAGS2,
ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA);
  312         }
  314         /*
  315          * Clear any pending sequencer interrupt.  It is no
  316          * longer relevant since we're resetting the Program
  317          * Counter.
  318          */
ahc_outb(ahc, CLRINT, CLRSEQINT);
ahc_outb(ahc, MWI_RESIDUAL, 0);
ahc_outb(ahc, SEQCTL, ahc->seqctl);
ahc_outb(ahc, SEQADDR0, 0);
ahc_outb(ahc, SEQADDR1, 0);
ahc_unpause(ahc);
  327 }
  329 /************************* Input/Output Queues ********************************/
  330 void
ahc_run_qoutfifo(struct ahc_softc *ahc)
  332 {
  333         struct scb *scb;
u_int  scb_index;
ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
  337         while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) {
scb_index = ahc->qoutfifo[ahc->qoutfifonext];
  340 #ifdef __sgi__
  341                 if ((ahc->qoutfifonext & 0x1f) == 0x1f) {
u_int modnext;
u_int32_t *nextp;
  345                         /*
  346                          * Clear 32 bytes of QOUTFIFO at a time
  347                          * so that we don't clobber an incoming
  348                          * byte DMA to the array on architectures
  349                          * non coherent caches.
  350                          */
modnext = ahc->qoutfifonext & ~0x1f;
nextp = (uint32_t *)(&ahc->qoutfifo[modnext]);
  353                         *nextp++ = 0xFFFFFFFFUL;
  354                         *nextp++ = 0xFFFFFFFFUL;
  355                         *nextp++ = 0xFFFFFFFFUL;
  356                         *nextp++ = 0xFFFFFFFFUL;
  357                         *nextp++ = 0xFFFFFFFFUL;
  358                         *nextp++ = 0xFFFFFFFFUL;
  359                         *nextp++ = 0xFFFFFFFFUL;
  360                         *nextp++ = 0xFFFFFFFFUL;
ahc_dmamap_sync(ahc, ahc->parent_dmat /*shared_data_dmat*/,
ahc->shared_data_dmamap,
  363                                         /*offset*/modnext, /*len*/32,
BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
  365                 }
  366 #else
  367                 if ((ahc->qoutfifonext & 0x03) == 0x03) {
u_int modnext;
  370                         /*
  371                          * Clear 32bits of QOUTFIFO at a time
  372                          * so that we don't clobber an incoming
  373                          * byte DMA to the array on architectures
  374                          * that only support 32bit load and store
  375                          * operations.
  376                          */
modnext = ahc->qoutfifonext & ~0x3;
  378                         *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL;
ahc_dmamap_sync(ahc, ahc->parent_dmat /*shared_data_dmat*/,
ahc->shared_data_dmamap,
  381                                         /*offset*/modnext, /*len*/4,
BUS_DMASYNC_PREREAD);
  383                 }
  384 #endif
ahc->qoutfifonext++;
scb = ahc_lookup_scb(ahc, scb_index);
  388                 if (scb == NULL) {
printf("%s: WARNING no command for scb %d "
  390                                "(cmdcmplt)\nQOUTPOS = %d\n",
ahc_name(ahc), scb_index,
  392                                (ahc->qoutfifonext - 1) & 0xFF);
  393                         continue;
  394                 }
  396                 /*
  397                  * Save off the residual
  398                  * if there is one.
  399                  */
ahc_update_residual(ahc, scb);
ahc_done(ahc, scb);
  402         }
  403 }
  405 void
ahc_run_untagged_queues(struct ahc_softc *ahc)
  407 {
  408         int i;
  410         for (i = 0; i < 16; i++)
ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]);
  412 }
  414 void
ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue)
  416 {
  417         struct scb *scb;
  419         if (ahc->untagged_queue_lock != 0)
  420                 return;
  422         if ((scb = TAILQ_FIRST(queue)) != NULL
  423             && (scb->flags & SCB_ACTIVE) == 0) {
scb->flags |= SCB_ACTIVE;
ahc_queue_scb(ahc, scb);
  426         }
  427 }
  429 /************************* Interrupt Handling *********************************/
  430 void
ahc_handle_brkadrint(struct ahc_softc *ahc)
  432 {
  433         /*
  434          * We upset the sequencer :-(
  435          * Lookup the error message
  436          */
  437 #ifndef SMALL_KERNEL
  438         int i;
  439         int error;
error = ahc_inb(ahc, ERROR);
  442         for (i = 0; error != 1 && i < num_errors; i++)
error >>= 1;
printf("%s: brkadrint, %s at seqaddr = 0x%x\n",
ahc_name(ahc), ahc_hard_errors[i].errmesg,
ahc_inb(ahc, SEQADDR0) |
  447                (ahc_inb(ahc, SEQADDR1) << 8));
ahc_dump_card_state(ahc);
  450 #endif
  452         /* Tell everyone that this HBA is no longer available */
ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS,
CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
CAM_NO_HBA);
  457         /* Disable all interrupt sources by resetting the controller */
ahc_shutdown(ahc);
  459 }
  461 void
ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat)
  463 {
  464         struct scb *scb;
  465         struct ahc_devinfo devinfo;
ahc_fetch_devinfo(ahc, &devinfo);
  469         /*
  470          * Clear the upper byte that holds SEQINT status
  471          * codes and clear the SEQINT bit. We will unpause
  472          * the sequencer, if appropriate, after servicing
  473          * the request.
  474          */
ahc_outb(ahc, CLRINT, CLRSEQINT);
  476         switch (intstat & SEQINT_MASK) {
  477         case BAD_STATUS:
  478         {
u_int  scb_index;
  480                 struct hardware_scb *hscb;
  482                 /*
  483                  * Set the default return value to 0 (don't
  484                  * send sense).  The sense code will change
  485                  * this if needed.
  486                  */
ahc_outb(ahc, RETURN_1, 0);
  489                 /*
  490                  * The sequencer will notify us when a command
  491                  * has an error that would be of interest to
  492                  * the kernel.  This allows us to leave the sequencer
  493                  * running in the common case of command completes
  494                  * without error.  The sequencer will already have
  495                  * DMA'd the SCB back up to us, so we can reference
  496                  * the in kernel copy directly.
  497                  */
scb_index = ahc_inb(ahc, SCB_TAG);
scb = ahc_lookup_scb(ahc, scb_index);
  500                 if (scb == NULL) {
ahc_print_devinfo(ahc, &devinfo);
printf("ahc_intr - referenced scb "
  503                                "not valid during seqint 0x%x scb(%d)\n",
intstat, scb_index);
ahc_dump_card_state(ahc);
panic("for safety");
  507                         goto unpause;
  508                 }
hscb = scb->hscb; 
  512                 /* Don't want to clobber the original sense code */
  513                 if ((scb->flags & SCB_SENSE) != 0) {
  514                         /*
  515                          * Clear the SCB_SENSE Flag and have
  516                          * the sequencer do a normal command
  517                          * complete.
  518                          */
scb->flags &= ~SCB_SENSE;
ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
  521                         break;
  522                 }
ahc_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
  524                 /* Freeze the queue until the client sees the error. */
ahc_freeze_devq(ahc, scb);
ahc_freeze_scb(scb);
ahc_set_scsi_status(scb, hscb->shared_data.status.scsi_status);
  528                 switch (hscb->shared_data.status.scsi_status) {
  529                 case SCSI_STATUS_OK:
printf("%s: Interrupted for status of 0 (?)\n",
ahc_name(ahc));
  532                         break;
  533                 case SCSI_STATUS_CMD_TERMINATED:
  534                 case SCSI_STATUS_CHECK_COND:
  535                 {
  536                         struct ahc_dma_seg *sg;
  537                         struct scsi_sense *sc;
  538                         struct ahc_initiator_tinfo *targ_info;
  539                         struct ahc_tmode_tstate *tstate;
  540                         struct ahc_transinfo *tinfo;
  541 #ifdef AHC_DEBUG
  542                         if (ahc_debug & AHC_SHOW_SENSE) {
ahc_print_path(ahc, scb);
printf("SCB %d: requests Check Status\n",
scb->hscb->tag);
  546                         }
  547 #endif
  549                         if (ahc_perform_autosense(scb) == 0)
  550                                 break;
targ_info = ahc_fetch_transinfo(ahc,
devinfo.channel,
devinfo.our_scsiid,
devinfo.target,
  556                                                         &tstate);
tinfo = &targ_info->curr;
sg = scb->sg_list;
sc = (struct scsi_sense *)(&hscb->shared_data.cdb); 
  560                         /*
  561                          * Save off the residual if there is one.
  562                          */
ahc_update_residual(ahc, scb);
  564 #ifdef AHC_DEBUG
  565                         if (ahc_debug & AHC_SHOW_SENSE) {
ahc_print_path(ahc, scb);
printf("Sending Sense\n");
  568                         }
  569 #endif
sg->addr = ahc_get_sense_bufaddr(ahc, scb);
sg->len = ahc_get_sense_bufsize(ahc, scb);
sg->len |= AHC_DMA_LAST_SEG;
  574                         /* Fixup byte order */
sg->addr = aic_htole32(sg->addr);
sg->len = aic_htole32(sg->len);
sc->opcode = REQUEST_SENSE;
sc->byte2 = 0;
  580                         if (tinfo->protocol_version <= SCSI_REV_2
  581                             && SCB_GET_LUN(scb) < 8)
sc->byte2 = SCB_GET_LUN(scb) << 5;
sc->unused[0] = 0;
sc->unused[1] = 0;
sc->length = sg->len;
sc->control = 0;
  588                         /*
  589                          * We can't allow the target to disconnect.
  590                          * This will be an untagged transaction and
  591                          * having the target disconnect will make this
  592                          * transaction indistinguishable from outstanding
  593                          * tagged transactions.
  594                          */
hscb->control = 0;
  597                         /*
  598                          * This request sense could be because the
  599                          * the device lost power or in some other
  600                          * way has lost our transfer negotiations.
  601                          * Renegotiate if appropriate.  Unit attention
  602                          * errors will be reported before any data
  603                          * phases occur.
  604                          */
  605                         if (ahc_get_residual(scb) 
  606                             == ahc_get_transfer_length(scb)) {
ahc_update_neg_request(ahc, &devinfo,
tstate, targ_info,
AHC_NEG_IF_NON_ASYNC);
  610                         }
  611                         if (tstate->auto_negotiate & devinfo.target_mask) {
hscb->control |= MK_MESSAGE;
scb->flags &= ~SCB_NEGOTIATE;
scb->flags |= SCB_AUTO_NEGOTIATE;
  615                         }
hscb->cdb_len = sizeof(*sc);
hscb->dataptr = sg->addr; 
hscb->datacnt = sg->len;
hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID;
hscb->sgptr = aic_htole32(hscb->sgptr);
  621 #ifdef __OpenBSD__
bus_dmamap_sync(ahc->parent_dmat,
ahc->scb_data->sense_dmamap,
  624                             (scb - ahc->scb_data->scbarray) *
  625                             sizeof(struct scsi_sense_data),
  626                             sizeof(struct scsi_sense_data),
BUS_DMASYNC_PREREAD);
bus_dmamap_sync(ahc->parent_dmat,
scb->sg_map->sg_dmamap,
  630                             0, scb->sg_map->sg_dmamap->dm_mapsize,
BUS_DMASYNC_PREWRITE);
bus_dmamap_sync(ahc->parent_dmat,
ahc->scb_data->hscb_dmamap,
  634                             0, ahc->scb_data->hscb_dmamap->dm_mapsize,
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
  636 #endif
scb->sg_count = 1;
scb->flags |= SCB_SENSE;
ahc_qinfifo_requeue_tail(ahc, scb);
ahc_outb(ahc, RETURN_1, SEND_SENSE);
  641                         /*
  642                          * Ensure we have enough time to actually
  643                          * retrieve the sense.
  644                          */
ahc_scb_timer_reset(scb, 5 * 1000000);
  646                         break;
  647                 }
  648                 default:
  649                         break;
  650                 }
  651                 break;
  652         }
  653         case NO_MATCH:
  654         {
  655                 /* Ensure we don't leave the selection hardware on */
ahc_outb(ahc, SCSISEQ,
ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
printf("%s:%c:%d: no active SCB for reconnecting "
  660                        "target - issuing BUS DEVICE RESET\n",
ahc_name(ahc), devinfo.channel, devinfo.target);
printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
  663                        "ARG_1 == 0x%x ACCUM = 0x%x\n",
ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
  667                        "SINDEX == 0x%x\n",
ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
ahc_index_busy_tcl(ahc,
BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
ahc_inb(ahc, SAVED_LUN))),
ahc_inb(ahc, SINDEX));
printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
  674                        "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
ahc_inb(ahc, SCB_CONTROL));
printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0));
printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL));
ahc_dump_card_state(ahc);
ahc->msgout_buf[0] = MSG_BUS_DEV_RESET;
ahc->msgout_len = 1;
ahc->msgout_index = 0;
ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
ahc_outb(ahc, MSG_OUT, HOST_MSG);
ahc_assert_atn(ahc);
  689                 break;
  690         }
  691         case SEND_REJECT: 
  692         {
u_int rejbyte = ahc_inb(ahc, ACCUM);
printf("%s:%c:%d: Warning - unknown message received from "
  695                        "target (0x%x).  Rejecting\n", 
ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte);
  697                 break; 
  698         }
  699         case PROTO_VIOLATION:
  700         {
ahc_handle_proto_violation(ahc);
  702                 break;
  703         }
  704         case IGN_WIDE_RES:
ahc_handle_ign_wide_residue(ahc, &devinfo);
  706                 break;
  707         case PDATA_REINIT:
ahc_reinitialize_dataptrs(ahc);
  709                 break;
  710         case BAD_PHASE:
  711         {
u_int lastphase;
lastphase = ahc_inb(ahc, LASTPHASE);
printf("%s:%c:%d: unknown scsi bus phase %x, "
  716                        "lastphase = 0x%x.  Attempting to continue\n",
ahc_name(ahc), devinfo.channel, devinfo.target,
lastphase, ahc_inb(ahc, SCSISIGI));
  719                 break;
  720         }
  721         case MISSED_BUSFREE:
  722         {
u_int lastphase;
lastphase = ahc_inb(ahc, LASTPHASE);
printf("%s:%c:%d: Missed busfree. "
  727                        "Lastphase = 0x%x, Curphase = 0x%x\n",
ahc_name(ahc), devinfo.channel, devinfo.target,
lastphase, ahc_inb(ahc, SCSISIGI));
ahc_restart(ahc);
  731                 return;
  732         }
  733         case HOST_MSG_LOOP:
  734         {
  735                 /*
  736                  * The sequencer has encountered a message phase
  737                  * that requires host assistance for completion.
  738                  * While handling the message phase(s), we will be
  739                  * notified by the sequencer after each byte is
  740                  * transferred so we can track bus phase changes.
  741                  *
  742                  * If this is the first time we've seen a HOST_MSG_LOOP
  743                  * interrupt, initialize the state of the host message
  744                  * loop.
  745                  */
  746                 if (ahc->msg_type == MSG_TYPE_NONE) {
  747                         struct scb *scb;
u_int scb_index;
u_int bus_phase;
bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
  752                         if (bus_phase != P_MESGIN
  753                          && bus_phase != P_MESGOUT) {
printf("ahc_intr: HOST_MSG_LOOP bad "
  755                                        "phase 0x%x\n",
bus_phase);
  757                                 /*
  758                                  * Probably transitioned to bus free before
  759                                  * we got here.  Just punt the message.
  760                                  */
ahc_clear_intstat(ahc);
ahc_restart(ahc);
  763                                 return;
  764                         }
scb_index = ahc_inb(ahc, SCB_TAG);
scb = ahc_lookup_scb(ahc, scb_index);
  768                         if (devinfo.role == ROLE_INITIATOR) {
  769                                 if (scb == NULL)
panic("HOST_MSG_LOOP with "
  771                                               "invalid SCB %x\n", scb_index);
  773                                 if (bus_phase == P_MESGOUT)
ahc_setup_initiator_msgout(ahc,
  775                                                                    &devinfo,
scb);
  777                                 else {
ahc->msg_type =
MSG_TYPE_INITIATOR_MSGIN;
ahc->msgin_index = 0;
  781                                 }
  782                         }
  783 #ifdef AHC_TARGET_MODE
  784                         else {
  785                                 if (bus_phase == P_MESGOUT) {
ahc->msg_type =
MSG_TYPE_TARGET_MSGOUT;
ahc->msgin_index = 0;
  789                                 }
  790                                 else 
ahc_setup_target_msgin(ahc,
  792                                                                &devinfo,
scb);
  794                         }
  795 #endif
  796                 }
ahc_handle_message_phase(ahc);
  799                 break;
  800         }
  801         case PERR_DETECTED:
  802         {
  803                 /*
  804                  * If we've cleared the parity error interrupt
  805                  * but the sequencer still believes that SCSIPERR
  806                  * is true, it must be that the parity error is
  807                  * for the currently presented byte on the bus,
  808                  * and we are not in a phase (data-in) where we will
  809                  * eventually ack this byte.  Ack the byte and
  810                  * throw it away in the hope that the target will
  811                  * take us to message out to deliver the appropriate
  812                  * error message.
  813                  */
  814                 if ((intstat & SCSIINT) == 0
  815                  && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) {
  817                         if ((ahc->features & AHC_DT) == 0) {
u_int curphase;
  820                                 /*
  821                                  * The hardware will only let you ack bytes
  822                                  * if the expected phase in SCSISIGO matches
  823                                  * the current phase.  Make sure this is
  824                                  * currently the case.
  825                                  */
curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
ahc_outb(ahc, LASTPHASE, curphase);
ahc_outb(ahc, SCSISIGO, curphase);
  829                         }
  830                         if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) {
  831                                 int wait;
  833                                 /*
  834                                  * In a data phase.  Faster to bitbucket
  835                                  * the data than to individually ack each
  836                                  * byte.  This is also the only strategy
  837                                  * that will work with AUTOACK enabled.
  838                                  */
ahc_outb(ahc, SXFRCTL1,
ahc_inb(ahc, SXFRCTL1) | BITBUCKET);
wait = 5000;
  842                                 while (--wait != 0) {
  843                                         if ((ahc_inb(ahc, SCSISIGI)
  844                                           & (CDI|MSGI)) != 0)
  845                                                 break;
aic_delay(100);
  847                                 }
ahc_outb(ahc, SXFRCTL1,
ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
  850                                 if (wait == 0) {
  851                                         struct  scb *scb;
u_int   scb_index;
ahc_print_devinfo(ahc, &devinfo);
printf("Unable to clear parity error.  "
  856                                                "Resetting bus.\n");
scb_index = ahc_inb(ahc, SCB_TAG);
scb = ahc_lookup_scb(ahc, scb_index);
  859                                         if (scb != NULL)
ahc_set_transaction_status(scb,
CAM_UNCOR_PARITY);
ahc_reset_channel(ahc, devinfo.channel, 
  863                                                           /*init reset*/TRUE);
  864                                 }
  865                         } else {
ahc_inb(ahc, SCSIDATL);
  867                         }
  868                 }
  869                 break;
  870         }
  871         case DATA_OVERRUN:
  872         {
  873                 /*
  874                  * When the sequencer detects an overrun, it
  875                  * places the controller in "BITBUCKET" mode
  876                  * and allows the target to complete its transfer.
  877                  * Unfortunately, none of the counters get updated
  878                  * when the controller is in this mode, so we have
  879                  * no way of knowing how large the overrun was.
  880                  */
u_int scbindex = ahc_inb(ahc, SCB_TAG);
u_int lastphase = ahc_inb(ahc, LASTPHASE);
u_int i;
scb = ahc_lookup_scb(ahc, scbindex);
  886                 for (i = 0; i < num_phases; i++) {
  887                         if (lastphase == ahc_phase_table[i].phase)
  888                                 break;
  889                 }
ahc_print_path(ahc, scb);
printf("data overrun detected %s."
  892                        "  Tag == 0x%x.\n",
ahc_phase_table[i].phasemsg,
scb->hscb->tag);
  895 #ifndef SMALL_KERNEL
ahc_print_path(ahc, scb);
printf("%s seen Data Phase.  Length = %ld.  NumSGs = %d.\n",
ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't",
ahc_get_transfer_length(scb), scb->sg_count);
  900                 if (scb->sg_count > 0) {
  901                         for (i = 0; i < scb->sg_count; i++) {
printf("sg[%d] - Addr 0x%x%x : Length %d\n",
i,
  905                                        (aic_le32toh(scb->sg_list[i].len) >> 24
  906                                         & SG_HIGH_ADDR_BITS),
aic_le32toh(scb->sg_list[i].addr),
aic_le32toh(scb->sg_list[i].len)
  909                                        & AHC_SG_LEN_MASK);
  910                         }
  911                 }
  912 #endif
  913                 /*
  914                  * Set this and it will take effect when the
  915                  * target does a command complete.
  916                  */
ahc_freeze_devq(ahc, scb);
  918                 if ((scb->flags & SCB_SENSE) == 0) {
ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR);
  920                 } else {
scb->flags &= ~SCB_SENSE;
ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
  923                 }
ahc_freeze_scb(scb);
  926                 if ((ahc->features & AHC_ULTRA2) != 0) {
  927                         /*
  928                          * Clear the channel in case we return
  929                          * to data phase later.
  930                          */
ahc_outb(ahc, SXFRCTL0,
ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
ahc_outb(ahc, SXFRCTL0,
ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
  935                 }
  936                 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
u_int dscommand1;
  939                         /* Ensure HHADDR is 0 for future DMA operations. */
dscommand1 = ahc_inb(ahc, DSCOMMAND1);
ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
ahc_outb(ahc, HADDR, 0);
ahc_outb(ahc, DSCOMMAND1, dscommand1);
  944                 }
  945                 break;
  946         }
  947         case MKMSG_FAILED:
  948         {
u_int scbindex;
printf("%s:%c:%d:%d: Attempt to issue message failed\n",
ahc_name(ahc), devinfo.channel, devinfo.target,
devinfo.lun);
scbindex = ahc_inb(ahc, SCB_TAG);
scb = ahc_lookup_scb(ahc, scbindex);
  956                 if (scb != NULL)
  957                         /*
  958                          * Ensure that we didn't put a second instance of this
  959                          * SCB into the QINFIFO.
  960                          */
ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
SCB_GET_CHANNEL(ahc, scb),
SCB_GET_LUN(scb), scb->hscb->tag,
ROLE_INITIATOR, /*status*/0,
SEARCH_REMOVE);
  966                 break;
  967         }
  968         case NO_FREE_SCB:
  969         {
printf("%s: No free or disconnected SCBs\n", ahc_name(ahc));
ahc_dump_card_state(ahc);
panic("for safety");
  973                 break;
  974         }
  975         case SCB_MISMATCH:
  976         {
u_int scbptr;
scbptr = ahc_inb(ahc, SCBPTR);
printf("Bogus TAG after DMA.  SCBPTR %d, tag %d, our tag %d\n",
scbptr, ahc_inb(ahc, ARG_1),
ahc->scb_data->hscbs[scbptr].tag);
ahc_dump_card_state(ahc);
panic("for safety");
  985                 break;
  986         }
  987         case OUT_OF_RANGE:
  988         {
  989 #ifndef SMALL_KERNEL
printf("%s: BTT calculation out of range\n", ahc_name(ahc));
printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
  992                        "ARG_1 == 0x%x ACCUM = 0x%x\n",
ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
  996                        "SINDEX == 0x%x\n, A == 0x%x\n",
ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
ahc_index_busy_tcl(ahc,
BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
ahc_inb(ahc, SAVED_LUN))),
ahc_inb(ahc, SINDEX),
ahc_inb(ahc, ACCUM));
printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
 1004                        "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
ahc_inb(ahc, SCB_CONTROL));
printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
 1010 #endif
ahc_dump_card_state(ahc);
panic("for safety");
 1013                 break;
 1014         }
 1015         default:
printf("ahc_intr: seqint, "
 1017                        "intstat == 0x%x, scsisigi = 0x%x\n",
intstat, ahc_inb(ahc, SCSISIGI));
 1019                 break;
 1020         }
unpause:
 1022         /*
 1023          *  The sequencer is paused immediately on
 1024          *  a SEQINT, so we should restart it when
 1025          *  we're done.
 1026          */
ahc_unpause(ahc);
 1028 }
 1030 void
ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
 1032 {
u_int   scb_index;
u_int   status0;
u_int   status;
 1036         struct  scb *scb;
 1037         char    cur_channel;
 1038         char    intr_channel;
 1040         if ((ahc->features & AHC_TWIN) != 0
 1041             && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0))
cur_channel = 'B';
 1043         else
cur_channel = 'A';
intr_channel = cur_channel;
 1047         if ((ahc->features & AHC_ULTRA2) != 0)
status0 = ahc_inb(ahc, SSTAT0) & IOERR;
 1049         else
status0 = 0;
status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
 1052         if (status == 0 && status0 == 0) {
 1053                 if ((ahc->features & AHC_TWIN) != 0) {
 1054                         /* Try the other channel */
ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
status = ahc_inb(ahc, SSTAT1)
 1057                                & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
intr_channel = (cur_channel == 'A') ? 'B' : 'A';
 1059                 }
 1060                 if (status == 0) {
printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc));
ahc_outb(ahc, CLRINT, CLRSCSIINT);
ahc_unpause(ahc);
 1064                         return;
 1065                 }
 1066         }
 1068         /* Make sure the sequencer is in a safe location. */
ahc_clear_critical_section(ahc);
scb_index = ahc_inb(ahc, SCB_TAG);
scb = ahc_lookup_scb(ahc, scb_index);
 1073         if (scb != NULL
 1074          && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
scb = NULL;
 1077         if ((ahc->features & AHC_ULTRA2) != 0
 1078          && (status0 & IOERR) != 0) {
 1079                 int now_lvd;
now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40;
printf("%s: Transceiver State Has Changed to %s mode\n",
ahc_name(ahc), now_lvd ? "LVD" : "SE");
ahc_outb(ahc, CLRSINT0, CLRIOERR);
 1085                 /*
 1086                  * When transitioning to SE mode, the reset line
 1087                  * glitches, triggering an arbitration bug in some
 1088                  * Ultra2 controllers.  This bug is cleared when we
 1089                  * assert the reset line.  Since a reset glitch has
 1090                  * already occurred with this transition and a
 1091                  * transceiver state change is handled just like
 1092                  * a bus reset anyway, asserting the reset line
 1093                  * ourselves is safe.
 1094                  */
ahc_reset_channel(ahc, intr_channel,
 1096                                  /*Initiate Reset*/now_lvd == 0);
 1097         } else if ((status & SCSIRSTI) != 0) {
printf("%s: Someone reset channel %c\n",
ahc_name(ahc), intr_channel);
 1100                 if (intr_channel != cur_channel)
ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE);
 1103         } else if ((status & SCSIPERR) != 0) {
 1104                 /*
 1105                  * Determine the bus phase and queue an appropriate message.
 1106                  * SCSIPERR is latched true as soon as a parity error
 1107                  * occurs.  If the sequencer acked the transfer that
 1108                  * caused the parity error and the currently presented
 1109                  * transfer on the bus has correct parity, SCSIPERR will
 1110                  * be cleared by CLRSCSIPERR.  Use this to determine if
 1111                  * we should look at the last phase the sequencer recorded,
 1112                  * or the current phase presented on the bus.
 1113                  */
 1114                 struct  ahc_devinfo devinfo;
u_int   mesg_out;
u_int   curphase;
u_int   errorphase;
u_int   lastphase;
u_int   scsirate;
u_int   i;
u_int   sstat2;
 1122                 int     silent;
lastphase = ahc_inb(ahc, LASTPHASE);
curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
sstat2 = ahc_inb(ahc, SSTAT2);
ahc_outb(ahc, CLRSINT1, CLRSCSIPERR);
 1128                 /*
 1129                  * For all phases save DATA, the sequencer won't
 1130                  * automatically ack a byte that has a parity error
 1131                  * in it.  So the only way that the current phase
 1132                  * could be 'data-in' is if the parity error is for
 1133                  * an already acked byte in the data phase.  During
 1134                  * synchronous data-in transfers, we may actually
 1135                  * ack bytes before latching the current phase in
 1136                  * LASTPHASE, leading to the discrepancy between
 1137                  * curphase and lastphase.
 1138                  */
 1139                 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0
 1140                  || curphase == P_DATAIN || curphase == P_DATAIN_DT)
errorphase = curphase;
 1142                 else
errorphase = lastphase;
 1145                 for (i = 0; i < num_phases; i++) {
 1146                         if (errorphase == ahc_phase_table[i].phase)
 1147                                 break;
 1148                 }
mesg_out = ahc_phase_table[i].mesg_out;
silent = FALSE;
 1151                 if (scb != NULL) {
 1152                         if (SCB_IS_SILENT(scb))
silent = TRUE;
 1154                         else
ahc_print_path(ahc, scb);
scb->flags |= SCB_TRANSMISSION_ERROR;
 1157                 } else
printf("%s:%c:%d: ", ahc_name(ahc), intr_channel,
SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID)));
scsirate = ahc_inb(ahc, SCSIRATE);
 1161                 if (silent == FALSE) {
printf("parity error detected %s. "
 1163                                "SEQADDR(0x%x) SCSIRATE(0x%x)\n",
ahc_phase_table[i].phasemsg,
ahc_inw(ahc, SEQADDR0),
scsirate);
 1167                         if ((ahc->features & AHC_DT) != 0) {
 1168                                 if ((sstat2 & CRCVALERR) != 0)
printf("\tCRC Value Mismatch\n");
 1170                                 if ((sstat2 & CRCENDERR) != 0)
printf("\tNo terminal CRC packet "
 1172                                                "received\n");
 1173                                 if ((sstat2 & CRCREQERR) != 0)
printf("\tIllegal CRC packet "
 1175                                                "request\n");
 1176                                 if ((sstat2 & DUAL_EDGE_ERR) != 0)
printf("\tUnexpected %sDT Data Phase\n",
 1178                                                (scsirate & SINGLE_EDGE)
 1179                                              ? "" : "non-");
 1180                         }
 1181                 }
 1183                 if ((ahc->features & AHC_DT) != 0
 1184                  && (sstat2 & DUAL_EDGE_ERR) != 0) {
 1185                         /*
 1186                          * This error applies regardless of
 1187                          * data direction, so ignore the value
 1188                          * in the phase table.
 1189                          */
mesg_out = MSG_INITIATOR_DET_ERR;
 1191                 }
 1193                 /*
 1194                  * We've set the hardware to assert ATN if we   
 1195                  * get a parity error on "in" phases, so all we  
 1196                  * need to do is stuff the message buffer with
 1197                  * the appropriate message.  "In" phases have set
 1198                  * mesg_out to something other than MSG_NOP.
 1199                  */
 1200                 if (mesg_out != MSG_NOOP) {
 1201                         if (ahc->msg_type != MSG_TYPE_NONE)
ahc->send_msg_perror = TRUE;
 1203                         else
ahc_outb(ahc, MSG_OUT, mesg_out);
 1205                 }
 1206                 /*
 1207                  * Force a renegotiation with this target just in
 1208                  * case we are out of sync for some external reason
 1209                  * unknown (or unreported) by the target.
 1210                  */
ahc_fetch_devinfo(ahc, &devinfo);
ahc_force_renegotiation(ahc, &devinfo);
ahc_outb(ahc, CLRINT, CLRSCSIINT);
ahc_unpause(ahc);
 1216         } else if ((status & SELTO) != 0) {
u_int   scbptr;
 1219                 /* Stop the selection */
ahc_outb(ahc, SCSISEQ, 0);
 1222                 /* No more pending messages */
ahc_clear_msg_state(ahc);
 1225                 /* Clear interrupt state */
ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
 1229                 /*
 1230                  * Although the driver does not care about the
 1231                  * 'Selection in Progress' status bit, the busy
 1232                  * LED does.  SELINGO is only cleared by a sucessfull
 1233                  * selection, so we must manually clear it to insure
 1234                  * the LED turns off just incase no future successful
 1235                  * selections occur (e.g. no devices on the bus).
 1236                  */
ahc_outb(ahc, CLRSINT0, CLRSELINGO);
scbptr = ahc_inb(ahc, WAITING_SCBH);
ahc_outb(ahc, SCBPTR, scbptr);
scb_index = ahc_inb(ahc, SCB_TAG);
scb = ahc_lookup_scb(ahc, scb_index);
 1244                 if (scb == NULL) {
printf("%s: ahc_intr - referenced scb not "
 1246                                "valid during SELTO scb(%d, %d)\n",
ahc_name(ahc), scbptr, scb_index);
ahc_dump_card_state(ahc);
 1249                 } else {
 1250                         struct ahc_devinfo devinfo;
 1251 #ifdef AHC_DEBUG
 1252                         if ((ahc_debug & AHC_SHOW_SELTO) != 0) {
ahc_print_path(ahc, scb);
printf("Saw Selection Timeout for SCB 0x%x\n",
scb_index);
 1256                         }
 1257 #endif
ahc_scb_devinfo(ahc, &devinfo, scb);
ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT);
ahc_freeze_devq(ahc, scb);
 1262                         /*
 1263                          * Cancel any pending transactions on the device
 1264                          * now that it seems to be missing.  This will
 1265                          * also revert us to async/narrow transfers until
 1266                          * we can renegotiate with the device.
 1267                          */
ahc_handle_devreset(ahc, &devinfo,
CAM_SEL_TIMEOUT,
 1270                                             "Selection Timeout",
 1271                                             /*verbose_level*/1);
 1272                 }
ahc_outb(ahc, CLRINT, CLRSCSIINT);
ahc_restart(ahc);
 1275         } else if ((status & BUSFREE) != 0
 1276                 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) {
 1277                 struct  ahc_devinfo devinfo;
u_int   lastphase;
u_int   saved_scsiid;
u_int   saved_lun;
u_int   target;
u_int   initiator_role_id;
 1283                 char    channel;
 1284                 int     printerror;
 1286                 /*
 1287                  * Clear our selection hardware as soon as possible.
 1288                  * We may have an entry in the waiting Q for this target,
 1289                  * that is affected by this busfree and we don't want to
 1290                  * go about selecting the target while we handle the event.
 1291                  */
ahc_outb(ahc, SCSISEQ,
ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
 1295                 /*
 1296                  * Disable busfree interrupts and clear the busfree
 1297                  * interrupt status.  We do this here so that several
 1298                  * bus transactions occur prior to clearing the SCSIINT
 1299                  * latch.  It can take a bit for the clearing to take effect.
 1300                  */
ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR);
 1304                 /*
 1305                  * Look at what phase we were last in.
 1306                  * If its message out, chances are pretty good
 1307                  * that the busfree was in response to one of
 1308                  * our abort requests.
 1309                  */
lastphase = ahc_inb(ahc, LASTPHASE);
saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
saved_lun = ahc_inb(ahc, SAVED_LUN);
target = SCSIID_TARGET(ahc, saved_scsiid);
initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
channel = SCSIID_CHANNEL(ahc, saved_scsiid);
ahc_compile_devinfo(&devinfo, initiator_role_id,
target, saved_lun, channel, ROLE_INITIATOR);
printerror = 1;
 1320                 if (lastphase == P_MESGOUT) {
u_int tag;
tag = SCB_LIST_NULL;
 1324                         if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE)
 1325                             || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) {
 1326                                 if (ahc->msgout_buf[ahc->msgout_index - 1]
 1327                                     == MSG_ABORT_TAG)
tag = scb->hscb->tag;
ahc_print_path(ahc, scb);
printf("SCB %d - Abort%s Completed.\n",
scb->hscb->tag, tag == SCB_LIST_NULL ?
 1332                                        "" : " Tag");
ahc_abort_scbs(ahc, target, channel,
saved_lun, tag,
ROLE_INITIATOR,
CAM_REQ_ABORTED);
printerror = 0;
 1338                         } else if (ahc_sent_msg(ahc, AHCMSG_1B,
MSG_BUS_DEV_RESET, TRUE)) {
 1340 #ifdef __FreeBSD__
 1341                                 /*
 1342                                  * Don't mark the user's request for this BDR
 1343                                  * as completing with CAM_BDR_SENT.  CAM3
 1344                                  * specifies CAM_REQ_CMP.
 1345                                  */
 1346                                 if (scb != NULL
 1347                                  && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
 1348                                  && ahc_match_scb(ahc, scb, target, channel,
CAM_LUN_WILDCARD,
SCB_LIST_NULL,
ROLE_INITIATOR)) {
ahc_set_transaction_status(scb, CAM_REQ_CMP);
 1353                                 }
 1354 #endif
ahc_compile_devinfo(&devinfo,
initiator_role_id,
target,
CAM_LUN_WILDCARD,
channel,
ROLE_INITIATOR);
ahc_handle_devreset(ahc, &devinfo,
CAM_BDR_SENT,
 1363                                                     "Bus Device Reset",
 1364                                                     /*verbose_level*/0);
printerror = 0;
 1366                         } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
MSG_EXT_PPR, FALSE)) {
 1368                                 struct ahc_initiator_tinfo *tinfo;
 1369                                 struct ahc_tmode_tstate *tstate;
 1371                                 /*
 1372                                  * PPR Rejected.  Try non-ppr negotiation
 1373                                  * and retry command.
 1374                                  */
tinfo = ahc_fetch_transinfo(ahc,
devinfo.channel,
devinfo.our_scsiid,
devinfo.target,
 1379                                                             &tstate);
tinfo->curr.transport_version = 2;
tinfo->goal.transport_version = 2;
tinfo->goal.ppr_options = 0;
ahc_qinfifo_requeue_tail(ahc, scb);
printerror = 0;
 1385                         } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
MSG_EXT_WDTR, FALSE)) {
 1387                                 /*
 1388                                  * Negotiation Rejected.  Go-narrow and
 1389                                  * retry command.
 1390                                  */
ahc_set_width(ahc, &devinfo,
MSG_EXT_WDTR_BUS_8_BIT,
AHC_TRANS_CUR|AHC_TRANS_GOAL,
 1394                                               /*paused*/TRUE);
ahc_qinfifo_requeue_tail(ahc, scb);
printerror = 0;
 1397                         } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
MSG_EXT_SDTR, FALSE)) {
 1399                                 /*
 1400                                  * Negotiation Rejected.  Go-async and
 1401                                  * retry command.
 1402                                  */
ahc_set_syncrate(ahc, &devinfo,
 1404                                                 /*syncrate*/NULL,
 1405                                                 /*period*/0, /*offset*/0,
 1406                                                 /*ppr_options*/0,
AHC_TRANS_CUR|AHC_TRANS_GOAL,
 1408                                                 /*paused*/TRUE);
ahc_qinfifo_requeue_tail(ahc, scb);
printerror = 0;
 1411                         }
 1412                 }
 1413                 if (printerror != 0) {
u_int i;
 1416                         if (scb != NULL) {
u_int tag;
 1419                                 if ((scb->hscb->control & TAG_ENB) != 0)
tag = scb->hscb->tag;
 1421                                 else
tag = SCB_LIST_NULL;
ahc_print_path(ahc, scb);
ahc_abort_scbs(ahc, target, channel,
SCB_GET_LUN(scb), tag,
ROLE_INITIATOR,
CAM_UNEXP_BUSFREE);
 1428                         } else {
 1429                                 /*
 1430                                  * We had not fully identified this connection,
 1431                                  * so we cannot abort anything.
 1432                                  */
printf("%s: ", ahc_name(ahc));
 1434                         }
 1435                         for (i = 0; i < num_phases; i++) {
 1436                                 if (lastphase == ahc_phase_table[i].phase)
 1437                                         break;
 1438                         }
 1439                         if (lastphase != P_BUSFREE) {
 1440                                 /*
 1441                                  * Renegotiate with this device at the
 1442                                  * next oportunity just in case this busfree
 1443                                  * is due to a negotiation mismatch with the
 1444                                  * device.
 1445                                  */
ahc_force_renegotiation(ahc, &devinfo);
 1447                         }
printf("Unexpected busfree %s\n"
 1449                                "SEQADDR == 0x%x\n",
ahc_phase_table[i].phasemsg,
ahc_inb(ahc, SEQADDR0)
 1452                                 | (ahc_inb(ahc, SEQADDR1) << 8));
 1453                 }
ahc_outb(ahc, CLRINT, CLRSCSIINT);
ahc_restart(ahc);
 1456         } else {
printf("%s: Missing case in ahc_handle_scsiint. status = %x\n",
ahc_name(ahc), status);
ahc_outb(ahc, CLRINT, CLRSCSIINT);
 1460         }
 1461 }
 1463 /*
 1464  * Force renegotiation to occur the next time we initiate
 1465  * a command to the current device.
 1466  */
 1467 void
ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
 1469 {
 1470         struct  ahc_initiator_tinfo *targ_info;
 1471         struct  ahc_tmode_tstate *tstate;
targ_info = ahc_fetch_transinfo(ahc,
devinfo->channel,
devinfo->our_scsiid,
devinfo->target,
 1477                                         &tstate);
ahc_update_neg_request(ahc, devinfo, tstate,
targ_info, AHC_NEG_IF_NON_ASYNC);
 1480 }
 1482 #define AHC_MAX_STEPS 2000
 1483 void
ahc_clear_critical_section(struct ahc_softc *ahc)
 1485 {
 1486         int     stepping;
 1487         int     steps;
u_int   simode0;
u_int   simode1;
 1491         if (ahc->num_critical_sections == 0)
 1492                 return;
stepping = FALSE;
steps = 0;
simode0 = 0;
simode1 = 0;
 1498         for (;;) {
 1499                 struct  cs *cs;
u_int   seqaddr;
u_int   i;
seqaddr = ahc_inb(ahc, SEQADDR0)
 1504                         | (ahc_inb(ahc, SEQADDR1) << 8);
 1506                 /*
 1507                  * Seqaddr represents the next instruction to execute, 
 1508                  * so we are really executing the instruction just
 1509                  * before it.
 1510                  */
cs = ahc->critical_sections;
 1512                 for (i = 0; i < ahc->num_critical_sections; i++, cs++) {
 1514                         if (cs->begin < seqaddr && cs->end >= seqaddr)
 1515                                 break;
 1516                 }
 1518                 if (i == ahc->num_critical_sections)
 1519                         break;
 1521                 if (steps > AHC_MAX_STEPS) {
printf("%s: Infinite loop in critical section\n",
ahc_name(ahc));
ahc_dump_card_state(ahc);
panic("critical section loop");
 1526                 }
steps++;
 1529                 if (stepping == FALSE) {
 1531                         /*
 1532                          * Disable all interrupt sources so that the
 1533                          * sequencer will not be stuck by a pausing
 1534                          * interrupt condition while we attempt to
 1535                          * leave a critical section.
 1536                          */
simode0 = ahc_inb(ahc, SIMODE0);
ahc_outb(ahc, SIMODE0, 0);
simode1 = ahc_inb(ahc, SIMODE1);
 1540                         if ((ahc->features & AHC_DT) != 0)
 1541                                 /*
 1542                                  * On DT class controllers, we
 1543                                  * use the enhanced busfree logic.
 1544                                  * Unfortunately we cannot re-enable
 1545                                  * busfree detection within the
 1546                                  * current connection, so we must
 1547                                  * leave it on while single stepping.
 1548                                  */
ahc_outb(ahc, SIMODE1, simode1 & ENBUSFREE);
 1550                         else
ahc_outb(ahc, SIMODE1, 0);
ahc_outb(ahc, CLRINT, CLRSCSIINT);
ahc_outb(ahc, SEQCTL, ahc->seqctl | STEP);
stepping = TRUE;
 1555                 }
 1556                 if ((ahc->features & AHC_DT) != 0) {
ahc_outb(ahc, CLRSINT1, CLRBUSFREE);
ahc_outb(ahc, CLRINT, CLRSCSIINT);
 1559                 }
ahc_outb(ahc, HCNTRL, ahc->unpause);
 1561                 while (!ahc_is_paused(ahc))
aic_delay(200);
 1563         }
 1564         if (stepping) {
ahc_outb(ahc, SIMODE0, simode0);
ahc_outb(ahc, SIMODE1, simode1);
ahc_outb(ahc, SEQCTL, ahc->seqctl);
 1568         }
 1569 }
 1571 /*
 1572  * Clear any pending interrupt status.
 1573  */
 1574 void
ahc_clear_intstat(struct ahc_softc *ahc)
 1576 {
 1577         /* Clear any interrupt conditions this may have caused */
ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
 1579                                 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG|
CLRREQINIT);
ahc_flush_device_writes(ahc);
ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO);
ahc_flush_device_writes(ahc);
ahc_outb(ahc, CLRINT, CLRSCSIINT);
ahc_flush_device_writes(ahc);
 1586 }
 1588 /**************************** Debugging Routines ******************************/
 1589 #ifdef AHC_DEBUG
uint32_t ahc_debug = 0; /* AHC_SHOW_MISC|AHC_SHOW_SENSE|AHC_DEBUG_OPTS;*/
 1592 void
ahc_print_scb(struct scb *scb)
 1594 {
 1595         int i;
 1597         struct hardware_scb *hscb = scb->hscb;
printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
 1600                (void *)scb,
hscb->control,
hscb->scsiid,
hscb->lun,
hscb->cdb_len);
printf("Shared Data: ");
 1606         for (i = 0; i < sizeof(hscb->shared_data.cdb); i++)
printf("%#02x", hscb->shared_data.cdb[i]);
printf("        dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n",
aic_le32toh(hscb->dataptr),
aic_le32toh(hscb->datacnt),
aic_le32toh(hscb->sgptr),
hscb->tag);
 1613         if (scb->sg_count > 0) {
 1614                 for (i = 0; i < scb->sg_count; i++) {
printf("sg[%d] - Addr 0x%x%x : Length %d\n",
i,
 1617                                (aic_le32toh(scb->sg_list[i].len) >> 24
 1618                                 & SG_HIGH_ADDR_BITS),
aic_le32toh(scb->sg_list[i].addr),
aic_le32toh(scb->sg_list[i].len));
 1621                 }
 1622         }
 1623 }
 1624 #endif
 1626 /************************* Transfer Negotiation *******************************/
 1627 /*
 1628  * Allocate per target mode instance (ID we respond to as a target)
 1629  * transfer negotiation data structures.
 1630  */
 1631 static struct ahc_tmode_tstate *
ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel)
 1633 {
 1634         struct ahc_tmode_tstate *master_tstate;
 1635         struct ahc_tmode_tstate *tstate;
 1636         int i;
master_tstate = ahc->enabled_targets[ahc->our_id];
 1639         if (channel == 'B') {
scsi_id += 8;
master_tstate = ahc->enabled_targets[ahc->our_id_b + 8];
 1642         }
 1643         if (ahc->enabled_targets[scsi_id] != NULL
 1644             && ahc->enabled_targets[scsi_id] != master_tstate)
panic("%s: ahc_alloc_tstate - Target already allocated",
ahc_name(ahc));
tstate = (struct ahc_tmode_tstate*)malloc(sizeof(*tstate),
M_DEVBUF, M_NOWAIT);
 1649         if (tstate == NULL)
 1650                 return (NULL);
 1652         /*
 1653          * If we have allocated a master tstate, copy user settings from
 1654          * the master tstate (taken from SRAM or the EEPROM) for this
 1655          * channel, but reset our current and goal settings to async/narrow
 1656          * until an initiator talks to us.
 1657          */
 1658         if (master_tstate != NULL) {
memcpy(tstate, master_tstate, sizeof(*tstate));
memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
tstate->ultraenb = 0;
 1662                 for (i = 0; i < AHC_NUM_TARGETS; i++) {
memset(&tstate->transinfo[i].curr, 0,
 1664                               sizeof(tstate->transinfo[i].curr));
memset(&tstate->transinfo[i].goal, 0,
 1666                               sizeof(tstate->transinfo[i].goal));
 1667                 }
 1668         } else
memset(tstate, 0, sizeof(*tstate));
ahc->enabled_targets[scsi_id] = tstate;
 1671         return (tstate);
 1672 }
 1674 #ifdef AHC_TARGET_MODE
 1675 /*
 1676  * Free per target mode instance (ID we respond to as a target)
 1677  * transfer negotiation data structures.
 1678  */
 1679 static void
ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force)
 1681 {
 1682         struct ahc_tmode_tstate *tstate;
 1684         /*
 1685          * Don't clean up our "master" tstate.
 1686          * It has our default user settings.
 1687          */
 1688         if (((channel == 'B' && scsi_id == ahc->our_id_b)
 1689           || (channel == 'A' && scsi_id == ahc->our_id))
 1690          && force == FALSE)
 1691                 return;
 1693         if (channel == 'B')
scsi_id += 8;
tstate = ahc->enabled_targets[scsi_id];
 1696         if (tstate != NULL)
free(tstate, M_DEVBUF);
ahc->enabled_targets[scsi_id] = NULL;
 1699 }
 1700 #endif
 1702 /*
 1703  * Called when we have an active connection to a target on the bus,
 1704  * this function finds the nearest syncrate to the input period limited
 1705  * by the capabilities of the bus connectivity of and sync settings for
 1706  * the target.
 1707  */
 1708 struct ahc_syncrate *
ahc_devlimited_syncrate(struct ahc_softc *ahc,
 1710                         struct ahc_initiator_tinfo *tinfo,
u_int *period, u_int *ppr_options, role_t role)
 1712 {
 1713         struct  ahc_transinfo *transinfo;
u_int   maxsync;
 1716         if ((ahc->features & AHC_ULTRA2) != 0) {
 1717                 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0
 1718                  && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) {
maxsync = AHC_SYNCRATE_DT;
 1720                 } else {
maxsync = AHC_SYNCRATE_ULTRA;
 1722                         /* Can't do DT on an SE bus */
 1723                         *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
 1724                 }
 1725         } else if ((ahc->features & AHC_ULTRA) != 0) {
maxsync = AHC_SYNCRATE_ULTRA;
 1727         } else {
maxsync = AHC_SYNCRATE_FAST;
 1729         }
 1730         /*
 1731          * Never allow a value higher than our current goal
 1732          * period otherwise we may allow a target initiated
 1733          * negotiation to go above the limit as set by the
 1734          * user.  In the case of an initiator initiated
 1735          * sync negotiation, we limit based on the user
 1736          * setting.  This allows the system to still accept
 1737          * incoming negotiations even if target initiated
 1738          * negotiation is not performed.
 1739          */
 1740         if (role == ROLE_TARGET)
transinfo = &tinfo->user;
 1742         else 
transinfo = &tinfo->goal;
 1744         *ppr_options &= transinfo->ppr_options;
 1745         if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
maxsync = MAX(maxsync, AHC_SYNCRATE_ULTRA2);
 1747                 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
 1748         }
 1749         if (transinfo->period == 0) {
 1750                 *period = 0;
 1751                 *ppr_options = 0;
 1752                 return (NULL);
 1753         }
 1754         *period = MAX(*period, transinfo->period);
 1755         return (ahc_find_syncrate(ahc, period, ppr_options, maxsync));
 1756 }
 1758 /*
 1759  * Look up the valid period to SCSIRATE conversion in our table.
 1760  * Return the period and offset that should be sent to the target
 1761  * if this was the beginning of an SDTR.
 1762  */
 1763 struct ahc_syncrate *
ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
u_int *ppr_options, u_int maxsync)
 1766 {
 1767         struct ahc_syncrate *syncrate;
 1769         if ((ahc->features & AHC_DT) == 0)
 1770                 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
 1772         /* Skip all DT only entries if DT is not available */
 1773         if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
 1774          && maxsync < AHC_SYNCRATE_ULTRA2)
maxsync = AHC_SYNCRATE_ULTRA2;
 1777         for (syncrate = &ahc_syncrates[maxsync];
syncrate->rate != NULL;
syncrate++) {
 1781                 /*
 1782                  * The Ultra2 table doesn't go as low
 1783                  * as for the Fast/Ultra cards.
 1784                  */
 1785                 if ((ahc->features & AHC_ULTRA2) != 0
 1786                  && (syncrate->sxfr_u2 == 0))
 1787                         break;
 1789                 if (*period <= syncrate->period) {
 1790                         /*
 1791                          * When responding to a target that requests
 1792                          * sync, the requested rate may fall between
 1793                          * two rates that we can output, but still be
 1794                          * a rate that we can receive.  Because of this,
 1795                          * we want to respond to the target with
 1796                          * the same rate that it sent to us even
 1797                          * if the period we use to send data to it
 1798                          * is lower.  Only lower the response period
 1799                          * if we must.
 1800                          */
 1801                         if (syncrate == &ahc_syncrates[maxsync])
 1802                                 *period = syncrate->period;
 1804                         /*
 1805                          * At some speeds, we only support
 1806                          * ST transfers.
 1807                          */
 1808                         if ((syncrate->sxfr_u2 & ST_SXFR) != 0)
 1809                                 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
 1810                         break;
 1811                 }
 1812         }
 1814         if ((*period == 0)
 1815          || (syncrate->rate == NULL)
 1816          || ((ahc->features & AHC_ULTRA2) != 0
 1817           && (syncrate->sxfr_u2 == 0))) {
 1818                 /* Use asynchronous transfers. */
 1819                 *period = 0;
syncrate = NULL;
 1821                 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
 1822         }
 1823         return (syncrate);
 1824 }
 1826 /*
 1827  * Convert from an entry in our syncrate table to the SCSI equivalent
 1828  * sync "period" factor.
 1829  */
u_int
ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync)
 1832 {
 1833         struct ahc_syncrate *syncrate;
 1835         if ((ahc->features & AHC_ULTRA2) != 0)
scsirate &= SXFR_ULTRA2;
 1837         else
scsirate &= SXFR;
syncrate = &ahc_syncrates[maxsync];
 1841         while (syncrate->rate != NULL) {
 1843                 if ((ahc->features & AHC_ULTRA2) != 0) {
 1844                         if (syncrate->sxfr_u2 == 0)
 1845                                 break;
 1846                         else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2))
 1847                                 return (syncrate->period);
 1848                 } else if (scsirate == (syncrate->sxfr & SXFR)) {
 1849                                 return (syncrate->period);
 1850                 }
syncrate++;
 1852         }
 1853         return (0); /* async */
 1854 }
 1856 /*
 1857  * Truncate the given synchronous offset to a value the
 1858  * current adapter type and syncrate are capable of.
 1859  */
 1860 void
ahc_validate_offset(struct ahc_softc *ahc,
 1862                     struct ahc_initiator_tinfo *tinfo,
 1863                     struct ahc_syncrate *syncrate,
u_int *offset, int wide, role_t role)
 1865 {
u_int maxoffset;
 1868         /* Limit offset to what we can do */
 1869         if (syncrate == NULL) {
maxoffset = 0;
 1871         } else if ((ahc->features & AHC_ULTRA2) != 0) {
maxoffset = MAX_OFFSET_ULTRA2;
 1873         } else {
 1874                 if (wide)
maxoffset = MAX_OFFSET_16BIT;
 1876                 else
maxoffset = MAX_OFFSET_8BIT;
 1878         }
 1879         *offset = MIN(*offset, maxoffset);
 1880         if (tinfo != NULL) {
 1881                 if (role == ROLE_TARGET)
 1882                         *offset = MIN(*offset, tinfo->user.offset);
 1883                 else
 1884                         *offset = MIN(*offset, tinfo->goal.offset);
 1885         }
 1886 }
 1888 /*
 1889  * Truncate the given transfer width parameter to a value the
 1890  * current adapter type is capable of.
 1891  */
 1892 void
ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo,
u_int *bus_width, role_t role)
 1895 {
 1896         switch (*bus_width) {
 1897         default:
 1898                 if (ahc->features & AHC_WIDE) {
 1899                         /* Respond Wide */
 1900                         *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
 1901                         break;
 1902                 }
 1903                 /* FALLTHROUGH */
 1904         case MSG_EXT_WDTR_BUS_8_BIT:
 1905                 *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
 1906                 break;
 1907         }
 1908         if (tinfo != NULL) {
 1909                 if (role == ROLE_TARGET)
 1910                         *bus_width = MIN(tinfo->user.width, *bus_width);
 1911                 else
 1912                         *bus_width = MIN(tinfo->goal.width, *bus_width);
 1913         }
 1914 }
 1916 /*
 1917  * Update the bitmask of targets for which the controller should
 1918  * negotiate with at the next convenient opportunity.  This currently
 1919  * means the next time we send the initial identify messages for
 1920  * a new transaction.
 1921  */
 1922 int
ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
 1924                        struct ahc_tmode_tstate *tstate,
 1925                        struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type)
 1926 {
u_int auto_negotiate_orig;
auto_negotiate_orig = tstate->auto_negotiate;
 1930         if (neg_type == AHC_NEG_ALWAYS) {
 1931                 /*
 1932                  * Force our "current" settings to be
 1933                  * unknown so that unless a bus reset
 1934                  * occurs the need to renegotiate is
 1935                  * recorded persistently.
 1936                  */
 1937                 if ((ahc->features & AHC_WIDE) != 0)
tinfo->curr.width = AHC_WIDTH_UNKNOWN;
tinfo->curr.period = AHC_PERIOD_UNKNOWN;
tinfo->curr.offset = AHC_OFFSET_UNKNOWN;
 1941         }
 1942         if (tinfo->curr.period != tinfo->goal.period
 1943          || tinfo->curr.width != tinfo->goal.width
 1944          || tinfo->curr.offset != tinfo->goal.offset
 1945          || tinfo->curr.ppr_options != tinfo->goal.ppr_options
 1946          || (neg_type == AHC_NEG_IF_NON_ASYNC
 1947           && (tinfo->goal.offset != 0
 1948            || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
 1949            || tinfo->goal.ppr_options != 0)))
tstate->auto_negotiate |= devinfo->target_mask;
 1951         else
tstate->auto_negotiate &= ~devinfo->target_mask;
 1954         return (auto_negotiate_orig != tstate->auto_negotiate);
 1955 }
 1957 /*
 1958  * Update the user/goal/curr tables of synchronous negotiation
 1959  * parameters as well as, in the case of a current or active update,
 1960  * any data structures on the host controller.  In the case of an
 1961  * active update, the specified target is currently talking to us on
 1962  * the bus, so the transfer parameter update must take effect
 1963  * immediately.
 1964  */
 1965 void
ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
 1967                  struct ahc_syncrate *syncrate, u_int period,
u_int offset, u_int ppr_options, u_int type, int paused)
 1969 {
 1970         struct  ahc_initiator_tinfo *tinfo;
 1971         struct  ahc_tmode_tstate *tstate;
u_int   old_period;
u_int   old_offset;
u_int   old_ppr;
 1975         int     active;
 1976         int     update_needed;
active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
update_needed = 0;
 1981         if (syncrate == NULL) {
period = 0;
offset = 0;
 1984         }
tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
devinfo->target, &tstate);
 1989         if ((type & AHC_TRANS_USER) != 0) {
tinfo->user.period = period;
tinfo->user.offset = offset;
tinfo->user.ppr_options = ppr_options;
 1993         }
 1995         if ((type & AHC_TRANS_GOAL) != 0) {
tinfo->goal.period = period;
tinfo->goal.offset = offset;
tinfo->goal.ppr_options = ppr_options;
 1999         }
old_period = tinfo->curr.period;
old_offset = tinfo->curr.offset;
old_ppr    = tinfo->curr.ppr_options;
 2005         if ((type & AHC_TRANS_CUR) != 0
 2006          && (old_period != period
 2007           || old_offset != offset
 2008           || old_ppr != ppr_options)) {
u_int   scsirate;
update_needed++;
scsirate = tinfo->scsirate;
 2013                 if ((ahc->features & AHC_ULTRA2) != 0) {
scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC);
 2016                         if (syncrate != NULL) {
scsirate |= syncrate->sxfr_u2;
 2018                                 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0)
scsirate |= ENABLE_CRC;
 2020                                 else
scsirate |= SINGLE_EDGE;
 2022                         }
 2023                 } else {
scsirate &= ~(SXFR|SOFS);
 2026                         /*
 2027                          * Ensure Ultra mode is set properly for
 2028                          * this target.
 2029                          */
tstate->ultraenb &= ~devinfo->target_mask;
 2031                         if (syncrate != NULL) {
 2032                                 if (syncrate->sxfr & ULTRA_SXFR) {
tstate->ultraenb |=
devinfo->target_mask;
 2035                                 }
scsirate |= syncrate->sxfr & SXFR;
scsirate |= offset & SOFS;
 2038                         }
 2039                         if (active) {
u_int sxfrctl0;
sxfrctl0 = ahc_inb(ahc, SXFRCTL0);
sxfrctl0 &= ~FAST20;
 2044                                 if (tstate->ultraenb & devinfo->target_mask)
sxfrctl0 |= FAST20;
ahc_outb(ahc, SXFRCTL0, sxfrctl0);
 2047                         }
 2048                 }
 2049                 if (active) {
ahc_outb(ahc, SCSIRATE, scsirate);
 2051                         if ((ahc->features & AHC_ULTRA2) != 0)
ahc_outb(ahc, SCSIOFFSET, offset);
 2053                 }
tinfo->scsirate = scsirate;
tinfo->curr.period = period;
tinfo->curr.offset = offset;
tinfo->curr.ppr_options = ppr_options;
ahc_send_async(ahc, devinfo->channel, devinfo->target,
CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
 2062                 if (1 /*bootverbose*/) {
 2063                         if (offset != 0) {
printf("%s: target %d synchronous at %sMHz%s, "
 2065                                        "offset = 0x%x\n", ahc_name(ahc),
devinfo->target, syncrate->rate,
 2067                                        (ppr_options & MSG_EXT_PPR_DT_REQ)
 2068                                        ? " DT" : "", offset);
 2069                         } else {
printf("%s: target %d using "
 2071                                        "asynchronous transfers\n",
ahc_name(ahc), devinfo->target);
 2073                         }
 2074                 }
 2075         }
update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
tinfo, AHC_NEG_TO_GOAL);
 2080         if (update_needed)
ahc_update_pending_scbs(ahc);
 2082 }
 2084 /*
 2085  * Update the user/goal/curr tables of wide negotiation
 2086  * parameters as well as, in the case of a current or active update,
 2087  * any data structures on the host controller.  In the case of an
 2088  * active update, the specified target is currently talking to us on
 2089  * the bus, so the transfer parameter update must take effect
 2090  * immediately.
 2091  */
 2092 void
ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
u_int width, u_int type, int paused)
 2095 {
 2096         struct  ahc_initiator_tinfo *tinfo;
 2097         struct  ahc_tmode_tstate *tstate;
u_int   oldwidth;
 2099         int     active;
 2100         int     update_needed;
active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
update_needed = 0;
tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
devinfo->target, &tstate);
 2107         if ((type & AHC_TRANS_USER) != 0)
tinfo->user.width = width;
 2110         if ((type & AHC_TRANS_GOAL) != 0)
tinfo->goal.width = width;
oldwidth = tinfo->curr.width;
 2114         if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) {
u_int   scsirate;
update_needed++;
scsirate =  tinfo->scsirate;
scsirate &= ~WIDEXFER;
 2120                 if (width == MSG_EXT_WDTR_BUS_16_BIT)
scsirate |= WIDEXFER;
tinfo->scsirate = scsirate;
 2125                 if (active)
ahc_outb(ahc, SCSIRATE, scsirate);
tinfo->curr.width = width;
ahc_send_async(ahc, devinfo->channel, devinfo->target,
CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
 2132                 if (1 /*bootverbose*/) {
printf("%s: target %d using %dbit transfers\n",
ahc_name(ahc), devinfo->target,
 2135                                8 * (0x01 << width));
 2136                 }
 2137         }
update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
tinfo, AHC_NEG_TO_GOAL);
 2141         if (update_needed)
ahc_update_pending_scbs(ahc);
 2143 }
 2145 /*
 2146  * Update the current state of tagged queuing for a given target.
 2147  */
 2148 void
ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
ahc_queue_alg alg)
 2151 {
ahc_platform_set_tags(ahc, devinfo, alg);
ahc_send_async(ahc, devinfo->channel, devinfo->target,
devinfo->lun, AC_TRANSFER_NEG, &alg);
 2155 }
 2157 /*
 2158  * When the transfer settings for a connection change, update any
 2159  * in-transit SCBs to contain the new data so the hardware will
 2160  * be set correctly during future (re)selections.
 2161  */
 2162 static void
ahc_update_pending_scbs(struct ahc_softc *ahc)
 2164 {
 2165         struct  scb *pending_scb;
 2166         int     pending_scb_count;
 2167         int     i;
 2168         int     paused;
u_int   saved_scbptr;
 2171         /*
 2172          * Traverse the pending SCB list and ensure that all of the
 2173          * SCBs there have the proper settings.
 2174          */
pending_scb_count = 0;
LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) {
 2177                 struct ahc_devinfo devinfo;
 2178                 struct hardware_scb *pending_hscb;
 2179                 struct ahc_initiator_tinfo *tinfo;
 2180                 struct ahc_tmode_tstate *tstate;
ahc_scb_devinfo(ahc, &devinfo, pending_scb);
tinfo = ahc_fetch_transinfo(ahc, devinfo.channel,
devinfo.our_scsiid,
devinfo.target, &tstate);
pending_hscb = pending_scb->hscb;
pending_hscb->control &= ~ULTRAENB;
 2188                 if ((tstate->ultraenb & devinfo.target_mask) != 0)
pending_hscb->control |= ULTRAENB;
pending_hscb->scsirate = tinfo->scsirate;
pending_hscb->scsioffset = tinfo->curr.offset;
 2192                 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
 2193                  && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
pending_hscb->control &= ~MK_MESSAGE;
 2196                 }
ahc_sync_scb(ahc, pending_scb,
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
pending_scb_count++;
 2200         }
 2202         if (pending_scb_count == 0)
 2203                 return;
 2205         if (ahc_is_paused(ahc)) {
paused = 1;
 2207         } else {
paused = 0;
ahc_pause(ahc);
 2210         }
saved_scbptr = ahc_inb(ahc, SCBPTR);
 2213         /* Ensure that the hscbs down on the card match the new information */
 2214         for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
 2215                 struct  hardware_scb *pending_hscb;
u_int   control;
u_int   scb_tag;
ahc_outb(ahc, SCBPTR, i);
scb_tag = ahc_inb(ahc, SCB_TAG);
pending_scb = ahc_lookup_scb(ahc, scb_tag);
 2222                 if (pending_scb == NULL)
 2223                         continue;
pending_hscb = pending_scb->hscb;
control = ahc_inb(ahc, SCB_CONTROL);
control &= ~(ULTRAENB|MK_MESSAGE);
control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE);
ahc_outb(ahc, SCB_CONTROL, control);
ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate);
ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset);
 2232         }
ahc_outb(ahc, SCBPTR, saved_scbptr);
 2235         if (paused == 0)
ahc_unpause(ahc);
 2237 }
 2239 /**************************** Pathing Information *****************************/
 2240 static void
ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
 2242 {
u_int   saved_scsiid;
role_t  role;
 2245         int     our_id;
 2247         if (ahc_inb(ahc, SSTAT0) & TARGET)
role = ROLE_TARGET;
 2249         else
role = ROLE_INITIATOR;
 2252         if (role == ROLE_TARGET
 2253          && (ahc->features & AHC_MULTI_TID) != 0
 2254          && (ahc_inb(ahc, SEQ_FLAGS)
 2255            & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) {
 2256                 /* We were selected, so pull our id from TARGIDIN */
our_id = ahc_inb(ahc, TARGIDIN) & OID;
 2258         } else if ((ahc->features & AHC_ULTRA2) != 0)
our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
 2260         else
our_id = ahc_inb(ahc, SCSIID) & OID;
saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
ahc_compile_devinfo(devinfo,
our_id,
SCSIID_TARGET(ahc, saved_scsiid),
ahc_inb(ahc, SAVED_LUN),
SCSIID_CHANNEL(ahc, saved_scsiid),
role);
 2270 }
 2272 struct ahc_phase_table_entry*
ahc_lookup_phase_entry(int phase)
 2274 {
 2275         struct ahc_phase_table_entry *entry;
 2276         struct ahc_phase_table_entry *last_entry;
 2278         /*
 2279          * num_phases doesn't include the default entry which
 2280          * will be returned if the phase doesn't match.
 2281          */
last_entry = &ahc_phase_table[num_phases];
 2283         for (entry = ahc_phase_table; entry < last_entry; entry++) {
 2284                 if (phase == entry->phase)
 2285                         break;
 2286         }
 2287         return (entry);
 2288 }
 2290 void
ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target,
u_int lun, char channel, role_t role)
 2293 {
devinfo->our_scsiid = our_id;
devinfo->target = target;
devinfo->lun = lun;
devinfo->target_offset = target;
devinfo->channel = channel;
devinfo->role = role;
 2300         if (channel == 'B')
devinfo->target_offset += 8;
devinfo->target_mask = (0x01 << devinfo->target_offset);
 2303 }
 2305 void
ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
 2307 {
printf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel,
devinfo->target, devinfo->lun);
 2310 }
 2312 void
ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
 2314                 struct scb *scb)
 2315 {
role_t  role;
 2317         int     our_id;
our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
role = ROLE_INITIATOR;
 2321         if ((scb->flags & SCB_TARGET_SCB) != 0)
role = ROLE_TARGET;
ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb),
SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role);
 2325 }
 2328 /************************ Message Phase Processing ****************************/
 2329 static void
ahc_assert_atn(struct ahc_softc *ahc)
 2331 {
u_int scsisigo;
scsisigo = ATNO;
 2335         if ((ahc->features & AHC_DT) == 0)
scsisigo |= ahc_inb(ahc, SCSISIGI);
ahc_outb(ahc, SCSISIGO, scsisigo);
 2338 }
 2340 /*
 2341  * When an initiator transaction with the MK_MESSAGE flag either reconnects
 2342  * or enters the initial message out phase, we are interrupted.  Fill our
 2343  * outgoing message buffer with the appropriate message and begin handing
 2344  * the message phase(s) manually.
 2345  */
 2346 static void
ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
 2348                            struct scb *scb)
 2349 {
 2350         /*
 2351          * To facilitate adding multiple messages together,
 2352          * each routine should increment the index and len
 2353          * variables instead of setting them explicitly.
 2354          */
ahc->msgout_index = 0;
ahc->msgout_len = 0;
 2358         if ((scb->flags & SCB_DEVICE_RESET) == 0
 2359          && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) {
u_int identify_msg;
identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
 2363                 if ((scb->hscb->control & DISCENB) != 0)
identify_msg |= MSG_IDENTIFY_DISCFLAG;
ahc->msgout_buf[ahc->msgout_index++] = identify_msg;
ahc->msgout_len++;
 2368                 if ((scb->hscb->control & TAG_ENB) != 0) {
ahc->msgout_buf[ahc->msgout_index++] =
scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag;
ahc->msgout_len += 2;
 2373                 }
 2374         }
 2376         if (scb->flags & SCB_DEVICE_RESET) {
ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET;
ahc->msgout_len++;
ahc_print_path(ahc, scb);
printf("Bus Device Reset Message Sent\n");
 2381                 /*
 2382                  * Clear our selection hardware in advance of
 2383                  * the busfree.  We may have an entry in the waiting
 2384                  * Q for this target, and we don't want to go about
 2385                  * selecting while we handle the busfree and blow it
 2386                  * away.
 2387                  */
ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
 2389         } else if ((scb->flags & SCB_ABORT) != 0) {
 2390                 if ((scb->hscb->control & TAG_ENB) != 0)
ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG;
 2392                 else
ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT;
ahc->msgout_len++;
ahc_print_path(ahc, scb);
printf("Abort%s Message Sent\n",
 2397                        (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
 2398                 /*
 2399                  * Clear our selection hardware in advance of
 2400                  * the busfree.  We may have an entry in the waiting
 2401                  * Q for this target, and we don't want to go about
 2402                  * selecting while we handle the busfree and blow it
 2403                  * away.
 2404                  */
ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
 2406         } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
ahc_build_transfer_msg(ahc, devinfo);
 2408         } else {
printf("ahc_intr: AWAITING_MSG for an SCB that "
 2410                        "does not have a waiting message\n");
printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
devinfo->target_mask);
panic("SCB = %d, SCB Control = %x, MSG_OUT = %x "
 2414                       "SCB flags = %x", scb->hscb->tag, scb->hscb->control,
ahc_inb(ahc, MSG_OUT), scb->flags);
 2416         }
 2418         /*
 2419          * Clear the MK_MESSAGE flag from the SCB so we aren't
 2420          * asked to send this message again.
 2421          */
ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE);
scb->hscb->control &= ~MK_MESSAGE;
ahc->msgout_index = 0;
ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
 2426 }
 2428 /*
 2429  * Build an appropriate transfer negotiation message for the
 2430  * currently active target.
 2431  */
 2432 static void
ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
 2434 {
 2435         /*
 2436          * We need to initiate transfer negotiations.
 2437          * If our current and goal settings are identical,
 2438          * we want to renegotiate due to a check condition.
 2439          */
 2440         struct  ahc_initiator_tinfo *tinfo;
 2441         struct  ahc_tmode_tstate *tstate;
 2442         struct  ahc_syncrate *rate;
 2443         int     dowide;
 2444         int     dosync;
 2445         int     doppr;
u_int   period;
u_int   ppr_options;
u_int   offset;
tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
devinfo->target, &tstate);
 2452         /*
 2453          * Filter our period based on the current connection.
 2454          * If we can't perform DT transfers on this segment (not in LVD
 2455          * mode for instance), then our decision to issue a PPR message
 2456          * may change.
 2457          */
period = tinfo->goal.period;
offset = tinfo->goal.offset;
ppr_options = tinfo->goal.ppr_options;
 2461         /* Target initiated PPR is not allowed in the SCSI spec */
 2462         if (devinfo->role == ROLE_TARGET)
ppr_options = 0;
rate = ahc_devlimited_syncrate(ahc, tinfo, &period,
 2465                                        &ppr_options, devinfo->role);
dowide = tinfo->curr.width != tinfo->goal.width;
dosync = tinfo->curr.offset != offset || tinfo->curr.period != period;
 2468         /*
 2469          * Only use PPR if we have options that need it, even if the device
 2470          * claims to support it.  There might be an expander in the way
 2471          * that doesn't.
 2472          */
doppr = ppr_options != 0;
 2475         if (!dowide && !dosync && !doppr) {
dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
dosync = tinfo->goal.offset != 0;
 2478         }
 2480         if (!dowide && !dosync && !doppr) {
 2481                 /*
 2482                  * Force async with a WDTR message if we have a wide bus,
 2483                  * or just issue an SDTR with a 0 offset.
 2484                  */
 2485                 if ((ahc->features & AHC_WIDE) != 0)
dowide = 1;
 2487                 else
dosync = 1;
 2490                 if (bootverbose) {
ahc_print_devinfo(ahc, devinfo);
printf("Ensuring async\n");
 2493                 }
 2494         }
 2496         /* Target initiated PPR is not allowed in the SCSI spec */
 2497         if (devinfo->role == ROLE_TARGET)
doppr = 0;
 2500         /*
 2501          * Both the PPR message and SDTR message require the
 2502          * goal syncrate to be limited to what the target device
 2503          * is capable of handling (based on whether an LVD->SE
 2504          * expander is on the bus), so combine these two cases.
 2505          * Regardless, guarantee that if we are using WDTR and SDTR
 2506          * messages that WDTR comes first.
 2507          */
 2508         if (doppr || (dosync && !dowide)) {
offset = tinfo->goal.offset;
ahc_validate_offset(ahc, tinfo, rate, &offset,
doppr ? tinfo->goal.width
 2513                                           : tinfo->curr.width,
devinfo->role);
 2515                 if (doppr) {
ahc_construct_ppr(ahc, devinfo, period, offset,
tinfo->goal.width, ppr_options);
 2518                 } else {
ahc_construct_sdtr(ahc, devinfo, period, offset);
 2520                 }
 2521         } else {
ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width);
 2523         }
 2524 }
 2526 /*
 2527  * Build a synchronous negotiation message in our message
 2528  * buffer based on the input parameters.
 2529  */
 2530 static void
ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
u_int period, u_int offset)
 2533 {
 2534         if (offset == 0)
period = AHC_ASYNC_XFER_PERIOD;
ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN;
ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR;
ahc->msgout_buf[ahc->msgout_index++] = period;
ahc->msgout_buf[ahc->msgout_index++] = offset;
ahc->msgout_len += 5;
 2542         if (bootverbose) {
printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
ahc_name(ahc), devinfo->channel, devinfo->target,
devinfo->lun, period, offset);
 2546         }
 2547 }
 2549 /*
 2550  * Build a wide negotiation message in our message
 2551  * buffer based on the input parameters.
 2552  */
 2553 static void
ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
u_int bus_width)
 2556 {
ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN;
ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR;
ahc->msgout_buf[ahc->msgout_index++] = bus_width;
ahc->msgout_len += 4;
 2562         if (bootverbose) {
printf("(%s:%c:%d:%d): Sending WDTR %x\n",
ahc_name(ahc), devinfo->channel, devinfo->target,
devinfo->lun, bus_width);
 2566         }
 2567 }
 2569 /*
 2570  * Build a parallel protocol request message in our message
 2571  * buffer based on the input parameters.
 2572  */
 2573 static void
ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
u_int period, u_int offset, u_int bus_width,
u_int ppr_options)
 2577 {
 2578         if (offset == 0)
period = AHC_ASYNC_XFER_PERIOD;
ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN;
ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR;
ahc->msgout_buf[ahc->msgout_index++] = period;
ahc->msgout_buf[ahc->msgout_index++] = 0;
ahc->msgout_buf[ahc->msgout_index++] = offset;
ahc->msgout_buf[ahc->msgout_index++] = bus_width;
ahc->msgout_buf[ahc->msgout_index++] = ppr_options;
ahc->msgout_len += 8;
 2589         if (bootverbose) {
printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
 2591                        "offset %x, ppr_options %x\n", ahc_name(ahc),
devinfo->channel, devinfo->target, devinfo->lun,
bus_width, period, offset, ppr_options);
 2594         }
 2595 }
 2597 /*
 2598  * Clear any active message state.
 2599  */
 2600 static void
ahc_clear_msg_state(struct ahc_softc *ahc)
 2602 {
ahc->msgout_len = 0;
ahc->msgin_index = 0;
ahc->msg_type = MSG_TYPE_NONE;
 2606         if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) {
 2607                 /*
 2608                  * The target didn't care to respond to our
 2609                  * message request, so clear ATN.
 2610                  */
ahc_outb(ahc, CLRSINT1, CLRATNO);
 2612         }
ahc_outb(ahc, MSG_OUT, MSG_NOOP);
ahc_outb(ahc, SEQ_FLAGS2,
ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
 2616 }
 2618 static void
ahc_handle_proto_violation(struct ahc_softc *ahc)
 2620 {
 2621         struct  ahc_devinfo devinfo;
 2622         struct  scb *scb;
u_int   scbid;
u_int   seq_flags;
u_int   curphase;
u_int   lastphase;
 2627         int     found;
ahc_fetch_devinfo(ahc, &devinfo);
scbid = ahc_inb(ahc, SCB_TAG);
scb = ahc_lookup_scb(ahc, scbid);
seq_flags = ahc_inb(ahc, SEQ_FLAGS);
curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
lastphase = ahc_inb(ahc, LASTPHASE);
 2635         if ((seq_flags & NOT_IDENTIFIED) != 0) {
 2637                 /*
 2638                  * The reconnecting target either did not send an
 2639                  * identify message, or did, but we didn't find an SCB
 2640                  * to match.
 2641                  */
ahc_print_devinfo(ahc, &devinfo);
printf("Target did not send an IDENTIFY message. "
 2644                        "LASTPHASE = 0x%x.\n", lastphase);
scb = NULL;
 2646         } else if (scb == NULL) {
 2647                 /*
 2648                  * We don't seem to have an SCB active for this
 2649                  * transaction.  Print an error and reset the bus.
 2650                  */
ahc_print_devinfo(ahc, &devinfo);
printf("No SCB found during protocol violation\n");
 2653                 goto proto_violation_reset;
 2654         } else {
ahc_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
 2656                 if ((seq_flags & NO_CDB_SENT) != 0) {
ahc_print_path(ahc, scb);
printf("No or incomplete CDB sent to device.\n");
 2659                 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) {
 2660                         /*
 2661                          * The target never bothered to provide status to
 2662                          * us prior to completing the command.  Since we don't
 2663                          * know the disposition of this command, we must attempt
 2664                          * to abort it.  Assert ATN and prepare to send an abort
 2665                          * message.
 2666                          */
ahc_print_path(ahc, scb);
printf("Completed command without status.\n");
 2669                 } else {
ahc_print_path(ahc, scb);
printf("Unknown protocol violation.\n");
ahc_dump_card_state(ahc);
 2673                 }
 2674         }
 2675         if ((lastphase & ~P_DATAIN_DT) == 0
 2676          || lastphase == P_COMMAND) {
proto_violation_reset:
 2678                 /*
 2679                  * Target either went directly to data/command
 2680                  * phase or didn't respond to our ATN.
 2681                  * The only safe thing to do is to blow
 2682                  * it away with a bus reset.
 2683                  */
found = ahc_reset_channel(ahc, 'A', TRUE);
printf("%s: Issued Channel %c Bus Reset. "
 2686                        "%d SCBs aborted\n", ahc_name(ahc), 'A', found);
 2687         } else {
 2688                 /*
 2689                  * Leave the selection hardware off in case
 2690                  * this abort attempt will affect yet to
 2691                  * be sent commands.
 2692                  */
ahc_outb(ahc, SCSISEQ,
ahc_inb(ahc, SCSISEQ) & ~ENSELO);
ahc_assert_atn(ahc);
ahc_outb(ahc, MSG_OUT, HOST_MSG);
 2697                 if (scb == NULL) {
ahc_print_devinfo(ahc, &devinfo);
ahc->msgout_buf[0] = MSG_ABORT_TASK;
ahc->msgout_len = 1;
ahc->msgout_index = 0;
ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
 2703                 } else {
ahc_print_path(ahc, scb);
scb->flags |= SCB_ABORT;
 2706                 }
printf("Protocol violation %s.  Attempting to abort.\n",
ahc_lookup_phase_entry(curphase)->phasemsg);
 2709         }
 2710 }
 2712 /*
 2713  * Manual message loop handler.
 2714  */
 2715 static void
ahc_handle_message_phase(struct ahc_softc *ahc)
 2717 { 
 2718         struct  ahc_devinfo devinfo;
u_int   bus_phase;
 2720         int     end_session;
ahc_fetch_devinfo(ahc, &devinfo);
end_session = FALSE;
bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
reswitch:
 2727         switch (ahc->msg_type) {
 2728         case MSG_TYPE_INITIATOR_MSGOUT:
 2729         {
 2730                 int lastbyte;
 2731                 int phasemis;
 2732                 int msgdone;
 2734                 if (ahc->msgout_len == 0)
panic("HOST_MSG_LOOP interrupt with no active message");
 2737 #ifdef AHC_DEBUG
 2738                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
ahc_print_devinfo(ahc, &devinfo);
printf("INITIATOR_MSG_OUT");
 2741                 }
 2742 #endif
phasemis = bus_phase != P_MESGOUT;
 2744                 if (phasemis) {
 2745 #ifdef AHC_DEBUG
 2746                         if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
printf(" PHASEMIS %s\n",
ahc_lookup_phase_entry(bus_phase)
 2749                                                              ->phasemsg);
 2750                         }
 2751 #endif
 2752                         if (bus_phase == P_MESGIN) {
 2753                                 /*
 2754                                  * Change gears and see if
 2755                                  * this messages is of interest to
 2756                                  * us or should be passed back to
 2757                                  * the sequencer.
 2758                                  */
ahc_outb(ahc, CLRSINT1, CLRATNO);
ahc->send_msg_perror = FALSE;
ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN;
ahc->msgin_index = 0;
 2763                                 goto reswitch;
 2764                         }
end_session = TRUE;
 2766                         break;
 2767                 }
 2769                 if (ahc->send_msg_perror) {
ahc_outb(ahc, CLRSINT1, CLRATNO);
ahc_outb(ahc, CLRSINT1, CLRREQINIT);
 2772 #ifdef AHC_DEBUG
 2773                         if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
printf(" byte 0x%x\n", ahc->send_msg_perror);
 2775 #endif
ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR);
 2777                         break;
 2778                 }
msgdone = ahc->msgout_index == ahc->msgout_len;
 2781                 if (msgdone) {
 2782                         /*
 2783                          * The target has requested a retry.
 2784                          * Re-assert ATN, reset our message index to
 2785                          * 0, and try again.
 2786                          */
ahc->msgout_index = 0;
ahc_assert_atn(ahc);
 2789                 }
lastbyte = ahc->msgout_index == (ahc->msgout_len - 1);
 2792                 if (lastbyte) {
 2793                         /* Last byte is signified by dropping ATN */
ahc_outb(ahc, CLRSINT1, CLRATNO);
 2795                 }
 2797                 /*
 2798                  * Clear our interrupt status and present
 2799                  * the next byte on the bus.
 2800                  */
ahc_outb(ahc, CLRSINT1, CLRREQINIT);
 2802 #ifdef AHC_DEBUG
 2803                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
printf(" byte 0x%x\n",
ahc->msgout_buf[ahc->msgout_index]);
 2806 #endif
ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
 2808                 break;
 2809         }
 2810         case MSG_TYPE_INITIATOR_MSGIN:
 2811         {
 2812                 int phasemis;
 2813                 int message_done;
 2815 #ifdef AHC_DEBUG
 2816                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
ahc_print_devinfo(ahc, &devinfo);
printf("INITIATOR_MSG_IN");
 2819                 }
 2820 #endif
phasemis = bus_phase != P_MESGIN;
 2822                 if (phasemis) {
 2823 #ifdef AHC_DEBUG
 2824                         if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
printf(" PHASEMIS %s\n",
ahc_lookup_phase_entry(bus_phase)
 2827                                                              ->phasemsg);
 2828                         }
 2829 #endif
ahc->msgin_index = 0;
 2831                         if (bus_phase == P_MESGOUT
 2832                          && (ahc->send_msg_perror == TRUE
 2833                           || (ahc->msgout_len != 0
 2834                            && ahc->msgout_index == 0))) {
ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
 2836                                 goto reswitch;
 2837                         }
end_session = TRUE;
 2839                         break;
 2840                 }
 2842                 /* Pull the byte in without acking it */
ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL);
 2844 #ifdef AHC_DEBUG
 2845                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
printf(" byte 0x%x\n",
ahc->msgin_buf[ahc->msgin_index]);
 2848 #endif
message_done = ahc_parse_msg(ahc, &devinfo);
 2852                 if (message_done) {
 2853                         /*
 2854                          * Clear our incoming message buffer in case there
 2855                          * is another message following this one.
 2856                          */
ahc->msgin_index = 0;
 2859                         /*
 2860                          * If this message illicited a response,
 2861                          * assert ATN so the target takes us to the
 2862                          * message out phase.
 2863                          */
 2864                         if (ahc->msgout_len != 0) {
 2865 #ifdef AHC_DEBUG
 2866                                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
ahc_print_devinfo(ahc, &devinfo);
printf("Asserting ATN for response\n");
 2869                                 }
 2870 #endif
ahc_assert_atn(ahc);
 2872                         }
 2873                 } else 
ahc->msgin_index++;
 2876                 if (message_done == MSGLOOP_TERMINATED) {
end_session = TRUE;
 2878                 } else {
 2879                         /* Ack the byte */
ahc_outb(ahc, CLRSINT1, CLRREQINIT);
ahc_inb(ahc, SCSIDATL);
 2882                 }
 2883                 break;
 2884         }
 2885         case MSG_TYPE_TARGET_MSGIN:
 2886         {
 2887                 int msgdone;
 2888                 int msgout_request;
 2890                 if (ahc->msgout_len == 0)
panic("Target MSGIN with no active message");
 2893                 /*
 2894                  * If we interrupted a mesgout session, the initiator
 2895                  * will not know this until our first REQ.  So, we
 2896                  * only honor mesgout requests after we've sent our
 2897                  * first byte.
 2898                  */
 2899                 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0
 2900                  && ahc->msgout_index > 0)
msgout_request = TRUE;
 2902                 else
msgout_request = FALSE;
 2905                 if (msgout_request) {
 2907                         /*
 2908                          * Change gears and see if
 2909                          * this messages is of interest to
 2910                          * us or should be passed back to
 2911                          * the sequencer.
 2912                          */
ahc->msg_type = MSG_TYPE_TARGET_MSGOUT;
ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO);
ahc->msgin_index = 0;
 2916                         /* Dummy read to REQ for first byte */
ahc_inb(ahc, SCSIDATL);
ahc_outb(ahc, SXFRCTL0,
ahc_inb(ahc, SXFRCTL0) | SPIOEN);
 2920                         break;
 2921                 }
msgdone = ahc->msgout_index == ahc->msgout_len;
 2924                 if (msgdone) {
ahc_outb(ahc, SXFRCTL0,
ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
end_session = TRUE;
 2928                         break;
 2929                 }
 2931                 /*
 2932                  * Present the next byte on the bus.
 2933                  */
ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN);
ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
 2936                 break;
 2937         }
 2938         case MSG_TYPE_TARGET_MSGOUT:
 2939         {
 2940                 int lastbyte;
 2941                 int msgdone;
 2943                 /*
 2944                  * The initiator signals that this is
 2945                  * the last byte by dropping ATN.
 2946                  */
lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0;
 2949                 /*
 2950                  * Read the latched byte, but turn off SPIOEN first
 2951                  * so that we don't inadvertently cause a REQ for the
 2952                  * next byte.
 2953                  */
ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL);
msgdone = ahc_parse_msg(ahc, &devinfo);
 2957                 if (msgdone == MSGLOOP_TERMINATED) {
 2958                         /*
 2959                          * The message is *really* done in that it caused
 2960                          * us to go to bus free.  The sequencer has already
 2961                          * been reset at this point, so pull the ejection
 2962                          * handle.
 2963                          */
 2964                         return;
 2965                 }
ahc->msgin_index++;
 2969                 /*
 2970                  * XXX Read spec about initiator dropping ATN too soon
 2971                  *     and use msgdone to detect it.
 2972                  */
 2973                 if (msgdone == MSGLOOP_MSGCOMPLETE) {
ahc->msgin_index = 0;
 2976                         /*
 2977                          * If this message illicited a response, transition
 2978                          * to the Message in phase and send it.
 2979                          */
 2980                         if (ahc->msgout_len != 0) {
ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO);
ahc_outb(ahc, SXFRCTL0,
ahc_inb(ahc, SXFRCTL0) | SPIOEN);
ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
ahc->msgin_index = 0;
 2986                                 break;
 2987                         }
 2988                 }
 2990                 if (lastbyte)
end_session = TRUE;
 2992                 else {
 2993                         /* Ask for the next byte. */
ahc_outb(ahc, SXFRCTL0,
ahc_inb(ahc, SXFRCTL0) | SPIOEN);
 2996                 }
 2998                 break;
 2999         }
 3000         default:
panic("Unknown REQINIT message type");
 3002         }
 3004         if (end_session) {
ahc_clear_msg_state(ahc);
ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP);
 3007         } else
ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP);
 3009 }
 3011 /*
 3012  * See if we sent a particular extended message to the target.
 3013  * If "full" is true, return true only if the target saw the full
 3014  * message.  If "full" is false, return true if the target saw at
 3015  * least the first byte of the message.
 3016  */
 3017 static int
ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full)
 3019 {
 3020         int found;
u_int index;
found = FALSE;
index = 0;
 3026         while (index < ahc->msgout_len) {
 3027                 if (ahc->msgout_buf[index] == MSG_EXTENDED) {
u_int end_index;
end_index = index + 1 + ahc->msgout_buf[index + 1];
 3031                         if (ahc->msgout_buf[index+2] == msgval
 3032                          && type == AHCMSG_EXT) {
 3034                                 if (full) {
 3035                                         if (ahc->msgout_index > end_index)
found = TRUE;
 3037                                 } else if (ahc->msgout_index > index)
found = TRUE;
 3039                         }
index = end_index;
 3041                 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK
 3042                         && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
 3044                         /* Skip tag type and tag id or residue param*/
index += 2;
 3046                 } else {
 3047                         /* Single byte message */
 3048                         if (type == AHCMSG_1B
 3049                          && ahc->msgout_buf[index] == msgval
 3050                          && ahc->msgout_index > index)
found = TRUE;
index++;
 3053                 }
 3055                 if (found)
 3056                         break;
 3057         }
 3058         return (found);
 3059 }
 3061 /*
 3062  * Wait for a complete incoming message, parse it, and respond accordingly.
 3063  */
 3064 static int
ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
 3066 {
 3067         struct  ahc_initiator_tinfo *tinfo;
 3068         struct  ahc_tmode_tstate *tstate;
 3069         int     reject;
 3070         int     done;
 3071         int     response;
u_int   targ_scsirate;
done = MSGLOOP_IN_PROG;
response = FALSE;
reject = FALSE;
tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
devinfo->target, &tstate);
targ_scsirate = tinfo->scsirate;
 3081         /*
 3082          * Parse as much of the message as is available,
 3083          * rejecting it if we don't support it.  When
 3084          * the entire message is available and has been
 3085          * handled, return MSGLOOP_MSGCOMPLETE, indicating
 3086          * that we have parsed an entire message.
 3087          *
 3088          * In the case of extended messages, we accept the length
 3089          * byte outright and perform more checking once we know the
 3090          * extended message type.
 3091          */
 3092         switch (ahc->msgin_buf[0]) {
 3093         case MSG_DISCONNECT:
 3094         case MSG_SAVEDATAPOINTER:
 3095         case MSG_CMDCOMPLETE:
 3096         case MSG_RESTOREPOINTERS:
 3097         case MSG_IGN_WIDE_RESIDUE:
 3098                 /*
 3099                  * End our message loop as these are messages
 3100                  * the sequencer handles on its own.
 3101                  */
done = MSGLOOP_TERMINATED;
 3103                 break;
 3104         case MSG_MESSAGE_REJECT:
response = ahc_handle_msg_reject(ahc, devinfo);
 3106                 /* FALLTHROUGH */
 3107         case MSG_NOOP:
done = MSGLOOP_MSGCOMPLETE;
 3109                 break;
 3110         case MSG_EXTENDED:
 3111         {
 3112                 /* Wait for enough of the message to begin validation */
 3113                 if (ahc->msgin_index < 2)
 3114                         break;
 3115                 switch (ahc->msgin_buf[2]) {
 3116                 case MSG_EXT_SDTR:
 3117                 {
 3118                         struct   ahc_syncrate *syncrate;
u_int    period;
u_int    ppr_options;
u_int    offset;
u_int    saved_offset;
 3124                         if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
reject = TRUE;
 3126                                 break;
 3127                         }
 3129                         /*
 3130                          * Wait until we have both args before validating
 3131                          * and acting on this message.
 3132                          *
 3133                          * Add one to MSG_EXT_SDTR_LEN to account for
 3134                          * the extended message preamble.
 3135                          */
 3136                         if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1))
 3137                                 break;
period = ahc->msgin_buf[3];
ppr_options = 0;
saved_offset = offset = ahc->msgin_buf[4];
syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
 3143                                                            &ppr_options,
devinfo->role);
ahc_validate_offset(ahc, tinfo, syncrate, &offset,
targ_scsirate & WIDEXFER,
devinfo->role);
 3148                         if (bootverbose) {
printf("(%s:%c:%d:%d): Received "
 3150                                        "SDTR period %x, offset %x\n\t"
 3151                                        "Filtered to period %x, offset %x\n",
ahc_name(ahc), devinfo->channel,
devinfo->target, devinfo->lun,
ahc->msgin_buf[3], saved_offset,
period, offset);
 3156                         }
ahc_set_syncrate(ahc, devinfo, 
syncrate, period,
offset, ppr_options,
AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
 3161                                          /*paused*/TRUE);
 3163                         /*
 3164                          * See if we initiated Sync Negotiation
 3165                          * and didn't have to fall down to async
 3166                          * transfers.
 3167                          */
 3168                         if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) {
 3169                                 /* We started it */
 3170                                 if (saved_offset != offset) {
 3171                                         /* Went too low - force async */
reject = TRUE;
 3173                                 }
 3174                         } else {
 3175                                 /*
 3176                                  * Send our own SDTR in reply
 3177                                  */
 3178                                 if (bootverbose
 3179                                  && devinfo->role == ROLE_INITIATOR) {
printf("(%s:%c:%d:%d): Target "
 3181                                                "Initiated SDTR\n",
ahc_name(ahc), devinfo->channel,
devinfo->target, devinfo->lun);
 3184                                 }
ahc->msgout_index = 0;
ahc->msgout_len = 0;
ahc_construct_sdtr(ahc, devinfo,
period, offset);
ahc->msgout_index = 0;
response = TRUE;
 3191                         }
done = MSGLOOP_MSGCOMPLETE;
 3193                         break;
 3194                 }
 3195                 case MSG_EXT_WDTR:
 3196                 {
u_int bus_width;
u_int saved_width;
u_int sending_reply;
sending_reply = FALSE;
 3202                         if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
reject = TRUE;
 3204                                 break;
 3205                         }
 3207                         /*
 3208                          * Wait until we have our arg before validating
 3209                          * and acting on this message.
 3210                          *
 3211                          * Add one to MSG_EXT_WDTR_LEN to account for
 3212                          * the extended message preamble.
 3213                          */
 3214                         if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1))
 3215                                 break;
bus_width = ahc->msgin_buf[3];
saved_width = bus_width;
ahc_validate_width(ahc, tinfo, &bus_width,
devinfo->role);
 3221                         if (bootverbose) {
printf("(%s:%c:%d:%d): Received WDTR "
 3223                                        "%x filtered to %x\n",
ahc_name(ahc), devinfo->channel,
devinfo->target, devinfo->lun,
saved_width, bus_width);
 3227                         }
 3229                         if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) {
 3230                                 /*
 3231                                  * Don't send a WDTR back to the
 3232                                  * target, since we asked first.
 3233                                  * If the width went higher than our
 3234                                  * request, reject it.
 3235                                  */
 3236                                 if (saved_width > bus_width) {
reject = TRUE;
printf("(%s:%c:%d:%d): requested %dBit "
 3239                                                "transfers.  Rejecting...\n",
ahc_name(ahc), devinfo->channel,
devinfo->target, devinfo->lun,
 3242                                                8 * (0x01 << bus_width));
bus_width = 0;
 3244                                 }
 3245                         } else {
 3246                                 /*
 3247                                  * Send our own WDTR in reply
 3248                                  */
 3249                                 if (bootverbose
 3250                                  && devinfo->role == ROLE_INITIATOR) {
printf("(%s:%c:%d:%d): Target "
 3252                                                "Initiated WDTR\n",
ahc_name(ahc), devinfo->channel,
devinfo->target, devinfo->lun);
 3255                                 }
ahc->msgout_index = 0;
ahc->msgout_len = 0;
ahc_construct_wdtr(ahc, devinfo, bus_width);
ahc->msgout_index = 0;
response = TRUE;
sending_reply = TRUE;
 3262                         }
 3263                         /*
 3264                          * After a wide message, we are async, but
 3265                          * some devices don't seem to honor this portion
 3266                          * of the spec.  Force a renegotiation of the
 3267                          * sync component of our transfer agreement even
 3268                          * if our goal is async.  By updating our width
 3269                          * after forcing the negotiation, we avoid
 3270                          * renegotiating for width.
 3271                          */
ahc_update_neg_request(ahc, devinfo, tstate,
tinfo, AHC_NEG_ALWAYS);
ahc_set_width(ahc, devinfo, bus_width,
AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
 3276                                       /*paused*/TRUE);
 3277                         if (sending_reply == FALSE && reject == FALSE) {
 3279                                 /*
 3280                                  * We will always have an SDTR to send.
 3281                                  */
ahc->msgout_index = 0;
ahc->msgout_len = 0;
ahc_build_transfer_msg(ahc, devinfo);
ahc->msgout_index = 0;
response = TRUE;
 3287                         }
done = MSGLOOP_MSGCOMPLETE;
 3289                         break;
 3290                 }
 3291                 case MSG_EXT_PPR:
 3292                 {
 3293                         struct  ahc_syncrate *syncrate;
u_int   period;
u_int   offset;
u_int   bus_width;
u_int   ppr_options;
u_int   saved_width;
u_int   saved_offset;
u_int   saved_ppr_options;
 3302                         if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) {
reject = TRUE;
 3304                                 break;
 3305                         }
 3307                         /*
 3308                          * Wait until we have all args before validating
 3309                          * and acting on this message.
 3310                          *
 3311                          * Add one to MSG_EXT_PPR_LEN to account for
 3312                          * the extended message preamble.
 3313                          */
 3314                         if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1))
 3315                                 break;
period = ahc->msgin_buf[3];
offset = ahc->msgin_buf[5];
bus_width = ahc->msgin_buf[6];
saved_width = bus_width;
ppr_options = ahc->msgin_buf[7];
 3322                         /*
 3323                          * According to the spec, a DT only
 3324                          * period factor with no DT option
 3325                          * set implies async.
 3326                          */
 3327                         if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
 3328                          && period == 9)
offset = 0;
saved_ppr_options = ppr_options;
saved_offset = offset;
 3333                         /*
 3334                          * Mask out any options we don't support
 3335                          * on any controller.  Transfer options are
 3336                          * only available if we are negotiating wide.
 3337                          */
ppr_options &= MSG_EXT_PPR_DT_REQ;
 3339                         if (bus_width == 0)
ppr_options = 0;
ahc_validate_width(ahc, tinfo, &bus_width,
devinfo->role);
syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
 3345                                                            &ppr_options,
devinfo->role);
ahc_validate_offset(ahc, tinfo, syncrate,
 3348                                             &offset, bus_width,
devinfo->role);
 3351                         if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) {
 3352                                 /*
 3353                                  * If we are unable to do any of the
 3354                                  * requested options (we went too low),
 3355                                  * then we'll have to reject the message.
 3356                                  */
 3357                                 if (saved_width > bus_width
 3358                                  || saved_offset != offset
 3359                                  || saved_ppr_options != ppr_options) {
reject = TRUE;
period = 0;
offset = 0;
bus_width = 0;
ppr_options = 0;
syncrate = NULL;
 3366                                 }
 3367                         } else {
 3368                                 if (devinfo->role != ROLE_TARGET)
printf("(%s:%c:%d:%d): Target "
 3370                                                "Initiated PPR\n",
ahc_name(ahc), devinfo->channel,
devinfo->target, devinfo->lun);
 3373                                 else
printf("(%s:%c:%d:%d): Initiator "
 3375                                                "Initiated PPR\n",
ahc_name(ahc), devinfo->channel,
devinfo->target, devinfo->lun);
ahc->msgout_index = 0;
ahc->msgout_len = 0;
ahc_construct_ppr(ahc, devinfo, period, offset,
bus_width, ppr_options);
ahc->msgout_index = 0;
response = TRUE;
 3384                         }
 3385                         if (bootverbose) {
printf("(%s:%c:%d:%d): Received PPR width %x, "
 3387                                        "period %x, offset %x,options %x\n"
 3388                                        "\tFiltered to width %x, period %x, "
 3389                                        "offset %x, options %x\n",
ahc_name(ahc), devinfo->channel,
devinfo->target, devinfo->lun,
saved_width, ahc->msgin_buf[3],
saved_offset, saved_ppr_options,
bus_width, period, offset, ppr_options);
 3395                         }
ahc_set_width(ahc, devinfo, bus_width,
AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
 3398                                       /*paused*/TRUE);
ahc_set_syncrate(ahc, devinfo,
syncrate, period,
offset, ppr_options,
AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
 3403                                          /*paused*/TRUE);
done = MSGLOOP_MSGCOMPLETE;
 3405                         break;
 3406                 }
 3407                 default:
 3408                         /* Unknown extended message.  Reject it. */
reject = TRUE;
 3410                         break;
 3411                 }
 3412                 break;
 3413         }
 3414 #ifdef AHC_TARGET_MODE
 3415         case MSG_BUS_DEV_RESET:
ahc_handle_devreset(ahc, devinfo,
CAM_BDR_SENT,
 3418                                     "Bus Device Reset Received",
 3419                                     /*verbose_level*/0);
ahc_restart(ahc);
done = MSGLOOP_TERMINATED;
 3422                 break;
 3423         case MSG_ABORT_TAG:
 3424         case MSG_ABORT:
 3425         case MSG_CLEAR_QUEUE:
 3426         {
 3427                 int tag;
 3429                 /* Target mode messages */
 3430                 if (devinfo->role != ROLE_TARGET) {
reject = TRUE;
 3432                         break;
 3433                 }
tag = SCB_LIST_NULL;
 3435                 if (ahc->msgin_buf[0] == MSG_ABORT_TAG)
tag = ahc_inb(ahc, INITIATOR_TAG);
ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
devinfo->lun, tag, ROLE_TARGET,
CAM_REQ_ABORTED);
tstate = ahc->enabled_targets[devinfo->our_scsiid];
 3442                 if (tstate != NULL) {
 3443                         struct ahc_tmode_lstate* lstate;
lstate = tstate->enabled_luns[devinfo->lun];
 3446                         if (lstate != NULL) {
ahc_queue_lstate_event(ahc, lstate,
devinfo->our_scsiid,
ahc->msgin_buf[0],
 3450                                                        /*arg*/tag);
ahc_send_lstate_events(ahc, lstate);
 3452                         }
 3453                 }
ahc_restart(ahc);
done = MSGLOOP_TERMINATED;
 3456                 break;
 3457         }
 3458 #endif
 3459         case MSG_TERM_IO_PROC:
 3460         default:
reject = TRUE;
 3462                 break;
 3463         }
 3465         if (reject) {
 3466                 /*
 3467                  * Setup to reject the message.
 3468                  */
ahc->msgout_index = 0;
ahc->msgout_len = 1;
ahc->msgout_buf[0] = MSG_MESSAGE_REJECT;
done = MSGLOOP_MSGCOMPLETE;
response = TRUE;
 3474         }
 3476         if (done != MSGLOOP_IN_PROG && !response)
 3477                 /* Clear the outgoing message buffer */
ahc->msgout_len = 0;
 3480         return (done);
 3481 }
 3483 /*
 3484  * Process a message reject message.
 3485  */
 3486 static int
ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
 3488 {
 3489         /*
 3490          * What we care about here is if we had an
 3491          * outstanding SDTR or WDTR message for this
 3492          * target.  If we did, this is a signal that
 3493          * the target is refusing negotiation.
 3494          */
 3495         struct scb *scb;
 3496         struct ahc_initiator_tinfo *tinfo;
 3497         struct ahc_tmode_tstate *tstate;
u_int scb_index;
u_int last_msg;
 3500         int   response = 0;
scb_index = ahc_inb(ahc, SCB_TAG);
scb = ahc_lookup_scb(ahc, scb_index);
tinfo = ahc_fetch_transinfo(ahc, devinfo->channel,
devinfo->our_scsiid,
devinfo->target, &tstate);
 3507         /* Might be necessary */
last_msg = ahc_inb(ahc, LAST_MSG);
 3510         if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
 3511                 /*
 3512                  * Target does not support the PPR message.
 3513                  * Attempt to negotiate SPI-2 style.
 3514                  */
 3515                 if (bootverbose) {
printf("(%s:%c:%d:%d): PPR Rejected. "
 3517                                "Trying WDTR/SDTR\n",
ahc_name(ahc), devinfo->channel,
devinfo->target, devinfo->lun);
 3520                 }
tinfo->goal.ppr_options = 0;
tinfo->curr.transport_version = 2;
tinfo->goal.transport_version = 2;
ahc->msgout_index = 0;
ahc->msgout_len = 0;
ahc_build_transfer_msg(ahc, devinfo);
ahc->msgout_index = 0;
response = 1;
 3529         } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
 3531                 /* note 8bit xfers */
printf("(%s:%c:%d:%d): refuses WIDE negotiation.  Using "
 3533                        "8bit transfers\n", ahc_name(ahc),
devinfo->channel, devinfo->target, devinfo->lun);
ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
 3537                               /*paused*/TRUE);
 3538                 /*
 3539                  * No need to clear the sync rate.  If the target
 3540                  * did not accept the command, our syncrate is
 3541                  * unaffected.  If the target started the negotiation,
 3542                  * but rejected our response, we already cleared the
 3543                  * sync rate before sending our WDTR.
 3544                  */
 3545                 if (tinfo->goal.offset != tinfo->curr.offset) {
 3547                         /* Start the sync negotiation */
ahc->msgout_index = 0;
ahc->msgout_len = 0;
ahc_build_transfer_msg(ahc, devinfo);
ahc->msgout_index = 0;
response = 1;
 3553                 }
 3554         } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) {
 3555                 /* note asynch xfers and clear flag */
ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0,
 3557                                  /*offset*/0, /*ppr_options*/0,
AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
 3559                                  /*paused*/TRUE);
printf("(%s:%c:%d:%d): refuses synchronous negotiation. "
 3561                        "Using asynchronous transfers\n",
ahc_name(ahc), devinfo->channel,
devinfo->target, devinfo->lun);
 3564         } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) {
 3565                 int tag_type;
 3566                 int mask;
tag_type = (scb->hscb->control & MSG_SIMPLE_TASK);
 3570                 if (tag_type == MSG_SIMPLE_TASK) {
printf("(%s:%c:%d:%d): refuses tagged commands.  "
 3572                                "Performing non-tagged I/O\n", ahc_name(ahc),
devinfo->channel, devinfo->target, devinfo->lun);
ahc_set_tags(ahc, devinfo, AHC_QUEUE_NONE);
mask = ~0x23;
 3576                 } else {
printf("(%s:%c:%d:%d): refuses %s tagged commands.  "
 3578                                "Performing simple queue tagged I/O only\n",
ahc_name(ahc), devinfo->channel, devinfo->target,
devinfo->lun, tag_type == MSG_ORDERED_TASK
 3581                                ? "ordered" : "head of queue");
ahc_set_tags(ahc, devinfo, AHC_QUEUE_BASIC);
mask = ~0x03;
 3584                 }
 3586                 /*
 3587                  * Resend the identify for this CCB as the target
 3588                  * may believe that the selection is invalid otherwise.
 3589                  */
ahc_outb(ahc, SCB_CONTROL,
ahc_inb(ahc, SCB_CONTROL) & mask);
scb->hscb->control &= mask;
ahc_set_transaction_tag(scb, /*enabled*/FALSE,
 3594                                         /*type*/MSG_SIMPLE_TASK);
ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG);
ahc_assert_atn(ahc);
 3598                 /*
 3599                  * This transaction is now at the head of
 3600                  * the untagged queue for this target.
 3601                  */
 3602                 if ((ahc->flags & AHC_SCB_BTT) == 0) {
 3603                         struct scb_tailq *untagged_q;
untagged_q =
 3606                             &(ahc->untagged_queues[devinfo->target_offset]);
TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe);
scb->flags |= SCB_UNTAGGEDQ;
 3609                 }
ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
scb->hscb->tag);
 3613                 /*
 3614                  * Requeue all tagged commands for this target
 3615                  * currently in our possession so they can be
 3616                  * converted to untagged commands.
 3617                  */
ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
SCB_GET_CHANNEL(ahc, scb),
SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
ROLE_INITIATOR, CAM_REQUEUE_REQ,
SEARCH_COMPLETE);
 3623         } else {
 3624                 /*
 3625                  * Otherwise, we ignore it.
 3626                  */
printf("%s:%c:%d: Message reject for %x -- ignored\n",
ahc_name(ahc), devinfo->channel, devinfo->target,
last_msg);
 3630         }
 3631         return (response);
 3632 }
 3634 /*
 3635  * Process an ingnore wide residue message.
 3636  */
 3637 static void
ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
 3639 {
u_int scb_index;
 3641         struct scb *scb;
scb_index = ahc_inb(ahc, SCB_TAG);
scb = ahc_lookup_scb(ahc, scb_index);
 3645         /*
 3646          * XXX Actually check data direction in the sequencer?
 3647          * Perhaps add datadir to some spare bits in the hscb?
 3648          */
 3649         if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0
 3650          || ahc_get_transfer_dir(scb) != CAM_DIR_IN) {
 3651                 /*
 3652                  * Ignore the message if we haven't
 3653                  * seen an appropriate data phase yet.
 3654                  */
 3655         } else {
 3656                 /*
 3657                  * If the residual occurred on the last
 3658                  * transfer and the transfer request was
 3659                  * expected to end on an odd count, do
 3660                  * nothing.  Otherwise, subtract a byte
 3661                  * and update the residual count accordingly.
 3662                  */
uint32_t sgptr;
sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
 3666                 if ((sgptr & SG_LIST_NULL) != 0
 3667                  && (ahc_inb(ahc, SCB_LUN) & SCB_XFERLEN_ODD) != 0) {
 3668                         /*
 3669                          * If the residual occurred on the last
 3670                          * transfer and the transfer request was
 3671                          * expected to end on an odd count, do
 3672                          * nothing.
 3673                          */
 3674                 } else {
 3675                         struct ahc_dma_seg *sg;
uint32_t data_cnt;
uint32_t data_addr;
uint32_t sglen;
 3680                         /* Pull in all of the sgptr */
sgptr = ahc_inl(ahc, SCB_RESIDUAL_SGPTR);
data_cnt = ahc_inl(ahc, SCB_RESIDUAL_DATACNT);
 3684                         if ((sgptr & SG_LIST_NULL) != 0) {
 3685                                 /*
 3686                                  * The residual data count is not updated
 3687                                  * for the command run to completion case.
 3688                                  * Explicitly zero the count.
 3689                                  */
data_cnt &= ~AHC_SG_LEN_MASK;
 3691                         }
data_addr = ahc_inl(ahc, SHADDR);
data_cnt += 1;
data_addr -= 1;
sgptr &= SG_PTR_MASK;
sg = ahc_sg_bus_to_virt(scb, sgptr);
 3701                         /*
 3702                          * The residual sg ptr points to the next S/G
 3703                          * to load so we must go back one.
 3704                          */
sg--;
sglen = aic_le32toh(sg->len) & AHC_SG_LEN_MASK;
 3707                         if (sg != scb->sg_list
 3708                          && sglen < (data_cnt & AHC_SG_LEN_MASK)) {
sg--;
sglen = aic_le32toh(sg->len);
 3712                                 /*
 3713                                  * Preserve High Address and SG_LIST bits
 3714                                  * while setting the count to 1.
 3715                                  */
data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK));
data_addr = aic_le32toh(sg->addr)
 3718                                           + (sglen & AHC_SG_LEN_MASK) - 1;
 3720                                 /*
 3721                                  * Increment sg so it points to the
 3722                                  * "next" sg.
 3723                                  */
sg++;
sgptr = ahc_sg_virt_to_bus(scb, sg);
 3726                         }
ahc_outl(ahc, SCB_RESIDUAL_SGPTR, sgptr);
ahc_outl(ahc, SCB_RESIDUAL_DATACNT, data_cnt);
 3729                         /*
 3730                          * Toggle the "oddness" of the transfer length
 3731                          * to handle this mid-transfer ignore wide
 3732                          * residue.  This ensures that the oddness is
 3733                          * correct for subsequent data transfers.
 3734                          */
ahc_outb(ahc, SCB_LUN,
ahc_inb(ahc, SCB_LUN) ^ SCB_XFERLEN_ODD);
 3737                 }
 3738         }
 3739 }
 3742 /*
 3743  * Reinitialize the data pointers for the active transfer
 3744  * based on its current residual.
 3745  */
 3746 static void
ahc_reinitialize_dataptrs(struct ahc_softc *ahc)
 3748 {
 3749         struct   scb *scb;
 3750         struct   ahc_dma_seg *sg;
u_int    scb_index;
uint32_t sgptr;
uint32_t resid;
uint32_t dataptr;
scb_index = ahc_inb(ahc, SCB_TAG);
scb = ahc_lookup_scb(ahc, scb_index);
sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24)
 3759               | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16)
 3760               | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8)
 3761               | ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
sgptr &= SG_PTR_MASK;
sg = ahc_sg_bus_to_virt(scb, sgptr);
 3766         /* The residual sg_ptr always points to the next sg */
sg--;
resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16)
 3770               | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8)
 3771               | ahc_inb(ahc, SCB_RESIDUAL_DATACNT);
dataptr = aic_le32toh(sg->addr)
 3774                 + (aic_le32toh(sg->len) & AHC_SG_LEN_MASK)
 3775                 - resid;
 3776         if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
u_int dscommand1;
dscommand1 = ahc_inb(ahc, DSCOMMAND1);
ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
ahc_outb(ahc, HADDR,
 3782                          (aic_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS);
ahc_outb(ahc, DSCOMMAND1, dscommand1);
 3784         }
ahc_outb(ahc, HADDR + 3, dataptr >> 24);
ahc_outb(ahc, HADDR + 2, dataptr >> 16);
ahc_outb(ahc, HADDR + 1, dataptr >> 8);
ahc_outb(ahc, HADDR, dataptr);
ahc_outb(ahc, HCNT + 2, resid >> 16);
ahc_outb(ahc, HCNT + 1, resid >> 8);
ahc_outb(ahc, HCNT, resid);
 3792         if ((ahc->features & AHC_ULTRA2) == 0) {
ahc_outb(ahc, STCNT + 2, resid >> 16);
ahc_outb(ahc, STCNT + 1, resid >> 8);
ahc_outb(ahc, STCNT, resid);
 3796         }
 3797 }
 3799 /*
 3800  * Handle the effects of issuing a bus device reset message.
 3801  */
 3802 static void
ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
cam_status status, char *message, int verbose_level)
 3805 {
 3806 #ifdef AHC_TARGET_MODE
 3807         struct ahc_tmode_tstate* tstate;
u_int lun;
 3809 #endif
 3810         int found;
found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role,
status);
 3816 #ifdef AHC_TARGET_MODE
 3817         /*
 3818          * Send an immediate notify ccb to all target mord peripheral
 3819          * drivers affected by this action.
 3820          */
tstate = ahc->enabled_targets[devinfo->our_scsiid];
 3822         if (tstate != NULL) {
 3823                 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
 3824                         struct ahc_tmode_lstate* lstate;
lstate = tstate->enabled_luns[lun];
 3827                         if (lstate == NULL)
 3828                                 continue;
ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid,
MSG_BUS_DEV_RESET, /*arg*/0);
ahc_send_lstate_events(ahc, lstate);
 3833                 }
 3834         }
 3835 #endif
 3837         /*
 3838          * Go back to async/narrow transfers and renegotiate.
 3839          */
ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
AHC_TRANS_CUR, /*paused*/TRUE);
ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL,
 3843                          /*period*/0, /*offset*/0, /*ppr_options*/0,
AHC_TRANS_CUR, /*paused*/TRUE);
 3846         if (status != CAM_SEL_TIMEOUT)
ahc_send_async(ahc, devinfo->channel, devinfo->target,
CAM_LUN_WILDCARD, AC_SENT_BDR, NULL);
 3850         if (message != NULL
 3851          && (verbose_level <= bootverbose))
printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc),
message, devinfo->channel, devinfo->target, found);
 3854 }
 3856 #ifdef AHC_TARGET_MODE
 3857 static void
ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
 3859                        struct scb *scb)
 3860 {
 3862         /*              
 3863          * To facilitate adding multiple messages together,
 3864          * each routine should increment the index and len
 3865          * variables instead of setting them explicitly.
 3866          */             
ahc->msgout_index = 0;
ahc->msgout_len = 0;
 3870         if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0)
ahc_build_transfer_msg(ahc, devinfo);
 3872         else
panic("ahc_intr: AWAITING target message with no message");
ahc->msgout_index = 0;
ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
 3877 }
 3878 #endif
 3880 int
ahc_softc_init(struct ahc_softc *ahc)
 3882 {
 3884         /* The IRQMS bit is only valid on VL and EISA chips */
 3885         if ((ahc->chip & AHC_PCI) == 0)
ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS;
 3887         else
ahc->unpause = 0;
ahc->pause = ahc->unpause | PAUSE; 
 3890         /* XXX The shared scb data stuff should be deprecated */
 3891         if (ahc->scb_data == NULL) {
ahc->scb_data = malloc(sizeof(*ahc->scb_data),
M_DEVBUF, M_NOWAIT);
 3894                 if (ahc->scb_data == NULL)
 3895                         return (ENOMEM);
memset(ahc->scb_data, 0, sizeof(*ahc->scb_data));
 3897         }
 3899         return (0);
 3900 }
 3902 void
ahc_softc_insert(struct ahc_softc *ahc)
 3904 {
 3905         struct ahc_softc *list_ahc;
 3907 #if AHC_PCI_CONFIG > 0
 3908         /*
 3909          * Second Function PCI devices need to inherit some
 3910          * settings from function 0.
 3911          */
 3912         if ((ahc->chip & AHC_BUS_MASK) == AHC_PCI
 3913          && (ahc->features & AHC_MULTI_FUNC) != 0) {
TAILQ_FOREACH(list_ahc, &ahc_tailq, links) {
ahc_dev_softc_t list_pci;
ahc_dev_softc_t pci;
list_pci = list_ahc->dev_softc;
pci = ahc->dev_softc;
 3920                         if (ahc_get_pci_slot(list_pci) == ahc_get_pci_slot(pci)
 3921                          && ahc_get_pci_bus(list_pci) == ahc_get_pci_bus(pci)) {
 3922                                 struct ahc_softc *master;
 3923                                 struct ahc_softc *slave;
 3925                                 if (ahc_get_pci_function(list_pci) == 0) {
master = list_ahc;
slave = ahc;
 3928                                 } else {
master = ahc;
slave = list_ahc;
 3931                                 }
slave->flags &= ~AHC_BIOS_ENABLED; 
slave->flags |=
master->flags & AHC_BIOS_ENABLED;
slave->flags &= ~AHC_PRIMARY_CHANNEL; 
slave->flags |=
master->flags & AHC_PRIMARY_CHANNEL;
 3938                                 break;
 3939                         }
 3940                 }
 3941         }
 3942 #endif
 3944         /*
 3945          * Insertion sort into our list of softcs.
 3946          */
list_ahc = TAILQ_FIRST(&ahc_tailq);
 3948         while (list_ahc != NULL
 3949             && ahc_softc_comp(ahc, list_ahc) <= 0)
list_ahc = TAILQ_NEXT(list_ahc, links);
 3951         if (list_ahc != NULL)
TAILQ_INSERT_BEFORE(list_ahc, ahc, links);
 3953         else
TAILQ_INSERT_TAIL(&ahc_tailq, ahc, links);
ahc->init_level++;
 3956 }
 3958 void
ahc_set_unit(struct ahc_softc *ahc, int unit)
 3960 {
ahc->unit = unit;
 3962 }
 3964 void
ahc_set_name(struct ahc_softc *ahc, char *name)
 3966 {
 3967         if (ahc->name != NULL)
free(ahc->name, M_DEVBUF);
ahc->name = name;
 3970 }
 3972 void
ahc_free(struct ahc_softc *ahc)
 3974 {
 3975         int i;
 3977         switch (ahc->init_level) {
 3978         default:
 3979         case 2:
ahc_shutdown(ahc);
 3981                 /* FALLTHROUGH */
 3982         case 1:
bus_dmamap_unload(ahc->parent_dmat, ahc->shared_data_dmamap);
bus_dmamap_destroy(ahc->parent_dmat, ahc->shared_data_dmamap);
bus_dmamem_unmap(ahc->parent_dmat, (caddr_t)ahc->qoutfifo, ahc->shared_data_size);
bus_dmamem_free(ahc->parent_dmat, &ahc->shared_data_seg, ahc->shared_data_nseg);
 3987                 break;
 3988         case 0:
 3989                 break;
 3990         }
ahc_platform_free(ahc);
ahc_fini_scbdata(ahc);
 3994         for (i = 0; i < AHC_NUM_TARGETS; i++) {
 3995                 struct ahc_tmode_tstate *tstate;
tstate = ahc->enabled_targets[i];
 3998                 if (tstate != NULL) {
 3999 #ifdef AHC_TARGET_MODE
 4000                         int j;
 4002                         for (j = 0; j < AHC_NUM_LUNS; j++) {
 4003                                 struct ahc_tmode_lstate *lstate;
lstate = tstate->enabled_luns[j];
 4006                                 if (lstate != NULL) {
 4007                                           /*xpt_free_path(lstate->path);*/
free(lstate, M_DEVBUF);
 4009                                 }
 4010                         }
 4011 #endif
free(tstate, M_DEVBUF);
 4013                 }
 4014         }
 4015 #ifdef AHC_TARGET_MODE
 4016         if (ahc->black_hole != NULL) {
 4017           /*xpt_free_path(ahc->black_hole->path);*/
free(ahc->black_hole, M_DEVBUF);
 4019         }
 4020 #endif
 4021 #ifndef __NetBSD__
 4022         if (ahc->name != NULL)
free(ahc->name, M_DEVBUF);
 4024 #endif
 4025         if (ahc->seep_config != NULL)
free(ahc->seep_config, M_DEVBUF);
 4027 #ifndef __FreeBSD__
free(ahc, M_DEVBUF);
 4029 #endif
 4030         return;
 4031 }
 4033 void
ahc_shutdown(void *arg)
 4035 {
 4036         struct  ahc_softc *ahc;
 4037         int     i;
ahc = (struct ahc_softc *)arg;
 4041         /* This will reset most registers to 0, but not all */
ahc_reset(ahc, /*reinit*/FALSE);
ahc_outb(ahc, SCSISEQ, 0);
ahc_outb(ahc, SXFRCTL0, 0);
ahc_outb(ahc, DSPCISTATUS, 0);
 4047         for (i = TARG_SCSIRATE; i < SCSICONF; i++)
ahc_outb(ahc, i, 0);
 4049 }
 4051 /*
 4052  * Reset the controller and record some information about it
 4053  * that is only available just after a reset.  If "reinit" is
 4054  * non-zero, this reset occured after initial configuration
 4055  * and the caller requests that the chip be fully reinitialized
 4056  * to a runable state.  Chip interrupts are *not* enabled after
 4057  * a reinitialization.  The caller must enable interrupts via
 4058  * ahc_intr_enable().
 4059  */
 4060 int
ahc_reset(struct ahc_softc *ahc, int reinit)
 4062 {
u_int   sblkctl;
u_int   sxfrctl1_a, sxfrctl1_b;
 4065         int     error;
 4066         int     wait;
 4068         /*
 4069          * Preserve the value of the SXFRCTL1 register for all channels.
 4070          * It contains settings that affect termination and we don't want
 4071          * to disturb the integrity of the bus.
 4072          */
ahc_pause(ahc);
sxfrctl1_b = 0;
 4075         if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) {
u_int sblkctl;
 4078                 /*
 4079                  * Save channel B's settings in case this chip
 4080                  * is setup for TWIN channel operation.
 4081                  */
sblkctl = ahc_inb(ahc, SBLKCTL);
ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
sxfrctl1_b = ahc_inb(ahc, SXFRCTL1);
ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
 4086         }
sxfrctl1_a = ahc_inb(ahc, SXFRCTL1);
ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause);
 4091         /*
 4092          * Ensure that the reset has finished.  We delay 1000us
 4093          * prior to reading the register to make sure the chip
 4094          * has sufficiently completed its reset to handle register
 4095          * accesses.
 4096          */
wait = 1000;
 4098         do {
aic_delay(1000);
 4100         } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK));
 4102         if (wait == 0) {
printf("%s: WARNING - Failed chip reset!  "
 4104                        "Trying to initialize anyway.\n", ahc_name(ahc));
 4105         }
ahc_outb(ahc, HCNTRL, ahc->pause);
 4108         /* Determine channel configuration */
sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE);
 4110         /* No Twin Channel PCI cards */
 4111         if ((ahc->chip & AHC_PCI) != 0)
sblkctl &= ~SELBUSB;
 4113         switch (sblkctl) {
 4114         case 0:
 4115                 /* Single Narrow Channel */
 4116                 break;
 4117         case 2:
 4118                 /* Wide Channel */
ahc->features |= AHC_WIDE;
 4120                 break;
 4121         case 8:
 4122                 /* Twin Channel */
ahc->features |= AHC_TWIN;
 4124                 break;
 4125         default:
printf(" Unsupported adapter type (0x%x).  Ignoring\n", sblkctl);
 4127                 return(-1);
 4128         }
 4130         /*
 4131          * Reload sxfrctl1.
 4132          *
 4133          * We must always initialize STPWEN to 1 before we
 4134          * restore the saved values.  STPWEN is initialized
 4135          * to a tri-state condition which can only be cleared
 4136          * by turning it on.
 4137          */
 4138         if ((ahc->features & AHC_TWIN) != 0) {
u_int sblkctl;
sblkctl = ahc_inb(ahc, SBLKCTL);
ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
ahc_outb(ahc, SXFRCTL1, sxfrctl1_b);
ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
 4145         }
ahc_outb(ahc, SXFRCTL1, sxfrctl1_a);
error = 0;
 4149         if (reinit != 0)
 4150                 /*
 4151                  * If a recovery action has forced a chip reset,
 4152                  * re-initialize the chip to our liking.
 4153                  */
error = ahc->bus_chip_init(ahc);
 4155 #ifdef AHC_DUMP_SEQ
 4156         else 
ahc_dumpseq(ahc);
 4158 #endif
 4160         return (error);
 4161 }
 4163 /*
 4164  * Determine the number of SCBs available on the controller
 4165  */
 4166 int
ahc_probe_scbs(struct ahc_softc *ahc) {
 4168         int i;
 4170         for (i = 0; i < AHC_SCB_MAX; i++) {
ahc_outb(ahc, SCBPTR, i);
ahc_outb(ahc, SCB_BASE, i);
 4174                 if (ahc_inb(ahc, SCB_BASE) != i)
 4175                         break;
ahc_outb(ahc, SCBPTR, 0);
 4177                 if (ahc_inb(ahc, SCB_BASE) != 0)
 4178                         break;
 4179         }
 4180         return (i);
 4181 }
 4183 #if 0
 4184 static void
 4185 ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 
 4186 {
bus_addr_t *baddr;
baddr = (bus_addr_t *)arg;
 4190         *baddr = segs->ds_addr;
 4191 }
 4192 #endif
 4194 static void
ahc_build_free_scb_list(struct ahc_softc *ahc)
 4196 {
 4197         int scbsize;
 4198         int i;
scbsize = 32;
 4201         if ((ahc->flags & AHC_LSCBS_ENABLED) != 0)
scbsize = 64;
 4204         for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
 4205                 int j;
ahc_outb(ahc, SCBPTR, i);
 4209                 /*
 4210                  * Touch all SCB bytes to avoid parity errors
 4211                  * should one of our debugging routines read
 4212                  * an otherwise uninitiatlized byte.
 4213                  */
 4214                 for (j = 0; j < scbsize; j++)
ahc_outb(ahc, SCB_BASE+j, 0xFF);
 4217                 /* Clear the control byte. */
ahc_outb(ahc, SCB_CONTROL, 0);
 4220                 /* Set the next pointer */
 4221                 if ((ahc->flags & AHC_PAGESCBS) != 0)
ahc_outb(ahc, SCB_NEXT, i+1);
 4223                 else 
ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
 4226                 /* Make the tag number, SCSIID, and lun invalid */
ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
ahc_outb(ahc, SCB_SCSIID, 0xFF);
ahc_outb(ahc, SCB_LUN, 0xFF);
 4230         }
 4232         if ((ahc->flags & AHC_PAGESCBS) != 0) {
 4233                 /* SCB 0 heads the free list. */
ahc_outb(ahc, FREE_SCBH, 0);
 4235         } else {
 4236                 /* No free list. */
ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL);
 4238         }
 4240         /* Make sure that the last SCB terminates the free list */
ahc_outb(ahc, SCBPTR, i-1);
ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
 4243 }
 4245 static int
ahc_init_scbdata(struct ahc_softc *ahc)
 4247 {
 4248         struct scb_data *scb_data;
 4249         int i;
scb_data = ahc->scb_data;
SLIST_INIT(&scb_data->free_scbs);
SLIST_INIT(&scb_data->sg_maps);
 4255         /* Allocate SCB resources */
scb_data->scbarray =
 4257             (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX_ALLOC,
M_DEVBUF, M_NOWAIT);
 4259         if (scb_data->scbarray == NULL)
 4260                 return (ENOMEM);
memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX_ALLOC);
 4263         /* Determine the number of hardware SCBs and initialize them */
scb_data->maxhscbs = ahc_probe_scbs(ahc);
 4266         if (ahc->scb_data->maxhscbs == 0) {
printf("%s: No SCB space found\n", ahc_name(ahc));
 4268                 return (ENXIO);
 4269         }
 4271         /*
 4272          * Create our DMA tags.  These tags define the kinds of device
 4273          * accessible memory allocations and memory mappings we will
 4274          * need to perform during normal operation.
 4275          *
 4276          * Unless we need to further restrict the allocation, we rely
 4277          * on the restrictions of the parent dmat, hence the common
 4278          * use of MAXADDR and MAXSIZE.
 4279          */
 4281         if (ahc_createdmamem(ahc->parent_dmat,
AHC_SCB_MAX * sizeof(struct hardware_scb), ahc->sc_dmaflags,
 4283              &scb_data->hscb_dmamap,
 4284              (caddr_t *)&scb_data->hscbs, &scb_data->hscb_busaddr,
 4285              &scb_data->hscb_seg, &scb_data->hscb_nseg, ahc_name(ahc),
 4286              "hardware SCB structures") < 0)
 4287                 goto error_exit;
scb_data->init_level++;
 4291         if (ahc_createdmamem(ahc->parent_dmat,
AHC_SCB_MAX * sizeof(struct scsi_sense_data), ahc->sc_dmaflags,
 4293              &scb_data->sense_dmamap, (caddr_t *)&scb_data->sense,
 4294              &scb_data->sense_busaddr, &scb_data->sense_seg,
 4295              &scb_data->sense_nseg, ahc_name(ahc), "sense buffers") < 0)
 4296                 goto error_exit;
scb_data->init_level++;
 4300         /* Perform initial CCB allocation */
memset(scb_data->hscbs, 0,
AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb));
 4303         do {
i = scb_data->numscbs;
ahc_alloc_scbs(ahc);
 4306         } while ((i != scb_data->numscbs) && 
 4307             (scb_data->numscbs < AHC_SCB_MAX_ALLOC));
 4309         if (scb_data->numscbs != AHC_SCB_MAX_ALLOC) {
printf("%s: ahc_init_scbdata - "
 4311                        "Unable to allocate initial scbs\n",
ahc_name(ahc));
 4313                 goto error_exit;
 4314         }
 4316         /*
 4317          * Reserve the next queued SCB.
 4318          */
ahc->next_queued_scb = ahc_get_scb(ahc);
 4321         /*
 4322          * Note that we were successfull
 4323          */
 4324         return (0); 
error_exit:
 4328         return (ENOMEM);
 4329 }
 4331 static void
ahc_fini_scbdata(struct ahc_softc *ahc)
 4333 {
 4334         struct scb_data *scb_data;
scb_data = ahc->scb_data;
 4337         if (scb_data == NULL)
 4338                 return;
 4340         switch (scb_data->init_level) {
 4341         default:
 4342         case 5:
 4343         {
 4344                 struct sg_map_node *sg_map;
 4346                 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) {
SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
ahc_freedmamem(ahc->parent_dmat, PAGE_SIZE,
sg_map->sg_dmamap, (caddr_t)sg_map->sg_vaddr,
 4350                             &sg_map->sg_dmasegs, sg_map->sg_nseg);
free(sg_map, M_DEVBUF);
 4352                 }
 4353         }
 4354         /*FALLTHROUGH*/
 4355         case 4:
ahc_freedmamem(ahc->parent_dmat,
AHC_SCB_MAX * sizeof(struct scsipi_sense_data),
scb_data->sense_dmamap, (caddr_t)scb_data->sense,
 4359                     &scb_data->sense_seg, scb_data->sense_nseg);
 4360         /*FALLTHROUGH*/
 4361         case 3:
ahc_freedmamem(ahc->parent_dmat,
AHC_SCB_MAX * sizeof(struct hardware_scb),
scb_data->hscb_dmamap, (caddr_t)scb_data->hscbs,
 4365                     &scb_data->hscb_seg, scb_data->hscb_nseg);
 4366         /*FALLTHROUGH*/
 4367         case 2:
 4368         case 1:
 4369         case 0:
 4370                 break;
 4371         }
 4372         if (scb_data->scbarray != NULL)
free(scb_data->scbarray, M_DEVBUF);
 4374 }
 4376 void
ahc_alloc_scbs(struct ahc_softc *ahc)
 4378 {
 4379         struct scb_data *scb_data;
 4380         struct scb *next_scb;
 4381         struct sg_map_node *sg_map;
bus_addr_t physaddr;
 4383         struct ahc_dma_seg *segs;
 4384         int newcount;
 4385         int i;
scb_data = ahc->scb_data;
 4388         if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC)
 4389                 /* Can't allocate any more */
 4390                 return;
next_scb = &scb_data->scbarray[scb_data->numscbs];
sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT);
 4396         if (sg_map == NULL)
 4397                 return;
 4399         /* Allocate S/G space for the next batch of SCBS */
 4400         if (ahc_createdmamem(ahc->parent_dmat, PAGE_SIZE, ahc->sc_dmaflags,
 4401                              &sg_map->sg_dmamap,
 4402                              (caddr_t *)&sg_map->sg_vaddr, &sg_map->sg_physaddr,
 4403                              &sg_map->sg_dmasegs, &sg_map->sg_nseg, ahc_name(ahc),
 4404                              "SG space") < 0) {
free(sg_map, M_DEVBUF);
 4406                 return;
 4407         }
SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
segs = sg_map->sg_vaddr;
physaddr = sg_map->sg_physaddr;
newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg)));
newcount = MIN(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs));
 4416         for (i = 0; i < newcount; i++) {
 4417                 struct scb_platform_data *pdata = NULL;
 4418                 int error;
 4420                 if (sizeof(*pdata) > 0) { 
pdata = (struct scb_platform_data *)
malloc(sizeof(*pdata), M_DEVBUF, M_NOWAIT);
 4423                         if (pdata == NULL)
 4424                                 break;
bzero(pdata, sizeof(*pdata));
 4426                 }
next_scb->platform_data = pdata;
next_scb->sg_map = sg_map;
next_scb->sg_list = segs;
 4431                 /*
 4432                  * The sequencer always starts with the second entry.
 4433                  * The first entry is embedded in the scb.
 4434                  */
next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg);
next_scb->ahc_softc = ahc;
next_scb->flags = SCB_FLAG_NONE;
error = bus_dmamap_create(ahc->parent_dmat, 
AHC_MAXTRANSFER_SIZE, AHC_NSEG, MAXPHYS, 0,
BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW|ahc->sc_dmaflags,
 4442                           &next_scb->dmamap);
 4443                 if (error != 0)
 4444                         break;
next_scb->hscb = &scb_data->hscbs[scb_data->numscbs];
next_scb->hscb->tag = ahc->scb_data->numscbs;
SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs,
next_scb, links.sle);
segs += AHC_NSEG;
physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg));
next_scb++;
ahc->scb_data->numscbs++;
 4454         }
 4455 }
 4457 #ifndef DEBUG
 4458 void
ahc_controller_info(struct ahc_softc *ahc, char *buf, size_t buf_len)
 4460 {
 4461         int len = 0;
snprintf(buf + len, buf_len - len, "%s: ",
ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]);
len = strlen(buf);
 4466         if ((ahc->features & AHC_TWIN) != 0)
snprintf(buf + len, buf_len - len,
 4468                          "Twin Channel, A SCSI Id=%d, B SCSI Id=%d, "
 4469                          "primary %c, ", ahc->our_id, ahc->our_id_b,
 4470                          (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A');
 4471         else {
 4472                 const char *speed;
 4473                 const char *type;
speed = "";
 4476                 if ((ahc->features & AHC_ULTRA) != 0) {
speed = "Ultra ";
 4478                 } else if ((ahc->features & AHC_DT) != 0) {
speed = "Ultra160 ";
 4480                 } else if ((ahc->features & AHC_ULTRA2) != 0) {
speed = "Ultra2 ";
 4482                 }
 4483                 if ((ahc->features & AHC_WIDE) != 0) {
type = "Wide";
 4485                 } else {
type = "Single";
 4487                 }
snprintf(buf + len, buf_len - len,
 4489                          "%s%s Channel %c, SCSI Id=%d, ",
speed, type, ahc->channel, ahc->our_id);
 4491         }
len = strlen(buf);
 4494         if ((ahc->flags & AHC_PAGESCBS) != 0)
snprintf(buf + len, buf_len - len, "%d/%d SCBs",
ahc->scb_data->maxhscbs, AHC_MAX_QUEUE);
 4497         else
snprintf(buf + len, buf_len - len, "%d SCBs",
ahc->scb_data->maxhscbs);
 4500 }
 4501 #endif /* !DEBUG */
 4503 int
ahc_chip_init(struct ahc_softc *ahc)
 4505 {
 4506         int      term;
 4507         int      error;
u_int    i;
u_int    scsi_conf;
u_int    scsiseq_template;
uint32_t physaddr;
ahc_outb(ahc, SEQ_FLAGS, 0);
ahc_outb(ahc, SEQ_FLAGS2, 0);
 4516         /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/
 4517         if (ahc->features & AHC_TWIN) {
 4519                 /*
 4520                  * Setup Channel B first.
 4521                  */
ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB);
term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0;
ahc_outb(ahc, SCSIID, ahc->our_id_b);
scsi_conf = ahc_inb(ahc, SCSICONF + 1);
ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
 4527                                         |term|ahc->seltime_b|ENSTIMER|ACTNEGEN);
 4528                 if ((ahc->features & AHC_ULTRA2) != 0)
ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
 4533                 /* Select Channel A */
ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB);
 4535         }
term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0;
 4537         if ((ahc->features & AHC_ULTRA2) != 0)
ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id);
 4539         else
ahc_outb(ahc, SCSIID, ahc->our_id);
scsi_conf = ahc_inb(ahc, SCSICONF);
ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
 4543                                 |term|ahc->seltime
 4544                                 |ENSTIMER|ACTNEGEN);
 4545         if ((ahc->features & AHC_ULTRA2) != 0)
ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
 4550         /* There are no untagged SCBs active yet. */
 4551         for (i = 0; i < 16; i++) {
ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0));
 4553                 if ((ahc->flags & AHC_SCB_BTT) != 0) {
 4554                         int lun;
 4556                         /*
 4557                          * The SCB based BTT allows an entry per
 4558                          * target and lun pair.
 4559                          */
 4560                         for (lun = 1; lun < AHC_NUM_LUNS; lun++)
ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun));
 4562                 }
 4563         }
 4565         /* All of our queues are empty */
 4566         for (i = 0; i < 256; i++)
ahc->qoutfifo[i] = SCB_LIST_NULL;
 4568 #ifdef __sgi__
ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
 4570 #else
ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD);
 4572 #endif
 4573         for (i = 0; i < 256; i++)
ahc->qinfifo[i] = SCB_LIST_NULL;
 4576         if ((ahc->features & AHC_MULTI_TID) != 0) {
ahc_outb(ahc, TARGID, 0);
ahc_outb(ahc, TARGID + 1, 0);
 4579         }
 4581         /*
 4582          * Tell the sequencer where it can find our arrays in memory.
 4583          */
physaddr = ahc->scb_data->hscb_busaddr;
ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF);
ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF);
ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF);
ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF);
physaddr = ahc->shared_data_busaddr;
ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF);
ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF);
ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF);
ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF);
 4596         /*
 4597          * Initialize the group code to command length table.
 4598          * This overrides the values in TARG_SCSIRATE, so only
 4599          * setup the table after we have processed that information.
 4600          */
ahc_outb(ahc, CMDSIZE_TABLE, 5);
ahc_outb(ahc, CMDSIZE_TABLE + 1, 9);
ahc_outb(ahc, CMDSIZE_TABLE + 2, 9);
ahc_outb(ahc, CMDSIZE_TABLE + 3, 0);
ahc_outb(ahc, CMDSIZE_TABLE + 4, 15);
ahc_outb(ahc, CMDSIZE_TABLE + 5, 11);
ahc_outb(ahc, CMDSIZE_TABLE + 6, 0);
ahc_outb(ahc, CMDSIZE_TABLE + 7, 0);
 4610         if ((ahc->features & AHC_HS_MAILBOX) != 0)
ahc_outb(ahc, HS_MAILBOX, 0);
 4613         /* Tell the sequencer of our initial queue positions */
 4614         if ((ahc->features & AHC_TARGETMODE) != 0) {
ahc->tqinfifonext = 1;
ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1);
ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
 4618         }
ahc->qinfifonext = 0;
ahc->qoutfifonext = 0;
 4621         if ((ahc->features & AHC_QUEUE_REGS) != 0) {
ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256);
ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
ahc_outb(ahc, SNSCB_QOFF, ahc->qinfifonext);
ahc_outb(ahc, SDSCB_QOFF, 0);
 4626         } else {
ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
ahc_outb(ahc, QINPOS, ahc->qinfifonext);
ahc_outb(ahc, QOUTPOS, ahc->qoutfifonext);
 4630         }
 4632         /* We don't have any waiting selections */
ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL);
 4635         /* Our disconnection list is empty too */
ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL);
 4638         /* Message out buffer starts empty */
ahc_outb(ahc, MSG_OUT, MSG_NOOP);
 4641         /*
 4642          * Setup the allowed SCSI Sequences based on operational mode.
 4643          * If we are a target, we'll enable select in operations once
 4644          * we've had a lun enabled.
 4645          */
scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP;
 4647         if ((ahc->flags & AHC_INITIATORROLE) != 0)
scsiseq_template |= ENRSELI;
ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template);
 4651         /* Initialize our list of free SCBs. */
ahc_build_free_scb_list(ahc);
 4654         /*
 4655          * Tell the sequencer which SCB will be the next one it receives.
 4656          */
ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
 4659         /*
 4660          * Load the Sequencer program and Enable the adapter
 4661          * in "fast" mode.
 4662          */
 4663         if (bootverbose)
printf("%s: Downloading Sequencer Program...",
ahc_name(ahc));
error = ahc_loadseq(ahc);
 4668         if (error != 0)
 4669                 return (error);
 4671         if ((ahc->features & AHC_ULTRA2) != 0) {
 4672                 int wait;
 4674                 /*
 4675                  * Wait for up to 500ms for our transceivers
 4676                  * to settle.  If the adapter does not have
 4677                  * a cable attached, the transceivers may
 4678                  * never settle, so don't complain if we
 4679                  * fail here.
 4680                  */
 4681                 for (wait = 5000;
 4682                      (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
wait--)
aic_delay(100);
 4685         }
ahc_restart(ahc);
 4687         return (0);
 4688 }
 4690 /*
 4691  * Start the board, ready for normal operation
 4692  */
 4693 int
ahc_init(struct ahc_softc *ahc)
 4695 {
 4696         int      max_targ;
u_int    i;
u_int    scsi_conf;
u_int    ultraenb;
u_int    discenable;
u_int    tagenable;
size_t   driver_data_size;
 4704 #ifdef AHC_DEBUG
 4705         if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0)
ahc->flags |= AHC_SEQUENCER_DEBUG;
 4707 #endif
 4709 #ifdef AHC_PRINT_SRAM
printf("Scratch Ram:");
 4711         for (i = 0x20; i < 0x5f; i++) {
 4712                 if (((i % 8) == 0) && (i != 0)) {
printf ("\n              ");
 4714                 }
printf (" 0x%x", ahc_inb(ahc, i));
 4716         }
 4717         if ((ahc->features & AHC_MORE_SRAM) != 0) {
 4718                 for (i = 0x70; i < 0x7f; i++) {
 4719                         if (((i % 8) == 0) && (i != 0)) {
printf ("\n              ");
 4721                         }
printf (" 0x%x", ahc_inb(ahc, i));
 4723                 }
 4724         }
printf ("\n");
 4726         /*
 4727          * Reading uninitialized scratch ram may
 4728          * generate parity errors.
 4729          */
ahc_outb(ahc, CLRINT, CLRPARERR);
ahc_outb(ahc, CLRINT, CLRBRKADRINT);
 4732 #endif
max_targ = 15;
 4735         /*
 4736          * Assume we have a board at this stage and it has been reset.
 4737          */
 4738         if ((ahc->flags & AHC_USEDEFAULTS) != 0)
ahc->our_id = ahc->our_id_b = 7;
 4741         /*
 4742          * Default to allowing initiator operations.
 4743          */
ahc->flags |= AHC_INITIATORROLE;
 4746         /*
 4747          * Only allow target mode features if this unit has them enabled.
 4748          */
 4749         //if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0)
ahc->features &= ~AHC_TARGETMODE;
 4752         /*
 4753          * DMA tag for our command fifos and other data in system memory
 4754          * the card's sequencer must be able to access.  For initiator
 4755          * roles, we need to allocate space for the qinfifo and qoutfifo.
 4756          * The qinfifo and qoutfifo are composed of 256 1 byte elements. 
 4757          * When providing for the target mode role, we must additionally
 4758          * provide space for the incoming target command fifo and an extra
 4759          * byte to deal with a DMA bug in some chip versions.
 4760          */
driver_data_size = 2 * 256 * sizeof(uint8_t);
 4762         if ((ahc->features & AHC_TARGETMODE) != 0)
driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd)
 4764                                  + /*DMA WideOdd Bug Buffer*/1;
ahc->init_level++;
 4768         if (ahc_createdmamem(ahc->parent_dmat, driver_data_size,
ahc->sc_dmaflags,
 4770                              &ahc->shared_data_dmamap, (caddr_t *)&ahc->qoutfifo,
 4771                              &ahc->shared_data_busaddr, &ahc->shared_data_seg,
 4772                              &ahc->shared_data_nseg, ahc_name(ahc), "shared data") < 0)
 4773                 return (ENOMEM);
ahc->init_level++;
 4777         if ((ahc->features & AHC_TARGETMODE) != 0) {
ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo;
ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS];
ahc->dma_bug_buf = ahc->shared_data_busaddr
 4781                                  + driver_data_size - 1;
 4782                 /* All target command blocks start out invalid. */
 4783                 for (i = 0; i < AHC_TMODE_CMDS; i++)
ahc->targetcmds[i].cmd_valid = 0;
 4785 #ifdef __sgi__
ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
 4787 #else
ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD);
 4789 #endif
ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256];
 4791         }
ahc->qinfifo = &ahc->qoutfifo[256];
ahc->init_level++;
 4796         /* Allocate SCB data now that buffer_dmat is initialized */
 4797         if (ahc->scb_data->maxhscbs == 0)
 4798                 if (ahc_init_scbdata(ahc) != 0)
 4799                         return (ENOMEM);
 4801         /*
 4802          * Allocate a tstate to house information for our
 4803          * initiator presence on the bus as well as the user
 4804          * data for any target mode initiator.
 4805          */
 4806         if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) {
printf("%s: unable to allocate ahc_tmode_tstate.  "
 4808                        "Failing attach\n", ahc_name(ahc));
 4809                 return (ENOMEM);
 4810         }
 4812         if ((ahc->features & AHC_TWIN) != 0) {
 4813                 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) {
printf("%s: unable to allocate ahc_tmode_tstate.  "
 4815                                "Failing attach\n", ahc_name(ahc));
 4816                         return (ENOMEM);
 4817                 }
 4818         }
ahc_outb(ahc, SEQ_FLAGS, 0);
ahc_outb(ahc, SEQ_FLAGS2, 0);
 4823         if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) {
ahc->flags |= AHC_PAGESCBS;
 4825         } else {
ahc->flags &= ~AHC_PAGESCBS;
 4827         }
 4829 #ifdef AHC_DEBUG
 4830         if (ahc_debug & AHC_SHOW_MISC) {
printf("%s: hardware scb %u bytes; kernel scb %u bytes; "
 4832                        "ahc_dma %u bytes\n",
ahc_name(ahc),
 4834                         (u_int)sizeof(struct hardware_scb),
 4835                         (u_int)sizeof(struct scb),
 4836                         (u_int)sizeof(struct ahc_dma_seg));
 4837         }
 4838 #endif /* AHC_DEBUG */
 4840         /*
 4841          * Look at the information that board initialization or
 4842          * the board bios has left us.
 4843          */
 4844         if (ahc->features & AHC_TWIN) {
scsi_conf = ahc_inb(ahc, SCSICONF + 1);
 4846                 if ((scsi_conf & RESET_SCSI) != 0
 4847                  && (ahc->flags & AHC_INITIATORROLE) != 0)
ahc->flags |= AHC_RESET_BUS_B;
 4849         }
scsi_conf = ahc_inb(ahc, SCSICONF);
 4852         if ((scsi_conf & RESET_SCSI) != 0
 4853          && (ahc->flags & AHC_INITIATORROLE) != 0)
ahc->flags |= AHC_RESET_BUS_A;
ultraenb = 0;   
tagenable = ALL_TARGETS_MASK;
 4859         /* Grab the disconnection disable table and invert it for our needs */
 4860         if ((ahc->flags & AHC_USEDEFAULTS) != 0) {
printf("%s: Host Adapter Bios disabled.  Using default SCSI "
 4862                         "device parameters\n", ahc_name(ahc));
ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B|
AHC_TERM_ENB_A|AHC_TERM_ENB_B;
discenable = ALL_TARGETS_MASK;
 4866                 if ((ahc->features & AHC_ULTRA) != 0)
ultraenb = ALL_TARGETS_MASK;
 4868         } else {
discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8)
 4870                            | ahc_inb(ahc, DISC_DSB));
 4871                 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0)
ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8)
 4873                                       | ahc_inb(ahc, ULTRA_ENB);
 4874         }
 4876         if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0)
max_targ = 7;
 4879         for (i = 0; i <= max_targ; i++) {
 4880                 struct ahc_initiator_tinfo *tinfo;
 4881                 struct ahc_tmode_tstate *tstate;
u_int our_id;
u_int target_id;
 4884                 char channel;
channel = 'A';
our_id = ahc->our_id;
target_id = i;
 4889                 if (i > 7 && (ahc->features & AHC_TWIN) != 0) {
channel = 'B';
our_id = ahc->our_id_b;
target_id = i % 8;
 4893                 }
tinfo = ahc_fetch_transinfo(ahc, channel, our_id,
target_id, &tstate);
 4896                 /* Default to async narrow across the board */
memset(tinfo, 0, sizeof(*tinfo));
 4898                 if (ahc->flags & AHC_USEDEFAULTS) {
 4899                         if ((ahc->features & AHC_WIDE) != 0)
tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
 4902                         /*
 4903                          * These will be truncated when we determine the
 4904                          * connection type we have with the target.
 4905                          */
tinfo->user.period = ahc_syncrates->period;
tinfo->user.offset = MAX_OFFSET;
 4908                 } else {
u_int scsirate;
uint16_t mask;
 4912                         /* Take the settings leftover in scratch RAM. */
scsirate = ahc_inb(ahc, TARG_SCSIRATE + i);
mask = (0x01 << i);
 4915                         if ((ahc->features & AHC_ULTRA2) != 0) {
u_int offset;
u_int maxsync;
 4919                                 if ((scsirate & SOFS) == 0x0F) {
 4920                                         /*
 4921                                          * Haven't negotiated yet,
 4922                                          * so the format is different.
 4923                                          */
scsirate = (scsirate & SXFR) >> 4
 4925                                                  | (ultraenb & mask)
 4926                                                   ? 0x08 : 0x0
 4927                                                  | (scsirate & WIDEXFER);
offset = MAX_OFFSET_ULTRA2;
 4929                                 } else
offset = ahc_inb(ahc, TARG_OFFSET + i);
 4931                                 if ((scsirate & ~WIDEXFER) == 0 && offset != 0)
 4932                                         /* Set to the lowest sync rate, 5MHz */
scsirate |= 0x1c;
maxsync = AHC_SYNCRATE_ULTRA2;
 4935                                 if ((ahc->features & AHC_DT) != 0)
maxsync = AHC_SYNCRATE_DT;
tinfo->user.period =
ahc_find_period(ahc, scsirate, maxsync);
 4939                                 if (offset == 0)
tinfo->user.period = 0;
 4941                                 else
tinfo->user.offset = MAX_OFFSET;
 4943                                 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/
 4944                                  && (ahc->features & AHC_DT) != 0)
tinfo->user.ppr_options =
MSG_EXT_PPR_DT_REQ;
 4947                         } else if ((scsirate & SOFS) != 0) {
 4948                                 if ((scsirate & SXFR) == 0x40
 4949                                  && (ultraenb & mask) != 0) {
 4950                                         /* Treat 10MHz as a non-ultra speed */
scsirate &= ~SXFR;
ultraenb &= ~mask;
 4953                                 }
tinfo->user.period = 
ahc_find_period(ahc, scsirate,
 4956                                                     (ultraenb & mask)
 4957                                                    ? AHC_SYNCRATE_ULTRA
 4958                                                    : AHC_SYNCRATE_FAST);
 4959                                 if (tinfo->user.period != 0)
tinfo->user.offset = MAX_OFFSET;
 4961                         }
 4962                         if (tinfo->user.period == 0)
tinfo->user.offset = 0;
 4964                         if ((scsirate & WIDEXFER) != 0
 4965                          && (ahc->features & AHC_WIDE) != 0)
tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
tinfo->user.protocol_version = 4;
 4968                         if ((ahc->features & AHC_DT) != 0)
tinfo->user.transport_version = 3;
 4970                         else
tinfo->user.transport_version = 2;
tinfo->goal.protocol_version = 2;
tinfo->goal.transport_version = 2;
tinfo->curr.protocol_version = 2;
tinfo->curr.transport_version = 2;
 4976                 }
tstate->ultraenb = 0;
tstate->discenable = discenable;
 4979         }
ahc->user_discenable = discenable;
ahc->user_tagenable = tagenable;
 4983         return (ahc->bus_chip_init(ahc));
 4984 }
 4986 void
ahc_intr_enable(struct ahc_softc *ahc, int enable)
 4988 {
u_int hcntrl;
hcntrl = ahc_inb(ahc, HCNTRL);
hcntrl &= ~INTEN;
ahc->pause &= ~INTEN;
ahc->unpause &= ~INTEN;
 4995         if (enable) {
hcntrl |= INTEN;
ahc->pause |= INTEN;
ahc->unpause |= INTEN;
 4999         }
ahc_outb(ahc, HCNTRL, hcntrl);
 5001 }
 5003 /************************** Busy Target Table *********************************/
 5004 /*
 5005  * Return the untagged transaction id for a given target/channel lun.
 5006  * Optionally, clear the entry.
 5007  */
u_int
ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl)
 5010 {
u_int scbid;
u_int target_offset;
 5014         if ((ahc->flags & AHC_SCB_BTT) != 0) {
u_int saved_scbptr;
saved_scbptr = ahc_inb(ahc, SCBPTR);
ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl));
ahc_outb(ahc, SCBPTR, saved_scbptr);
 5021         } else {
target_offset = TCL_TARGET_OFFSET(tcl);
scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset);
 5024         }
 5026         return (scbid);
 5027 }
 5029 void
ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl)
 5031 {
u_int target_offset;
 5034         if ((ahc->flags & AHC_SCB_BTT) != 0) {
u_int saved_scbptr;
saved_scbptr = ahc_inb(ahc, SCBPTR);
ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL);
ahc_outb(ahc, SCBPTR, saved_scbptr);
 5041         } else {
target_offset = TCL_TARGET_OFFSET(tcl);
ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL);
 5044         }
 5045 }
 5047 void
ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid)
 5049 {
u_int target_offset;
 5052         if ((ahc->flags & AHC_SCB_BTT) != 0) {
u_int saved_scbptr;
saved_scbptr = ahc_inb(ahc, SCBPTR);
ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid);
ahc_outb(ahc, SCBPTR, saved_scbptr);
 5059         } else {
target_offset = TCL_TARGET_OFFSET(tcl);
ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid);
 5062         }
 5063 }
 5065 /************************** SCB and SCB queue management **********************/
 5066 int
ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target,
 5068               char channel, int lun, u_int tag, role_t role)
 5069 {
 5070         char chan;
 5071         int targ, slun, match;
 5073         if (scb == NULL)
 5074                 return 0;
targ = SCB_GET_TARGET(ahc, scb);
chan = SCB_GET_CHANNEL(ahc, scb);
slun = SCB_GET_LUN(scb);
match = ((chan == channel) || (channel == ALL_CHANNELS));
 5081         if (match != 0)
match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
 5083         if (match != 0)
match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
 5085         if (match != 0) {
 5086 #ifdef AHC_TARGET_MODE
 5087                 int group;
group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
 5090                 if (role == ROLE_INITIATOR) {
match = (group != XPT_FC_GROUP_TMODE)
 5092                               && ((tag == scb->hscb->tag)
 5093                                || (tag == SCB_LIST_NULL));
 5094                 } else if (role == ROLE_TARGET) {
match = (group == XPT_FC_GROUP_TMODE)
 5096                               && ((tag == scb->io_ctx->csio.tag_id)
 5097                                || (tag == SCB_LIST_NULL));
 5098                 }
 5099 #else /* !AHC_TARGET_MODE */
match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL));
 5101 #endif /* AHC_TARGET_MODE */
 5102         }
 5104         return match;
 5105 }
 5107 void
ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb)
 5109 {
 5110         int     target;
 5111         char    channel;
 5112         int     lun;
target = SCB_GET_TARGET(ahc, scb);
lun = SCB_GET_LUN(scb);
channel = SCB_GET_CHANNEL(ahc, scb);
ahc_search_qinfifo(ahc, target, channel, lun,
 5119                            /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN,
CAM_REQUEUE_REQ, SEARCH_COMPLETE);
ahc_platform_freeze_devq(ahc, scb);
 5123 }
 5125 void
ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb)
 5127 {
 5128         struct scb *prev_scb;
prev_scb = NULL;
 5131         if (ahc_qinfifo_count(ahc) != 0) {
u_int prev_tag;
uint8_t prev_pos;
prev_pos = ahc->qinfifonext - 1;
prev_tag = ahc->qinfifo[prev_pos];
prev_scb = ahc_lookup_scb(ahc, prev_tag);
 5138         }
ahc_qinfifo_requeue(ahc, prev_scb, scb);
 5140         if ((ahc->features & AHC_QUEUE_REGS) != 0) {
ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
 5142         } else {
ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
 5144         }
 5145 }
 5147 static void
ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb,
 5149                     struct scb *scb)
 5150 {
 5151         if (prev_scb == NULL) {
ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
 5153         } else {
prev_scb->hscb->next = scb->hscb->tag;
ahc_sync_scb(ahc, prev_scb, 
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
 5157         }
ahc->qinfifo[ahc->qinfifonext] = scb->hscb->tag;
ahc_dmamap_sync(ahc, ahc->parent_dmat, ahc->shared_data_dmamap,
 5160                         /*offset*/ahc->qinfifonext+256, /*len*/1,
BUS_DMASYNC_PREWRITE);
ahc->qinfifonext++;
scb->hscb->next = ahc->next_queued_scb->hscb->tag;
ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
 5165 }
 5167 static int
ahc_qinfifo_count(struct ahc_softc *ahc)
 5169 {
uint8_t qinpos;
uint8_t diff;
 5173         if ((ahc->features & AHC_QUEUE_REGS) != 0) {
qinpos = ahc_inb(ahc, SNSCB_QOFF);
ahc_outb(ahc, SNSCB_QOFF, qinpos);
 5176         } else
qinpos = ahc_inb(ahc, QINPOS);
diff = ahc->qinfifonext - qinpos;
 5179         return (diff);
 5180 }
 5182 int
ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel,
 5184                    int lun, u_int tag, role_t role, uint32_t status,
ahc_search_action action)
 5186 {
 5187         struct  scb *scb;
 5188         struct  scb *prev_scb;
uint8_t qinstart;
uint8_t qinpos;
uint8_t qintail;
uint8_t next;
uint8_t prev;
uint8_t curscbptr;
 5195         int     found;
 5196         int     have_qregs;
qintail = ahc->qinfifonext;
have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0;
 5200         if (have_qregs) {
qinstart = ahc_inb(ahc, SNSCB_QOFF);
ahc_outb(ahc, SNSCB_QOFF, qinstart);
 5203         } else
qinstart = ahc_inb(ahc, QINPOS);
qinpos = qinstart;
found = 0;
prev_scb = NULL;
 5209         if (action == SEARCH_COMPLETE) {
 5210                 /*
 5211                  * Don't attempt to run any queued untagged transactions
 5212                  * until we are done with the abort process.
 5213                  */
ahc_freeze_untagged_queues(ahc);
 5215         }
 5217         /*
 5218          * Start with an empty queue.  Entries that are not chosen
 5219          * for removal will be re-added to the queue as we go.
 5220          */
ahc->qinfifonext = qinpos;
ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
 5224         while (qinpos != qintail) {
scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]);
 5226                 if (scb == NULL) {
printf("qinpos = %d, SCB index = %d\n",
qinpos, ahc->qinfifo[qinpos]);
panic("Loop 1");
 5230                 }
 5232                 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) {
 5233                         /*
 5234                          * We found an scb that needs to be acted on.
 5235                          */
found++;
 5237                         switch (action) {
 5238                         case SEARCH_COMPLETE:
 5239                         {
cam_status ostat;
cam_status cstat;
ostat = ahc_get_transaction_status(scb);
 5244                                 if (ostat == CAM_REQ_INPROG)
ahc_set_transaction_status(scb, status);
cstat = ahc_get_transaction_status(scb);
 5247                                 if (cstat != CAM_REQ_CMP)
ahc_freeze_scb(scb);
 5249                                 if ((scb->flags & SCB_ACTIVE) == 0)
printf("Inactive SCB in qinfifo\n");
ahc_done(ahc, scb);
 5253                                 /* FALLTHROUGH */
 5254                         }
 5255                         case SEARCH_REMOVE:
 5256                                 break;
 5257                         case SEARCH_COUNT:
ahc_qinfifo_requeue(ahc, prev_scb, scb);
prev_scb = scb;
 5260                                 break;
 5261                         }
 5262                 } else {
ahc_qinfifo_requeue(ahc, prev_scb, scb);
prev_scb = scb;
 5265                 }
qinpos++;
 5267         }
 5269         if ((ahc->features & AHC_QUEUE_REGS) != 0) {
ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
 5271         } else {
ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
 5273         }
 5275         if (action != SEARCH_COUNT
 5276          && (found != 0)
 5277          && (qinstart != ahc->qinfifonext)) {
 5278                 /*
 5279                  * The sequencer may be in the process of DMA'ing
 5280                  * down the SCB at the beginning of the queue.
 5281                  * This could be problematic if either the first,
 5282                  * or the second SCB is removed from the queue
 5283                  * (the first SCB includes a pointer to the "next"
 5284                  * SCB to DMA). If we have removed any entries, swap
 5285                  * the first element in the queue with the next HSCB
 5286                  * so the sequencer will notice that NEXT_QUEUED_SCB
 5287                  * has changed during its DMA attempt and will retry
 5288                  * the DMA.
 5289                  */
scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]);
 5292                 if (scb == NULL) {
printf("found = %d, qinstart = %d, qinfifionext = %d\n",
found, qinstart, ahc->qinfifonext);
panic("First/Second Qinfifo fixup");
 5296                 }
 5297                 /*
 5298                  * ahc_swap_with_next_hscb forces our next pointer to
 5299                  * point to the reserved SCB for future commands.  Save
 5300                  * and restore our original next pointer to maintain
 5301                  * queue integrity.
 5302                  */
next = scb->hscb->next;
ahc->scb_data->scbindex[scb->hscb->tag] = NULL;
ahc_swap_with_next_hscb(ahc, scb);
scb->hscb->next = next;
ahc->qinfifo[qinstart] = scb->hscb->tag;
 5309                 /* Tell the card about the new head of the qinfifo. */
ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
 5312                 /* Fixup the tail "next" pointer. */
qintail = ahc->qinfifonext - 1;
scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]);
scb->hscb->next = ahc->next_queued_scb->hscb->tag;
 5316         }
 5318         /*
 5319          * Search waiting for selection list.
 5320          */
curscbptr = ahc_inb(ahc, SCBPTR);
next = ahc_inb(ahc, WAITING_SCBH);  /* Start at head of list. */
prev = SCB_LIST_NULL;
 5325         while (next != SCB_LIST_NULL) {
uint8_t scb_index;
ahc_outb(ahc, SCBPTR, next);
scb_index = ahc_inb(ahc, SCB_TAG);
 5330                 if (scb_index >= ahc->scb_data->numscbs) {
printf("Waiting List inconsistency. "
 5332                                "SCB index == %d, yet numscbs == %d.",
scb_index, ahc->scb_data->numscbs);
ahc_dump_card_state(ahc);
panic("for safety");
 5336                 }
scb = ahc_lookup_scb(ahc, scb_index);
 5338                 if (scb == NULL) {
printf("scb_index = %d, next = %d\n",
scb_index, next);
panic("Waiting List traversal");
 5342                 }
 5343                 if (ahc_match_scb(ahc, scb, target, channel,
lun, SCB_LIST_NULL, role)) {
 5345                         /*
 5346                          * We found an scb that needs to be acted on.
 5347                          */
found++;
 5349                         switch (action) {
 5350                         case SEARCH_COMPLETE:
 5351                         {
cam_status ostat;
cam_status cstat;
ostat = ahc_get_transaction_status(scb);
 5356                                 if (ostat == CAM_REQ_INPROG)
ahc_set_transaction_status(scb, status);
cstat = ahc_get_transaction_status(scb);
 5359                                 if (cstat != CAM_REQ_CMP)
ahc_freeze_scb(scb);
 5361                                 if ((scb->flags & SCB_ACTIVE) == 0)
printf("Inactive SCB in Wait List\n");
ahc_done(ahc, scb);
 5364                                 /* FALLTHROUGH */
 5365                         }
 5366                         case SEARCH_REMOVE:
next = ahc_rem_wscb(ahc, next, prev);
 5368                                 break;
 5369                         case SEARCH_COUNT:
prev = next;
next = ahc_inb(ahc, SCB_NEXT);
 5372                                 break;
 5373                         }
 5374                 } else {
prev = next;
next = ahc_inb(ahc, SCB_NEXT);
 5378                 }
 5379         }
ahc_outb(ahc, SCBPTR, curscbptr);
found += ahc_search_untagged_queues(ahc, /*scsi_xfer*/NULL, target,
channel, lun, status, action);
 5385         if (action == SEARCH_COMPLETE)
ahc_release_untagged_queues(ahc);
 5387         return (found);
 5388 }
 5390 int
ahc_search_untagged_queues(struct ahc_softc *ahc, struct scsi_xfer *xs,
 5392                            int target, char channel, int lun, uint32_t status,
ahc_search_action action)
 5394 {
 5395         struct  scb *scb;
 5396         int     maxtarget;
 5397         int     found;
 5398         int     i;
 5400         if (action == SEARCH_COMPLETE) {
 5401                 /*
 5402                  * Don't attempt to run any queued untagged transactions
 5403                  * until we are done with the abort process.
 5404                  */
ahc_freeze_untagged_queues(ahc);
 5406         }
found = 0;
i = 0;
 5410         if ((ahc->flags & AHC_SCB_BTT) == 0) {
maxtarget = 16;
 5413                 if (target != CAM_TARGET_WILDCARD) {
i = target;
 5416                         if (channel == 'B')
i += 8;
maxtarget = i + 1;
 5419                 }
 5420         } else {
maxtarget = 0;
 5422         }
 5424         for (; i < maxtarget; i++) {
 5425                 struct scb_tailq *untagged_q;
 5426                 struct scb *next_scb;
untagged_q = &(ahc->untagged_queues[i]);
next_scb = TAILQ_FIRST(untagged_q);
 5430                 while (next_scb != NULL) {
scb = next_scb;
next_scb = TAILQ_NEXT(scb, links.tqe);
 5435                         /*
 5436                          * The head of the list may be the currently
 5437                          * active untagged command for a device.
 5438                          * We're only searching for commands that
 5439                          * have not been started.  A transaction
 5440                          * marked active but still in the qinfifo
 5441                          * is removed by the qinfifo scanning code
 5442                          * above.
 5443                          */
 5444                         if ((scb->flags & SCB_ACTIVE) != 0)
 5445                                 continue;
 5447                         if (ahc_match_scb(ahc, scb, target, channel, lun,
SCB_LIST_NULL, ROLE_INITIATOR) == 0
 5449                             || (xs != NULL && xs != scb->xs))
 5450                                 continue;
 5452                         /*
 5453                          * We found an scb that needs to be acted on.
 5454                          */
found++;
 5456                         switch (action) {
 5457                         case SEARCH_COMPLETE:
 5458                         {
cam_status ostat;
cam_status cstat;
ostat = ahc_get_transaction_status(scb);
 5463                                 if (ostat == CAM_REQ_INPROG)
ahc_set_transaction_status(scb, status);
cstat = ahc_get_transaction_status(scb);
 5466                                 if (cstat != CAM_REQ_CMP)
ahc_freeze_scb(scb);
ahc_done(ahc, scb);
 5469                                 break;
 5470                         }
 5471                         case SEARCH_REMOVE:
scb->flags &= ~SCB_UNTAGGEDQ;
TAILQ_REMOVE(untagged_q, scb, links.tqe);
 5474                                 break;
 5475                         case SEARCH_COUNT:
 5476                                 break;
 5477                         }
 5478                 }
 5479         }
 5481         if (action == SEARCH_COMPLETE)
ahc_release_untagged_queues(ahc);
 5483         return (found);
 5484 }
 5486 int
ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel,
 5488                      int lun, u_int tag, int stop_on_first, int remove,
 5489                      int save_state)
 5490 {
 5491         struct  scb *scbp;
u_int   next;
u_int   prev;
u_int   count;
u_int   active_scb;
count = 0;
next = ahc_inb(ahc, DISCONNECTED_SCBH);
prev = SCB_LIST_NULL;
 5501         if (save_state) {
 5502                 /* restore this when we're done */
active_scb = ahc_inb(ahc, SCBPTR);
 5504         } else
 5505                 /* Silence compiler */
active_scb = SCB_LIST_NULL;
 5508         while (next != SCB_LIST_NULL) {
u_int scb_index;
ahc_outb(ahc, SCBPTR, next);
scb_index = ahc_inb(ahc, SCB_TAG);
 5513                 if (scb_index >= ahc->scb_data->numscbs) {
printf("Disconnected List inconsistency. "
 5515                                "SCB index == %d, yet numscbs == %d.",
scb_index, ahc->scb_data->numscbs);
ahc_dump_card_state(ahc);
panic("for safety");
 5519                 }
 5521                 if (next == prev) {
panic("Disconnected List Loop. "
 5523                               "cur SCBPTR == %x, prev SCBPTR == %x.",
next, prev);
 5525                 }
scbp = ahc_lookup_scb(ahc, scb_index);
 5527                 if (ahc_match_scb(ahc, scbp, target, channel, lun,
tag, ROLE_INITIATOR)) {
count++;
 5530                         if (remove) {
next =
ahc_rem_scb_from_disc_list(ahc, prev, next);
 5533                         } else {
prev = next;
next = ahc_inb(ahc, SCB_NEXT);
 5536                         }
 5537                         if (stop_on_first)
 5538                                 break;
 5539                 } else {
prev = next;
next = ahc_inb(ahc, SCB_NEXT);
 5542                 }
 5543         }
 5544         if (save_state)
ahc_outb(ahc, SCBPTR, active_scb);
 5546         return (count);
 5547 }
 5549 /*
 5550  * Remove an SCB from the on chip list of disconnected transactions.
 5551  * This is empty/unused if we are not performing SCB paging.
 5552  */
 5553 static u_int
ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr)
 5555 {
u_int next;
ahc_outb(ahc, SCBPTR, scbptr);
next = ahc_inb(ahc, SCB_NEXT);
ahc_outb(ahc, SCB_CONTROL, 0);
ahc_add_curscb_to_free_list(ahc);
 5565         if (prev != SCB_LIST_NULL) {
ahc_outb(ahc, SCBPTR, prev);
ahc_outb(ahc, SCB_NEXT, next);
 5568         } else
ahc_outb(ahc, DISCONNECTED_SCBH, next);
 5571         return (next);
 5572 }
 5574 /*
 5575  * Add the SCB as selected by SCBPTR onto the on chip list of
 5576  * free hardware SCBs.  This list is empty/unused if we are not
 5577  * performing SCB paging.
 5578  */
 5579 static void
ahc_add_curscb_to_free_list(struct ahc_softc *ahc)
 5581 {
 5582         /*
 5583          * Invalidate the tag so that our abort
 5584          * routines don't think it's active.
 5585          */
ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
 5588         if ((ahc->flags & AHC_PAGESCBS) != 0) {
ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH));
ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR));
 5591         }
 5592 }
 5594 /*
 5595  * Manipulate the waiting for selection list and return the
 5596  * scb that follows the one that we remove.
 5597  */
 5598 static u_int
ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev)
 5600 {       
u_int curscb, next;
 5603         /*
 5604          * Select the SCB we want to abort and
 5605          * pull the next pointer out of it.
 5606          */
curscb = ahc_inb(ahc, SCBPTR);
ahc_outb(ahc, SCBPTR, scbpos);
next = ahc_inb(ahc, SCB_NEXT);
 5611         /* Clear the necessary fields */
ahc_outb(ahc, SCB_CONTROL, 0);
ahc_add_curscb_to_free_list(ahc);
 5616         /* update the waiting list */
 5617         if (prev == SCB_LIST_NULL) {
 5618                 /* First in the list */
ahc_outb(ahc, WAITING_SCBH, next); 
 5621                 /*
 5622                  * Ensure we aren't attempting to perform
 5623                  * selection for this entry.
 5624                  */
ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
 5626         } else {
 5627                 /*
 5628                  * Select the scb that pointed to us 
 5629                  * and update its next pointer.
 5630                  */
ahc_outb(ahc, SCBPTR, prev);
ahc_outb(ahc, SCB_NEXT, next);
 5633         }
 5635         /*
 5636          * Point us back at the original scb position.
 5637          */
ahc_outb(ahc, SCBPTR, curscb);
 5639         return next;
 5640 }
 5642 /******************************** Error Handling ******************************/
 5643 /*
 5644  * Abort all SCBs that match the given description (target/channel/lun/tag),
 5645  * setting their status to the passed in status if the status has not already
 5646  * been modified from CAM_REQ_INPROG.  This routine assumes that the sequencer
 5647  * is paused before it is called.
 5648  */
 5649 int
ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel,
 5651                int lun, u_int tag, role_t role, uint32_t status)
 5652 {
 5653         struct  scb *scbp;
 5654         struct  scb *scbp_next;
u_int   active_scb;
 5656         int     i, j;
 5657         int     maxtarget;
 5658         int     minlun;
 5659         int     maxlun;
 5661         int     found;
 5663         /*
 5664          * Don't attempt to run any queued untagged transactions
 5665          * until we are done with the abort process.
 5666          */
ahc_freeze_untagged_queues(ahc);
 5669         /* restore this when we're done */
active_scb = ahc_inb(ahc, SCBPTR);
found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL,
role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
 5675         /*
 5676          * Clean out the busy target table for any untagged commands.
 5677          */
i = 0;
maxtarget = 16;
 5680         if (target != CAM_TARGET_WILDCARD) {
i = target;
 5682                 if (channel == 'B')
i += 8;
maxtarget = i + 1;
 5685         }
 5687         if (lun == CAM_LUN_WILDCARD) {
 5689                 /*
 5690                  * Unless we are using an SCB based
 5691                  * busy targets table, there is only
 5692                  * one table entry for all luns of
 5693                  * a target.
 5694                  */
minlun = 0;
maxlun = 1;
 5697                 if ((ahc->flags & AHC_SCB_BTT) != 0)
maxlun = AHC_NUM_LUNS;
 5699         } else {
minlun = lun;
maxlun = lun + 1;
 5702         }
 5704         if (role != ROLE_TARGET) {
 5705                 for (;i < maxtarget; i++) {
 5706                         for (j = minlun;j < maxlun; j++) {
u_int scbid;
u_int tcl;
tcl = BUILD_TCL(i << 4, j);
scbid = ahc_index_busy_tcl(ahc, tcl);
scbp = ahc_lookup_scb(ahc, scbid);
 5713                                 if (scbp == NULL
 5714                                  || ahc_match_scb(ahc, scbp, target, channel,
lun, tag, role) == 0)
 5716                                         continue;
ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j));
 5718                         }
 5719                 }
 5721                 /*
 5722                  * Go through the disconnected list and remove any entries we
 5723                  * have queued for completion, 0'ing their control byte too.
 5724                  * We save the active SCB and restore it ourselves, so there
 5725                  * is no reason for this search to restore it too.
 5726                  */
ahc_search_disc_list(ahc, target, channel, lun, tag,
 5728                                      /*stop_on_first*/FALSE, /*remove*/TRUE,
 5729                                      /*save_state*/FALSE);
 5730         }
 5732         /*
 5733          * Go through the hardware SCB array looking for commands that
 5734          * were active but not on any list.  In some cases, these remnants
 5735          * might not still have mappings in the scbindex array (e.g. unexpected
 5736          * bus free with the same scb queued for an abort).  Don't hold this
 5737          * against them.
 5738          */
 5739         for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
u_int scbid;
ahc_outb(ahc, SCBPTR, i);
scbid = ahc_inb(ahc, SCB_TAG);
scbp = ahc_lookup_scb(ahc, scbid);
 5745                 if ((scbp == NULL && scbid != SCB_LIST_NULL)
 5746                  || (scbp != NULL
 5747                   && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)))
ahc_add_curscb_to_free_list(ahc);
 5749         }
 5751         /*
 5752          * Go through the pending CCB list and look for
 5753          * commands for this target that are still active.
 5754          * These are other tagged commands that were
 5755          * disconnected when the reset occurred.
 5756          */
scbp_next = LIST_FIRST(&ahc->pending_scbs);
 5758         while (scbp_next != NULL) {
scbp = scbp_next;
scbp_next = LIST_NEXT(scbp, pending_links);
 5761                 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) {
cam_status ostat;
ostat = ahc_get_transaction_status(scbp);
 5765                         if (ostat == CAM_REQ_INPROG)
ahc_set_transaction_status(scbp, status);
 5767                         if (ahc_get_transaction_status(scbp) != CAM_REQ_CMP)
ahc_freeze_scb(scbp);
 5769                         if ((scbp->flags & SCB_ACTIVE) == 0)
printf("Inactive SCB on pending list\n");
ahc_done(ahc, scbp);
found++;
 5773                 }
 5774         }
ahc_outb(ahc, SCBPTR, active_scb);
ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status);
ahc_release_untagged_queues(ahc);
 5778         return found;
 5779 }
 5781 static void
ahc_reset_current_bus(struct ahc_softc *ahc)
 5783 {
uint8_t scsiseq;
ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST);
scsiseq = ahc_inb(ahc, SCSISEQ);
ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO);
ahc_flush_device_writes(ahc);
aic_delay(AHC_BUSRESET_DELAY);
 5791         /* Turn off the bus reset */
ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO);
ahc_clear_intstat(ahc);
 5796         /* Re-enable reset interrupts */
ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST);
 5798 }
 5800 int
ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset)
 5802 {
 5803         struct  ahc_devinfo devinfo;
u_int   initiator, target, max_scsiid;
u_int   sblkctl;
u_int   scsiseq;
u_int   simode1;
 5808         int     found;
 5809         int     restart_needed;
 5810         char    cur_channel;
ahc->pending_device = NULL;
ahc_compile_devinfo(&devinfo,
CAM_TARGET_WILDCARD,
CAM_TARGET_WILDCARD,
CAM_LUN_WILDCARD,
channel, ROLE_UNKNOWN);
ahc_pause(ahc);
 5821         /* Make sure the sequencer is in a safe location. */
ahc_clear_critical_section(ahc);
 5824         /*
 5825          * Run our command complete fifos to ensure that we perform
 5826          * completion processing on any commands that 'completed'
 5827          * before the reset occurred.
 5828          */
ahc_run_qoutfifo(ahc);
 5830 #ifdef AHC_TARGET_MODE
 5831         /*
 5832          * XXX - In Twin mode, the tqinfifo may have commands
 5833          *       for an unaffected channel in it.  However, if
 5834          *       we have run out of ATIO resources to drain that
 5835          *       queue, we may not get them all out here.  Further,
 5836          *       the blocked transactions for the reset channel
 5837          *       should just be killed off, irrespecitve of whether
 5838          *       we are blocked on ATIO resources.  Write a routine
 5839          *       to compact the tqinfifo appropriately.
 5840          */
 5841         if ((ahc->flags & AHC_TARGETROLE) != 0) {
ahc_run_tqinfifo(ahc, /*paused*/TRUE);
 5843         }
 5844 #endif
 5846         /*
 5847          * Reset the bus if we are initiating this reset
 5848          */
sblkctl = ahc_inb(ahc, SBLKCTL);
cur_channel = 'A';
 5851         if ((ahc->features & AHC_TWIN) != 0
 5852          && ((sblkctl & SELBUSB) != 0))
cur_channel = 'B';
scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
 5855         if (cur_channel != channel) {
 5856                 /* Case 1: Command for another bus is active
 5857                  * Stealthily reset the other bus without
 5858                  * upsetting the current bus.
 5859                  */
ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB);
simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
 5862 #ifdef AHC_TARGET_MODE
 5863                 /*
 5864                  * Bus resets clear ENSELI, so we cannot
 5865                  * defer re-enabling bus reset interrupts
 5866                  * if we are in target mode.
 5867                  */
 5868                 if ((ahc->flags & AHC_TARGETROLE) != 0)
simode1 |= ENSCSIRST;
 5870 #endif
ahc_outb(ahc, SIMODE1, simode1);
 5872                 if (initiate_reset)
ahc_reset_current_bus(ahc);
ahc_clear_intstat(ahc);
ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
ahc_outb(ahc, SBLKCTL, sblkctl);
restart_needed = FALSE;
 5878         } else {
 5879                 /* Case 2: A command from this bus is active or we're idle */
simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
 5881 #ifdef AHC_TARGET_MODE
 5882                 /*
 5883                  * Bus resets clear ENSELI, so we cannot
 5884                  * defer re-enabling bus reset interrupts
 5885                  * if we are in target mode.
 5886                  */
 5887                 if ((ahc->flags & AHC_TARGETROLE) != 0)
simode1 |= ENSCSIRST;
 5889 #endif
ahc_outb(ahc, SIMODE1, simode1);
 5891                 if (initiate_reset)
ahc_reset_current_bus(ahc);
ahc_clear_intstat(ahc);
ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
restart_needed = TRUE;
 5896         }
 5898         /*
 5899          * Clean up all the state information for the
 5900          * pending transactions on this bus.
 5901          */
found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel,
CAM_LUN_WILDCARD, SCB_LIST_NULL,
ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7;
 5908 #ifdef AHC_TARGET_MODE
 5909         /*
 5910          * Send an immediate notify ccb to all target more peripheral
 5911          * drivers affected by this action.
 5912          */
 5913         for (target = 0; target <= max_scsiid; target++) {
 5914                 struct ahc_tmode_tstate* tstate;
u_int lun;
tstate = ahc->enabled_targets[target];
 5918                 if (tstate == NULL)
 5919                         continue;
 5920                 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
 5921                         struct ahc_tmode_lstate* lstate;
lstate = tstate->enabled_luns[lun];
 5924                         if (lstate == NULL)
 5925                                 continue;
ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD,
EVENT_TYPE_BUS_RESET, /*arg*/0);
ahc_send_lstate_events(ahc, lstate);
 5930                 }
 5931         }
 5932 #endif
 5933         /* Notify the XPT that a bus reset occurred */
ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD,
CAM_LUN_WILDCARD, AC_BUS_RESET, NULL);
 5937         /*
 5938          * Revert to async/narrow transfers until we renegotiate.
 5939          */
 5940         for (target = 0; target <= max_scsiid; target++) {
 5942                 if (ahc->enabled_targets[target] == NULL)
 5943                         continue;
 5944                 for (initiator = 0; initiator <= max_scsiid; initiator++) {
 5945                         struct ahc_devinfo devinfo;
ahc_compile_devinfo(&devinfo, target, initiator,
CAM_LUN_WILDCARD,
channel, ROLE_UNKNOWN);
ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
AHC_TRANS_CUR, /*paused*/TRUE);
ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL,
 5953                                          /*period*/0, /*offset*/0,
 5954                                          /*ppr_options*/0, AHC_TRANS_CUR,
 5955                                          /*paused*/TRUE);
 5956                 }
 5957         }
 5959         if (restart_needed)
ahc_restart(ahc);
 5961         else
ahc_unpause(ahc);
 5963         return found;
 5964 }
 5967 /***************************** Residual Processing ****************************/
 5968 /*
 5969  * Calculate the residual for a just completed SCB.
 5970  */
 5971 void
ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb)
 5973 {
 5974         struct hardware_scb *hscb;
 5975         struct status_pkt *spkt;
uint32_t sgptr;
uint32_t resid_sgptr;
uint32_t resid;
 5980         /*
 5981          * 5 cases.
 5982          * 1) No residual.
 5983          *    SG_RESID_VALID clear in sgptr.
 5984          * 2) Transferless command
 5985          * 3) Never performed any transfers.
 5986          *    sgptr has SG_FULL_RESID set.
 5987          * 4) No residual but target did not
 5988          *    save data pointers after the
 5989          *    last transfer, so sgptr was
 5990          *    never updated.
 5991          * 5) We have a partial residual.
 5992          *    Use residual_sgptr to determine
 5993          *    where we are.
 5994          */
hscb = scb->hscb;
sgptr = aic_le32toh(hscb->sgptr);
 5998         if ((sgptr & SG_RESID_VALID) == 0)
 5999                 /* Case 1 */
 6000                 return;
sgptr &= ~SG_RESID_VALID;
 6003         if ((sgptr & SG_LIST_NULL) != 0)
 6004                 /* Case 2 */
 6005                 return;
spkt = &hscb->shared_data.status;
resid_sgptr = aic_le32toh(spkt->residual_sg_ptr);
 6009         if ((sgptr & SG_FULL_RESID) != 0) {
 6010                 /* Case 3 */
resid = ahc_get_transfer_length(scb);
 6012         } else if ((resid_sgptr & SG_LIST_NULL) != 0) {
 6013                 /* Case 4 */
 6014                 return;
 6015         } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) {
panic("Bogus resid sgptr value 0x%x", resid_sgptr);
 6017         } else {
 6018                 struct ahc_dma_seg *sg;
 6020                 /*
 6021                  * Remainder of the SG where the transfer
 6022                  * stopped.  
 6023                  */
resid = aic_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK;
sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK);
 6027                 /* The residual sg_ptr always points to the next sg */
sg--;
 6030                 /*
 6031                  * Add up the contents of all residual
 6032                  * SG segments that are after the SG where
 6033                  * the transfer stopped.
 6034                  */
 6035                 while ((aic_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) {
sg++;
resid += aic_le32toh(sg->len) & AHC_SG_LEN_MASK;
 6038                 }
 6039         }
 6040         if ((scb->flags & SCB_SENSE) == 0)
ahc_set_residual(scb, resid);
 6042         else
ahc_set_sense_residual(scb, resid);
 6045 #ifdef AHC_DEBUG
 6046         if ((ahc_debug & AHC_SHOW_MISC) != 0) {
ahc_print_path(ahc, scb);
printf("Handled %sResidual of %d bytes\n",
 6049                        (scb->flags & SCB_SENSE) ? "Sense " : "", resid);
 6050         }
 6051 #endif
 6052 }
 6054 /******************************* Target Mode **********************************/
 6055 #ifdef AHC_TARGET_MODE
 6056 /*
 6057  * Add a target mode event to this lun's queue
 6058  */
 6059 static void
ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate,
u_int initiator_id, u_int event_type, u_int event_arg)
 6062 {
 6063         struct ahc_tmode_event *event;
 6064         int pending;
xpt_freeze_devq(lstate->path, /*count*/1);
 6067         if (lstate->event_w_idx >= lstate->event_r_idx)
pending = lstate->event_w_idx - lstate->event_r_idx;
 6069         else
pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1
 6071                         - (lstate->event_r_idx - lstate->event_w_idx);
 6073         if (event_type == EVENT_TYPE_BUS_RESET
 6074          || event_type == MSG_BUS_DEV_RESET) {
 6075                 /*
 6076                  * Any earlier events are irrelevant, so reset our buffer.
 6077                  * This has the effect of allowing us to deal with reset
 6078                  * floods (an external device holding down the reset line)
 6079                  * without losing the event that is really interesting.
 6080                  */
lstate->event_r_idx = 0;
lstate->event_w_idx = 0;
xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE);
 6084         }
 6086         if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) {
xpt_print_path(lstate->path);
printf("immediate event %x:%x lost\n",
lstate->event_buffer[lstate->event_r_idx].event_type,
lstate->event_buffer[lstate->event_r_idx].event_arg);
lstate->event_r_idx++;
 6092                 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
lstate->event_r_idx = 0;
xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE);
 6095         }
event = &lstate->event_buffer[lstate->event_w_idx];
event->initiator_id = initiator_id;
event->event_type = event_type;
event->event_arg = event_arg;
lstate->event_w_idx++;
 6102         if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
lstate->event_w_idx = 0;
 6104 }
 6106 /*
 6107  * Send any target mode events queued up waiting
 6108  * for immediate notify resources.
 6109  */
 6110 void
ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate)
 6112 {
 6113         struct ccb_hdr *ccbh;
 6114         struct ccb_immed_notify *inot;
 6116         while (lstate->event_r_idx != lstate->event_w_idx
 6117             && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) {
 6118                 struct ahc_tmode_event *event;
event = &lstate->event_buffer[lstate->event_r_idx];
SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle);
inot = (struct ccb_immed_notify *)ccbh;
 6123                 switch (event->event_type) {
 6124                 case EVENT_TYPE_BUS_RESET:
ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN;
 6126                         break;
 6127                 default:
ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN;
inot->message_args[0] = event->event_type;
inot->message_args[1] = event->event_arg;
 6131                         break;
 6132                 }
inot->initiator_id = event->initiator_id;
inot->sense_len = 0;
xpt_done((union ccb *)inot);
lstate->event_r_idx++;
 6137                 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
lstate->event_r_idx = 0;
 6139         }
 6140 }
 6141 #endif
 6143 /******************** Sequencer Program Patching/Download *********************/
 6145 #ifdef AHC_DUMP_SEQ
 6146 void
ahc_dumpseq(struct ahc_softc* ahc)
 6148 {
 6149         int i;
ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
ahc_outb(ahc, SEQADDR0, 0);
ahc_outb(ahc, SEQADDR1, 0);
 6154         for (i = 0; i < ahc->instruction_ram_size; i++) {
uint8_t ins_bytes[4];
ahc_insb(ahc, SEQRAM, ins_bytes, 4);
printf("0x%08x\n", ins_bytes[0] << 24
 6159                                  | ins_bytes[1] << 16
 6160                                  | ins_bytes[2] << 8
 6161                                  | ins_bytes[3]);
 6162         }
 6163 }
 6164 #endif
 6166 static int
ahc_loadseq(struct ahc_softc *ahc)
 6168 {
 6169         struct  cs cs_table[NUM_CRITICAL_SECTIONS];
u_int   begin_set[NUM_CRITICAL_SECTIONS];
u_int   end_set[NUM_CRITICAL_SECTIONS];
 6172         const struct    patch *cur_patch;
u_int   cs_count;
u_int   cur_cs;
u_int   i;
u_int   skip_addr;
u_int   sg_prefetch_cnt;
 6178         int     downloaded;
uint8_t download_consts[7];
 6181         /*
 6182          * Start out with 0 critical sections
 6183          * that apply to this firmware load.
 6184          */
cs_count = 0;
cur_cs = 0;
memset(begin_set, 0, sizeof(begin_set));
memset(end_set, 0, sizeof(end_set));
 6190         /* Setup downloadable constant table */
download_consts[QOUTFIFO_OFFSET] = 0;
 6192         if (ahc->targetcmds != NULL)
download_consts[QOUTFIFO_OFFSET] += 32;
download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1;
download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1;
download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1);
sg_prefetch_cnt = ahc->pci_cachesize;
 6198         if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg)))
sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg);
download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt;
download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1);
download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1);
cur_patch = patches;
downloaded = 0;
skip_addr = 0;
ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
ahc_outb(ahc, SEQADDR0, 0);
ahc_outb(ahc, SEQADDR1, 0);
 6211         for (i = 0; i < sizeof(seqprog)/4; i++) {
 6212                 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) {
 6213                         /*
 6214                          * Don't download this instruction as it
 6215                          * is in a patch that was removed.
 6216                          */
 6217                         continue;
 6218                 }
 6220                 if (downloaded == ahc->instruction_ram_size) {
 6221                         /*
 6222                          * We're about to exceed the instruction
 6223                          * storage capacity for this chip.  Fail
 6224                          * the load.
 6225                          */
printf("\n%s: Program too large for instruction memory "
 6227                                "size of %d!\n", ahc_name(ahc),
ahc->instruction_ram_size);
 6229                         return (ENOMEM);
 6230                 }
 6232                 /*
 6233                  * Move through the CS table until we find a CS
 6234                  * that might apply to this instruction.
 6235                  */
 6236                 for (; cur_cs < NUM_CRITICAL_SECTIONS; cur_cs++) {
 6237                         if (critical_sections[cur_cs].end <= i) {
 6238                                 if (begin_set[cs_count] == TRUE
 6239                                  && end_set[cs_count] == FALSE) {
cs_table[cs_count].end = downloaded;
end_set[cs_count] = TRUE;
cs_count++;
 6243                                 }
 6244                                 continue;
 6245                         }
 6246                         if (critical_sections[cur_cs].begin <= i
 6247                          && begin_set[cs_count] == FALSE) {
cs_table[cs_count].begin = downloaded;
begin_set[cs_count] = TRUE;
 6250                         }
 6251                         break;
 6252                 }
ahc_download_instr(ahc, i, download_consts);
downloaded++;
 6255         }
ahc->num_critical_sections = cs_count;
 6258         if (cs_count != 0) {
cs_count *= sizeof(struct cs);
ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT);
 6262                 if (ahc->critical_sections == NULL)
panic("ahc_loadseq: Could not malloc");
memcpy(ahc->critical_sections, cs_table, cs_count);
 6265         }
ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE);
 6268         if (bootverbose) {
printf(" %d instructions downloaded\n", downloaded);
printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags);
 6272         }
 6273         return (0);
 6274 }
 6276 static int
ahc_check_patch(struct ahc_softc *ahc, const struct patch **start_patch,
u_int start_instr, u_int *skip_addr)
 6279 {
 6280         const struct    patch *cur_patch;
 6281         const struct    patch *last_patch;
u_int   num_patches;
num_patches = sizeof(patches)/sizeof(struct patch);
last_patch = &patches[num_patches];
cur_patch = *start_patch;
 6288         while (cur_patch < last_patch && start_instr == cur_patch->begin) {
 6290                 if (cur_patch->patch_func(ahc) == 0) {
 6292                         /* Start rejecting code */
 6293                         *skip_addr = start_instr + cur_patch->skip_instr;
cur_patch += cur_patch->skip_patch;
 6295                 } else {
 6296                         /* Accepted this patch.  Advance to the next
 6297                          * one and wait for our intruction pointer to
 6298                          * hit this point.
 6299                          */
cur_patch++;
 6301                 }
 6302         }
 6304         *start_patch = cur_patch;
 6305         if (start_instr < *skip_addr)
 6306                 /* Still skipping */
 6307                 return (0);
 6309         return (1);
 6310 }
 6312 static void
ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts)
 6314 {
 6315         union   ins_formats instr;
 6316         struct  ins_format1 *fmt1_ins;
 6317         struct  ins_format3 *fmt3_ins;
u_int   opcode;
 6320         /*
 6321          * The firmware is always compiled into a little endian format.
 6322          */
instr.integer = aic_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);
fmt1_ins = &instr.format1;
fmt3_ins = NULL;
 6328         /* Pull the opcode */
opcode = instr.format1.opcode;
 6330         switch (opcode) {
 6331         case AIC_OP_JMP:
 6332         case AIC_OP_JC:
 6333         case AIC_OP_JNC:
 6334         case AIC_OP_CALL:
 6335         case AIC_OP_JNE:
 6336         case AIC_OP_JNZ:
 6337         case AIC_OP_JE:
 6338         case AIC_OP_JZ:
 6339         {
 6340                 const struct patch *cur_patch;
 6341                 int address_offset;
u_int address;
u_int skip_addr;
u_int i;
fmt3_ins = &instr.format3;
address_offset = 0;
address = fmt3_ins->address;
cur_patch = patches;
skip_addr = 0;
 6352                 for (i = 0; i < address;) {
ahc_check_patch(ahc, &cur_patch, i, &skip_addr);
 6356                         if (skip_addr > i) {
 6357                                 int end_addr;
end_addr = MIN(address, skip_addr);
address_offset += end_addr - i;
i = skip_addr;
 6362                         } else {
i++;
 6364                         }
 6365                 }
address -= address_offset;
fmt3_ins->address = address;
 6368                 /* FALLTHROUGH */
 6369         }
 6370         case AIC_OP_OR:
 6371         case AIC_OP_AND:
 6372         case AIC_OP_XOR:
 6373         case AIC_OP_ADD:
 6374         case AIC_OP_ADC:
 6375         case AIC_OP_BMOV:
 6376                 if (fmt1_ins->parity != 0) {
fmt1_ins->immediate = dconsts[fmt1_ins->immediate];
 6378                 }
fmt1_ins->parity = 0;
 6380                 if ((ahc->features & AHC_CMD_CHAN) == 0
 6381                  && opcode == AIC_OP_BMOV) {
 6382                         /*
 6383                          * Block move was added at the same time
 6384                          * as the command channel.  Verify that
 6385                          * this is only a move of a single element
 6386                          * and convert the BMOV to a MOV
 6387                          * (AND with an immediate of FF).
 6388                          */
 6389                         if (fmt1_ins->immediate != 1)
panic("%s: BMOV not supported",
ahc_name(ahc));
fmt1_ins->opcode = AIC_OP_AND;
fmt1_ins->immediate = 0xff;
 6394                 }
 6395                 /* FALLTHROUGH */
 6396         case AIC_OP_ROL:
 6397                 if ((ahc->features & AHC_ULTRA2) != 0) {
 6398                         int i, count;
 6400                         /* Calculate odd parity for the instruction */
 6401                         for (i = 0, count = 0; i < 31; i++) {
uint32_t mask;
mask = 0x01 << i;
 6405                                 if ((instr.integer & mask) != 0)
count++;
 6407                         }
 6408                         if ((count & 0x01) == 0)
instr.format1.parity = 1;
 6410                 } else {
 6411                         /* Compress the instruction for older sequencers */
 6412                         if (fmt3_ins != NULL) {
instr.integer =
fmt3_ins->immediate
 6415                                       | (fmt3_ins->source << 8)
 6416                                       | (fmt3_ins->address << 16)
 6417                                       | (fmt3_ins->opcode << 25);
 6418                         } else {
instr.integer =
fmt1_ins->immediate
 6421                                       | (fmt1_ins->source << 8)
 6422                                       | (fmt1_ins->destination << 16)
 6423                                       | (fmt1_ins->ret << 24)
 6424                                       | (fmt1_ins->opcode << 25);
 6425                         }
 6426                 }
 6427                 /* The sequencer is a little endian cpu */
instr.integer = aic_htole32(instr.integer);
ahc_outsb(ahc, SEQRAM, instr.bytes, 4);
 6430                 break;
 6431         default:
panic("Unknown opcode encountered in seq program");
 6433                 break;
 6434         }
 6435 }
 6437 #ifndef SMALL_KERNEL
 6438 int
ahc_print_register(ahc_reg_parse_entry_t *table, u_int num_entries,
 6440                    const char *name, u_int address, u_int value,
u_int *cur_column, u_int wrap_point)
 6442 {
u_int printed_mask;
 6444         int entry, printed;
 6446         if (cur_column != NULL && *cur_column >= wrap_point) {
printf("\n");
 6448                 *cur_column = 0;
 6449         }
printed = printf("%s[0x%x]", name, value);
 6451         if (table == NULL) {
printed += printf(" ");
 6453                 if (cur_column != NULL)
 6454                         *cur_column += printed;
 6455                 return (printed);
 6456         }
printed_mask = 0;
 6459         while (printed_mask != 0xFF) {
 6460                 for (entry = 0; entry < num_entries; entry++) {
 6461                         if (((value & table[entry].mask) != table[entry].value)
 6462                             || ((printed_mask & table[entry].mask) ==
table[entry].mask))
 6464                                 continue;
printed += printf("%s%s",
printed_mask == 0 ? ":(" : "|",
table[entry].name);
printed_mask |= table[entry].mask;
 6471                         break;
 6472                 }
 6473                 if (entry >= num_entries)
 6474                         break;
 6475         }
printed += printf("%s", printed_mask == 0 ? " " : ") ");
 6478         if (cur_column != NULL)
 6479                 *cur_column += printed;
 6481         return (printed);
 6482 }
 6483 #endif
 6485 void
ahc_dump_card_state(struct ahc_softc *ahc)
 6487 {
 6488 #ifndef SMALL_KERNEL
 6489         struct  scb *scb;
 6490         struct  scb_tailq *untagged_q;
u_int   cur_col;
 6492         int     paused;
 6493         int     target;
 6494         int     maxtarget;
 6495         int     i;
uint8_t last_phase;
uint8_t qinpos;
uint8_t qintail;
uint8_t qoutpos;
uint8_t scb_index;
uint8_t saved_scbptr;
 6503         if (ahc_is_paused(ahc)) {
paused = 1;
 6505         } else {
paused = 0;
ahc_pause(ahc);
 6508         }
saved_scbptr = ahc_inb(ahc, SCBPTR);
last_phase = ahc_inb(ahc, LASTPHASE);
printf("================== Dump Card State Begins =================\n"
 6513                "%s: Dumping Card State %s, at SEQADDR 0x%x\n",
ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg,
ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
 6516         if (paused)
printf("Card was paused\n");
printf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n",
ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX),
ahc_inb(ahc, ARG_2));
printf("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT),
ahc_inb(ahc, SCBPTR));
cur_col = 0;
 6524         if ((ahc->features & AHC_DT) != 0)
ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50);
ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50);
ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50);
ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50);
ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50);
ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50);
ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50);
ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50);
ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50);
ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50);
ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50);
ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50);
ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50);
ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50);
ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50);
ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50);
ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50);
ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50);
ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50);
 6544         if (cur_col != 0)
printf("\n");
printf("STACK:");
 6547         for (i = 0; i < STACK_SIZE; i++)
printf(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8));
printf("\nSCB count = %d\n", ahc->scb_data->numscbs);
printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag);
printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB));
 6552         /* QINFIFO */
printf("QINFIFO entries: ");
 6554         if ((ahc->features & AHC_QUEUE_REGS) != 0) {
qinpos = ahc_inb(ahc, SNSCB_QOFF);
ahc_outb(ahc, SNSCB_QOFF, qinpos);
 6557         } else
qinpos = ahc_inb(ahc, QINPOS);
qintail = ahc->qinfifonext;
 6560         while (qinpos != qintail) {
printf("%d ", ahc->qinfifo[qinpos]);
qinpos++;
 6563         }
printf("\n");
printf("Waiting Queue entries: ");
scb_index = ahc_inb(ahc, WAITING_SCBH);
i = 0;
 6569         while (scb_index != SCB_LIST_NULL && i++ < 256) {
ahc_outb(ahc, SCBPTR, scb_index);
printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
scb_index = ahc_inb(ahc, SCB_NEXT);
 6573         }
printf("\n");
printf("Disconnected Queue entries: ");
scb_index = ahc_inb(ahc, DISCONNECTED_SCBH);
i = 0;
 6579         while (scb_index != SCB_LIST_NULL && i++ < 256) {
ahc_outb(ahc, SCBPTR, scb_index);
printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
scb_index = ahc_inb(ahc, SCB_NEXT);
 6583         }
printf("\n");
ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
printf("QOUTFIFO entries: ");
qoutpos = ahc->qoutfifonext;
i = 0;
 6590         while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) {
printf("%d ", ahc->qoutfifo[qoutpos]);
qoutpos++;
 6593         }
printf("\n");
printf("Sequencer Free SCB List: ");
scb_index = ahc_inb(ahc, FREE_SCBH);
i = 0;
 6599         while (scb_index != SCB_LIST_NULL && i++ < 256) {
ahc_outb(ahc, SCBPTR, scb_index);
printf("%d ", scb_index);
scb_index = ahc_inb(ahc, SCB_NEXT);
 6603         }
printf("\n");
printf("Sequencer SCB Info: ");
 6607         for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
ahc_outb(ahc, SCBPTR, i);
 6609                 /*cur_col =*/ printf("\n%3d ", i);
ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60);
ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60);
ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60);
ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
 6615         }
printf("\n");
printf("Pending list: ");
i = 0;
LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
 6621                 if (i++ > 256)
 6622                         break;
 6623                 /*cur_col =*/ printf("\n%3d ", scb->hscb->tag);
ahc_scb_control_print(scb->hscb->control, &cur_col, 60);
ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60);
ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60);
 6627                 if ((ahc->flags & AHC_PAGESCBS) == 0) {
ahc_outb(ahc, SCBPTR, scb->hscb->tag);
printf("(");
ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL),
 6631                                               &cur_col, 60);
ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
printf(")");
 6634                 }
 6635         }
printf("\n");
printf("Kernel Free SCB list: ");
i = 0;
SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) {
 6641                 if (i++ > 256)
 6642                         break;
printf("%d ", scb->hscb->tag);
 6644         }
printf("\n");
maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7;
 6648         for (target = 0; target <= maxtarget; target++) {
untagged_q = &ahc->untagged_queues[target];
 6650                 if (TAILQ_FIRST(untagged_q) == NULL)
 6651                         continue;
printf("Untagged Q(%d): ", target);
i = 0;
TAILQ_FOREACH(scb, untagged_q, links.tqe) {
 6655                         if (i++ > 256)
 6656                                 break;
printf("%d ", scb->hscb->tag);
 6658                 }
printf("\n");
 6660         }
ahc_platform_dump_card_state(ahc);
printf("\n================= Dump Card State Ends ==================\n");
ahc_outb(ahc, SCBPTR, saved_scbptr);
 6665         if (paused == 0)
ahc_unpause(ahc);
 6667 #endif
 6668 }
 6670 /************************* Target Mode ****************************************/
 6671 #ifdef AHC_TARGET_MODE
cam_status
ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb,
 6674                     struct ahc_tmode_tstate **tstate,
 6675                     struct ahc_tmode_lstate **lstate,
 6676                     int notfound_failure)
 6677 {
 6679         if ((ahc->features & AHC_TARGETMODE) == 0)
 6680                 return (CAM_REQ_INVALID);
 6682         /*
 6683          * Handle the 'black hole' device that sucks up
 6684          * requests to unattached luns on enabled targets.
 6685          */
 6686         if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD
 6687          && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) {
 6688                 *tstate = NULL;
 6689                 *lstate = ahc->black_hole;
 6690         } else {
u_int max_id;
max_id = (ahc->features & AHC_WIDE) ? 15 : 7;
 6694                 if (ccb->ccb_h.target_id > max_id)
 6695                         return (CAM_TID_INVALID);
 6697                 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS)
 6698                         return (CAM_LUN_INVALID);
 6700                 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id];
 6701                 *lstate = NULL;
 6702                 if (*tstate != NULL)
 6703                         *lstate =
 6704                             (*tstate)->enabled_luns[ccb->ccb_h.target_lun];
 6705         }
 6707         if (notfound_failure != 0 && *lstate == NULL)
 6708                 return (CAM_PATH_INVALID);
 6710         return (CAM_REQ_CMP);
 6711 }
 6713 void
ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb)
 6715 {
 6716         struct     ahc_tmode_tstate *tstate;
 6717         struct     ahc_tmode_lstate *lstate;
 6718         struct     ccb_en_lun *cel;
cam_status status;
u_long     s;
u_int      target;
u_int      lun;
u_int      target_mask;
u_int      our_id;
 6725         int        error;
 6726         char       channel;
status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate,
 6729                                      /*notfound_failure*/FALSE);
 6731         if (status != CAM_REQ_CMP) {
ccb->ccb_h.status = status;
 6733                 return;
 6734         }
 6736         if (cam_sim_bus(sim) == 0)
our_id = ahc->our_id;
 6738         else
our_id = ahc->our_id_b;
 6741         if (ccb->ccb_h.target_id != our_id) {
 6742                 /*
 6743                  * our_id represents our initiator ID, or
 6744                  * the ID of the first target to have an
 6745                  * enabled lun in target mode.  There are
 6746                  * two cases that may preclude enabling a
 6747                  * target id other than our_id.
 6748                  *
 6749                  *   o our_id is for an active initiator role.
 6750                  *     Since the hardware does not support
 6751                  *     reselections to the initiator role at
 6752                  *     anything other than our_id, and our_id
 6753                  *     is used by the hardware to indicate the
 6754                  *     ID to use for both select-out and
 6755                  *     reselect-out operations, the only target
 6756                  *     ID we can support in this mode is our_id.
 6757                  *
 6758                  *   o The MULTARGID feature is not available and
 6759                  *     a previous target mode ID has been enabled.
 6760                  */
 6761                 if ((ahc->features & AHC_MULTIROLE) != 0) {
 6763                         if ((ahc->features & AHC_MULTI_TID) != 0
 6764                          && (ahc->flags & AHC_INITIATORROLE) != 0) {
 6765                                 /*
 6766                                  * Only allow additional targets if
 6767                                  * the initiator role is disabled.
 6768                                  * The hardware cannot handle a re-select-in
 6769                                  * on the initiator id during a re-select-out
 6770                                  * on a different target id.
 6771                                  */
status = CAM_TID_INVALID;
 6773                         } else if ((ahc->flags & AHC_INITIATORROLE) != 0
 6774                                 || ahc->enabled_luns > 0) {
 6775                                 /*
 6776                                  * Only allow our target id to change
 6777                                  * if the initiator role is not configured
 6778                                  * and there are no enabled luns which
 6779                                  * are attached to the currently registered
 6780                                  * scsi id.
 6781                                  */
status = CAM_TID_INVALID;
 6783                         }
 6784                 } else if ((ahc->features & AHC_MULTI_TID) == 0
 6785                         && ahc->enabled_luns > 0) {
status = CAM_TID_INVALID;
 6788                 }
 6789         }
 6791         if (status != CAM_REQ_CMP) {
ccb->ccb_h.status = status;
 6793                 return;
 6794         }
 6796         /*
 6797          * We now have an id that is valid.
 6798          * If we aren't in target mode, switch modes.
 6799          */
 6800         if ((ahc->flags & AHC_TARGETROLE) == 0
 6801          && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
u_long   s;
ahc_flag saved_flags;
printf("Configuring Target Mode\n");
s = splbio();
 6807                 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
ccb->ccb_h.status = CAM_BUSY;
splx(s);
 6810                         return;
 6811                 }
saved_flags = ahc->flags;
ahc->flags |= AHC_TARGETROLE;
 6814                 if ((ahc->features & AHC_MULTIROLE) == 0)
ahc->flags &= ~AHC_INITIATORROLE;
ahc_pause(ahc);
error = ahc_loadseq(ahc);
 6818                 if (error != 0) {
 6819                         /*
 6820                          * Restore original configuration and notify
 6821                          * the caller that we cannot support target mode.
 6822                          * Since the adapter started out in this
 6823                          * configuration, the firmware load will succeed,
 6824                          * so there is no point in checking ahc_loadseq's
 6825                          * return value.
 6826                          */
ahc->flags = saved_flags;
 6828                         (void)ahc_loadseq(ahc);
ahc_restart(ahc);
splx(s);
ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
 6832                         return;
 6833                 }
ahc_restart(ahc);
splx(s);
 6836         }
cel = &ccb->cel;
target = ccb->ccb_h.target_id;
lun = ccb->ccb_h.target_lun;
channel = SIM_CHANNEL(ahc, sim);
target_mask = 0x01 << target;
 6842         if (channel == 'B')
target_mask <<= 8;
 6845         if (cel->enable != 0) {
u_int scsiseq;
 6848                 /* Are we already enabled?? */
 6849                 if (lstate != NULL) {
xpt_print_path(ccb->ccb_h.path);
printf("Lun already enabled\n");
ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
 6853                         return;
 6854                 }
 6856                 if (cel->grp6_len != 0
 6857                  || cel->grp7_len != 0) {
 6858                         /*
 6859                          * Don't (yet?) support vendor
 6860                          * specific commands.
 6861                          */
ccb->ccb_h.status = CAM_REQ_INVALID;
printf("Non-zero Group Codes\n");
 6864                         return;
 6865                 }
 6867                 /*
 6868                  * Seems to be okay.
 6869                  * Setup our data structures.
 6870                  */
 6871                 if (target != CAM_TARGET_WILDCARD && tstate == NULL) {
tstate = ahc_alloc_tstate(ahc, target, channel);
 6873                         if (tstate == NULL) {
xpt_print_path(ccb->ccb_h.path);
printf("Couldn't allocate tstate\n");
ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
 6877                                 return;
 6878                         }
 6879                 }
lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT);
 6881                 if (lstate == NULL) {
xpt_print_path(ccb->ccb_h.path);
printf("Couldn't allocate lstate\n");
ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
 6885                         return;
 6886                 }
memset(lstate, 0, sizeof(*lstate));
status = xpt_create_path(&lstate->path, /*periph*/NULL,
xpt_path_path_id(ccb->ccb_h.path),
xpt_path_target_id(ccb->ccb_h.path),
xpt_path_lun_id(ccb->ccb_h.path));
 6892                 if (status != CAM_REQ_CMP) {
free(lstate, M_DEVBUF);
xpt_print_path(ccb->ccb_h.path);
printf("Couldn't allocate path\n");
ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
 6897                         return;
 6898                 }
SLIST_INIT(&lstate->accept_tios);
SLIST_INIT(&lstate->immed_notifies);
s = splbio();
ahc_pause(ahc);
 6903                 if (target != CAM_TARGET_WILDCARD) {
tstate->enabled_luns[lun] = lstate;
ahc->enabled_luns++;
 6907                         if ((ahc->features & AHC_MULTI_TID) != 0) {
u_int targid_mask;
targid_mask = ahc_inb(ahc, TARGID)
 6911                                             | (ahc_inb(ahc, TARGID + 1) << 8);
targid_mask |= target_mask;
ahc_outb(ahc, TARGID, targid_mask);
ahc_outb(ahc, TARGID+1, (targid_mask >> 8));
ahc_update_scsiid(ahc, targid_mask);
 6918                         } else {
u_int our_id;
 6920                                 char  channel;
channel = SIM_CHANNEL(ahc, sim);
our_id = SIM_SCSI_ID(ahc, sim);
 6925                                 /*
 6926                                  * This can only happen if selections
 6927                                  * are not enabled
 6928                                  */
 6929                                 if (target != our_id) {
u_int sblkctl;
 6931                                         char  cur_channel;
 6932                                         int   swap;
sblkctl = ahc_inb(ahc, SBLKCTL);
cur_channel = (sblkctl & SELBUSB)
 6936                                                     ? 'B' : 'A';
 6937                                         if ((ahc->features & AHC_TWIN) == 0)
cur_channel = 'A';
swap = cur_channel != channel;
 6940                                         if (channel == 'A')
ahc->our_id = target;
 6942                                         else
ahc->our_id_b = target;
 6945                                         if (swap)
ahc_outb(ahc, SBLKCTL,
sblkctl ^ SELBUSB);
ahc_outb(ahc, SCSIID, target);
 6951                                         if (swap)
ahc_outb(ahc, SBLKCTL, sblkctl);
 6953                                 }
 6954                         }
 6955                 } else
ahc->black_hole = lstate;
 6957                 /* Allow select-in operations */
 6958                 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) {
scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
scsiseq |= ENSELI;
ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
scsiseq = ahc_inb(ahc, SCSISEQ);
scsiseq |= ENSELI;
ahc_outb(ahc, SCSISEQ, scsiseq);
 6965                 }
ahc_unpause(ahc);
splx(s);
ccb->ccb_h.status = CAM_REQ_CMP;
xpt_print_path(ccb->ccb_h.path);
printf("Lun now enabled for target mode\n");
 6971         } else {
 6972                 struct scb *scb;
 6973                 int i, empty;
 6975                 if (lstate == NULL) {
ccb->ccb_h.status = CAM_LUN_INVALID;
 6977                         return;
 6978                 }
s = splbio();
ccb->ccb_h.status = CAM_REQ_CMP;
LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
 6984                         struct ccb_hdr *ccbh;
ccbh = &scb->io_ctx->ccb_h;
 6987                         if (ccbh->func_code == XPT_CONT_TARGET_IO
 6988                          && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){
printf("CTIO pending\n");
ccb->ccb_h.status = CAM_REQ_INVALID;
splx(s);
 6992                                 return;
 6993                         }
 6994                 }
 6996                 if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
printf("ATIOs pending\n");
ccb->ccb_h.status = CAM_REQ_INVALID;
 6999                 }
 7001                 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
printf("INOTs pending\n");
ccb->ccb_h.status = CAM_REQ_INVALID;
 7004                 }
 7006                 if (ccb->ccb_h.status != CAM_REQ_CMP) {
splx(s);
 7008                         return;
 7009                 }
xpt_print_path(ccb->ccb_h.path);
printf("Target mode disabled\n");
xpt_free_path(lstate->path);
free(lstate, M_DEVBUF);
ahc_pause(ahc);
 7017                 /* Can we clean up the target too? */
 7018                 if (target != CAM_TARGET_WILDCARD) {
tstate->enabled_luns[lun] = NULL;
ahc->enabled_luns--;
 7021                         for (empty = 1, i = 0; i < 8; i++)
 7022                                 if (tstate->enabled_luns[i] != NULL) {
empty = 0;
 7024                                         break;
 7025                                 }
 7027                         if (empty) {
ahc_free_tstate(ahc, target, channel,
 7029                                                 /*force*/FALSE);
 7030                                 if (ahc->features & AHC_MULTI_TID) {
u_int targid_mask;
targid_mask = ahc_inb(ahc, TARGID)
 7034                                                     | (ahc_inb(ahc, TARGID + 1)
 7035                                                        << 8);
targid_mask &= ~target_mask;
ahc_outb(ahc, TARGID, targid_mask);
ahc_outb(ahc, TARGID+1,
 7040                                                  (targid_mask >> 8));
ahc_update_scsiid(ahc, targid_mask);
 7042                                 }
 7043                         }
 7044                 } else {
ahc->black_hole = NULL;
 7048                         /*
 7049                          * We can't allow selections without
 7050                          * our black hole device.
 7051                          */
empty = TRUE;
 7053                 }
 7054                 if (ahc->enabled_luns == 0) {
 7055                         /* Disallow select-in */
u_int scsiseq;
scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
scsiseq &= ~ENSELI;
ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
scsiseq = ahc_inb(ahc, SCSISEQ);
scsiseq &= ~ENSELI;
ahc_outb(ahc, SCSISEQ, scsiseq);
 7065                         if ((ahc->features & AHC_MULTIROLE) == 0) {
printf("Configuring Initiator Mode\n");
ahc->flags &= ~AHC_TARGETROLE;
ahc->flags |= AHC_INITIATORROLE;
 7069                                 /*
 7070                                  * Returning to a configuration that
 7071                                  * fit previously will always succeed.
 7072                                  */
 7073                                 (void)ahc_loadseq(ahc);
ahc_restart(ahc);
 7075                                 /*
 7076                                  * Unpaused.  The extra unpause
 7077                                  * that follows is harmless.
 7078                                  */
 7079                         }
 7080                 }
ahc_unpause(ahc);
splx(s);
 7083         }
 7084 }
 7086 static void
ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask)
 7088 {
u_int scsiid_mask;
u_int scsiid;
 7092         if ((ahc->features & AHC_MULTI_TID) == 0)
panic("ahc_update_scsiid called on non-multitid unit");
 7095         /*
 7096          * Since we will rely on the TARGID mask
 7097          * for selection enables, ensure that OID
 7098          * in SCSIID is not set to some other ID
 7099          * that we don't want to allow selections on.
 7100          */
 7101         if ((ahc->features & AHC_ULTRA2) != 0)
scsiid = ahc_inb(ahc, SCSIID_ULTRA2);
 7103         else
scsiid = ahc_inb(ahc, SCSIID);
scsiid_mask = 0x1 << (scsiid & OID);
 7106         if ((targid_mask & scsiid_mask) == 0) {
u_int our_id;
 7109                 /* ffs counts from 1 */
our_id = ffs(targid_mask);
 7111                 if (our_id == 0)
our_id = ahc->our_id;
 7113                 else
our_id--;
scsiid &= TID;
scsiid |= our_id;
 7117         }
 7118         if ((ahc->features & AHC_ULTRA2) != 0)
ahc_outb(ahc, SCSIID_ULTRA2, scsiid);
 7120         else
ahc_outb(ahc, SCSIID, scsiid);
 7122 }
 7124 #ifdef AHC_TARGET_MODE
 7125 void
ahc_run_tqinfifo(struct ahc_softc *ahc, int paused)
 7127 {
 7128         struct target_cmd *cmd;
 7130         /*
 7131          * If the card supports auto-access pause,
 7132          * we can access the card directly regardless
 7133          * of whether it is paused or not.
 7134          */
 7135         if ((ahc->features & AHC_AUTOPAUSE) != 0)
paused = TRUE;
ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD);
 7139         while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) {
 7141                 /*
 7142                  * Only advance through the queue if we
 7143                  * have the resources to process the command.
 7144                  */
 7145                 if (ahc_handle_target_cmd(ahc, cmd) != 0)
 7146                         break;
cmd->cmd_valid = 0;
ahc_dmamap_sync(ahc, ahc->parent_dmat/*shared_data_dmat*/,
ahc->shared_data_dmamap,
ahc_targetcmd_offset(ahc, ahc->tqinfifonext),
 7152                                 sizeof(struct target_cmd),
 7153 #ifdef __sgi__
BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
 7155 #else
BUS_DMASYNC_PREREAD);
 7157 #endif
ahc->tqinfifonext++;
 7160                 /*
 7161                  * Lazily update our position in the target mode incoming
 7162                  * command queue as seen by the sequencer.
 7163                  */
 7164                 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
 7165                         if ((ahc->features & AHC_HS_MAILBOX) != 0) {
u_int hs_mailbox;
hs_mailbox = ahc_inb(ahc, HS_MAILBOX);
hs_mailbox &= ~HOST_TQINPOS;
hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS;
ahc_outb(ahc, HS_MAILBOX, hs_mailbox);
 7172                         } else {
 7173                                 if (!paused)
ahc_pause(ahc); 
ahc_outb(ahc, KERNEL_TQINPOS,
ahc->tqinfifonext & HOST_TQINPOS);
 7177                                 if (!paused)
ahc_unpause(ahc);
 7179                         }
 7180                 }
 7181         }
 7182 }
 7183 #endif
 7185 static int
ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd)
 7187 {
 7188         struct    ahc_tmode_tstate *tstate;
 7189         struct    ahc_tmode_lstate *lstate;
 7190         struct    ccb_accept_tio *atio;
uint8_t *byte;
 7192         int       initiator;
 7193         int       target;
 7194         int       lun;
initiator = SCSIID_TARGET(ahc, cmd->scsiid);
target = SCSIID_OUR_ID(cmd->scsiid);
lun    = (cmd->identify & MSG_IDENTIFY_LUNMASK);
byte = cmd->bytes;
tstate = ahc->enabled_targets[target];
lstate = NULL;
 7203         if (tstate != NULL)
lstate = tstate->enabled_luns[lun];
 7206         /*
 7207          * Commands for disabled luns go to the black hole driver.
 7208          */
 7209         if (lstate == NULL)
lstate = ahc->black_hole;
atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios);
 7213         if (atio == NULL) {
ahc->flags |= AHC_TQINFIFO_BLOCKED;
 7215                 /*
 7216                  * Wait for more ATIOs from the peripheral driver for this lun.
 7217                  */
 7218                 if (bootverbose)
printf("%s: ATIOs exhausted\n", ahc_name(ahc));
 7220                 return (1);
 7221         } else
ahc->flags &= ~AHC_TQINFIFO_BLOCKED;
 7223 #if 0
printf("Incoming command from %d for %d:%d%s\n",
initiator, target, lun,
lstate == ahc->black_hole ? "(Black Holed)" : "");
 7227 #endif
SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle);
 7230         if (lstate == ahc->black_hole) {
 7231                 /* Fill in the wildcards */
atio->ccb_h.target_id = target;
atio->ccb_h.target_lun = lun;
 7234         }
 7236         /*
 7237          * Package it up and send it off to
 7238          * whomever has this lun enabled.
 7239          */
atio->sense_len = 0;
atio->init_id = initiator;
 7242         if (byte[0] != 0xFF) {
 7243                 /* Tag was included */
atio->tag_action = *byte++;
atio->tag_id = *byte++;
atio->ccb_h.flags = CAM_TAG_ACTION_VALID;
 7247         } else {
atio->ccb_h.flags = 0;
 7249         }
byte++;
 7252         /* Okay.  Now determine the cdb size based on the command code */
 7253         switch (*byte >> CMD_GROUP_CODE_SHIFT) {
 7254         case 0:
atio->cdb_len = 6;
 7256                 break;
 7257         case 1:
 7258         case 2:
atio->cdb_len = 10;
 7260                 break;
 7261         case 4:
atio->cdb_len = 16;
 7263                 break;
 7264         case 5:
atio->cdb_len = 12;
 7266                 break;
 7267         case 3:
 7268         default:
 7269                 /* Only copy the opcode. */
atio->cdb_len = 1;
printf("Reserved or VU command code type encountered\n");
 7272                 break;
 7273         }
memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len);
atio->ccb_h.status |= CAM_CDB_RECVD;
 7279         if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) {
 7280                 /*
 7281                  * We weren't allowed to disconnect.
 7282                  * We're hanging on the bus until a
 7283                  * continue target I/O comes in response
 7284                  * to this accept tio.
 7285                  */
 7286 #if 0
printf("Received Immediate Command %d:%d:%d - %p\n",
initiator, target, lun, ahc->pending_device);
 7289 #endif
ahc->pending_device = lstate;
ahc_freeze_ccb((union ccb *)atio);
atio->ccb_h.flags |= CAM_DIS_DISCONNECT;
 7293         }
xpt_done((union ccb*)atio);
 7295         return (0);
 7296 }
 7297 #endif
 7299 static int
ahc_createdmamem(bus_dma_tag_t tag, int size, int flags, bus_dmamap_t *mapp,
caddr_t *vaddr, bus_addr_t *baddr, bus_dma_segment_t *seg, int *nseg,
 7302     const char *myname, const char *what)
 7303 {
 7304         int error;
 7306         if ((error = bus_dmamap_create(tag, size, 1, size, 0,
BUS_DMA_NOWAIT | flags, mapp)) != 0) {
printf("%s: failed to create DMA map for %s, error = %d\n",
myname, what, error);
 7310                 return (error);
 7311         }
 7313         if ((error = bus_dmamem_alloc(tag, size, PAGE_SIZE, 0,
seg, 1, nseg, BUS_DMA_NOWAIT)) != 0) {
printf("%s: failed to allocate DMA mem for %s, error = %d\n",
myname, what, error);
 7317                 goto destroy;
 7318         }
 7320         if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr,
BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
printf("%s: failed to map DMA mem for %s, error = %d\n",
myname, what, error);
 7324                 goto free;
 7325         }
 7327         if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL,
BUS_DMA_NOWAIT)) != 0) {
printf("%s: failed to load DMA map for %s, error = %d\n",
myname, what, error);
 7331                 goto unmap;
 7332         }
 7334         *baddr = (*mapp)->dm_segs[0].ds_addr;
 7335         return (0);
unmap:
bus_dmamem_unmap(tag, *vaddr, size);
free:
bus_dmamem_free(tag, seg, *nseg);
destroy:
bus_dmamap_destroy(tag, *mapp);
 7344         *vaddr = 0;
bzero(seg, sizeof(*seg));
 7346         return (error);
 7347 }
 7349 static void
ahc_freedmamem(bus_dma_tag_t tag, int size, bus_dmamap_t map, caddr_t vaddr,
bus_dma_segment_t *seg, int nseg)
 7352 {
bus_dmamap_unload(tag, map);
bus_dmamem_unmap(tag, vaddr, size);
bus_dmamem_free(tag, seg, nseg);
bus_dmamap_destroy(tag, map);
 7358 }